diff options
author | Vipul Kumar Samar <vipulkumar.samar@st.com> | 2012-07-10 07:42:45 -0400 |
---|---|---|
committer | Shiraz Hashim <shiraz.hashim@st.com> | 2012-07-18 00:34:39 -0400 |
commit | 5cfc545f50c4b6c0800e578b51019f2ecf490f1e (patch) | |
tree | 1bfcd4ffaaee3222c0b3230cb66d80c995a71ab8 /drivers | |
parent | e28f1aa110c919716188b979c4404e4c8e9794b9 (diff) |
Clk:spear3xx:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk
ids are exceeding this predefined limit.
This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
ras_pll3_48m -> ras_pll3_
pll3_48m -> pll3_
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/spear/spear3xx_clock.c | 180 |
1 files changed, 86 insertions, 94 deletions
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index 01dd6daff2a1..c3157454bb3f 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c | |||
@@ -122,12 +122,12 @@ static struct gpt_rate_tbl gpt_rtbl[] = { | |||
122 | }; | 122 | }; |
123 | 123 | ||
124 | /* clock parents */ | 124 | /* clock parents */ |
125 | static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; | 125 | static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", }; |
126 | static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", | 126 | static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", |
127 | }; | 127 | }; |
128 | static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", }; | 128 | static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", }; |
129 | static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", }; | 129 | static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", }; |
130 | static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; | 130 | static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; |
131 | static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; | 131 | static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; |
132 | static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", | 132 | static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", |
133 | "pll2_clk", }; | 133 | "pll2_clk", }; |
@@ -137,7 +137,7 @@ static void __init spear300_clk_init(void) | |||
137 | { | 137 | { |
138 | struct clk *clk; | 138 | struct clk *clk; |
139 | 139 | ||
140 | clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0, | 140 | clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, |
141 | 1, 1); | 141 | 1, 1); |
142 | clk_register_clkdev(clk, NULL, "60000000.clcd"); | 142 | clk_register_clkdev(clk, NULL, "60000000.clcd"); |
143 | 143 | ||
@@ -219,15 +219,11 @@ static void __init spear310_clk_init(void) | |||
219 | #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 | 219 | #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 |
220 | #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 | 220 | #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 |
221 | 221 | ||
222 | static const char *i2s_ref_parents[] = { "ras_pll2_clk", | 222 | static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", }; |
223 | "ras_gen2_synth_gate_clk", }; | 223 | static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", }; |
224 | static const char *sdhci_parents[] = { "ras_pll3_48m_clk", | ||
225 | "ras_gen3_synth_gate_clk", | ||
226 | }; | ||
227 | static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", | 224 | static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", |
228 | "ras_gen0_synth_gate_clk", }; | 225 | "ras_syn0_gclk", }; |
229 | static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk", | 226 | static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; |
230 | }; | ||
231 | 227 | ||
232 | static void __init spear320_clk_init(void) | 228 | static void __init spear320_clk_init(void) |
233 | { | 229 | { |
@@ -237,7 +233,7 @@ static void __init spear320_clk_init(void) | |||
237 | CLK_IS_ROOT, 125000000); | 233 | CLK_IS_ROOT, 125000000); |
238 | clk_register_clkdev(clk, "smii_125m_pad", NULL); | 234 | clk_register_clkdev(clk, "smii_125m_pad", NULL); |
239 | 235 | ||
240 | clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0, | 236 | clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, |
241 | 1, 1); | 237 | 1, 1); |
242 | clk_register_clkdev(clk, NULL, "90000000.clcd"); | 238 | clk_register_clkdev(clk, NULL, "90000000.clcd"); |
243 | 239 | ||
@@ -363,9 +359,9 @@ void __init spear3xx_clk_init(void) | |||
363 | clk_register_clkdev(clk, NULL, "fc900000.rtc"); | 359 | clk_register_clkdev(clk, NULL, "fc900000.rtc"); |
364 | 360 | ||
365 | /* clock derived from 24 MHz osc clk */ | 361 | /* clock derived from 24 MHz osc clk */ |
366 | clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, | 362 | clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, |
367 | 48000000); | 363 | 48000000); |
368 | clk_register_clkdev(clk, "pll3_48m_clk", NULL); | 364 | clk_register_clkdev(clk, "pll3_clk", NULL); |
369 | 365 | ||
370 | clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, | 366 | clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, |
371 | 1); | 367 | 1); |
@@ -392,98 +388,98 @@ void __init spear3xx_clk_init(void) | |||
392 | HCLK_RATIO_MASK, 0, &_lock); | 388 | HCLK_RATIO_MASK, 0, &_lock); |
393 | clk_register_clkdev(clk, "ahb_clk", NULL); | 389 | clk_register_clkdev(clk, "ahb_clk", NULL); |
394 | 390 | ||
395 | clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", | 391 | clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, |
396 | "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, | 392 | UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
397 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 393 | &_lock, &clk1); |
398 | clk_register_clkdev(clk, "uart_synth_clk", NULL); | 394 | clk_register_clkdev(clk, "uart_syn_clk", NULL); |
399 | clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); | 395 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); |
400 | 396 | ||
401 | clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents, | 397 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, |
402 | ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, | 398 | ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, |
403 | UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); | 399 | UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); |
404 | clk_register_clkdev(clk, "uart0_mux_clk", NULL); | 400 | clk_register_clkdev(clk, "uart0_mclk", NULL); |
405 | 401 | ||
406 | clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0, | 402 | clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB, |
407 | PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock); | 403 | UART_CLK_ENB, 0, &_lock); |
408 | clk_register_clkdev(clk, NULL, "d0000000.serial"); | 404 | clk_register_clkdev(clk, NULL, "d0000000.serial"); |
409 | 405 | ||
410 | clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", | 406 | clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, |
411 | "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, | 407 | FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
412 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 408 | &_lock, &clk1); |
413 | clk_register_clkdev(clk, "firda_synth_clk", NULL); | 409 | clk_register_clkdev(clk, "firda_syn_clk", NULL); |
414 | clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); | 410 | clk_register_clkdev(clk1, "firda_syn_gclk", NULL); |
415 | 411 | ||
416 | clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, | 412 | clk = clk_register_mux(NULL, "firda_mclk", firda_parents, |
417 | ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, | 413 | ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, |
418 | FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); | 414 | FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); |
419 | clk_register_clkdev(clk, "firda_mux_clk", NULL); | 415 | clk_register_clkdev(clk, "firda_mclk", NULL); |
420 | 416 | ||
421 | clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, | 417 | clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, |
422 | PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); | 418 | PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); |
423 | clk_register_clkdev(clk, NULL, "firda"); | 419 | clk_register_clkdev(clk, NULL, "firda"); |
424 | 420 | ||
425 | /* gpt clocks */ | 421 | /* gpt clocks */ |
426 | clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, | 422 | clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, |
427 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); | 423 | ARRAY_SIZE(gpt_rtbl), &_lock); |
428 | clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, | 424 | clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, |
429 | ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, | 425 | ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, |
430 | GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 426 | GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
431 | clk_register_clkdev(clk, NULL, "gpt0"); | 427 | clk_register_clkdev(clk, NULL, "gpt0"); |
432 | 428 | ||
433 | clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, | 429 | clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, |
434 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); | 430 | ARRAY_SIZE(gpt_rtbl), &_lock); |
435 | clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents, | 431 | clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, |
436 | ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, | 432 | ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, |
437 | GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 433 | GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
438 | clk_register_clkdev(clk, "gpt1_mux_clk", NULL); | 434 | clk_register_clkdev(clk, "gpt1_mclk", NULL); |
439 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, | 435 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, |
440 | PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); | 436 | PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); |
441 | clk_register_clkdev(clk, NULL, "gpt1"); | 437 | clk_register_clkdev(clk, NULL, "gpt1"); |
442 | 438 | ||
443 | clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, | 439 | clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, |
444 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); | 440 | ARRAY_SIZE(gpt_rtbl), &_lock); |
445 | clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, | 441 | clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, |
446 | ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, | 442 | ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, |
447 | GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 443 | GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
448 | clk_register_clkdev(clk, "gpt2_mux_clk", NULL); | 444 | clk_register_clkdev(clk, "gpt2_mclk", NULL); |
449 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, | 445 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, |
450 | PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); | 446 | PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); |
451 | clk_register_clkdev(clk, NULL, "gpt2"); | 447 | clk_register_clkdev(clk, NULL, "gpt2"); |
452 | 448 | ||
453 | /* general synths clocks */ | 449 | /* general synths clocks */ |
454 | clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk", | 450 | clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", |
455 | "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl, | 451 | 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
456 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 452 | &_lock, &clk1); |
457 | clk_register_clkdev(clk, "gen0_synth_clk", NULL); | 453 | clk_register_clkdev(clk, "gen0_syn_clk", NULL); |
458 | clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL); | 454 | clk_register_clkdev(clk1, "gen0_syn_gclk", NULL); |
459 | 455 | ||
460 | clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk", | 456 | clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", |
461 | "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl, | 457 | 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
462 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 458 | &_lock, &clk1); |
463 | clk_register_clkdev(clk, "gen1_synth_clk", NULL); | 459 | clk_register_clkdev(clk, "gen1_syn_clk", NULL); |
464 | clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL); | 460 | clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); |
465 | 461 | ||
466 | clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents, | 462 | clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, |
467 | ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG, | 463 | ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG, |
468 | GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, | 464 | GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, |
469 | &_lock); | 465 | &_lock); |
470 | clk_register_clkdev(clk, "gen2_3_parent_clk", NULL); | 466 | clk_register_clkdev(clk, "gen2_3_par_clk", NULL); |
471 | 467 | ||
472 | clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk", | 468 | clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", |
473 | "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, | 469 | "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, |
474 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 470 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); |
475 | clk_register_clkdev(clk, "gen2_synth_clk", NULL); | 471 | clk_register_clkdev(clk, "gen2_syn_clk", NULL); |
476 | clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL); | 472 | clk_register_clkdev(clk1, "gen2_syn_gclk", NULL); |
477 | 473 | ||
478 | clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk", | 474 | clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", |
479 | "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, | 475 | "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, |
480 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 476 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); |
481 | clk_register_clkdev(clk, "gen3_synth_clk", NULL); | 477 | clk_register_clkdev(clk, "gen3_syn_clk", NULL); |
482 | clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL); | 478 | clk_register_clkdev(clk1, "gen3_syn_gclk", NULL); |
483 | 479 | ||
484 | /* clock derived from pll3 clk */ | 480 | /* clock derived from pll3 clk */ |
485 | clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0, | 481 | clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, |
486 | PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock); | 482 | USBH_CLK_ENB, 0, &_lock); |
487 | clk_register_clkdev(clk, "usbh_clk", NULL); | 483 | clk_register_clkdev(clk, "usbh_clk", NULL); |
488 | 484 | ||
489 | clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, | 485 | clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, |
@@ -494,8 +490,8 @@ void __init spear3xx_clk_init(void) | |||
494 | 1); | 490 | 1); |
495 | clk_register_clkdev(clk, "usbh.1_clk", NULL); | 491 | clk_register_clkdev(clk, "usbh.1_clk", NULL); |
496 | 492 | ||
497 | clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, | 493 | clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, |
498 | PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); | 494 | USBD_CLK_ENB, 0, &_lock); |
499 | clk_register_clkdev(clk, NULL, "designware_udc"); | 495 | clk_register_clkdev(clk, NULL, "designware_udc"); |
500 | 496 | ||
501 | /* clock derived from ahb clk */ | 497 | /* clock derived from ahb clk */ |
@@ -579,29 +575,25 @@ void __init spear3xx_clk_init(void) | |||
579 | RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); | 575 | RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); |
580 | clk_register_clkdev(clk, "ras_pll2_clk", NULL); | 576 | clk_register_clkdev(clk, "ras_pll2_clk", NULL); |
581 | 577 | ||
582 | clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0, | 578 | clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, |
583 | RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); | 579 | RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); |
584 | clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL); | 580 | clk_register_clkdev(clk, "ras_pll3_clk", NULL); |
585 | 581 | ||
586 | clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk", | 582 | clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0, |
587 | "gen0_synth_gate_clk", 0, RAS_CLK_ENB, | 583 | RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock); |
588 | RAS_SYNT0_CLK_ENB, 0, &_lock); | 584 | clk_register_clkdev(clk, "ras_syn0_gclk", NULL); |
589 | clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL); | 585 | |
590 | 586 | clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0, | |
591 | clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk", | 587 | RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock); |
592 | "gen1_synth_gate_clk", 0, RAS_CLK_ENB, | 588 | clk_register_clkdev(clk, "ras_syn1_gclk", NULL); |
593 | RAS_SYNT1_CLK_ENB, 0, &_lock); | 589 | |
594 | clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL); | 590 | clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0, |
595 | 591 | RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock); | |
596 | clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk", | 592 | clk_register_clkdev(clk, "ras_syn2_gclk", NULL); |
597 | "gen2_synth_gate_clk", 0, RAS_CLK_ENB, | 593 | |
598 | RAS_SYNT2_CLK_ENB, 0, &_lock); | 594 | clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0, |
599 | clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL); | 595 | RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock); |
600 | 596 | clk_register_clkdev(clk, "ras_syn3_gclk", NULL); | |
601 | clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk", | ||
602 | "gen3_synth_gate_clk", 0, RAS_CLK_ENB, | ||
603 | RAS_SYNT3_CLK_ENB, 0, &_lock); | ||
604 | clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL); | ||
605 | 597 | ||
606 | if (of_machine_is_compatible("st,spear300")) | 598 | if (of_machine_is_compatible("st,spear300")) |
607 | spear300_clk_init(); | 599 | spear300_clk_init(); |