aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2012-05-16 06:08:43 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-07-01 09:15:45 -0400
commit409ec8db46dc60e5da7169b6bac6b294513d386a (patch)
tree8db0c43d5ca25147721ba11b7bc1c8c091e5d6be /drivers
parent95442b223405dae313e3e273765cc1c905d67717 (diff)
dmaengine: PL08x: move the bus and increment selection to dma prepare function
Move the bus and transfer increment selection to the DMA prepare function rather than the slave configuration function. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/dma/amba-pl08x.c26
1 files changed, 14 insertions, 12 deletions
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 7eb0e8ef6a57..bd51a44746be 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1258,13 +1258,9 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1258 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; 1258 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1259 1259
1260 if (plchan->runtime_direction == DMA_DEV_TO_MEM) { 1260 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
1261 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | 1261 plchan->src_cctl = pl08x_cctl(cctl);
1262 pl08x_select_bus(plchan->cd->periph_buses,
1263 pl08x->mem_buses);
1264 } else { 1262 } else {
1265 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR | 1263 plchan->dst_cctl = pl08x_cctl(cctl);
1266 pl08x_select_bus(pl08x->mem_buses,
1267 plchan->cd->periph_buses);
1268 } 1264 }
1269 1265
1270 dev_dbg(&pl08x->adev->dev, 1266 dev_dbg(&pl08x->adev->dev,
@@ -1451,6 +1447,8 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1451 struct scatterlist *sg; 1447 struct scatterlist *sg;
1452 dma_addr_t slave_addr; 1448 dma_addr_t slave_addr;
1453 int ret, tmp; 1449 int ret, tmp;
1450 u8 src_buses, dst_buses;
1451 u32 cctl;
1454 1452
1455 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", 1453 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1456 __func__, sg_dma_len(sgl), plchan->name); 1454 __func__, sg_dma_len(sgl), plchan->name);
@@ -1474,11 +1472,15 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1474 txd->direction = direction; 1472 txd->direction = direction;
1475 1473
1476 if (direction == DMA_MEM_TO_DEV) { 1474 if (direction == DMA_MEM_TO_DEV) {
1477 txd->cctl = plchan->dst_cctl; 1475 cctl = plchan->dst_cctl | PL080_CONTROL_SRC_INCR;
1478 slave_addr = plchan->cfg.dst_addr; 1476 slave_addr = plchan->cfg.dst_addr;
1477 src_buses = pl08x->mem_buses;
1478 dst_buses = plchan->cd->periph_buses;
1479 } else if (direction == DMA_DEV_TO_MEM) { 1479 } else if (direction == DMA_DEV_TO_MEM) {
1480 txd->cctl = plchan->src_cctl; 1480 cctl = plchan->src_cctl | PL080_CONTROL_DST_INCR;
1481 slave_addr = plchan->cfg.src_addr; 1481 slave_addr = plchan->cfg.src_addr;
1482 src_buses = plchan->cd->periph_buses;
1483 dst_buses = pl08x->mem_buses;
1482 } else { 1484 } else {
1483 pl08x_free_txd(pl08x, txd); 1485 pl08x_free_txd(pl08x, txd);
1484 dev_err(&pl08x->adev->dev, 1486 dev_err(&pl08x->adev->dev,
@@ -1486,6 +1488,8 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1486 return NULL; 1488 return NULL;
1487 } 1489 }
1488 1490
1491 txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses);
1492
1489 if (plchan->cfg.device_fc) 1493 if (plchan->cfg.device_fc)
1490 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : 1494 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1491 PL080_FLOW_PER2MEM_PER; 1495 PL080_FLOW_PER2MEM_PER;
@@ -1785,10 +1789,8 @@ static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1785 chan->name = chan->cd->bus_id; 1789 chan->name = chan->cd->bus_id;
1786 chan->cfg.src_addr = chan->cd->addr; 1790 chan->cfg.src_addr = chan->cd->addr;
1787 chan->cfg.dst_addr = chan->cd->addr; 1791 chan->cfg.dst_addr = chan->cd->addr;
1788 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR | 1792 chan->src_cctl = cctl;
1789 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses); 1793 chan->dst_cctl = cctl;
1790 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1791 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1792} 1794}
1793 1795
1794/* 1796/*