diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2009-08-26 04:16:46 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-26 20:38:51 -0400 |
commit | d4ec09acdb15cdb5afdb5cd03f6bceb5c3c690a5 (patch) | |
tree | 11b9a9e797958a86b4c33ffc8710a4528f7b4ba5 /drivers | |
parent | aed0628dae0c26b47d40d65f942abe30279b52a5 (diff) |
sfc: Do not reinitialise XAUI serdes before it has completed reset
falcon_reset_xaui() waits for XGXS reset to complete, but the XAUI
serdes reset may take longer. It needs to check both reset active
bits.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/sfc/falcon_hwdefs.h | 2 | ||||
-rw-r--r-- | drivers/net/sfc/falcon_xmac.c | 8 |
2 files changed, 7 insertions, 3 deletions
diff --git a/drivers/net/sfc/falcon_hwdefs.h b/drivers/net/sfc/falcon_hwdefs.h index 375e2a5961ec..2d2261117ace 100644 --- a/drivers/net/sfc/falcon_hwdefs.h +++ b/drivers/net/sfc/falcon_hwdefs.h | |||
@@ -700,6 +700,8 @@ | |||
700 | /* XGXS/XAUI powerdown/reset register */ | 700 | /* XGXS/XAUI powerdown/reset register */ |
701 | #define XX_PWR_RST_REG 0x1300 | 701 | #define XX_PWR_RST_REG 0x1300 |
702 | 702 | ||
703 | #define XX_SD_RST_ACT_LBN 16 | ||
704 | #define XX_SD_RST_ACT_WIDTH 1 | ||
703 | #define XX_PWRDND_EN_LBN 15 | 705 | #define XX_PWRDND_EN_LBN 15 |
704 | #define XX_PWRDND_EN_WIDTH 1 | 706 | #define XX_PWRDND_EN_WIDTH 1 |
705 | #define XX_PWRDNC_EN_LBN 14 | 707 | #define XX_PWRDNC_EN_LBN 14 |
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c index 2b3269c03263..bec52ca37eee 100644 --- a/drivers/net/sfc/falcon_xmac.c +++ b/drivers/net/sfc/falcon_xmac.c | |||
@@ -64,13 +64,15 @@ int falcon_reset_xaui(struct efx_nic *efx) | |||
64 | efx_oword_t reg; | 64 | efx_oword_t reg; |
65 | int count; | 65 | int count; |
66 | 66 | ||
67 | /* Start reset sequence */ | ||
67 | EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1); | 68 | EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1); |
68 | falcon_write(efx, ®, XX_PWR_RST_REG); | 69 | falcon_write(efx, ®, XX_PWR_RST_REG); |
69 | 70 | ||
70 | /* Give some time for the link to establish */ | 71 | /* Wait up to 10 ms for completion, then reinitialise */ |
71 | for (count = 0; count < 1000; count++) { /* wait upto 10ms */ | 72 | for (count = 0; count < 1000; count++) { |
72 | falcon_read(efx, ®, XX_PWR_RST_REG); | 73 | falcon_read(efx, ®, XX_PWR_RST_REG); |
73 | if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) { | 74 | if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0 && |
75 | EFX_OWORD_FIELD(reg, XX_SD_RST_ACT) == 0) { | ||
74 | falcon_setup_xaui(efx); | 76 | falcon_setup_xaui(efx); |
75 | return 0; | 77 | return 0; |
76 | } | 78 | } |