diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-04-16 14:06:59 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-05-28 18:11:00 -0400 |
commit | ce11ce171047f43e30a9cef8eeccada8eceb2418 (patch) | |
tree | 7ef680c6b370c96679d357a03da8b7fa87486b1a /drivers | |
parent | df62b1e663904e257fd5b174a9b29e6be6d0e902 (diff) |
e752x_edac: convert driver to use the new edac ABI
The legacy edac ABI is going to be removed. Port the driver to use
and benefit from the new API functionality.
Cc: Mark Gross <mark.gross@intel.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/edac/e752x_edac.c | 49 |
1 files changed, 34 insertions, 15 deletions
diff --git a/drivers/edac/e752x_edac.c b/drivers/edac/e752x_edac.c index cf17579ebc6d..aaa3bb8893c1 100644 --- a/drivers/edac/e752x_edac.c +++ b/drivers/edac/e752x_edac.c | |||
@@ -6,6 +6,9 @@ | |||
6 | * | 6 | * |
7 | * See "enum e752x_chips" below for supported chipsets | 7 | * See "enum e752x_chips" below for supported chipsets |
8 | * | 8 | * |
9 | * Datasheet: | ||
10 | * http://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html | ||
11 | * | ||
9 | * Written by Tom Zimmerman | 12 | * Written by Tom Zimmerman |
10 | * | 13 | * |
11 | * Contributors: | 14 | * Contributors: |
@@ -350,8 +353,10 @@ static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, | |||
350 | channel = !(error_one & 1); | 353 | channel = !(error_one & 1); |
351 | 354 | ||
352 | /* e752x mc reads 34:6 of the DRAM linear address */ | 355 | /* e752x mc reads 34:6 of the DRAM linear address */ |
353 | edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), | 356 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, |
354 | sec1_syndrome, row, channel, "e752x CE"); | 357 | page, offset_in_page(sec1_add << 4), sec1_syndrome, |
358 | row, channel, -1, | ||
359 | "e752x CE", "", NULL); | ||
355 | } | 360 | } |
356 | 361 | ||
357 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, | 362 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, |
@@ -385,9 +390,12 @@ static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, | |||
385 | edac_mc_find_csrow_by_page(mci, block_page); | 390 | edac_mc_find_csrow_by_page(mci, block_page); |
386 | 391 | ||
387 | /* e752x mc reads 34:6 of the DRAM linear address */ | 392 | /* e752x mc reads 34:6 of the DRAM linear address */ |
388 | edac_mc_handle_ue(mci, block_page, | 393 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, |
389 | offset_in_page(error_2b << 4), | 394 | block_page, |
390 | row, "e752x UE from Read"); | 395 | offset_in_page(error_2b << 4), 0, |
396 | row, -1, -1, | ||
397 | "e752x UE from Read", "", NULL); | ||
398 | |||
391 | } | 399 | } |
392 | if (error_one & 0x0404) { | 400 | if (error_one & 0x0404) { |
393 | error_2b = scrb_add; | 401 | error_2b = scrb_add; |
@@ -401,9 +409,11 @@ static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, | |||
401 | edac_mc_find_csrow_by_page(mci, block_page); | 409 | edac_mc_find_csrow_by_page(mci, block_page); |
402 | 410 | ||
403 | /* e752x mc reads 34:6 of the DRAM linear address */ | 411 | /* e752x mc reads 34:6 of the DRAM linear address */ |
404 | edac_mc_handle_ue(mci, block_page, | 412 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, |
405 | offset_in_page(error_2b << 4), | 413 | block_page, |
406 | row, "e752x UE from Scruber"); | 414 | offset_in_page(error_2b << 4), 0, |
415 | row, -1, -1, | ||
416 | "e752x UE from Scruber", "", NULL); | ||
407 | } | 417 | } |
408 | } | 418 | } |
409 | 419 | ||
@@ -426,7 +436,9 @@ static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, | |||
426 | return; | 436 | return; |
427 | 437 | ||
428 | debugf3("%s()\n", __func__); | 438 | debugf3("%s()\n", __func__); |
429 | edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); | 439 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, |
440 | -1, -1, -1, | ||
441 | "e752x UE log memory write", "", NULL); | ||
430 | } | 442 | } |
431 | 443 | ||
432 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, | 444 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, |
@@ -1081,10 +1093,11 @@ static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | |||
1081 | nr_pages = cumul_size - last_cumul_size; | 1093 | nr_pages = cumul_size - last_cumul_size; |
1082 | last_cumul_size = cumul_size; | 1094 | last_cumul_size = cumul_size; |
1083 | 1095 | ||
1084 | for (i = 0; i < drc_chan + 1; i++) { | 1096 | for (i = 0; i < csrow->nr_channels; i++) { |
1085 | struct dimm_info *dimm = csrow->channels[i].dimm; | 1097 | struct dimm_info *dimm = csrow->channels[i].dimm; |
1086 | 1098 | ||
1087 | dimm->nr_pages = nr_pages / (drc_chan + 1); | 1099 | debugf3("Initializing rank at (%i,%i)\n", index, i); |
1100 | dimm->nr_pages = nr_pages / csrow->nr_channels; | ||
1088 | dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | 1101 | dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ |
1089 | dimm->mtype = MEM_RDDR; /* only one type supported */ | 1102 | dimm->mtype = MEM_RDDR; /* only one type supported */ |
1090 | dimm->dtype = mem_dev ? DEV_X4 : DEV_X8; | 1103 | dimm->dtype = mem_dev ? DEV_X4 : DEV_X8; |
@@ -1232,6 +1245,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |||
1232 | u16 pci_data; | 1245 | u16 pci_data; |
1233 | u8 stat8; | 1246 | u8 stat8; |
1234 | struct mem_ctl_info *mci; | 1247 | struct mem_ctl_info *mci; |
1248 | struct edac_mc_layer layers[2]; | ||
1235 | struct e752x_pvt *pvt; | 1249 | struct e752x_pvt *pvt; |
1236 | u16 ddrcsr; | 1250 | u16 ddrcsr; |
1237 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ | 1251 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ |
@@ -1258,11 +1272,16 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |||
1258 | /* Dual channel = 1, Single channel = 0 */ | 1272 | /* Dual channel = 1, Single channel = 0 */ |
1259 | drc_chan = dual_channel_active(ddrcsr); | 1273 | drc_chan = dual_channel_active(ddrcsr); |
1260 | 1274 | ||
1261 | mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0); | 1275 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
1262 | 1276 | layers[0].size = E752X_NR_CSROWS; | |
1263 | if (mci == NULL) { | 1277 | layers[0].is_virt_csrow = true; |
1278 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | ||
1279 | layers[1].size = drc_chan + 1; | ||
1280 | layers[1].is_virt_csrow = false; | ||
1281 | mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | ||
1282 | sizeof(*pvt)); | ||
1283 | if (mci == NULL) | ||
1264 | return -ENOMEM; | 1284 | return -ENOMEM; |
1265 | } | ||
1266 | 1285 | ||
1267 | debugf3("%s(): init mci\n", __func__); | 1286 | debugf3("%s(): init mci\n", __func__); |
1268 | mci->mtype_cap = MEM_FLAG_RDDR; | 1287 | mci->mtype_cap = MEM_FLAG_RDDR; |