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authorLinus Torvalds <torvalds@linux-foundation.org>2012-04-27 22:52:30 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-04-27 22:52:30 -0400
commit84c6a81bc68ca5cf15d1b2b58bcc5645c64010b5 (patch)
treecd2e0ccf78d2226fcc969539594d392088dddac9 /drivers
parent9f7e2f9037ffa03f4c4cd6f19159a367e4e02f44 (diff)
parent2431a8154634027ce3915200699f26fb3725a1f2 (diff)
Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull misc SPI device driver bug fixes from Grant Likely. * tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6: spi/spi-bfin5xx: Fix flush of last bit after each spi transfer spi/spi-bfin5xx: fix reversed if condition in interrupt mode spi/spi_bfin_sport: drop bits_per_word from client data spi/bfin_spi: drop bits_per_word from client data spi/spi-bfin-sport: move word length setup to transfer handler spi/bfin5xx: rename config macro name for bfin5xx spi controller driver spi/pl022: Allow request for higher frequency than maximum possible spi/bcm63xx: set master driver mode_bits. spi/bcm63xx: don't use the stopping state spi/bcm63xx: convert to the pump message infrastructure spi/spi-ep93xx.c: use dma_transfer_direction instead of dma_data_direction spi: fix spi.h kernel-doc warning spi/pl022: Fix calculate_effective_freq() spi/pl022: Fix range checking for bits per word
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/Kconfig2
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/spi-bcm63xx.c163
-rw-r--r--drivers/spi/spi-bfin-sport.c21
-rw-r--r--drivers/spi/spi-bfin5xx.c14
-rw-r--r--drivers/spi/spi-ep93xx.c24
-rw-r--r--drivers/spi/spi-pl022.c58
7 files changed, 157 insertions, 127 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3ed748355b98..00c024039c97 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -74,7 +74,7 @@ config SPI_ATMEL
74 This selects a driver for the Atmel SPI Controller, present on 74 This selects a driver for the Atmel SPI Controller, present on
75 many AT32 (AVR32) and AT91 (ARM) chips. 75 many AT32 (AVR32) and AT91 (ARM) chips.
76 76
77config SPI_BFIN 77config SPI_BFIN5XX
78 tristate "SPI controller driver for ADI Blackfin5xx" 78 tristate "SPI controller driver for ADI Blackfin5xx"
79 depends on BLACKFIN 79 depends on BLACKFIN
80 help 80 help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index a1d48e0ba3dc..9d75d2198ff5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
15obj-$(CONFIG_SPI_ATH79) += spi-ath79.o 15obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
17obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 17obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
18obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o 18obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
19obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o 19obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
20obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o 20obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
21obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o 21obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index f01b2648452e..7491971139a6 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Broadcom BCM63xx SPI controller support 2 * Broadcom BCM63xx SPI controller support
3 * 3 *
4 * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org> 4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
@@ -30,6 +30,8 @@
30#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
31#include <linux/completion.h> 31#include <linux/completion.h>
32#include <linux/err.h> 32#include <linux/err.h>
33#include <linux/workqueue.h>
34#include <linux/pm_runtime.h>
33 35
34#include <bcm63xx_dev_spi.h> 36#include <bcm63xx_dev_spi.h>
35 37
@@ -37,8 +39,6 @@
37#define DRV_VER "0.1.2" 39#define DRV_VER "0.1.2"
38 40
39struct bcm63xx_spi { 41struct bcm63xx_spi {
40 spinlock_t lock;
41 int stopping;
42 struct completion done; 42 struct completion done;
43 43
44 void __iomem *regs; 44 void __iomem *regs;
@@ -96,17 +96,12 @@ static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
96 { 391000, SPI_CLK_0_391MHZ } 96 { 391000, SPI_CLK_0_391MHZ }
97}; 97};
98 98
99static int bcm63xx_spi_setup_transfer(struct spi_device *spi, 99static int bcm63xx_spi_check_transfer(struct spi_device *spi,
100 struct spi_transfer *t) 100 struct spi_transfer *t)
101{ 101{
102 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
103 u8 bits_per_word; 102 u8 bits_per_word;
104 u8 clk_cfg, reg;
105 u32 hz;
106 int i;
107 103
108 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; 104 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
109 hz = (t) ? t->speed_hz : spi->max_speed_hz;
110 if (bits_per_word != 8) { 105 if (bits_per_word != 8) {
111 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 106 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
112 __func__, bits_per_word); 107 __func__, bits_per_word);
@@ -119,6 +114,19 @@ static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
119 return -EINVAL; 114 return -EINVAL;
120 } 115 }
121 116
117 return 0;
118}
119
120static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
121 struct spi_transfer *t)
122{
123 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
124 u32 hz;
125 u8 clk_cfg, reg;
126 int i;
127
128 hz = (t) ? t->speed_hz : spi->max_speed_hz;
129
122 /* Find the closest clock configuration */ 130 /* Find the closest clock configuration */
123 for (i = 0; i < SPI_CLK_MASK; i++) { 131 for (i = 0; i < SPI_CLK_MASK; i++) {
124 if (hz <= bcm63xx_spi_freq_table[i][0]) { 132 if (hz <= bcm63xx_spi_freq_table[i][0]) {
@@ -139,8 +147,6 @@ static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
139 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 147 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
140 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 148 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
141 clk_cfg, hz); 149 clk_cfg, hz);
142
143 return 0;
144} 150}
145 151
146/* the spi->mode bits understood by this driver: */ 152/* the spi->mode bits understood by this driver: */
@@ -153,9 +159,6 @@ static int bcm63xx_spi_setup(struct spi_device *spi)
153 159
154 bs = spi_master_get_devdata(spi->master); 160 bs = spi_master_get_devdata(spi->master);
155 161
156 if (bs->stopping)
157 return -ESHUTDOWN;
158
159 if (!spi->bits_per_word) 162 if (!spi->bits_per_word)
160 spi->bits_per_word = 8; 163 spi->bits_per_word = 8;
161 164
@@ -165,7 +168,7 @@ static int bcm63xx_spi_setup(struct spi_device *spi)
165 return -EINVAL; 168 return -EINVAL;
166 } 169 }
167 170
168 ret = bcm63xx_spi_setup_transfer(spi, NULL); 171 ret = bcm63xx_spi_check_transfer(spi, NULL);
169 if (ret < 0) { 172 if (ret < 0) {
170 dev_err(&spi->dev, "setup: unsupported mode bits %x\n", 173 dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
171 spi->mode & ~MODEBITS); 174 spi->mode & ~MODEBITS);
@@ -190,28 +193,29 @@ static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
190 bs->remaining_bytes -= size; 193 bs->remaining_bytes -= size;
191} 194}
192 195
193static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 196static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
197 struct spi_transfer *t)
194{ 198{
195 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 199 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
196 u16 msg_ctl; 200 u16 msg_ctl;
197 u16 cmd; 201 u16 cmd;
198 202
203 /* Disable the CMD_DONE interrupt */
204 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
205
199 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 206 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
200 t->tx_buf, t->rx_buf, t->len); 207 t->tx_buf, t->rx_buf, t->len);
201 208
202 /* Transmitter is inhibited */ 209 /* Transmitter is inhibited */
203 bs->tx_ptr = t->tx_buf; 210 bs->tx_ptr = t->tx_buf;
204 bs->rx_ptr = t->rx_buf; 211 bs->rx_ptr = t->rx_buf;
205 init_completion(&bs->done);
206 212
207 if (t->tx_buf) { 213 if (t->tx_buf) {
208 bs->remaining_bytes = t->len; 214 bs->remaining_bytes = t->len;
209 bcm63xx_spi_fill_tx_fifo(bs); 215 bcm63xx_spi_fill_tx_fifo(bs);
210 } 216 }
211 217
212 /* Enable the command done interrupt which 218 init_completion(&bs->done);
213 * we use to determine completion of a command */
214 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
215 219
216 /* Fill in the Message control register */ 220 /* Fill in the Message control register */
217 msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); 221 msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
@@ -230,33 +234,76 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
230 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 234 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
231 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 235 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
232 bcm_spi_writew(bs, cmd, SPI_CMD); 236 bcm_spi_writew(bs, cmd, SPI_CMD);
233 wait_for_completion(&bs->done);
234 237
235 /* Disable the CMD_DONE interrupt */ 238 /* Enable the CMD_DONE interrupt */
236 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 239 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
237 240
238 return t->len - bs->remaining_bytes; 241 return t->len - bs->remaining_bytes;
239} 242}
240 243
241static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m) 244static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
242{ 245{
243 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 246 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
244 struct spi_transfer *t;
245 int ret = 0;
246 247
247 if (unlikely(list_empty(&m->transfers))) 248 pm_runtime_get_sync(&bs->pdev->dev);
248 return -EINVAL;
249 249
250 if (bs->stopping) 250 return 0;
251 return -ESHUTDOWN; 251}
252
253static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
254{
255 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
256
257 pm_runtime_put(&bs->pdev->dev);
258
259 return 0;
260}
261
262static int bcm63xx_spi_transfer_one(struct spi_master *master,
263 struct spi_message *m)
264{
265 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
266 struct spi_transfer *t;
267 struct spi_device *spi = m->spi;
268 int status = 0;
269 unsigned int timeout = 0;
252 270
253 list_for_each_entry(t, &m->transfers, transfer_list) { 271 list_for_each_entry(t, &m->transfers, transfer_list) {
254 ret += bcm63xx_txrx_bufs(spi, t); 272 unsigned int len = t->len;
255 } 273 u8 rx_tail;
256 274
257 m->complete(m->context); 275 status = bcm63xx_spi_check_transfer(spi, t);
276 if (status < 0)
277 goto exit;
258 278
259 return ret; 279 /* configure adapter for a new transfer */
280 bcm63xx_spi_setup_transfer(spi, t);
281
282 while (len) {
283 /* send the data */
284 len -= bcm63xx_txrx_bufs(spi, t);
285
286 timeout = wait_for_completion_timeout(&bs->done, HZ);
287 if (!timeout) {
288 status = -ETIMEDOUT;
289 goto exit;
290 }
291
292 /* read out all data */
293 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
294
295 /* Read out all the data */
296 if (rx_tail)
297 memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
298 }
299
300 m->actual_length += t->len;
301 }
302exit:
303 m->status = status;
304 spi_finalize_current_message(master);
305
306 return 0;
260} 307}
261 308
262/* This driver supports single master mode only. Hence 309/* This driver supports single master mode only. Hence
@@ -267,39 +314,15 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
267 struct spi_master *master = (struct spi_master *)dev_id; 314 struct spi_master *master = (struct spi_master *)dev_id;
268 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 315 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
269 u8 intr; 316 u8 intr;
270 u16 cmd;
271 317
272 /* Read interupts and clear them immediately */ 318 /* Read interupts and clear them immediately */
273 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 319 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
274 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 320 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
275 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 321 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
276 322
277 /* A tansfer completed */ 323 /* A transfer completed */
278 if (intr & SPI_INTR_CMD_DONE) { 324 if (intr & SPI_INTR_CMD_DONE)
279 u8 rx_tail; 325 complete(&bs->done);
280
281 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
282
283 /* Read out all the data */
284 if (rx_tail)
285 memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
286
287 /* See if there is more data to send */
288 if (bs->remaining_bytes > 0) {
289 bcm63xx_spi_fill_tx_fifo(bs);
290
291 /* Start the transfer */
292 bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
293 SPI_MSG_CTL);
294 cmd = bcm_spi_readw(bs, SPI_CMD);
295 cmd |= SPI_CMD_START_IMMEDIATE;
296 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
297 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
298 bcm_spi_writew(bs, cmd, SPI_CMD);
299 } else {
300 complete(&bs->done);
301 }
302 }
303 326
304 return IRQ_HANDLED; 327 return IRQ_HANDLED;
305} 328}
@@ -345,7 +368,6 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
345 } 368 }
346 369
347 bs = spi_master_get_devdata(master); 370 bs = spi_master_get_devdata(master);
348 init_completion(&bs->done);
349 371
350 platform_set_drvdata(pdev, master); 372 platform_set_drvdata(pdev, master);
351 bs->pdev = pdev; 373 bs->pdev = pdev;
@@ -379,12 +401,13 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
379 master->bus_num = pdata->bus_num; 401 master->bus_num = pdata->bus_num;
380 master->num_chipselect = pdata->num_chipselect; 402 master->num_chipselect = pdata->num_chipselect;
381 master->setup = bcm63xx_spi_setup; 403 master->setup = bcm63xx_spi_setup;
382 master->transfer = bcm63xx_transfer; 404 master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
405 master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
406 master->transfer_one_message = bcm63xx_spi_transfer_one;
407 master->mode_bits = MODEBITS;
383 bs->speed_hz = pdata->speed_hz; 408 bs->speed_hz = pdata->speed_hz;
384 bs->stopping = 0;
385 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 409 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
386 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 410 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
387 spin_lock_init(&bs->lock);
388 411
389 /* Initialize hardware */ 412 /* Initialize hardware */
390 clk_enable(bs->clk); 413 clk_enable(bs->clk);
@@ -418,18 +441,16 @@ static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
418 struct spi_master *master = platform_get_drvdata(pdev); 441 struct spi_master *master = platform_get_drvdata(pdev);
419 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 442 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
420 443
444 spi_unregister_master(master);
445
421 /* reset spi block */ 446 /* reset spi block */
422 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 447 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
423 spin_lock(&bs->lock);
424 bs->stopping = 1;
425 448
426 /* HW shutdown */ 449 /* HW shutdown */
427 clk_disable(bs->clk); 450 clk_disable(bs->clk);
428 clk_put(bs->clk); 451 clk_put(bs->clk);
429 452
430 spin_unlock(&bs->lock);
431 platform_set_drvdata(pdev, 0); 453 platform_set_drvdata(pdev, 0);
432 spi_unregister_master(master);
433 454
434 return 0; 455 return 0;
435} 456}
diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c
index 248a2cc671a9..1fe51198a622 100644
--- a/drivers/spi/spi-bfin-sport.c
+++ b/drivers/spi/spi-bfin-sport.c
@@ -252,19 +252,15 @@ static void
252bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data) 252bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data)
253{ 253{
254 struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip; 254 struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip;
255 unsigned int bits = (drv_data->ops == &bfin_sport_transfer_ops_u8 ? 7 : 15);
256 255
257 bfin_sport_spi_disable(drv_data); 256 bfin_sport_spi_disable(drv_data);
258 dev_dbg(drv_data->dev, "restoring spi ctl state\n"); 257 dev_dbg(drv_data->dev, "restoring spi ctl state\n");
259 258
260 bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); 259 bfin_write(&drv_data->regs->tcr1, chip->ctl_reg);
261 bfin_write(&drv_data->regs->tcr2, bits);
262 bfin_write(&drv_data->regs->tclkdiv, chip->baud); 260 bfin_write(&drv_data->regs->tclkdiv, chip->baud);
263 bfin_write(&drv_data->regs->tfsdiv, bits);
264 SSYNC(); 261 SSYNC();
265 262
266 bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); 263 bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS));
267 bfin_write(&drv_data->regs->rcr2, bits);
268 SSYNC(); 264 SSYNC();
269 265
270 bfin_sport_spi_cs_active(chip); 266 bfin_sport_spi_cs_active(chip);
@@ -420,11 +416,15 @@ bfin_sport_spi_pump_transfers(unsigned long data)
420 drv_data->cs_change = transfer->cs_change; 416 drv_data->cs_change = transfer->cs_change;
421 417
422 /* Bits per word setup */ 418 /* Bits per word setup */
423 bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; 419 bits_per_word = transfer->bits_per_word ? :
424 if (bits_per_word == 8) 420 message->spi->bits_per_word ? : 8;
425 drv_data->ops = &bfin_sport_transfer_ops_u8; 421 if (bits_per_word % 16 == 0)
426 else
427 drv_data->ops = &bfin_sport_transfer_ops_u16; 422 drv_data->ops = &bfin_sport_transfer_ops_u16;
423 else
424 drv_data->ops = &bfin_sport_transfer_ops_u8;
425 bfin_write(&drv_data->regs->tcr2, bits_per_word - 1);
426 bfin_write(&drv_data->regs->tfsdiv, bits_per_word - 1);
427 bfin_write(&drv_data->regs->rcr2, bits_per_word - 1);
428 428
429 drv_data->state = RUNNING_STATE; 429 drv_data->state = RUNNING_STATE;
430 430
@@ -598,11 +598,12 @@ bfin_sport_spi_setup(struct spi_device *spi)
598 } 598 }
599 chip->cs_chg_udelay = chip_info->cs_chg_udelay; 599 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
600 chip->idle_tx_val = chip_info->idle_tx_val; 600 chip->idle_tx_val = chip_info->idle_tx_val;
601 spi->bits_per_word = chip_info->bits_per_word;
602 } 601 }
603 } 602 }
604 603
605 if (spi->bits_per_word != 8 && spi->bits_per_word != 16) { 604 if (spi->bits_per_word % 8) {
605 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
606 spi->bits_per_word);
606 ret = -EINVAL; 607 ret = -EINVAL;
607 goto error; 608 goto error;
608 } 609 }
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c
index 3b83ff8b1e2b..9bb4d4af8547 100644
--- a/drivers/spi/spi-bfin5xx.c
+++ b/drivers/spi/spi-bfin5xx.c
@@ -396,7 +396,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
396 /* last read */ 396 /* last read */
397 if (drv_data->rx) { 397 if (drv_data->rx) {
398 dev_dbg(&drv_data->pdev->dev, "last read\n"); 398 dev_dbg(&drv_data->pdev->dev, "last read\n");
399 if (n_bytes % 2) { 399 if (!(n_bytes % 2)) {
400 u16 *buf = (u16 *)drv_data->rx; 400 u16 *buf = (u16 *)drv_data->rx;
401 for (loop = 0; loop < n_bytes / 2; loop++) 401 for (loop = 0; loop < n_bytes / 2; loop++)
402 *buf++ = bfin_read(&drv_data->regs->rdbr); 402 *buf++ = bfin_read(&drv_data->regs->rdbr);
@@ -424,7 +424,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
424 if (drv_data->rx && drv_data->tx) { 424 if (drv_data->rx && drv_data->tx) {
425 /* duplex */ 425 /* duplex */
426 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); 426 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
427 if (n_bytes % 2) { 427 if (!(n_bytes % 2)) {
428 u16 *buf = (u16 *)drv_data->rx; 428 u16 *buf = (u16 *)drv_data->rx;
429 u16 *buf2 = (u16 *)drv_data->tx; 429 u16 *buf2 = (u16 *)drv_data->tx;
430 for (loop = 0; loop < n_bytes / 2; loop++) { 430 for (loop = 0; loop < n_bytes / 2; loop++) {
@@ -442,7 +442,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
442 } else if (drv_data->rx) { 442 } else if (drv_data->rx) {
443 /* read */ 443 /* read */
444 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); 444 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
445 if (n_bytes % 2) { 445 if (!(n_bytes % 2)) {
446 u16 *buf = (u16 *)drv_data->rx; 446 u16 *buf = (u16 *)drv_data->rx;
447 for (loop = 0; loop < n_bytes / 2; loop++) { 447 for (loop = 0; loop < n_bytes / 2; loop++) {
448 *buf++ = bfin_read(&drv_data->regs->rdbr); 448 *buf++ = bfin_read(&drv_data->regs->rdbr);
@@ -458,7 +458,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
458 } else if (drv_data->tx) { 458 } else if (drv_data->tx) {
459 /* write */ 459 /* write */
460 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); 460 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
461 if (n_bytes % 2) { 461 if (!(n_bytes % 2)) {
462 u16 *buf = (u16 *)drv_data->tx; 462 u16 *buf = (u16 *)drv_data->tx;
463 for (loop = 0; loop < n_bytes / 2; loop++) { 463 for (loop = 0; loop < n_bytes / 2; loop++) {
464 bfin_read(&drv_data->regs->rdbr); 464 bfin_read(&drv_data->regs->rdbr);
@@ -587,6 +587,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
587 if (message->state == DONE_STATE) { 587 if (message->state == DONE_STATE) {
588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); 588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
589 message->status = 0; 589 message->status = 0;
590 bfin_spi_flush(drv_data);
590 bfin_spi_giveback(drv_data); 591 bfin_spi_giveback(drv_data);
591 return; 592 return;
592 } 593 }
@@ -870,8 +871,10 @@ static void bfin_spi_pump_transfers(unsigned long data)
870 message->actual_length += drv_data->len_in_bytes; 871 message->actual_length += drv_data->len_in_bytes;
871 /* Move to next transfer of this msg */ 872 /* Move to next transfer of this msg */
872 message->state = bfin_spi_next_transfer(drv_data); 873 message->state = bfin_spi_next_transfer(drv_data);
873 if (drv_data->cs_change) 874 if (drv_data->cs_change && message->state != DONE_STATE) {
875 bfin_spi_flush(drv_data);
874 bfin_spi_cs_deactive(drv_data, chip); 876 bfin_spi_cs_deactive(drv_data, chip);
877 }
875 } 878 }
876 879
877 /* Schedule next transfer tasklet */ 880 /* Schedule next transfer tasklet */
@@ -1026,7 +1029,6 @@ static int bfin_spi_setup(struct spi_device *spi)
1026 chip->cs_chg_udelay = chip_info->cs_chg_udelay; 1029 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1027 chip->idle_tx_val = chip_info->idle_tx_val; 1030 chip->idle_tx_val = chip_info->idle_tx_val;
1028 chip->pio_interrupt = chip_info->pio_interrupt; 1031 chip->pio_interrupt = chip_info->pio_interrupt;
1029 spi->bits_per_word = chip_info->bits_per_word;
1030 } else { 1032 } else {
1031 /* force a default base state */ 1033 /* force a default base state */
1032 chip->ctl_reg &= bfin_ctl_reg; 1034 chip->ctl_reg &= bfin_ctl_reg;
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 6db2887852d6..e8055073e84d 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -545,13 +545,12 @@ static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
545 * in case of failure. 545 * in case of failure.
546 */ 546 */
547static struct dma_async_tx_descriptor * 547static struct dma_async_tx_descriptor *
548ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir) 548ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
549{ 549{
550 struct spi_transfer *t = espi->current_msg->state; 550 struct spi_transfer *t = espi->current_msg->state;
551 struct dma_async_tx_descriptor *txd; 551 struct dma_async_tx_descriptor *txd;
552 enum dma_slave_buswidth buswidth; 552 enum dma_slave_buswidth buswidth;
553 struct dma_slave_config conf; 553 struct dma_slave_config conf;
554 enum dma_transfer_direction slave_dirn;
555 struct scatterlist *sg; 554 struct scatterlist *sg;
556 struct sg_table *sgt; 555 struct sg_table *sgt;
557 struct dma_chan *chan; 556 struct dma_chan *chan;
@@ -567,14 +566,13 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
567 memset(&conf, 0, sizeof(conf)); 566 memset(&conf, 0, sizeof(conf));
568 conf.direction = dir; 567 conf.direction = dir;
569 568
570 if (dir == DMA_FROM_DEVICE) { 569 if (dir == DMA_DEV_TO_MEM) {
571 chan = espi->dma_rx; 570 chan = espi->dma_rx;
572 buf = t->rx_buf; 571 buf = t->rx_buf;
573 sgt = &espi->rx_sgt; 572 sgt = &espi->rx_sgt;
574 573
575 conf.src_addr = espi->sspdr_phys; 574 conf.src_addr = espi->sspdr_phys;
576 conf.src_addr_width = buswidth; 575 conf.src_addr_width = buswidth;
577 slave_dirn = DMA_DEV_TO_MEM;
578 } else { 576 } else {
579 chan = espi->dma_tx; 577 chan = espi->dma_tx;
580 buf = t->tx_buf; 578 buf = t->tx_buf;
@@ -582,7 +580,6 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
582 580
583 conf.dst_addr = espi->sspdr_phys; 581 conf.dst_addr = espi->sspdr_phys;
584 conf.dst_addr_width = buswidth; 582 conf.dst_addr_width = buswidth;
585 slave_dirn = DMA_MEM_TO_DEV;
586 } 583 }
587 584
588 ret = dmaengine_slave_config(chan, &conf); 585 ret = dmaengine_slave_config(chan, &conf);
@@ -633,8 +630,7 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
633 if (!nents) 630 if (!nents)
634 return ERR_PTR(-ENOMEM); 631 return ERR_PTR(-ENOMEM);
635 632
636 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, 633 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
637 slave_dirn, DMA_CTRL_ACK);
638 if (!txd) { 634 if (!txd) {
639 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 635 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
640 return ERR_PTR(-ENOMEM); 636 return ERR_PTR(-ENOMEM);
@@ -651,12 +647,12 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
651 * unmapped. 647 * unmapped.
652 */ 648 */
653static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, 649static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
654 enum dma_data_direction dir) 650 enum dma_transfer_direction dir)
655{ 651{
656 struct dma_chan *chan; 652 struct dma_chan *chan;
657 struct sg_table *sgt; 653 struct sg_table *sgt;
658 654
659 if (dir == DMA_FROM_DEVICE) { 655 if (dir == DMA_DEV_TO_MEM) {
660 chan = espi->dma_rx; 656 chan = espi->dma_rx;
661 sgt = &espi->rx_sgt; 657 sgt = &espi->rx_sgt;
662 } else { 658 } else {
@@ -677,16 +673,16 @@ static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
677 struct spi_message *msg = espi->current_msg; 673 struct spi_message *msg = espi->current_msg;
678 struct dma_async_tx_descriptor *rxd, *txd; 674 struct dma_async_tx_descriptor *rxd, *txd;
679 675
680 rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE); 676 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM);
681 if (IS_ERR(rxd)) { 677 if (IS_ERR(rxd)) {
682 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); 678 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
683 msg->status = PTR_ERR(rxd); 679 msg->status = PTR_ERR(rxd);
684 return; 680 return;
685 } 681 }
686 682
687 txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE); 683 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV);
688 if (IS_ERR(txd)) { 684 if (IS_ERR(txd)) {
689 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE); 685 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
690 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); 686 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
691 msg->status = PTR_ERR(txd); 687 msg->status = PTR_ERR(txd);
692 return; 688 return;
@@ -705,8 +701,8 @@ static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
705 701
706 wait_for_completion(&espi->wait); 702 wait_for_completion(&espi->wait);
707 703
708 ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE); 704 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
709 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE); 705 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
710} 706}
711 707
712/** 708/**
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 09c925aaf320..400ae2121a2a 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1667,9 +1667,15 @@ static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1667 /* cpsdvsr = 254 & scr = 255 */ 1667 /* cpsdvsr = 254 & scr = 255 */
1668 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1668 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1669 1669
1670 if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1670 if (freq > max_tclk)
1671 dev_warn(&pl022->adev->dev,
1672 "Max speed that can be programmed is %d Hz, you requested %d\n",
1673 max_tclk, freq);
1674
1675 if (freq < min_tclk) {
1671 dev_err(&pl022->adev->dev, 1676 dev_err(&pl022->adev->dev,
1672 "controller data is incorrect: out of range frequency"); 1677 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1678 freq, min_tclk);
1673 return -EINVAL; 1679 return -EINVAL;
1674 } 1680 }
1675 1681
@@ -1681,26 +1687,37 @@ static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1681 while (scr <= SCR_MAX) { 1687 while (scr <= SCR_MAX) {
1682 tmp = spi_rate(rate, cpsdvsr, scr); 1688 tmp = spi_rate(rate, cpsdvsr, scr);
1683 1689
1684 if (tmp > freq) 1690 if (tmp > freq) {
1691 /* we need lower freq */
1685 scr++; 1692 scr++;
1693 continue;
1694 }
1695
1686 /* 1696 /*
1687 * If found exact value, update and break. 1697 * If found exact value, mark found and break.
1688 * If found more closer value, update and continue. 1698 * If found more closer value, update and break.
1689 */ 1699 */
1690 else if ((tmp == freq) || (tmp > best_freq)) { 1700 if (tmp > best_freq) {
1691 best_freq = tmp; 1701 best_freq = tmp;
1692 best_cpsdvsr = cpsdvsr; 1702 best_cpsdvsr = cpsdvsr;
1693 best_scr = scr; 1703 best_scr = scr;
1694 1704
1695 if (tmp == freq) 1705 if (tmp == freq)
1696 break; 1706 found = 1;
1697 } 1707 }
1698 scr++; 1708 /*
1709 * increased scr will give lower rates, which are not
1710 * required
1711 */
1712 break;
1699 } 1713 }
1700 cpsdvsr += 2; 1714 cpsdvsr += 2;
1701 scr = SCR_MIN; 1715 scr = SCR_MIN;
1702 } 1716 }
1703 1717
1718 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1719 freq);
1720
1704 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1721 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1705 clk_freq->scr = (u8) (best_scr & 0xFF); 1722 clk_freq->scr = (u8) (best_scr & 0xFF);
1706 dev_dbg(&pl022->adev->dev, 1723 dev_dbg(&pl022->adev->dev,
@@ -1823,9 +1840,12 @@ static int pl022_setup(struct spi_device *spi)
1823 } else 1840 } else
1824 chip->cs_control = chip_info->cs_control; 1841 chip->cs_control = chip_info->cs_control;
1825 1842
1826 if (bits <= 3) { 1843 /* Check bits per word with vendor specific range */
1827 /* PL022 doesn't support less than 4-bits */ 1844 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1828 status = -ENOTSUPP; 1845 status = -ENOTSUPP;
1846 dev_err(&spi->dev, "illegal data size for this controller!\n");
1847 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1848 pl022->vendor->max_bpw);
1829 goto err_config_params; 1849 goto err_config_params;
1830 } else if (bits <= 8) { 1850 } else if (bits <= 8) {
1831 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1851 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
@@ -1838,20 +1858,10 @@ static int pl022_setup(struct spi_device *spi)
1838 chip->read = READING_U16; 1858 chip->read = READING_U16;
1839 chip->write = WRITING_U16; 1859 chip->write = WRITING_U16;
1840 } else { 1860 } else {
1841 if (pl022->vendor->max_bpw >= 32) { 1861 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1842 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1862 chip->n_bytes = 4;
1843 chip->n_bytes = 4; 1863 chip->read = READING_U32;
1844 chip->read = READING_U32; 1864 chip->write = WRITING_U32;
1845 chip->write = WRITING_U32;
1846 } else {
1847 dev_err(&spi->dev,
1848 "illegal data size for this controller!\n");
1849 dev_err(&spi->dev,
1850 "a standard pl022 can only handle "
1851 "1 <= n <= 16 bit words\n");
1852 status = -ENOTSUPP;
1853 goto err_config_params;
1854 }
1855 } 1865 }
1856 1866
1857 /* Now Initialize all register settings required for this chip */ 1867 /* Now Initialize all register settings required for this chip */