drm/radeon/kms: move disp eng pll setup to init path

We really only need to set it up once on init or resume
rather than on every mode set.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

4 files changed, 36 insertions, 33 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 0fda830ef806..807b89b4933f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -355,15 +355,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
-static void atombios_disable_ss(struct drm_crtc *crtc)
+static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 {
-        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
         u32 ss_cntl;
 
         if (ASIC_IS_DCE4(rdev)) {
-                switch (radeon_crtc->pll_id) {
+                switch (pll_id) {
                 case ATOM_PPLL1:
                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
@@ -379,7 +376,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
                         return;
                 }
         } else if (ASIC_IS_AVIVO(rdev)) {
-                switch (radeon_crtc->pll_id) {
+                switch (pll_id) {
                 case ATOM_PPLL1:
                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
                         ss_cntl &= ~1;
@@ -406,13 +403,11 @@ union atom_enable_ss {
         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 };
 
-static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+static void atombios_crtc_program_ss(struct radeon_device *rdev,
                                      int enable,
                                      int pll_id,
                                      struct radeon_atom_ss *ss)
 {
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
         union atom_enable_ss args;
 
@@ -479,7 +474,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
         } else if (ASIC_IS_AVIVO(rdev)) {
                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
-                        atombios_disable_ss(crtc);
+                        atombios_disable_ss(rdev, pll_id);
                         return;
                 }
                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
@@ -491,7 +486,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
         } else {
                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
-                        atombios_disable_ss(crtc);
+                        atombios_disable_ss(rdev, pll_id);
                         return;
                 }
                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
@@ -702,11 +697,9 @@ union set_pixel_clock {
 /* on DCE5, make sure the voltage is high enough to support the
  * required disp clk.
  */
-static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
+static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
                                     u32 dispclk)
 {
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
         u8 frev, crev;
         int index;
         union set_pixel_clock args;
@@ -996,7 +989,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
                                           &ref_div, &post_div);
 
-        atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
+        atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
 
         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
@@ -1019,7 +1012,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
                         ss.step = step_size;
                 }
 
-                atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
+                atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
         }
 }
 
@@ -1494,6 +1487,24 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 
 }
 
+void radeon_atom_dcpll_init(struct radeon_device *rdev)
+{
+        /* always set DCPLL */
+        if (ASIC_IS_DCE4(rdev)) {
+                struct radeon_atom_ss ss;
+                bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
+                                                                   ASIC_INTERNAL_SS_ON_DCPLL,
+                                                                   rdev->clock.default_dispclk);
+                if (ss_enabled)
+                        atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
+                /* XXX: DCE5, make sure voltage, dispclk is high enough */
+                atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);
+                if (ss_enabled)
+                        atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
+        }
+
+}
+
 int atombios_crtc_mode_set(struct drm_crtc *crtc,
                            struct drm_display_mode *mode,
                            struct drm_display_mode *adjusted_mode,
@@ -1515,19 +1526,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
                 }
         }
 
-        /* always set DCPLL */
-        if (ASIC_IS_DCE4(rdev)) {
-                struct radeon_atom_ss ss;
-                bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
-                                                                   ASIC_INTERNAL_SS_ON_DCPLL,
-                                                                   rdev->clock.default_dispclk);
-                if (ss_enabled)
-                        atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
-                /* XXX: DCE5, make sure voltage, dispclk is high enough */
-                atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
-                if (ss_enabled)
-                        atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
-        }
         atombios_crtc_set_pll(crtc, adjusted_mode);
 
         if (ASIC_IS_DCE4(rdev))
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0afb13bd8dca..a811bc64ad5c 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -959,9 +959,11 @@ int radeon_resume_kms(struct drm_device *dev)
         radeon_fbdev_set_suspend(rdev, 0);
         console_unlock();
 
-        /* init dig PHYs */
-        if (rdev->is_atom_bios)
+        /* init dig PHYs, disp eng pll */
+        if (rdev->is_atom_bios) {
                 radeon_atom_encoder_init(rdev);
+                radeon_atom_dcpll_init(rdev);
+        }
         /* reset hpd state */
         radeon_hpd_init(rdev);
         /* blat the mode back in */
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index d3ffc18774a6..8c49fef1ce78 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1305,9 +1305,11 @@ int radeon_modeset_init(struct radeon_device *rdev)
                 return ret;
         }
 
-        /* init dig PHYs */
-        if (rdev->is_atom_bios)
+        /* init dig PHYs, disp eng pll */
+        if (rdev->is_atom_bios) {
                 radeon_atom_encoder_init(rdev);
+                radeon_atom_dcpll_init(rdev);
+        }
 
         /* initialize hpd */
         radeon_hpd_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 08ff857c8fd6..8cb19f38f8da 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -484,6 +484,7 @@ extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
+extern void radeon_atom_dcpll_init(struct radeon_device *rdev);
 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
                                            int action, uint8_t lane_num,
                                            uint8_t lane_set);