PCI/MSI: Add pci_msi_ignore_mask to prevent writes to MSI/MSI-X Mask Bits

MSI-X vector Mask Bits are in MSI-X Tables in PCI memory space.  Xen PV
guests can't write to those tables.  MSI vector Mask Bits are in PCI
configuration space.  Xen PV guests can write to config space, but those
writes are ignored.

Commit 0e4ccb1505a9 ("PCI: Add x86_msi.msi_mask_irq() and
msix_mask_irq()") added a way to override default_mask_msi_irqs() and
default_mask_msix_irqs() so they can be no-ops in Xen guests, but this is
more complicated than necessary.

Add "pci_msi_ignore_mask" in the core PCI MSI code.  If set,
default_mask_msi_irqs() and default_mask_msix_irqs() return without doing
anything.  This is less flexible, but much simpler.

[bhelgaas: changelog]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: David Vrabel <david.vrabel@citrix.com>
CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
CC: xen-devel@lists.xenproject.org

1 files changed, 6 insertions, 1 deletions

diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 9fab30af0e75..066c2fb9763a 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -23,6 +23,7 @@
 #include "pci.h"
 
 static int pci_msi_enable = 1;
+int pci_msi_ignore_mask;
 
 #define msix_table_size(flags)  ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
 
@@ -167,7 +168,7 @@ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 {
         u32 mask_bits = desc->masked;
 
-        if (!desc->msi_attrib.maskbit)
+        if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
                 return 0;
 
         mask_bits &= ~mask;
@@ -199,6 +200,10 @@ u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
         u32 mask_bits = desc->masked;
         unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
                                                 PCI_MSIX_ENTRY_VECTOR_CTRL;
+
+        if (pci_msi_ignore_mask)
+                return 0;
+
         mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
         if (flag)
                 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;