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authorYaniv Rosner <yanivr@broadcom.com>2009-11-05 12:18:04 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-05 23:00:26 -0500
commit18afb0a6fa69efb76b7a67a151c0530d63789141 (patch)
tree5b3b034905ebad5cee0d71ffa7f46598b1c35278 /drivers
parent6a2a2d6bf8581216e08be15fcb563cfd6c430e1e (diff)
bnx2x: Fix Parallel-Detect settings
Enable Parallel-Detect for 10G and 1G only if the relevant speed capability is enabled Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x_link.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index e32d3370862e..b5964cb7e761 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -1107,18 +1107,21 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
1107 MDIO_REG_BANK_SERDES_DIGITAL, 1107 MDIO_REG_BANK_SERDES_DIGITAL,
1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1108 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1109 &control2); 1109 &control2);
1110 1110 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1111 1111 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1112 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 1112 else
1113 1113 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1114 1114 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1115 params->speed_cap_mask, control2);
1115 CL45_WR_OVER_CL22(bp, params->port, 1116 CL45_WR_OVER_CL22(bp, params->port,
1116 params->phy_addr, 1117 params->phy_addr,
1117 MDIO_REG_BANK_SERDES_DIGITAL, 1118 MDIO_REG_BANK_SERDES_DIGITAL,
1118 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1119 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1119 control2); 1120 control2);
1120 1121
1121 if (phy_flags & PHY_XGXS_FLAG) { 1122 if ((phy_flags & PHY_XGXS_FLAG) &&
1123 (params->speed_cap_mask &
1124 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1122 DP(NETIF_MSG_LINK, "XGXS\n"); 1125 DP(NETIF_MSG_LINK, "XGXS\n");
1123 1126
1124 CL45_WR_OVER_CL22(bp, params->port, 1127 CL45_WR_OVER_CL22(bp, params->port,