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authorStephen Hemminger <shemminger@osdl.org>2005-06-27 14:33:14 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-06-27 18:05:07 -0400
commitd25f5a6774c3c567b11f8637a787603a62d102b1 (patch)
tree30bb7fd421f93590de9a98eec4e135d4e0c67f34 /drivers
parent7e676d9136d89d0cdf661de4b9a5f8955af94e03 (diff)
[PATCH] skge: handle Tx/Rx arbiter timeout
Need to handle receive and transmit packet arbiter timeouts. Transmit arbiter timeouts happens when Gigabit sends to 100Mbit port on same switch and pause occurs. Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/skge.c18
-rw-r--r--drivers/net/skge.h7
2 files changed, 23 insertions, 2 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 290d6aa92383..9f24714260be 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -2731,6 +2731,24 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2731 if (status & IS_XA2_F) 2731 if (status & IS_XA2_F)
2732 skge_tx_intr(hw->dev[1]); 2732 skge_tx_intr(hw->dev[1]);
2733 2733
2734 if (status & IS_PA_TO_RX1) {
2735 struct skge_port *skge = netdev_priv(hw->dev[0]);
2736 ++skge->net_stats.rx_over_errors;
2737 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2738 }
2739
2740 if (status & IS_PA_TO_RX2) {
2741 struct skge_port *skge = netdev_priv(hw->dev[1]);
2742 ++skge->net_stats.rx_over_errors;
2743 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2744 }
2745
2746 if (status & IS_PA_TO_TX1)
2747 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2748
2749 if (status & IS_PA_TO_TX2)
2750 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2751
2734 if (status & IS_MAC1) 2752 if (status & IS_MAC1)
2735 skge_mac_intr(hw, 0); 2753 skge_mac_intr(hw, 0);
2736 2754
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index ba6dfd2f01d8..37323cd29e7e 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -203,8 +203,11 @@ enum {
203 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */ 203 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
204 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */ 204 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
205 205
206 IS_PORT_1 = IS_XA1_F| IS_R1_F| IS_MAC1, 206 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
207 IS_PORT_2 = IS_XA2_F| IS_R2_F| IS_MAC2, 207 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
208
209 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
210 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
208}; 211};
209 212
210 213