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authorPaul Mundt <lethal@linux-sh.org>2007-11-26 03:56:31 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:18:57 -0500
commitff1b7506051014cc38036401b89e426bf3d6a608 (patch)
treea6612722484e5ffa621d58edbfb9e817f3f543cb /drivers
parent1322b9def91ab8e9e673b58a64e13d6effaaa652 (diff)
rtc: rtc-sh: SH-2A support.
Trivial support for the SH-2A on-chip RTC. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/rtc/Kconfig2
-rw-r--r--drivers/rtc/rtc-sh.c20
2 files changed, 19 insertions, 3 deletions
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 5900c772a1bc..45e4b9648176 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -404,7 +404,7 @@ config RTC_DRV_SA1100
404 404
405config RTC_DRV_SH 405config RTC_DRV_SH
406 tristate "SuperH On-Chip RTC" 406 tristate "SuperH On-Chip RTC"
407 depends on RTC_CLASS && (CPU_SH3 || CPU_SH4 || CPU_SH5) 407 depends on RTC_CLASS && SUPERH
408 help 408 help
409 Say Y here to enable support for the on-chip RTC found in 409 Say Y here to enable support for the on-chip RTC found in
410 most SuperH processors. 410 most SuperH processors.
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index a1d5d55985f6..af9bc57c8920 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -26,9 +26,13 @@
26#include <asm/rtc.h> 26#include <asm/rtc.h>
27 27
28#define DRV_NAME "sh-rtc" 28#define DRV_NAME "sh-rtc"
29#define DRV_VERSION "0.1.4" 29#define DRV_VERSION "0.1.5"
30 30
31#ifdef CONFIG_CPU_SH3 31#ifdef CONFIG_CPU_SH2A
32#define rtc_reg_size sizeof(u16)
33#define RTC_BIT_INVERTED 0
34#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
35#elif defined(CONFIG_CPU_SH3)
32#define rtc_reg_size sizeof(u16) 36#define rtc_reg_size sizeof(u16)
33#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */ 37#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
34#define RTC_DEF_CAPABILITIES 0UL 38#define RTC_DEF_CAPABILITIES 0UL
@@ -62,6 +66,18 @@
62#define RCR1 RTC_REG(14) /* Control */ 66#define RCR1 RTC_REG(14) /* Control */
63#define RCR2 RTC_REG(15) /* Control */ 67#define RCR2 RTC_REG(15) /* Control */
64 68
69/*
70 * Note on RYRAR and RCR3: Up until this point most of the register
71 * definitions are consistent across all of the available parts. However,
72 * the placement of the optional RYRAR and RCR3 (the RYRAR control
73 * register used to control RYRCNT/RYRAR compare) varies considerably
74 * across various parts, occasionally being mapped in to a completely
75 * unrelated address space. For proper RYRAR support a separate resource
76 * would have to be handed off, but as this is purely optional in
77 * practice, we simply opt not to support it, thereby keeping the code
78 * quite a bit more simplified.
79 */
80
65/* ALARM Bits - or with BCD encoded value */ 81/* ALARM Bits - or with BCD encoded value */
66#define AR_ENB 0x80 /* Enable for alarm cmp */ 82#define AR_ENB 0x80 /* Enable for alarm cmp */
67 83