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authorKevin Hilman <khilman@deeprootsystems.com>2009-02-10 23:30:37 -0500
committerWim Van Sebroeck <wim@iguana.be>2009-09-18 04:37:01 -0400
commit9fd868f440c3d722199a14200b2a64a0a5e70221 (patch)
tree395a15115f6abd320158cc8b4a21dd04b2501ff5 /drivers
parent0ecc3bf47b09de24c6b1163ba6558448aadd31ce (diff)
[WATCHDOG] davinci: use clock framework for timer frequency
Remove use of CLOCK_TICK_RATE in favor of using clock framework for getting timer frequency. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/watchdog/davinci_wdt.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 83e22e7ea4a2..9d7520fa9e9c 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -25,6 +25,7 @@
25#include <linux/uaccess.h> 25#include <linux/uaccess.h>
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/device.h> 27#include <linux/device.h>
28#include <linux/clk.h>
28 29
29#define MODULE_NAME "DAVINCI-WDT: " 30#define MODULE_NAME "DAVINCI-WDT: "
30 31
@@ -69,6 +70,7 @@ static unsigned long wdt_status;
69 70
70static struct resource *wdt_mem; 71static struct resource *wdt_mem;
71static void __iomem *wdt_base; 72static void __iomem *wdt_base;
73struct clk *wdt_clk;
72 74
73static void wdt_service(void) 75static void wdt_service(void)
74{ 76{
@@ -86,6 +88,9 @@ static void wdt_enable(void)
86{ 88{
87 u32 tgcr; 89 u32 tgcr;
88 u32 timer_margin; 90 u32 timer_margin;
91 unsigned long wdt_freq;
92
93 wdt_freq = clk_get_rate(wdt_clk);
89 94
90 spin_lock(&io_lock); 95 spin_lock(&io_lock);
91 96
@@ -99,9 +104,9 @@ static void wdt_enable(void)
99 iowrite32(0, wdt_base + TIM12); 104 iowrite32(0, wdt_base + TIM12);
100 iowrite32(0, wdt_base + TIM34); 105 iowrite32(0, wdt_base + TIM34);
101 /* set timeout period */ 106 /* set timeout period */
102 timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff); 107 timer_margin = (((u64)heartbeat * wdt_freq) & 0xffffffff);
103 iowrite32(timer_margin, wdt_base + PRD12); 108 iowrite32(timer_margin, wdt_base + PRD12);
104 timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32); 109 timer_margin = (((u64)heartbeat * wdt_freq) >> 32);
105 iowrite32(timer_margin, wdt_base + PRD34); 110 iowrite32(timer_margin, wdt_base + PRD34);
106 /* enable run continuously */ 111 /* enable run continuously */
107 iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR); 112 iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
@@ -199,6 +204,12 @@ static int __devinit davinci_wdt_probe(struct platform_device *pdev)
199 struct resource *res; 204 struct resource *res;
200 struct device *dev = &pdev->dev; 205 struct device *dev = &pdev->dev;
201 206
207 wdt_clk = clk_get(dev, NULL);
208 if (WARN_ON(IS_ERR(wdt_clk)))
209 return PTR_ERR(wdt_clk);
210
211 clk_enable(wdt_clk);
212
202 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) 213 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
203 heartbeat = DEFAULT_HEARTBEAT; 214 heartbeat = DEFAULT_HEARTBEAT;
204 215
@@ -245,6 +256,10 @@ static int __devexit davinci_wdt_remove(struct platform_device *pdev)
245 kfree(wdt_mem); 256 kfree(wdt_mem);
246 wdt_mem = NULL; 257 wdt_mem = NULL;
247 } 258 }
259
260 clk_disable(wdt_clk);
261 clk_put(wdt_clk);
262
248 return 0; 263 return 0;
249} 264}
250 265