diff options
author | Michael Chan <mchan@broadcom.com> | 2005-04-21 20:05:28 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2005-04-21 20:05:28 -0400 |
commit | 85e94cedc44d1c2c1663b5b18f703ca5e7316e59 (patch) | |
tree | 0e28e8b073f7ecefd2916dd40d248b914d1a6c0b /drivers | |
parent | 053d78000be4906fac6446ad517ca3897dc6cd84 (diff) |
[TG3]: Minor 5752 fixes
Some minor 5752 fixes mostly for correctness and add 5752 PHY ID.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/tg3.c | 24 | ||||
-rw-r--r-- | drivers/net/tg3.h | 1 |
2 files changed, 18 insertions, 7 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index c1881976927d..f22f19bbf11a 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -1094,7 +1094,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state) | |||
1094 | CLOCK_CTRL_ALTCLK | | 1094 | CLOCK_CTRL_ALTCLK | |
1095 | CLOCK_CTRL_PWRDOWN_PLL133); | 1095 | CLOCK_CTRL_PWRDOWN_PLL133); |
1096 | udelay(40); | 1096 | udelay(40); |
1097 | } else if (!((GET_ASIC_REV(tp->pci_chip_rev_id) == 5750) && | 1097 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1098 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { | 1098 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
1099 | u32 newbits1, newbits2; | 1099 | u32 newbits1, newbits2; |
1100 | 1100 | ||
@@ -5237,8 +5237,11 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5237 | RDMAC_MODE_LNGREAD_ENAB); | 5237 | RDMAC_MODE_LNGREAD_ENAB); |
5238 | if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) | 5238 | if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) |
5239 | rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE; | 5239 | rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE; |
5240 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | 5240 | |
5241 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | 5241 | /* If statement applies to 5705 and 5750 PCI devices only */ |
5242 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | ||
5243 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | ||
5244 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | ||
5242 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && | 5245 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
5243 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || | 5246 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
5244 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | 5247 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { |
@@ -5249,6 +5252,9 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5249 | } | 5252 | } |
5250 | } | 5253 | } |
5251 | 5254 | ||
5255 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | ||
5256 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | ||
5257 | |||
5252 | #if TG3_TSO_SUPPORT != 0 | 5258 | #if TG3_TSO_SUPPORT != 0 |
5253 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | 5259 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
5254 | rdmac_mode |= (1 << 27); | 5260 | rdmac_mode |= (1 << 27); |
@@ -5351,8 +5357,10 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5351 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | 5357 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | |
5352 | WDMAC_MODE_LNGREAD_ENAB); | 5358 | WDMAC_MODE_LNGREAD_ENAB); |
5353 | 5359 | ||
5354 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | 5360 | /* If statement applies to 5705 and 5750 PCI devices only */ |
5355 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | 5361 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
5362 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | ||
5363 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | ||
5356 | if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) && | 5364 | if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) && |
5357 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || | 5365 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
5358 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | 5366 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { |
@@ -7025,7 +7033,7 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |||
7025 | tw32(NVRAM_CFG1, nvcfg1); | 7033 | tw32(NVRAM_CFG1, nvcfg1); |
7026 | } | 7034 | } |
7027 | 7035 | ||
7028 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | 7036 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { |
7029 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { | 7037 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
7030 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: | 7038 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
7031 | tp->nvram_jedecnum = JEDEC_ATMEL; | 7039 | tp->nvram_jedecnum = JEDEC_ATMEL; |
@@ -8462,7 +8470,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
8462 | /* DMA read watermark not used on PCIE */ | 8470 | /* DMA read watermark not used on PCIE */ |
8463 | tp->dma_rwctrl |= 0x00180000; | 8471 | tp->dma_rwctrl |= 0x00180000; |
8464 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | 8472 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { |
8465 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | 8473 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
8474 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | ||
8466 | tp->dma_rwctrl |= 0x003f0000; | 8475 | tp->dma_rwctrl |= 0x003f0000; |
8467 | else | 8476 | else |
8468 | tp->dma_rwctrl |= 0x003f000f; | 8477 | tp->dma_rwctrl |= 0x003f000f; |
@@ -8628,6 +8637,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp) | |||
8628 | case PHY_ID_BCM5704: return "5704"; | 8637 | case PHY_ID_BCM5704: return "5704"; |
8629 | case PHY_ID_BCM5705: return "5705"; | 8638 | case PHY_ID_BCM5705: return "5705"; |
8630 | case PHY_ID_BCM5750: return "5750"; | 8639 | case PHY_ID_BCM5750: return "5750"; |
8640 | case PHY_ID_BCM5752: return "5752"; | ||
8631 | case PHY_ID_BCM8002: return "8002/serdes"; | 8641 | case PHY_ID_BCM8002: return "8002/serdes"; |
8632 | case 0: return "serdes"; | 8642 | case 0: return "serdes"; |
8633 | default: return "unknown"; | 8643 | default: return "unknown"; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 3a91a57a3205..4732a804974b 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2150,6 +2150,7 @@ struct tg3 { | |||
2150 | #define PHY_ID_BCM5704 0x60008190 | 2150 | #define PHY_ID_BCM5704 0x60008190 |
2151 | #define PHY_ID_BCM5705 0x600081a0 | 2151 | #define PHY_ID_BCM5705 0x600081a0 |
2152 | #define PHY_ID_BCM5750 0x60008180 | 2152 | #define PHY_ID_BCM5750 0x60008180 |
2153 | #define PHY_ID_BCM5752 0x60008100 | ||
2153 | #define PHY_ID_BCM8002 0x60010140 | 2154 | #define PHY_ID_BCM8002 0x60010140 |
2154 | #define PHY_ID_INVALID 0xffffffff | 2155 | #define PHY_ID_INVALID 0xffffffff |
2155 | #define PHY_ID_REV_MASK 0x0000000f | 2156 | #define PHY_ID_REV_MASK 0x0000000f |