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authorEric Anholt <eric@anholt.net>2009-07-10 16:02:26 -0400
committerEric Anholt <eric@anholt.net>2009-07-10 17:10:58 -0400
commitd05ca301997c94c2ef3c112b15319d13fa8cddab (patch)
tree5455f4c87ef8b66e390b587799922535778ff822 /drivers
parent901782b21ecb2af4dde1598b3142bf0e80b20853 (diff)
drm/i915: Zap the GTT mapping when transitioning from untiled to tiled.
As of 52dc7d32b88156248167864f77a9026abe27b432, we could leave an old linear GTT mapping in place, so that apps trying to GTT-mapped write in tiled data wouldn't get the fence added, and garbage would get displayed. Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c6
3 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9d6889799d01..d08752875885 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -673,6 +673,7 @@ void i915_gem_free_object(struct drm_gem_object *obj);
673int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 673int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
674void i915_gem_object_unpin(struct drm_gem_object *obj); 674void i915_gem_object_unpin(struct drm_gem_object *obj);
675int i915_gem_object_unbind(struct drm_gem_object *obj); 675int i915_gem_object_unbind(struct drm_gem_object *obj);
676void i915_gem_release_mmap(struct drm_gem_object *obj);
676void i915_gem_lastclose(struct drm_device *dev); 677void i915_gem_lastclose(struct drm_device *dev);
677uint32_t i915_get_gem_seqno(struct drm_device *dev); 678uint32_t i915_get_gem_seqno(struct drm_device *dev);
678int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); 679int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 08d8e5d85955..5bf420378b6d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1266,7 +1266,7 @@ out_free_list:
1266 * mapping will then trigger a page fault on the next user access, allowing 1266 * mapping will then trigger a page fault on the next user access, allowing
1267 * fixup by i915_gem_fault(). 1267 * fixup by i915_gem_fault().
1268 */ 1268 */
1269static void 1269void
1270i915_gem_release_mmap(struct drm_gem_object *obj) 1270i915_gem_release_mmap(struct drm_gem_object *obj)
1271{ 1271{
1272 struct drm_device *dev = obj->dev; 1272 struct drm_device *dev = obj->dev;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index daeae62e1c28..a2d527b22ec4 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -521,6 +521,12 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
521 goto err; 521 goto err;
522 } 522 }
523 523
524 /* If we've changed tiling, GTT-mappings of the object
525 * need to re-fault to ensure that the correct fence register
526 * setup is in place.
527 */
528 i915_gem_release_mmap(obj);
529
524 obj_priv->tiling_mode = args->tiling_mode; 530 obj_priv->tiling_mode = args->tiling_mode;
525 obj_priv->stride = args->stride; 531 obj_priv->stride = args->stride;
526 } 532 }