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authorMichael Chan <mchan@broadcom.com>2007-10-10 19:16:51 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:55:57 -0400
commit846f5c622fe033520c775cc2c40c06f3e2adea85 (patch)
tree384203c173be7827d96e1a722fdd754a3b8ca886 /drivers
parent489310a440e606512b1fd79d8562d1da6b715448 (diff)
[BNX2]: Fix default WoL setting.
Change the default WoL setting to match the NVRAM's setting. It always defaulted to WoL disabled before and caused a lot of confusion for users. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2.c20
-rw-r--r--drivers/net/bnx2.h1
2 files changed, 15 insertions, 6 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 21493e0cbd42..574d043cdfcd 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -6569,8 +6569,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6569 if (i != 2) 6569 if (i != 2)
6570 bp->fw_version[j++] = '.'; 6570 bp->fw_version[j++] = '.';
6571 } 6571 }
6572 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) & 6572 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
6573 BNX2_PORT_FEATURE_ASF_ENABLED) { 6573 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
6574 bp->wol = 1;
6575
6576 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
6574 bp->flags |= ASF_ENABLE_FLAG; 6577 bp->flags |= ASF_ENABLE_FLAG;
6575 6578
6576 for (i = 0; i < 30; i++) { 6579 for (i = 0; i < 30; i++) {
@@ -6640,11 +6643,14 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6640 bp->phy_port = PORT_TP; 6643 bp->phy_port = PORT_TP;
6641 if (bp->phy_flags & PHY_SERDES_FLAG) { 6644 if (bp->phy_flags & PHY_SERDES_FLAG) {
6642 bp->phy_port = PORT_FIBRE; 6645 bp->phy_port = PORT_FIBRE;
6643 bp->flags |= NO_WOL_FLAG; 6646 reg = REG_RD_IND(bp, bp->shmem_base +
6647 BNX2_SHARED_HW_CFG_CONFIG);
6648 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
6649 bp->flags |= NO_WOL_FLAG;
6650 bp->wol = 0;
6651 }
6644 if (CHIP_NUM(bp) != CHIP_NUM_5706) { 6652 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
6645 bp->phy_addr = 2; 6653 bp->phy_addr = 2;
6646 reg = REG_RD_IND(bp, bp->shmem_base +
6647 BNX2_SHARED_HW_CFG_CONFIG);
6648 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) 6654 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
6649 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG; 6655 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
6650 } 6656 }
@@ -6659,8 +6665,10 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6659 6665
6660 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 6666 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
6661 (CHIP_ID(bp) == CHIP_ID_5708_B0) || 6667 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
6662 (CHIP_ID(bp) == CHIP_ID_5708_B1)) 6668 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
6663 bp->flags |= NO_WOL_FLAG; 6669 bp->flags |= NO_WOL_FLAG;
6670 bp->wol = 0;
6671 }
6664 6672
6665 if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 6673 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6666 bp->tx_quick_cons_trip_int = 6674 bp->tx_quick_cons_trip_int =
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 56c190fc6de6..1dce0d1a2581 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6908,6 +6908,7 @@ struct fw_info {
6908#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0 6908#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
6909#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 6909#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
6910#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 6910#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
6911#define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX 0x8000
6911 6912
6912#define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040 6913#define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
6913#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 6914#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000