diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-07-07 21:39:18 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-07-12 20:13:41 -0400 |
commit | 631872155f35b907ae3950016d9e72a308449d69 (patch) | |
tree | b75acbc33e97a3c811a240fccc16b3f17cb0ed83 /drivers | |
parent | f56cb86f9abd229418f894a8ffedfb9ff465c181 (diff) |
drm/nv50: move tlb flushing to a helper function
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 62 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_sgdma.c | 34 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_instmem.c | 23 |
4 files changed, 23 insertions, 97 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index e21eacc47290..6a6873d4b28a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -1039,6 +1039,7 @@ extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); | |||
1039 | extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); | 1039 | extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); |
1040 | extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); | 1040 | extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); |
1041 | extern void nv50_instmem_flush(struct drm_device *); | 1041 | extern void nv50_instmem_flush(struct drm_device *); |
1042 | extern void nv50_vm_flush(struct drm_device *, int engine); | ||
1042 | 1043 | ||
1043 | /* nv04_mc.c */ | 1044 | /* nv04_mc.c */ |
1044 | extern int nv04_mc_init(struct drm_device *); | 1045 | extern int nv04_mc_init(struct drm_device *); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 5152c0a7e6f7..5f8f95d40395 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -176,34 +176,10 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, | |||
176 | } | 176 | } |
177 | dev_priv->engine.instmem.flush(dev); | 177 | dev_priv->engine.instmem.flush(dev); |
178 | 178 | ||
179 | nv_wr32(dev, 0x100c80, 0x00050001); | 179 | nv50_vm_flush(dev, 5); |
180 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | 180 | nv50_vm_flush(dev, 0); |
181 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | 181 | nv50_vm_flush(dev, 4); |
182 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | 182 | nv50_vm_flush(dev, 6); |
183 | return -EBUSY; | ||
184 | } | ||
185 | |||
186 | nv_wr32(dev, 0x100c80, 0x00000001); | ||
187 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
188 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
189 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
190 | return -EBUSY; | ||
191 | } | ||
192 | |||
193 | nv_wr32(dev, 0x100c80, 0x00040001); | ||
194 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
195 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
196 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
197 | return -EBUSY; | ||
198 | } | ||
199 | |||
200 | nv_wr32(dev, 0x100c80, 0x00060001); | ||
201 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
202 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
203 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
204 | return -EBUSY; | ||
205 | } | ||
206 | |||
207 | return 0; | 183 | return 0; |
208 | } | 184 | } |
209 | 185 | ||
@@ -232,32 +208,10 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) | |||
232 | } | 208 | } |
233 | dev_priv->engine.instmem.flush(dev); | 209 | dev_priv->engine.instmem.flush(dev); |
234 | 210 | ||
235 | nv_wr32(dev, 0x100c80, 0x00050001); | 211 | nv50_vm_flush(dev, 5); |
236 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | 212 | nv50_vm_flush(dev, 0); |
237 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | 213 | nv50_vm_flush(dev, 4); |
238 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | 214 | nv50_vm_flush(dev, 6); |
239 | return; | ||
240 | } | ||
241 | |||
242 | nv_wr32(dev, 0x100c80, 0x00000001); | ||
243 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
244 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
245 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
246 | return; | ||
247 | } | ||
248 | |||
249 | nv_wr32(dev, 0x100c80, 0x00040001); | ||
250 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
251 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
252 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
253 | return; | ||
254 | } | ||
255 | |||
256 | nv_wr32(dev, 0x100c80, 0x00060001); | ||
257 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
258 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
259 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
260 | } | ||
261 | } | 215 | } |
262 | 216 | ||
263 | /* | 217 | /* |
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 1b2ab5a714ce..491767fe4fcf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c | |||
@@ -118,21 +118,8 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) | |||
118 | dev_priv->engine.instmem.flush(nvbe->dev); | 118 | dev_priv->engine.instmem.flush(nvbe->dev); |
119 | 119 | ||
120 | if (dev_priv->card_type == NV_50) { | 120 | if (dev_priv->card_type == NV_50) { |
121 | nv_wr32(dev, 0x100c80, 0x00050001); | 121 | nv50_vm_flush(dev, 5); /* PGRAPH */ |
122 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | 122 | nv50_vm_flush(dev, 0); /* PFIFO */ |
123 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
124 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", | ||
125 | nv_rd32(dev, 0x100c80)); | ||
126 | return -EBUSY; | ||
127 | } | ||
128 | |||
129 | nv_wr32(dev, 0x100c80, 0x00000001); | ||
130 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
131 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
132 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", | ||
133 | nv_rd32(dev, 0x100c80)); | ||
134 | return -EBUSY; | ||
135 | } | ||
136 | } | 123 | } |
137 | 124 | ||
138 | nvbe->bound = true; | 125 | nvbe->bound = true; |
@@ -171,21 +158,8 @@ nouveau_sgdma_unbind(struct ttm_backend *be) | |||
171 | dev_priv->engine.instmem.flush(nvbe->dev); | 158 | dev_priv->engine.instmem.flush(nvbe->dev); |
172 | 159 | ||
173 | if (dev_priv->card_type == NV_50) { | 160 | if (dev_priv->card_type == NV_50) { |
174 | nv_wr32(dev, 0x100c80, 0x00050001); | 161 | nv50_vm_flush(dev, 5); |
175 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | 162 | nv50_vm_flush(dev, 0); |
176 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
177 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", | ||
178 | nv_rd32(dev, 0x100c80)); | ||
179 | return -EBUSY; | ||
180 | } | ||
181 | |||
182 | nv_wr32(dev, 0x100c80, 0x00000001); | ||
183 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
184 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
185 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", | ||
186 | nv_rd32(dev, 0x100c80)); | ||
187 | return -EBUSY; | ||
188 | } | ||
189 | } | 163 | } |
190 | 164 | ||
191 | nvbe->bound = false; | 165 | nvbe->bound = false; |
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c index d9feee3b9f58..2a5ec887291c 100644 --- a/drivers/gpu/drm/nouveau/nv50_instmem.c +++ b/drivers/gpu/drm/nouveau/nv50_instmem.c | |||
@@ -453,19 +453,8 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) | |||
453 | } | 453 | } |
454 | dev_priv->engine.instmem.flush(dev); | 454 | dev_priv->engine.instmem.flush(dev); |
455 | 455 | ||
456 | nv_wr32(dev, 0x100c80, 0x00040001); | 456 | nv50_vm_flush(dev, 4); |
457 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | 457 | nv50_vm_flush(dev, 6); |
458 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (1)\n"); | ||
459 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
460 | return -EBUSY; | ||
461 | } | ||
462 | |||
463 | nv_wr32(dev, 0x100c80, 0x00060001); | ||
464 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
465 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
466 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
467 | return -EBUSY; | ||
468 | } | ||
469 | 458 | ||
470 | gpuobj->im_bound = 1; | 459 | gpuobj->im_bound = 1; |
471 | return 0; | 460 | return 0; |
@@ -502,3 +491,11 @@ nv50_instmem_flush(struct drm_device *dev) | |||
502 | NV_ERROR(dev, "PRAMIN flush timeout\n"); | 491 | NV_ERROR(dev, "PRAMIN flush timeout\n"); |
503 | } | 492 | } |
504 | 493 | ||
494 | void | ||
495 | nv50_vm_flush(struct drm_device *dev, int engine) | ||
496 | { | ||
497 | nv_wr32(dev, 0x100c80, (engine << 16) | 1); | ||
498 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) | ||
499 | NV_ERROR(dev, "vm flush timeout: engine %d\n", engine); | ||
500 | } | ||
501 | |||