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authorOlimpiu Pascariu <olimpiu.pascariu@gmail.com>2010-03-21 14:46:26 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-05-17 23:51:14 -0400
commit0dd8be8c94d0f273685092106daf0875d9287da0 (patch)
treee40ea0b1e0c2441b5470578ca23e21ea6911c023 /drivers
parent1c614239b6f11692087f9500465803adf710122f (diff)
V4L/DVB: cx25821: fix coding style issues in cx25821-medusa-video.c
Fixes up warnings and errors found by the checkpatch.pl tool on cx25821-medusa-video.c Signed-off-by: Olimpiu Pascariu <olimpiu.pascariu@gmail.com> Acked-by: Dan Carpenter <error27@gmail.com> Cc: Palash Bandyopadhyay <palash.bandyopadhyay@conexant.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-video.c207
1 files changed, 108 insertions, 99 deletions
diff --git a/drivers/staging/cx25821/cx25821-medusa-video.c b/drivers/staging/cx25821/cx25821-medusa-video.c
index d6016200d699..0bb33ba7e99d 100644
--- a/drivers/staging/cx25821/cx25821-medusa-video.c
+++ b/drivers/staging/cx25821/cx25821-medusa-video.c
@@ -24,11 +24,12 @@
24#include "cx25821-medusa-video.h" 24#include "cx25821-medusa-video.h"
25#include "cx25821-biffuncs.h" 25#include "cx25821-biffuncs.h"
26 26
27///////////////////////////////////////////////////////////////////////////////////////// 27/*
28//medusa_enable_bluefield_output() 28 * medusa_enable_bluefield_output()
29// 29 *
30// Enable the generation of blue filed output if no video 30 * Enable the generation of blue filed output if no video
31// 31 *
32 */
32static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel, 33static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
33 int enable) 34 int enable)
34{ 35{
@@ -73,15 +74,15 @@ static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
73 } 74 }
74 75
75 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); 76 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
76 value &= 0xFFFFFF7F; // clear BLUE_FIELD_EN 77 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
77 if (enable) 78 if (enable)
78 value |= 0x00000080; // set BLUE_FIELD_EN 79 value |= 0x00000080; /* set BLUE_FIELD_EN */
79 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); 80 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
80 81
81 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); 82 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
82 value &= 0xFFFFFF7F; 83 value &= 0xFFFFFF7F;
83 if (enable) 84 if (enable)
84 value |= 0x00000080; // set BLUE_FIELD_EN 85 value |= 0x00000080; /* set BLUE_FIELD_EN */
85 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); 86 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
86} 87}
87 88
@@ -95,17 +96,18 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
95 mutex_lock(&dev->lock); 96 mutex_lock(&dev->lock);
96 97
97 for (i = 0; i < MAX_DECODERS; i++) { 98 for (i = 0; i < MAX_DECODERS; i++) {
98 // set video format NTSC-M 99 /* set video format NTSC-M */
99 value = 100 value =
100 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 101 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
101 &tmp); 102 &tmp);
102 value &= 0xFFFFFFF0; 103 value &= 0xFFFFFFF0;
103 value |= 0x10001; // enable the fast locking mode bit[16] 104 /* enable the fast locking mode bit[16] */
105 value |= 0x10001;
104 ret_val = 106 ret_val =
105 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 107 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
106 value); 108 value);
107 109
108 // resolution NTSC 720x480 110 /* resolution NTSC 720x480 */
109 value = 111 value =
110 cx25821_i2c_read(&dev->i2c_bus[0], 112 cx25821_i2c_read(&dev->i2c_bus[0],
111 HORIZ_TIM_CTRL + (0x200 * i), &tmp); 113 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
@@ -119,17 +121,17 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
119 cx25821_i2c_read(&dev->i2c_bus[0], 121 cx25821_i2c_read(&dev->i2c_bus[0],
120 VERT_TIM_CTRL + (0x200 * i), &tmp); 122 VERT_TIM_CTRL + (0x200 * i), &tmp);
121 value &= 0x00C00C00; 123 value &= 0x00C00C00;
122 value |= 0x1C1E001A; // vblank_cnt + 2 to get camera ID 124 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
123 ret_val = 125 ret_val =
124 cx25821_i2c_write(&dev->i2c_bus[0], 126 cx25821_i2c_write(&dev->i2c_bus[0],
125 VERT_TIM_CTRL + (0x200 * i), value); 127 VERT_TIM_CTRL + (0x200 * i), value);
126 128
127 // chroma subcarrier step size 129 /* chroma subcarrier step size */
128 ret_val = 130 ret_val =
129 cx25821_i2c_write(&dev->i2c_bus[0], 131 cx25821_i2c_write(&dev->i2c_bus[0],
130 SC_STEP_SIZE + (0x200 * i), 0x43E00000); 132 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
131 133
132 // enable VIP optional active 134 /* enable VIP optional active */
133 value = 135 value =
134 cx25821_i2c_read(&dev->i2c_bus[0], 136 cx25821_i2c_read(&dev->i2c_bus[0],
135 OUT_CTRL_NS + (0x200 * i), &tmp); 137 OUT_CTRL_NS + (0x200 * i), &tmp);
@@ -139,7 +141,7 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
139 cx25821_i2c_write(&dev->i2c_bus[0], 141 cx25821_i2c_write(&dev->i2c_bus[0],
140 OUT_CTRL_NS + (0x200 * i), value); 142 OUT_CTRL_NS + (0x200 * i), value);
141 143
142 // enable VIP optional active (VIP_OPT_AL) for direct output. 144 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
143 value = 145 value =
144 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 146 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
145 &tmp); 147 &tmp);
@@ -149,19 +151,21 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
149 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 151 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
150 value); 152 value);
151 153
152 // clear VPRES_VERT_EN bit, fixes the chroma run away problem 154 /*
153 // when the input switching rate < 16 fields 155 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
154 // 156 * when the input switching rate < 16 fields
157 */
155 value = 158 value =
156 cx25821_i2c_read(&dev->i2c_bus[0], 159 cx25821_i2c_read(&dev->i2c_bus[0],
157 MISC_TIM_CTRL + (0x200 * i), &tmp); 160 MISC_TIM_CTRL + (0x200 * i), &tmp);
158 value = setBitAtPos(value, 14); // disable special play detection 161 /* disable special play detection */
162 value = setBitAtPos(value, 14);
159 value = clearBitAtPos(value, 15); 163 value = clearBitAtPos(value, 15);
160 ret_val = 164 ret_val =
161 cx25821_i2c_write(&dev->i2c_bus[0], 165 cx25821_i2c_write(&dev->i2c_bus[0],
162 MISC_TIM_CTRL + (0x200 * i), value); 166 MISC_TIM_CTRL + (0x200 * i), value);
163 167
164 // set vbi_gate_en to 0 168 /* set vbi_gate_en to 0 */
165 value = 169 value =
166 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 170 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
167 &tmp); 171 &tmp);
@@ -170,12 +174,12 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
170 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 174 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
171 value); 175 value);
172 176
173 // Enable the generation of blue field output if no video 177 /* Enable the generation of blue field output if no video */
174 medusa_enable_bluefield_output(dev, i, 1); 178 medusa_enable_bluefield_output(dev, i, 1);
175 } 179 }
176 180
177 for (i = 0; i < MAX_ENCODERS; i++) { 181 for (i = 0; i < MAX_ENCODERS; i++) {
178 // NTSC hclock 182 /* NTSC hclock */
179 value = 183 value =
180 cx25821_i2c_read(&dev->i2c_bus[0], 184 cx25821_i2c_read(&dev->i2c_bus[0],
181 DENC_A_REG_1 + (0x100 * i), &tmp); 185 DENC_A_REG_1 + (0x100 * i), &tmp);
@@ -185,7 +189,7 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
185 cx25821_i2c_write(&dev->i2c_bus[0], 189 cx25821_i2c_write(&dev->i2c_bus[0],
186 DENC_A_REG_1 + (0x100 * i), value); 190 DENC_A_REG_1 + (0x100 * i), value);
187 191
188 // burst begin and burst end 192 /* burst begin and burst end */
189 value = 193 value =
190 cx25821_i2c_read(&dev->i2c_bus[0], 194 cx25821_i2c_read(&dev->i2c_bus[0],
191 DENC_A_REG_2 + (0x100 * i), &tmp); 195 DENC_A_REG_2 + (0x100 * i), &tmp);
@@ -204,7 +208,7 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
204 cx25821_i2c_write(&dev->i2c_bus[0], 208 cx25821_i2c_write(&dev->i2c_bus[0],
205 DENC_A_REG_3 + (0x100 * i), value); 209 DENC_A_REG_3 + (0x100 * i), value);
206 210
207 // set NTSC vblank, no phase alternation, 7.5 IRE pedestal 211 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
208 value = 212 value =
209 cx25821_i2c_read(&dev->i2c_bus[0], 213 cx25821_i2c_read(&dev->i2c_bus[0],
210 DENC_A_REG_4 + (0x100 * i), &tmp); 214 DENC_A_REG_4 + (0x100 * i), &tmp);
@@ -227,17 +231,19 @@ static int medusa_initialize_ntsc(struct cx25821_dev *dev)
227 cx25821_i2c_write(&dev->i2c_bus[0], 231 cx25821_i2c_write(&dev->i2c_bus[0],
228 DENC_A_REG_6 + (0x100 * i), 0x009A89C1); 232 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
229 233
230 // Subcarrier Increment 234 /* Subcarrier Increment */
231 ret_val = 235 ret_val =
232 cx25821_i2c_write(&dev->i2c_bus[0], 236 cx25821_i2c_write(&dev->i2c_bus[0],
233 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F); 237 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
234 } 238 }
235 239
236 //set picture resolutions 240 /* set picture resolutions */
237 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720 241 /* 0 - 720 */
238 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 480 242 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
243 /* 0 - 480 */
244 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
239 245
240 // set Bypass input format to NTSC 525 lines 246 /* set Bypass input format to NTSC 525 lines */
241 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 247 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
242 value |= 0x00080200; 248 value |= 0x00080200;
243 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 249 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
@@ -252,7 +258,7 @@ static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
252 int ret_val = -1; 258 int ret_val = -1;
253 u32 value = 0, tmp = 0; 259 u32 value = 0, tmp = 0;
254 260
255 // Setup for 2D threshold 261 /* Setup for 2D threshold */
256 ret_val = 262 ret_val =
257 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec), 263 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec),
258 0x20002861); 264 0x20002861);
@@ -263,7 +269,7 @@ static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
263 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec), 269 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec),
264 0x200A1023); 270 0x200A1023);
265 271
266 // Setup flat chroma and luma thresholds 272 /* Setup flat chroma and luma thresholds */
267 value = 273 value =
268 cx25821_i2c_read(&dev->i2c_bus[0], 274 cx25821_i2c_read(&dev->i2c_bus[0],
269 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp); 275 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
@@ -272,12 +278,12 @@ static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
272 cx25821_i2c_write(&dev->i2c_bus[0], 278 cx25821_i2c_write(&dev->i2c_bus[0],
273 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value); 279 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
274 280
275 // set comb 2D blend 281 /* set comb 2D blend */
276 ret_val = 282 ret_val =
277 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec), 283 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec),
278 0x210F0F0F); 284 0x210F0F0F);
279 285
280 // COMB MISC CONTROL 286 /* COMB MISC CONTROL */
281 ret_val = 287 ret_val =
282 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec), 288 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec),
283 0x41120A7F); 289 0x41120A7F);
@@ -295,17 +301,18 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
295 mutex_lock(&dev->lock); 301 mutex_lock(&dev->lock);
296 302
297 for (i = 0; i < MAX_DECODERS; i++) { 303 for (i = 0; i < MAX_DECODERS; i++) {
298 // set video format PAL-BDGHI 304 /* set video format PAL-BDGHI */
299 value = 305 value =
300 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 306 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
301 &tmp); 307 &tmp);
302 value &= 0xFFFFFFF0; 308 value &= 0xFFFFFFF0;
303 value |= 0x10004; // enable the fast locking mode bit[16] 309 /* enable the fast locking mode bit[16] */
310 value |= 0x10004;
304 ret_val = 311 ret_val =
305 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i), 312 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
306 value); 313 value);
307 314
308 // resolution PAL 720x576 315 /* resolution PAL 720x576 */
309 value = 316 value =
310 cx25821_i2c_read(&dev->i2c_bus[0], 317 cx25821_i2c_read(&dev->i2c_bus[0],
311 HORIZ_TIM_CTRL + (0x200 * i), &tmp); 318 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
@@ -315,22 +322,22 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
315 cx25821_i2c_write(&dev->i2c_bus[0], 322 cx25821_i2c_write(&dev->i2c_bus[0],
316 HORIZ_TIM_CTRL + (0x200 * i), value); 323 HORIZ_TIM_CTRL + (0x200 * i), value);
317 324
318 // vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 325 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
319 value = 326 value =
320 cx25821_i2c_read(&dev->i2c_bus[0], 327 cx25821_i2c_read(&dev->i2c_bus[0],
321 VERT_TIM_CTRL + (0x200 * i), &tmp); 328 VERT_TIM_CTRL + (0x200 * i), &tmp);
322 value &= 0x00C00C00; 329 value &= 0x00C00C00;
323 value |= 0x28240026; // vblank_cnt + 2 to get camera ID 330 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
324 ret_val = 331 ret_val =
325 cx25821_i2c_write(&dev->i2c_bus[0], 332 cx25821_i2c_write(&dev->i2c_bus[0],
326 VERT_TIM_CTRL + (0x200 * i), value); 333 VERT_TIM_CTRL + (0x200 * i), value);
327 334
328 // chroma subcarrier step size 335 /* chroma subcarrier step size */
329 ret_val = 336 ret_val =
330 cx25821_i2c_write(&dev->i2c_bus[0], 337 cx25821_i2c_write(&dev->i2c_bus[0],
331 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0); 338 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
332 339
333 // enable VIP optional active 340 /* enable VIP optional active */
334 value = 341 value =
335 cx25821_i2c_read(&dev->i2c_bus[0], 342 cx25821_i2c_read(&dev->i2c_bus[0],
336 OUT_CTRL_NS + (0x200 * i), &tmp); 343 OUT_CTRL_NS + (0x200 * i), &tmp);
@@ -340,7 +347,7 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
340 cx25821_i2c_write(&dev->i2c_bus[0], 347 cx25821_i2c_write(&dev->i2c_bus[0],
341 OUT_CTRL_NS + (0x200 * i), value); 348 OUT_CTRL_NS + (0x200 * i), value);
342 349
343 // enable VIP optional active (VIP_OPT_AL) for direct output. 350 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
344 value = 351 value =
345 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 352 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
346 &tmp); 353 &tmp);
@@ -350,18 +357,21 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
350 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i), 357 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
351 value); 358 value);
352 359
353 // clear VPRES_VERT_EN bit, fixes the chroma run away problem 360 /*
354 // when the input switching rate < 16 fields 361 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
362 * when the input switching rate < 16 fields
363 */
355 value = 364 value =
356 cx25821_i2c_read(&dev->i2c_bus[0], 365 cx25821_i2c_read(&dev->i2c_bus[0],
357 MISC_TIM_CTRL + (0x200 * i), &tmp); 366 MISC_TIM_CTRL + (0x200 * i), &tmp);
358 value = setBitAtPos(value, 14); // disable special play detection 367 /* disable special play detection */
368 value = setBitAtPos(value, 14);
359 value = clearBitAtPos(value, 15); 369 value = clearBitAtPos(value, 15);
360 ret_val = 370 ret_val =
361 cx25821_i2c_write(&dev->i2c_bus[0], 371 cx25821_i2c_write(&dev->i2c_bus[0],
362 MISC_TIM_CTRL + (0x200 * i), value); 372 MISC_TIM_CTRL + (0x200 * i), value);
363 373
364 // set vbi_gate_en to 0 374 /* set vbi_gate_en to 0 */
365 value = 375 value =
366 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i), 376 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
367 &tmp); 377 &tmp);
@@ -372,12 +382,12 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
372 382
373 medusa_PALCombInit(dev, i); 383 medusa_PALCombInit(dev, i);
374 384
375 // Enable the generation of blue field output if no video 385 /* Enable the generation of blue field output if no video */
376 medusa_enable_bluefield_output(dev, i, 1); 386 medusa_enable_bluefield_output(dev, i, 1);
377 } 387 }
378 388
379 for (i = 0; i < MAX_ENCODERS; i++) { 389 for (i = 0; i < MAX_ENCODERS; i++) {
380 // PAL hclock 390 /* PAL hclock */
381 value = 391 value =
382 cx25821_i2c_read(&dev->i2c_bus[0], 392 cx25821_i2c_read(&dev->i2c_bus[0],
383 DENC_A_REG_1 + (0x100 * i), &tmp); 393 DENC_A_REG_1 + (0x100 * i), &tmp);
@@ -387,7 +397,7 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
387 cx25821_i2c_write(&dev->i2c_bus[0], 397 cx25821_i2c_write(&dev->i2c_bus[0],
388 DENC_A_REG_1 + (0x100 * i), value); 398 DENC_A_REG_1 + (0x100 * i), value);
389 399
390 // burst begin and burst end 400 /* burst begin and burst end */
391 value = 401 value =
392 cx25821_i2c_read(&dev->i2c_bus[0], 402 cx25821_i2c_read(&dev->i2c_bus[0],
393 DENC_A_REG_2 + (0x100 * i), &tmp); 403 DENC_A_REG_2 + (0x100 * i), &tmp);
@@ -397,7 +407,7 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
397 cx25821_i2c_write(&dev->i2c_bus[0], 407 cx25821_i2c_write(&dev->i2c_bus[0],
398 DENC_A_REG_2 + (0x100 * i), value); 408 DENC_A_REG_2 + (0x100 * i), value);
399 409
400 // hblank and vactive 410 /* hblank and vactive */
401 value = 411 value =
402 cx25821_i2c_read(&dev->i2c_bus[0], 412 cx25821_i2c_read(&dev->i2c_bus[0],
403 DENC_A_REG_3 + (0x100 * i), &tmp); 413 DENC_A_REG_3 + (0x100 * i), &tmp);
@@ -407,7 +417,7 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
407 cx25821_i2c_write(&dev->i2c_bus[0], 417 cx25821_i2c_write(&dev->i2c_bus[0],
408 DENC_A_REG_3 + (0x100 * i), value); 418 DENC_A_REG_3 + (0x100 * i), value);
409 419
410 // set PAL vblank, phase alternation, 0 IRE pedestal 420 /* set PAL vblank, phase alternation, 0 IRE pedestal */
411 value = 421 value =
412 cx25821_i2c_read(&dev->i2c_bus[0], 422 cx25821_i2c_read(&dev->i2c_bus[0],
413 DENC_A_REG_4 + (0x100 * i), &tmp); 423 DENC_A_REG_4 + (0x100 * i), &tmp);
@@ -430,17 +440,19 @@ static int medusa_initialize_pal(struct cx25821_dev *dev)
430 cx25821_i2c_write(&dev->i2c_bus[0], 440 cx25821_i2c_write(&dev->i2c_bus[0],
431 DENC_A_REG_6 + (0x100 * i), 0x00A493CF); 441 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
432 442
433 // Subcarrier Increment 443 /* Subcarrier Increment */
434 ret_val = 444 ret_val =
435 cx25821_i2c_write(&dev->i2c_bus[0], 445 cx25821_i2c_write(&dev->i2c_bus[0],
436 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB); 446 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
437 } 447 }
438 448
439 //set picture resolutions 449 /* set picture resolutions */
440 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720 450 /* 0 - 720 */
441 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 576 451 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
452 /* 0 - 576 */
453 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
442 454
443 // set Bypass input format to PAL 625 lines 455 /* set Bypass input format to PAL 625 lines */
444 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 456 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
445 value &= 0xFFF7FDFF; 457 value &= 0xFFF7FDFF;
446 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 458 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
@@ -455,18 +467,17 @@ int medusa_set_videostandard(struct cx25821_dev *dev)
455 int status = STATUS_SUCCESS; 467 int status = STATUS_SUCCESS;
456 u32 value = 0, tmp = 0; 468 u32 value = 0, tmp = 0;
457 469
458 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) { 470 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
459 status = medusa_initialize_pal(dev); 471 status = medusa_initialize_pal(dev);
460 } else { 472 else
461 status = medusa_initialize_ntsc(dev); 473 status = medusa_initialize_ntsc(dev);
462 }
463 474
464 // Enable DENC_A output 475 /* Enable DENC_A output */
465 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp); 476 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
466 value = setBitAtPos(value, 4); 477 value = setBitAtPos(value, 4);
467 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value); 478 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
468 479
469 // Enable DENC_B output 480 /* Enable DENC_B output */
470 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp); 481 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
471 value = setBitAtPos(value, 4); 482 value = setBitAtPos(value, 4);
472 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value); 483 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
@@ -486,10 +497,10 @@ void medusa_set_resolution(struct cx25821_dev *dev, int width,
486 497
487 mutex_lock(&dev->lock); 498 mutex_lock(&dev->lock);
488 499
489 // validate the width - cannot be negative 500 /* validate the width - cannot be negative */
490 if (width > MAX_WIDTH) { 501 if (width > MAX_WIDTH) {
491 printk 502 printk
492 ("cx25821 %s() : width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH \n", 503 ("cx25821 %s() : width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
493 __func__, width, MAX_WIDTH); 504 __func__, width, MAX_WIDTH);
494 width = MAX_WIDTH; 505 width = MAX_WIDTH;
495 } 506 }
@@ -523,14 +534,14 @@ void medusa_set_resolution(struct cx25821_dev *dev, int width,
523 vscale = 0x1E00; 534 vscale = 0x1E00;
524 break; 535 break;
525 536
526 default: //720 537 default: /* 720 */
527 hscale = 0x0; 538 hscale = 0x0;
528 vscale = 0x0; 539 vscale = 0x0;
529 break; 540 break;
530 } 541 }
531 542
532 for (; decoder < decoder_count; decoder++) { 543 for (; decoder < decoder_count; decoder++) {
533 // write scaling values for each decoder 544 /* write scaling values for each decoder */
534 ret_val = 545 ret_val =
535 cx25821_i2c_write(&dev->i2c_bus[0], 546 cx25821_i2c_write(&dev->i2c_bus[0],
536 HSCALE_CTRL + (0x200 * decoder), hscale); 547 HSCALE_CTRL + (0x200 * decoder), hscale);
@@ -552,7 +563,7 @@ static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
552 563
553 mutex_lock(&dev->lock); 564 mutex_lock(&dev->lock);
554 565
555 // no support 566 /* no support */
556 if (decoder < VDEC_A && decoder > VDEC_H) { 567 if (decoder < VDEC_A && decoder > VDEC_H) {
557 mutex_unlock(&dev->lock); 568 mutex_unlock(&dev->lock);
558 return; 569 return;
@@ -577,11 +588,10 @@ static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
577 588
578 _display_field_cnt[decoder] = duration; 589 _display_field_cnt[decoder] = duration;
579 590
580 // update hardware 591 /* update hardware */
581 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp); 592 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
582 593
583 if (!(decoder % 2)) // EVEN decoder 594 if (!(decoder % 2)) { /* EVEN decoder */
584 {
585 fld_cnt &= 0xFFFF0000; 595 fld_cnt &= 0xFFFF0000;
586 fld_cnt |= duration; 596 fld_cnt |= duration;
587 } else { 597 } else {
@@ -594,8 +604,7 @@ static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
594 mutex_unlock(&dev->lock); 604 mutex_unlock(&dev->lock);
595} 605}
596 606
597///////////////////////////////////////////////////////////////////////////////////////// 607/* Map to Medusa register setting */
598// Map to Medusa register setting
599static int mapM(int srcMin, 608static int mapM(int srcMin,
600 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal) 609 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal)
601{ 610{
@@ -603,20 +612,21 @@ static int mapM(int srcMin,
603 int denominator; 612 int denominator;
604 int quotient; 613 int quotient;
605 614
606 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax)) { 615 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
607 return -1; 616 return -1;
608 } 617 /*
609 // This is the overall expression used: 618 * This is the overall expression used:
610 // *dstVal = (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin; 619 * *dstVal =
611 // but we need to account for rounding so below we use the modulus 620 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
612 // operator to find the remainder and increment if necessary. 621 * but we need to account for rounding so below we use the modulus
622 * operator to find the remainder and increment if necessary.
623 */
613 numerator = (srcVal - srcMin) * (dstMax - dstMin); 624 numerator = (srcVal - srcMin) * (dstMax - dstMin);
614 denominator = srcMax - srcMin; 625 denominator = srcMax - srcMin;
615 quotient = numerator / denominator; 626 quotient = numerator / denominator;
616 627
617 if (2 * (numerator % denominator) >= denominator) { 628 if (2 * (numerator % denominator) >= denominator)
618 quotient++; 629 quotient++;
619 }
620 630
621 *dstVal = quotient + dstMin; 631 *dstVal = quotient + dstMin;
622 632
@@ -636,7 +646,6 @@ static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
636 } 646 }
637} 647}
638 648
639/////////////////////////////////////////////////////////////////////////////////////////
640int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder) 649int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
641{ 650{
642 int ret_val = 0; 651 int ret_val = 0;
@@ -665,7 +674,6 @@ int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
665 return ret_val; 674 return ret_val;
666} 675}
667 676
668/////////////////////////////////////////////////////////////////////////////////////////
669int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder) 677int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
670{ 678{
671 int ret_val = 0; 679 int ret_val = 0;
@@ -695,7 +703,6 @@ int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
695 return ret_val; 703 return ret_val;
696} 704}
697 705
698/////////////////////////////////////////////////////////////////////////////////////////
699int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder) 706int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
700{ 707{
701 int ret_val = 0; 708 int ret_val = 0;
@@ -727,7 +734,6 @@ int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
727 return ret_val; 734 return ret_val;
728} 735}
729 736
730/////////////////////////////////////////////////////////////////////////////////////////
731int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder) 737int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
732{ 738{
733 int ret_val = 0; 739 int ret_val = 0;
@@ -768,9 +774,8 @@ int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
768 return ret_val; 774 return ret_val;
769} 775}
770 776
771///////////////////////////////////////////////////////////////////////////////////////// 777/* Program the display sequence and monitor output. */
772// Program the display sequence and monitor output. 778
773//
774int medusa_video_init(struct cx25821_dev *dev) 779int medusa_video_init(struct cx25821_dev *dev)
775{ 780{
776 u32 value = 0, tmp = 0; 781 u32 value = 0, tmp = 0;
@@ -781,7 +786,7 @@ int medusa_video_init(struct cx25821_dev *dev)
781 786
782 _num_decoders = dev->_max_num_decoders; 787 _num_decoders = dev->_max_num_decoders;
783 788
784 // disable Auto source selection on all video decoders 789 /* disable Auto source selection on all video decoders */
785 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); 790 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
786 value &= 0xFFFFF0FF; 791 value &= 0xFFFFF0FF;
787 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); 792 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
@@ -790,7 +795,7 @@ int medusa_video_init(struct cx25821_dev *dev)
790 mutex_unlock(&dev->lock); 795 mutex_unlock(&dev->lock);
791 return -EINVAL; 796 return -EINVAL;
792 } 797 }
793 // Turn off Master source switch enable 798 /* Turn off Master source switch enable */
794 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); 799 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
795 value &= 0xFFFFFFDF; 800 value &= 0xFFFFFFDF;
796 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); 801 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
@@ -800,32 +805,31 @@ int medusa_video_init(struct cx25821_dev *dev)
800 805
801 mutex_unlock(&dev->lock); 806 mutex_unlock(&dev->lock);
802 807
803 for (i = 0; i < _num_decoders; i++) { 808 for (i = 0; i < _num_decoders; i++)
804 medusa_set_decoderduration(dev, i, _display_field_cnt[i]); 809 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
805 }
806 810
807 mutex_lock(&dev->lock); 811 mutex_lock(&dev->lock);
808 812
809 // Select monitor as DENC A input, power up the DAC 813 /* Select monitor as DENC A input, power up the DAC */
810 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp); 814 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
811 value &= 0xFF70FF70; 815 value &= 0xFF70FF70;
812 value |= 0x00090008; // set en_active 816 value |= 0x00090008; /* set en_active */
813 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value); 817 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
814 818
815 if (ret_val < 0) { 819 if (ret_val < 0) {
816 mutex_unlock(&dev->lock); 820 mutex_unlock(&dev->lock);
817 return -EINVAL; 821 return -EINVAL;
818 } 822 }
819 // enable input is VIP/656 823 /* enable input is VIP/656 */
820 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 824 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
821 value |= 0x00040100; // enable VIP 825 value |= 0x00040100; /* enable VIP */
822 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 826 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
823 827
824 if (ret_val < 0) { 828 if (ret_val < 0) {
825 mutex_unlock(&dev->lock); 829 mutex_unlock(&dev->lock);
826 return -EINVAL; 830 return -EINVAL;
827 } 831 }
828 // select AFE clock to output mode 832 /* select AFE clock to output mode */
829 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); 833 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
830 value &= 0x83FFFFFF; 834 value &= 0x83FFFFFF;
831 ret_val = 835 ret_val =
@@ -836,15 +840,20 @@ int medusa_video_init(struct cx25821_dev *dev)
836 mutex_unlock(&dev->lock); 840 mutex_unlock(&dev->lock);
837 return -EINVAL; 841 return -EINVAL;
838 } 842 }
839 // Turn on all of the data out and control output pins. 843 /* Turn on all of the data out and control output pins. */
840 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp); 844 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
841 value &= 0xFEF0FE00; 845 value &= 0xFEF0FE00;
842 if (_num_decoders == MAX_DECODERS) { 846 if (_num_decoders == MAX_DECODERS) {
843 // Note: The octal board does not support control pins(bit16-19). 847 /*
844 // These bits are ignored in the octal board. 848 * Note: The octal board does not support control pins(bit16-19)
845 value |= 0x010001F8; // disable VDEC A-C port, default to Mobilygen Interface 849 * These bits are ignored in the octal board.
850 *
851 * disable VDEC A-C port, default to Mobilygen Interface
852 */
853 value |= 0x010001F8;
846 } else { 854 } else {
847 value |= 0x010F0108; // disable VDEC A-C port, default to Mobilygen Interface 855 /* disable VDEC A-C port, default to Mobilygen Interface */
856 value |= 0x010F0108;
848 } 857 }
849 858
850 value |= 7; 859 value |= 7;