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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-21 16:14:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-21 16:14:22 -0400
commitf234012f52a37e48f2330e1ca2df69800e797c3b (patch)
tree70547e9b3a0ec6bd87e42aa895765f27f140ef90 /drivers
parent00d94a6a5e3d6a44818e2911a4d606e28e29fecb (diff)
parent11a2f1b78a43d0c2bd026d79b952742c7588f529 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc: sdhci: remove needless double parenthesis sdhci: Specific quirk vor VIA SDHCI controller in VX855ES s3cmci: fix dma configuration call mmc: Add new via-sdmmc host controller driver sdhci: Add support for hosts that are only capable of 1-bit transfers MAINTAINERS: add myself as atmel-mci maintainer (sd/mmc interface) sdhci: Add SDHCI_QUIRK_NO_MULTIBLOCK quirk sdhci: Add better ADMA error reporting sdhci-s3c: Samsung S3C based SDHCI controller glue
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/host/Kconfig36
-rw-r--r--drivers/mmc/host/Makefile2
-rw-r--r--drivers/mmc/host/s3cmci.c2
-rw-r--r--drivers/mmc/host/sdhci-of.c3
-rw-r--r--drivers/mmc/host/sdhci-pci.c20
-rw-r--r--drivers/mmc/host/sdhci-s3c.c428
-rw-r--r--drivers/mmc/host/sdhci.c52
-rw-r--r--drivers/mmc/host/sdhci.h6
-rw-r--r--drivers/mmc/host/via-sdmmc.c1362
9 files changed, 1905 insertions, 6 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 40111a6d8d5b..891ef18bd77b 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -94,6 +94,31 @@ config MMC_SDHCI_PLTFM
94 94
95 If unsure, say N. 95 If unsure, say N.
96 96
97config MMC_SDHCI_S3C
98 tristate "SDHCI support on Samsung S3C SoC"
99 depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
100 help
101 This selects the Secure Digital Host Controller Interface (SDHCI)
102 often referrered to as the HSMMC block in some of the Samsung S3C
103 range of SoC.
104
105 Note, due to the problems with DMA, the DMA support is only
106 available with CONFIG_EXPERIMENTAL is selected.
107
108 If you have a controller with this interface, say Y or M here.
109
110 If unsure, say N.
111
112config MMC_SDHCI_S3C_DMA
113 bool "DMA support on S3C SDHCI"
114 depends on MMC_SDHCI_S3C && EXPERIMENTAL
115 help
116 Enable DMA support on the Samsung S3C SDHCI glue. The DMA
117 has proved to be problematic if the controller encounters
118 certain errors, and thus should be treated with care.
119
120 YMMV.
121
97config MMC_OMAP 122config MMC_OMAP
98 tristate "TI OMAP Multimedia Card Interface support" 123 tristate "TI OMAP Multimedia Card Interface support"
99 depends on ARCH_OMAP 124 depends on ARCH_OMAP
@@ -265,3 +290,14 @@ config MMC_CB710
265 This driver can also be built as a module. If so, the module 290 This driver can also be built as a module. If so, the module
266 will be called cb710-mmc. 291 will be called cb710-mmc.
267 292
293config MMC_VIA_SDMMC
294 tristate "VIA SD/MMC Card Reader Driver"
295 depends on PCI
296 help
297 This selects the VIA SD/MMC Card Reader driver, say Y or M here.
298 VIA provides one multi-functional card reader which integrated into
299 some motherboards manufactured by VIA. This card reader supports
300 SD/MMC/SDHC.
301 If you have a controller with this interface, say Y or M here.
302
303 If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 79da397c5fea..cf153f628457 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
15obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o 15obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o
16obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o 16obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
17obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o 17obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
18obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
18obj-$(CONFIG_MMC_WBSD) += wbsd.o 19obj-$(CONFIG_MMC_WBSD) += wbsd.o
19obj-$(CONFIG_MMC_AU1X) += au1xmmc.o 20obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
20obj-$(CONFIG_MMC_OMAP) += omap.o 21obj-$(CONFIG_MMC_OMAP) += omap.o
@@ -31,6 +32,7 @@ obj-$(CONFIG_MMC_S3C) += s3cmci.o
31obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o 32obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
32obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o 33obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
33obj-$(CONFIG_MMC_CB710) += cb710-mmc.o 34obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
35obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
34 36
35ifeq ($(CONFIG_CB710_DEBUG),y) 37ifeq ($(CONFIG_CB710_DEBUG),y)
36 CFLAGS-cb710-mmc += -DDEBUG 38 CFLAGS-cb710-mmc += -DDEBUG
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 4eb4f37544ab..8c08cd7efa7f 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -794,7 +794,7 @@ static void s3cmci_dma_setup(struct s3cmci_host *host,
794 host->mem->start + host->sdidata); 794 host->mem->start + host->sdidata);
795 795
796 if (!setup_ok) { 796 if (!setup_ok) {
797 s3c2410_dma_config(host->dma, 4, 0); 797 s3c2410_dma_config(host->dma, 4);
798 s3c2410_dma_set_buffdone_fn(host->dma, 798 s3c2410_dma_set_buffdone_fn(host->dma,
799 s3cmci_dma_done_callback); 799 s3cmci_dma_done_callback);
800 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); 800 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 128c614d11aa..d79fa55c3b89 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -250,6 +250,9 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
250 host->ops = &sdhci_of_data->ops; 250 host->ops = &sdhci_of_data->ops;
251 } 251 }
252 252
253 if (of_get_property(np, "sdhci,1-bit-only", NULL))
254 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
255
253 clk = of_get_property(np, "clock-frequency", &size); 256 clk = of_get_property(np, "clock-frequency", &size);
254 if (clk && size == sizeof(*clk) && *clk) 257 if (clk && size == sizeof(*clk) && *clk)
255 of_host->clock = *clk; 258 of_host->clock = *clk;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 65be27995d5c..2f15cc17d887 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -284,6 +284,18 @@ static const struct sdhci_pci_fixes sdhci_jmicron = {
284 .resume = jmicron_resume, 284 .resume = jmicron_resume,
285}; 285};
286 286
287static int via_probe(struct sdhci_pci_chip *chip)
288{
289 if (chip->pdev->revision == 0x10)
290 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
291
292 return 0;
293}
294
295static const struct sdhci_pci_fixes sdhci_via = {
296 .probe = via_probe,
297};
298
287static const struct pci_device_id pci_ids[] __devinitdata = { 299static const struct pci_device_id pci_ids[] __devinitdata = {
288 { 300 {
289 .vendor = PCI_VENDOR_ID_RICOH, 301 .vendor = PCI_VENDOR_ID_RICOH,
@@ -349,6 +361,14 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
349 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 361 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
350 }, 362 },
351 363
364 {
365 .vendor = PCI_VENDOR_ID_VIA,
366 .device = 0x95d0,
367 .subvendor = PCI_ANY_ID,
368 .subdevice = PCI_ANY_ID,
369 .driver_data = (kernel_ulong_t)&sdhci_via,
370 },
371
352 { /* Generic SD host controller */ 372 { /* Generic SD host controller */
353 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 373 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
354 }, 374 },
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
new file mode 100644
index 000000000000..50997d2a63e7
--- /dev/null
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -0,0 +1,428 @@
1/* linux/drivers/mmc/host/sdhci-s3c.c
2 *
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * SDHCI (HSMMC) support for Samsung SoC
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <linux/mmc/host.h>
22
23#include <plat/sdhci.h>
24#include <plat/regs-sdhci.h>
25
26#include "sdhci.h"
27
28#define MAX_BUS_CLK (4)
29
30/**
31 * struct sdhci_s3c - S3C SDHCI instance
32 * @host: The SDHCI host created
33 * @pdev: The platform device we where created from.
34 * @ioarea: The resource created when we claimed the IO area.
35 * @pdata: The platform data for this controller.
36 * @cur_clk: The index of the current bus clock.
37 * @clk_io: The clock for the internal bus interface.
38 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
39 */
40struct sdhci_s3c {
41 struct sdhci_host *host;
42 struct platform_device *pdev;
43 struct resource *ioarea;
44 struct s3c_sdhci_platdata *pdata;
45 unsigned int cur_clk;
46
47 struct clk *clk_io;
48 struct clk *clk_bus[MAX_BUS_CLK];
49};
50
51static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
52{
53 return sdhci_priv(host);
54}
55
56/**
57 * get_curclk - convert ctrl2 register to clock source number
58 * @ctrl2: Control2 register value.
59 */
60static u32 get_curclk(u32 ctrl2)
61{
62 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
63 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
64
65 return ctrl2;
66}
67
68static void sdhci_s3c_check_sclk(struct sdhci_host *host)
69{
70 struct sdhci_s3c *ourhost = to_s3c(host);
71 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
72
73 if (get_curclk(tmp) != ourhost->cur_clk) {
74 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
75
76 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
77 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
78 writel(tmp, host->ioaddr + 0x80);
79 }
80}
81
82/**
83 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
84 * @host: The SDHCI host instance.
85 *
86 * Callback to return the maximum clock rate acheivable by the controller.
87*/
88static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
89{
90 struct sdhci_s3c *ourhost = to_s3c(host);
91 struct clk *busclk;
92 unsigned int rate, max;
93 int clk;
94
95 /* note, a reset will reset the clock source */
96
97 sdhci_s3c_check_sclk(host);
98
99 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
100 busclk = ourhost->clk_bus[clk];
101 if (!busclk)
102 continue;
103
104 rate = clk_get_rate(busclk);
105 if (rate > max)
106 max = rate;
107 }
108
109 return max;
110}
111
112static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
113{
114 return sdhci_s3c_get_max_clk(host) / 1000000;
115}
116
117/**
118 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
119 * @ourhost: Our SDHCI instance.
120 * @src: The source clock index.
121 * @wanted: The clock frequency wanted.
122 */
123static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
124 unsigned int src,
125 unsigned int wanted)
126{
127 unsigned long rate;
128 struct clk *clksrc = ourhost->clk_bus[src];
129 int div;
130
131 if (!clksrc)
132 return UINT_MAX;
133
134 rate = clk_get_rate(clksrc);
135
136 for (div = 1; div < 256; div *= 2) {
137 if ((rate / div) <= wanted)
138 break;
139 }
140
141 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
142 src, rate, wanted, rate / div);
143
144 return (wanted - (rate / div));
145}
146
147/**
148 * sdhci_s3c_set_clock - callback on clock change
149 * @host: The SDHCI host being changed
150 * @clock: The clock rate being requested.
151 *
152 * When the card's clock is going to be changed, look at the new frequency
153 * and find the best clock source to go with it.
154*/
155static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
156{
157 struct sdhci_s3c *ourhost = to_s3c(host);
158 unsigned int best = UINT_MAX;
159 unsigned int delta;
160 int best_src = 0;
161 int src;
162 u32 ctrl;
163
164 /* don't bother if the clock is going off. */
165 if (clock == 0)
166 return;
167
168 for (src = 0; src < MAX_BUS_CLK; src++) {
169 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
170 if (delta < best) {
171 best = delta;
172 best_src = src;
173 }
174 }
175
176 dev_dbg(&ourhost->pdev->dev,
177 "selected source %d, clock %d, delta %d\n",
178 best_src, clock, best);
179
180 /* select the new clock source */
181
182 if (ourhost->cur_clk != best_src) {
183 struct clk *clk = ourhost->clk_bus[best_src];
184
185 /* turn clock off to card before changing clock source */
186 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
187
188 ourhost->cur_clk = best_src;
189 host->max_clk = clk_get_rate(clk);
190 host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
191
192 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
193 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
194 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
195 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
196 }
197
198 /* reconfigure the hardware for new clock rate */
199
200 {
201 struct mmc_ios ios;
202
203 ios.clock = clock;
204
205 if (ourhost->pdata->cfg_card)
206 (ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr,
207 &ios, NULL);
208 }
209}
210
211static struct sdhci_ops sdhci_s3c_ops = {
212 .get_max_clock = sdhci_s3c_get_max_clk,
213 .get_timeout_clock = sdhci_s3c_get_timeout_clk,
214 .set_clock = sdhci_s3c_set_clock,
215};
216
217static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
218{
219 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
220 struct device *dev = &pdev->dev;
221 struct sdhci_host *host;
222 struct sdhci_s3c *sc;
223 struct resource *res;
224 int ret, irq, ptr, clks;
225
226 if (!pdata) {
227 dev_err(dev, "no device data specified\n");
228 return -ENOENT;
229 }
230
231 irq = platform_get_irq(pdev, 0);
232 if (irq < 0) {
233 dev_err(dev, "no irq specified\n");
234 return irq;
235 }
236
237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
238 if (!res) {
239 dev_err(dev, "no memory specified\n");
240 return -ENOENT;
241 }
242
243 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
244 if (IS_ERR(host)) {
245 dev_err(dev, "sdhci_alloc_host() failed\n");
246 return PTR_ERR(host);
247 }
248
249 sc = sdhci_priv(host);
250
251 sc->host = host;
252 sc->pdev = pdev;
253 sc->pdata = pdata;
254
255 platform_set_drvdata(pdev, host);
256
257 sc->clk_io = clk_get(dev, "hsmmc");
258 if (IS_ERR(sc->clk_io)) {
259 dev_err(dev, "failed to get io clock\n");
260 ret = PTR_ERR(sc->clk_io);
261 goto err_io_clk;
262 }
263
264 /* enable the local io clock and keep it running for the moment. */
265 clk_enable(sc->clk_io);
266
267 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
268 struct clk *clk;
269 char *name = pdata->clocks[ptr];
270
271 if (name == NULL)
272 continue;
273
274 clk = clk_get(dev, name);
275 if (IS_ERR(clk)) {
276 dev_err(dev, "failed to get clock %s\n", name);
277 continue;
278 }
279
280 clks++;
281 sc->clk_bus[ptr] = clk;
282 clk_enable(clk);
283
284 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
285 ptr, name, clk_get_rate(clk));
286 }
287
288 if (clks == 0) {
289 dev_err(dev, "failed to find any bus clocks\n");
290 ret = -ENOENT;
291 goto err_no_busclks;
292 }
293
294 sc->ioarea = request_mem_region(res->start, resource_size(res),
295 mmc_hostname(host->mmc));
296 if (!sc->ioarea) {
297 dev_err(dev, "failed to reserve register area\n");
298 ret = -ENXIO;
299 goto err_req_regs;
300 }
301
302 host->ioaddr = ioremap_nocache(res->start, resource_size(res));
303 if (!host->ioaddr) {
304 dev_err(dev, "failed to map registers\n");
305 ret = -ENXIO;
306 goto err_req_regs;
307 }
308
309 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
310 if (pdata->cfg_gpio)
311 pdata->cfg_gpio(pdev, pdata->max_width);
312
313 host->hw_name = "samsung-hsmmc";
314 host->ops = &sdhci_s3c_ops;
315 host->quirks = 0;
316 host->irq = irq;
317
318 /* Setup quirks for the controller */
319
320 /* Currently with ADMA enabled we are getting some length
321 * interrupts that are not being dealt with, do disable
322 * ADMA until this is sorted out. */
323 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
324 host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
325
326#ifndef CONFIG_MMC_SDHCI_S3C_DMA
327
328 /* we currently see overruns on errors, so disable the SDMA
329 * support as well. */
330 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
331
332 /* PIO currently has problems with multi-block IO */
333 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
334
335#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
336
337 /* It seems we do not get an DATA transfer complete on non-busy
338 * transfers, not sure if this is a problem with this specific
339 * SDHCI block, or a missing configuration that needs to be set. */
340 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
341
342 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
343 SDHCI_QUIRK_32BIT_DMA_SIZE);
344
345 ret = sdhci_add_host(host);
346 if (ret) {
347 dev_err(dev, "sdhci_add_host() failed\n");
348 goto err_add_host;
349 }
350
351 return 0;
352
353 err_add_host:
354 release_resource(sc->ioarea);
355 kfree(sc->ioarea);
356
357 err_req_regs:
358 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
359 clk_disable(sc->clk_bus[ptr]);
360 clk_put(sc->clk_bus[ptr]);
361 }
362
363 err_no_busclks:
364 clk_disable(sc->clk_io);
365 clk_put(sc->clk_io);
366
367 err_io_clk:
368 sdhci_free_host(host);
369
370 return ret;
371}
372
373static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
374{
375 return 0;
376}
377
378#ifdef CONFIG_PM
379
380static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
381{
382 struct sdhci_host *host = platform_get_drvdata(dev);
383
384 sdhci_suspend_host(host, pm);
385 return 0;
386}
387
388static int sdhci_s3c_resume(struct platform_device *dev)
389{
390 struct sdhci_host *host = platform_get_drvdata(dev);
391
392 sdhci_resume_host(host);
393 return 0;
394}
395
396#else
397#define sdhci_s3c_suspend NULL
398#define sdhci_s3c_resume NULL
399#endif
400
401static struct platform_driver sdhci_s3c_driver = {
402 .probe = sdhci_s3c_probe,
403 .remove = __devexit_p(sdhci_s3c_remove),
404 .suspend = sdhci_s3c_suspend,
405 .resume = sdhci_s3c_resume,
406 .driver = {
407 .owner = THIS_MODULE,
408 .name = "s3c-sdhci",
409 },
410};
411
412static int __init sdhci_s3c_init(void)
413{
414 return platform_driver_register(&sdhci_s3c_driver);
415}
416
417static void __exit sdhci_s3c_exit(void)
418{
419 platform_driver_unregister(&sdhci_s3c_driver);
420}
421
422module_init(sdhci_s3c_init);
423module_exit(sdhci_s3c_exit);
424
425MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
426MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
427MODULE_LICENSE("GPL v2");
428MODULE_ALIAS("platform:s3c-sdhci");
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 35789c6edc19..6779b4ecab18 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -584,7 +584,7 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
584 * longer to time out, but that's much better than having a too-short 584 * longer to time out, but that's much better than having a too-short
585 * timeout value. 585 * timeout value.
586 */ 586 */
587 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)) 587 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
588 return 0xE; 588 return 0xE;
589 589
590 /* timeout in us */ 590 /* timeout in us */
@@ -1051,12 +1051,19 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1051 * At least the Marvell CaFe chip gets confused if we set the voltage 1051 * At least the Marvell CaFe chip gets confused if we set the voltage
1052 * and set turn on power at the same time, so set the voltage first. 1052 * and set turn on power at the same time, so set the voltage first.
1053 */ 1053 */
1054 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)) 1054 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1055 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1055 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1056 1056
1057 pwr |= SDHCI_POWER_ON; 1057 pwr |= SDHCI_POWER_ON;
1058 1058
1059 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1059 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1060
1061 /*
1062 * Some controllers need an extra 10ms delay of 10ms before they
1063 * can apply clock after applying power
1064 */
1065 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1066 mdelay(10);
1060} 1067}
1061 1068
1062/*****************************************************************************\ 1069/*****************************************************************************\
@@ -1382,6 +1389,35 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1382 sdhci_finish_command(host); 1389 sdhci_finish_command(host);
1383} 1390}
1384 1391
1392#ifdef DEBUG
1393static void sdhci_show_adma_error(struct sdhci_host *host)
1394{
1395 const char *name = mmc_hostname(host->mmc);
1396 u8 *desc = host->adma_desc;
1397 __le32 *dma;
1398 __le16 *len;
1399 u8 attr;
1400
1401 sdhci_dumpregs(host);
1402
1403 while (true) {
1404 dma = (__le32 *)(desc + 4);
1405 len = (__le16 *)(desc + 2);
1406 attr = *desc;
1407
1408 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1409 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1410
1411 desc += 8;
1412
1413 if (attr & 2)
1414 break;
1415 }
1416}
1417#else
1418static void sdhci_show_adma_error(struct sdhci_host *host) { }
1419#endif
1420
1385static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 1421static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1386{ 1422{
1387 BUG_ON(intmask == 0); 1423 BUG_ON(intmask == 0);
@@ -1411,8 +1447,11 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1411 host->data->error = -ETIMEDOUT; 1447 host->data->error = -ETIMEDOUT;
1412 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1448 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1413 host->data->error = -EILSEQ; 1449 host->data->error = -EILSEQ;
1414 else if (intmask & SDHCI_INT_ADMA_ERROR) 1450 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1451 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1452 sdhci_show_adma_error(host);
1415 host->data->error = -EIO; 1453 host->data->error = -EIO;
1454 }
1416 1455
1417 if (host->data->error) 1456 if (host->data->error)
1418 sdhci_finish_data(host); 1457 sdhci_finish_data(host);
@@ -1729,7 +1768,10 @@ int sdhci_add_host(struct sdhci_host *host)
1729 mmc->ops = &sdhci_ops; 1768 mmc->ops = &sdhci_ops;
1730 mmc->f_min = host->max_clk / 256; 1769 mmc->f_min = host->max_clk / 256;
1731 mmc->f_max = host->max_clk; 1770 mmc->f_max = host->max_clk;
1732 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1771 mmc->caps = MMC_CAP_SDIO_IRQ;
1772
1773 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1774 mmc->caps |= MMC_CAP_4_BIT_DATA;
1733 1775
1734 if (caps & SDHCI_CAN_DO_HISPD) 1776 if (caps & SDHCI_CAN_DO_HISPD)
1735 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1777 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
@@ -1802,7 +1844,7 @@ int sdhci_add_host(struct sdhci_host *host)
1802 /* 1844 /*
1803 * Maximum block count. 1845 * Maximum block count.
1804 */ 1846 */
1805 mmc->max_blk_count = 65535; 1847 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1806 1848
1807 /* 1849 /*
1808 * Init tasklets. 1850 * Init tasklets.
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 2de08349c3ca..831ddf7dcb49 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -226,6 +226,12 @@ struct sdhci_host {
226#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) 226#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
227/* Controller has to be forced to use block size of 2048 bytes */ 227/* Controller has to be forced to use block size of 2048 bytes */
228#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 228#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
229/* Controller cannot do multi-block transfers */
230#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
231/* Controller can only handle 1-bit data transfers */
232#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
233/* Controller needs 10ms delay between applying power and clock */
234#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
229 235
230 int irq; /* Device IRQ */ 236 int irq; /* Device IRQ */
231 void __iomem * ioaddr; /* Mapped address */ 237 void __iomem * ioaddr; /* Mapped address */
diff --git a/drivers/mmc/host/via-sdmmc.c b/drivers/mmc/host/via-sdmmc.c
new file mode 100644
index 000000000000..632858a94376
--- /dev/null
+++ b/drivers/mmc/host/via-sdmmc.c
@@ -0,0 +1,1362 @@
1/*
2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 */
10
11#include <linux/pci.h>
12#include <linux/dma-mapping.h>
13#include <linux/highmem.h>
14#include <linux/delay.h>
15
16#include <linux/mmc/host.h>
17
18#define DRV_NAME "via_sdmmc"
19
20#define PCI_DEVICE_ID_VIA_9530 0x9530
21
22#define VIA_CRDR_SDC_OFF 0x200
23#define VIA_CRDR_DDMA_OFF 0x400
24#define VIA_CRDR_PCICTRL_OFF 0x600
25
26#define VIA_CRDR_MIN_CLOCK 375000
27#define VIA_CRDR_MAX_CLOCK 48000000
28
29/*
30 * PCI registers
31 */
32
33#define VIA_CRDR_PCI_WORK_MODE 0x40
34#define VIA_CRDR_PCI_DBG_MODE 0x41
35
36/*
37 * SDC MMIO Registers
38 */
39
40#define VIA_CRDR_SDCTRL 0x0
41#define VIA_CRDR_SDCTRL_START 0x01
42#define VIA_CRDR_SDCTRL_WRITE 0x04
43#define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
44#define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
45#define VIA_CRDR_SDCTRL_MULTI_WR 0x30
46#define VIA_CRDR_SDCTRL_MULTI_RD 0x40
47#define VIA_CRDR_SDCTRL_STOP 0x70
48
49#define VIA_CRDR_SDCTRL_RSP_NONE 0x0
50#define VIA_CRDR_SDCTRL_RSP_R1 0x10000
51#define VIA_CRDR_SDCTRL_RSP_R2 0x20000
52#define VIA_CRDR_SDCTRL_RSP_R3 0x30000
53#define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
54
55#define VIA_CRDR_SDCARG 0x4
56
57#define VIA_CRDR_SDBUSMODE 0x8
58#define VIA_CRDR_SDMODE_4BIT 0x02
59#define VIA_CRDR_SDMODE_CLK_ON 0x40
60
61#define VIA_CRDR_SDBLKLEN 0xc
62/*
63 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
64 * Bit 11 - Bit 13 : Reserved.
65 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
66 * INTEN : Enable SD host interrupt.
67 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
68 */
69#define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
70#define VIA_CRDR_SDBLKLEN_INTEN 0x8000
71#define VIA_CRDR_MAX_BLOCK_COUNT 65536
72#define VIA_CRDR_MAX_BLOCK_LENGTH 2048
73
74#define VIA_CRDR_SDRESP0 0x10
75#define VIA_CRDR_SDRESP1 0x14
76#define VIA_CRDR_SDRESP2 0x18
77#define VIA_CRDR_SDRESP3 0x1c
78
79#define VIA_CRDR_SDCURBLKCNT 0x20
80
81#define VIA_CRDR_SDINTMASK 0x24
82/*
83 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
84 * BDDIE : Block Data transfer Done Interrupt Enable
85 * CIRIE : Card Insertion or Removal Interrupt Enable
86 * CRDIE : Command-Response transfer Done Interrupt Enable
87 * CRTOIE : Command-Response response TimeOut Interrupt Enable
88 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
89 * DTIE : Data access Timeout Interrupt Enable
90 * SCIE : reSponse CRC error Interrupt Enable
91 * RCIE : Read data CRC error Interrupt Enable
92 * WCIE : Write data CRC error Interrupt Enable
93 */
94#define VIA_CRDR_SDINTMASK_MBDIE 0x10
95#define VIA_CRDR_SDINTMASK_BDDIE 0x20
96#define VIA_CRDR_SDINTMASK_CIRIE 0x80
97#define VIA_CRDR_SDINTMASK_CRDIE 0x200
98#define VIA_CRDR_SDINTMASK_CRTOIE 0x400
99#define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
100#define VIA_CRDR_SDINTMASK_DTIE 0x1000
101#define VIA_CRDR_SDINTMASK_SCIE 0x2000
102#define VIA_CRDR_SDINTMASK_RCIE 0x4000
103#define VIA_CRDR_SDINTMASK_WCIE 0x8000
104
105#define VIA_CRDR_SDACTIVE_INTMASK \
106 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
107 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
108 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
109 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
110
111#define VIA_CRDR_SDSTATUS 0x28
112/*
113 * CECC : Reserved
114 * WP : SD card Write Protect status
115 * SLOTD : Reserved
116 * SLOTG : SD SLOT status(Gpi pin status)
117 * MBD : Multiple Blocks transfer Done interrupt status
118 * BDD : Block Data transfer Done interrupt status
119 * CD : Reserved
120 * CIR : Card Insertion or Removal interrupt detected on GPI pin
121 * IO : Reserved
122 * CRD : Command-Response transfer Done interrupt status
123 * CRTO : Command-Response response TimeOut interrupt status
124 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
125 * DT : Data access Timeout interrupt status
126 * SC : reSponse CRC error interrupt status
127 * RC : Read data CRC error interrupt status
128 * WC : Write data CRC error interrupt status
129 */
130#define VIA_CRDR_SDSTS_CECC 0x01
131#define VIA_CRDR_SDSTS_WP 0x02
132#define VIA_CRDR_SDSTS_SLOTD 0x04
133#define VIA_CRDR_SDSTS_SLOTG 0x08
134#define VIA_CRDR_SDSTS_MBD 0x10
135#define VIA_CRDR_SDSTS_BDD 0x20
136#define VIA_CRDR_SDSTS_CD 0x40
137#define VIA_CRDR_SDSTS_CIR 0x80
138#define VIA_CRDR_SDSTS_IO 0x100
139#define VIA_CRDR_SDSTS_CRD 0x200
140#define VIA_CRDR_SDSTS_CRTO 0x400
141#define VIA_CRDR_SDSTS_ASCRDIE 0x800
142#define VIA_CRDR_SDSTS_DT 0x1000
143#define VIA_CRDR_SDSTS_SC 0x2000
144#define VIA_CRDR_SDSTS_RC 0x4000
145#define VIA_CRDR_SDSTS_WC 0x8000
146
147#define VIA_CRDR_SDSTS_IGN_MASK\
148 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
149#define VIA_CRDR_SDSTS_INT_MASK \
150 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
151 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
152 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
153 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
154#define VIA_CRDR_SDSTS_W1C_MASK \
155 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
156 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
157 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
158 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
159#define VIA_CRDR_SDSTS_CMD_MASK \
160 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
161#define VIA_CRDR_SDSTS_DATA_MASK\
162 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
163 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
164
165#define VIA_CRDR_SDSTATUS2 0x2a
166/*
167 * CFE : Enable SD host automatic Clock FReezing
168 */
169#define VIA_CRDR_SDSTS_CFE 0x80
170
171#define VIA_CRDR_SDRSPTMO 0x2C
172
173#define VIA_CRDR_SDCLKSEL 0x30
174
175#define VIA_CRDR_SDEXTCTRL 0x34
176#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
177#define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
178#define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
179#define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
180#define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
181#define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
182#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
183#define VIA_CRDR_SDEXTCTRL_HISPD 0x80
184/* 0x38-0xFF reserved */
185
186/*
187 * Data DMA Control Registers
188 */
189
190#define VIA_CRDR_DMABASEADD 0x0
191#define VIA_CRDR_DMACOUNTER 0x4
192
193#define VIA_CRDR_DMACTRL 0x8
194/*
195 * DIR :Transaction Direction
196 * 0 : From card to memory
197 * 1 : From memory to card
198 */
199#define VIA_CRDR_DMACTRL_DIR 0x100
200#define VIA_CRDR_DMACTRL_ENIRQ 0x10000
201#define VIA_CRDR_DMACTRL_SFTRST 0x1000000
202
203#define VIA_CRDR_DMASTS 0xc
204
205#define VIA_CRDR_DMASTART 0x10
206/*0x14-0xFF reserved*/
207
208/*
209 * PCI Control Registers
210 */
211
212/*0x0 - 0x1 reserved*/
213#define VIA_CRDR_PCICLKGATT 0x2
214/*
215 * SFTRST :
216 * 0 : Soft reset all the controller and it will be de-asserted automatically
217 * 1 : Soft reset is de-asserted
218 */
219#define VIA_CRDR_PCICLKGATT_SFTRST 0x01
220/*
221 * 3V3 : Pad power select
222 * 0 : 1.8V
223 * 1 : 3.3V
224 * NOTE : No mater what the actual value should be, this bit always
225 * read as 0. This is a hardware bug.
226 */
227#define VIA_CRDR_PCICLKGATT_3V3 0x10
228/*
229 * PAD_PWRON : Pad Power on/off select
230 * 0 : Power off
231 * 1 : Power on
232 * NOTE : No mater what the actual value should be, this bit always
233 * read as 0. This is a hardware bug.
234 */
235#define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
236
237#define VIA_CRDR_PCISDCCLK 0x5
238
239#define VIA_CRDR_PCIDMACLK 0x7
240#define VIA_CRDR_PCIDMACLK_SDC 0x2
241
242#define VIA_CRDR_PCIINTCTRL 0x8
243#define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
244
245#define VIA_CRDR_PCIINTSTATUS 0x9
246#define VIA_CRDR_PCIINTSTATUS_SDC 0x04
247
248#define VIA_CRDR_PCITMOCTRL 0xa
249#define VIA_CRDR_PCITMOCTRL_NO 0x0
250#define VIA_CRDR_PCITMOCTRL_32US 0x1
251#define VIA_CRDR_PCITMOCTRL_256US 0x2
252#define VIA_CRDR_PCITMOCTRL_1024US 0x3
253#define VIA_CRDR_PCITMOCTRL_256MS 0x4
254#define VIA_CRDR_PCITMOCTRL_512MS 0x5
255#define VIA_CRDR_PCITMOCTRL_1024MS 0x6
256
257/*0xB-0xFF reserved*/
258
259enum PCI_HOST_CLK_CONTROL {
260 PCI_CLK_375K = 0x03,
261 PCI_CLK_8M = 0x04,
262 PCI_CLK_12M = 0x00,
263 PCI_CLK_16M = 0x05,
264 PCI_CLK_24M = 0x01,
265 PCI_CLK_33M = 0x06,
266 PCI_CLK_48M = 0x02
267};
268
269struct sdhcreg {
270 u32 sdcontrol_reg;
271 u32 sdcmdarg_reg;
272 u32 sdbusmode_reg;
273 u32 sdblklen_reg;
274 u32 sdresp_reg[4];
275 u32 sdcurblkcnt_reg;
276 u32 sdintmask_reg;
277 u32 sdstatus_reg;
278 u32 sdrsptmo_reg;
279 u32 sdclksel_reg;
280 u32 sdextctrl_reg;
281};
282
283struct pcictrlreg {
284 u8 reserve[2];
285 u8 pciclkgat_reg;
286 u8 pcinfcclk_reg;
287 u8 pcimscclk_reg;
288 u8 pcisdclk_reg;
289 u8 pcicaclk_reg;
290 u8 pcidmaclk_reg;
291 u8 pciintctrl_reg;
292 u8 pciintstatus_reg;
293 u8 pcitmoctrl_reg;
294 u8 Resv;
295};
296
297struct via_crdr_mmc_host {
298 struct mmc_host *mmc;
299 struct mmc_request *mrq;
300 struct mmc_command *cmd;
301 struct mmc_data *data;
302
303 void __iomem *mmiobase;
304 void __iomem *sdhc_mmiobase;
305 void __iomem *ddma_mmiobase;
306 void __iomem *pcictrl_mmiobase;
307
308 struct pcictrlreg pm_pcictrl_reg;
309 struct sdhcreg pm_sdhc_reg;
310
311 struct work_struct carddet_work;
312 struct tasklet_struct finish_tasklet;
313
314 struct timer_list timer;
315 spinlock_t lock;
316 u8 power;
317 int reject;
318 unsigned int quirks;
319};
320
321/* some devices need a very long delay for power to stabilize */
322#define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
323
324static struct pci_device_id via_ids[] = {
325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
327 {0,}
328};
329
330MODULE_DEVICE_TABLE(pci, via_ids);
331
332static void via_print_sdchc(struct via_crdr_mmc_host *host)
333{
334 void __iomem *addrbase = host->sdhc_mmiobase;
335
336 pr_debug("SDC MMIO Registers:\n");
337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
349}
350
351static void via_print_pcictrl(struct via_crdr_mmc_host *host)
352{
353 void __iomem *addrbase = host->pcictrl_mmiobase;
354
355 pr_debug("PCI Control Registers:\n");
356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
357 readb(addrbase + VIA_CRDR_PCICLKGATT),
358 readb(addrbase + VIA_CRDR_PCISDCCLK),
359 readb(addrbase + VIA_CRDR_PCIDMACLK));
360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
361 readb(addrbase + VIA_CRDR_PCIINTCTRL),
362 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
363}
364
365static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
366{
367 struct pcictrlreg *pm_pcictrl_reg;
368 void __iomem *addrbase;
369
370 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
371 addrbase = host->pcictrl_mmiobase;
372
373 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
374 pm_pcictrl_reg->pciclkgat_reg |=
375 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
376 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
377 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
378 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
379 pm_pcictrl_reg->pciintstatus_reg =
380 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
381 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
382}
383
384static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
385{
386 struct pcictrlreg *pm_pcictrl_reg;
387 void __iomem *addrbase;
388
389 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
390 addrbase = host->pcictrl_mmiobase;
391
392 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
393 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
394 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
395 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
396 writeb(pm_pcictrl_reg->pciintstatus_reg,
397 addrbase + VIA_CRDR_PCIINTSTATUS);
398 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
399}
400
401static void via_save_sdcreg(struct via_crdr_mmc_host *host)
402{
403 struct sdhcreg *pm_sdhc_reg;
404 void __iomem *addrbase;
405
406 pm_sdhc_reg = &(host->pm_sdhc_reg);
407 addrbase = host->sdhc_mmiobase;
408
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
410 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
411 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
412 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
413 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
414 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
415 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
416 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
417 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
418 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
419}
420
421static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
422{
423 struct sdhcreg *pm_sdhc_reg;
424 void __iomem *addrbase;
425
426 pm_sdhc_reg = &(host->pm_sdhc_reg);
427 addrbase = host->sdhc_mmiobase;
428
429 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
430 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
431 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
432 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
433 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
434 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
435 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
436 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
437 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
438 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
439}
440
441static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
442{
443 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
444 msleep(300);
445 else
446 msleep(3);
447}
448
449static void via_set_ddma(struct via_crdr_mmc_host *host,
450 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
451{
452 void __iomem *addrbase;
453 u32 ctrl_data = 0;
454
455 if (enirq)
456 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
457
458 if (dir)
459 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
460
461 addrbase = host->ddma_mmiobase;
462
463 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
464 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
465 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
466 writel(0x01, addrbase + VIA_CRDR_DMASTART);
467
468 /* It seems that our DMA can not work normally with 375kHz clock */
469 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
470 addrbase = host->pcictrl_mmiobase;
471 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
472 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
473 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
474 }
475}
476
477static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
478 struct mmc_data *data)
479{
480 void __iomem *addrbase;
481 u32 blk_reg;
482 int count;
483
484 WARN_ON(host->data);
485
486 /* Sanity checks */
487 BUG_ON(data->blksz > host->mmc->max_blk_size);
488 BUG_ON(data->blocks > host->mmc->max_blk_count);
489
490 host->data = data;
491
492 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
493 ((data->flags & MMC_DATA_READ) ?
494 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
495 BUG_ON(count != 1);
496
497 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
498 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
499
500 addrbase = host->sdhc_mmiobase;
501
502 blk_reg = data->blksz - 1;
503 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
504 blk_reg |= (data->blocks) << 16;
505
506 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
507}
508
509static void via_sdc_get_response(struct via_crdr_mmc_host *host,
510 struct mmc_command *cmd)
511{
512 void __iomem *addrbase = host->sdhc_mmiobase;
513 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
514 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
515 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
516 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
517
518 if (cmd->flags & MMC_RSP_136) {
519 cmd->resp[0] = ((u8) (dwdata1)) |
520 (((u8) (dwdata0 >> 24)) << 8) |
521 (((u8) (dwdata0 >> 16)) << 16) |
522 (((u8) (dwdata0 >> 8)) << 24);
523
524 cmd->resp[1] = ((u8) (dwdata2)) |
525 (((u8) (dwdata1 >> 24)) << 8) |
526 (((u8) (dwdata1 >> 16)) << 16) |
527 (((u8) (dwdata1 >> 8)) << 24);
528
529 cmd->resp[2] = ((u8) (dwdata3)) |
530 (((u8) (dwdata2 >> 24)) << 8) |
531 (((u8) (dwdata2 >> 16)) << 16) |
532 (((u8) (dwdata2 >> 8)) << 24);
533
534 cmd->resp[3] = 0xff |
535 ((((u8) (dwdata3 >> 24))) << 8) |
536 (((u8) (dwdata3 >> 16)) << 16) |
537 (((u8) (dwdata3 >> 8)) << 24);
538 } else {
539 dwdata0 >>= 8;
540 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
541 (((dwdata0 >> 8) & 0xff) << 16) |
542 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
543
544 dwdata1 >>= 8;
545 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
546 (((dwdata1 >> 8) & 0xff) << 16) |
547 (((dwdata1 >> 16) & 0xff) << 8);
548 }
549}
550
551static void via_sdc_send_command(struct via_crdr_mmc_host *host,
552 struct mmc_command *cmd)
553{
554 void __iomem *addrbase;
555 struct mmc_data *data;
556 u32 cmdctrl = 0;
557
558 WARN_ON(host->cmd);
559
560 data = cmd->data;
561 mod_timer(&host->timer, jiffies + HZ);
562 host->cmd = cmd;
563
564 /*Command index*/
565 cmdctrl = cmd->opcode << 8;
566
567 /*Response type*/
568 switch (mmc_resp_type(cmd)) {
569 case MMC_RSP_NONE:
570 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
571 break;
572 case MMC_RSP_R1:
573 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
574 break;
575 case MMC_RSP_R1B:
576 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
577 break;
578 case MMC_RSP_R2:
579 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
580 break;
581 case MMC_RSP_R3:
582 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
583 break;
584 default:
585 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
586 break;
587 }
588
589 if (!(cmd->data))
590 goto nodata;
591
592 via_sdc_preparedata(host, data);
593
594 /*Command control*/
595 if (data->blocks > 1) {
596 if (data->flags & MMC_DATA_WRITE) {
597 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
598 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
599 } else {
600 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
601 }
602 } else {
603 if (data->flags & MMC_DATA_WRITE) {
604 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
605 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
606 } else {
607 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
608 }
609 }
610
611nodata:
612 if (cmd == host->mrq->stop)
613 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
614
615 cmdctrl |= VIA_CRDR_SDCTRL_START;
616
617 addrbase = host->sdhc_mmiobase;
618 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
619 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
620}
621
622static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
623{
624 struct mmc_data *data;
625
626 BUG_ON(!host->data);
627
628 data = host->data;
629 host->data = NULL;
630
631 if (data->error)
632 data->bytes_xfered = 0;
633 else
634 data->bytes_xfered = data->blocks * data->blksz;
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
637 ((data->flags & MMC_DATA_READ) ?
638 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
639
640 if (data->stop)
641 via_sdc_send_command(host, data->stop);
642 else
643 tasklet_schedule(&host->finish_tasklet);
644}
645
646static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
647{
648 via_sdc_get_response(host, host->cmd);
649
650 host->cmd->error = 0;
651
652 if (!host->cmd->data)
653 tasklet_schedule(&host->finish_tasklet);
654
655 host->cmd = NULL;
656}
657
658static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
659{
660 void __iomem *addrbase;
661 struct via_crdr_mmc_host *host;
662 unsigned long flags;
663 u16 status;
664
665 host = mmc_priv(mmc);
666
667 spin_lock_irqsave(&host->lock, flags);
668
669 addrbase = host->pcictrl_mmiobase;
670 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
671
672 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
673 status &= VIA_CRDR_SDSTS_W1C_MASK;
674 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
675
676 WARN_ON(host->mrq != NULL);
677 host->mrq = mrq;
678
679 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
680 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
681 host->mrq->cmd->error = -ENOMEDIUM;
682 tasklet_schedule(&host->finish_tasklet);
683 } else {
684 via_sdc_send_command(host, mrq->cmd);
685 }
686
687 mmiowb();
688 spin_unlock_irqrestore(&host->lock, flags);
689}
690
691static void via_sdc_set_power(struct via_crdr_mmc_host *host,
692 unsigned short power, unsigned int on)
693{
694 unsigned long flags;
695 u8 gatt;
696
697 spin_lock_irqsave(&host->lock, flags);
698
699 host->power = (1 << power);
700
701 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
702 if (host->power == MMC_VDD_165_195)
703 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
704 else
705 gatt |= VIA_CRDR_PCICLKGATT_3V3;
706 if (on)
707 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
708 else
709 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
710 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
711
712 mmiowb();
713 spin_unlock_irqrestore(&host->lock, flags);
714
715 via_pwron_sleep(host);
716}
717
718static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
719{
720 struct via_crdr_mmc_host *host;
721 unsigned long flags;
722 void __iomem *addrbase;
723 u32 org_data, sdextctrl;
724 u8 clock;
725
726 host = mmc_priv(mmc);
727
728 spin_lock_irqsave(&host->lock, flags);
729
730 addrbase = host->sdhc_mmiobase;
731 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
732 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
733
734 if (ios->bus_width == MMC_BUS_WIDTH_1)
735 org_data &= ~VIA_CRDR_SDMODE_4BIT;
736 else
737 org_data |= VIA_CRDR_SDMODE_4BIT;
738
739 if (ios->power_mode == MMC_POWER_OFF)
740 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
741 else
742 org_data |= VIA_CRDR_SDMODE_CLK_ON;
743
744 if (ios->timing == MMC_TIMING_SD_HS)
745 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
746 else
747 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
748
749 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
750 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
751
752 if (ios->clock >= 48000000)
753 clock = PCI_CLK_48M;
754 else if (ios->clock >= 33000000)
755 clock = PCI_CLK_33M;
756 else if (ios->clock >= 24000000)
757 clock = PCI_CLK_24M;
758 else if (ios->clock >= 16000000)
759 clock = PCI_CLK_16M;
760 else if (ios->clock >= 12000000)
761 clock = PCI_CLK_12M;
762 else if (ios->clock >= 8000000)
763 clock = PCI_CLK_8M;
764 else
765 clock = PCI_CLK_375K;
766
767 addrbase = host->pcictrl_mmiobase;
768 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
769 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
770
771 mmiowb();
772 spin_unlock_irqrestore(&host->lock, flags);
773
774 if (ios->power_mode != MMC_POWER_OFF)
775 via_sdc_set_power(host, ios->vdd, 1);
776 else
777 via_sdc_set_power(host, ios->vdd, 0);
778}
779
780static int via_sdc_get_ro(struct mmc_host *mmc)
781{
782 struct via_crdr_mmc_host *host;
783 unsigned long flags;
784 u16 status;
785
786 host = mmc_priv(mmc);
787
788 spin_lock_irqsave(&host->lock, flags);
789
790 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
791
792 spin_unlock_irqrestore(&host->lock, flags);
793
794 return !(status & VIA_CRDR_SDSTS_WP);
795}
796
797static const struct mmc_host_ops via_sdc_ops = {
798 .request = via_sdc_request,
799 .set_ios = via_sdc_set_ios,
800 .get_ro = via_sdc_get_ro,
801};
802
803static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
804{
805 void __iomem *addrbase;
806 unsigned long flags;
807 u8 gatt;
808
809 addrbase = host->pcictrl_mmiobase;
810
811 spin_lock_irqsave(&host->lock, flags);
812
813 via_save_pcictrlreg(host);
814 via_save_sdcreg(host);
815
816 spin_unlock_irqrestore(&host->lock, flags);
817
818 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
819 if (host->power == MMC_VDD_165_195)
820 gatt &= VIA_CRDR_PCICLKGATT_3V3;
821 else
822 gatt |= VIA_CRDR_PCICLKGATT_3V3;
823 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
824 via_pwron_sleep(host);
825 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
826 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
827 msleep(3);
828
829 spin_lock_irqsave(&host->lock, flags);
830
831 via_restore_pcictrlreg(host);
832 via_restore_sdcreg(host);
833
834 mmiowb();
835 spin_unlock_irqrestore(&host->lock, flags);
836}
837
838static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
839{
840 BUG_ON(intmask == 0);
841
842 if (!host->cmd) {
843 pr_err("%s: Got command interrupt 0x%x even "
844 "though no command operation was in progress.\n",
845 mmc_hostname(host->mmc), intmask);
846 return;
847 }
848
849 if (intmask & VIA_CRDR_SDSTS_CRTO)
850 host->cmd->error = -ETIMEDOUT;
851 else if (intmask & VIA_CRDR_SDSTS_SC)
852 host->cmd->error = -EILSEQ;
853
854 if (host->cmd->error)
855 tasklet_schedule(&host->finish_tasklet);
856 else if (intmask & VIA_CRDR_SDSTS_CRD)
857 via_sdc_finish_command(host);
858}
859
860static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
861{
862 BUG_ON(intmask == 0);
863
864 if (intmask & VIA_CRDR_SDSTS_DT)
865 host->data->error = -ETIMEDOUT;
866 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
867 host->data->error = -EILSEQ;
868
869 via_sdc_finish_data(host);
870}
871
872static irqreturn_t via_sdc_isr(int irq, void *dev_id)
873{
874 struct via_crdr_mmc_host *sdhost = dev_id;
875 void __iomem *addrbase;
876 u8 pci_status;
877 u16 sd_status;
878 irqreturn_t result;
879
880 if (!sdhost)
881 return IRQ_NONE;
882
883 spin_lock(&sdhost->lock);
884
885 addrbase = sdhost->pcictrl_mmiobase;
886 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
887 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
888 result = IRQ_NONE;
889 goto out;
890 }
891
892 addrbase = sdhost->sdhc_mmiobase;
893 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
894 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
895 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
896 if (!sd_status) {
897 result = IRQ_NONE;
898 goto out;
899 }
900
901 if (sd_status & VIA_CRDR_SDSTS_CIR) {
902 writew(sd_status & VIA_CRDR_SDSTS_CIR,
903 addrbase + VIA_CRDR_SDSTATUS);
904
905 schedule_work(&sdhost->carddet_work);
906 }
907
908 sd_status &= ~VIA_CRDR_SDSTS_CIR;
909 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
910 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
911 addrbase + VIA_CRDR_SDSTATUS);
912 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
913 }
914 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
915 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
916 addrbase + VIA_CRDR_SDSTATUS);
917 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
918 }
919
920 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
921 if (sd_status) {
922 pr_err("%s: Unexpected interrupt 0x%x\n",
923 mmc_hostname(sdhost->mmc), sd_status);
924 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
925 }
926
927 result = IRQ_HANDLED;
928
929 mmiowb();
930out:
931 spin_unlock(&sdhost->lock);
932
933 return result;
934}
935
936static void via_sdc_timeout(unsigned long ulongdata)
937{
938 struct via_crdr_mmc_host *sdhost;
939 unsigned long flags;
940
941 sdhost = (struct via_crdr_mmc_host *)ulongdata;
942
943 spin_lock_irqsave(&sdhost->lock, flags);
944
945 if (sdhost->mrq) {
946 pr_err("%s: Timeout waiting for hardware interrupt."
947 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
948 sdhost->mrq->cmd->opcode);
949
950 if (sdhost->data) {
951 writel(VIA_CRDR_DMACTRL_SFTRST,
952 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
953 sdhost->data->error = -ETIMEDOUT;
954 via_sdc_finish_data(sdhost);
955 } else {
956 if (sdhost->cmd)
957 sdhost->cmd->error = -ETIMEDOUT;
958 else
959 sdhost->mrq->cmd->error = -ETIMEDOUT;
960 tasklet_schedule(&sdhost->finish_tasklet);
961 }
962 }
963
964 mmiowb();
965 spin_unlock_irqrestore(&sdhost->lock, flags);
966}
967
968static void via_sdc_tasklet_finish(unsigned long param)
969{
970 struct via_crdr_mmc_host *host;
971 unsigned long flags;
972 struct mmc_request *mrq;
973
974 host = (struct via_crdr_mmc_host *)param;
975
976 spin_lock_irqsave(&host->lock, flags);
977
978 del_timer(&host->timer);
979 mrq = host->mrq;
980 host->mrq = NULL;
981 host->cmd = NULL;
982 host->data = NULL;
983
984 spin_unlock_irqrestore(&host->lock, flags);
985
986 mmc_request_done(host->mmc, mrq);
987}
988
989static void via_sdc_card_detect(struct work_struct *work)
990{
991 struct via_crdr_mmc_host *host;
992 void __iomem *addrbase;
993 unsigned long flags;
994 u16 status;
995
996 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
997
998 addrbase = host->ddma_mmiobase;
999 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
1000
1001 spin_lock_irqsave(&host->lock, flags);
1002
1003 addrbase = host->pcictrl_mmiobase;
1004 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1005
1006 addrbase = host->sdhc_mmiobase;
1007 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1008 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1009 if (host->mrq) {
1010 pr_err("%s: Card removed during transfer!\n",
1011 mmc_hostname(host->mmc));
1012 host->mrq->cmd->error = -ENOMEDIUM;
1013 tasklet_schedule(&host->finish_tasklet);
1014 }
1015
1016 mmiowb();
1017 spin_unlock_irqrestore(&host->lock, flags);
1018
1019 via_reset_pcictrl(host);
1020
1021 spin_lock_irqsave(&host->lock, flags);
1022 }
1023
1024 mmiowb();
1025 spin_unlock_irqrestore(&host->lock, flags);
1026
1027 via_print_pcictrl(host);
1028 via_print_sdchc(host);
1029
1030 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1031}
1032
1033static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1034{
1035 struct mmc_host *mmc = host->mmc;
1036 void __iomem *addrbase;
1037 u32 lenreg;
1038 u32 status;
1039
1040 init_timer(&host->timer);
1041 host->timer.data = (unsigned long)host;
1042 host->timer.function = via_sdc_timeout;
1043
1044 spin_lock_init(&host->lock);
1045
1046 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1047 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1048 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1049 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1050 mmc->ops = &via_sdc_ops;
1051
1052 /*Hardware cannot do scatter lists*/
1053 mmc->max_hw_segs = 1;
1054 mmc->max_phys_segs = 1;
1055
1056 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1057 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1058
1059 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1060 mmc->max_req_size = mmc->max_seg_size;
1061
1062 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1063
1064 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1065 (unsigned long)host);
1066
1067 addrbase = host->sdhc_mmiobase;
1068 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1069 msleep(1);
1070
1071 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1072 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1073
1074 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1075 status &= VIA_CRDR_SDSTS_W1C_MASK;
1076 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1077
1078 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1079 status |= VIA_CRDR_SDSTS_CFE;
1080 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1081
1082 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1083
1084 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1085 msleep(1);
1086}
1087
1088static int __devinit via_sd_probe(struct pci_dev *pcidev,
1089 const struct pci_device_id *id)
1090{
1091 struct mmc_host *mmc;
1092 struct via_crdr_mmc_host *sdhost;
1093 u32 base, len;
1094 u8 rev, gatt;
1095 int ret;
1096
1097 pci_read_config_byte(pcidev, PCI_CLASS_REVISION, &rev);
1098 pr_info(DRV_NAME
1099 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1100 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1101 (int)rev);
1102
1103 ret = pci_enable_device(pcidev);
1104 if (ret)
1105 return ret;
1106
1107 ret = pci_request_regions(pcidev, DRV_NAME);
1108 if (ret)
1109 goto disable;
1110
1111 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1112 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1113
1114 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1115 if (!mmc) {
1116 ret = -ENOMEM;
1117 goto release;
1118 }
1119
1120 sdhost = mmc_priv(mmc);
1121 sdhost->mmc = mmc;
1122 dev_set_drvdata(&pcidev->dev, sdhost);
1123
1124 len = pci_resource_len(pcidev, 0);
1125 base = pci_resource_start(pcidev, 0);
1126 sdhost->mmiobase = ioremap_nocache(base, len);
1127 if (!sdhost->mmiobase) {
1128 ret = -ENOMEM;
1129 goto free_mmc_host;
1130 }
1131
1132 sdhost->sdhc_mmiobase =
1133 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1134 sdhost->ddma_mmiobase =
1135 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1136 sdhost->pcictrl_mmiobase =
1137 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1138
1139 sdhost->power = MMC_VDD_165_195;
1140
1141 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1142 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1143 via_pwron_sleep(sdhost);
1144 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1145 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1146 msleep(3);
1147
1148 via_init_mmc_host(sdhost);
1149
1150 ret =
1151 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1152 sdhost);
1153 if (ret)
1154 goto unmap;
1155
1156 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1157 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1158 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1159 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1160
1161 /* device-specific quirks */
1162 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1163 pcidev->subsystem_device == 0x3891)
1164 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1165
1166 mmc_add_host(mmc);
1167
1168 return 0;
1169
1170unmap:
1171 iounmap(sdhost->mmiobase);
1172free_mmc_host:
1173 dev_set_drvdata(&pcidev->dev, NULL);
1174 mmc_free_host(mmc);
1175release:
1176 pci_release_regions(pcidev);
1177disable:
1178 pci_disable_device(pcidev);
1179
1180 return ret;
1181}
1182
1183static void __devexit via_sd_remove(struct pci_dev *pcidev)
1184{
1185 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1186 unsigned long flags;
1187 u8 gatt;
1188
1189 spin_lock_irqsave(&sdhost->lock, flags);
1190
1191 /* Ensure we don't accept more commands from mmc layer */
1192 sdhost->reject = 1;
1193
1194 /* Disable generating further interrupts */
1195 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1196 mmiowb();
1197
1198 if (sdhost->mrq) {
1199 printk(KERN_ERR "%s: Controller removed during "
1200 "transfer\n", mmc_hostname(sdhost->mmc));
1201
1202 /* make sure all DMA is stopped */
1203 writel(VIA_CRDR_DMACTRL_SFTRST,
1204 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1205 mmiowb();
1206 sdhost->mrq->cmd->error = -ENOMEDIUM;
1207 if (sdhost->mrq->stop)
1208 sdhost->mrq->stop->error = -ENOMEDIUM;
1209 tasklet_schedule(&sdhost->finish_tasklet);
1210 }
1211 spin_unlock_irqrestore(&sdhost->lock, flags);
1212
1213 mmc_remove_host(sdhost->mmc);
1214
1215 free_irq(pcidev->irq, sdhost);
1216
1217 del_timer_sync(&sdhost->timer);
1218
1219 tasklet_kill(&sdhost->finish_tasklet);
1220
1221 /* switch off power */
1222 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1223 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1224 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1225
1226 iounmap(sdhost->mmiobase);
1227 dev_set_drvdata(&pcidev->dev, NULL);
1228 mmc_free_host(sdhost->mmc);
1229 pci_release_regions(pcidev);
1230 pci_disable_device(pcidev);
1231
1232 pr_info(DRV_NAME
1233 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1234 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1235}
1236
1237#ifdef CONFIG_PM
1238
1239static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1240{
1241 struct sdhcreg *pm_sdhcreg;
1242 void __iomem *addrbase;
1243 u32 lenreg;
1244 u16 status;
1245
1246 pm_sdhcreg = &(host->pm_sdhc_reg);
1247 addrbase = host->sdhc_mmiobase;
1248
1249 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1250
1251 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1252 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1253
1254 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1255 status &= VIA_CRDR_SDSTS_W1C_MASK;
1256 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1257
1258 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1259 status |= VIA_CRDR_SDSTS_CFE;
1260 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1261
1262 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1263 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1264 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1265 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1266 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1267 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1268
1269 via_print_pcictrl(host);
1270 via_print_sdchc(host);
1271}
1272
1273static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1274{
1275 struct via_crdr_mmc_host *host;
1276 int ret = 0;
1277
1278 host = pci_get_drvdata(pcidev);
1279
1280 via_save_pcictrlreg(host);
1281 via_save_sdcreg(host);
1282
1283 ret = mmc_suspend_host(host->mmc, state);
1284
1285 pci_save_state(pcidev);
1286 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1287 pci_disable_device(pcidev);
1288 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1289
1290 return ret;
1291}
1292
1293static int via_sd_resume(struct pci_dev *pcidev)
1294{
1295 struct via_crdr_mmc_host *sdhost;
1296 int ret = 0;
1297 u8 gatt;
1298
1299 sdhost = pci_get_drvdata(pcidev);
1300
1301 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1302 if (sdhost->power == MMC_VDD_165_195)
1303 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1304 else
1305 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1306 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1307 via_pwron_sleep(sdhost);
1308 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1309 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1310 msleep(3);
1311
1312 msleep(100);
1313
1314 pci_set_power_state(pcidev, PCI_D0);
1315 pci_restore_state(pcidev);
1316 ret = pci_enable_device(pcidev);
1317 if (ret)
1318 return ret;
1319
1320 via_restore_pcictrlreg(sdhost);
1321 via_init_sdc_pm(sdhost);
1322
1323 ret = mmc_resume_host(sdhost->mmc);
1324
1325 return ret;
1326}
1327
1328#else /* CONFIG_PM */
1329
1330#define via_sd_suspend NULL
1331#define via_sd_resume NULL
1332
1333#endif /* CONFIG_PM */
1334
1335static struct pci_driver via_sd_driver = {
1336 .name = DRV_NAME,
1337 .id_table = via_ids,
1338 .probe = via_sd_probe,
1339 .remove = __devexit_p(via_sd_remove),
1340 .suspend = via_sd_suspend,
1341 .resume = via_sd_resume,
1342};
1343
1344static int __init via_sd_drv_init(void)
1345{
1346 pr_info(DRV_NAME ": VIA SD/MMC Card Reader driver "
1347 "(C) 2008 VIA Technologies, Inc.\n");
1348
1349 return pci_register_driver(&via_sd_driver);
1350}
1351
1352static void __exit via_sd_drv_exit(void)
1353{
1354 pci_unregister_driver(&via_sd_driver);
1355}
1356
1357module_init(via_sd_drv_init);
1358module_exit(via_sd_drv_exit);
1359
1360MODULE_LICENSE("GPL");
1361MODULE_AUTHOR("VIA Technologies Inc.");
1362MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 14:26:45 -0400