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authorBruce Allan <bruce.w.allan@intel.com>2009-12-01 10:53:07 -0500
committerDavid S. Miller <davem@davemloft.net>2009-12-02 03:35:54 -0500
commit9b71b419a60d200f553658a97c9f49a46f58e8bb (patch)
treeb51e41f5fb76bc9e5a48d9169d2c21414a737372 /drivers
parent5ff5b664351a94754031c1e5783f0cea6b3000ed (diff)
e1000e: add debug messages
Add some helpful debug messages. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000e/ich8lan.c4
-rw-r--r--drivers/net/e1000e/phy.c26
2 files changed, 23 insertions, 7 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 1ce2bf97fa37..6efb77fbbd70 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -314,8 +314,10 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
314 phy->ops.write_reg = e1000e_write_phy_reg_bm; 314 phy->ops.write_reg = e1000e_write_phy_reg_bm;
315 phy->ops.read_reg = e1000e_read_phy_reg_bm; 315 phy->ops.read_reg = e1000e_read_phy_reg_bm;
316 ret_val = e1000e_determine_phy_address(hw); 316 ret_val = e1000e_determine_phy_address(hw);
317 if (ret_val) 317 if (ret_val) {
318 e_dbg("Cannot determine PHY addr. Erroring out\n");
318 return ret_val; 319 return ret_val;
320 }
319 } 321 }
320 322
321 phy->id = 0; 323 phy->id = 0;
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 1bc09b240e62..3e5940afe36d 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -2472,7 +2472,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2472 /* Gig must be disabled for MDIO accesses to page 800 */ 2472 /* Gig must be disabled for MDIO accesses to page 800 */
2473 if ((hw->mac.type == e1000_pchlan) && 2473 if ((hw->mac.type == e1000_pchlan) &&
2474 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2474 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2475 e_dbg("Attempting to access page 800 while gig enabled\n"); 2475 e_dbg("Attempting to access page 800 while gig enabled.\n");
2476 2476
2477 /* All operations in this function are phy address 1 */ 2477 /* All operations in this function are phy address 1 */
2478 hw->phy.addr = 1; 2478 hw->phy.addr = 1;
@@ -2482,20 +2482,26 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2482 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2482 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2483 2483
2484 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2484 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2485 if (ret_val) 2485 if (ret_val) {
2486 e_dbg("Could not read PHY page 769\n");
2486 goto out; 2487 goto out;
2488 }
2487 2489
2488 /* First clear bit 4 to avoid a power state change */ 2490 /* First clear bit 4 to avoid a power state change */
2489 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2491 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2490 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2492 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2491 if (ret_val) 2493 if (ret_val) {
2494 e_dbg("Could not clear PHY page 769 bit 4\n");
2492 goto out; 2495 goto out;
2496 }
2493 2497
2494 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2498 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2495 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2499 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2496 phy_reg | BM_WUC_ENABLE_BIT); 2500 phy_reg | BM_WUC_ENABLE_BIT);
2497 if (ret_val) 2501 if (ret_val) {
2502 e_dbg("Could not write PHY page 769 bit 2\n");
2498 goto out; 2503 goto out;
2504 }
2499 2505
2500 /* Select page 800 */ 2506 /* Select page 800 */
2501 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2507 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -2503,8 +2509,10 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2503 2509
2504 /* Write the page 800 offset value using opcode 0x11 */ 2510 /* Write the page 800 offset value using opcode 0x11 */
2505 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2511 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2506 if (ret_val) 2512 if (ret_val) {
2513 e_dbg("Could not write address opcode to page 800\n");
2507 goto out; 2514 goto out;
2515 }
2508 2516
2509 if (read) { 2517 if (read) {
2510 /* Read the page 800 value using opcode 0x12 */ 2518 /* Read the page 800 value using opcode 0x12 */
@@ -2516,8 +2524,10 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2516 *data); 2524 *data);
2517 } 2525 }
2518 2526
2519 if (ret_val) 2527 if (ret_val) {
2528 e_dbg("Could not access data value from page 800\n");
2520 goto out; 2529 goto out;
2530 }
2521 2531
2522 /* 2532 /*
2523 * Restore 769_17.2 to its original value 2533 * Restore 769_17.2 to its original value
@@ -2528,6 +2538,10 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2528 2538
2529 /* Clear 769_17.2 */ 2539 /* Clear 769_17.2 */
2530 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2540 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2541 if (ret_val) {
2542 e_dbg("Could not clear PHY page 769 bit 2\n");
2543 goto out;
2544 }
2531 2545
2532out: 2546out:
2533 return ret_val; 2547 return ret_val;