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authorSteven Toth <stoth@hauppauge.com>2008-05-03 13:21:58 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-05-14 01:56:40 -0400
commit90257e787faaf5ebfaa1839917e4dc6c5c104c14 (patch)
tree5fd11ab92dd50169e62ed293423a5ac7777ebd28 /drivers
parentc6c34b1ffd40e00191e05bf0ef543a35ccd7d75d (diff)
V4L/DVB(7875): mxl5005s: Remove redundant functions
Remove redundant functions Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/common/tuners/mxl5005s.c120
1 files changed, 0 insertions, 120 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 96391648871a..786f8daa6de9 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -304,7 +304,6 @@ static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
304 u8 *RegVal, int *count); 304 u8 *RegVal, int *count);
305static u32 MXL_Ceiling(u32 value, u32 resolution); 305static u32 MXL_Ceiling(u32 value, u32 resolution);
306static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); 306static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
307static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
308static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, 307static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
309 u32 value, u16 controlGroup); 308 u32 value, u16 controlGroup);
310static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); 309static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
@@ -3492,21 +3491,6 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3492 return 0 ; /* successful return */ 3491 return 0 ; /* successful return */
3493} 3492}
3494 3493
3495static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3496{
3497 struct mxl5005s_state *state = fe->tuner_priv;
3498 int i ;
3499
3500 for (i = 0; i < 104; i++) {
3501 if (RegNum == state->TunerRegs[i].Reg_Num) {
3502 state->TunerRegs[i].Reg_Val = RegVal;
3503 return 0;
3504 }
3505 }
3506
3507 return 1;
3508}
3509
3510static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) 3494static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3511{ 3495{
3512 struct mxl5005s_state *state = fe->tuner_priv; 3496 struct mxl5005s_state *state = fe->tuner_priv;
@@ -3570,92 +3554,6 @@ static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3570 return 1; 3554 return 1;
3571} 3555}
3572 3556
3573static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum,
3574 u8 *RegNum, int *count)
3575{
3576 struct mxl5005s_state *state = fe->tuner_priv;
3577 u16 i, j, k ;
3578 u16 Count ;
3579
3580 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3581
3582 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3583
3584 Count = 1;
3585 RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]);
3586
3587 for (k = 1; k < state->Init_Ctrl[i].size; k++) {
3588
3589 for (j = 0; j < Count; j++) {
3590
3591 if (state->Init_Ctrl[i].addr[k] !=
3592 RegNum[j]) {
3593
3594 Count++;
3595 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]);
3596
3597 }
3598 }
3599
3600 }
3601 *count = Count;
3602 return 0;
3603 }
3604 }
3605 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3606
3607 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3608
3609 Count = 1;
3610 RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]);
3611
3612 for (k = 1; k < state->CH_Ctrl[i].size; k++) {
3613
3614 for (j = 0; j < Count; j++) {
3615
3616 if (state->CH_Ctrl[i].addr[k] !=
3617 RegNum[j]) {
3618
3619 Count++;
3620 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]);
3621
3622 }
3623 }
3624 }
3625 *count = Count;
3626 return 0;
3627 }
3628 }
3629#ifdef _MXL_INTERNAL
3630 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3631
3632 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3633
3634 Count = 1;
3635 RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]);
3636
3637 for (k = 1; k < state->MXL_Ctrl[i].size; k++) {
3638
3639 for (j = 0; j < Count; j++) {
3640
3641 if (state->MXL_Ctrl[i].addr[k] !=
3642 RegNum[j]) {
3643
3644 Count++;
3645 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k];
3646
3647 }
3648 }
3649 }
3650 *count = Count;
3651 return 0;
3652 }
3653 }
3654#endif
3655 *count = 0;
3656 return 1;
3657}
3658
3659static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, 3557static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3660 u8 bitVal) 3558 u8 bitVal)
3661{ 3559{
@@ -3758,24 +3656,6 @@ static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3758 return status; 3656 return status;
3759} 3657}
3760 3658
3761static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum,
3762 u8 *RegVal, int *count)
3763{
3764 u16 status = 0;
3765 int i;
3766
3767 u8 RegAddr[] = { 138 };
3768
3769 *count = sizeof(RegAddr) / sizeof(u8);
3770
3771 for (i = 0; i < *count; i++) {
3772 RegNum[i] = RegAddr[i];
3773 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3774 }
3775
3776 return status;
3777}
3778
3779static u16 MXL_GetMasterControl(u8 *MasterReg, int state) 3659static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3780{ 3660{
3781 if (state == 1) /* Load_Start */ 3661 if (state == 1) /* Load_Start */