aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorEilon Greenstein <eilong@broadcom.com>2009-01-15 00:27:36 -0500
committerDavid S. Miller <davem@davemloft.net>2009-01-15 11:28:14 -0500
commit68d5948436c2f782ebb5ddf25a6588ee452e8c30 (patch)
treeb37f39931a313d18ac8acb529b1bd09d5c50d6c9 /drivers
parent0c6671b0d94f706dfc20cb22d792218ba9814412 (diff)
bnx2x: Endianness issues
Adding missing le_to_cpu and disabling wrong HW endianity flag (the two complete each other) Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x_main.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index ca8b25126b22..d2350dd300b2 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -1438,7 +1438,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1438 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x" 1438 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
1439 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags), 1439 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags),
1440 cqe_fp_flags, cqe->fast_path_cqe.status_flags, 1440 cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1441 cqe->fast_path_cqe.rss_hash_result, 1441 le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1442 le16_to_cpu(cqe->fast_path_cqe.vlan_tag), 1442 le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1443 le16_to_cpu(cqe->fast_path_cqe.pkt_len)); 1443 le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1444 1444
@@ -2821,8 +2821,10 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2821static void bnx2x_attn_int(struct bnx2x *bp) 2821static void bnx2x_attn_int(struct bnx2x *bp)
2822{ 2822{
2823 /* read local copy of bits */ 2823 /* read local copy of bits */
2824 u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits; 2824 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2825 u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack; 2825 attn_bits);
2826 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2827 attn_bits_ack);
2826 u32 attn_state = bp->attn_state; 2828 u32 attn_state = bp->attn_state;
2827 2829
2828 /* look for changed bits */ 2830 /* look for changed bits */
@@ -2870,7 +2872,7 @@ static void bnx2x_sp_task(struct work_struct *work)
2870 if (status & 0x2) 2872 if (status & 0x2)
2871 bp->stats_pending = 0; 2873 bp->stats_pending = 0;
2872 2874
2873 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx, 2875 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2874 IGU_INT_NOP, 1); 2876 IGU_INT_NOP, 1);
2875 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx), 2877 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2876 IGU_INT_NOP, 1); 2878 IGU_INT_NOP, 1);
@@ -5161,7 +5163,6 @@ static int bnx2x_init_common(struct bnx2x *bp)
5161 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 5163 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5162 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 5164 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5163 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 5165 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5164 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 1);
5165 5166
5166/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 5167/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5167 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 5168 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);