diff options
author | Michael Chan <mchan@broadcom.com> | 2005-04-21 20:11:21 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2005-04-21 20:11:21 -0400 |
commit | 361b4ac29bc651c7612d4bf21434ae6fe06b78e4 (patch) | |
tree | a0d1b0a7f89a7d45c63b269bef5eeacf6f8dc734 /drivers | |
parent | 3e7d83bc96d59013792e5546e7832668d3adbce7 (diff) |
[TG3]: Add nvram detection for 5752
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/tg3.c | 63 | ||||
-rw-r--r-- | drivers/net/tg3.h | 14 |
2 files changed, 76 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a94631af21cd..dbdd3ecafdc1 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -7096,6 +7096,63 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |||
7096 | } | 7096 | } |
7097 | } | 7097 | } |
7098 | 7098 | ||
7099 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) | ||
7100 | { | ||
7101 | u32 nvcfg1; | ||
7102 | |||
7103 | nvcfg1 = tr32(NVRAM_CFG1); | ||
7104 | |||
7105 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | ||
7106 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: | ||
7107 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | ||
7108 | tp->nvram_jedecnum = JEDEC_ATMEL; | ||
7109 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | ||
7110 | break; | ||
7111 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | ||
7112 | tp->nvram_jedecnum = JEDEC_ATMEL; | ||
7113 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | ||
7114 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | ||
7115 | break; | ||
7116 | case FLASH_5752VENDOR_ST_M45PE10: | ||
7117 | case FLASH_5752VENDOR_ST_M45PE20: | ||
7118 | case FLASH_5752VENDOR_ST_M45PE40: | ||
7119 | tp->nvram_jedecnum = JEDEC_ST; | ||
7120 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | ||
7121 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | ||
7122 | break; | ||
7123 | } | ||
7124 | |||
7125 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | ||
7126 | switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | ||
7127 | case FLASH_5752PAGE_SIZE_256: | ||
7128 | tp->nvram_pagesize = 256; | ||
7129 | break; | ||
7130 | case FLASH_5752PAGE_SIZE_512: | ||
7131 | tp->nvram_pagesize = 512; | ||
7132 | break; | ||
7133 | case FLASH_5752PAGE_SIZE_1K: | ||
7134 | tp->nvram_pagesize = 1024; | ||
7135 | break; | ||
7136 | case FLASH_5752PAGE_SIZE_2K: | ||
7137 | tp->nvram_pagesize = 2048; | ||
7138 | break; | ||
7139 | case FLASH_5752PAGE_SIZE_4K: | ||
7140 | tp->nvram_pagesize = 4096; | ||
7141 | break; | ||
7142 | case FLASH_5752PAGE_SIZE_264: | ||
7143 | tp->nvram_pagesize = 264; | ||
7144 | break; | ||
7145 | } | ||
7146 | } | ||
7147 | else { | ||
7148 | /* For eeprom, set pagesize to maximum eeprom size */ | ||
7149 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | ||
7150 | |||
7151 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | ||
7152 | tw32(NVRAM_CFG1, nvcfg1); | ||
7153 | } | ||
7154 | } | ||
7155 | |||
7099 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ | 7156 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
7100 | static void __devinit tg3_nvram_init(struct tg3 *tp) | 7157 | static void __devinit tg3_nvram_init(struct tg3 *tp) |
7101 | { | 7158 | { |
@@ -7128,7 +7185,11 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) | |||
7128 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | 7185 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); |
7129 | } | 7186 | } |
7130 | 7187 | ||
7131 | tg3_get_nvram_info(tp); | 7188 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
7189 | tg3_get_5752_nvram_info(tp); | ||
7190 | else | ||
7191 | tg3_get_nvram_info(tp); | ||
7192 | |||
7132 | tg3_get_nvram_size(tp); | 7193 | tg3_get_nvram_size(tp); |
7133 | 7194 | ||
7134 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | 7195 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 548f469e9500..261c2db7ce17 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -1399,6 +1399,20 @@ | |||
1399 | #define FLASH_VENDOR_SAIFUN 0x01000003 | 1399 | #define FLASH_VENDOR_SAIFUN 0x01000003 |
1400 | #define FLASH_VENDOR_SST_SMALL 0x00000001 | 1400 | #define FLASH_VENDOR_SST_SMALL 0x00000001 |
1401 | #define FLASH_VENDOR_SST_LARGE 0x02000001 | 1401 | #define FLASH_VENDOR_SST_LARGE 0x02000001 |
1402 | #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 | ||
1403 | #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 | ||
1404 | #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 | ||
1405 | #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 | ||
1406 | #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 | ||
1407 | #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 | ||
1408 | #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 | ||
1409 | #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 | ||
1410 | #define FLASH_5752PAGE_SIZE_256 0x00000000 | ||
1411 | #define FLASH_5752PAGE_SIZE_512 0x10000000 | ||
1412 | #define FLASH_5752PAGE_SIZE_1K 0x20000000 | ||
1413 | #define FLASH_5752PAGE_SIZE_2K 0x30000000 | ||
1414 | #define FLASH_5752PAGE_SIZE_4K 0x40000000 | ||
1415 | #define FLASH_5752PAGE_SIZE_264 0x50000000 | ||
1402 | #define NVRAM_CFG2 0x00007018 | 1416 | #define NVRAM_CFG2 0x00007018 |
1403 | #define NVRAM_CFG3 0x0000701c | 1417 | #define NVRAM_CFG3 0x0000701c |
1404 | #define NVRAM_SWARB 0x00007020 | 1418 | #define NVRAM_SWARB 0x00007020 |