diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-12-03 11:14:45 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-12-03 11:14:45 -0500 |
commit | d894f4510d2155f9136c8c1bb91912481329f6e0 (patch) | |
tree | 442f30ec38d6cf9e7621f08f5a4f443037594815 /drivers | |
parent | 4200b66cbf6f4970dd7e192cc929cbccae12a4ca (diff) | |
parent | 02a121da5a53d415b6596bc19cc6999d295d32a4 (diff) |
Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
sata_mv: Fix broken Marvell 7042 support.
libata: Fix early use of port printk. (Was Re: ata4294967295: failed to start port (errno=-19))
ata_piix: add more toshiba laptops to broken suspend list
libata: More IVB horkage from TSST
libata: report protocol and full CDB on error
Several fixes for the AVR32 PATA driver
sata_mv: fix compilation error when enabling DEBUG
Set proper ATA UDMA mode for bf548 according to system clock.
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/ata/ata_piix.c | 28 | ||||
-rw-r--r-- | drivers/ata/libata-core.c | 8 | ||||
-rw-r--r-- | drivers/ata/libata-eh.c | 42 | ||||
-rw-r--r-- | drivers/ata/pata_at32.c | 61 | ||||
-rw-r--r-- | drivers/ata/pata_bf54x.c | 7 | ||||
-rw-r--r-- | drivers/ata/sata_mv.c | 64 |
6 files changed, 149 insertions, 61 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 483269db2c7d..b538e1d22bf2 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
@@ -967,6 +967,13 @@ static int piix_broken_suspend(void) | |||
967 | }, | 967 | }, |
968 | }, | 968 | }, |
969 | { | 969 | { |
970 | .ident = "TECRA M3", | ||
971 | .matches = { | ||
972 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
973 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), | ||
974 | }, | ||
975 | }, | ||
976 | { | ||
970 | .ident = "TECRA M5", | 977 | .ident = "TECRA M5", |
971 | .matches = { | 978 | .matches = { |
972 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | 979 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
@@ -981,6 +988,20 @@ static int piix_broken_suspend(void) | |||
981 | }, | 988 | }, |
982 | }, | 989 | }, |
983 | { | 990 | { |
991 | .ident = "TECRA A8", | ||
992 | .matches = { | ||
993 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
994 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), | ||
995 | }, | ||
996 | }, | ||
997 | { | ||
998 | .ident = "Satellite R25", | ||
999 | .matches = { | ||
1000 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
1001 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), | ||
1002 | }, | ||
1003 | }, | ||
1004 | { | ||
984 | .ident = "Satellite U200", | 1005 | .ident = "Satellite U200", |
985 | .matches = { | 1006 | .matches = { |
986 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | 1007 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
@@ -988,6 +1009,13 @@ static int piix_broken_suspend(void) | |||
988 | }, | 1009 | }, |
989 | }, | 1010 | }, |
990 | { | 1011 | { |
1012 | .ident = "Satellite U200", | ||
1013 | .matches = { | ||
1014 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
1015 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), | ||
1016 | }, | ||
1017 | }, | ||
1018 | { | ||
991 | .ident = "Satellite Pro U200", | 1019 | .ident = "Satellite Pro U200", |
992 | .matches = { | 1020 | .matches = { |
993 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | 1021 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 33f06277b3be..b514a80f1370 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c | |||
@@ -4185,6 +4185,9 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { | |||
4185 | /* Devices which get the IVB wrong */ | 4185 | /* Devices which get the IVB wrong */ |
4186 | { "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, }, | 4186 | { "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, }, |
4187 | { "TSSTcorp CDDVDW SH-S202J", "SB00", ATA_HORKAGE_IVB, }, | 4187 | { "TSSTcorp CDDVDW SH-S202J", "SB00", ATA_HORKAGE_IVB, }, |
4188 | { "TSSTcorp CDDVDW SH-S202J", "SB01", ATA_HORKAGE_IVB, }, | ||
4189 | { "TSSTcorp CDDVDW SH-S202N", "SB00", ATA_HORKAGE_IVB, }, | ||
4190 | { "TSSTcorp CDDVDW SH-S202N", "SB01", ATA_HORKAGE_IVB, }, | ||
4188 | 4191 | ||
4189 | /* End Marker */ | 4192 | /* End Marker */ |
4190 | { } | 4193 | { } |
@@ -6964,12 +6967,11 @@ int ata_host_start(struct ata_host *host) | |||
6964 | if (ap->ops->port_start) { | 6967 | if (ap->ops->port_start) { |
6965 | rc = ap->ops->port_start(ap); | 6968 | rc = ap->ops->port_start(ap); |
6966 | if (rc) { | 6969 | if (rc) { |
6967 | ata_port_printk(ap, KERN_ERR, "failed to " | 6970 | if (rc != -ENODEV) |
6968 | "start port (errno=%d)\n", rc); | 6971 | dev_printk(KERN_ERR, host->dev, "failed to start port %d (errno=%d)\n", i, rc); |
6969 | goto err_out; | 6972 | goto err_out; |
6970 | } | 6973 | } |
6971 | } | 6974 | } |
6972 | |||
6973 | ata_eh_freeze_port(ap); | 6975 | ata_eh_freeze_port(ap); |
6974 | } | 6976 | } |
6975 | 6977 | ||
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index 0dac69db1fdf..e6605f038647 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c | |||
@@ -1850,30 +1850,54 @@ static void ata_eh_link_report(struct ata_link *link) | |||
1850 | ehc->i.serror & SERR_DEV_XCHG ? "DevExch " : ""); | 1850 | ehc->i.serror & SERR_DEV_XCHG ? "DevExch " : ""); |
1851 | 1851 | ||
1852 | for (tag = 0; tag < ATA_MAX_QUEUE; tag++) { | 1852 | for (tag = 0; tag < ATA_MAX_QUEUE; tag++) { |
1853 | static const char *dma_str[] = { | ||
1854 | [DMA_BIDIRECTIONAL] = "bidi", | ||
1855 | [DMA_TO_DEVICE] = "out", | ||
1856 | [DMA_FROM_DEVICE] = "in", | ||
1857 | [DMA_NONE] = "", | ||
1858 | }; | ||
1859 | struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag); | 1853 | struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag); |
1860 | struct ata_taskfile *cmd = &qc->tf, *res = &qc->result_tf; | 1854 | struct ata_taskfile *cmd = &qc->tf, *res = &qc->result_tf; |
1855 | const u8 *cdb = qc->cdb; | ||
1856 | char data_buf[20] = ""; | ||
1857 | char cdb_buf[70] = ""; | ||
1861 | 1858 | ||
1862 | if (!(qc->flags & ATA_QCFLAG_FAILED) || | 1859 | if (!(qc->flags & ATA_QCFLAG_FAILED) || |
1863 | qc->dev->link != link || !qc->err_mask) | 1860 | qc->dev->link != link || !qc->err_mask) |
1864 | continue; | 1861 | continue; |
1865 | 1862 | ||
1863 | if (qc->dma_dir != DMA_NONE) { | ||
1864 | static const char *dma_str[] = { | ||
1865 | [DMA_BIDIRECTIONAL] = "bidi", | ||
1866 | [DMA_TO_DEVICE] = "out", | ||
1867 | [DMA_FROM_DEVICE] = "in", | ||
1868 | }; | ||
1869 | static const char *prot_str[] = { | ||
1870 | [ATA_PROT_PIO] = "pio", | ||
1871 | [ATA_PROT_DMA] = "dma", | ||
1872 | [ATA_PROT_NCQ] = "ncq", | ||
1873 | [ATA_PROT_ATAPI] = "pio", | ||
1874 | [ATA_PROT_ATAPI_DMA] = "dma", | ||
1875 | }; | ||
1876 | |||
1877 | snprintf(data_buf, sizeof(data_buf), " %s %u %s", | ||
1878 | prot_str[qc->tf.protocol], qc->nbytes, | ||
1879 | dma_str[qc->dma_dir]); | ||
1880 | } | ||
1881 | |||
1882 | if (is_atapi_taskfile(&qc->tf)) | ||
1883 | snprintf(cdb_buf, sizeof(cdb_buf), | ||
1884 | "cdb %02x %02x %02x %02x %02x %02x %02x %02x " | ||
1885 | "%02x %02x %02x %02x %02x %02x %02x %02x\n ", | ||
1886 | cdb[0], cdb[1], cdb[2], cdb[3], | ||
1887 | cdb[4], cdb[5], cdb[6], cdb[7], | ||
1888 | cdb[8], cdb[9], cdb[10], cdb[11], | ||
1889 | cdb[12], cdb[13], cdb[14], cdb[15]); | ||
1890 | |||
1866 | ata_dev_printk(qc->dev, KERN_ERR, | 1891 | ata_dev_printk(qc->dev, KERN_ERR, |
1867 | "cmd %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x " | 1892 | "cmd %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x " |
1868 | "tag %d cdb 0x%x data %u %s\n " | 1893 | "tag %d%s\n %s" |
1869 | "res %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x " | 1894 | "res %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x " |
1870 | "Emask 0x%x (%s)%s\n", | 1895 | "Emask 0x%x (%s)%s\n", |
1871 | cmd->command, cmd->feature, cmd->nsect, | 1896 | cmd->command, cmd->feature, cmd->nsect, |
1872 | cmd->lbal, cmd->lbam, cmd->lbah, | 1897 | cmd->lbal, cmd->lbam, cmd->lbah, |
1873 | cmd->hob_feature, cmd->hob_nsect, | 1898 | cmd->hob_feature, cmd->hob_nsect, |
1874 | cmd->hob_lbal, cmd->hob_lbam, cmd->hob_lbah, | 1899 | cmd->hob_lbal, cmd->hob_lbam, cmd->hob_lbah, |
1875 | cmd->device, qc->tag, qc->cdb[0], qc->nbytes, | 1900 | cmd->device, qc->tag, data_buf, cdb_buf, |
1876 | dma_str[qc->dma_dir], | ||
1877 | res->command, res->feature, res->nsect, | 1901 | res->command, res->feature, res->nsect, |
1878 | res->lbal, res->lbam, res->lbah, | 1902 | res->lbal, res->lbam, res->lbah, |
1879 | res->hob_feature, res->hob_nsect, | 1903 | res->hob_feature, res->hob_nsect, |
diff --git a/drivers/ata/pata_at32.c b/drivers/ata/pata_at32.c index bb250a48e27c..67e574de31e8 100644 --- a/drivers/ata/pata_at32.c +++ b/drivers/ata/pata_at32.c | |||
@@ -28,7 +28,7 @@ | |||
28 | #include <asm/arch/smc.h> | 28 | #include <asm/arch/smc.h> |
29 | 29 | ||
30 | #define DRV_NAME "pata_at32" | 30 | #define DRV_NAME "pata_at32" |
31 | #define DRV_VERSION "0.0.2" | 31 | #define DRV_VERSION "0.0.3" |
32 | 32 | ||
33 | /* | 33 | /* |
34 | * CompactFlash controller memory layout relative to the base address: | 34 | * CompactFlash controller memory layout relative to the base address: |
@@ -64,6 +64,8 @@ | |||
64 | * Mode 2 | 8.3 | 240 ns | 0x07 | 64 | * Mode 2 | 8.3 | 240 ns | 0x07 |
65 | * Mode 3 | 11.1 | 180 ns | 0x0f | 65 | * Mode 3 | 11.1 | 180 ns | 0x0f |
66 | * Mode 4 | 16.7 | 120 ns | 0x1f | 66 | * Mode 4 | 16.7 | 120 ns | 0x1f |
67 | * | ||
68 | * Alter PIO_MASK below according to table to set maximal PIO mode. | ||
67 | */ | 69 | */ |
68 | #define PIO_MASK (0x1f) | 70 | #define PIO_MASK (0x1f) |
69 | 71 | ||
@@ -85,36 +87,40 @@ struct at32_ide_info { | |||
85 | */ | 87 | */ |
86 | static int pata_at32_setup_timing(struct device *dev, | 88 | static int pata_at32_setup_timing(struct device *dev, |
87 | struct at32_ide_info *info, | 89 | struct at32_ide_info *info, |
88 | const struct ata_timing *timing) | 90 | const struct ata_timing *ata) |
89 | { | 91 | { |
90 | /* These two values are found through testing */ | ||
91 | const int min_recover = 25; | ||
92 | const int ncs_hold = 15; | ||
93 | |||
94 | struct smc_config *smc = &info->smc; | 92 | struct smc_config *smc = &info->smc; |
93 | struct smc_timing timing; | ||
95 | 94 | ||
96 | int active; | 95 | int active; |
97 | int recover; | 96 | int recover; |
98 | 97 | ||
98 | memset(&timing, 0, sizeof(struct smc_timing)); | ||
99 | |||
99 | /* Total cycle time */ | 100 | /* Total cycle time */ |
100 | smc->read_cycle = timing->cyc8b; | 101 | timing.read_cycle = ata->cyc8b; |
101 | 102 | ||
102 | /* DIOR <= CFIOR timings */ | 103 | /* DIOR <= CFIOR timings */ |
103 | smc->nrd_setup = timing->setup; | 104 | timing.nrd_setup = ata->setup; |
104 | smc->nrd_pulse = timing->act8b; | 105 | timing.nrd_pulse = ata->act8b; |
106 | timing.nrd_recover = ata->rec8b; | ||
107 | |||
108 | /* Convert nanosecond timing to clock cycles */ | ||
109 | smc_set_timing(smc, &timing); | ||
105 | 110 | ||
106 | /* Compute recover, extend total cycle if needed */ | 111 | /* Add one extra cycle setup due to signal ring */ |
107 | active = smc->nrd_setup + smc->nrd_pulse; | 112 | smc->nrd_setup = smc->nrd_setup + 1; |
113 | |||
114 | active = smc->nrd_setup + smc->nrd_pulse; | ||
108 | recover = smc->read_cycle - active; | 115 | recover = smc->read_cycle - active; |
109 | 116 | ||
110 | if (recover < min_recover) { | 117 | /* Need at least two cycles recovery */ |
111 | smc->read_cycle = active + min_recover; | 118 | if (recover < 2) |
112 | recover = min_recover; | 119 | smc->read_cycle = active + 2; |
113 | } | ||
114 | 120 | ||
115 | /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */ | 121 | /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */ |
116 | smc->ncs_read_setup = 0; | 122 | smc->ncs_read_setup = 1; |
117 | smc->ncs_read_pulse = active + ncs_hold; | 123 | smc->ncs_read_pulse = smc->read_cycle - 2; |
118 | 124 | ||
119 | /* Write timings same as read timings */ | 125 | /* Write timings same as read timings */ |
120 | smc->write_cycle = smc->read_cycle; | 126 | smc->write_cycle = smc->read_cycle; |
@@ -123,11 +129,13 @@ static int pata_at32_setup_timing(struct device *dev, | |||
123 | smc->ncs_write_setup = smc->ncs_read_setup; | 129 | smc->ncs_write_setup = smc->ncs_read_setup; |
124 | smc->ncs_write_pulse = smc->ncs_read_pulse; | 130 | smc->ncs_write_pulse = smc->ncs_read_pulse; |
125 | 131 | ||
126 | /* Do some debugging output */ | 132 | /* Do some debugging output of ATA and SMC timings */ |
127 | dev_dbg(dev, "SMC: C=%d S=%d P=%d R=%d NCSS=%d NCSP=%d NCSR=%d\n", | 133 | dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n", |
134 | ata->cyc8b, ata->setup, ata->act8b, ata->rec8b); | ||
135 | |||
136 | dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n", | ||
128 | smc->read_cycle, smc->nrd_setup, smc->nrd_pulse, | 137 | smc->read_cycle, smc->nrd_setup, smc->nrd_pulse, |
129 | recover, smc->ncs_read_setup, smc->ncs_read_pulse, | 138 | smc->ncs_read_setup, smc->ncs_read_pulse); |
130 | smc->read_cycle - smc->ncs_read_pulse); | ||
131 | 139 | ||
132 | /* Finally, configure the SMC */ | 140 | /* Finally, configure the SMC */ |
133 | return smc_set_configuration(info->cs, smc); | 141 | return smc_set_configuration(info->cs, smc); |
@@ -182,7 +190,6 @@ static struct scsi_host_template at32_sht = { | |||
182 | }; | 190 | }; |
183 | 191 | ||
184 | static struct ata_port_operations at32_port_ops = { | 192 | static struct ata_port_operations at32_port_ops = { |
185 | .port_disable = ata_port_disable, | ||
186 | .set_piomode = pata_at32_set_piomode, | 193 | .set_piomode = pata_at32_set_piomode, |
187 | .tf_load = ata_tf_load, | 194 | .tf_load = ata_tf_load, |
188 | .tf_read = ata_tf_read, | 195 | .tf_read = ata_tf_read, |
@@ -203,7 +210,6 @@ static struct ata_port_operations at32_port_ops = { | |||
203 | 210 | ||
204 | .irq_clear = pata_at32_irq_clear, | 211 | .irq_clear = pata_at32_irq_clear, |
205 | .irq_on = ata_irq_on, | 212 | .irq_on = ata_irq_on, |
206 | .irq_ack = ata_irq_ack, | ||
207 | 213 | ||
208 | .port_start = ata_sff_port_start, | 214 | .port_start = ata_sff_port_start, |
209 | }; | 215 | }; |
@@ -223,8 +229,7 @@ static int __init pata_at32_init_one(struct device *dev, | |||
223 | /* Setup ATA bindings */ | 229 | /* Setup ATA bindings */ |
224 | ap->ops = &at32_port_ops; | 230 | ap->ops = &at32_port_ops; |
225 | ap->pio_mask = PIO_MASK; | 231 | ap->pio_mask = PIO_MASK; |
226 | ap->flags = ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS | 232 | ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS; |
227 | | ATA_FLAG_PIO_POLLING; | ||
228 | 233 | ||
229 | /* | 234 | /* |
230 | * Since all 8-bit taskfile transfers has to go on the lower | 235 | * Since all 8-bit taskfile transfers has to go on the lower |
@@ -357,12 +362,12 @@ static int __init pata_at32_probe(struct platform_device *pdev) | |||
357 | info->smc.tdf_mode = 0; /* TDF optimization disabled */ | 362 | info->smc.tdf_mode = 0; /* TDF optimization disabled */ |
358 | info->smc.tdf_cycles = 0; /* No TDF wait cycles */ | 363 | info->smc.tdf_cycles = 0; /* No TDF wait cycles */ |
359 | 364 | ||
360 | /* Setup ATA timing */ | 365 | /* Setup SMC to ATA timing */ |
361 | ret = pata_at32_setup_timing(dev, info, &initial_timing); | 366 | ret = pata_at32_setup_timing(dev, info, &initial_timing); |
362 | if (ret) | 367 | if (ret) |
363 | goto err_setup_timing; | 368 | goto err_setup_timing; |
364 | 369 | ||
365 | /* Setup ATA addresses */ | 370 | /* Map ATA address space */ |
366 | ret = -ENOMEM; | 371 | ret = -ENOMEM; |
367 | info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16); | 372 | info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16); |
368 | info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16); | 373 | info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16); |
@@ -373,7 +378,7 @@ static int __init pata_at32_probe(struct platform_device *pdev) | |||
373 | pata_at32_debug_bus(dev, info); | 378 | pata_at32_debug_bus(dev, info); |
374 | #endif | 379 | #endif |
375 | 380 | ||
376 | /* Register ATA device */ | 381 | /* Setup and register ATA device */ |
377 | ret = pata_at32_init_one(dev, info); | 382 | ret = pata_at32_init_one(dev, info); |
378 | if (ret) | 383 | if (ret) |
379 | goto err_ata_device; | 384 | goto err_ata_device; |
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c index 81db405a5445..088a41f4e656 100644 --- a/drivers/ata/pata_bf54x.c +++ b/drivers/ata/pata_bf54x.c | |||
@@ -1489,6 +1489,8 @@ static int __devinit bfin_atapi_probe(struct platform_device *pdev) | |||
1489 | int board_idx = 0; | 1489 | int board_idx = 0; |
1490 | struct resource *res; | 1490 | struct resource *res; |
1491 | struct ata_host *host; | 1491 | struct ata_host *host; |
1492 | unsigned int fsclk = get_sclk(); | ||
1493 | int udma_mode = 5; | ||
1492 | const struct ata_port_info *ppi[] = | 1494 | const struct ata_port_info *ppi[] = |
1493 | { &bfin_port_info[board_idx], NULL }; | 1495 | { &bfin_port_info[board_idx], NULL }; |
1494 | 1496 | ||
@@ -1507,6 +1509,11 @@ static int __devinit bfin_atapi_probe(struct platform_device *pdev) | |||
1507 | if (res == NULL) | 1509 | if (res == NULL) |
1508 | return -EINVAL; | 1510 | return -EINVAL; |
1509 | 1511 | ||
1512 | while (bfin_port_info[board_idx].udma_mask>0 && udma_fsclk[udma_mode] > fsclk) { | ||
1513 | udma_mode--; | ||
1514 | bfin_port_info[board_idx].udma_mask >>= 1; | ||
1515 | } | ||
1516 | |||
1510 | /* | 1517 | /* |
1511 | * Now that that's out of the way, wire up the port.. | 1518 | * Now that that's out of the way, wire up the port.. |
1512 | */ | 1519 | */ |
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index a43f64d2775b..8d864e5e97ed 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
@@ -164,10 +164,14 @@ enum { | |||
164 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | 164 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, |
165 | MV_PCI_ERR_COMMAND = 0x1d50, | 165 | MV_PCI_ERR_COMMAND = 0x1d50, |
166 | 166 | ||
167 | PCI_IRQ_CAUSE_OFS = 0x1d58, | 167 | PCI_IRQ_CAUSE_OFS = 0x1d58, |
168 | PCI_IRQ_MASK_OFS = 0x1d5c, | 168 | PCI_IRQ_MASK_OFS = 0x1d5c, |
169 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ | 169 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
170 | 170 | ||
171 | PCIE_IRQ_CAUSE_OFS = 0x1900, | ||
172 | PCIE_IRQ_MASK_OFS = 0x1910, | ||
173 | PCIE_UNMASK_ALL_IRQS = 0x70a, /* assorted bits */ | ||
174 | |||
171 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, | 175 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, |
172 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, | 176 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, |
173 | PORT0_ERR = (1 << 0), /* shift by port # */ | 177 | PORT0_ERR = (1 << 0), /* shift by port # */ |
@@ -303,6 +307,7 @@ enum { | |||
303 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ | 307 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ |
304 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ | 308 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ |
305 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ | 309 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ |
310 | MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ | ||
306 | 311 | ||
307 | /* Port private flags (pp_flags) */ | 312 | /* Port private flags (pp_flags) */ |
308 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ | 313 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ |
@@ -388,7 +393,15 @@ struct mv_port_signal { | |||
388 | u32 pre; | 393 | u32 pre; |
389 | }; | 394 | }; |
390 | 395 | ||
391 | struct mv_host_priv; | 396 | struct mv_host_priv { |
397 | u32 hp_flags; | ||
398 | struct mv_port_signal signal[8]; | ||
399 | const struct mv_hw_ops *ops; | ||
400 | u32 irq_cause_ofs; | ||
401 | u32 irq_mask_ofs; | ||
402 | u32 unmask_all_irqs; | ||
403 | }; | ||
404 | |||
392 | struct mv_hw_ops { | 405 | struct mv_hw_ops { |
393 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, | 406 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
394 | unsigned int port); | 407 | unsigned int port); |
@@ -401,12 +414,6 @@ struct mv_hw_ops { | |||
401 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); | 414 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); |
402 | }; | 415 | }; |
403 | 416 | ||
404 | struct mv_host_priv { | ||
405 | u32 hp_flags; | ||
406 | struct mv_port_signal signal[8]; | ||
407 | const struct mv_hw_ops *ops; | ||
408 | }; | ||
409 | |||
410 | static void mv_irq_clear(struct ata_port *ap); | 417 | static void mv_irq_clear(struct ata_port *ap); |
411 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); | 418 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
412 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | 419 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
@@ -631,11 +638,13 @@ static const struct pci_device_id mv_pci_tbl[] = { | |||
631 | /* Adaptec 1430SA */ | 638 | /* Adaptec 1430SA */ |
632 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, | 639 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, |
633 | 640 | ||
634 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, | 641 | /* Marvell 7042 support */ |
635 | |||
636 | /* add Marvell 7042 support */ | ||
637 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, | 642 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
638 | 643 | ||
644 | /* Highpoint RocketRAID PCIe series */ | ||
645 | { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, | ||
646 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, | ||
647 | |||
639 | { } /* terminate list */ | 648 | { } /* terminate list */ |
640 | }; | 649 | }; |
641 | 650 | ||
@@ -1648,13 +1657,14 @@ static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) | |||
1648 | 1657 | ||
1649 | static void mv_pci_error(struct ata_host *host, void __iomem *mmio) | 1658 | static void mv_pci_error(struct ata_host *host, void __iomem *mmio) |
1650 | { | 1659 | { |
1660 | struct mv_host_priv *hpriv = host->private_data; | ||
1651 | struct ata_port *ap; | 1661 | struct ata_port *ap; |
1652 | struct ata_queued_cmd *qc; | 1662 | struct ata_queued_cmd *qc; |
1653 | struct ata_eh_info *ehi; | 1663 | struct ata_eh_info *ehi; |
1654 | unsigned int i, err_mask, printed = 0; | 1664 | unsigned int i, err_mask, printed = 0; |
1655 | u32 err_cause; | 1665 | u32 err_cause; |
1656 | 1666 | ||
1657 | err_cause = readl(mmio + PCI_IRQ_CAUSE_OFS); | 1667 | err_cause = readl(mmio + hpriv->irq_cause_ofs); |
1658 | 1668 | ||
1659 | dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", | 1669 | dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", |
1660 | err_cause); | 1670 | err_cause); |
@@ -1662,7 +1672,7 @@ static void mv_pci_error(struct ata_host *host, void __iomem *mmio) | |||
1662 | DPRINTK("All regs @ PCI error\n"); | 1672 | DPRINTK("All regs @ PCI error\n"); |
1663 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); | 1673 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); |
1664 | 1674 | ||
1665 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | 1675 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
1666 | 1676 | ||
1667 | for (i = 0; i < host->n_ports; i++) { | 1677 | for (i = 0; i < host->n_ports; i++) { |
1668 | ap = host->ports[i]; | 1678 | ap = host->ports[i]; |
@@ -1926,6 +1936,8 @@ static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |||
1926 | #define ZERO(reg) writel(0, mmio + (reg)) | 1936 | #define ZERO(reg) writel(0, mmio + (reg)) |
1927 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) | 1937 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) |
1928 | { | 1938 | { |
1939 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | ||
1940 | struct mv_host_priv *hpriv = host->private_data; | ||
1929 | u32 tmp; | 1941 | u32 tmp; |
1930 | 1942 | ||
1931 | tmp = readl(mmio + MV_PCI_MODE); | 1943 | tmp = readl(mmio + MV_PCI_MODE); |
@@ -1937,8 +1949,8 @@ static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) | |||
1937 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); | 1949 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
1938 | ZERO(HC_MAIN_IRQ_MASK_OFS); | 1950 | ZERO(HC_MAIN_IRQ_MASK_OFS); |
1939 | ZERO(MV_PCI_SERR_MASK); | 1951 | ZERO(MV_PCI_SERR_MASK); |
1940 | ZERO(PCI_IRQ_CAUSE_OFS); | 1952 | ZERO(hpriv->irq_cause_ofs); |
1941 | ZERO(PCI_IRQ_MASK_OFS); | 1953 | ZERO(hpriv->irq_mask_ofs); |
1942 | ZERO(MV_PCI_ERR_LOW_ADDRESS); | 1954 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
1943 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | 1955 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); |
1944 | ZERO(MV_PCI_ERR_ATTRIBUTE); | 1956 | ZERO(MV_PCI_ERR_ATTRIBUTE); |
@@ -2170,7 +2182,7 @@ static void mv_phy_reset(struct ata_port *ap, unsigned int *class, | |||
2170 | mv_scr_read(ap, SCR_ERROR, &serror); | 2182 | mv_scr_read(ap, SCR_ERROR, &serror); |
2171 | mv_scr_read(ap, SCR_CONTROL, &scontrol); | 2183 | mv_scr_read(ap, SCR_CONTROL, &scontrol); |
2172 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " | 2184 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
2173 | "SCtrl 0x%08x\n", status, serror, scontrol); | 2185 | "SCtrl 0x%08x\n", sstatus, serror, scontrol); |
2174 | } | 2186 | } |
2175 | #endif | 2187 | #endif |
2176 | 2188 | ||
@@ -2490,6 +2502,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx) | |||
2490 | break; | 2502 | break; |
2491 | 2503 | ||
2492 | case chip_7042: | 2504 | case chip_7042: |
2505 | hp_flags |= MV_HP_PCIE; | ||
2493 | case chip_6042: | 2506 | case chip_6042: |
2494 | hpriv->ops = &mv6xxx_ops; | 2507 | hpriv->ops = &mv6xxx_ops; |
2495 | hp_flags |= MV_HP_GEN_IIE; | 2508 | hp_flags |= MV_HP_GEN_IIE; |
@@ -2516,6 +2529,15 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx) | |||
2516 | } | 2529 | } |
2517 | 2530 | ||
2518 | hpriv->hp_flags = hp_flags; | 2531 | hpriv->hp_flags = hp_flags; |
2532 | if (hp_flags & MV_HP_PCIE) { | ||
2533 | hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; | ||
2534 | hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; | ||
2535 | hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; | ||
2536 | } else { | ||
2537 | hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; | ||
2538 | hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; | ||
2539 | hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; | ||
2540 | } | ||
2519 | 2541 | ||
2520 | return 0; | 2542 | return 0; |
2521 | } | 2543 | } |
@@ -2595,10 +2617,10 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx) | |||
2595 | } | 2617 | } |
2596 | 2618 | ||
2597 | /* Clear any currently outstanding host interrupt conditions */ | 2619 | /* Clear any currently outstanding host interrupt conditions */ |
2598 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | 2620 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
2599 | 2621 | ||
2600 | /* and unmask interrupt generation for host regs */ | 2622 | /* and unmask interrupt generation for host regs */ |
2601 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); | 2623 | writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); |
2602 | 2624 | ||
2603 | if (IS_GEN_I(hpriv)) | 2625 | if (IS_GEN_I(hpriv)) |
2604 | writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS); | 2626 | writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS); |
@@ -2609,8 +2631,8 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx) | |||
2609 | "PCI int cause/mask=0x%08x/0x%08x\n", | 2631 | "PCI int cause/mask=0x%08x/0x%08x\n", |
2610 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), | 2632 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), |
2611 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), | 2633 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), |
2612 | readl(mmio + PCI_IRQ_CAUSE_OFS), | 2634 | readl(mmio + hpriv->irq_cause_ofs), |
2613 | readl(mmio + PCI_IRQ_MASK_OFS)); | 2635 | readl(mmio + hpriv->irq_mask_ofs)); |
2614 | 2636 | ||
2615 | done: | 2637 | done: |
2616 | return rc; | 2638 | return rc; |