aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorSujith <Sujith.Manoharan@atheros.com>2009-08-07 00:15:11 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-14 09:12:48 -0400
commitc16c9d0657268daaf8a03e7895fb5c5f005285db (patch)
treea72ffc8d40b52e4eee85abf003e41048dfd8756f /drivers
parent54e4cec69e70ba30aec68650fb95b3a7e1e6dc18 (diff)
ath9k: Try to fix whitespace damage
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c251
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h193
2 files changed, 215 insertions, 229 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 86b13d1b290d..4303a4d88288 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -2854,7 +2854,6 @@ static struct eeprom_ops eep_def_ops = {
2854 .get_spur_channel = ath9k_hw_def_get_spur_channel 2854 .get_spur_channel = ath9k_hw_def_get_spur_channel
2855}; 2855};
2856 2856
2857
2858static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 2857static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
2859{ 2858{
2860 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF; 2859 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
@@ -2871,22 +2870,24 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
2871 u16 *eep_data; 2870 u16 *eep_data;
2872 int addr, eep_start_loc = AR9287_EEP_START_LOC; 2871 int addr, eep_start_loc = AR9287_EEP_START_LOC;
2873 eep_data = (u16 *)eep; 2872 eep_data = (u16 *)eep;
2873
2874 if (!ath9k_hw_use_flash(ah)) { 2874 if (!ath9k_hw_use_flash(ah)) {
2875 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2875 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2876 "Reading from EEPROM, not flash\n"); 2876 "Reading from EEPROM, not flash\n");
2877 } 2877 }
2878 2878
2879 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); 2879 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
2880 addr++) { 2880 addr++) {
2881 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 2881 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
2882 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2882 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2883 "Unable to read eeprom region \n"); 2883 "Unable to read eeprom region \n");
2884 return false; 2884 return false;
2885 } 2885 }
2886 eep_data++; 2886 eep_data++;
2887 } 2887 }
2888 return true; 2888 return true;
2889} 2889}
2890
2890static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) 2891static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
2891{ 2892{
2892 u32 sum = 0, el, integer; 2893 u32 sum = 0, el, integer;
@@ -2996,7 +2997,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
2996} 2997}
2997 2998
2998static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah, 2999static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
2999 enum eeprom_param param) 3000 enum eeprom_param param)
3000{ 3001{
3001 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 3002 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
3002 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 3003 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
@@ -3059,6 +3060,7 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
3059{ 3060{
3060#define TMP_VAL_VPD_TABLE \ 3061#define TMP_VAL_VPD_TABLE \
3061 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep)); 3062 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
3063
3062 int i, j, k; 3064 int i, j, k;
3063 int16_t ss; 3065 int16_t ss;
3064 u16 idxL = 0, idxR = 0, numPiers; 3066 u16 idxL = 0, idxR = 0, numPiers;
@@ -3079,6 +3081,7 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
3079 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 3081 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3080 3082
3081 ath9k_hw_get_channel_centers(ah, chan, &centers); 3083 ath9k_hw_get_channel_centers(ah, chan, &centers);
3084
3082 for (numPiers = 0; numPiers < availPiers; numPiers++) { 3085 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3083 if (bChans[numPiers] == AR9287_BCHAN_UNUSED) 3086 if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
3084 break; 3087 break;
@@ -3205,16 +3208,18 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
3205} 3208}
3206 3209
3207static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, 3210static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
3208 struct ath9k_channel *chan, 3211 struct ath9k_channel *chan,
3209 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, 3212 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
3210 u8 *pCalChans, u16 availPiers, 3213 u8 *pCalChans, u16 availPiers,
3211 int8_t *pPwr) 3214 int8_t *pPwr)
3212{ 3215{
3213 u8 pcdac, i = 0; 3216 u8 pcdac, i = 0;
3214 u16 idxL = 0, idxR = 0, numPiers; 3217 u16 idxL = 0, idxR = 0, numPiers;
3215 bool match; 3218 bool match;
3216 struct chan_centers centers; 3219 struct chan_centers centers;
3220
3217 ath9k_hw_get_channel_centers(ah, chan, &centers); 3221 ath9k_hw_get_channel_centers(ah, chan, &centers);
3222
3218 for (numPiers = 0; numPiers < availPiers; numPiers++) { 3223 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3219 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED) 3224 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
3220 break; 3225 break;
@@ -3272,9 +3277,9 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
3272 } 3277 }
3273} 3278}
3274 3279
3275
3276static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, 3280static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
3277 struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) 3281 struct ath9k_channel *chan,
3282 int16_t *pTxPowerIndexOffset)
3278{ 3283{
3279 struct cal_data_per_freq_ar9287 *pRawDataset; 3284 struct cal_data_per_freq_ar9287 *pRawDataset;
3280 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 3285 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
@@ -3430,7 +3435,6 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
3430 *pTxPowerIndexOffset = 0; 3435 *pTxPowerIndexOffset = 0;
3431} 3436}
3432 3437
3433
3434static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, 3438static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3435 struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, 3439 struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl,
3436 u16 AntennaReduction, u16 twiceMaxRegulatoryPower, 3440 u16 AntennaReduction, u16 twiceMaxRegulatoryPower,
@@ -3440,8 +3444,8 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3440#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 3444#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
3441 3445
3442 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 3446 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
3443 static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, 3447 static const u16 tpScaleReductionTable[5] =
3444 AR5416_MAX_RATE_POWER }; 3448 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
3445 int i; 3449 int i;
3446 int16_t twiceLargestAntenna; 3450 int16_t twiceLargestAntenna;
3447 struct cal_ctl_data_ar9287 *rep; 3451 struct cal_ctl_data_ar9287 *rep;
@@ -3452,8 +3456,9 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3452 struct cal_target_power_ht targetPowerHt20, 3456 struct cal_target_power_ht targetPowerHt20,
3453 targetPowerHt40 = {0, {0, 0, 0, 0} }; 3457 targetPowerHt40 = {0, {0, 0, 0, 0} };
3454 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 3458 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
3455 u16 ctlModesFor11g[] = {CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, 3459 u16 ctlModesFor11g[] =
3456 CTL_11G_EXT, CTL_2GHT40}; 3460 {CTL_11B, CTL_11G, CTL_2GHT20,
3461 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40};
3457 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq; 3462 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
3458 struct chan_centers centers; 3463 struct chan_centers centers;
3459 int tx_chainmask; 3464 int tx_chainmask;
@@ -3464,7 +3469,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3464 ath9k_hw_get_channel_centers(ah, chan, &centers); 3469 ath9k_hw_get_channel_centers(ah, chan, &centers);
3465 3470
3466 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0], 3471 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
3467 pEepData->modalHeader.antennaGainCh[1]); 3472 pEepData->modalHeader.antennaGainCh[1]);
3468 3473
3469 twiceLargestAntenna = (int16_t)min((AntennaReduction) - 3474 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
3470 twiceLargestAntenna, 0); 3475 twiceLargestAntenna, 0);
@@ -3489,42 +3494,41 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3489 scaledPower = max((u16)0, scaledPower); 3494 scaledPower = max((u16)0, scaledPower);
3490 3495
3491 if (IS_CHAN_2GHZ(chan)) { 3496 if (IS_CHAN_2GHZ(chan)) {
3492 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - 3497 numCtlModes =
3493 SUB_NUM_CTL_MODES_AT_2G_40; 3498 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
3494 pCtlMode = ctlModesFor11g; 3499 pCtlMode = ctlModesFor11g;
3495 3500
3496 ath9k_hw_get_legacy_target_powers(ah, chan, 3501 ath9k_hw_get_legacy_target_powers(ah, chan,
3497 pEepData->calTargetPowerCck, 3502 pEepData->calTargetPowerCck,
3498 AR9287_NUM_2G_CCK_TARGET_POWERS, 3503 AR9287_NUM_2G_CCK_TARGET_POWERS,
3499 &targetPowerCck, 4, false); 3504 &targetPowerCck, 4, false);
3500 ath9k_hw_get_legacy_target_powers(ah, chan, 3505 ath9k_hw_get_legacy_target_powers(ah, chan,
3501 pEepData->calTargetPower2G, 3506 pEepData->calTargetPower2G,
3502 AR9287_NUM_2G_20_TARGET_POWERS, 3507 AR9287_NUM_2G_20_TARGET_POWERS,
3503 &targetPowerOfdm, 4, false); 3508 &targetPowerOfdm, 4, false);
3504 ath9k_hw_get_target_powers(ah, chan, 3509 ath9k_hw_get_target_powers(ah, chan,
3505 pEepData->calTargetPower2GHT20, 3510 pEepData->calTargetPower2GHT20,
3506 AR9287_NUM_2G_20_TARGET_POWERS, 3511 AR9287_NUM_2G_20_TARGET_POWERS,
3507 &targetPowerHt20, 8, false); 3512 &targetPowerHt20, 8, false);
3508 3513
3509 if (IS_CHAN_HT40(chan)) { 3514 if (IS_CHAN_HT40(chan)) {
3510 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 3515 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
3511 ath9k_hw_get_target_powers(ah, chan, 3516 ath9k_hw_get_target_powers(ah, chan,
3512 pEepData->calTargetPower2GHT40, 3517 pEepData->calTargetPower2GHT40,
3513 AR9287_NUM_2G_40_TARGET_POWERS, 3518 AR9287_NUM_2G_40_TARGET_POWERS,
3514 &targetPowerHt40, 8, true); 3519 &targetPowerHt40, 8, true);
3515 ath9k_hw_get_legacy_target_powers(ah, chan, 3520 ath9k_hw_get_legacy_target_powers(ah, chan,
3516 pEepData->calTargetPowerCck, 3521 pEepData->calTargetPowerCck,
3517 AR9287_NUM_2G_CCK_TARGET_POWERS, 3522 AR9287_NUM_2G_CCK_TARGET_POWERS,
3518 &targetPowerCckExt, 4, true); 3523 &targetPowerCckExt, 4, true);
3519 ath9k_hw_get_legacy_target_powers(ah, chan, 3524 ath9k_hw_get_legacy_target_powers(ah, chan,
3520 pEepData->calTargetPower2G, 3525 pEepData->calTargetPower2G,
3521 AR9287_NUM_2G_20_TARGET_POWERS, 3526 AR9287_NUM_2G_20_TARGET_POWERS,
3522 &targetPowerOfdmExt, 4, true); 3527 &targetPowerOfdmExt, 4, true);
3523 } 3528 }
3524 } 3529 }
3525 3530
3526 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 3531 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
3527
3528 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 3532 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
3529 (pCtlMode[ctlMode] == CTL_2GHT40); 3533 (pCtlMode[ctlMode] == CTL_2GHT40);
3530 if (isHt40CtlMode) 3534 if (isHt40CtlMode)
@@ -3534,14 +3538,15 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3534 else 3538 else
3535 freq = centers.ctl_center; 3539 freq = centers.ctl_center;
3536 3540
3537
3538 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 3541 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
3539 ah->eep_ops->get_eeprom_rev(ah) <= 2) 3542 ah->eep_ops->get_eeprom_rev(ah) <= 2)
3540 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 3543 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
3544
3541 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 3545 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3542 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d," 3546 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d,"
3543 "EXT_ADDITIVE %d\n", ctlMode, numCtlModes, 3547 "EXT_ADDITIVE %d\n", ctlMode, numCtlModes,
3544 isHt40CtlMode, (pCtlMode[ctlMode] & EXT_ADDITIVE)); 3548 isHt40CtlMode, (pCtlMode[ctlMode] & EXT_ADDITIVE));
3549
3545 for (i = 0; (i < AR9287_NUM_CTLS) 3550 for (i = 0; (i < AR9287_NUM_CTLS)
3546 && pEepData->ctlIndex[i]; i++) { 3551 && pEepData->ctlIndex[i]; i++) {
3547 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 3552 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
@@ -3552,12 +3557,12 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3552 pEepData->ctlIndex[i], chan->channel); 3557 pEepData->ctlIndex[i], chan->channel);
3553 3558
3554 if ((((cfgCtl & ~CTL_MODE_M) | 3559 if ((((cfgCtl & ~CTL_MODE_M) |
3555 (pCtlMode[ctlMode] & CTL_MODE_M)) == 3560 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
3556 pEepData->ctlIndex[i]) || 3561 pEepData->ctlIndex[i]) ||
3557 (((cfgCtl & ~CTL_MODE_M) | 3562 (((cfgCtl & ~CTL_MODE_M) |
3558 (pCtlMode[ctlMode] & CTL_MODE_M)) == 3563 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
3559 ((pEepData->ctlIndex[i] & 3564 ((pEepData->ctlIndex[i] &
3560 CTL_MODE_M) | SD_NO_CTL))) { 3565 CTL_MODE_M) | SD_NO_CTL))) {
3561 3566
3562 rep = &(pEepData->ctlData[i]); 3567 rep = &(pEepData->ctlData[i]);
3563 twiceMinEdgePower = ath9k_hw_get_max_edge_power( 3568 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
@@ -3592,7 +3597,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3592 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 3597 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
3593 scaledPower, minCtlPower); 3598 scaledPower, minCtlPower);
3594 3599
3595
3596 switch (pCtlMode[ctlMode]) { 3600 switch (pCtlMode[ctlMode]) {
3597 3601
3598 case CTL_11B: 3602 case CTL_11B:
@@ -3650,9 +3654,13 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3650 } 3654 }
3651 } 3655 }
3652 3656
3653 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 3657 ratesArray[rate6mb] =
3654 ratesArray[rate18mb] = ratesArray[rate24mb] = 3658 ratesArray[rate9mb] =
3655 targetPowerOfdm.tPow2x[0]; 3659 ratesArray[rate12mb] =
3660 ratesArray[rate18mb] =
3661 ratesArray[rate24mb] =
3662 targetPowerOfdm.tPow2x[0];
3663
3656 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 3664 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
3657 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 3665 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
3658 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 3666 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
@@ -3663,7 +3671,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3663 3671
3664 if (IS_CHAN_2GHZ(chan)) { 3672 if (IS_CHAN_2GHZ(chan)) {
3665 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 3673 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
3666 ratesArray[rate2s] = ratesArray[rate2l] = 3674 ratesArray[rate2s] = ratesArray[rate2l] =
3667 targetPowerCck.tPow2x[1]; 3675 targetPowerCck.tPow2x[1];
3668 ratesArray[rate5_5s] = ratesArray[rate5_5l] = 3676 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
3669 targetPowerCck.tPow2x[2]; 3677 targetPowerCck.tPow2x[2];
@@ -3680,35 +3688,38 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3680 if (IS_CHAN_2GHZ(chan)) 3688 if (IS_CHAN_2GHZ(chan))
3681 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 3689 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
3682 } 3690 }
3691
3683#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN 3692#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
3684#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN 3693#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
3685} 3694}
3686 3695
3687static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah, 3696static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
3688 struct ath9k_channel *chan, u16 cfgCtl, 3697 struct ath9k_channel *chan, u16 cfgCtl,
3689 u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, 3698 u8 twiceAntennaReduction,
3690 u8 powerLimit) 3699 u8 twiceMaxRegulatoryPower,
3700 u8 powerLimit)
3691{ 3701{
3692#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 3702#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
3693#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 3703#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
3704
3694 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 3705 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
3695 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 3706 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
3696 int16_t ratesArray[Ar5416RateSize]; 3707 int16_t ratesArray[Ar5416RateSize];
3697 int16_t txPowerIndexOffset = 0; 3708 int16_t txPowerIndexOffset = 0;
3698 u8 ht40PowerIncForPdadc = 2; 3709 u8 ht40PowerIncForPdadc = 2;
3699 int i; 3710 int i;
3711
3700 memset(ratesArray, 0, sizeof(ratesArray)); 3712 memset(ratesArray, 0, sizeof(ratesArray));
3701 3713
3702 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= 3714 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
3703 AR9287_EEP_MINOR_VER_2) 3715 AR9287_EEP_MINOR_VER_2)
3704 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 3716 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
3705 3717
3706 ath9k_hw_set_AR9287_power_per_rate_table(ah, chan, 3718 ath9k_hw_set_AR9287_power_per_rate_table(ah, chan,
3707 &ratesArray[0], cfgCtl, 3719 &ratesArray[0], cfgCtl,
3708 twiceAntennaReduction, 3720 twiceAntennaReduction,
3709 twiceMaxRegulatoryPower, 3721 twiceMaxRegulatoryPower,
3710 powerLimit); 3722 powerLimit);
3711
3712 3723
3713 ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset); 3724 ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset);
3714 3725
@@ -3723,99 +3734,85 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
3723 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; 3734 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
3724 } 3735 }
3725 3736
3726
3727 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 3737 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
3728 ATH9K_POW_SM(ratesArray[rate18mb], 24) 3738 ATH9K_POW_SM(ratesArray[rate18mb], 24)
3729 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 3739 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
3730 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 3740 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
3731 | ATH9K_POW_SM(ratesArray[rate6mb], 0) 3741 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
3732 );
3733 3742
3734 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 3743 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
3735 ATH9K_POW_SM(ratesArray[rate54mb], 24) 3744 ATH9K_POW_SM(ratesArray[rate54mb], 24)
3736 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 3745 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
3737 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 3746 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
3738 | ATH9K_POW_SM(ratesArray[rate24mb], 0) 3747 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
3739 );
3740 3748
3741 if (IS_CHAN_2GHZ(chan)) { 3749 if (IS_CHAN_2GHZ(chan)) {
3742 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 3750 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
3743 ATH9K_POW_SM(ratesArray[rate2s], 24) 3751 ATH9K_POW_SM(ratesArray[rate2s], 24)
3744 | ATH9K_POW_SM(ratesArray[rate2l], 16) 3752 | ATH9K_POW_SM(ratesArray[rate2l], 16)
3745 | ATH9K_POW_SM(ratesArray[rateXr], 8) 3753 | ATH9K_POW_SM(ratesArray[rateXr], 8)
3746 | ATH9K_POW_SM(ratesArray[rate1l], 0) 3754 | ATH9K_POW_SM(ratesArray[rate1l], 0));
3747 );
3748 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 3755 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
3749 ATH9K_POW_SM(ratesArray[rate11s], 24) 3756 ATH9K_POW_SM(ratesArray[rate11s], 24)
3750 | ATH9K_POW_SM(ratesArray[rate11l], 16) 3757 | ATH9K_POW_SM(ratesArray[rate11l], 16)
3751 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 3758 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
3752 | ATH9K_POW_SM(ratesArray[rate5_5l], 0) 3759 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
3753 );
3754 } 3760 }
3755 3761
3756 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 3762 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
3757 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 3763 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
3758 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 3764 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
3759 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 3765 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
3760 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0) 3766 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
3761 );
3762 3767
3763 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 3768 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
3764 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 3769 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
3765 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 3770 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
3766 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 3771 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
3767 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0) 3772 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
3768 );
3769 3773
3770 if (IS_CHAN_HT40(chan)) { 3774 if (IS_CHAN_HT40(chan)) {
3771 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 3775 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
3772 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 3776 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
3773 ATH9K_POW_SM(ratesArray[rateHt40_3], 24) 3777 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
3774 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16) 3778 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
3775 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8) 3779 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
3776 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0) 3780 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
3777 );
3778 3781
3779 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 3782 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
3780 ATH9K_POW_SM(ratesArray[rateHt40_7], 24) 3783 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
3781 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16) 3784 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
3782 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8) 3785 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
3783 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0) 3786 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
3784 );
3785 } else { 3787 } else {
3786 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 3788 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
3787 ATH9K_POW_SM(ratesArray[rateHt40_3] + 3789 ATH9K_POW_SM(ratesArray[rateHt40_3] +
3788 ht40PowerIncForPdadc, 24) 3790 ht40PowerIncForPdadc, 24)
3789 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 3791 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
3790 ht40PowerIncForPdadc, 16) 3792 ht40PowerIncForPdadc, 16)
3791 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 3793 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
3792 ht40PowerIncForPdadc, 8) 3794 ht40PowerIncForPdadc, 8)
3793 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 3795 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
3794 ht40PowerIncForPdadc, 0) 3796 ht40PowerIncForPdadc, 0));
3795 );
3796 3797
3797 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 3798 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
3798 ATH9K_POW_SM(ratesArray[rateHt40_7] + 3799 ATH9K_POW_SM(ratesArray[rateHt40_7] +
3799 ht40PowerIncForPdadc, 24) 3800 ht40PowerIncForPdadc, 24)
3800 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 3801 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
3801 ht40PowerIncForPdadc, 16) 3802 ht40PowerIncForPdadc, 16)
3802 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 3803 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
3803 ht40PowerIncForPdadc, 8) 3804 ht40PowerIncForPdadc, 8)
3804 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 3805 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
3805 ht40PowerIncForPdadc, 0) 3806 ht40PowerIncForPdadc, 0));
3806 );
3807
3808 } 3807 }
3809 3808
3810 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 3809 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
3811 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 3810 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
3812 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 3811 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
3813 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 3812 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
3814 | ATH9K_POW_SM(ratesArray[rateDupCck], 0) 3813 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
3815 );
3816 } 3814 }
3817 3815
3818
3819 if (IS_CHAN_2GHZ(chan)) 3816 if (IS_CHAN_2GHZ(chan))
3820 i = rate1l; 3817 i = rate1l;
3821 else 3818 else
@@ -3840,7 +3837,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
3840 break; 3837 break;
3841 default: 3838 default:
3842 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 3839 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3843 "Invalid chainmask configuration\n"); 3840 "Invalid chainmask configuration\n");
3844 break; 3841 break;
3845 } 3842 }
3846} 3843}
@@ -3848,7 +3845,6 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
3848static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah, 3845static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah,
3849 struct ath9k_channel *chan) 3846 struct ath9k_channel *chan)
3850{ 3847{
3851 return;
3852} 3848}
3853 3849
3854static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah, 3850static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
@@ -3856,7 +3852,6 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
3856{ 3852{
3857 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 3853 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
3858 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 3854 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
3859
3860 u16 antWrites[AR9287_ANT_16S]; 3855 u16 antWrites[AR9287_ANT_16S];
3861 u32 regChainOffset; 3856 u32 regChainOffset;
3862 u8 txRxAttenLocal; 3857 u8 txRxAttenLocal;
@@ -3886,7 +3881,6 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
3886 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3); 3881 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
3887 } 3882 }
3888 3883
3889
3890 REG_WRITE(ah, AR_PHY_SWITCH_COM, 3884 REG_WRITE(ah, AR_PHY_SWITCH_COM,
3891 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); 3885 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
3892 3886
@@ -3899,11 +3893,11 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
3899 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 3893 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
3900 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) 3894 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
3901 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 3895 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
3902 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 3896 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
3903 SM(pModal->iqCalICh[i], 3897 SM(pModal->iqCalICh[i],
3904 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 3898 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
3905 SM(pModal->iqCalQCh[i], 3899 SM(pModal->iqCalQCh[i],
3906 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 3900 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
3907 3901
3908 txRxAttenLocal = pModal->txRxAttenCh[i]; 3902 txRxAttenLocal = pModal->txRxAttenCh[i];
3909 3903
@@ -3995,23 +3989,20 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
3995} 3989}
3996 3990
3997static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah, 3991static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah,
3998 enum ieee80211_band freq_band) 3992 enum ieee80211_band freq_band)
3999{ 3993{
4000 return 1; 3994 return 1;
4001} 3995}
4002 3996
4003
4004
4005
4006static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah, 3997static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
4007 struct ath9k_channel *chan) 3998 struct ath9k_channel *chan)
4008{ 3999{
4009 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 4000 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
4010 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 4001 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
4002
4011 return pModal->antCtrlCommon & 0xFFFF; 4003 return pModal->antCtrlCommon & 0xFFFF;
4012} 4004}
4013 4005
4014
4015static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah, 4006static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
4016 u16 i, bool is2GHz) 4007 u16 i, bool is2GHz)
4017{ 4008{
@@ -4020,8 +4011,8 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
4020 u16 spur_val = AR_NO_SPUR; 4011 u16 spur_val = AR_NO_SPUR;
4021 4012
4022 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 4013 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
4023 "Getting spur idx %d is2Ghz. %d val %x\n", 4014 "Getting spur idx %d is2Ghz. %d val %x\n",
4024 i, is2GHz, ah->config.spurchans[i][is2GHz]); 4015 i, is2GHz, ah->config.spurchans[i][is2GHz]);
4025 4016
4026 switch (ah->config.spurmode) { 4017 switch (ah->config.spurmode) {
4027 case SPUR_DISABLE: 4018 case SPUR_DISABLE:
@@ -4055,10 +4046,10 @@ static struct eeprom_ops eep_AR9287_ops = {
4055 .get_spur_channel = ath9k_hw_AR9287_get_spur_channel 4046 .get_spur_channel = ath9k_hw_AR9287_get_spur_channel
4056}; 4047};
4057 4048
4058
4059int ath9k_hw_eeprom_init(struct ath_hw *ah) 4049int ath9k_hw_eeprom_init(struct ath_hw *ah)
4060{ 4050{
4061 int status; 4051 int status;
4052
4062 if (AR_SREV_9287(ah)) { 4053 if (AR_SREV_9287(ah)) {
4063 ah->eep_map = EEP_MAP_AR9287; 4054 ah->eep_map = EEP_MAP_AR9287;
4064 ah->eep_ops = &eep_AR9287_ops; 4055 ah->eep_ops = &eep_AR9287_ops;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index db77e90ed9ab..a6447096fd14 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -385,106 +385,103 @@ struct calDataPerFreqOpLoop {
385} __packed; 385} __packed;
386 386
387struct modal_eep_4k_header { 387struct modal_eep_4k_header {
388 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 388 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
389 u32 antCtrlCommon; 389 u32 antCtrlCommon;
390 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 390 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
391 u8 switchSettling; 391 u8 switchSettling;
392 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 392 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
393 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 393 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
394 u8 adcDesiredSize; 394 u8 adcDesiredSize;
395 u8 pgaDesiredSize; 395 u8 pgaDesiredSize;
396 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 396 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
397 u8 txEndToXpaOff; 397 u8 txEndToXpaOff;
398 u8 txEndToRxOn; 398 u8 txEndToRxOn;
399 u8 txFrameToXpaOn; 399 u8 txFrameToXpaOn;
400 u8 thresh62; 400 u8 thresh62;
401 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 401 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
402 u8 xpdGain; 402 u8 xpdGain;
403 u8 xpd; 403 u8 xpd;
404 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 404 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
405 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 405 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
406 u8 pdGainOverlap; 406 u8 pdGainOverlap;
407 u8 ob_01; 407 u8 ob_01;
408 u8 db1_01; 408 u8 db1_01;
409 u8 xpaBiasLvl; 409 u8 xpaBiasLvl;
410 u8 txFrameToDataStart; 410 u8 txFrameToDataStart;
411 u8 txFrameToPaOn; 411 u8 txFrameToPaOn;
412 u8 ht40PowerIncForPdadc; 412 u8 ht40PowerIncForPdadc;
413 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 413 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
414 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 414 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
415 u8 swSettleHt40; 415 u8 swSettleHt40;
416 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 416 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
417 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 417 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
418 u8 db2_01; 418 u8 db2_01;
419 u8 version; 419 u8 version;
420 u16 ob_234; 420 u16 ob_234;
421 u16 db1_234; 421 u16 db1_234;
422 u16 db2_234; 422 u16 db2_234;
423 u8 futureModal[4]; 423 u8 futureModal[4];
424
425 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 424 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
426} __packed; 425} __packed;
427 426
428struct base_eep_ar9287_header { 427struct base_eep_ar9287_header {
429 u16 length; 428 u16 length;
430 u16 checksum; 429 u16 checksum;
431 u16 version; 430 u16 version;
432 u8 opCapFlags; 431 u8 opCapFlags;
433 u8 eepMisc; 432 u8 eepMisc;
434 u16 regDmn[2]; 433 u16 regDmn[2];
435 u8 macAddr[6]; 434 u8 macAddr[6];
436 u8 rxMask; 435 u8 rxMask;
437 u8 txMask; 436 u8 txMask;
438 u16 rfSilent; 437 u16 rfSilent;
439 u16 blueToothOptions; 438 u16 blueToothOptions;
440 u16 deviceCap; 439 u16 deviceCap;
441 u32 binBuildNumber; 440 u32 binBuildNumber;
442 u8 deviceType; 441 u8 deviceType;
443 u8 openLoopPwrCntl; 442 u8 openLoopPwrCntl;
444 int8_t pwrTableOffset; 443 int8_t pwrTableOffset;
445 int8_t tempSensSlope; 444 int8_t tempSensSlope;
446 int8_t tempSensSlopePalOn; 445 int8_t tempSensSlopePalOn;
447 u8 futureBase[29]; 446 u8 futureBase[29];
448} __packed; 447} __packed;
449 448
450struct modal_eep_ar9287_header { 449struct modal_eep_ar9287_header {
451 u32 antCtrlChain[AR9287_MAX_CHAINS]; 450 u32 antCtrlChain[AR9287_MAX_CHAINS];
452 u32 antCtrlCommon; 451 u32 antCtrlCommon;
453 int8_t antennaGainCh[AR9287_MAX_CHAINS]; 452 int8_t antennaGainCh[AR9287_MAX_CHAINS];
454 u8 switchSettling; 453 u8 switchSettling;
455 u8 txRxAttenCh[AR9287_MAX_CHAINS]; 454 u8 txRxAttenCh[AR9287_MAX_CHAINS];
456 u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 455 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
457 int8_t adcDesiredSize; 456 int8_t adcDesiredSize;
458 u8 txEndToXpaOff; 457 u8 txEndToXpaOff;
459 u8 txEndToRxOn; 458 u8 txEndToRxOn;
460 u8 txFrameToXpaOn; 459 u8 txFrameToXpaOn;
461 u8 thresh62; 460 u8 thresh62;
462 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 461 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
463 u8 xpdGain; 462 u8 xpdGain;
464 u8 xpd; 463 u8 xpd;
465 int8_t iqCalICh[AR9287_MAX_CHAINS]; 464 int8_t iqCalICh[AR9287_MAX_CHAINS];
466 int8_t iqCalQCh[AR9287_MAX_CHAINS]; 465 int8_t iqCalQCh[AR9287_MAX_CHAINS];
467 u8 pdGainOverlap; 466 u8 pdGainOverlap;
468 u8 xpaBiasLvl; 467 u8 xpaBiasLvl;
469 u8 txFrameToDataStart; 468 u8 txFrameToDataStart;
470 u8 txFrameToPaOn; 469 u8 txFrameToPaOn;
471 u8 ht40PowerIncForPdadc; 470 u8 ht40PowerIncForPdadc;
472 u8 bswAtten[AR9287_MAX_CHAINS]; 471 u8 bswAtten[AR9287_MAX_CHAINS];
473 u8 bswMargin[AR9287_MAX_CHAINS]; 472 u8 bswMargin[AR9287_MAX_CHAINS];
474 u8 swSettleHt40; 473 u8 swSettleHt40;
475 u8 version; 474 u8 version;
476 u8 db1; 475 u8 db1;
477 u8 db2; 476 u8 db2;
478 u8 ob_cck; 477 u8 ob_cck;
479 u8 ob_psk; 478 u8 ob_psk;
480 u8 ob_qam; 479 u8 ob_qam;
481 u8 ob_pal_off; 480 u8 ob_pal_off;
482 u8 futureModal[30]; 481 u8 futureModal[30];
483 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; 482 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
484} __packed; 483} __packed;
485 484
486
487
488struct cal_data_per_freq { 485struct cal_data_per_freq {
489 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 486 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
490 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 487 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
@@ -525,7 +522,6 @@ struct cal_data_op_loop_ar9287 {
525 u8 empty[2][5]; 522 u8 empty[2][5];
526} __packed; 523} __packed;
527 524
528
529struct cal_data_per_freq_ar9287 { 525struct cal_data_per_freq_ar9287 {
530 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 526 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
531 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 527 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
@@ -601,26 +597,25 @@ struct ar5416_eeprom_4k {
601} __packed; 597} __packed;
602 598
603struct ar9287_eeprom { 599struct ar9287_eeprom {
604 struct base_eep_ar9287_header baseEepHeader; 600 struct base_eep_ar9287_header baseEepHeader;
605 u8 custData[AR9287_DATA_SZ]; 601 u8 custData[AR9287_DATA_SZ];
606 struct modal_eep_ar9287_header modalHeader; 602 struct modal_eep_ar9287_header modalHeader;
607 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 603 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
608 union cal_data_per_freq_ar9287_u 604 union cal_data_per_freq_ar9287_u
609 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 605 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
610 struct cal_target_power_leg 606 struct cal_target_power_leg
611 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 607 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
612 struct cal_target_power_leg 608 struct cal_target_power_leg
613 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 609 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
614 struct cal_target_power_ht 610 struct cal_target_power_ht
615 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 611 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
616 struct cal_target_power_ht 612 struct cal_target_power_ht
617 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 613 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
618 u8 ctlIndex[AR9287_NUM_CTLS]; 614 u8 ctlIndex[AR9287_NUM_CTLS];
619 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 615 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
620 u8 padding; 616 u8 padding;
621} __packed; 617} __packed;
622 618
623
624enum reg_ext_bitmap { 619enum reg_ext_bitmap {
625 REG_EXT_JAPAN_MIDBAND = 1, 620 REG_EXT_JAPAN_MIDBAND = 1,
626 REG_EXT_FCC_DFS_HT40 = 2, 621 REG_EXT_FCC_DFS_HT40 = 2,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 23:03:31 -0500