diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2009-12-03 13:08:53 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-12-07 19:46:34 -0500 |
commit | b500f68045058454549f5f8553110ef086d8d06b (patch) | |
tree | 1ae853d3fb595c6c124d4111021d4fd188dfee92 /drivers | |
parent | eed45b30cd1423f8dc10b4312700773cac13c1c8 (diff) |
drm/radeon/kms: add regs and irq tracking bits for hpd
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 54 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_reg.h | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs600d.h | 112 |
4 files changed, 154 insertions, 23 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 61ccde5637d7..05894edadab4 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
@@ -558,6 +558,7 @@ | |||
558 | # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) | 558 | # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) |
559 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) | 559 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) |
560 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) | 560 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) |
561 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 | ||
561 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 | 562 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 |
562 | # define DC_HPD4_INTERRUPT (1 << 14) | 563 | # define DC_HPD4_INTERRUPT (1 << 14) |
563 | # define DC_HPD4_RX_INTERRUPT (1 << 15) | 564 | # define DC_HPD4_RX_INTERRUPT (1 << 15) |
@@ -590,6 +591,18 @@ | |||
590 | # define DC_HPD6_INTERRUPT (1 << 21) | 591 | # define DC_HPD6_INTERRUPT (1 << 21) |
591 | # define DC_HPD6_RX_INTERRUPT (1 << 22) | 592 | # define DC_HPD6_RX_INTERRUPT (1 << 22) |
592 | 593 | ||
594 | #define DACA_AUTO_DETECT_CONTROL 0x7828 | ||
595 | #define DACB_AUTO_DETECT_CONTROL 0x7a28 | ||
596 | #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 | ||
597 | #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 | ||
598 | # define DACx_AUTODETECT_MODE(x) ((x) << 0) | ||
599 | # define DACx_AUTODETECT_MODE_NONE 0 | ||
600 | # define DACx_AUTODETECT_MODE_CONNECT 1 | ||
601 | # define DACx_AUTODETECT_MODE_DISCONNECT 2 | ||
602 | # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) | ||
603 | /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ | ||
604 | # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) | ||
605 | |||
593 | #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 | 606 | #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 |
594 | #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 | 607 | #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 |
595 | #define DACA_AUTODETECT_INT_CONTROL 0x7838 | 608 | #define DACA_AUTODETECT_INT_CONTROL 0x7838 |
@@ -597,23 +610,62 @@ | |||
597 | # define DACx_AUTODETECT_ACK (1 << 0) | 610 | # define DACx_AUTODETECT_ACK (1 << 0) |
598 | # define DACx_AUTODETECT_INT_ENABLE (1 << 16) | 611 | # define DACx_AUTODETECT_INT_ENABLE (1 << 16) |
599 | 612 | ||
613 | #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 | ||
614 | #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 | ||
615 | #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 | ||
616 | # define DC_HOT_PLUG_DETECTx_EN (1 << 0) | ||
617 | |||
618 | #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 | ||
619 | #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 | ||
620 | #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 | ||
621 | # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) | ||
622 | # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) | ||
623 | |||
624 | /* DCE 3.0 */ | ||
625 | #define DC_HPD1_INT_STATUS 0x7d00 | ||
626 | #define DC_HPD2_INT_STATUS 0x7d0c | ||
627 | #define DC_HPD3_INT_STATUS 0x7d18 | ||
628 | #define DC_HPD4_INT_STATUS 0x7d24 | ||
629 | /* DCE 3.2 */ | ||
630 | #define DC_HPD5_INT_STATUS 0x7dc0 | ||
631 | #define DC_HPD6_INT_STATUS 0x7df4 | ||
632 | # define DC_HPDx_INT_STATUS (1 << 0) | ||
633 | # define DC_HPDx_SENSE (1 << 1) | ||
634 | # define DC_HPDx_RX_INT_STATUS (1 << 8) | ||
635 | |||
600 | #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 | 636 | #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 |
601 | #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 | 637 | #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 |
602 | #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c | 638 | #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c |
603 | # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) | 639 | # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) |
604 | # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) | 640 | # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) |
605 | # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) | 641 | # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) |
606 | /* DCE 3.2 */ | 642 | /* DCE 3.0 */ |
607 | #define DC_HPD1_INT_CONTROL 0x7d04 | 643 | #define DC_HPD1_INT_CONTROL 0x7d04 |
608 | #define DC_HPD2_INT_CONTROL 0x7d10 | 644 | #define DC_HPD2_INT_CONTROL 0x7d10 |
609 | #define DC_HPD3_INT_CONTROL 0x7d1c | 645 | #define DC_HPD3_INT_CONTROL 0x7d1c |
610 | #define DC_HPD4_INT_CONTROL 0x7d28 | 646 | #define DC_HPD4_INT_CONTROL 0x7d28 |
647 | /* DCE 3.2 */ | ||
648 | #define DC_HPD5_INT_CONTROL 0x7dc4 | ||
649 | #define DC_HPD6_INT_CONTROL 0x7df8 | ||
611 | # define DC_HPDx_INT_ACK (1 << 0) | 650 | # define DC_HPDx_INT_ACK (1 << 0) |
612 | # define DC_HPDx_INT_POLARITY (1 << 8) | 651 | # define DC_HPDx_INT_POLARITY (1 << 8) |
613 | # define DC_HPDx_INT_EN (1 << 16) | 652 | # define DC_HPDx_INT_EN (1 << 16) |
614 | # define DC_HPDx_RX_INT_ACK (1 << 20) | 653 | # define DC_HPDx_RX_INT_ACK (1 << 20) |
615 | # define DC_HPDx_RX_INT_EN (1 << 24) | 654 | # define DC_HPDx_RX_INT_EN (1 << 24) |
616 | 655 | ||
656 | /* DCE 3.0 */ | ||
657 | #define DC_HPD1_CONTROL 0x7d08 | ||
658 | #define DC_HPD2_CONTROL 0x7d14 | ||
659 | #define DC_HPD3_CONTROL 0x7d20 | ||
660 | #define DC_HPD4_CONTROL 0x7d2c | ||
661 | /* DCE 3.2 */ | ||
662 | #define DC_HPD5_CONTROL 0x7dc8 | ||
663 | #define DC_HPD6_CONTROL 0x7dfc | ||
664 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) | ||
665 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | ||
666 | /* DCE 3.2 */ | ||
667 | # define DC_HPDx_EN (1 << 28) | ||
668 | |||
617 | /* | 669 | /* |
618 | * PM4 | 670 | * PM4 |
619 | */ | 671 | */ |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index f3deb4982b2d..eafe5fad38b3 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -339,6 +339,8 @@ struct radeon_irq { | |||
339 | bool sw_int; | 339 | bool sw_int; |
340 | /* FIXME: use a define max crtc rather than hardcode it */ | 340 | /* FIXME: use a define max crtc rather than hardcode it */ |
341 | bool crtc_vblank_int[2]; | 341 | bool crtc_vblank_int[2]; |
342 | /* FIXME: use defines for max hpd/dacs */ | ||
343 | bool hpd[6]; | ||
342 | spinlock_t sw_lock; | 344 | spinlock_t sw_lock; |
343 | int sw_refcount; | 345 | int sw_refcount; |
344 | }; | 346 | }; |
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index b8116401ffae..6d0a009dd4a1 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h | |||
@@ -887,6 +887,7 @@ | |||
887 | # define RADEON_FP_PANEL_FORMAT (1 << 3) | 887 | # define RADEON_FP_PANEL_FORMAT (1 << 3) |
888 | # define RADEON_FP_EN_TMDS (1 << 7) | 888 | # define RADEON_FP_EN_TMDS (1 << 7) |
889 | # define RADEON_FP_DETECT_SENSE (1 << 8) | 889 | # define RADEON_FP_DETECT_SENSE (1 << 8) |
890 | # define RADEON_FP_DETECT_INT_POL (1 << 9) | ||
890 | # define R200_FP_SOURCE_SEL_MASK (3 << 10) | 891 | # define R200_FP_SOURCE_SEL_MASK (3 << 10) |
891 | # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) | 892 | # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) |
892 | # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) | 893 | # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) |
@@ -894,6 +895,7 @@ | |||
894 | # define R200_FP_SOURCE_SEL_TRANS (3 << 10) | 895 | # define R200_FP_SOURCE_SEL_TRANS (3 << 10) |
895 | # define RADEON_FP_SEL_CRTC1 (0 << 13) | 896 | # define RADEON_FP_SEL_CRTC1 (0 << 13) |
896 | # define RADEON_FP_SEL_CRTC2 (1 << 13) | 897 | # define RADEON_FP_SEL_CRTC2 (1 << 13) |
898 | # define R300_HPD_SEL(x) ((x) << 13) | ||
897 | # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) | 899 | # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) |
898 | # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) | 900 | # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) |
899 | # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) | 901 | # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) |
@@ -909,6 +911,7 @@ | |||
909 | # define RADEON_FP2_ON (1 << 2) | 911 | # define RADEON_FP2_ON (1 << 2) |
910 | # define RADEON_FP2_PANEL_FORMAT (1 << 3) | 912 | # define RADEON_FP2_PANEL_FORMAT (1 << 3) |
911 | # define RADEON_FP2_DETECT_SENSE (1 << 8) | 913 | # define RADEON_FP2_DETECT_SENSE (1 << 8) |
914 | # define RADEON_FP2_DETECT_INT_POL (1 << 9) | ||
912 | # define R200_FP2_SOURCE_SEL_MASK (3 << 10) | 915 | # define R200_FP2_SOURCE_SEL_MASK (3 << 10) |
913 | # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) | 916 | # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) |
914 | # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) | 917 | # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) |
@@ -988,14 +991,20 @@ | |||
988 | 991 | ||
989 | #define RADEON_GEN_INT_CNTL 0x0040 | 992 | #define RADEON_GEN_INT_CNTL 0x0040 |
990 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) | 993 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) |
994 | # define RADEON_FP_DETECT_MASK (1 << 4) | ||
991 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) | 995 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) |
996 | # define RADEON_FP2_DETECT_MASK (1 << 10) | ||
992 | # define RADEON_SW_INT_ENABLE (1 << 25) | 997 | # define RADEON_SW_INT_ENABLE (1 << 25) |
993 | #define RADEON_GEN_INT_STATUS 0x0044 | 998 | #define RADEON_GEN_INT_STATUS 0x0044 |
994 | # define AVIVO_DISPLAY_INT_STATUS (1 << 0) | 999 | # define AVIVO_DISPLAY_INT_STATUS (1 << 0) |
995 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) | 1000 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) |
996 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) | 1001 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) |
1002 | # define RADEON_FP_DETECT_STAT (1 << 4) | ||
1003 | # define RADEON_FP_DETECT_STAT_ACK (1 << 4) | ||
997 | # define RADEON_CRTC2_VBLANK_STAT (1 << 9) | 1004 | # define RADEON_CRTC2_VBLANK_STAT (1 << 9) |
998 | # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) | 1005 | # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) |
1006 | # define RADEON_FP2_DETECT_STAT (1 << 10) | ||
1007 | # define RADEON_FP2_DETECT_STAT_ACK (1 << 10) | ||
999 | # define RADEON_SW_INT_FIRE (1 << 26) | 1008 | # define RADEON_SW_INT_FIRE (1 << 26) |
1000 | # define RADEON_SW_INT_TEST (1 << 25) | 1009 | # define RADEON_SW_INT_TEST (1 << 25) |
1001 | # define RADEON_SW_INT_TEST_ACK (1 << 25) | 1010 | # define RADEON_SW_INT_TEST_ACK (1 << 25) |
diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h index 81308924859a..c1c8f5885cbb 100644 --- a/drivers/gpu/drm/radeon/rs600d.h +++ b/drivers/gpu/drm/radeon/rs600d.h | |||
@@ -30,27 +30,12 @@ | |||
30 | 30 | ||
31 | /* Registers */ | 31 | /* Registers */ |
32 | #define R_000040_GEN_INT_CNTL 0x000040 | 32 | #define R_000040_GEN_INT_CNTL 0x000040 |
33 | #define S_000040_DISPLAY_INT_STATUS(x) (((x) & 0x1) << 0) | 33 | #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) |
34 | #define G_000040_DISPLAY_INT_STATUS(x) (((x) >> 0) & 0x1) | 34 | #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) |
35 | #define C_000040_DISPLAY_INT_STATUS 0xFFFFFFFE | 35 | #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF |
36 | #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) | 36 | #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) |
37 | #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) | 37 | #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) |
38 | #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF | 38 | #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF |
39 | #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) | ||
40 | #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) | ||
41 | #define C_000040_CRTC2_VSYNC 0xFFFFFFBF | ||
42 | #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) | ||
43 | #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) | ||
44 | #define C_000040_SNAPSHOT2 0xFFFFFF7F | ||
45 | #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) | ||
46 | #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) | ||
47 | #define C_000040_CRTC2_VBLANK 0xFFFFFDFF | ||
48 | #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) | ||
49 | #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) | ||
50 | #define C_000040_FP2_DETECT 0xFFFFFBFF | ||
51 | #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) | ||
52 | #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) | ||
53 | #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF | ||
54 | #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) | 39 | #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) |
55 | #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) | 40 | #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) |
56 | #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF | 41 | #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF |
@@ -370,7 +355,90 @@ | |||
370 | #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) | 355 | #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) |
371 | #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) | 356 | #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) |
372 | #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF | 357 | #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF |
373 | 358 | #define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16) | |
359 | #define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1) | ||
360 | #define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF | ||
361 | #define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17) | ||
362 | #define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1) | ||
363 | #define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF | ||
364 | #define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18) | ||
365 | #define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1) | ||
366 | #define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF | ||
367 | #define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19) | ||
368 | #define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1) | ||
369 | #define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF | ||
370 | #define R_007828_DACA_AUTODETECT_CONTROL 0x007828 | ||
371 | #define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0) | ||
372 | #define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) | ||
373 | #define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC | ||
374 | #define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) | ||
375 | #define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) | ||
376 | #define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF | ||
377 | #define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) | ||
378 | #define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) | ||
379 | #define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF | ||
380 | #define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838 | ||
381 | #define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0) | ||
382 | #define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE | ||
383 | #define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) | ||
384 | #define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) | ||
385 | #define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF | ||
386 | #define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28 | ||
387 | #define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0) | ||
388 | #define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) | ||
389 | #define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC | ||
390 | #define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) | ||
391 | #define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) | ||
392 | #define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF | ||
393 | #define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) | ||
394 | #define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) | ||
395 | #define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF | ||
396 | #define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38 | ||
397 | #define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0) | ||
398 | #define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE | ||
399 | #define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) | ||
400 | #define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) | ||
401 | #define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF | ||
402 | #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00 | ||
403 | #define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0) | ||
404 | #define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1) | ||
405 | #define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE | ||
406 | #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04 | ||
407 | #define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0) | ||
408 | #define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1) | ||
409 | #define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE | ||
410 | #define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1) | ||
411 | #define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1) | ||
412 | #define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD | ||
413 | #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08 | ||
414 | #define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0) | ||
415 | #define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE | ||
416 | #define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8) | ||
417 | #define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1) | ||
418 | #define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF | ||
419 | #define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16) | ||
420 | #define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1) | ||
421 | #define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF | ||
422 | #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10 | ||
423 | #define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0) | ||
424 | #define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1) | ||
425 | #define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE | ||
426 | #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14 | ||
427 | #define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0) | ||
428 | #define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1) | ||
429 | #define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE | ||
430 | #define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1) | ||
431 | #define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1) | ||
432 | #define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD | ||
433 | #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18 | ||
434 | #define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0) | ||
435 | #define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE | ||
436 | #define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8) | ||
437 | #define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1) | ||
438 | #define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF | ||
439 | #define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16) | ||
440 | #define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1) | ||
441 | #define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF | ||
374 | 442 | ||
375 | /* MC registers */ | 443 | /* MC registers */ |
376 | #define R_000000_MC_STATUS 0x000000 | 444 | #define R_000000_MC_STATUS 0x000000 |