bcma: add driver for PCIe Gen 2 core

New Broadcom PCIe devices (802.11ac ones?) use Gen2 and have to be
initialized differently.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

3 files changed, 184 insertions, 0 deletions

diff --git a/drivers/bcma/Makefile b/drivers/bcma/Makefile
index 734b32f09c0a..91290f7f61b8 100644
--- a/drivers/bcma/Makefile
+++ b/drivers/bcma/Makefile
@@ -3,6 +3,7 @@ bcma-y					+= driver_chipcommon.o driver_chipcommon_pmu.o
 bcma-$(CONFIG_BCMA_SFLASH)              += driver_chipcommon_sflash.o
 bcma-$(CONFIG_BCMA_NFLASH)              += driver_chipcommon_nflash.o
 bcma-y                                  += driver_pci.o
+bcma-y                                  += driver_pcie2.o
 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
 bcma-$(CONFIG_BCMA_DRIVER_MIPS)         += driver_mips.o
 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN)     += driver_gmac_cmn.o
diff --git a/drivers/bcma/driver_pcie2.c b/drivers/bcma/driver_pcie2.c
new file mode 100644
index 000000000000..e4be537b0c66
--- /dev/null
+++ b/drivers/bcma/driver_pcie2.c
@@ -0,0 +1,175 @@
+/*
+ * Broadcom specific AMBA
+ * PCIe Gen 2 Core
+ *
+ * Copyright 2014, Broadcom Corporation
+ * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include "bcma_private.h"
+#include <linux/bcma/bcma.h>
+
+/**************************************************
+ * R/W ops.
+ **************************************************/
+
+#if 0
+static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
+{
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
+        pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
+        return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
+}
+#endif
+
+static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
+                                      u32 val)
+{
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
+}
+
+/**************************************************
+ * Init.
+ **************************************************/
+
+static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
+                                                bool enable)
+{
+        u32 val;
+
+        /* restore back to default */
+        val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
+        val |= PCIE2_CLKC_DLYPERST;
+        val &= ~PCIE2_CLKC_DISSPROMLD;
+        if (enable) {
+                val &= ~PCIE2_CLKC_DLYPERST;
+                val |= PCIE2_CLKC_DISSPROMLD;
+        }
+        pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
+        /* flush */
+        return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
+}
+
+static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
+{
+        /* LTR0 */
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
+        /* LTR1 */
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
+        /* LTR2 */
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
+}
+
+static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
+{
+        u8 core_rev = pcie2->core->id.rev;
+        u32 devstsctr2;
+
+        if (core_rev < 2 || core_rev == 10 || core_rev > 13)
+                return;
+
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
+                      PCIE2_CAP_DEVSTSCTRL2_OFFSET);
+        devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
+        if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
+                /* force the right LTR values */
+                bcma_core_pcie2_set_ltr_vals(pcie2);
+
+                /* TODO:
+                si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
+
+                /* enable the LTR */
+                devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
+                pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
+                              PCIE2_CAP_DEVSTSCTRL2_OFFSET);
+                pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
+
+                /* set the LTR state to be active */
+                pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
+                              PCIE2_LTR_ACTIVE);
+                usleep_range(1000, 2000);
+
+                /* set the LTR state to be sleep */
+                pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
+                              PCIE2_LTR_SLEEP);
+                usleep_range(1000, 2000);
+        }
+}
+
+static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
+{
+        u8 core_rev = pcie2->core->id.rev;
+        bool pciewar160, pciewar162;
+
+        pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
+        pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
+                     core_rev == 9 || core_rev == 11;
+
+        if (!pciewar160 && !pciewar162)
+                return;
+
+/* TODO */
+#if 0
+        pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
+                    PCIE_DISABLE_L1CLK_GATING);
+#if 0
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
+                      PCIEGEN2_COE_PVT_TL_CTRL_0);
+        pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
+                     ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
+#endif
+#endif
+}
+
+static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
+{
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
+        pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
+}
+
+static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
+{
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
+        pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
+}
+
+static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
+{
+        struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
+        u8 core_rev = pcie2->core->id.rev;
+        u32 alp_khz, pm_value;
+
+        if (core_rev <= 13) {
+                alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
+                pm_value = (1000000 * 2) / alp_khz;
+                pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
+                              PCIE2_PVT_REG_PM_CLK_PERIOD);
+                pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
+        }
+}
+
+void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
+{
+        struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
+        u32 tmp;
+
+        tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
+        if ((tmp & 0xe) >> 1 == 2)
+                bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
+
+        /* TODO: Do we need pcie_reqsize? */
+
+        if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
+                bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
+        bcma_core_pcie2_hw_ltr_war(pcie2);
+        pciedev_crwlpciegen2(pcie2);
+        pciedev_reg_pm_clk_period(pcie2);
+        pciedev_crwlpciegen2_180(pcie2);
+        pciedev_crwlpciegen2_182(pcie2);
+}
diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c
index 34ea4c588d36..0ff8d58831ef 100644
--- a/drivers/bcma/main.c
+++ b/drivers/bcma/main.c
@@ -132,6 +132,7 @@ static int bcma_register_cores(struct bcma_bus *bus)
                 case BCMA_CORE_CHIPCOMMON:
                 case BCMA_CORE_PCI:
                 case BCMA_CORE_PCIE:
+                case BCMA_CORE_PCIE2:
                 case BCMA_CORE_MIPS_74K:
                 case BCMA_CORE_4706_MAC_GBIT_COMMON:
                         continue;
@@ -281,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *bus)
                 bcma_core_pci_init(&bus->drv_pci[1]);
         }
 
+        /* Init PCIe Gen 2 core */
+        core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
+        if (core) {
+                bus->drv_pcie2.core = core;
+                bcma_core_pcie2_init(&bus->drv_pcie2);
+        }
+
         /* Init GBIT MAC COMMON core */
         core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
         if (core) {