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authorH Hartley Sweeten <hsweeten@visionengravers.com>2014-05-29 13:56:32 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-06-18 17:56:45 -0400
commit9c340ac934dbbfd46e776465b08391baac32d486 (patch)
tree35dab4ac9042f21f091f59a9ab5954f67a3e9f63 /drivers
parent9588fa8fe908c5501de5076de9a0c9d44ef737ec (diff)
staging: comedi: ni_stc.h: add read/write callbacks to struct ni_private
The {read,write}[bwl] macros used to access the registers in the ni_atmio, ni_mio_cs, and ni_pcimio drivers and the included ni_mio_common.c file all rely on a local variable having a specific name. They also require some of the ni_mio_common code to need a __maybe_unused tag on the devpriv local variable. Remove all the macros by converting them into private functions and storing the callbacks in the private data. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/comedi/drivers/ni_atmio.c62
-rw-r--r--drivers/staging/comedi/drivers/ni_mio_common.c379
-rw-r--r--drivers/staging/comedi/drivers/ni_mio_cs.c55
-rw-r--r--drivers/staging/comedi/drivers/ni_pcimio.c118
-rw-r--r--drivers/staging/comedi/drivers/ni_stc.h7
5 files changed, 384 insertions, 237 deletions
diff --git a/drivers/staging/comedi/drivers/ni_atmio.c b/drivers/staging/comedi/drivers/ni_atmio.c
index 5b54a49c84b2..ae9ace9ee99b 100644
--- a/drivers/staging/comedi/drivers/ni_atmio.c
+++ b/drivers/staging/comedi/drivers/ni_atmio.c
@@ -272,12 +272,35 @@ static const int ni_irqpin[] = {
272 272
273/* How we access registers */ 273/* How we access registers */
274 274
275#define ni_writel(a, b) (outl((a), (b)+dev->iobase)) 275static uint8_t ni_atmio_inb(struct comedi_device *dev, int reg)
276#define ni_readl(a) (inl((a)+dev->iobase)) 276{
277#define ni_writew(a, b) (outw((a), (b)+dev->iobase)) 277 return inb(dev->iobase + reg);
278#define ni_readw(a) (inw((a)+dev->iobase)) 278}
279#define ni_writeb(a, b) (outb((a), (b)+dev->iobase)) 279
280#define ni_readb(a) (inb((a)+dev->iobase)) 280static uint16_t ni_atmio_inw(struct comedi_device *dev, int reg)
281{
282 return inw(dev->iobase + reg);
283}
284
285static uint32_t ni_atmio_inl(struct comedi_device *dev, int reg)
286{
287 return inl(dev->iobase + reg);
288}
289
290static void ni_atmio_outb(struct comedi_device *dev, uint8_t val, int reg)
291{
292 outb(val, dev->iobase + reg);
293}
294
295static void ni_atmio_outw(struct comedi_device *dev, uint16_t val, int reg)
296{
297 outw(val, dev->iobase + reg);
298}
299
300static void ni_atmio_outl(struct comedi_device *dev, uint32_t val, int reg)
301{
302 outl(val, dev->iobase + reg);
303}
281 304
282/* How we access windowed registers */ 305/* How we access windowed registers */
283 306
@@ -292,10 +315,10 @@ static void ni_atmio_win_out(struct comedi_device *dev, uint16_t data, int addr)
292 315
293 spin_lock_irqsave(&devpriv->window_lock, flags); 316 spin_lock_irqsave(&devpriv->window_lock, flags);
294 if ((addr) < 8) { 317 if ((addr) < 8) {
295 ni_writew(data, addr * 2); 318 devpriv->writew(dev, data, addr * 2);
296 } else { 319 } else {
297 ni_writew(addr, Window_Address); 320 devpriv->writew(dev, addr, Window_Address);
298 ni_writew(data, Window_Data); 321 devpriv->writew(dev, data, Window_Data);
299 } 322 }
300 spin_unlock_irqrestore(&devpriv->window_lock, flags); 323 spin_unlock_irqrestore(&devpriv->window_lock, flags);
301} 324}
@@ -308,10 +331,10 @@ static uint16_t ni_atmio_win_in(struct comedi_device *dev, int addr)
308 331
309 spin_lock_irqsave(&devpriv->window_lock, flags); 332 spin_lock_irqsave(&devpriv->window_lock, flags);
310 if (addr < 8) { 333 if (addr < 8) {
311 ret = ni_readw(addr * 2); 334 ret = devpriv->readw(dev, addr * 2);
312 } else { 335 } else {
313 ni_writew(addr, Window_Address); 336 devpriv->writew(dev, addr, Window_Address);
314 ret = ni_readw(Window_Data); 337 ret = devpriv->readw(dev, Window_Data);
315 } 338 }
316 spin_unlock_irqrestore(&devpriv->window_lock, flags); 339 spin_unlock_irqrestore(&devpriv->window_lock, flags);
317 340
@@ -405,10 +428,17 @@ static int ni_atmio_attach(struct comedi_device *dev,
405 return ret; 428 return ret;
406 devpriv = dev->private; 429 devpriv = dev->private;
407 430
408 devpriv->stc_writew = &ni_atmio_win_out; 431 devpriv->readb = ni_atmio_inb;
409 devpriv->stc_readw = &ni_atmio_win_in; 432 devpriv->readw = ni_atmio_inw;
410 devpriv->stc_writel = &win_out2; 433 devpriv->readl = ni_atmio_inl;
411 devpriv->stc_readl = &win_in2; 434 devpriv->writeb = ni_atmio_outb;
435 devpriv->writew = ni_atmio_outw;
436 devpriv->writel = ni_atmio_outl;
437
438 devpriv->stc_writew = ni_atmio_win_out;
439 devpriv->stc_readw = ni_atmio_win_in;
440 devpriv->stc_writel = win_out2;
441 devpriv->stc_readl = win_in2;
412 442
413 iobase = it->options[0]; 443 iobase = it->options[0];
414 irq = it->options[1]; 444 irq = it->options[1];
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c
index 45c42089f690..7632bd6cafc1 100644
--- a/drivers/staging/comedi/drivers/ni_mio_common.c
+++ b/drivers/staging/comedi/drivers/ni_mio_common.c
@@ -275,12 +275,12 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
275 case AI_AO_Select: 275 case AI_AO_Select:
276 devpriv->ai_ao_select_reg &= ~bit_mask; 276 devpriv->ai_ao_select_reg &= ~bit_mask;
277 devpriv->ai_ao_select_reg |= bit_values & bit_mask; 277 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
278 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); 278 devpriv->writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
279 break; 279 break;
280 case G0_G1_Select: 280 case G0_G1_Select:
281 devpriv->g0_g1_select_reg &= ~bit_mask; 281 devpriv->g0_g1_select_reg &= ~bit_mask;
282 devpriv->g0_g1_select_reg |= bit_values & bit_mask; 282 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
283 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); 283 devpriv->writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
284 break; 284 break;
285 default: 285 default:
286 printk("Warning %s() called with invalid register\n", __func__); 286 printk("Warning %s() called with invalid register\n", __func__);
@@ -356,7 +356,7 @@ static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
356 (ni_stc_dma_channel_select_bitfield(mite_channel) << 356 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
357 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; 357 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
358 } 358 }
359 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); 359 devpriv->writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
360 mmiowb(); 360 mmiowb();
361 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 361 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
362} 362}
@@ -572,11 +572,11 @@ static void ni_clear_ai_fifo(struct comedi_device *dev)
572 572
573 if (board->reg_type == ni_reg_6143) { 573 if (board->reg_type == ni_reg_6143) {
574 /* Flush the 6143 data FIFO */ 574 /* Flush the 6143 data FIFO */
575 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */ 575 devpriv->writel(dev, 0x10, AIFIFO_Control_6143);
576 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */ 576 devpriv->writel(dev, 0x00, AIFIFO_Control_6143);
577 /* Wait for complete */ 577 /* Wait for complete */
578 for (i = 0; i < timeout; i++) { 578 for (i = 0; i < timeout; i++) {
579 if (!(ni_readl(AIFIFO_Status_6143) & 0x10)) 579 if (!(devpriv->readl(dev, AIFIFO_Status_6143) & 0x10))
580 break; 580 break;
581 udelay(1); 581 udelay(1);
582 } 582 }
@@ -586,8 +586,8 @@ static void ni_clear_ai_fifo(struct comedi_device *dev)
586 } else { 586 } else {
587 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); 587 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
588 if (board->reg_type == ni_reg_625x) { 588 if (board->reg_type == ni_reg_625x) {
589 ni_writeb(0, M_Offset_Static_AI_Control(0)); 589 devpriv->writeb(dev, 0, M_Offset_Static_AI_Control(0));
590 ni_writeb(1, M_Offset_Static_AI_Control(0)); 590 devpriv->writeb(dev, 1, M_Offset_Static_AI_Control(0));
591#if 0 591#if 0
592 /* the NI example code does 3 convert pulses for 625x boards, 592 /* the NI example code does 3 convert pulses for 625x boards,
593 but that appears to be wrong in practice. */ 593 but that appears to be wrong in practice. */
@@ -628,8 +628,8 @@ static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
628 unsigned long flags; 628 unsigned long flags;
629 629
630 spin_lock_irqsave(&devpriv->window_lock, flags); 630 spin_lock_irqsave(&devpriv->window_lock, flags);
631 ni_writew(addr, AO_Window_Address_611x); 631 devpriv->writew(dev, addr, AO_Window_Address_611x);
632 ni_writew(data, AO_Window_Data_611x); 632 devpriv->writew(dev, data, AO_Window_Data_611x);
633 spin_unlock_irqrestore(&devpriv->window_lock, flags); 633 spin_unlock_irqrestore(&devpriv->window_lock, flags);
634} 634}
635 635
@@ -640,8 +640,8 @@ static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
640 unsigned long flags; 640 unsigned long flags;
641 641
642 spin_lock_irqsave(&devpriv->window_lock, flags); 642 spin_lock_irqsave(&devpriv->window_lock, flags);
643 ni_writew(addr, AO_Window_Address_611x); 643 devpriv->writew(dev, addr, AO_Window_Address_611x);
644 ni_writel(data, AO_Window_Data_611x); 644 devpriv->writel(dev, data, AO_Window_Data_611x);
645 spin_unlock_irqrestore(&devpriv->window_lock, flags); 645 spin_unlock_irqrestore(&devpriv->window_lock, flags);
646} 646}
647 647
@@ -652,8 +652,8 @@ static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
652 unsigned short data; 652 unsigned short data;
653 653
654 spin_lock_irqsave(&devpriv->window_lock, flags); 654 spin_lock_irqsave(&devpriv->window_lock, flags);
655 ni_writew(addr, AO_Window_Address_611x); 655 devpriv->writew(dev, addr, AO_Window_Address_611x);
656 data = ni_readw(AO_Window_Data_611x); 656 data = devpriv->readw(dev, AO_Window_Data_611x);
657 spin_unlock_irqrestore(&devpriv->window_lock, flags); 657 spin_unlock_irqrestore(&devpriv->window_lock, flags);
658 return data; 658 return data;
659} 659}
@@ -770,6 +770,7 @@ static void ni_ao_fifo_load(struct comedi_device *dev,
770 struct comedi_subdevice *s, int n) 770 struct comedi_subdevice *s, int n)
771{ 771{
772 const struct ni_board_struct *board = comedi_board(dev); 772 const struct ni_board_struct *board = comedi_board(dev);
773 struct ni_private *devpriv = dev->private;
773 struct comedi_async *async = s->async; 774 struct comedi_async *async = s->async;
774 struct comedi_cmd *cmd = &async->cmd; 775 struct comedi_cmd *cmd = &async->cmd;
775 int chan; 776 int chan;
@@ -798,9 +799,9 @@ static void ni_ao_fifo_load(struct comedi_device *dev,
798 i++; 799 i++;
799 packed_data |= (d << 16) & 0xffff0000; 800 packed_data |= (d << 16) & 0xffff0000;
800 } 801 }
801 ni_writel(packed_data, DAC_FIFO_Data_611x); 802 devpriv->writel(dev, packed_data, DAC_FIFO_Data_611x);
802 } else { 803 } else {
803 ni_writew(d, DAC_FIFO_Data); 804 devpriv->writew(dev, d, DAC_FIFO_Data);
804 } 805 }
805 chan++; 806 chan++;
806 chan %= cmd->chanlist_len; 807 chan %= cmd->chanlist_len;
@@ -888,7 +889,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev,
888 u32 dl; 889 u32 dl;
889 890
890 for (i = 0; i < n / 2; i++) { 891 for (i = 0; i < n / 2; i++) {
891 dl = ni_readl(ADC_FIFO_Data_611x); 892 dl = devpriv->readl(dev, ADC_FIFO_Data_611x);
892 /* This may get the hi/lo data in the wrong order */ 893 /* This may get the hi/lo data in the wrong order */
893 data[0] = (dl >> 16) & 0xffff; 894 data[0] = (dl >> 16) & 0xffff;
894 data[1] = dl & 0xffff; 895 data[1] = dl & 0xffff;
@@ -896,7 +897,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev,
896 } 897 }
897 /* Check if there's a single sample stuck in the FIFO */ 898 /* Check if there's a single sample stuck in the FIFO */
898 if (n % 2) { 899 if (n % 2) {
899 dl = ni_readl(ADC_FIFO_Data_611x); 900 dl = devpriv->readl(dev, ADC_FIFO_Data_611x);
900 data[0] = dl & 0xffff; 901 data[0] = dl & 0xffff;
901 cfc_write_to_buffer(s, data[0]); 902 cfc_write_to_buffer(s, data[0]);
902 } 903 }
@@ -906,7 +907,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev,
906 907
907 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ 908 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
908 for (i = 0; i < n / 2; i++) { 909 for (i = 0; i < n / 2; i++) {
909 dl = ni_readl(AIFIFO_Data_6143); 910 dl = devpriv->readl(dev, AIFIFO_Data_6143);
910 911
911 data[0] = (dl >> 16) & 0xffff; 912 data[0] = (dl >> 16) & 0xffff;
912 data[1] = dl & 0xffff; 913 data[1] = dl & 0xffff;
@@ -914,8 +915,9 @@ static void ni_ai_fifo_read(struct comedi_device *dev,
914 } 915 }
915 if (n % 2) { 916 if (n % 2) {
916 /* Assume there is a single sample stuck in the FIFO */ 917 /* Assume there is a single sample stuck in the FIFO */
917 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 918 /* Get stranded sample into FIFO */
918 dl = ni_readl(AIFIFO_Data_6143); 919 devpriv->writel(dev, 0x01, AIFIFO_Control_6143);
920 dl = devpriv->readl(dev, AIFIFO_Data_6143);
919 data[0] = (dl >> 16) & 0xffff; 921 data[0] = (dl >> 16) & 0xffff;
920 cfc_write_to_buffer(s, data[0]); 922 cfc_write_to_buffer(s, data[0]);
921 } 923 }
@@ -928,7 +930,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev,
928 } 930 }
929 for (i = 0; i < n; i++) { 931 for (i = 0; i < n; i++) {
930 devpriv->ai_fifo_buffer[i] = 932 devpriv->ai_fifo_buffer[i] =
931 ni_readw(ADC_FIFO_Data_Register); 933 devpriv->readw(dev, ADC_FIFO_Data_Register);
932 } 934 }
933 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 935 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
934 n * 936 n *
@@ -965,7 +967,7 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev)
965 while ((devpriv->stc_readw(dev, 967 while ((devpriv->stc_readw(dev,
966 AI_Status_1_Register) & 968 AI_Status_1_Register) &
967 AI_FIFO_Empty_St) == 0) { 969 AI_FIFO_Empty_St) == 0) {
968 dl = ni_readl(ADC_FIFO_Data_611x); 970 dl = devpriv->readl(dev, ADC_FIFO_Data_611x);
969 971
970 /* This may get the hi/lo data in the wrong order */ 972 /* This may get the hi/lo data in the wrong order */
971 data[0] = (dl >> 16); 973 data[0] = (dl >> 16);
@@ -974,8 +976,8 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev)
974 } 976 }
975 } else if (board->reg_type == ni_reg_6143) { 977 } else if (board->reg_type == ni_reg_6143) {
976 i = 0; 978 i = 0;
977 while (ni_readl(AIFIFO_Status_6143) & 0x04) { 979 while (devpriv->readl(dev, AIFIFO_Status_6143) & 0x04) {
978 dl = ni_readl(AIFIFO_Data_6143); 980 dl = devpriv->readl(dev, AIFIFO_Data_6143);
979 981
980 /* This may get the hi/lo data in the wrong order */ 982 /* This may get the hi/lo data in the wrong order */
981 data[0] = (dl >> 16); 983 data[0] = (dl >> 16);
@@ -984,9 +986,10 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev)
984 i += 2; 986 i += 2;
985 } 987 }
986 /* Check if stranded sample is present */ 988 /* Check if stranded sample is present */
987 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 989 if (devpriv->readl(dev, AIFIFO_Status_6143) & 0x01) {
988 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 990 /* Get stranded sample into FIFO */
989 dl = ni_readl(AIFIFO_Data_6143); 991 devpriv->writel(dev, 0x01, AIFIFO_Control_6143);
992 dl = devpriv->readl(dev, AIFIFO_Data_6143);
990 data[0] = (dl >> 16) & 0xffff; 993 data[0] = (dl >> 16) & 0xffff;
991 cfc_write_to_buffer(s, data[0]); 994 cfc_write_to_buffer(s, data[0]);
992 } 995 }
@@ -1007,7 +1010,7 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev)
1007 if (fifo_empty) 1010 if (fifo_empty)
1008 break; 1011 break;
1009 devpriv->ai_fifo_buffer[i] = 1012 devpriv->ai_fifo_buffer[i] =
1010 ni_readw(ADC_FIFO_Data_Register); 1013 devpriv->readw(dev, ADC_FIFO_Data_Register);
1011 } 1014 }
1012 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1015 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1013 i * 1016 i *
@@ -1020,7 +1023,7 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev)
1020static void get_last_sample_611x(struct comedi_device *dev) 1023static void get_last_sample_611x(struct comedi_device *dev)
1021{ 1024{
1022 const struct ni_board_struct *board = comedi_board(dev); 1025 const struct ni_board_struct *board = comedi_board(dev);
1023 struct ni_private *devpriv __maybe_unused = dev->private; 1026 struct ni_private *devpriv = dev->private;
1024 struct comedi_subdevice *s = dev->read_subdev; 1027 struct comedi_subdevice *s = dev->read_subdev;
1025 unsigned short data; 1028 unsigned short data;
1026 u32 dl; 1029 u32 dl;
@@ -1029,8 +1032,8 @@ static void get_last_sample_611x(struct comedi_device *dev)
1029 return; 1032 return;
1030 1033
1031 /* Check if there's a single sample stuck in the FIFO */ 1034 /* Check if there's a single sample stuck in the FIFO */
1032 if (ni_readb(XXX_Status) & 0x80) { 1035 if (devpriv->readb(dev, XXX_Status) & 0x80) {
1033 dl = ni_readl(ADC_FIFO_Data_611x); 1036 dl = devpriv->readl(dev, ADC_FIFO_Data_611x);
1034 data = (dl & 0xffff); 1037 data = (dl & 0xffff);
1035 cfc_write_to_buffer(s, data); 1038 cfc_write_to_buffer(s, data);
1036 } 1039 }
@@ -1039,7 +1042,7 @@ static void get_last_sample_611x(struct comedi_device *dev)
1039static void get_last_sample_6143(struct comedi_device *dev) 1042static void get_last_sample_6143(struct comedi_device *dev)
1040{ 1043{
1041 const struct ni_board_struct *board = comedi_board(dev); 1044 const struct ni_board_struct *board = comedi_board(dev);
1042 struct ni_private *devpriv __maybe_unused = dev->private; 1045 struct ni_private *devpriv = dev->private;
1043 struct comedi_subdevice *s = dev->read_subdev; 1046 struct comedi_subdevice *s = dev->read_subdev;
1044 unsigned short data; 1047 unsigned short data;
1045 u32 dl; 1048 u32 dl;
@@ -1048,9 +1051,10 @@ static void get_last_sample_6143(struct comedi_device *dev)
1048 return; 1051 return;
1049 1052
1050 /* Check if there's a single sample stuck in the FIFO */ 1053 /* Check if there's a single sample stuck in the FIFO */
1051 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1054 if (devpriv->readl(dev, AIFIFO_Status_6143) & 0x01) {
1052 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1055 /* Get stranded sample into FIFO */
1053 dl = ni_readl(AIFIFO_Data_6143); 1056 devpriv->writel(dev, 0x01, AIFIFO_Control_6143);
1057 dl = devpriv->readl(dev, AIFIFO_Data_6143);
1054 1058
1055 /* This may get the hi/lo data in the wrong order */ 1059 /* This may get the hi/lo data in the wrong order */
1056 data = (dl >> 16) & 0xffff; 1060 data = (dl >> 16) & 0xffff;
@@ -1416,7 +1420,7 @@ static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1416 ni_clear_ai_fifo(dev); 1420 ni_clear_ai_fifo(dev);
1417 1421
1418 if (board->reg_type != ni_reg_6143) 1422 if (board->reg_type != ni_reg_6143)
1419 ni_writeb(0, Misc_Command); 1423 devpriv->writeb(dev, 0, Misc_Command);
1420 1424
1421 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ 1425 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1422 devpriv->stc_writew(dev, 1426 devpriv->stc_writew(dev,
@@ -1560,9 +1564,10 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1560 bypass_bits |= MSeries_AI_Bypass_Dither_Bit; 1564 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1561 /* don't use 2's complement encoding */ 1565 /* don't use 2's complement encoding */
1562 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; 1566 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1563 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass); 1567 devpriv->writel(dev, bypass_bits,
1568 M_Offset_AI_Config_FIFO_Bypass);
1564 } else { 1569 } else {
1565 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass); 1570 devpriv->writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass);
1566 } 1571 }
1567 offset = 0; 1572 offset = 0;
1568 for (i = 0; i < n_chan; i++) { 1573 for (i = 0; i < n_chan; i++) {
@@ -1600,7 +1605,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1600 config_bits |= MSeries_AI_Config_Dither_Bit; 1605 config_bits |= MSeries_AI_Config_Dither_Bit;
1601 /* don't use 2's complement encoding */ 1606 /* don't use 2's complement encoding */
1602 config_bits |= MSeries_AI_Config_Polarity_Bit; 1607 config_bits |= MSeries_AI_Config_Polarity_Bit;
1603 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data); 1608 devpriv->writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data);
1604 } 1609 }
1605 ni_prime_channelgain_list(dev); 1610 ni_prime_channelgain_list(dev);
1606} 1611}
@@ -1669,21 +1674,21 @@ static void ni_load_channelgain_list(struct comedi_device *dev,
1669 if ((list[0] & CR_ALT_SOURCE) 1674 if ((list[0] & CR_ALT_SOURCE)
1670 && !devpriv->ai_calib_source_enabled) { 1675 && !devpriv->ai_calib_source_enabled) {
1671 /* Strobe Relay enable bit */ 1676 /* Strobe Relay enable bit */
1672 ni_writew(devpriv->ai_calib_source | 1677 devpriv->writew(dev, devpriv->ai_calib_source |
1673 Calibration_Channel_6143_RelayOn, 1678 Calibration_Channel_6143_RelayOn,
1674 Calibration_Channel_6143); 1679 Calibration_Channel_6143);
1675 ni_writew(devpriv->ai_calib_source, 1680 devpriv->writew(dev, devpriv->ai_calib_source,
1676 Calibration_Channel_6143); 1681 Calibration_Channel_6143);
1677 devpriv->ai_calib_source_enabled = 1; 1682 devpriv->ai_calib_source_enabled = 1;
1678 msleep_interruptible(100); /* Allow relays to change */ 1683 msleep_interruptible(100); /* Allow relays to change */
1679 } else if (!(list[0] & CR_ALT_SOURCE) 1684 } else if (!(list[0] & CR_ALT_SOURCE)
1680 && devpriv->ai_calib_source_enabled) { 1685 && devpriv->ai_calib_source_enabled) {
1681 /* Strobe Relay disable bit */ 1686 /* Strobe Relay disable bit */
1682 ni_writew(devpriv->ai_calib_source | 1687 devpriv->writew(dev, devpriv->ai_calib_source |
1683 Calibration_Channel_6143_RelayOff, 1688 Calibration_Channel_6143_RelayOff,
1684 Calibration_Channel_6143); 1689 Calibration_Channel_6143);
1685 ni_writew(devpriv->ai_calib_source, 1690 devpriv->writew(dev, devpriv->ai_calib_source,
1686 Calibration_Channel_6143); 1691 Calibration_Channel_6143);
1687 devpriv->ai_calib_source_enabled = 0; 1692 devpriv->ai_calib_source_enabled = 0;
1688 msleep_interruptible(100); /* Allow relays to change */ 1693 msleep_interruptible(100); /* Allow relays to change */
1689 } 1694 }
@@ -1711,8 +1716,8 @@ static void ni_load_channelgain_list(struct comedi_device *dev,
1711 hi = 0; 1716 hi = 0;
1712 if ((list[i] & CR_ALT_SOURCE)) { 1717 if ((list[i] & CR_ALT_SOURCE)) {
1713 if (board->reg_type == ni_reg_611x) 1718 if (board->reg_type == ni_reg_611x)
1714 ni_writew(CR_CHAN(list[i]) & 0x0003, 1719 devpriv->writew(dev, CR_CHAN(list[i]) & 0x0003,
1715 Calibration_Channel_Select_611x); 1720 Calibration_Channel_Select_611x);
1716 } else { 1721 } else {
1717 if (board->reg_type == ni_reg_611x) 1722 if (board->reg_type == ni_reg_611x)
1718 aref = AREF_DIFF; 1723 aref = AREF_DIFF;
@@ -1734,7 +1739,7 @@ static void ni_load_channelgain_list(struct comedi_device *dev,
1734 } 1739 }
1735 hi |= AI_CONFIG_CHANNEL(chan); 1740 hi |= AI_CONFIG_CHANNEL(chan);
1736 1741
1737 ni_writew(hi, Configuration_Memory_High); 1742 devpriv->writew(dev, hi, Configuration_Memory_High);
1738 1743
1739 if (board->reg_type != ni_reg_6143) { 1744 if (board->reg_type != ni_reg_6143) {
1740 lo = range; 1745 lo = range;
@@ -1743,7 +1748,7 @@ static void ni_load_channelgain_list(struct comedi_device *dev,
1743 if (dither) 1748 if (dither)
1744 lo |= AI_DITHER; 1749 lo |= AI_DITHER;
1745 1750
1746 ni_writew(lo, Configuration_Memory_Low); 1751 devpriv->writew(dev, lo, Configuration_Memory_Low);
1747 } 1752 }
1748 } 1753 }
1749 1754
@@ -1784,16 +1789,19 @@ static int ni_ai_insn_read(struct comedi_device *dev,
1784 /* The 611x has screwy 32-bit FIFOs. */ 1789 /* The 611x has screwy 32-bit FIFOs. */
1785 d = 0; 1790 d = 0;
1786 for (i = 0; i < NI_TIMEOUT; i++) { 1791 for (i = 0; i < NI_TIMEOUT; i++) {
1787 if (ni_readb(XXX_Status) & 0x80) { 1792 if (devpriv->readb(dev, XXX_Status) & 0x80) {
1788 d = (ni_readl(ADC_FIFO_Data_611x) >> 16) 1793 d = devpriv->readl(dev,
1789 & 0xffff; 1794 ADC_FIFO_Data_611x);
1795 d >>= 16;
1796 d &= 0xffff;
1790 break; 1797 break;
1791 } 1798 }
1792 if (!(devpriv->stc_readw(dev, 1799 if (!(devpriv->stc_readw(dev,
1793 AI_Status_1_Register) & 1800 AI_Status_1_Register) &
1794 AI_FIFO_Empty_St)) { 1801 AI_FIFO_Empty_St)) {
1795 d = ni_readl(ADC_FIFO_Data_611x) & 1802 d = devpriv->readl(dev,
1796 0xffff; 1803 ADC_FIFO_Data_611x);
1804 d &= 0xffff;
1797 break; 1805 break;
1798 } 1806 }
1799 } 1807 }
@@ -1813,9 +1821,13 @@ static int ni_ai_insn_read(struct comedi_device *dev,
1813 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ 1821 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1814 dl = 0; 1822 dl = 0;
1815 for (i = 0; i < NI_TIMEOUT; i++) { 1823 for (i = 0; i < NI_TIMEOUT; i++) {
1816 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1824 if (devpriv->readl(dev, AIFIFO_Status_6143) &
1817 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1825 0x01) {
1818 dl = ni_readl(AIFIFO_Data_6143); 1826 /* Get stranded sample into FIFO */
1827 devpriv->writel(dev, 0x01,
1828 AIFIFO_Control_6143);
1829 dl = devpriv->readl(dev,
1830 AIFIFO_Data_6143);
1819 break; 1831 break;
1820 } 1832 }
1821 } 1833 }
@@ -1842,10 +1854,11 @@ static int ni_ai_insn_read(struct comedi_device *dev,
1842 return -ETIME; 1854 return -ETIME;
1843 } 1855 }
1844 if (board->reg_type & ni_reg_m_series_mask) { 1856 if (board->reg_type & ni_reg_m_series_mask) {
1845 data[n] = 1857 dl = devpriv->readl(dev, M_Offset_AI_FIFO_Data);
1846 ni_readl(M_Offset_AI_FIFO_Data) & mask; 1858 dl &= mask;
1859 data[n] = dl;
1847 } else { 1860 } else {
1848 d = ni_readw(ADC_FIFO_Data_Register); 1861 d = devpriv->readw(dev, ADC_FIFO_Data_Register);
1849 d += signbits; /* subtle: needs to be short addition */ 1862 d += signbits; /* subtle: needs to be short addition */
1850 data[n] = d; 1863 data[n] = d;
1851 } 1864 }
@@ -2500,7 +2513,8 @@ static int ni_ai_insn_config(struct comedi_device *dev,
2500 return -EINVAL; 2513 return -EINVAL;
2501 2514
2502 devpriv->ai_calib_source = calib_source; 2515 devpriv->ai_calib_source = calib_source;
2503 ni_writew(calib_source, Calibration_Channel_6143); 2516 devpriv->writew(dev, calib_source,
2517 Calibration_Channel_6143);
2504 } else { 2518 } else {
2505 unsigned int calib_source; 2519 unsigned int calib_source;
2506 unsigned int calib_source_adjust; 2520 unsigned int calib_source_adjust;
@@ -2512,8 +2526,8 @@ static int ni_ai_insn_config(struct comedi_device *dev,
2512 return -EINVAL; 2526 return -EINVAL;
2513 devpriv->ai_calib_source = calib_source; 2527 devpriv->ai_calib_source = calib_source;
2514 if (board->reg_type == ni_reg_611x) { 2528 if (board->reg_type == ni_reg_611x) {
2515 ni_writeb(calib_source_adjust, 2529 devpriv->writeb(dev, calib_source_adjust,
2516 Cal_Gain_Select_611x); 2530 Cal_Gain_Select_611x);
2517 } 2531 }
2518 } 2532 }
2519 return 2; 2533 return 2;
@@ -2566,9 +2580,10 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2566 if (timed) { 2580 if (timed) {
2567 for (i = 0; i < board->n_aochan; ++i) { 2581 for (i = 0; i < board->n_aochan; ++i) {
2568 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; 2582 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2569 ni_writeb(devpriv->ao_conf[i], 2583 devpriv->writeb(dev, devpriv->ao_conf[i],
2570 M_Offset_AO_Config_Bank(i)); 2584 M_Offset_AO_Config_Bank(i));
2571 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i)); 2585 devpriv->writeb(dev, 0xf,
2586 M_Offset_AO_Waveform_Order(i));
2572 } 2587 }
2573 } 2588 }
2574 for (i = 0; i < n_chans; i++) { 2589 for (i = 0; i < n_chans; i++) {
@@ -2581,21 +2596,23 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2581 switch (krange->max - krange->min) { 2596 switch (krange->max - krange->min) {
2582 case 20000000: 2597 case 20000000:
2583 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2598 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2584 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); 2599 devpriv->writeb(dev, 0,
2600 M_Offset_AO_Reference_Attenuation(chan));
2585 break; 2601 break;
2586 case 10000000: 2602 case 10000000:
2587 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2603 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2588 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); 2604 devpriv->writeb(dev, 0,
2605 M_Offset_AO_Reference_Attenuation(chan));
2589 break; 2606 break;
2590 case 4000000: 2607 case 4000000:
2591 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2608 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2592 ni_writeb(MSeries_Attenuate_x5_Bit, 2609 devpriv->writeb(dev, MSeries_Attenuate_x5_Bit,
2593 M_Offset_AO_Reference_Attenuation(chan)); 2610 M_Offset_AO_Reference_Attenuation(chan));
2594 break; 2611 break;
2595 case 2000000: 2612 case 2000000:
2596 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2613 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2597 ni_writeb(MSeries_Attenuate_x5_Bit, 2614 devpriv->writeb(dev, MSeries_Attenuate_x5_Bit,
2598 M_Offset_AO_Reference_Attenuation(chan)); 2615 M_Offset_AO_Reference_Attenuation(chan));
2599 break; 2616 break;
2600 default: 2617 default:
2601 printk("%s: bug! unhandled ao reference voltage\n", 2618 printk("%s: bug! unhandled ao reference voltage\n",
@@ -2616,9 +2633,9 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2616 } 2633 }
2617 if (timed) 2634 if (timed)
2618 conf |= MSeries_AO_Update_Timed_Bit; 2635 conf |= MSeries_AO_Update_Timed_Bit;
2619 ni_writeb(conf, M_Offset_AO_Config_Bank(chan)); 2636 devpriv->writeb(dev, conf, M_Offset_AO_Config_Bank(chan));
2620 devpriv->ao_conf[chan] = conf; 2637 devpriv->ao_conf[chan] = conf;
2621 ni_writeb(i, M_Offset_AO_Waveform_Order(chan)); 2638 devpriv->writeb(dev, i, M_Offset_AO_Waveform_Order(chan));
2622 } 2639 }
2623 return invert; 2640 return invert;
2624} 2641}
@@ -2664,7 +2681,7 @@ static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2664 conf |= (CR_AREF(chanspec[i]) == 2681 conf |= (CR_AREF(chanspec[i]) ==
2665 AREF_OTHER) ? AO_Ground_Ref : 0; 2682 AREF_OTHER) ? AO_Ground_Ref : 0;
2666 2683
2667 ni_writew(conf, AO_Configuration); 2684 devpriv->writew(dev, conf, AO_Configuration);
2668 devpriv->ao_conf[chan] = conf; 2685 devpriv->ao_conf[chan] = conf;
2669 } 2686 }
2670 return invert; 2687 return invert;
@@ -2709,10 +2726,10 @@ static int ni_ao_insn_write(struct comedi_device *dev,
2709 devpriv->ao[chan] = data[0]; 2726 devpriv->ao[chan] = data[0];
2710 2727
2711 if (board->reg_type & ni_reg_m_series_mask) { 2728 if (board->reg_type & ni_reg_m_series_mask) {
2712 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan)); 2729 devpriv->writew(dev, data[0], M_Offset_DAC_Direct_Data(chan));
2713 } else 2730 } else
2714 ni_writew(data[0] ^ invert, 2731 devpriv->writew(dev, data[0] ^ invert,
2715 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data); 2732 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2716 2733
2717 return 1; 2734 return 1;
2718} 2735}
@@ -3225,14 +3242,14 @@ static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3225 struct comedi_insn *insn, 3242 struct comedi_insn *insn,
3226 unsigned int *data) 3243 unsigned int *data)
3227{ 3244{
3228 struct ni_private *devpriv __maybe_unused = dev->private; 3245 struct ni_private *devpriv = dev->private;
3229 int ret; 3246 int ret;
3230 3247
3231 ret = comedi_dio_insn_config(dev, s, insn, data, 0); 3248 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3232 if (ret) 3249 if (ret)
3233 return ret; 3250 return ret;
3234 3251
3235 ni_writel(s->io_bits, M_Offset_DIO_Direction); 3252 devpriv->writel(dev, s->io_bits, M_Offset_DIO_Direction);
3236 3253
3237 return insn->n; 3254 return insn->n;
3238} 3255}
@@ -3242,12 +3259,12 @@ static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3242 struct comedi_insn *insn, 3259 struct comedi_insn *insn,
3243 unsigned int *data) 3260 unsigned int *data)
3244{ 3261{
3245 struct ni_private *devpriv __maybe_unused = dev->private; 3262 struct ni_private *devpriv = dev->private;
3246 3263
3247 if (comedi_dio_update_state(s, data)) 3264 if (comedi_dio_update_state(s, data))
3248 ni_writel(s->state, M_Offset_Static_Digital_Output); 3265 devpriv->writel(dev, s->state, M_Offset_Static_Digital_Output);
3249 3266
3250 data[1] = ni_readl(M_Offset_Static_Digital_Input); 3267 data[1] = devpriv->readl(dev, M_Offset_Static_Digital_Input);
3251 3268
3252 return insn->n; 3269 return insn->n;
3253} 3270}
@@ -3326,14 +3343,14 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
3326 struct comedi_subdevice *s, 3343 struct comedi_subdevice *s,
3327 unsigned int trig_num) 3344 unsigned int trig_num)
3328{ 3345{
3329#ifdef PCIDMA
3330 struct ni_private *devpriv = dev->private; 3346 struct ni_private *devpriv = dev->private;
3331 unsigned long flags;
3332#endif
3333 struct comedi_cmd *cmd = &s->async->cmd; 3347 struct comedi_cmd *cmd = &s->async->cmd;
3348 const unsigned timeout = 1000;
3334 int retval = 0; 3349 int retval = 0;
3335 unsigned i; 3350 unsigned i;
3336 const unsigned timeout = 1000; 3351#ifdef PCIDMA
3352 unsigned long flags;
3353#endif
3337 3354
3338 if (trig_num != cmd->start_arg) 3355 if (trig_num != cmd->start_arg)
3339 return -EINVAL; 3356 return -EINVAL;
@@ -3358,11 +3375,12 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
3358#endif 3375#endif
3359/* 3376/*
3360* XXX not sure what interrupt C group does 3377* XXX not sure what interrupt C group does
3361* ni_writeb(Interrupt_Group_C_Enable_Bit, 3378* devpriv->writeb(dev, Interrupt_Group_C_Enable_Bit,
3362* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo 3379* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3363*/ 3380*/
3364 for (i = 0; i < timeout; ++i) { 3381 for (i = 0; i < timeout; ++i) {
3365 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) 3382 if (devpriv->readl(dev, M_Offset_CDIO_Status) &
3383 CDO_FIFO_Full_Bit)
3366 break; 3384 break;
3367 udelay(10); 3385 udelay(10);
3368 } 3386 }
@@ -3371,20 +3389,20 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
3371 s->cancel(dev, s); 3389 s->cancel(dev, s);
3372 return -EIO; 3390 return -EIO;
3373 } 3391 }
3374 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | 3392 devpriv->writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3375 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, 3393 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3376 M_Offset_CDIO_Command); 3394 M_Offset_CDIO_Command);
3377 return retval; 3395 return retval;
3378} 3396}
3379 3397
3380static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3398static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3381{ 3399{
3382 struct ni_private *devpriv __maybe_unused = dev->private; 3400 struct ni_private *devpriv = dev->private;
3383 const struct comedi_cmd *cmd = &s->async->cmd; 3401 const struct comedi_cmd *cmd = &s->async->cmd;
3384 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; 3402 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3385 int retval; 3403 int retval;
3386 3404
3387 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command); 3405 devpriv->writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command);
3388 switch (cmd->scan_begin_src) { 3406 switch (cmd->scan_begin_src) {
3389 case TRIG_EXT: 3407 case TRIG_EXT:
3390 cdo_mode_bits |= 3408 cdo_mode_bits |=
@@ -3397,11 +3415,11 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3397 } 3415 }
3398 if (cmd->scan_begin_arg & CR_INVERT) 3416 if (cmd->scan_begin_arg & CR_INVERT)
3399 cdo_mode_bits |= CDO_Polarity_Bit; 3417 cdo_mode_bits |= CDO_Polarity_Bit;
3400 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode); 3418 devpriv->writel(dev, cdo_mode_bits, M_Offset_CDO_Mode);
3401 if (s->io_bits) { 3419 if (s->io_bits) {
3402 ni_writel(s->state, M_Offset_CDO_FIFO_Data); 3420 devpriv->writel(dev, s->state, M_Offset_CDO_FIFO_Data);
3403 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command); 3421 devpriv->writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3404 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable); 3422 devpriv->writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable);
3405 } else { 3423 } else {
3406 comedi_error(dev, 3424 comedi_error(dev,
3407 "attempted to run digital output command with no lines configured as outputs"); 3425 "attempted to run digital output command with no lines configured as outputs");
@@ -3418,17 +3436,18 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3418 3436
3419static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3437static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3420{ 3438{
3421 struct ni_private *devpriv __maybe_unused = dev->private; 3439 struct ni_private *devpriv = dev->private;
3422 3440
3423 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | 3441 devpriv->writel(dev, CDO_Disarm_Bit |
3424 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | 3442 CDO_Error_Interrupt_Enable_Clear_Bit |
3425 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, 3443 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3426 M_Offset_CDIO_Command); 3444 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3445 M_Offset_CDIO_Command);
3427/* 3446/*
3428* XXX not sure what interrupt C group does ni_writeb(0, 3447* XXX not sure what interrupt C group does devpriv->writeb(dev, 0,
3429* M_Offset_Interrupt_C_Enable); 3448* M_Offset_Interrupt_C_Enable);
3430*/ 3449*/
3431 ni_writel(0, M_Offset_CDO_Mask_Enable); 3450 devpriv->writel(dev, 0, M_Offset_CDO_Mask_Enable);
3432 ni_release_cdo_mite_channel(dev); 3451 ni_release_cdo_mite_channel(dev);
3433 return 0; 3452 return 0;
3434} 3453}
@@ -3436,7 +3455,7 @@ static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3436static void handle_cdio_interrupt(struct comedi_device *dev) 3455static void handle_cdio_interrupt(struct comedi_device *dev)
3437{ 3456{
3438 const struct ni_board_struct *board = comedi_board(dev); 3457 const struct ni_board_struct *board = comedi_board(dev);
3439 struct ni_private *devpriv __maybe_unused = dev->private; 3458 struct ni_private *devpriv = dev->private;
3440 unsigned cdio_status; 3459 unsigned cdio_status;
3441 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; 3460 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3442#ifdef PCIDMA 3461#ifdef PCIDMA
@@ -3460,16 +3479,18 @@ static void handle_cdio_interrupt(struct comedi_device *dev)
3460 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3479 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3461#endif 3480#endif
3462 3481
3463 cdio_status = ni_readl(M_Offset_CDIO_Status); 3482 cdio_status = devpriv->readl(dev, M_Offset_CDIO_Status);
3464 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { 3483 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3465 /* printk("cdio error: statux=0x%x\n", cdio_status); */ 3484 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3466 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */ 3485 /* XXX just guessing this is needed and does something useful */
3486 devpriv->writel(dev, CDO_Error_Interrupt_Confirm_Bit,
3487 M_Offset_CDIO_Command);
3467 s->async->events |= COMEDI_CB_OVERFLOW; 3488 s->async->events |= COMEDI_CB_OVERFLOW;
3468 } 3489 }
3469 if (cdio_status & CDO_FIFO_Empty_Bit) { 3490 if (cdio_status & CDO_FIFO_Empty_Bit) {
3470 /* printk("cdio fifo empty\n"); */ 3491 /* printk("cdio fifo empty\n"); */
3471 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, 3492 devpriv->writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3472 M_Offset_CDIO_Command); 3493 M_Offset_CDIO_Command);
3473 /* s->async->events |= COMEDI_CB_EOA; */ 3494 /* s->async->events |= COMEDI_CB_EOA; */
3474 } 3495 }
3475 cfc_handle_events(dev, s); 3496 cfc_handle_events(dev, s);
@@ -3786,28 +3807,28 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3786 switch (reg) { 3807 switch (reg) {
3787 /* m-series-only registers */ 3808 /* m-series-only registers */
3788 case NITIO_G0_CNT_MODE: 3809 case NITIO_G0_CNT_MODE:
3789 ni_writew(bits, M_Offset_G0_Counting_Mode); 3810 devpriv->writew(dev, bits, M_Offset_G0_Counting_Mode);
3790 break; 3811 break;
3791 case NITIO_G1_CNT_MODE: 3812 case NITIO_G1_CNT_MODE:
3792 ni_writew(bits, M_Offset_G1_Counting_Mode); 3813 devpriv->writew(dev, bits, M_Offset_G1_Counting_Mode);
3793 break; 3814 break;
3794 case NITIO_G0_GATE2: 3815 case NITIO_G0_GATE2:
3795 ni_writew(bits, M_Offset_G0_Second_Gate); 3816 devpriv->writew(dev, bits, M_Offset_G0_Second_Gate);
3796 break; 3817 break;
3797 case NITIO_G1_GATE2: 3818 case NITIO_G1_GATE2:
3798 ni_writew(bits, M_Offset_G1_Second_Gate); 3819 devpriv->writew(dev, bits, M_Offset_G1_Second_Gate);
3799 break; 3820 break;
3800 case NITIO_G0_DMA_CFG: 3821 case NITIO_G0_DMA_CFG:
3801 ni_writew(bits, M_Offset_G0_DMA_Config); 3822 devpriv->writew(dev, bits, M_Offset_G0_DMA_Config);
3802 break; 3823 break;
3803 case NITIO_G1_DMA_CFG: 3824 case NITIO_G1_DMA_CFG:
3804 ni_writew(bits, M_Offset_G1_DMA_Config); 3825 devpriv->writew(dev, bits, M_Offset_G1_DMA_Config);
3805 break; 3826 break;
3806 case NITIO_G0_ABZ: 3827 case NITIO_G0_ABZ:
3807 ni_writew(bits, M_Offset_G0_MSeries_ABZ); 3828 devpriv->writew(dev, bits, M_Offset_G0_MSeries_ABZ);
3808 break; 3829 break;
3809 case NITIO_G1_ABZ: 3830 case NITIO_G1_ABZ:
3810 ni_writew(bits, M_Offset_G1_MSeries_ABZ); 3831 devpriv->writew(dev, bits, M_Offset_G1_MSeries_ABZ);
3811 break; 3832 break;
3812 3833
3813 /* 32 bit registers */ 3834 /* 32 bit registers */
@@ -3849,9 +3870,9 @@ static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3849 switch (reg) { 3870 switch (reg) {
3850 /* m-series only registers */ 3871 /* m-series only registers */
3851 case NITIO_G0_DMA_STATUS: 3872 case NITIO_G0_DMA_STATUS:
3852 return ni_readw(M_Offset_G0_DMA_Status); 3873 return devpriv->readw(dev, M_Offset_G0_DMA_Status);
3853 case NITIO_G1_DMA_STATUS: 3874 case NITIO_G1_DMA_STATUS:
3854 return ni_readw(M_Offset_G1_DMA_Status); 3875 return devpriv->readw(dev, M_Offset_G1_DMA_Status);
3855 3876
3856 /* 32 bit registers */ 3877 /* 32 bit registers */
3857 case NITIO_G0_HW_SAVE: 3878 case NITIO_G0_HW_SAVE:
@@ -3948,13 +3969,13 @@ static int ni_freq_out_insn_config(struct comedi_device *dev,
3948static int ni_8255_callback(int dir, int port, int data, unsigned long arg) 3969static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
3949{ 3970{
3950 struct comedi_device *dev = (struct comedi_device *)arg; 3971 struct comedi_device *dev = (struct comedi_device *)arg;
3951 struct ni_private *devpriv __maybe_unused = dev->private; 3972 struct ni_private *devpriv = dev->private;
3952 3973
3953 if (dir) { 3974 if (dir) {
3954 ni_writeb(data, Port_A + 2 * port); 3975 devpriv->writeb(dev, data, Port_A + 2 * port);
3955 return 0; 3976 return 0;
3956 } else { 3977 } else {
3957 return ni_readb(Port_A + 2 * port); 3978 return devpriv->readb(dev, Port_A + 2 * port);
3958 } 3979 }
3959} 3980}
3960 3981
@@ -4019,9 +4040,9 @@ static int ni_m_series_pwm_config(struct comedi_device *dev,
4019 data[4] = down_count * devpriv->clock_ns; 4040 data[4] = down_count * devpriv->clock_ns;
4020 return -EAGAIN; 4041 return -EAGAIN;
4021 } 4042 }
4022 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | 4043 devpriv->writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
4023 MSeries_Cal_PWM_Low_Time_Bits(down_count), 4044 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4024 M_Offset_Cal_PWM); 4045 M_Offset_Cal_PWM);
4025 devpriv->pwm_up_count = up_count; 4046 devpriv->pwm_up_count = up_count;
4026 devpriv->pwm_down_count = down_count; 4047 devpriv->pwm_down_count = down_count;
4027 return 5; 4048 return 5;
@@ -4088,9 +4109,9 @@ static int ni_6143_pwm_config(struct comedi_device *dev,
4088 data[4] = down_count * devpriv->clock_ns; 4109 data[4] = down_count * devpriv->clock_ns;
4089 return -EAGAIN; 4110 return -EAGAIN;
4090 } 4111 }
4091 ni_writel(up_count, Calibration_HighTime_6143); 4112 devpriv->writel(dev, up_count, Calibration_HighTime_6143);
4092 devpriv->pwm_up_count = up_count; 4113 devpriv->pwm_up_count = up_count;
4093 ni_writel(down_count, Calibration_LowTime_6143); 4114 devpriv->writel(dev, down_count, Calibration_LowTime_6143);
4094 devpriv->pwm_down_count = down_count; 4115 devpriv->pwm_down_count = down_count;
4095 return 5; 4116 return 5;
4096 break; 4117 break;
@@ -4194,14 +4215,16 @@ static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4194 } 4215 }
4195 4216
4196 for (bit = 1 << (bits - 1); bit; bit >>= 1) { 4217 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4197 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command); 4218 devpriv->writeb(dev, ((bit & bitstring) ? 0x02 : 0),
4219 Serial_Command);
4198 udelay(1); 4220 udelay(1);
4199 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command); 4221 devpriv->writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4222 Serial_Command);
4200 udelay(1); 4223 udelay(1);
4201 } 4224 }
4202 ni_writeb(loadbit, Serial_Command); 4225 devpriv->writeb(dev, loadbit, Serial_Command);
4203 udelay(1); 4226 udelay(1);
4204 ni_writeb(0, Serial_Command); 4227 devpriv->writeb(dev, 0, Serial_Command);
4205} 4228}
4206 4229
4207static int ni_calib_insn_write(struct comedi_device *dev, 4230static int ni_calib_insn_write(struct comedi_device *dev,
@@ -4282,25 +4305,26 @@ static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4282 4305
4283static int ni_read_eeprom(struct comedi_device *dev, int addr) 4306static int ni_read_eeprom(struct comedi_device *dev, int addr)
4284{ 4307{
4285 struct ni_private *devpriv __maybe_unused = dev->private; 4308 struct ni_private *devpriv = dev->private;
4286 int bit; 4309 int bit;
4287 int bitstring; 4310 int bitstring;
4288 4311
4289 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); 4312 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4290 ni_writeb(0x04, Serial_Command); 4313 devpriv->writeb(dev, 0x04, Serial_Command);
4291 for (bit = 0x8000; bit; bit >>= 1) { 4314 for (bit = 0x8000; bit; bit >>= 1) {
4292 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0), 4315 devpriv->writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4293 Serial_Command); 4316 Serial_Command);
4294 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0), 4317 devpriv->writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4295 Serial_Command); 4318 Serial_Command);
4296 } 4319 }
4297 bitstring = 0; 4320 bitstring = 0;
4298 for (bit = 0x80; bit; bit >>= 1) { 4321 for (bit = 0x80; bit; bit >>= 1) {
4299 ni_writeb(0x04, Serial_Command); 4322 devpriv->writeb(dev, 0x04, Serial_Command);
4300 ni_writeb(0x05, Serial_Command); 4323 devpriv->writeb(dev, 0x05, Serial_Command);
4301 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0); 4324 bitstring |= ((devpriv->readb(dev, XXX_Status) & PROMOUT)
4325 ? bit : 0);
4302 } 4326 }
4303 ni_writeb(0x00, Serial_Command); 4327 devpriv->writeb(dev, 0x00, Serial_Command);
4304 4328
4305 return bitstring; 4329 return bitstring;
4306} 4330}
@@ -4403,8 +4427,8 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4403 ~MSeries_PFI_Output_Select_Mask(chan); 4427 ~MSeries_PFI_Output_Select_Mask(chan);
4404 devpriv->pfi_output_select_reg[array_offset] |= 4428 devpriv->pfi_output_select_reg[array_offset] |=
4405 MSeries_PFI_Output_Select_Bits(chan, source); 4429 MSeries_PFI_Output_Select_Bits(chan, source);
4406 ni_writew(devpriv->pfi_output_select_reg[array_offset], 4430 devpriv->writew(dev, devpriv->pfi_output_select_reg[array_offset],
4407 M_Offset_PFI_Output_Select(pfi_reg_index)); 4431 M_Offset_PFI_Output_Select(pfi_reg_index));
4408 return 2; 4432 return 2;
4409} 4433}
4410 4434
@@ -4434,15 +4458,15 @@ static int ni_config_filter(struct comedi_device *dev,
4434 enum ni_pfi_filter_select filter) 4458 enum ni_pfi_filter_select filter)
4435{ 4459{
4436 const struct ni_board_struct *board = comedi_board(dev); 4460 const struct ni_board_struct *board = comedi_board(dev);
4437 struct ni_private *devpriv __maybe_unused = dev->private; 4461 struct ni_private *devpriv = dev->private;
4438 unsigned bits; 4462 unsigned bits;
4439 4463
4440 if ((board->reg_type & ni_reg_m_series_mask) == 0) 4464 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4441 return -ENOTSUPP; 4465 return -ENOTSUPP;
4442 bits = ni_readl(M_Offset_PFI_Filter); 4466 bits = devpriv->readl(dev, M_Offset_PFI_Filter);
4443 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); 4467 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
4444 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); 4468 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
4445 ni_writel(bits, M_Offset_PFI_Filter); 4469 devpriv->writel(dev, bits, M_Offset_PFI_Filter);
4446 return 0; 4470 return 0;
4447} 4471}
4448 4472
@@ -4493,15 +4517,15 @@ static int ni_pfi_insn_bits(struct comedi_device *dev,
4493 unsigned int *data) 4517 unsigned int *data)
4494{ 4518{
4495 const struct ni_board_struct *board = comedi_board(dev); 4519 const struct ni_board_struct *board = comedi_board(dev);
4496 struct ni_private *devpriv __maybe_unused = dev->private; 4520 struct ni_private *devpriv = dev->private;
4497 4521
4498 if (!(board->reg_type & ni_reg_m_series_mask)) 4522 if (!(board->reg_type & ni_reg_m_series_mask))
4499 return -ENOTSUPP; 4523 return -ENOTSUPP;
4500 4524
4501 if (comedi_dio_update_state(s, data)) 4525 if (comedi_dio_update_state(s, data))
4502 ni_writew(s->state, M_Offset_PFI_DO); 4526 devpriv->writew(dev, s->state, M_Offset_PFI_DO);
4503 4527
4504 data[1] = ni_readw(M_Offset_PFI_DI); 4528 data[1] = devpriv->readw(dev, M_Offset_PFI_DI);
4505 4529
4506 return insn->n; 4530 return insn->n;
4507} 4531}
@@ -4766,7 +4790,8 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4766 } 4790 }
4767 break; 4791 break;
4768 } 4792 }
4769 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); 4793 devpriv->writew(dev, devpriv->clock_and_fout2,
4794 M_Offset_Clock_and_Fout2);
4770 pll_control_bits |= 4795 pll_control_bits |=
4771 MSeries_PLL_Divisor_Bits(freq_divider) | 4796 MSeries_PLL_Divisor_Bits(freq_divider) |
4772 MSeries_PLL_Multiplier_Bits(freq_multiplier); 4797 MSeries_PLL_Multiplier_Bits(freq_multiplier);
@@ -4774,11 +4799,12 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4774 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n", 4799 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
4775 * freq_divider, freq_multiplier, pll_control_bits); */ 4800 * freq_divider, freq_multiplier, pll_control_bits); */
4776 /* printk("clock_ns=%d\n", devpriv->clock_ns); */ 4801 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
4777 ni_writew(pll_control_bits, M_Offset_PLL_Control); 4802 devpriv->writew(dev, pll_control_bits, M_Offset_PLL_Control);
4778 devpriv->clock_source = source; 4803 devpriv->clock_source = source;
4779 /* it seems to typically take a few hundred microseconds for PLL to lock */ 4804 /* it seems to typically take a few hundred microseconds for PLL to lock */
4780 for (i = 0; i < timeout; ++i) { 4805 for (i = 0; i < timeout; ++i) {
4781 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) 4806 if (devpriv->readw(dev, M_Offset_PLL_Status) &
4807 MSeries_PLL_Locked_Bit)
4782 break; 4808 break;
4783 udelay(1); 4809 udelay(1);
4784 } 4810 }
@@ -4806,9 +4832,9 @@ static int ni_set_master_clock(struct comedi_device *dev,
4806 devpriv->clock_and_fout2 &= 4832 devpriv->clock_and_fout2 &=
4807 ~(MSeries_Timebase1_Select_Bit | 4833 ~(MSeries_Timebase1_Select_Bit |
4808 MSeries_Timebase3_Select_Bit); 4834 MSeries_Timebase3_Select_Bit);
4809 ni_writew(devpriv->clock_and_fout2, 4835 devpriv->writew(dev, devpriv->clock_and_fout2,
4810 M_Offset_Clock_and_Fout2); 4836 M_Offset_Clock_and_Fout2);
4811 ni_writew(0, M_Offset_PLL_Control); 4837 devpriv->writew(dev, 0, M_Offset_PLL_Control);
4812 } 4838 }
4813 devpriv->clock_source = source; 4839 devpriv->clock_source = source;
4814 } else { 4840 } else {
@@ -5355,13 +5381,15 @@ static int ni_E_init(struct comedi_device *dev)
5355 s->async_dma_dir = DMA_BIDIRECTIONAL; 5381 s->async_dma_dir = DMA_BIDIRECTIONAL;
5356 s->len_chanlist = s->n_chan; 5382 s->len_chanlist = s->n_chan;
5357 5383
5358 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command); 5384 devpriv->writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,
5359 ni_writel(s->io_bits, M_Offset_DIO_Direction); 5385 M_Offset_CDIO_Command);
5386 devpriv->writel(dev, s->io_bits, M_Offset_DIO_Direction);
5360 } else { 5387 } else {
5361 s->insn_bits = &ni_dio_insn_bits; 5388 s->insn_bits = &ni_dio_insn_bits;
5362 s->insn_config = &ni_dio_insn_config; 5389 s->insn_config = &ni_dio_insn_config;
5363 devpriv->dio_control = DIO_Pins_Dir(s->io_bits); 5390 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
5364 ni_writew(devpriv->dio_control, DIO_Control_Register); 5391 devpriv->writew(dev, devpriv->dio_control,
5392 DIO_Control_Register);
5365 } 5393 }
5366 5394
5367 /* 8255 device */ 5395 /* 8255 device */
@@ -5388,7 +5416,7 @@ static int ni_E_init(struct comedi_device *dev)
5388 s->insn_config = &ni_m_series_pwm_config; 5416 s->insn_config = &ni_m_series_pwm_config;
5389 s->n_chan = 1; 5417 s->n_chan = 1;
5390 s->maxdata = 0; 5418 s->maxdata = 0;
5391 ni_writel(0x0, M_Offset_Cal_PWM); 5419 devpriv->writel(dev, 0x0, M_Offset_Cal_PWM);
5392 } else if (board->reg_type == ni_reg_6143) { 5420 } else if (board->reg_type == ni_reg_6143) {
5393 /* internal PWM analog output used for AI nonlinearity calibration */ 5421 /* internal PWM analog output used for AI nonlinearity calibration */
5394 s->subdev_flags = SDF_INTERNAL; 5422 s->subdev_flags = SDF_INTERNAL;
@@ -5422,10 +5450,10 @@ static int ni_E_init(struct comedi_device *dev)
5422 if (board->reg_type & ni_reg_m_series_mask) { 5450 if (board->reg_type & ni_reg_m_series_mask) {
5423 unsigned i; 5451 unsigned i;
5424 s->n_chan = 16; 5452 s->n_chan = 16;
5425 ni_writew(s->state, M_Offset_PFI_DO); 5453 devpriv->writew(dev, s->state, M_Offset_PFI_DO);
5426 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { 5454 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5427 ni_writew(devpriv->pfi_output_select_reg[i], 5455 devpriv->writew(dev, devpriv->pfi_output_select_reg[i],
5428 M_Offset_PFI_Output_Select(i + 1)); 5456 M_Offset_PFI_Output_Select(i + 1));
5429 } 5457 }
5430 } else { 5458 } else {
5431 s->n_chan = 10; 5459 s->n_chan = 10;
@@ -5559,19 +5587,20 @@ static int ni_E_init(struct comedi_device *dev)
5559 } 5587 }
5560 5588
5561 /* DMA setup */ 5589 /* DMA setup */
5562 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); 5590 devpriv->writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5563 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); 5591 devpriv->writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5564 5592
5565 if (board->reg_type & ni_reg_6xxx_mask) { 5593 if (board->reg_type & ni_reg_6xxx_mask) {
5566 ni_writeb(0, Magic_611x); 5594 devpriv->writeb(dev, 0, Magic_611x);
5567 } else if (board->reg_type & ni_reg_m_series_mask) { 5595 } else if (board->reg_type & ni_reg_m_series_mask) {
5568 int channel; 5596 int channel;
5569 for (channel = 0; channel < board->n_aochan; ++channel) { 5597 for (channel = 0; channel < board->n_aochan; ++channel) {
5570 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel)); 5598 devpriv->writeb(dev, 0xf,
5571 ni_writeb(0x0, 5599 M_Offset_AO_Waveform_Order(channel));
5572 M_Offset_AO_Reference_Attenuation(channel)); 5600 devpriv->writeb(dev, 0x0,
5601 M_Offset_AO_Reference_Attenuation(channel));
5573 } 5602 }
5574 ni_writeb(0x0, M_Offset_AO_Calibration); 5603 devpriv->writeb(dev, 0x0, M_Offset_AO_Calibration);
5575 } 5604 }
5576 5605
5577 return 0; 5606 return 0;
diff --git a/drivers/staging/comedi/drivers/ni_mio_cs.c b/drivers/staging/comedi/drivers/ni_mio_cs.c
index e0945f72a869..d61baffb4bf0 100644
--- a/drivers/staging/comedi/drivers/ni_mio_cs.c
+++ b/drivers/staging/comedi/drivers/ni_mio_cs.c
@@ -143,12 +143,35 @@ static const struct ni_board_struct ni_boards[] = {
143 143
144/* How we access registers */ 144/* How we access registers */
145 145
146#define ni_writel(a, b) (outl((a), (b)+dev->iobase)) 146static uint8_t mio_cs_inb(struct comedi_device *dev, int reg)
147#define ni_readl(a) (inl((a)+dev->iobase)) 147{
148#define ni_writew(a, b) (outw((a), (b)+dev->iobase)) 148 return inb(dev->iobase + reg);
149#define ni_readw(a) (inw((a)+dev->iobase)) 149}
150#define ni_writeb(a, b) (outb((a), (b)+dev->iobase)) 150
151#define ni_readb(a) (inb((a)+dev->iobase)) 151static uint16_t mio_cs_inw(struct comedi_device *dev, int reg)
152{
153 return inw(dev->iobase + reg);
154}
155
156static uint32_t mio_cs_inl(struct comedi_device *dev, int reg)
157{
158 return inl(dev->iobase + reg);
159}
160
161static void mio_cs_outb(struct comedi_device *dev, uint8_t val, int reg)
162{
163 outb(val, dev->iobase + reg);
164}
165
166static void mio_cs_outw(struct comedi_device *dev, uint16_t val, int reg)
167{
168 outw(val, dev->iobase + reg);
169}
170
171static void mio_cs_outl(struct comedi_device *dev, uint32_t val, int reg)
172{
173 outl(val, dev->iobase + reg);
174}
152 175
153/* How we access windowed registers */ 176/* How we access windowed registers */
154 177
@@ -163,10 +186,10 @@ static void mio_cs_win_out(struct comedi_device *dev, uint16_t data, int addr)
163 186
164 spin_lock_irqsave(&devpriv->window_lock, flags); 187 spin_lock_irqsave(&devpriv->window_lock, flags);
165 if (addr < 8) { 188 if (addr < 8) {
166 ni_writew(data, addr * 2); 189 devpriv->writew(dev, data, addr * 2);
167 } else { 190 } else {
168 ni_writew(addr, Window_Address); 191 devpriv->writew(dev, addr, Window_Address);
169 ni_writew(data, Window_Data); 192 devpriv->writew(dev, data, Window_Data);
170 } 193 }
171 spin_unlock_irqrestore(&devpriv->window_lock, flags); 194 spin_unlock_irqrestore(&devpriv->window_lock, flags);
172} 195}
@@ -179,10 +202,10 @@ static uint16_t mio_cs_win_in(struct comedi_device *dev, int addr)
179 202
180 spin_lock_irqsave(&devpriv->window_lock, flags); 203 spin_lock_irqsave(&devpriv->window_lock, flags);
181 if (addr < 8) { 204 if (addr < 8) {
182 ret = ni_readw(addr * 2); 205 ret = devpriv->readw(dev, addr * 2);
183 } else { 206 } else {
184 ni_writew(addr, Window_Address); 207 devpriv->writew(dev, addr, Window_Address);
185 ret = ni_readw(Window_Data); 208 ret = devpriv->readw(dev, Window_Data);
186 } 209 }
187 spin_unlock_irqrestore(&devpriv->window_lock, flags); 210 spin_unlock_irqrestore(&devpriv->window_lock, flags);
188 211
@@ -252,6 +275,14 @@ static int mio_cs_auto_attach(struct comedi_device *dev,
252 return ret; 275 return ret;
253 276
254 devpriv = dev->private; 277 devpriv = dev->private;
278
279 devpriv->readb = mio_cs_inb;
280 devpriv->readw = mio_cs_inw;
281 devpriv->readl = mio_cs_inl;
282 devpriv->writeb = mio_cs_outb;
283 devpriv->writew = mio_cs_outw;
284 devpriv->writel = mio_cs_outl;
285
255 devpriv->stc_writew = mio_cs_win_out; 286 devpriv->stc_writew = mio_cs_win_out;
256 devpriv->stc_readw = mio_cs_win_in; 287 devpriv->stc_readw = mio_cs_win_in;
257 devpriv->stc_writel = win_out2; 288 devpriv->stc_writel = win_out2;
diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c
index cfe97345dd47..c1c2730cf3e1 100644
--- a/drivers/staging/comedi/drivers/ni_pcimio.c
+++ b/drivers/staging/comedi/drivers/ni_pcimio.c
@@ -1044,12 +1044,47 @@ static const struct ni_board_struct ni_boards[] = {
1044 1044
1045/* How we access registers */ 1045/* How we access registers */
1046 1046
1047#define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b))) 1047static uint8_t pcimio_readb(struct comedi_device *dev, int reg)
1048#define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a))) 1048{
1049#define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b))) 1049 struct ni_private *devpriv = dev->private;
1050#define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a))) 1050
1051#define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b))) 1051 return readb(devpriv->mite->daq_io_addr + reg);
1052#define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a))) 1052}
1053
1054static uint16_t pcimio_readw(struct comedi_device *dev, int reg)
1055{
1056 struct ni_private *devpriv = dev->private;
1057
1058 return readw(devpriv->mite->daq_io_addr + reg);
1059}
1060
1061static uint32_t pcimio_readl(struct comedi_device *dev, int reg)
1062{
1063 struct ni_private *devpriv = dev->private;
1064
1065 return readl(devpriv->mite->daq_io_addr + reg);
1066}
1067
1068static void pcimio_writeb(struct comedi_device *dev, uint8_t val, int reg)
1069{
1070 struct ni_private *devpriv = dev->private;
1071
1072 writeb(val, devpriv->mite->daq_io_addr + reg);
1073}
1074
1075static void pcimio_writew(struct comedi_device *dev, uint16_t val, int reg)
1076{
1077 struct ni_private *devpriv = dev->private;
1078
1079 writew(val, devpriv->mite->daq_io_addr + reg);
1080}
1081
1082static void pcimio_writel(struct comedi_device *dev, uint32_t val, int reg)
1083{
1084 struct ni_private *devpriv = dev->private;
1085
1086 writel(val, devpriv->mite->daq_io_addr + reg);
1087}
1053 1088
1054/* How we access STC registers */ 1089/* How we access STC registers */
1055 1090
@@ -1067,8 +1102,8 @@ static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1067 unsigned long flags; 1102 unsigned long flags;
1068 1103
1069 spin_lock_irqsave(&devpriv->window_lock, flags); 1104 spin_lock_irqsave(&devpriv->window_lock, flags);
1070 ni_writew(reg, Window_Address); 1105 devpriv->writew(dev, reg, Window_Address);
1071 ni_writew(data, Window_Data); 1106 devpriv->writew(dev, data, Window_Data);
1072 spin_unlock_irqrestore(&devpriv->window_lock, flags); 1107 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1073} 1108}
1074 1109
@@ -1079,8 +1114,8 @@ static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1079 uint16_t ret; 1114 uint16_t ret;
1080 1115
1081 spin_lock_irqsave(&devpriv->window_lock, flags); 1116 spin_lock_irqsave(&devpriv->window_lock, flags);
1082 ni_writew(reg, Window_Address); 1117 devpriv->writew(dev, reg, Window_Address);
1083 ret = ni_readw(Window_Data); 1118 ret = devpriv->readw(dev, Window_Data);
1084 spin_unlock_irqrestore(&devpriv->window_lock, flags); 1119 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1085 1120
1086 return ret; 1121 return ret;
@@ -1119,12 +1154,12 @@ static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1119 break; 1154 break;
1120 case AI_SI2_Load_A_Register: 1155 case AI_SI2_Load_A_Register:
1121 /* this is actually a 32 bit register on m series boards */ 1156 /* this is actually a 32 bit register on m series boards */
1122 ni_writel(data, M_Offset_AI_SI2_Load_A); 1157 devpriv->writel(dev, data, M_Offset_AI_SI2_Load_A);
1123 return; 1158 return;
1124 break; 1159 break;
1125 case AI_SI2_Load_B_Register: 1160 case AI_SI2_Load_B_Register:
1126 /* this is actually a 32 bit register on m series boards */ 1161 /* this is actually a 32 bit register on m series boards */
1127 ni_writel(data, M_Offset_AI_SI2_Load_B); 1162 devpriv->writel(dev, data, M_Offset_AI_SI2_Load_B);
1128 return; 1163 return;
1129 break; 1164 break;
1130 case AI_START_STOP_Select_Register: 1165 case AI_START_STOP_Select_Register:
@@ -1242,7 +1277,7 @@ static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1242 return; 1277 return;
1243 break; 1278 break;
1244 } 1279 }
1245 ni_writew(data, offset); 1280 devpriv->writew(dev, data, offset);
1246} 1281}
1247 1282
1248static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) 1283static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
@@ -1261,7 +1296,7 @@ static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1261 offset = M_Offset_AO_Status_2; 1296 offset = M_Offset_AO_Status_2;
1262 break; 1297 break;
1263 case DIO_Serial_Input_Register: 1298 case DIO_Serial_Input_Register:
1264 return ni_readb(M_Offset_SCXI_Serial_Data_In); 1299 return devpriv->readb(dev, M_Offset_SCXI_Serial_Data_In);
1265 break; 1300 break;
1266 case Joint_Status_1_Register: 1301 case Joint_Status_1_Register:
1267 offset = M_Offset_Joint_Status_1; 1302 offset = M_Offset_Joint_Status_1;
@@ -1280,7 +1315,7 @@ static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1280 return 0; 1315 return 0;
1281 break; 1316 break;
1282 } 1317 }
1283 return ni_readw(offset); 1318 return devpriv->readw(dev, offset);
1284} 1319}
1285 1320
1286static void m_series_stc_writel(struct comedi_device *dev, uint32_t data, 1321static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
@@ -1325,7 +1360,7 @@ static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1325 return; 1360 return;
1326 break; 1361 break;
1327 } 1362 }
1328 ni_writel(data, offset); 1363 devpriv->writel(dev, data, offset);
1329} 1364}
1330 1365
1331static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) 1366static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
@@ -1354,7 +1389,7 @@ static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1354 return 0; 1389 return 0;
1355 break; 1390 break;
1356 } 1391 }
1357 return ni_readl(offset); 1392 return devpriv->readl(dev, offset);
1358} 1393}
1359 1394
1360#define interrupt_pin(a) 0 1395#define interrupt_pin(a) 0
@@ -1403,12 +1438,14 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1403 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number)); 1438 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1404 for (i = 0; i < serial_number_eeprom_length; ++i) { 1439 for (i = 0; i < serial_number_eeprom_length; ++i) {
1405 char *byte_ptr = (char *)&devpriv->serial_number + i; 1440 char *byte_ptr = (char *)&devpriv->serial_number + i;
1406 *byte_ptr = ni_readb(serial_number_eeprom_offset + i); 1441 *byte_ptr = devpriv->readb(dev,
1442 serial_number_eeprom_offset + i);
1407 } 1443 }
1408 devpriv->serial_number = be32_to_cpu(devpriv->serial_number); 1444 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1409 1445
1410 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) 1446 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1411 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i); 1447 devpriv->eeprom_buffer[i] = devpriv->readb(dev,
1448 Start_Cal_EEPROM + i);
1412 1449
1413 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1); 1450 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1414 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR); 1451 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
@@ -1425,18 +1462,24 @@ static void init_6143(struct comedi_device *dev)
1425 devpriv->stc_writew(dev, 0, Interrupt_Control_Register); 1462 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1426 1463
1427 /* Initialise 6143 AI specific bits */ 1464 /* Initialise 6143 AI specific bits */
1428 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */ 1465
1429 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */ 1466 /* Set G0,G1 DMA mode to E series version */
1430 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */ 1467 devpriv->writeb(dev, 0x00, Magic_6143);
1468 /* Set EOCMode, ADCMode and pipelinedelay */
1469 devpriv->writeb(dev, 0x80, PipelineDelay_6143);
1470 /* Set EOC Delay */
1471 devpriv->writeb(dev, 0x00, EOC_Set_6143);
1431 1472
1432 /* Set the FIFO half full level */ 1473 /* Set the FIFO half full level */
1433 ni_writel(board->ai_fifo_depth / 2, AIFIFO_Flag_6143); 1474 devpriv->writel(dev, board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
1434 1475
1435 /* Strobe Relay disable bit */ 1476 /* Strobe Relay disable bit */
1436 devpriv->ai_calib_source_enabled = 0; 1477 devpriv->ai_calib_source_enabled = 0;
1437 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, 1478 devpriv->writew(dev, devpriv->ai_calib_source |
1438 Calibration_Channel_6143); 1479 Calibration_Channel_6143_RelayOff,
1439 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143); 1480 Calibration_Channel_6143);
1481 devpriv->writew(dev, devpriv->ai_calib_source,
1482 Calibration_Channel_6143);
1440} 1483}
1441 1484
1442static void pcimio_detach(struct comedi_device *dev) 1485static void pcimio_detach(struct comedi_device *dev)
@@ -1489,16 +1532,23 @@ static int pcimio_auto_attach(struct comedi_device *dev,
1489 if (!devpriv->mite) 1532 if (!devpriv->mite)
1490 return -ENOMEM; 1533 return -ENOMEM;
1491 1534
1535 devpriv->readb = pcimio_readb;
1536 devpriv->readw = pcimio_readw;
1537 devpriv->readl = pcimio_readl;
1538 devpriv->writeb = pcimio_writeb;
1539 devpriv->writew = pcimio_writew;
1540 devpriv->writel = pcimio_writel;
1541
1492 if (board->reg_type & ni_reg_m_series_mask) { 1542 if (board->reg_type & ni_reg_m_series_mask) {
1493 devpriv->stc_writew = &m_series_stc_writew; 1543 devpriv->stc_writew = m_series_stc_writew;
1494 devpriv->stc_readw = &m_series_stc_readw; 1544 devpriv->stc_readw = m_series_stc_readw;
1495 devpriv->stc_writel = &m_series_stc_writel; 1545 devpriv->stc_writel = m_series_stc_writel;
1496 devpriv->stc_readl = &m_series_stc_readl; 1546 devpriv->stc_readl = m_series_stc_readl;
1497 } else { 1547 } else {
1498 devpriv->stc_writew = &e_series_win_out; 1548 devpriv->stc_writew = e_series_win_out;
1499 devpriv->stc_readw = &e_series_win_in; 1549 devpriv->stc_readw = e_series_win_in;
1500 devpriv->stc_writel = &win_out2; 1550 devpriv->stc_writel = win_out2;
1501 devpriv->stc_readl = &win_in2; 1551 devpriv->stc_readl = win_in2;
1502 } 1552 }
1503 1553
1504 ret = mite_setup(devpriv->mite); 1554 ret = mite_setup(devpriv->mite);
diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h
index 1cc035ba9c93..a93ef6b488e1 100644
--- a/drivers/staging/comedi/drivers/ni_stc.h
+++ b/drivers/staging/comedi/drivers/ni_stc.h
@@ -1421,6 +1421,13 @@ struct ni_board_struct {
1421#define NUM_GPCT 2 1421#define NUM_GPCT 2
1422 1422
1423struct ni_private { 1423struct ni_private {
1424 uint8_t (*readb)(struct comedi_device *, int reg);
1425 uint16_t (*readw)(struct comedi_device *, int reg);
1426 uint32_t (*readl)(struct comedi_device *, int reg);
1427 void (*writeb)(struct comedi_device *, uint8_t value, int reg);
1428 void (*writew)(struct comedi_device *, uint16_t value, int reg);
1429 void (*writel)(struct comedi_device *, uint32_t value, int reg);
1430
1424 uint16_t (*stc_readw)(struct comedi_device *, int reg); 1431 uint16_t (*stc_readw)(struct comedi_device *, int reg);
1425 uint32_t (*stc_readl)(struct comedi_device *, int reg); 1432 uint32_t (*stc_readl)(struct comedi_device *, int reg);
1426 void (*stc_writew)(struct comedi_device *, uint16_t value, int reg); 1433 void (*stc_writew)(struct comedi_device *, uint16_t value, int reg);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 18:55:26 -0500