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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-09-09 12:01:30 -0400
committerDavid S. Miller <davem@davemloft.net>2009-09-11 15:54:38 -0400
commit8ff44985c761ad6697a3c97e7b14cf5362ff3801 (patch)
tree3f9903a9573ea74938c8ff66be449e1d0a965dba /drivers
parenta4b11649618ef5366ee553f4083449d6bee5d8ec (diff)
phy/marvell: Make non-aneg speed/duplex forcing work for 88E1111 PHYs
According to specs, when auto-negotiation is disabled, Marvell PHYs need a software reset after changing speed/duplex forcing bits. Otherwise, the modified bits have no effect. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/phy/marvell.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index dd6f54d1b495..6f69b9ba0df8 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -155,8 +155,27 @@ static int marvell_config_aneg(struct phy_device *phydev)
155 return err; 155 return err;
156 156
157 err = genphy_config_aneg(phydev); 157 err = genphy_config_aneg(phydev);
158 if (err < 0)
159 return err;
158 160
159 return err; 161 if (phydev->autoneg != AUTONEG_ENABLE) {
162 int bmcr;
163
164 /*
165 * A write to speed/duplex bits (that is performed by
166 * genphy_config_aneg() call above) must be followed by
167 * a software reset. Otherwise, the write has no effect.
168 */
169 bmcr = phy_read(phydev, MII_BMCR);
170 if (bmcr < 0)
171 return bmcr;
172
173 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
174 if (err < 0)
175 return err;
176 }
177
178 return 0;
160} 179}
161 180
162static int m88e1121_config_aneg(struct phy_device *phydev) 181static int m88e1121_config_aneg(struct phy_device *phydev)