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authorAjit Khaparde <ajitk@serverengines.com>2010-07-29 02:16:33 -0400
committerDavid S. Miller <davem@davemloft.net>2010-07-31 02:59:05 -0400
commit7c185276e8d820fa50a678c61abd611ee599920e (patch)
tree5c8b5ac0e55eb2bafca470da939177ecc52a9755 /drivers
parent6dedec818ac2a3783581a761b0680e713f78afde (diff)
be2net: add code to dump registers for debug
when the BE device becomes unresponsive, dump the registers to help debugging Signed-off-by: Somnath K <somnathk@serverengines.com> Signed-off-by: Ajit Khaparde <ajitk@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/benet/be.h1
-rw-r--r--drivers/net/benet/be_cmds.c1
-rw-r--r--drivers/net/benet/be_cmds.h1
-rw-r--r--drivers/net/benet/be_hw.h10
-rw-r--r--drivers/net/benet/be_main.c127
5 files changed, 140 insertions, 0 deletions
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h
index e06369c36dd4..5e6f581c49d4 100644
--- a/drivers/net/benet/be.h
+++ b/drivers/net/benet/be.h
@@ -288,6 +288,7 @@ struct be_adapter {
288 u32 function_mode; 288 u32 function_mode;
289 u32 rx_fc; /* Rx flow control */ 289 u32 rx_fc; /* Rx flow control */
290 u32 tx_fc; /* Tx flow control */ 290 u32 tx_fc; /* Tx flow control */
291 bool ue_detected;
291 int link_speed; 292 int link_speed;
292 u8 port_type; 293 u8 port_type;
293 u8 transceiver; 294 u8 transceiver;
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c
index 6eaf8a3fa5ea..7fd860dcbc80 100644
--- a/drivers/net/benet/be_cmds.c
+++ b/drivers/net/benet/be_cmds.c
@@ -206,6 +206,7 @@ static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
206 206
207 if (msecs > 4000) { 207 if (msecs > 4000) {
208 dev_err(&adapter->pdev->dev, "mbox poll timed out\n"); 208 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
209 be_dump_ue(adapter);
209 return -1; 210 return -1;
210 } 211 }
211 212
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h
index 036531cd200f..bdc10a28cfda 100644
--- a/drivers/net/benet/be_cmds.h
+++ b/drivers/net/benet/be_cmds.h
@@ -992,4 +992,5 @@ extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
992extern int be_cmd_get_phy_info(struct be_adapter *adapter, 992extern int be_cmd_get_phy_info(struct be_adapter *adapter,
993 struct be_dma_mem *cmd); 993 struct be_dma_mem *cmd);
994extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); 994extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
995extern void be_dump_ue(struct be_adapter *adapter);
995 996
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h
index 06839676e3c4..6c8f9bb8bfe6 100644
--- a/drivers/net/benet/be_hw.h
+++ b/drivers/net/benet/be_hw.h
@@ -56,6 +56,16 @@
56#define PCICFG_PM_CONTROL_OFFSET 0x44 56#define PCICFG_PM_CONTROL_OFFSET 0x44
57#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ 57#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
58 58
59/********* Online Control Registers *******/
60#define PCICFG_ONLINE0 0xB0
61#define PCICFG_ONLINE1 0xB4
62
63/********* UE Status and Mask Registers ***/
64#define PCICFG_UE_STATUS_LOW 0xA0
65#define PCICFG_UE_STATUS_HIGH 0xA4
66#define PCICFG_UE_STATUS_LOW_MASK 0xA8
67#define PCICFG_UE_STATUS_HI_MASK 0xAC
68
59/********* ISR0 Register offset **********/ 69/********* ISR0 Register offset **********/
60#define CEV_ISR0_OFFSET 0xC18 70#define CEV_ISR0_OFFSET 0xC18
61#define CEV_ISR_SIZE 4 71#define CEV_ISR_SIZE 4
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c
index e72b482c4327..e4a8ae3a1c8d 100644
--- a/drivers/net/benet/be_main.c
+++ b/drivers/net/benet/be_main.c
@@ -40,6 +40,76 @@ static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
40 { 0 } 40 { 0 }
41}; 41};
42MODULE_DEVICE_TABLE(pci, be_dev_ids); 42MODULE_DEVICE_TABLE(pci, be_dev_ids);
43/* UE Status Low CSR */
44static char *ue_status_low_desc[] = {
45 "CEV",
46 "CTX",
47 "DBUF",
48 "ERX",
49 "Host",
50 "MPU",
51 "NDMA",
52 "PTC ",
53 "RDMA ",
54 "RXF ",
55 "RXIPS ",
56 "RXULP0 ",
57 "RXULP1 ",
58 "RXULP2 ",
59 "TIM ",
60 "TPOST ",
61 "TPRE ",
62 "TXIPS ",
63 "TXULP0 ",
64 "TXULP1 ",
65 "UC ",
66 "WDMA ",
67 "TXULP2 ",
68 "HOST1 ",
69 "P0_OB_LINK ",
70 "P1_OB_LINK ",
71 "HOST_GPIO ",
72 "MBOX ",
73 "AXGMAC0",
74 "AXGMAC1",
75 "JTAG",
76 "MPU_INTPEND"
77};
78/* UE Status High CSR */
79static char *ue_status_hi_desc[] = {
80 "LPCMEMHOST",
81 "MGMT_MAC",
82 "PCS0ONLINE",
83 "MPU_IRAM",
84 "PCS1ONLINE",
85 "PCTL0",
86 "PCTL1",
87 "PMEM",
88 "RR",
89 "TXPB",
90 "RXPP",
91 "XAUI",
92 "TXP",
93 "ARM",
94 "IPC",
95 "HOST2",
96 "HOST3",
97 "HOST4",
98 "HOST5",
99 "HOST6",
100 "HOST7",
101 "HOST8",
102 "HOST9",
103 "NETC"
104 "Unknown",
105 "Unknown",
106 "Unknown",
107 "Unknown",
108 "Unknown",
109 "Unknown",
110 "Unknown",
111 "Unknown"
112};
43 113
44static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q) 114static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
45{ 115{
@@ -1673,6 +1743,59 @@ static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
1673 return 1; 1743 return 1;
1674} 1744}
1675 1745
1746static inline bool be_detect_ue(struct be_adapter *adapter)
1747{
1748 u32 online0 = 0, online1 = 0;
1749
1750 pci_read_config_dword(adapter->pdev, PCICFG_ONLINE0, &online0);
1751
1752 pci_read_config_dword(adapter->pdev, PCICFG_ONLINE1, &online1);
1753
1754 if (!online0 || !online1) {
1755 adapter->ue_detected = true;
1756 dev_err(&adapter->pdev->dev,
1757 "UE Detected!! online0=%d online1=%d\n",
1758 online0, online1);
1759 return true;
1760 }
1761
1762 return false;
1763}
1764
1765void be_dump_ue(struct be_adapter *adapter)
1766{
1767 u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask;
1768 u32 i;
1769
1770 pci_read_config_dword(adapter->pdev,
1771 PCICFG_UE_STATUS_LOW, &ue_status_lo);
1772 pci_read_config_dword(adapter->pdev,
1773 PCICFG_UE_STATUS_HIGH, &ue_status_hi);
1774 pci_read_config_dword(adapter->pdev,
1775 PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask);
1776 pci_read_config_dword(adapter->pdev,
1777 PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask);
1778
1779 ue_status_lo = (ue_status_lo & (~ue_status_lo_mask));
1780 ue_status_hi = (ue_status_hi & (~ue_status_hi_mask));
1781
1782 if (ue_status_lo) {
1783 for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) {
1784 if (ue_status_lo & 1)
1785 dev_err(&adapter->pdev->dev,
1786 "UE: %s bit set\n", ue_status_low_desc[i]);
1787 }
1788 }
1789 if (ue_status_hi) {
1790 for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) {
1791 if (ue_status_hi & 1)
1792 dev_err(&adapter->pdev->dev,
1793 "UE: %s bit set\n", ue_status_hi_desc[i]);
1794 }
1795 }
1796
1797}
1798
1676static void be_worker(struct work_struct *work) 1799static void be_worker(struct work_struct *work)
1677{ 1800{
1678 struct be_adapter *adapter = 1801 struct be_adapter *adapter =
@@ -1690,6 +1813,10 @@ static void be_worker(struct work_struct *work)
1690 adapter->rx_post_starved = false; 1813 adapter->rx_post_starved = false;
1691 be_post_rx_frags(adapter); 1814 be_post_rx_frags(adapter);
1692 } 1815 }
1816 if (!adapter->ue_detected) {
1817 if (be_detect_ue(adapter))
1818 be_dump_ue(adapter);
1819 }
1693 1820
1694 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); 1821 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1695} 1822}