aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorLaxman Dewangan <ldewangan@nvidia.com>2012-11-13 09:03:58 -0500
committerSamuel Ortiz <sameo@linux.intel.com>2012-11-20 06:21:09 -0500
commit4aab3fadad32ff4df05832beff7c16fd6ad938aa (patch)
tree87220245213c0509f44185db64caacab5b3ff79e /drivers
parent43c1af0f4861b721def8c67ed6af2a69a4efcca3 (diff)
mfd: tps65910: Move interrupt implementation code to mfd file
In place of implementing the irq support in separate file, moving implementation to main mfd file. The irq files only contains the table and init steps only and does not need extra file to have this only for this purpose. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/tps65910-irq.c243
-rw-r--r--drivers/mfd/tps65910.c216
3 files changed, 217 insertions, 244 deletions
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8a68fc7ea870..a30c49ecdd95 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -56,7 +56,7 @@ obj-$(CONFIG_TPS6105X) += tps6105x.o
56obj-$(CONFIG_TPS65010) += tps65010.o 56obj-$(CONFIG_TPS65010) += tps65010.o
57obj-$(CONFIG_TPS6507X) += tps6507x.o 57obj-$(CONFIG_TPS6507X) += tps6507x.o
58obj-$(CONFIG_MFD_TPS65217) += tps65217.o 58obj-$(CONFIG_MFD_TPS65217) += tps65217.o
59obj-$(CONFIG_MFD_TPS65910) += tps65910.o tps65910-irq.o 59obj-$(CONFIG_MFD_TPS65910) += tps65910.o
60tps65912-objs := tps65912-core.o tps65912-irq.o 60tps65912-objs := tps65912-core.o tps65912-irq.o
61obj-$(CONFIG_MFD_TPS65912) += tps65912.o 61obj-$(CONFIG_MFD_TPS65912) += tps65912.o
62obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o 62obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o
diff --git a/drivers/mfd/tps65910-irq.c b/drivers/mfd/tps65910-irq.c
deleted file mode 100644
index 554543a584a1..000000000000
--- a/drivers/mfd/tps65910-irq.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/*
2 * tps65910-irq.c -- TI TPS6591x
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/bug.h>
20#include <linux/device.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h>
26
27
28static const struct regmap_irq tps65911_irqs[] = {
29 /* INT_STS */
30 [TPS65911_IRQ_PWRHOLD_F] = {
31 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
32 .reg_offset = 0,
33 },
34 [TPS65911_IRQ_VBAT_VMHI] = {
35 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
36 .reg_offset = 0,
37 },
38 [TPS65911_IRQ_PWRON] = {
39 .mask = INT_MSK_PWRON_IT_MSK_MASK,
40 .reg_offset = 0,
41 },
42 [TPS65911_IRQ_PWRON_LP] = {
43 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
44 .reg_offset = 0,
45 },
46 [TPS65911_IRQ_PWRHOLD_R] = {
47 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
48 .reg_offset = 0,
49 },
50 [TPS65911_IRQ_HOTDIE] = {
51 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
52 .reg_offset = 0,
53 },
54 [TPS65911_IRQ_RTC_ALARM] = {
55 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
56 .reg_offset = 0,
57 },
58 [TPS65911_IRQ_RTC_PERIOD] = {
59 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
60 .reg_offset = 0,
61 },
62
63 /* INT_STS2 */
64 [TPS65911_IRQ_GPIO0_R] = {
65 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
66 .reg_offset = 1,
67 },
68 [TPS65911_IRQ_GPIO0_F] = {
69 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
70 .reg_offset = 1,
71 },
72 [TPS65911_IRQ_GPIO1_R] = {
73 .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
74 .reg_offset = 1,
75 },
76 [TPS65911_IRQ_GPIO1_F] = {
77 .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
78 .reg_offset = 1,
79 },
80 [TPS65911_IRQ_GPIO2_R] = {
81 .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
82 .reg_offset = 1,
83 },
84 [TPS65911_IRQ_GPIO2_F] = {
85 .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
86 .reg_offset = 1,
87 },
88 [TPS65911_IRQ_GPIO3_R] = {
89 .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
90 .reg_offset = 1,
91 },
92 [TPS65911_IRQ_GPIO3_F] = {
93 .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
94 .reg_offset = 1,
95 },
96
97 /* INT_STS3 */
98 [TPS65911_IRQ_GPIO4_R] = {
99 .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
100 .reg_offset = 2,
101 },
102 [TPS65911_IRQ_GPIO4_F] = {
103 .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
104 .reg_offset = 2,
105 },
106 [TPS65911_IRQ_GPIO5_R] = {
107 .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
108 .reg_offset = 2,
109 },
110 [TPS65911_IRQ_GPIO5_F] = {
111 .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
112 .reg_offset = 2,
113 },
114 [TPS65911_IRQ_WTCHDG] = {
115 .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
116 .reg_offset = 2,
117 },
118 [TPS65911_IRQ_VMBCH2_H] = {
119 .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
120 .reg_offset = 2,
121 },
122 [TPS65911_IRQ_VMBCH2_L] = {
123 .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
124 .reg_offset = 2,
125 },
126 [TPS65911_IRQ_PWRDN] = {
127 .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
128 .reg_offset = 2,
129 },
130};
131
132static const struct regmap_irq tps65910_irqs[] = {
133 /* INT_STS */
134 [TPS65910_IRQ_VBAT_VMBDCH] = {
135 .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
136 .reg_offset = 0,
137 },
138 [TPS65910_IRQ_VBAT_VMHI] = {
139 .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
140 .reg_offset = 0,
141 },
142 [TPS65910_IRQ_PWRON] = {
143 .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
144 .reg_offset = 0,
145 },
146 [TPS65910_IRQ_PWRON_LP] = {
147 .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
148 .reg_offset = 0,
149 },
150 [TPS65910_IRQ_PWRHOLD] = {
151 .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
152 .reg_offset = 0,
153 },
154 [TPS65910_IRQ_HOTDIE] = {
155 .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
156 .reg_offset = 0,
157 },
158 [TPS65910_IRQ_RTC_ALARM] = {
159 .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
160 .reg_offset = 0,
161 },
162 [TPS65910_IRQ_RTC_PERIOD] = {
163 .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
164 .reg_offset = 0,
165 },
166
167 /* INT_STS2 */
168 [TPS65910_IRQ_GPIO_R] = {
169 .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
170 .reg_offset = 1,
171 },
172 [TPS65910_IRQ_GPIO_F] = {
173 .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
174 .reg_offset = 1,
175 },
176};
177
178static struct regmap_irq_chip tps65911_irq_chip = {
179 .name = "tps65910",
180 .irqs = tps65911_irqs,
181 .num_irqs = ARRAY_SIZE(tps65911_irqs),
182 .num_regs = 3,
183 .irq_reg_stride = 2,
184 .status_base = TPS65910_INT_STS,
185 .mask_base = TPS65910_INT_MSK,
186 .ack_base = TPS65910_INT_MSK,
187};
188
189static struct regmap_irq_chip tps65910_irq_chip = {
190 .name = "tps65910",
191 .irqs = tps65910_irqs,
192 .num_irqs = ARRAY_SIZE(tps65910_irqs),
193 .num_regs = 2,
194 .irq_reg_stride = 2,
195 .status_base = TPS65910_INT_STS,
196 .mask_base = TPS65910_INT_MSK,
197 .ack_base = TPS65910_INT_MSK,
198};
199
200int tps65910_irq_init(struct tps65910 *tps65910, int irq,
201 struct tps65910_platform_data *pdata)
202{
203 int ret = 0;
204 static struct regmap_irq_chip *tps6591x_irqs_chip;
205
206 if (!irq) {
207 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
208 return -EINVAL;
209 }
210
211 if (!pdata) {
212 dev_warn(tps65910->dev, "No interrupt support, no pdata\n");
213 return -EINVAL;
214 }
215
216
217 switch (tps65910_chip_id(tps65910)) {
218 case TPS65910:
219 tps6591x_irqs_chip = &tps65910_irq_chip;
220 break;
221 case TPS65911:
222 tps6591x_irqs_chip = &tps65911_irq_chip;
223 break;
224 }
225
226 tps65910->chip_irq = irq;
227 ret = regmap_add_irq_chip(tps65910->regmap, tps65910->chip_irq,
228 IRQF_ONESHOT, pdata->irq_base,
229 tps6591x_irqs_chip, &tps65910->irq_data);
230 if (ret < 0) {
231 dev_warn(tps65910->dev,
232 "Failed to add irq_chip %d\n", ret);
233 return ret;
234 }
235 return ret;
236}
237
238int tps65910_irq_exit(struct tps65910 *tps65910)
239{
240 if (tps65910->chip_irq > 0)
241 regmap_del_irq_chip(tps65910->chip_irq, tps65910->irq_data);
242 return 0;
243}
diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c
index 27fbbe510101..d4d4eb5b5b6f 100644
--- a/drivers/mfd/tps65910.c
+++ b/drivers/mfd/tps65910.c
@@ -19,6 +19,9 @@
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/irqdomain.h>
22#include <linux/mfd/core.h> 25#include <linux/mfd/core.h>
23#include <linux/regmap.h> 26#include <linux/regmap.h>
24#include <linux/mfd/tps65910.h> 27#include <linux/mfd/tps65910.h>
@@ -50,6 +53,219 @@ static struct mfd_cell tps65910s[] = {
50}; 53};
51 54
52 55
56static const struct regmap_irq tps65911_irqs[] = {
57 /* INT_STS */
58 [TPS65911_IRQ_PWRHOLD_F] = {
59 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
60 .reg_offset = 0,
61 },
62 [TPS65911_IRQ_VBAT_VMHI] = {
63 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
64 .reg_offset = 0,
65 },
66 [TPS65911_IRQ_PWRON] = {
67 .mask = INT_MSK_PWRON_IT_MSK_MASK,
68 .reg_offset = 0,
69 },
70 [TPS65911_IRQ_PWRON_LP] = {
71 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
72 .reg_offset = 0,
73 },
74 [TPS65911_IRQ_PWRHOLD_R] = {
75 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
76 .reg_offset = 0,
77 },
78 [TPS65911_IRQ_HOTDIE] = {
79 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
80 .reg_offset = 0,
81 },
82 [TPS65911_IRQ_RTC_ALARM] = {
83 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
84 .reg_offset = 0,
85 },
86 [TPS65911_IRQ_RTC_PERIOD] = {
87 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
88 .reg_offset = 0,
89 },
90
91 /* INT_STS2 */
92 [TPS65911_IRQ_GPIO0_R] = {
93 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
94 .reg_offset = 1,
95 },
96 [TPS65911_IRQ_GPIO0_F] = {
97 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
98 .reg_offset = 1,
99 },
100 [TPS65911_IRQ_GPIO1_R] = {
101 .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
102 .reg_offset = 1,
103 },
104 [TPS65911_IRQ_GPIO1_F] = {
105 .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
106 .reg_offset = 1,
107 },
108 [TPS65911_IRQ_GPIO2_R] = {
109 .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
110 .reg_offset = 1,
111 },
112 [TPS65911_IRQ_GPIO2_F] = {
113 .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
114 .reg_offset = 1,
115 },
116 [TPS65911_IRQ_GPIO3_R] = {
117 .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
118 .reg_offset = 1,
119 },
120 [TPS65911_IRQ_GPIO3_F] = {
121 .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
122 .reg_offset = 1,
123 },
124
125 /* INT_STS2 */
126 [TPS65911_IRQ_GPIO4_R] = {
127 .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
128 .reg_offset = 2,
129 },
130 [TPS65911_IRQ_GPIO4_F] = {
131 .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
132 .reg_offset = 2,
133 },
134 [TPS65911_IRQ_GPIO5_R] = {
135 .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
136 .reg_offset = 2,
137 },
138 [TPS65911_IRQ_GPIO5_F] = {
139 .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
140 .reg_offset = 2,
141 },
142 [TPS65911_IRQ_WTCHDG] = {
143 .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
144 .reg_offset = 2,
145 },
146 [TPS65911_IRQ_VMBCH2_H] = {
147 .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
148 .reg_offset = 2,
149 },
150 [TPS65911_IRQ_VMBCH2_L] = {
151 .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
152 .reg_offset = 2,
153 },
154 [TPS65911_IRQ_PWRDN] = {
155 .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
156 .reg_offset = 2,
157 },
158};
159
160static const struct regmap_irq tps65910_irqs[] = {
161 /* INT_STS */
162 [TPS65910_IRQ_VBAT_VMBDCH] = {
163 .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
164 .reg_offset = 0,
165 },
166 [TPS65910_IRQ_VBAT_VMHI] = {
167 .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
168 .reg_offset = 0,
169 },
170 [TPS65910_IRQ_PWRON] = {
171 .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
172 .reg_offset = 0,
173 },
174 [TPS65910_IRQ_PWRON_LP] = {
175 .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
176 .reg_offset = 0,
177 },
178 [TPS65910_IRQ_PWRHOLD] = {
179 .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
180 .reg_offset = 0,
181 },
182 [TPS65910_IRQ_HOTDIE] = {
183 .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
184 .reg_offset = 0,
185 },
186 [TPS65910_IRQ_RTC_ALARM] = {
187 .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
188 .reg_offset = 0,
189 },
190 [TPS65910_IRQ_RTC_PERIOD] = {
191 .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
192 .reg_offset = 0,
193 },
194
195 /* INT_STS2 */
196 [TPS65910_IRQ_GPIO_R] = {
197 .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
198 .reg_offset = 1,
199 },
200 [TPS65910_IRQ_GPIO_F] = {
201 .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
202 .reg_offset = 1,
203 },
204};
205
206static struct regmap_irq_chip tps65911_irq_chip = {
207 .name = "tps65910",
208 .irqs = tps65911_irqs,
209 .num_irqs = ARRAY_SIZE(tps65911_irqs),
210 .num_regs = 3,
211 .irq_reg_stride = 2,
212 .status_base = TPS65910_INT_STS,
213 .mask_base = TPS65910_INT_MSK,
214 .ack_base = TPS65910_INT_MSK,
215};
216
217static struct regmap_irq_chip tps65910_irq_chip = {
218 .name = "tps65910",
219 .irqs = tps65910_irqs,
220 .num_irqs = ARRAY_SIZE(tps65910_irqs),
221 .num_regs = 2,
222 .irq_reg_stride = 2,
223 .status_base = TPS65910_INT_STS,
224 .mask_base = TPS65910_INT_MSK,
225 .ack_base = TPS65910_INT_MSK,
226};
227
228static int tps65910_irq_init(struct tps65910 *tps65910, int irq,
229 struct tps65910_platform_data *pdata)
230{
231 int ret = 0;
232 static struct regmap_irq_chip *tps6591x_irqs_chip;
233
234 if (!irq) {
235 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
236 return -EINVAL;
237 }
238
239 if (!pdata) {
240 dev_warn(tps65910->dev, "No interrupt support, no pdata\n");
241 return -EINVAL;
242 }
243
244 switch (tps65910_chip_id(tps65910)) {
245 case TPS65910:
246 tps6591x_irqs_chip = &tps65910_irq_chip;
247 break;
248 case TPS65911:
249 tps6591x_irqs_chip = &tps65911_irq_chip;
250 break;
251 }
252
253 tps65910->chip_irq = irq;
254 ret = regmap_add_irq_chip(tps65910->regmap, tps65910->chip_irq,
255 IRQF_ONESHOT, pdata->irq_base,
256 tps6591x_irqs_chip, &tps65910->irq_data);
257 if (ret < 0)
258 dev_warn(tps65910->dev, "Failed to add irq_chip %d\n", ret);
259 return ret;
260}
261
262static int tps65910_irq_exit(struct tps65910 *tps65910)
263{
264 if (tps65910->chip_irq > 0)
265 regmap_del_irq_chip(tps65910->chip_irq, tps65910->irq_data);
266 return 0;
267}
268
53static bool is_volatile_reg(struct device *dev, unsigned int reg) 269static bool is_volatile_reg(struct device *dev, unsigned int reg)
54{ 270{
55 struct tps65910 *tps65910 = dev_get_drvdata(dev); 271 struct tps65910 *tps65910 = dev_get_drvdata(dev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 19:01:10 -0500