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authorGeert Uytterhoeven <geert@linux-m68k.org>2010-04-04 05:00:35 -0400
committerJames Bottomley <James.Bottomley@suse.de>2010-05-02 15:55:17 -0400
commit21351013402ab4556d1ef62aed6cbe8dfb809f77 (patch)
tree1fc91dfe92457cb656c19ea451cac04c72781a22 /drivers
parentbe4540db062975ce557daf0119153fb17ecd6693 (diff)
[SCSI] a3000: Reindentation
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/scsi/a3000.c280
-rw-r--r--drivers/scsi/a3000.h46
2 files changed, 163 insertions, 163 deletions
diff --git a/drivers/scsi/a3000.c b/drivers/scsi/a3000.c
index 291568442aa9..31434f7c3685 100644
--- a/drivers/scsi/a3000.c
+++ b/drivers/scsi/a3000.c
@@ -19,26 +19,26 @@
19#include "wd33c93.h" 19#include "wd33c93.h"
20#include "a3000.h" 20#include "a3000.h"
21 21
22#include<linux/stat.h> 22#include <linux/stat.h>
23 23
24#define DMA(ptr) ((a3000_scsiregs *)((ptr)->base)) 24
25#define HDATA(ptr) ((struct WD33C93_hostdata *)((ptr)->hostdata)) 25#define DMA(ptr) ((a3000_scsiregs *)((ptr)->base))
26#define HDATA(ptr) ((struct WD33C93_hostdata *)((ptr)->hostdata))
26 27
27static struct Scsi_Host *a3000_host = NULL; 28static struct Scsi_Host *a3000_host = NULL;
28 29
29static int a3000_release(struct Scsi_Host *instance); 30static int a3000_release(struct Scsi_Host *instance);
30 31
31static irqreturn_t a3000_intr (int irq, void *dummy) 32static irqreturn_t a3000_intr(int irq, void *dummy)
32{ 33{
33 unsigned long flags; 34 unsigned long flags;
34 unsigned int status = DMA(a3000_host)->ISTR; 35 unsigned int status = DMA(a3000_host)->ISTR;
35 36
36 if (!(status & ISTR_INT_P)) 37 if (!(status & ISTR_INT_P))
37 return IRQ_NONE; 38 return IRQ_NONE;
38 if (status & ISTR_INTS) 39 if (status & ISTR_INTS) {
39 {
40 spin_lock_irqsave(a3000_host->host_lock, flags); 40 spin_lock_irqsave(a3000_host->host_lock, flags);
41 wd33c93_intr (a3000_host); 41 wd33c93_intr(a3000_host);
42 spin_unlock_irqrestore(a3000_host->host_lock, flags); 42 spin_unlock_irqrestore(a3000_host->host_lock, flags);
43 return IRQ_HANDLED; 43 return IRQ_HANDLED;
44 } 44 }
@@ -48,161 +48,161 @@ static irqreturn_t a3000_intr (int irq, void *dummy)
48 48
49static int dma_setup(struct scsi_cmnd *cmd, int dir_in) 49static int dma_setup(struct scsi_cmnd *cmd, int dir_in)
50{ 50{
51 unsigned short cntr = CNTR_PDMD | CNTR_INTEN; 51 unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
52 unsigned long addr = virt_to_bus(cmd->SCp.ptr); 52 unsigned long addr = virt_to_bus(cmd->SCp.ptr);
53 53
54 /* 54 /*
55 * if the physical address has the wrong alignment, or if 55 * if the physical address has the wrong alignment, or if
56 * physical address is bad, or if it is a write and at the 56 * physical address is bad, or if it is a write and at the
57 * end of a physical memory chunk, then allocate a bounce 57 * end of a physical memory chunk, then allocate a bounce
58 * buffer 58 * buffer
59 */ 59 */
60 if (addr & A3000_XFER_MASK) 60 if (addr & A3000_XFER_MASK) {
61 { 61 HDATA(a3000_host)->dma_bounce_len =
62 HDATA(a3000_host)->dma_bounce_len = (cmd->SCp.this_residual + 511) 62 (cmd->SCp.this_residual + 511) & ~0x1ff;
63 & ~0x1ff; 63 HDATA(a3000_host)->dma_bounce_buffer =
64 HDATA(a3000_host)->dma_bounce_buffer = 64 kmalloc(HDATA(a3000_host)->dma_bounce_len, GFP_KERNEL);
65 kmalloc (HDATA(a3000_host)->dma_bounce_len, GFP_KERNEL); 65
66 66 /* can't allocate memory; use PIO */
67 /* can't allocate memory; use PIO */ 67 if (!HDATA(a3000_host)->dma_bounce_buffer) {
68 if (!HDATA(a3000_host)->dma_bounce_buffer) { 68 HDATA(a3000_host)->dma_bounce_len = 0;
69 HDATA(a3000_host)->dma_bounce_len = 0; 69 return 1;
70 return 1; 70 }
71 } 71
72 72 if (!dir_in) {
73 if (!dir_in) { 73 /* copy to bounce buffer for a write */
74 /* copy to bounce buffer for a write */ 74 memcpy(HDATA(a3000_host)->dma_bounce_buffer,
75 memcpy (HDATA(a3000_host)->dma_bounce_buffer, 75 cmd->SCp.ptr, cmd->SCp.this_residual);
76 cmd->SCp.ptr, cmd->SCp.this_residual); 76 }
77
78 addr = virt_to_bus(HDATA(a3000_host)->dma_bounce_buffer);
77 } 79 }
78 80
79 addr = virt_to_bus(HDATA(a3000_host)->dma_bounce_buffer); 81 /* setup dma direction */
80 } 82 if (!dir_in)
81 83 cntr |= CNTR_DDIR;
82 /* setup dma direction */
83 if (!dir_in)
84 cntr |= CNTR_DDIR;
85 84
86 /* remember direction */ 85 /* remember direction */
87 HDATA(a3000_host)->dma_dir = dir_in; 86 HDATA(a3000_host)->dma_dir = dir_in;
88 87
89 DMA(a3000_host)->CNTR = cntr; 88 DMA(a3000_host)->CNTR = cntr;
90 89
91 /* setup DMA *physical* address */ 90 /* setup DMA *physical* address */
92 DMA(a3000_host)->ACR = addr; 91 DMA(a3000_host)->ACR = addr;
93 92
94 if (dir_in) 93 if (dir_in) {
95 /* invalidate any cache */ 94 /* invalidate any cache */
96 cache_clear (addr, cmd->SCp.this_residual); 95 cache_clear(addr, cmd->SCp.this_residual);
97 else 96 } else {
98 /* push any dirty cache */ 97 /* push any dirty cache */
99 cache_push (addr, cmd->SCp.this_residual); 98 cache_push(addr, cmd->SCp.this_residual);
99 }
100 100
101 /* start DMA */ 101 /* start DMA */
102 mb(); /* make sure setup is completed */ 102 mb(); /* make sure setup is completed */
103 DMA(a3000_host)->ST_DMA = 1; 103 DMA(a3000_host)->ST_DMA = 1;
104 mb(); /* make sure DMA has started before next IO */ 104 mb(); /* make sure DMA has started before next IO */
105 105
106 /* return success */ 106 /* return success */
107 return 0; 107 return 0;
108} 108}
109 109
110static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt, 110static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt,
111 int status) 111 int status)
112{ 112{
113 /* disable SCSI interrupts */ 113 /* disable SCSI interrupts */
114 unsigned short cntr = CNTR_PDMD; 114 unsigned short cntr = CNTR_PDMD;
115 115
116 if (!HDATA(instance)->dma_dir) 116 if (!HDATA(instance)->dma_dir)
117 cntr |= CNTR_DDIR; 117 cntr |= CNTR_DDIR;
118 118
119 DMA(instance)->CNTR = cntr; 119 DMA(instance)->CNTR = cntr;
120 mb(); /* make sure CNTR is updated before next IO */ 120 mb(); /* make sure CNTR is updated before next IO */
121 121
122 /* flush if we were reading */ 122 /* flush if we were reading */
123 if (HDATA(instance)->dma_dir) { 123 if (HDATA(instance)->dma_dir) {
124 DMA(instance)->FLUSH = 1; 124 DMA(instance)->FLUSH = 1;
125 mb(); /* don't allow prefetch */ 125 mb(); /* don't allow prefetch */
126 while (!(DMA(instance)->ISTR & ISTR_FE_FLG)) 126 while (!(DMA(instance)->ISTR & ISTR_FE_FLG))
127 barrier(); 127 barrier();
128 mb(); /* no IO until FLUSH is done */ 128 mb(); /* no IO until FLUSH is done */
129 } 129 }
130 130
131 /* clear a possible interrupt */ 131 /* clear a possible interrupt */
132 /* I think that this CINT is only necessary if you are 132 /* I think that this CINT is only necessary if you are
133 * using the terminal count features. HM 7 Mar 1994 133 * using the terminal count features. HM 7 Mar 1994
134 */ 134 */
135 DMA(instance)->CINT = 1; 135 DMA(instance)->CINT = 1;
136 136
137 /* stop DMA */ 137 /* stop DMA */
138 DMA(instance)->SP_DMA = 1; 138 DMA(instance)->SP_DMA = 1;
139 mb(); /* make sure DMA is stopped before next IO */ 139 mb(); /* make sure DMA is stopped before next IO */
140 140
141 /* restore the CONTROL bits (minus the direction flag) */ 141 /* restore the CONTROL bits (minus the direction flag) */
142 DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN; 142 DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN;
143 mb(); /* make sure CNTR is updated before next IO */ 143 mb(); /* make sure CNTR is updated before next IO */
144 144
145 /* copy from a bounce buffer, if necessary */ 145 /* copy from a bounce buffer, if necessary */
146 if (status && HDATA(instance)->dma_bounce_buffer) { 146 if (status && HDATA(instance)->dma_bounce_buffer) {
147 if (SCpnt) { 147 if (SCpnt) {
148 if (HDATA(instance)->dma_dir && SCpnt) 148 if (HDATA(instance)->dma_dir && SCpnt)
149 memcpy (SCpnt->SCp.ptr, 149 memcpy(SCpnt->SCp.ptr,
150 HDATA(instance)->dma_bounce_buffer, 150 HDATA(instance)->dma_bounce_buffer,
151 SCpnt->SCp.this_residual); 151 SCpnt->SCp.this_residual);
152 kfree (HDATA(instance)->dma_bounce_buffer); 152 kfree(HDATA(instance)->dma_bounce_buffer);
153 HDATA(instance)->dma_bounce_buffer = NULL; 153 HDATA(instance)->dma_bounce_buffer = NULL;
154 HDATA(instance)->dma_bounce_len = 0; 154 HDATA(instance)->dma_bounce_len = 0;
155 } else { 155 } else {
156 kfree (HDATA(instance)->dma_bounce_buffer); 156 kfree(HDATA(instance)->dma_bounce_buffer);
157 HDATA(instance)->dma_bounce_buffer = NULL; 157 HDATA(instance)->dma_bounce_buffer = NULL;
158 HDATA(instance)->dma_bounce_len = 0; 158 HDATA(instance)->dma_bounce_len = 0;
159 }
159 } 160 }
160 }
161} 161}
162 162
163static int __init a3000_detect(struct scsi_host_template *tpnt) 163static int __init a3000_detect(struct scsi_host_template *tpnt)
164{ 164{
165 wd33c93_regs regs; 165 wd33c93_regs regs;
166 166
167 if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI)) 167 if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI))
168 return 0; 168 return 0;
169 if (!request_mem_region(0xDD0000, 256, "wd33c93")) 169 if (!request_mem_region(0xDD0000, 256, "wd33c93"))
170 return 0; 170 return 0;
171 171
172 tpnt->proc_name = "A3000"; 172 tpnt->proc_name = "A3000";
173 tpnt->proc_info = &wd33c93_proc_info; 173 tpnt->proc_info = &wd33c93_proc_info;
174 174
175 a3000_host = scsi_register (tpnt, sizeof(struct WD33C93_hostdata)); 175 a3000_host = scsi_register(tpnt, sizeof(struct WD33C93_hostdata));
176 if (a3000_host == NULL) 176 if (a3000_host == NULL)
177 goto fail_register; 177 goto fail_register;
178 178
179 a3000_host->base = ZTWO_VADDR(0xDD0000); 179 a3000_host->base = ZTWO_VADDR(0xDD0000);
180 a3000_host->irq = IRQ_AMIGA_PORTS; 180 a3000_host->irq = IRQ_AMIGA_PORTS;
181 DMA(a3000_host)->DAWR = DAWR_A3000; 181 DMA(a3000_host)->DAWR = DAWR_A3000;
182 regs.SASR = &(DMA(a3000_host)->SASR); 182 regs.SASR = &(DMA(a3000_host)->SASR);
183 regs.SCMD = &(DMA(a3000_host)->SCMD); 183 regs.SCMD = &(DMA(a3000_host)->SCMD);
184 HDATA(a3000_host)->no_sync = 0xff; 184 HDATA(a3000_host)->no_sync = 0xff;
185 HDATA(a3000_host)->fast = 0; 185 HDATA(a3000_host)->fast = 0;
186 HDATA(a3000_host)->dma_mode = CTRL_DMA; 186 HDATA(a3000_host)->dma_mode = CTRL_DMA;
187 wd33c93_init(a3000_host, regs, dma_setup, dma_stop, WD33C93_FS_12_15); 187 wd33c93_init(a3000_host, regs, dma_setup, dma_stop, WD33C93_FS_12_15);
188 if (request_irq(IRQ_AMIGA_PORTS, a3000_intr, IRQF_SHARED, "A3000 SCSI", 188 if (request_irq(IRQ_AMIGA_PORTS, a3000_intr, IRQF_SHARED, "A3000 SCSI",
189 a3000_intr)) 189 a3000_intr))
190 goto fail_irq; 190 goto fail_irq;
191 DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN; 191 DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN;
192 192
193 return 1; 193 return 1;
194 194
195fail_irq: 195fail_irq:
196 scsi_unregister(a3000_host); 196 scsi_unregister(a3000_host);
197fail_register: 197fail_register:
198 release_mem_region(0xDD0000, 256); 198 release_mem_region(0xDD0000, 256);
199 return 0; 199 return 0;
200} 200}
201 201
202static int a3000_bus_reset(struct scsi_cmnd *cmd) 202static int a3000_bus_reset(struct scsi_cmnd *cmd)
203{ 203{
204 /* FIXME perform bus-specific reset */ 204 /* FIXME perform bus-specific reset */
205 205
206 /* FIXME 2: kill this entire function, which should 206 /* FIXME 2: kill this entire function, which should
207 cause mid-layer to call wd33c93_host_reset anyway? */ 207 cause mid-layer to call wd33c93_host_reset anyway? */
208 208
@@ -236,10 +236,10 @@ static struct scsi_host_template driver_template = {
236 236
237static int a3000_release(struct Scsi_Host *instance) 237static int a3000_release(struct Scsi_Host *instance)
238{ 238{
239 DMA(instance)->CNTR = 0; 239 DMA(instance)->CNTR = 0;
240 release_mem_region(0xDD0000, 256); 240 release_mem_region(0xDD0000, 256);
241 free_irq(IRQ_AMIGA_PORTS, a3000_intr); 241 free_irq(IRQ_AMIGA_PORTS, a3000_intr);
242 return 1; 242 return 1;
243} 243}
244 244
245MODULE_LICENSE("GPL"); 245MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/a3000.h b/drivers/scsi/a3000.h
index c7afe16fd6e4..684813ee378c 100644
--- a/drivers/scsi/a3000.h
+++ b/drivers/scsi/a3000.h
@@ -12,40 +12,40 @@
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#ifndef CMD_PER_LUN 14#ifndef CMD_PER_LUN
15#define CMD_PER_LUN 2 15#define CMD_PER_LUN 2
16#endif 16#endif
17 17
18#ifndef CAN_QUEUE 18#ifndef CAN_QUEUE
19#define CAN_QUEUE 16 19#define CAN_QUEUE 16
20#endif 20#endif
21 21
22/* 22/*
23 * if the transfer address ANDed with this results in a non-zero 23 * if the transfer address ANDed with this results in a non-zero
24 * result, then we can't use DMA. 24 * result, then we can't use DMA.
25 */ 25 */
26#define A3000_XFER_MASK (0x00000003) 26#define A3000_XFER_MASK (0x00000003)
27 27
28typedef struct { 28typedef struct {
29 unsigned char pad1[2]; 29 unsigned char pad1[2];
30 volatile unsigned short DAWR; 30 volatile unsigned short DAWR;
31 volatile unsigned int WTC; 31 volatile unsigned int WTC;
32 unsigned char pad2[2]; 32 unsigned char pad2[2];
33 volatile unsigned short CNTR; 33 volatile unsigned short CNTR;
34 volatile unsigned long ACR; 34 volatile unsigned long ACR;
35 unsigned char pad3[2]; 35 unsigned char pad3[2];
36 volatile unsigned short ST_DMA; 36 volatile unsigned short ST_DMA;
37 unsigned char pad4[2]; 37 unsigned char pad4[2];
38 volatile unsigned short FLUSH; 38 volatile unsigned short FLUSH;
39 unsigned char pad5[2]; 39 unsigned char pad5[2];
40 volatile unsigned short CINT; 40 volatile unsigned short CINT;
41 unsigned char pad6[2]; 41 unsigned char pad6[2];
42 volatile unsigned short ISTR; 42 volatile unsigned short ISTR;
43 unsigned char pad7[30]; 43 unsigned char pad7[30];
44 volatile unsigned short SP_DMA; 44 volatile unsigned short SP_DMA;
45 unsigned char pad8; 45 unsigned char pad8;
46 volatile unsigned char SASR; 46 volatile unsigned char SASR;
47 unsigned char pad9; 47 unsigned char pad9;
48 volatile unsigned char SCMD; 48 volatile unsigned char SCMD;
49} a3000_scsiregs; 49} a3000_scsiregs;
50 50
51#define DAWR_A3000 (3) 51#define DAWR_A3000 (3)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 05:31:50 -0500