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authorMauro Carvalho Chehab <mchehab@redhat.com>2009-09-13 10:30:11 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-09-18 22:47:38 -0400
commit1a9fc855643f8770c92ba99fad5f209358c6030d (patch)
tree6543fad6dc85485136588a3022e917d6942f30be /drivers
parentbb4c9a74b88aac4c30566cc8616a01c47028761f (diff)
V4L/DVB (12733): cx25821: some CodingStyle fixes
The original driver were generated with some dos editor, and used their own coding style. This patch does some automatic CodingStyle fixes, by running dos2unix and Lindent tools. More work still needs to be done for it to use upstream CodingStyle. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/cx25821/cx25821-alsa.c413
-rw-r--r--drivers/staging/cx25821/cx25821-audio-upstream.c1628
-rw-r--r--drivers/staging/cx25821/cx25821-audio-upstream.h119
-rw-r--r--drivers/staging/cx25821/cx25821-audio.h117
-rw-r--r--drivers/staging/cx25821/cx25821-audups11.c615
-rw-r--r--drivers/staging/cx25821/cx25821-biffuncs.h88
-rw-r--r--drivers/staging/cx25821/cx25821-cards.c84
-rw-r--r--drivers/staging/cx25821/cx25821-core.c2462
-rw-r--r--drivers/staging/cx25821/cx25821-gpio.c154
-rw-r--r--drivers/staging/cx25821/cx25821-gpio.h1
-rw-r--r--drivers/staging/cx25821/cx25821-i2c.c247
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-defines.h92
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-reg.h909
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-video.c1346
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-video.h60
-rw-r--r--drivers/staging/cx25821/cx25821-reg.h3033
-rw-r--r--drivers/staging/cx25821/cx25821-sram.h527
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream-ch2.c1682
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream-ch2.h208
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream.c1817
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream.h222
-rw-r--r--drivers/staging/cx25821/cx25821-video.c1576
-rw-r--r--drivers/staging/cx25821/cx25821-video.h90
-rw-r--r--drivers/staging/cx25821/cx25821-video0.c636
-rw-r--r--drivers/staging/cx25821/cx25821-video1.c635
-rw-r--r--drivers/staging/cx25821/cx25821-video2.c647
-rw-r--r--drivers/staging/cx25821/cx25821-video3.c645
-rw-r--r--drivers/staging/cx25821/cx25821-video4.c642
-rw-r--r--drivers/staging/cx25821/cx25821-video5.c645
-rw-r--r--drivers/staging/cx25821/cx25821-video6.c645
-rw-r--r--drivers/staging/cx25821/cx25821-video7.c639
-rw-r--r--drivers/staging/cx25821/cx25821-videoioctl.c710
-rw-r--r--drivers/staging/cx25821/cx25821-vidups10.c614
-rw-r--r--drivers/staging/cx25821/cx25821-vidups9.c614
-rw-r--r--drivers/staging/cx25821/cx25821.h756
35 files changed, 12592 insertions, 12726 deletions
diff --git a/drivers/staging/cx25821/cx25821-alsa.c b/drivers/staging/cx25821/cx25821-alsa.c
index 3ab5641d298c..0e162f7c8ab8 100644
--- a/drivers/staging/cx25821/cx25821-alsa.c
+++ b/drivers/staging/cx25821/cx25821-alsa.c
@@ -1,26 +1,25 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on SAA713x ALSA driver and CX88 driver 6 * Based on SAA713x ALSA driver and CX88 driver
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, version 2 10 * the Free Software Foundation, version 2
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * 20 *
21 */ 21 */
22 22
23
24#include <linux/module.h> 23#include <linux/module.h>
25#include <linux/init.h> 24#include <linux/init.h>
26#include <linux/device.h> 25#include <linux/device.h>
@@ -37,7 +36,6 @@
37#include <sound/initval.h> 36#include <sound/initval.h>
38#include <sound/tlv.h> 37#include <sound/tlv.h>
39 38
40
41#include "cx25821.h" 39#include "cx25821.h"
42#include "cx25821-reg.h" 40#include "cx25821-reg.h"
43 41
@@ -49,52 +47,49 @@
49#define dprintk_core(level,fmt, arg...) if (debug >= level) \ 47#define dprintk_core(level,fmt, arg...) if (debug >= level) \
50 printk(KERN_DEBUG "%s/1: " fmt, chip->dev->name , ## arg) 48 printk(KERN_DEBUG "%s/1: " fmt, chip->dev->name , ## arg)
51 49
52
53/**************************************************************************** 50/****************************************************************************
54 Data type declarations - Can be moded to a header file later 51 Data type declarations - Can be moded to a header file later
55 ****************************************************************************/ 52 ****************************************************************************/
56 53
57
58static struct snd_card *snd_cx25821_cards[SNDRV_CARDS]; 54static struct snd_card *snd_cx25821_cards[SNDRV_CARDS];
59static int devno; 55static int devno;
60 56
61struct cx25821_audio_dev { 57struct cx25821_audio_dev {
62 struct cx25821_dev *dev; 58 struct cx25821_dev *dev;
63 struct cx25821_dmaqueue q; 59 struct cx25821_dmaqueue q;
64 60
65 /* pci i/o */ 61 /* pci i/o */
66 struct pci_dev *pci; 62 struct pci_dev *pci;
67 63
68 /* audio controls */ 64 /* audio controls */
69 int irq; 65 int irq;
70 66
71 struct snd_card *card; 67 struct snd_card *card;
72 68
73 unsigned long iobase; 69 unsigned long iobase;
74 spinlock_t reg_lock; 70 spinlock_t reg_lock;
75 atomic_t count; 71 atomic_t count;
76 72
77 unsigned int dma_size; 73 unsigned int dma_size;
78 unsigned int period_size; 74 unsigned int period_size;
79 unsigned int num_periods; 75 unsigned int num_periods;
80 76
81 struct videobuf_dmabuf *dma_risc; 77 struct videobuf_dmabuf *dma_risc;
82 78
83 struct cx25821_buffer *buf; 79 struct cx25821_buffer *buf;
84 80
85 struct snd_pcm_substream *substream; 81 struct snd_pcm_substream *substream;
86}; 82};
87typedef struct cx25821_audio_dev snd_cx25821_card_t; 83typedef struct cx25821_audio_dev snd_cx25821_card_t;
88 84
89 85
90
91/**************************************************************************** 86/****************************************************************************
92 Module global static vars 87 Module global static vars
93 ****************************************************************************/ 88 ****************************************************************************/
94 89
95static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 90static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
96static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 91static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
97static int enable[SNDRV_CARDS] = {1, [1 ... (SNDRV_CARDS - 1)] = 1}; 92static int enable[SNDRV_CARDS] = { 1,[1...(SNDRV_CARDS - 1)] = 1 };
98 93
99module_param_array(enable, bool, NULL, 0444); 94module_param_array(enable, bool, NULL, 0444);
100MODULE_PARM_DESC(enable, "Enable cx25821 soundcard. default enabled."); 95MODULE_PARM_DESC(enable, "Enable cx25821 soundcard. default enabled.");
@@ -102,7 +97,6 @@ MODULE_PARM_DESC(enable, "Enable cx25821 soundcard. default enabled.");
102module_param_array(index, int, NULL, 0444); 97module_param_array(index, int, NULL, 0444);
103MODULE_PARM_DESC(index, "Index value for cx25821 capture interface(s)."); 98MODULE_PARM_DESC(index, "Index value for cx25821 capture interface(s).");
104 99
105
106/**************************************************************************** 100/****************************************************************************
107 Module macros 101 Module macros
108 ****************************************************************************/ 102 ****************************************************************************/
@@ -110,11 +104,11 @@ MODULE_PARM_DESC(index, "Index value for cx25821 capture interface(s).");
110MODULE_DESCRIPTION("ALSA driver module for cx25821 based capture cards"); 104MODULE_DESCRIPTION("ALSA driver module for cx25821 based capture cards");
111MODULE_AUTHOR("Hiep Huynh"); 105MODULE_AUTHOR("Hiep Huynh");
112MODULE_LICENSE("GPL"); 106MODULE_LICENSE("GPL");
113MODULE_SUPPORTED_DEVICE("{{Conexant,25821}");//"{{Conexant,23881}," 107MODULE_SUPPORTED_DEVICE("{{Conexant,25821}"); //"{{Conexant,23881},"
114 108
115static unsigned int debug; 109static unsigned int debug;
116module_param(debug,int,0644); 110module_param(debug, int, 0644);
117MODULE_PARM_DESC(debug,"enable debug messages"); 111MODULE_PARM_DESC(debug, "enable debug messages");
118 112
119/**************************************************************************** 113/****************************************************************************
120 Module specific funtions 114 Module specific funtions
@@ -123,7 +117,7 @@ MODULE_PARM_DESC(debug,"enable debug messages");
123#define AUD_INT_DN_RISCI1 (1 << 0) 117#define AUD_INT_DN_RISCI1 (1 << 0)
124#define AUD_INT_UP_RISCI1 (1 << 1) 118#define AUD_INT_UP_RISCI1 (1 << 1)
125#define AUD_INT_RDS_DN_RISCI1 (1 << 2) 119#define AUD_INT_RDS_DN_RISCI1 (1 << 2)
126#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */ 120#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */
127#define AUD_INT_UP_RISCI2 (1 << 5) 121#define AUD_INT_UP_RISCI2 (1 << 5)
128#define AUD_INT_RDS_DN_RISCI2 (1 << 6) 122#define AUD_INT_RDS_DN_RISCI2 (1 << 6)
129#define AUD_INT_DN_SYNC (1 << 12) 123#define AUD_INT_DN_SYNC (1 << 12)
@@ -140,40 +134,46 @@ MODULE_PARM_DESC(debug,"enable debug messages");
140 * BOARD Specific: Sets audio DMA 134 * BOARD Specific: Sets audio DMA
141 */ 135 */
142 136
143static int _cx25821_start_audio_dma(snd_cx25821_card_t *chip) 137static int _cx25821_start_audio_dma(snd_cx25821_card_t * chip)
144{ 138{
145 struct cx25821_buffer *buf = chip->buf; 139 struct cx25821_buffer *buf = chip->buf;
146 struct cx25821_dev * dev = chip->dev; 140 struct cx25821_dev *dev = chip->dev;
147 struct sram_channel *audio_ch = &cx25821_sram_channels[AUDIO_SRAM_CHANNEL]; 141 struct sram_channel *audio_ch =
142 &cx25821_sram_channels[AUDIO_SRAM_CHANNEL];
148 u32 tmp = 0; 143 u32 tmp = 0;
149 144
150 // enable output on the GPIO 0 for the MCLK ADC (Audio) 145 // enable output on the GPIO 0 for the MCLK ADC (Audio)
151 cx25821_set_gpiopin_direction( chip->dev, 0, 0 ); 146 cx25821_set_gpiopin_direction(chip->dev, 0, 0);
152 147
153 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ 148 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */
154 cx_clear(AUD_INT_DMA_CTL, FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN ); 149 cx_clear(AUD_INT_DMA_CTL,
150 FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN);
155 151
156 /* setup fifo + format - out channel */ 152 /* setup fifo + format - out channel */
157 cx25821_sram_channel_setup_audio(chip->dev, audio_ch, buf->bpl, buf->risc.dma); 153 cx25821_sram_channel_setup_audio(chip->dev, audio_ch, buf->bpl,
154 buf->risc.dma);
158 155
159 /* sets bpl size */ 156 /* sets bpl size */
160 cx_write(AUD_A_LNGTH, buf->bpl); 157 cx_write(AUD_A_LNGTH, buf->bpl);
161 158
162 /* reset counter */ 159 /* reset counter */
163 cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET); //GP_COUNT_CONTROL_RESET = 0x3 160 cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET); //GP_COUNT_CONTROL_RESET = 0x3
164 atomic_set(&chip->count, 0); 161 atomic_set(&chip->count, 0);
165 162
166 //Set the input mode to 16-bit 163 //Set the input mode to 16-bit
167 tmp = cx_read(AUD_A_CFG); 164 tmp = cx_read(AUD_A_CFG);
168 cx_write(AUD_A_CFG, tmp | FLD_AUD_DST_PK_MODE | FLD_AUD_DST_ENABLE | FLD_AUD_CLK_ENABLE); 165 cx_write(AUD_A_CFG,
166 tmp | FLD_AUD_DST_PK_MODE | FLD_AUD_DST_ENABLE |
167 FLD_AUD_CLK_ENABLE);
169 168
170 //printk(KERN_INFO "DEBUG: Start audio DMA, %d B/line, cmds_start(0x%x)= %d lines/FIFO, %d periods, %d " 169 //printk(KERN_INFO "DEBUG: Start audio DMA, %d B/line, cmds_start(0x%x)= %d lines/FIFO, %d periods, %d "
171 // "byte buffer\n", buf->bpl, audio_ch->cmds_start, cx_read(audio_ch->cmds_start + 12)>>1, 170 // "byte buffer\n", buf->bpl, audio_ch->cmds_start, cx_read(audio_ch->cmds_start + 12)>>1,
172 // chip->num_periods, buf->bpl * chip->num_periods); 171 // chip->num_periods, buf->bpl * chip->num_periods);
173
174 172
175 /* Enables corresponding bits at AUD_INT_STAT */ 173 /* Enables corresponding bits at AUD_INT_STAT */
176 cx_write(AUD_A_INT_MSK, FLD_AUD_DST_RISCI1 | FLD_AUD_DST_OF | FLD_AUD_DST_SYNC | FLD_AUD_DST_OPC_ERR ); 174 cx_write(AUD_A_INT_MSK,
175 FLD_AUD_DST_RISCI1 | FLD_AUD_DST_OF | FLD_AUD_DST_SYNC |
176 FLD_AUD_DST_OPC_ERR);
177 177
178 /* Clean any pending interrupt bits already set */ 178 /* Clean any pending interrupt bits already set */
179 cx_write(AUD_A_INT_STAT, ~0); 179 cx_write(AUD_A_INT_STAT, ~0);
@@ -181,9 +181,10 @@ static int _cx25821_start_audio_dma(snd_cx25821_card_t *chip)
181 /* enable audio irqs */ 181 /* enable audio irqs */
182 cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT); 182 cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
183 183
184 // Turn on audio downstream fifo and risc enable 0x101 184 // Turn on audio downstream fifo and risc enable 0x101
185 tmp = cx_read(AUD_INT_DMA_CTL); 185 tmp = cx_read(AUD_INT_DMA_CTL);
186 cx_set(AUD_INT_DMA_CTL, tmp | (FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN) ); 186 cx_set(AUD_INT_DMA_CTL,
187 tmp | (FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN));
187 188
188 mdelay(100); 189 mdelay(100);
189 return 0; 190 return 0;
@@ -192,16 +193,19 @@ static int _cx25821_start_audio_dma(snd_cx25821_card_t *chip)
192/* 193/*
193 * BOARD Specific: Resets audio DMA 194 * BOARD Specific: Resets audio DMA
194 */ 195 */
195static int _cx25821_stop_audio_dma(snd_cx25821_card_t *chip) 196static int _cx25821_stop_audio_dma(snd_cx25821_card_t * chip)
196{ 197{
197 struct cx25821_dev *dev = chip->dev; 198 struct cx25821_dev *dev = chip->dev;
198 199
199 /* stop dma */ 200 /* stop dma */
200 cx_clear(AUD_INT_DMA_CTL, FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN ); 201 cx_clear(AUD_INT_DMA_CTL,
202 FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN);
201 203
202 /* disable irqs */ 204 /* disable irqs */
203 cx_clear(PCI_INT_MSK, PCI_MSK_AUD_INT); 205 cx_clear(PCI_INT_MSK, PCI_MSK_AUD_INT);
204 cx_clear(AUD_A_INT_MSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC | AUD_INT_DN_RISCI2 | AUD_INT_DN_RISCI1); 206 cx_clear(AUD_A_INT_MSK,
207 AUD_INT_OPC_ERR | AUD_INT_DN_SYNC | AUD_INT_DN_RISCI2 |
208 AUD_INT_DN_RISCI1);
205 209
206 return 0; 210 return 0;
207} 211}
@@ -212,50 +216,54 @@ static int _cx25821_stop_audio_dma(snd_cx25821_card_t *chip)
212 * BOARD Specific: IRQ dma bits 216 * BOARD Specific: IRQ dma bits
213 */ 217 */
214static char *cx25821_aud_irqs[32] = { 218static char *cx25821_aud_irqs[32] = {
215 "dn_risci1", "up_risci1", "rds_dn_risc1", /* 0-2 */ 219 "dn_risci1", "up_risci1", "rds_dn_risc1", /* 0-2 */
216 NULL, /* reserved */ 220 NULL, /* reserved */
217 "dn_risci2", "up_risci2", "rds_dn_risc2", /* 4-6 */ 221 "dn_risci2", "up_risci2", "rds_dn_risc2", /* 4-6 */
218 NULL, /* reserved */ 222 NULL, /* reserved */
219 "dnf_of", "upf_uf", "rds_dnf_uf", /* 8-10 */ 223 "dnf_of", "upf_uf", "rds_dnf_uf", /* 8-10 */
220 NULL, /* reserved */ 224 NULL, /* reserved */
221 "dn_sync", "up_sync", "rds_dn_sync", /* 12-14 */ 225 "dn_sync", "up_sync", "rds_dn_sync", /* 12-14 */
222 NULL, /* reserved */ 226 NULL, /* reserved */
223 "opc_err", "par_err", "rip_err", /* 16-18 */ 227 "opc_err", "par_err", "rip_err", /* 16-18 */
224 "pci_abort", "ber_irq", "mchg_irq" /* 19-21 */ 228 "pci_abort", "ber_irq", "mchg_irq" /* 19-21 */
225}; 229};
226 230
227/* 231/*
228 * BOARD Specific: Threats IRQ audio specific calls 232 * BOARD Specific: Threats IRQ audio specific calls
229 */ 233 */
230static void cx25821_aud_irq(snd_cx25821_card_t *chip, u32 status, u32 mask) 234static void cx25821_aud_irq(snd_cx25821_card_t * chip, u32 status, u32 mask)
231{ 235{
232 struct cx25821_dev *dev = chip->dev; 236 struct cx25821_dev *dev = chip->dev;
233 237
234 if (0 == (status & mask)) 238 if (0 == (status & mask)) {
235 {
236 return; 239 return;
237 } 240 }
238 241
239 cx_write(AUD_A_INT_STAT, status); 242 cx_write(AUD_A_INT_STAT, status);
240 if (debug > 1 || (status & mask & ~0xff)) 243 if (debug > 1 || (status & mask & ~0xff))
241 cx25821_print_irqbits(dev->name, "irq aud", 244 cx25821_print_irqbits(dev->name, "irq aud",
242 cx25821_aud_irqs, ARRAY_SIZE(cx25821_aud_irqs), 245 cx25821_aud_irqs,
243 status, mask); 246 ARRAY_SIZE(cx25821_aud_irqs), status,
247 mask);
244 248
245 /* risc op code error */ 249 /* risc op code error */
246 if (status & AUD_INT_OPC_ERR) { 250 if (status & AUD_INT_OPC_ERR) {
247 printk(KERN_WARNING "WARNING %s/1: Audio risc op code error\n",dev->name); 251 printk(KERN_WARNING "WARNING %s/1: Audio risc op code error\n",
248 252 dev->name);
249 cx_clear(AUD_INT_DMA_CTL, FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN ); 253
250 cx25821_sram_channel_dump_audio(dev, &cx25821_sram_channels[AUDIO_SRAM_CHANNEL]); 254 cx_clear(AUD_INT_DMA_CTL,
255 FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN);
256 cx25821_sram_channel_dump_audio(dev,
257 &cx25821_sram_channels
258 [AUDIO_SRAM_CHANNEL]);
251 } 259 }
252 if (status & AUD_INT_DN_SYNC) { 260 if (status & AUD_INT_DN_SYNC) {
253 printk(KERN_WARNING "WARNING %s: Downstream sync error!\n",dev->name); 261 printk(KERN_WARNING "WARNING %s: Downstream sync error!\n",
262 dev->name);
254 cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET); 263 cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET);
255 return; 264 return;
256 } 265 }
257 266
258
259 /* risc1 downstream */ 267 /* risc1 downstream */
260 if (status & AUD_INT_DN_RISCI1) { 268 if (status & AUD_INT_DN_RISCI1) {
261 atomic_set(&chip->count, cx_read(AUD_A_GPCNT)); 269 atomic_set(&chip->count, cx_read(AUD_A_GPCNT));
@@ -263,7 +271,6 @@ static void cx25821_aud_irq(snd_cx25821_card_t *chip, u32 status, u32 mask)
263 } 271 }
264} 272}
265 273
266
267/* 274/*
268 * BOARD Specific: Handles IRQ calls 275 * BOARD Specific: Handles IRQ calls
269 */ 276 */
@@ -276,30 +283,26 @@ static irqreturn_t cx25821_irq(int irq, void *dev_id)
276 int loop, handled = 0; 283 int loop, handled = 0;
277 int audint_count = 0; 284 int audint_count = 0;
278 285
279
280 audint_status = cx_read(AUD_A_INT_STAT); 286 audint_status = cx_read(AUD_A_INT_STAT);
281 audint_mask = cx_read(AUD_A_INT_MSK); 287 audint_mask = cx_read(AUD_A_INT_MSK);
282 audint_count = cx_read(AUD_A_GPCNT); 288 audint_count = cx_read(AUD_A_GPCNT);
283 status = cx_read(PCI_INT_STAT); 289 status = cx_read(PCI_INT_STAT);
284 290
285 for (loop = 0; loop < 1; loop++) 291 for (loop = 0; loop < 1; loop++) {
286 {
287 status = cx_read(PCI_INT_STAT); 292 status = cx_read(PCI_INT_STAT);
288 if (0 == status) 293 if (0 == status) {
289 {
290 status = cx_read(PCI_INT_STAT); 294 status = cx_read(PCI_INT_STAT);
291 audint_status = cx_read(AUD_A_INT_STAT); 295 audint_status = cx_read(AUD_A_INT_STAT);
292 audint_mask = cx_read(AUD_A_INT_MSK); 296 audint_mask = cx_read(AUD_A_INT_MSK);
293 297
294 if (status) 298 if (status) {
295 {
296 handled = 1; 299 handled = 1;
297 cx_write(PCI_INT_STAT, status); 300 cx_write(PCI_INT_STAT, status);
298 301
299 cx25821_aud_irq(chip, audint_status, audint_mask); 302 cx25821_aud_irq(chip, audint_status,
303 audint_mask);
300 break; 304 break;
301 } 305 } else
302 else
303 goto out; 306 goto out;
304 } 307 }
305 308
@@ -314,19 +317,18 @@ static irqreturn_t cx25821_irq(int irq, void *dev_id)
314 if (handled) 317 if (handled)
315 cx_write(PCI_INT_STAT, pci_status); 318 cx_write(PCI_INT_STAT, pci_status);
316 319
317 out: 320 out:
318 return IRQ_RETVAL(handled); 321 return IRQ_RETVAL(handled);
319} 322}
320 323
321 324static int dsp_buffer_free(snd_cx25821_card_t * chip)
322static int dsp_buffer_free(snd_cx25821_card_t *chip)
323{ 325{
324 BUG_ON(!chip->dma_size); 326 BUG_ON(!chip->dma_size);
325 327
326 dprintk(2,"Freeing buffer\n"); 328 dprintk(2, "Freeing buffer\n");
327 videobuf_sg_dma_unmap(&chip->pci->dev, chip->dma_risc); 329 videobuf_sg_dma_unmap(&chip->pci->dev, chip->dma_risc);
328 videobuf_dma_free(chip->dma_risc); 330 videobuf_dma_free(chip->dma_risc);
329 btcx_riscmem_free(chip->pci,&chip->buf->risc); 331 btcx_riscmem_free(chip->pci, &chip->buf->risc);
330 kfree(chip->buf); 332 kfree(chip->buf);
331 333
332 chip->dma_risc = NULL; 334 chip->dma_risc = NULL;
@@ -345,27 +347,24 @@ static int dsp_buffer_free(snd_cx25821_card_t *chip)
345#define DEFAULT_FIFO_SIZE 384 347#define DEFAULT_FIFO_SIZE 384
346static struct snd_pcm_hardware snd_cx25821_digital_hw = { 348static struct snd_pcm_hardware snd_cx25821_digital_hw = {
347 .info = SNDRV_PCM_INFO_MMAP | 349 .info = SNDRV_PCM_INFO_MMAP |
348 SNDRV_PCM_INFO_INTERLEAVED | 350 SNDRV_PCM_INFO_INTERLEAVED |
349 SNDRV_PCM_INFO_BLOCK_TRANSFER | 351 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID,
350 SNDRV_PCM_INFO_MMAP_VALID,
351 .formats = SNDRV_PCM_FMTBIT_S16_LE, 352 .formats = SNDRV_PCM_FMTBIT_S16_LE,
352 353
353 .rates = SNDRV_PCM_RATE_48000, 354 .rates = SNDRV_PCM_RATE_48000,
354 .rate_min = 48000, 355 .rate_min = 48000,
355 .rate_max = 48000, 356 .rate_max = 48000,
356 .channels_min = 2, 357 .channels_min = 2,
357 .channels_max = 2, 358 .channels_max = 2,
358 /* Analog audio output will be full of clicks and pops if there 359 /* Analog audio output will be full of clicks and pops if there
359 are not exactly four lines in the SRAM FIFO buffer. */ 360 are not exactly four lines in the SRAM FIFO buffer. */
360 .period_bytes_min = DEFAULT_FIFO_SIZE/3, 361 .period_bytes_min = DEFAULT_FIFO_SIZE / 3,
361 .period_bytes_max = DEFAULT_FIFO_SIZE/3, 362 .period_bytes_max = DEFAULT_FIFO_SIZE / 3,
362 .periods_min = 1, 363 .periods_min = 1,
363 .periods_max = AUDIO_LINE_SIZE, 364 .periods_max = AUDIO_LINE_SIZE,
364 .buffer_bytes_max = (AUDIO_LINE_SIZE*AUDIO_LINE_SIZE), //128*128 = 16384 = 1024 * 16 365 .buffer_bytes_max = (AUDIO_LINE_SIZE * AUDIO_LINE_SIZE), //128*128 = 16384 = 1024 * 16
365}; 366};
366 367
367
368
369/* 368/*
370 * audio pcm capture open callback 369 * audio pcm capture open callback
371 */ 370 */
@@ -378,11 +377,12 @@ static int snd_cx25821_pcm_open(struct snd_pcm_substream *substream)
378 377
379 if (!chip) { 378 if (!chip) {
380 printk(KERN_ERR "DEBUG: cx25821 can't find device struct." 379 printk(KERN_ERR "DEBUG: cx25821 can't find device struct."
381 " Can't proceed with open\n"); 380 " Can't proceed with open\n");
382 return -ENODEV; 381 return -ENODEV;
383 } 382 }
384 383
385 err = snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIODS); 384 err =
385 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIODS);
386 if (err < 0) 386 if (err < 0)
387 goto _error; 387 goto _error;
388 388
@@ -390,13 +390,12 @@ static int snd_cx25821_pcm_open(struct snd_pcm_substream *substream)
390 390
391 runtime->hw = snd_cx25821_digital_hw; 391 runtime->hw = snd_cx25821_digital_hw;
392 392
393 if (cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size != DEFAULT_FIFO_SIZE) 393 if (cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size !=
394 { 394 DEFAULT_FIFO_SIZE) {
395 bpl = cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size / 3; //since there are 3 audio Clusters 395 bpl = cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size / 3; //since there are 3 audio Clusters
396 bpl &= ~7; /* must be multiple of 8 */ 396 bpl &= ~7; /* must be multiple of 8 */
397 397
398 if( bpl > AUDIO_LINE_SIZE ) 398 if (bpl > AUDIO_LINE_SIZE) {
399 {
400 bpl = AUDIO_LINE_SIZE; 399 bpl = AUDIO_LINE_SIZE;
401 } 400 }
402 runtime->hw.period_bytes_min = bpl; 401 runtime->hw.period_bytes_min = bpl;
@@ -404,8 +403,8 @@ static int snd_cx25821_pcm_open(struct snd_pcm_substream *substream)
404 } 403 }
405 404
406 return 0; 405 return 0;
407_error: 406 _error:
408 dprintk(1,"Error opening PCM!\n"); 407 dprintk(1, "Error opening PCM!\n");
409 return err; 408 return err;
410} 409}
411 410
@@ -420,8 +419,8 @@ static int snd_cx25821_close(struct snd_pcm_substream *substream)
420/* 419/*
421 * hw_params callback 420 * hw_params callback
422 */ 421 */
423static int snd_cx25821_hw_params(struct snd_pcm_substream * substream, 422static int snd_cx25821_hw_params(struct snd_pcm_substream *substream,
424 struct snd_pcm_hw_params * hw_params) 423 struct snd_pcm_hw_params *hw_params)
425{ 424{
426 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); 425 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream);
427 struct videobuf_dmabuf *dma; 426 struct videobuf_dmabuf *dma;
@@ -434,37 +433,34 @@ static int snd_cx25821_hw_params(struct snd_pcm_substream * substream,
434 substream->runtime->dma_area = NULL; 433 substream->runtime->dma_area = NULL;
435 } 434 }
436 435
437
438 chip->period_size = params_period_bytes(hw_params); 436 chip->period_size = params_period_bytes(hw_params);
439 chip->num_periods = params_periods(hw_params); 437 chip->num_periods = params_periods(hw_params);
440 chip->dma_size = chip->period_size * params_periods(hw_params); 438 chip->dma_size = chip->period_size * params_periods(hw_params);
441 439
442 BUG_ON(!chip->dma_size); 440 BUG_ON(!chip->dma_size);
443 BUG_ON(chip->num_periods & (chip->num_periods-1)); 441 BUG_ON(chip->num_periods & (chip->num_periods - 1));
444 442
445 buf = videobuf_sg_alloc(sizeof(*buf)); 443 buf = videobuf_sg_alloc(sizeof(*buf));
446 if (NULL == buf) 444 if (NULL == buf)
447 return -ENOMEM; 445 return -ENOMEM;
448 446
449 447 if (chip->period_size > AUDIO_LINE_SIZE) {
450 if( chip->period_size > AUDIO_LINE_SIZE )
451 {
452 chip->period_size = AUDIO_LINE_SIZE; 448 chip->period_size = AUDIO_LINE_SIZE;
453 } 449 }
454 450
455
456 buf->vb.memory = V4L2_MEMORY_MMAP; 451 buf->vb.memory = V4L2_MEMORY_MMAP;
457 buf->vb.field = V4L2_FIELD_NONE; 452 buf->vb.field = V4L2_FIELD_NONE;
458 buf->vb.width = chip->period_size; 453 buf->vb.width = chip->period_size;
459 buf->bpl = chip->period_size; 454 buf->bpl = chip->period_size;
460 buf->vb.height = chip->num_periods; 455 buf->vb.height = chip->num_periods;
461 buf->vb.size = chip->dma_size; 456 buf->vb.size = chip->dma_size;
462 457
463 dma = videobuf_to_dma(&buf->vb); 458 dma = videobuf_to_dma(&buf->vb);
464 videobuf_dma_init(dma); 459 videobuf_dma_init(dma);
465 460
466 ret = videobuf_dma_init_kernel(dma, PCI_DMA_FROMDEVICE, 461 ret = videobuf_dma_init_kernel(dma, PCI_DMA_FROMDEVICE,
467 (PAGE_ALIGN(buf->vb.size) >> PAGE_SHIFT)); 462 (PAGE_ALIGN(buf->vb.size) >>
463 PAGE_SHIFT));
468 if (ret < 0) 464 if (ret < 0)
469 goto error; 465 goto error;
470 466
@@ -472,19 +468,19 @@ static int snd_cx25821_hw_params(struct snd_pcm_substream * substream,
472 if (ret < 0) 468 if (ret < 0)
473 goto error; 469 goto error;
474 470
475 471 ret =
476 ret = cx25821_risc_databuffer_audio(chip->pci, &buf->risc, dma->sglist, buf->vb.width, buf->vb.height, 1); 472 cx25821_risc_databuffer_audio(chip->pci, &buf->risc, dma->sglist,
477 if (ret < 0) 473 buf->vb.width, buf->vb.height, 1);
478 { 474 if (ret < 0) {
479 printk(KERN_INFO "DEBUG: ERROR after cx25821_risc_databuffer_audio() \n"); 475 printk(KERN_INFO
476 "DEBUG: ERROR after cx25821_risc_databuffer_audio() \n");
480 goto error; 477 goto error;
481 } 478 }
482 479
483
484 /* Loop back to start of program */ 480 /* Loop back to start of program */
485 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP|RISC_IRQ1|RISC_CNT_INC); 481 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
486 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma); 482 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
487 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 483 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
488 484
489 buf->vb.state = VIDEOBUF_PREPARED; 485 buf->vb.state = VIDEOBUF_PREPARED;
490 486
@@ -497,7 +493,7 @@ static int snd_cx25821_hw_params(struct snd_pcm_substream * substream,
497 493
498 return 0; 494 return 0;
499 495
500error: 496 error:
501 kfree(buf); 497 kfree(buf);
502 return ret; 498 return ret;
503} 499}
@@ -505,7 +501,7 @@ error:
505/* 501/*
506 * hw free callback 502 * hw free callback
507 */ 503 */
508static int snd_cx25821_hw_free(struct snd_pcm_substream * substream) 504static int snd_cx25821_hw_free(struct snd_pcm_substream *substream)
509{ 505{
510 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); 506 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream);
511 507
@@ -528,7 +524,8 @@ static int snd_cx25821_prepare(struct snd_pcm_substream *substream)
528/* 524/*
529 * trigger callback 525 * trigger callback
530 */ 526 */
531static int snd_cx25821_card_trigger(struct snd_pcm_substream *substream, int cmd) 527static int snd_cx25821_card_trigger(struct snd_pcm_substream *substream,
528 int cmd)
532{ 529{
533 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); 530 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream);
534 int err = 0; 531 int err = 0;
@@ -536,17 +533,16 @@ static int snd_cx25821_card_trigger(struct snd_pcm_substream *substream, int cmd
536 /* Local interrupts are already disabled by ALSA */ 533 /* Local interrupts are already disabled by ALSA */
537 spin_lock(&chip->reg_lock); 534 spin_lock(&chip->reg_lock);
538 535
539 switch (cmd) 536 switch (cmd) {
540 { 537 case SNDRV_PCM_TRIGGER_START:
541 case SNDRV_PCM_TRIGGER_START: 538 err = _cx25821_start_audio_dma(chip);
542 err = _cx25821_start_audio_dma(chip); 539 break;
543 break; 540 case SNDRV_PCM_TRIGGER_STOP:
544 case SNDRV_PCM_TRIGGER_STOP: 541 err = _cx25821_stop_audio_dma(chip);
545 err = _cx25821_stop_audio_dma(chip); 542 break;
546 break; 543 default:
547 default: 544 err = -EINVAL;
548 err = -EINVAL; 545 break;
549 break;
550 } 546 }
551 547
552 spin_unlock(&chip->reg_lock); 548 spin_unlock(&chip->reg_lock);
@@ -557,7 +553,8 @@ static int snd_cx25821_card_trigger(struct snd_pcm_substream *substream, int cmd
557/* 553/*
558 * pointer callback 554 * pointer callback
559 */ 555 */
560static snd_pcm_uframes_t snd_cx25821_pointer(struct snd_pcm_substream *substream) 556static snd_pcm_uframes_t snd_cx25821_pointer(struct snd_pcm_substream
557 *substream)
561{ 558{
562 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream); 559 snd_cx25821_card_t *chip = snd_pcm_substream_chip(substream);
563 struct snd_pcm_runtime *runtime = substream->runtime; 560 struct snd_pcm_runtime *runtime = substream->runtime;
@@ -565,14 +562,14 @@ static snd_pcm_uframes_t snd_cx25821_pointer(struct snd_pcm_substream *substream
565 562
566 count = atomic_read(&chip->count); 563 count = atomic_read(&chip->count);
567 564
568 return runtime->period_size * (count & (runtime->periods-1)); 565 return runtime->period_size * (count & (runtime->periods - 1));
569} 566}
570 567
571/* 568/*
572 * page callback (needed for mmap) 569 * page callback (needed for mmap)
573 */ 570 */
574static struct page *snd_cx25821_page(struct snd_pcm_substream *substream, 571static struct page *snd_cx25821_page(struct snd_pcm_substream *substream,
575 unsigned long offset) 572 unsigned long offset)
576{ 573{
577 void *pageptr = substream->runtime->dma_area + offset; 574 void *pageptr = substream->runtime->dma_area + offset;
578 575
@@ -594,20 +591,19 @@ static struct snd_pcm_ops snd_cx25821_pcm_ops = {
594 .page = snd_cx25821_page, 591 .page = snd_cx25821_page,
595}; 592};
596 593
597
598/* 594/*
599 * ALSA create a PCM device: Called when initializing the board. Sets up the name and hooks up 595 * ALSA create a PCM device: Called when initializing the board. Sets up the name and hooks up
600 * the callbacks 596 * the callbacks
601 */ 597 */
602static int snd_cx25821_pcm(snd_cx25821_card_t *chip, int device, char *name) 598static int snd_cx25821_pcm(snd_cx25821_card_t * chip, int device, char *name)
603{ 599{
604 struct snd_pcm *pcm; 600 struct snd_pcm *pcm;
605 int err; 601 int err;
606 602
607 err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm); 603 err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
608 if (err < 0) 604 if (err < 0) {
609 { 605 printk(KERN_INFO "ERROR: FAILED snd_pcm_new() in %s\n",
610 printk(KERN_INFO "ERROR: FAILED snd_pcm_new() in %s\n", __func__); 606 __func__);
611 return err; 607 return err;
612 } 608 }
613 pcm->private_data = chip; 609 pcm->private_data = chip;
@@ -618,7 +614,6 @@ static int snd_cx25821_pcm(snd_cx25821_card_t *chip, int device, char *name)
618 return 0; 614 return 0;
619} 615}
620 616
621
622/**************************************************************************** 617/****************************************************************************
623 Basic Flow for Sound Devices 618 Basic Flow for Sound Devices
624 ****************************************************************************/ 619 ****************************************************************************/
@@ -629,15 +624,16 @@ static int snd_cx25821_pcm(snd_cx25821_card_t *chip, int device, char *name)
629 */ 624 */
630 625
631static struct pci_device_id cx25821_audio_pci_tbl[] __devinitdata = { 626static struct pci_device_id cx25821_audio_pci_tbl[] __devinitdata = {
632 {0x14f1,0x0920,PCI_ANY_ID,PCI_ANY_ID,0,0,0}, 627 {0x14f1, 0x0920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
633 {0, } 628 {0,}
634}; 629};
630
635MODULE_DEVICE_TABLE(pci, cx25821_audio_pci_tbl); 631MODULE_DEVICE_TABLE(pci, cx25821_audio_pci_tbl);
636 632
637/* 633/*
638 * Not used in the function snd_cx25821_dev_free so removing 634 * Not used in the function snd_cx25821_dev_free so removing
639 * from the file. 635 * from the file.
640 */ 636 */
641/* 637/*
642static int snd_cx25821_free(snd_cx25821_card_t *chip) 638static int snd_cx25821_free(snd_cx25821_card_t *chip)
643{ 639{
@@ -649,12 +645,12 @@ static int snd_cx25821_free(snd_cx25821_card_t *chip)
649 645
650 return 0; 646 return 0;
651} 647}
652*/ 648*/
653 649
654/* 650/*
655 * Component Destructor 651 * Component Destructor
656 */ 652 */
657static void snd_cx25821_dev_free(struct snd_card * card) 653static void snd_cx25821_dev_free(struct snd_card *card)
658{ 654{
659 snd_cx25821_card_t *chip = card->private_data; 655 snd_cx25821_card_t *chip = card->private_data;
660 656
@@ -662,19 +658,18 @@ static void snd_cx25821_dev_free(struct snd_card * card)
662 snd_card_free(chip->card); 658 snd_card_free(chip->card);
663} 659}
664 660
665
666/* 661/*
667 * Alsa Constructor - Component probe 662 * Alsa Constructor - Component probe
668 */ 663 */
669static int cx25821_audio_initdev(struct cx25821_dev *dev) 664static int cx25821_audio_initdev(struct cx25821_dev *dev)
670{ 665{
671 struct snd_card *card; 666 struct snd_card *card;
672 snd_cx25821_card_t *chip; 667 snd_cx25821_card_t *chip;
673 int err; 668 int err;
674 669
675 if (devno >= SNDRV_CARDS) 670 if (devno >= SNDRV_CARDS) {
676 { 671 printk(KERN_INFO "DEBUG ERROR: devno >= SNDRV_CARDS %s\n",
677 printk(KERN_INFO "DEBUG ERROR: devno >= SNDRV_CARDS %s\n", __func__); 672 __func__);
678 return (-ENODEV); 673 return (-ENODEV);
679 } 674 }
680 675
@@ -684,10 +679,13 @@ static int cx25821_audio_initdev(struct cx25821_dev *dev)
684 return (-ENOENT); 679 return (-ENOENT);
685 } 680 }
686 681
687 card = snd_card_new(index[devno], id[devno], THIS_MODULE, sizeof(snd_cx25821_card_t)); 682 card =
688 if (!card) 683 snd_card_new(index[devno], id[devno], THIS_MODULE,
689 { 684 sizeof(snd_cx25821_card_t));
690 printk(KERN_INFO "DEBUG ERROR: cannot create snd_card_new in %s\n", __func__); 685 if (!card) {
686 printk(KERN_INFO
687 "DEBUG ERROR: cannot create snd_card_new in %s\n",
688 __func__);
691 return (-ENOMEM); 689 return (-ENOMEM);
692 } 690 }
693 691
@@ -703,37 +701,38 @@ static int cx25821_audio_initdev(struct cx25821_dev *dev)
703 chip->pci = dev->pci; 701 chip->pci = dev->pci;
704 chip->iobase = pci_resource_start(dev->pci, 0); 702 chip->iobase = pci_resource_start(dev->pci, 0);
705 703
706
707 chip->irq = dev->pci->irq; 704 chip->irq = dev->pci->irq;
708 705
709 err = request_irq(dev->pci->irq, cx25821_irq, 706 err = request_irq(dev->pci->irq, cx25821_irq,
710 IRQF_SHARED | IRQF_DISABLED, chip->dev->name, chip); 707 IRQF_SHARED | IRQF_DISABLED, chip->dev->name, chip);
711 708
712 if (err < 0) { 709 if (err < 0) {
713 printk(KERN_ERR "ERROR %s: can't get IRQ %d for ALSA\n", chip->dev->name, dev->pci->irq); 710 printk(KERN_ERR "ERROR %s: can't get IRQ %d for ALSA\n",
711 chip->dev->name, dev->pci->irq);
714 goto error; 712 goto error;
715 } 713 }
716 714
717 715 if ((err = snd_cx25821_pcm(chip, 0, "cx25821 Digital")) < 0) {
718 if ((err = snd_cx25821_pcm(chip, 0, "cx25821 Digital")) < 0) 716 printk(KERN_INFO
719 { 717 "DEBUG ERROR: cannot create snd_cx25821_pcm %s\n",
720 printk(KERN_INFO "DEBUG ERROR: cannot create snd_cx25821_pcm %s\n", __func__); 718 __func__);
721 goto error; 719 goto error;
722 } 720 }
723 721
724 snd_card_set_dev(card, &chip->pci->dev); 722 snd_card_set_dev(card, &chip->pci->dev);
725 723
726
727 strcpy(card->shortname, "cx25821"); 724 strcpy(card->shortname, "cx25821");
728 sprintf(card->longname, "%s at 0x%lx irq %d", chip->dev->name, chip->iobase, chip->irq); 725 sprintf(card->longname, "%s at 0x%lx irq %d", chip->dev->name,
729 strcpy (card->mixername, "CX25821"); 726 chip->iobase, chip->irq);
727 strcpy(card->mixername, "CX25821");
730 728
731 printk(KERN_INFO "%s/%i: ALSA support for cx25821 boards\n", card->driver, devno); 729 printk(KERN_INFO "%s/%i: ALSA support for cx25821 boards\n",
730 card->driver, devno);
732 731
733 err = snd_card_register(card); 732 err = snd_card_register(card);
734 if (err < 0) 733 if (err < 0) {
735 { 734 printk(KERN_INFO "DEBUG ERROR: cannot register sound card %s\n",
736 printk(KERN_INFO "DEBUG ERROR: cannot register sound card %s\n", __func__); 735 __func__);
737 goto error; 736 goto error;
738 } 737 }
739 738
@@ -742,12 +741,11 @@ static int cx25821_audio_initdev(struct cx25821_dev *dev)
742 devno++; 741 devno++;
743 return 0; 742 return 0;
744 743
745error: 744 error:
746 snd_card_free(card); 745 snd_card_free(card);
747 return err; 746 return err;
748} 747}
749 748
750
751/**************************************************************************** 749/****************************************************************************
752 LINUX MODULE INIT 750 LINUX MODULE INIT
753 ****************************************************************************/ 751 ****************************************************************************/
@@ -768,13 +766,14 @@ static int cx25821_alsa_init(void)
768 struct cx25821_dev *dev = NULL; 766 struct cx25821_dev *dev = NULL;
769 struct list_head *list; 767 struct list_head *list;
770 768
771 list_for_each(list,&cx25821_devlist) { 769 list_for_each(list, &cx25821_devlist) {
772 dev = list_entry(list, struct cx25821_dev, devlist); 770 dev = list_entry(list, struct cx25821_dev, devlist);
773 cx25821_audio_initdev(dev); 771 cx25821_audio_initdev(dev);
774 } 772 }
775 773
776 if (dev == NULL) 774 if (dev == NULL)
777 printk(KERN_INFO "cx25821 ERROR ALSA: no cx25821 cards found\n"); 775 printk(KERN_INFO
776 "cx25821 ERROR ALSA: no cx25821 cards found\n");
778 777
779 return 0; 778 return 0;
780 779
diff --git a/drivers/staging/cx25821/cx25821-audio-upstream.c b/drivers/staging/cx25821/cx25821-audio-upstream.c
index 376c953a8786..ddddf651266b 100644
--- a/drivers/staging/cx25821/cx25821-audio-upstream.c
+++ b/drivers/staging/cx25821/cx25821-audio-upstream.c
@@ -1,824 +1,804 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23 23#include "cx25821-video.h"
24#include "cx25821-video.h" 24#include "cx25821-audio-upstream.h"
25#include "cx25821-audio-upstream.h" 25
26 26#include <linux/fs.h>
27#include <linux/fs.h> 27#include <linux/errno.h>
28#include <linux/errno.h> 28#include <linux/kernel.h>
29#include <linux/kernel.h> 29#include <linux/init.h>
30#include <linux/init.h> 30#include <linux/module.h>
31#include <linux/module.h> 31#include <linux/syscalls.h>
32#include <linux/syscalls.h> 32#include <linux/file.h>
33#include <linux/file.h> 33#include <linux/fcntl.h>
34#include <linux/fcntl.h> 34#include <linux/delay.h>
35#include <linux/delay.h> 35#include <asm/uaccess.h>
36#include <asm/uaccess.h> 36
37 37MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
38 38MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
39MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); 39MODULE_LICENSE("GPL");
40MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); 40
41MODULE_LICENSE("GPL"); 41static int _intr_msk =
42 42 FLD_AUD_SRC_RISCI1 | FLD_AUD_SRC_OF | FLD_AUD_SRC_SYNC |
43 43 FLD_AUD_SRC_OPC_ERR;
44static int _intr_msk = FLD_AUD_SRC_RISCI1 | FLD_AUD_SRC_OF | FLD_AUD_SRC_SYNC | FLD_AUD_SRC_OPC_ERR; 44
45 45int cx25821_sram_channel_setup_upstream_audio(struct cx25821_dev *dev,
46 46 struct sram_channel *ch,
47int cx25821_sram_channel_setup_upstream_audio(struct cx25821_dev *dev, 47 unsigned int bpl, u32 risc)
48 struct sram_channel *ch, 48{
49 unsigned int bpl, u32 risc) 49 unsigned int i, lines;
50{ 50 u32 cdt;
51 unsigned int i, lines; 51
52 u32 cdt; 52 if (ch->cmds_start == 0) {
53 53 cx_write(ch->ptr1_reg, 0);
54 54 cx_write(ch->ptr2_reg, 0);
55 if (ch->cmds_start == 0) { 55 cx_write(ch->cnt2_reg, 0);
56 cx_write(ch->ptr1_reg, 0); 56 cx_write(ch->cnt1_reg, 0);
57 cx_write(ch->ptr2_reg, 0); 57 return 0;
58 cx_write(ch->cnt2_reg, 0); 58 }
59 cx_write(ch->cnt1_reg, 0); 59
60 return 0; 60 bpl = (bpl + 7) & ~7; /* alignment */
61 } 61 cdt = ch->cdt;
62 62 lines = ch->fifo_size / bpl;
63 bpl = (bpl + 7) & ~7; /* alignment */ 63
64 cdt = ch->cdt; 64 if (lines > 3) {
65 lines = ch->fifo_size / bpl; 65 lines = 3;
66 66 }
67 if (lines > 3) 67
68 { 68 BUG_ON(lines < 2);
69 lines = 3; 69
70 } 70 /* write CDT */
71 71 for (i = 0; i < lines; i++) {
72 BUG_ON(lines < 2); 72 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
73 73 cx_write(cdt + 16 * i + 4, 0);
74 74 cx_write(cdt + 16 * i + 8, 0);
75 /* write CDT */ 75 cx_write(cdt + 16 * i + 12, 0);
76 for (i = 0; i < lines; i++) { 76 }
77 cx_write(cdt + 16*i, ch->fifo_start + bpl*i); 77
78 cx_write(cdt + 16*i + 4, 0); 78 /* write CMDS */
79 cx_write(cdt + 16*i + 8, 0); 79 cx_write(ch->cmds_start + 0, risc);
80 cx_write(cdt + 16*i + 12, 0); 80
81 } 81 cx_write(ch->cmds_start + 4, 0);
82 82 cx_write(ch->cmds_start + 8, cdt);
83 /* write CMDS */ 83 cx_write(ch->cmds_start + 12, AUDIO_CDT_SIZE_QW);
84 cx_write(ch->cmds_start + 0, risc); 84 cx_write(ch->cmds_start + 16, ch->ctrl_start);
85 85
86 cx_write(ch->cmds_start + 4, 0); 86 //IQ size
87 cx_write(ch->cmds_start + 8, cdt); 87 cx_write(ch->cmds_start + 20, AUDIO_IQ_SIZE_DW);
88 cx_write(ch->cmds_start + 12, AUDIO_CDT_SIZE_QW); 88
89 cx_write(ch->cmds_start + 16, ch->ctrl_start); 89 for (i = 24; i < 80; i += 4)
90 90 cx_write(ch->cmds_start + i, 0);
91 //IQ size 91
92 cx_write(ch->cmds_start + 20, AUDIO_IQ_SIZE_DW); 92 /* fill registers */
93 93 cx_write(ch->ptr1_reg, ch->fifo_start);
94 for (i = 24; i < 80; i += 4) 94 cx_write(ch->ptr2_reg, cdt);
95 cx_write(ch->cmds_start + i, 0); 95 cx_write(ch->cnt2_reg, AUDIO_CDT_SIZE_QW);
96 96 cx_write(ch->cnt1_reg, AUDIO_CLUSTER_SIZE_QW - 1);
97 /* fill registers */ 97
98 cx_write(ch->ptr1_reg, ch->fifo_start); 98 return 0;
99 cx_write(ch->ptr2_reg, cdt); 99}
100 cx_write(ch->cnt2_reg, AUDIO_CDT_SIZE_QW); 100
101 cx_write(ch->cnt1_reg, AUDIO_CLUSTER_SIZE_QW - 1); 101static __le32 *cx25821_risc_field_upstream_audio(struct cx25821_dev *dev,
102 102 __le32 * rp,
103 return 0; 103 dma_addr_t databuf_phys_addr,
104} 104 unsigned int bpl,
105 105 int fifo_enable)
106 106{
107static __le32 *cx25821_risc_field_upstream_audio( struct cx25821_dev *dev, __le32 *rp, 107 unsigned int line;
108 dma_addr_t databuf_phys_addr, 108 struct sram_channel *sram_ch =
109 unsigned int bpl, int fifo_enable) 109 &dev->sram_channels[dev->_audio_upstream_channel_select];
110{ 110 int offset = 0;
111 unsigned int line; 111
112 struct sram_channel *sram_ch = &dev->sram_channels[dev->_audio_upstream_channel_select]; 112 /* scan lines */
113 int offset = 0; 113 for (line = 0; line < LINES_PER_AUDIO_BUFFER; line++) {
114 114 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
115 115 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
116 /* scan lines */ 116 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
117 for (line = 0; line < LINES_PER_AUDIO_BUFFER; line++) 117
118 { 118 // Check if we need to enable the FIFO after the first 3 lines
119 *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl); 119 // For the upstream audio channel, the risc engine will enable the FIFO.
120 *(rp++) = cpu_to_le32(databuf_phys_addr + offset); 120 if (fifo_enable && line == 2) {
121 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 121 *(rp++) = RISC_WRITECR;
122 122 *(rp++) = sram_ch->dma_ctl;
123 // Check if we need to enable the FIFO after the first 3 lines 123 *(rp++) = sram_ch->fld_aud_fifo_en;
124 // For the upstream audio channel, the risc engine will enable the FIFO. 124 *(rp++) = 0x00000020;
125 if ( fifo_enable && line == 2 ) 125 }
126 { 126
127 *(rp++) = RISC_WRITECR; 127 offset += AUDIO_LINE_SIZE;
128 *(rp++) = sram_ch->dma_ctl; 128 }
129 *(rp++) = sram_ch->fld_aud_fifo_en; 129
130 *(rp++) = 0x00000020; 130 return rp;
131 } 131}
132 132
133 offset += AUDIO_LINE_SIZE; 133int cx25821_risc_buffer_upstream_audio(struct cx25821_dev *dev,
134 } 134 struct pci_dev *pci,
135 135 unsigned int bpl, unsigned int lines)
136 return rp; 136{
137} 137 __le32 *rp;
138 138 int fifo_enable = 0;
139int cx25821_risc_buffer_upstream_audio( struct cx25821_dev *dev, 139 int frame = 0, i = 0;
140 struct pci_dev *pci, 140 int frame_size = AUDIO_DATA_BUF_SZ;
141 unsigned int bpl, unsigned int lines) 141 int databuf_offset = 0;
142{ 142 int risc_flag = RISC_CNT_INC;
143 __le32 *rp; 143 dma_addr_t risc_phys_jump_addr;
144 int fifo_enable = 0; 144
145 int frame = 0, i = 0; 145 /* Virtual address of Risc buffer program */
146 int frame_size = AUDIO_DATA_BUF_SZ; 146 rp = dev->_risc_virt_addr;
147 int databuf_offset = 0; 147
148 int risc_flag = RISC_CNT_INC; 148 /* sync instruction */
149 dma_addr_t risc_phys_jump_addr; 149 *(rp++) = cpu_to_le32(RISC_RESYNC | AUDIO_SYNC_LINE);
150 150
151 151 for (frame = 0; frame < NUM_AUDIO_FRAMES; frame++) {
152 /* Virtual address of Risc buffer program */ 152 databuf_offset = frame_size * frame;
153 rp = dev->_risc_virt_addr; 153
154 154 if (frame == 0) {
155 /* sync instruction */ 155 fifo_enable = 1;
156 *(rp++) = cpu_to_le32(RISC_RESYNC | AUDIO_SYNC_LINE); 156 risc_flag = RISC_CNT_RESET;
157 157 } else {
158 158 fifo_enable = 0;
159 for( frame = 0; frame < NUM_AUDIO_FRAMES; frame++ ) 159 risc_flag = RISC_CNT_INC;
160 { 160 }
161 databuf_offset = frame_size * frame; 161
162 162 //Calculate physical jump address
163 if( frame == 0 ) 163 if ((frame + 1) == NUM_AUDIO_FRAMES) {
164 { 164 risc_phys_jump_addr =
165 fifo_enable = 1; 165 dev->_risc_phys_start_addr +
166 risc_flag = RISC_CNT_RESET; 166 RISC_SYNC_INSTRUCTION_SIZE;
167 } 167 } else {
168 else 168 risc_phys_jump_addr =
169 { 169 dev->_risc_phys_start_addr +
170 fifo_enable = 0; 170 RISC_SYNC_INSTRUCTION_SIZE +
171 risc_flag = RISC_CNT_INC; 171 AUDIO_RISC_DMA_BUF_SIZE * (frame + 1);
172 } 172 }
173 173
174 //Calculate physical jump address 174 rp = cx25821_risc_field_upstream_audio(dev, rp,
175 if( (frame+1) == NUM_AUDIO_FRAMES ) 175 dev->
176 { 176 _audiodata_buf_phys_addr
177 risc_phys_jump_addr = dev->_risc_phys_start_addr + RISC_SYNC_INSTRUCTION_SIZE; 177 + databuf_offset, bpl,
178 } 178 fifo_enable);
179 else 179
180 { 180 if (USE_RISC_NOOP_AUDIO) {
181 risc_phys_jump_addr = dev->_risc_phys_start_addr + RISC_SYNC_INSTRUCTION_SIZE + AUDIO_RISC_DMA_BUF_SIZE*(frame+1); 181 for (i = 0; i < NUM_NO_OPS; i++) {
182 } 182 *(rp++) = cpu_to_le32(RISC_NOOP);
183 183 }
184 rp = cx25821_risc_field_upstream_audio(dev, rp, dev->_audiodata_buf_phys_addr+databuf_offset, bpl, fifo_enable); 184 }
185 185
186 186 // Loop to (Nth)FrameRISC or to Start of Risc program & generate IRQ
187 if( USE_RISC_NOOP_AUDIO ) 187 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
188 { 188 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
189 for( i = 0; i < NUM_NO_OPS; i++ ) 189 *(rp++) = cpu_to_le32(0);
190 { 190
191 *(rp++) = cpu_to_le32(RISC_NOOP); 191 //Recalculate virtual address based on frame index
192 } 192 rp = dev->_risc_virt_addr + RISC_SYNC_INSTRUCTION_SIZE / 4 +
193 } 193 (AUDIO_RISC_DMA_BUF_SIZE * (frame + 1) / 4);
194 194 }
195 195
196 // Loop to (Nth)FrameRISC or to Start of Risc program & generate IRQ 196 return 0;
197 *(rp++) = cpu_to_le32(RISC_JUMP|RISC_IRQ1|risc_flag); 197}
198 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 198
199 *(rp++) = cpu_to_le32(0); 199void cx25821_free_memory_audio(struct cx25821_dev *dev)
200 200{
201 //Recalculate virtual address based on frame index 201 if (dev->_risc_virt_addr) {
202 rp = dev->_risc_virt_addr + RISC_SYNC_INSTRUCTION_SIZE/4 + (AUDIO_RISC_DMA_BUF_SIZE*(frame+1)/4 ) ; 202 pci_free_consistent(dev->pci, dev->_audiorisc_size,
203 } 203 dev->_risc_virt_addr, dev->_risc_phys_addr);
204 204 dev->_risc_virt_addr = NULL;
205 return 0; 205 }
206} 206
207 207 if (dev->_audiodata_buf_virt_addr) {
208 208 pci_free_consistent(dev->pci, dev->_audiodata_buf_size,
209void cx25821_free_memory_audio(struct cx25821_dev *dev) 209 dev->_audiodata_buf_virt_addr,
210{ 210 dev->_audiodata_buf_phys_addr);
211 if (dev->_risc_virt_addr) 211 dev->_audiodata_buf_virt_addr = NULL;
212 { 212 }
213 pci_free_consistent(dev->pci, dev->_audiorisc_size, dev->_risc_virt_addr, dev->_risc_phys_addr); 213}
214 dev->_risc_virt_addr = NULL; 214
215 } 215void cx25821_stop_upstream_audio(struct cx25821_dev *dev)
216 216{
217 if (dev->_audiodata_buf_virt_addr) 217 struct sram_channel *sram_ch =
218 { 218 &dev->sram_channels[AUDIO_UPSTREAM_SRAM_CHANNEL_B];
219 pci_free_consistent(dev->pci, dev->_audiodata_buf_size, dev->_audiodata_buf_virt_addr, dev->_audiodata_buf_phys_addr); 219 u32 tmp = 0;
220 dev->_audiodata_buf_virt_addr = NULL; 220
221 } 221 if (!dev->_audio_is_running) {
222} 222 printk
223 223 ("cx25821: No audio file is currently running so return!\n");
224void cx25821_stop_upstream_audio(struct cx25821_dev *dev) 224 return;
225{ 225 }
226 struct sram_channel *sram_ch = &dev->sram_channels[AUDIO_UPSTREAM_SRAM_CHANNEL_B]; 226 //Disable RISC interrupts
227 u32 tmp = 0; 227 cx_write(sram_ch->int_msk, 0);
228 228
229 if( !dev->_audio_is_running ) 229 //Turn OFF risc and fifo enable in AUD_DMA_CNTRL
230 { 230 tmp = cx_read(sram_ch->dma_ctl);
231 printk("cx25821: No audio file is currently running so return!\n"); 231 cx_write(sram_ch->dma_ctl,
232 return; 232 tmp & ~(sram_ch->fld_aud_fifo_en | sram_ch->fld_aud_risc_en));
233 } 233
234 234 //Clear data buffer memory
235 //Disable RISC interrupts 235 if (dev->_audiodata_buf_virt_addr)
236 cx_write( sram_ch->int_msk, 0 ); 236 memset(dev->_audiodata_buf_virt_addr, 0,
237 237 dev->_audiodata_buf_size);
238 //Turn OFF risc and fifo enable in AUD_DMA_CNTRL 238
239 tmp = cx_read( sram_ch->dma_ctl ); 239 dev->_audio_is_running = 0;
240 cx_write( sram_ch->dma_ctl, tmp & ~(sram_ch->fld_aud_fifo_en | sram_ch->fld_aud_risc_en) ); 240 dev->_is_first_audio_frame = 0;
241 241 dev->_audioframe_count = 0;
242 //Clear data buffer memory 242 dev->_audiofile_status = END_OF_FILE;
243 if( dev->_audiodata_buf_virt_addr ) 243
244 memset( dev->_audiodata_buf_virt_addr, 0, dev->_audiodata_buf_size ); 244 if (dev->_irq_audio_queues) {
245 245 kfree(dev->_irq_audio_queues);
246 dev->_audio_is_running = 0; 246 dev->_irq_audio_queues = NULL;
247 dev->_is_first_audio_frame = 0; 247 }
248 dev->_audioframe_count = 0; 248
249 dev->_audiofile_status = END_OF_FILE; 249 if (dev->_audiofilename != NULL)
250 250 kfree(dev->_audiofilename);
251 if( dev->_irq_audio_queues ) 251}
252 { 252
253 kfree(dev->_irq_audio_queues); 253void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev)
254 dev->_irq_audio_queues = NULL; 254{
255 } 255 if (dev->_audio_is_running) {
256 256 cx25821_stop_upstream_audio(dev);
257 if( dev->_audiofilename != NULL ) 257 }
258 kfree(dev->_audiofilename); 258
259} 259 cx25821_free_memory_audio(dev);
260 260}
261 261
262void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev) 262int cx25821_get_audio_data(struct cx25821_dev *dev,
263{ 263 struct sram_channel *sram_ch)
264 if( dev->_audio_is_running ) 264{
265 { 265 struct file *myfile;
266 cx25821_stop_upstream_audio(dev); 266 int frame_index_temp = dev->_audioframe_index;
267 } 267 int i = 0;
268 268 int line_size = AUDIO_LINE_SIZE;
269 cx25821_free_memory_audio(dev); 269 int frame_size = AUDIO_DATA_BUF_SZ;
270} 270 int frame_offset = frame_size * frame_index_temp;
271 271 ssize_t vfs_read_retval = 0;
272 272 char mybuf[line_size];
273int cx25821_get_audio_data(struct cx25821_dev *dev, struct sram_channel *sram_ch ) 273 loff_t file_offset = dev->_audioframe_count * frame_size;
274{ 274 loff_t pos;
275 struct file * myfile; 275 mm_segment_t old_fs;
276 int frame_index_temp = dev->_audioframe_index; 276
277 int i = 0; 277 if (dev->_audiofile_status == END_OF_FILE)
278 int line_size = AUDIO_LINE_SIZE; 278 return 0;
279 int frame_size = AUDIO_DATA_BUF_SZ; 279
280 int frame_offset = frame_size * frame_index_temp; 280 myfile = filp_open(dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0);
281 ssize_t vfs_read_retval = 0; 281
282 char mybuf[line_size]; 282 if (IS_ERR(myfile)) {
283 loff_t file_offset = dev->_audioframe_count * frame_size; 283 const int open_errno = -PTR_ERR(myfile);
284 loff_t pos; 284 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
285 mm_segment_t old_fs; 285 __func__, dev->_audiofilename, open_errno);
286 286 return PTR_ERR(myfile);
287 287 } else {
288 if( dev->_audiofile_status == END_OF_FILE ) 288 if (!(myfile->f_op)) {
289 return 0; 289 printk("%s: File has no file operations registered!\n",
290 290 __func__);
291 myfile = filp_open( dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0 ); 291 filp_close(myfile, NULL);
292 292 return -EIO;
293 293 }
294 if (IS_ERR(myfile)) 294
295 { 295 if (!myfile->f_op->read) {
296 const int open_errno = -PTR_ERR(myfile); 296 printk("%s: File has no READ operations registered! \n",
297 printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_audiofilename, open_errno); 297 __func__);
298 return PTR_ERR(myfile); 298 filp_close(myfile, NULL);
299 } 299 return -EIO;
300 else 300 }
301 { 301
302 if( !(myfile->f_op) ) 302 pos = myfile->f_pos;
303 { 303 old_fs = get_fs();
304 printk("%s: File has no file operations registered!\n", __func__); 304 set_fs(KERNEL_DS);
305 filp_close(myfile, NULL); 305
306 return -EIO; 306 for (i = 0; i < dev->_audio_lines_count; i++) {
307 } 307 pos = file_offset;
308 308
309 309 vfs_read_retval =
310 if( !myfile->f_op->read ) 310 vfs_read(myfile, mybuf, line_size, &pos);
311 { 311
312 printk("%s: File has no READ operations registered! \n", __func__); 312 if (vfs_read_retval > 0 && vfs_read_retval == line_size
313 filp_close(myfile, NULL); 313 && dev->_audiodata_buf_virt_addr != NULL) {
314 return -EIO; 314 memcpy((void *)(dev->_audiodata_buf_virt_addr +
315 } 315 frame_offset / 4), mybuf,
316 316 vfs_read_retval);
317 pos = myfile->f_pos; 317 }
318 old_fs = get_fs(); 318
319 set_fs(KERNEL_DS); 319 file_offset += vfs_read_retval;
320 320 frame_offset += vfs_read_retval;
321 321
322 for( i = 0; i < dev->_audio_lines_count; i++ ) 322 if (vfs_read_retval < line_size) {
323 { 323 printk(KERN_INFO
324 pos = file_offset; 324 "Done: exit %s() since no more bytes to read from Audio file.\n",
325 325 __func__);
326 vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos); 326 break;
327 327 }
328 328 }
329 if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_audiodata_buf_virt_addr != NULL ) 329
330 { 330 if (i > 0)
331 memcpy( (void*)(dev->_audiodata_buf_virt_addr+frame_offset/4), mybuf, vfs_read_retval); 331 dev->_audioframe_count++;
332 } 332
333 333 dev->_audiofile_status =
334 file_offset += vfs_read_retval; 334 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
335 frame_offset += vfs_read_retval; 335
336 336 set_fs(old_fs);
337 if( vfs_read_retval < line_size ) 337 filp_close(myfile, NULL);
338 { 338 }
339 printk(KERN_INFO "Done: exit %s() since no more bytes to read from Audio file.\n", __func__ ); 339
340 break; 340 return 0;
341 } 341}
342 } 342
343 343static void cx25821_audioups_handler(struct work_struct *work)
344 if( i > 0 ) 344{
345 dev->_audioframe_count++; 345 struct cx25821_dev *dev =
346 346 container_of(work, struct cx25821_dev, _audio_work_entry);
347 dev->_audiofile_status = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 347
348 348 if (!dev) {
349 349 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
350 set_fs(old_fs); 350 __func__);
351 filp_close(myfile, NULL); 351 return;
352 } 352 }
353 353
354 return 0; 354 cx25821_get_audio_data(dev,
355} 355 &dev->sram_channels[dev->
356 356 _audio_upstream_channel_select]);
357static void cx25821_audioups_handler(struct work_struct *work) 357}
358{ 358
359 struct cx25821_dev *dev = container_of(work, struct cx25821_dev, _audio_work_entry); 359int cx25821_openfile_audio(struct cx25821_dev *dev,
360 360 struct sram_channel *sram_ch)
361 if( !dev ) 361{
362 { 362 struct file *myfile;
363 printk("ERROR %s(): since container_of(work_struct) FAILED! \n", __func__ ); 363 int i = 0, j = 0;
364 return; 364 int line_size = AUDIO_LINE_SIZE;
365 } 365 ssize_t vfs_read_retval = 0;
366 366 char mybuf[line_size];
367 cx25821_get_audio_data( dev, &dev->sram_channels[dev->_audio_upstream_channel_select] ); 367 loff_t pos;
368} 368 loff_t offset = (unsigned long)0;
369 369 mm_segment_t old_fs;
370int cx25821_openfile_audio(struct cx25821_dev *dev, struct sram_channel *sram_ch) 370
371{ 371 myfile = filp_open(dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0);
372 struct file * myfile; 372
373 int i = 0, j = 0; 373 if (IS_ERR(myfile)) {
374 int line_size = AUDIO_LINE_SIZE; 374 const int open_errno = -PTR_ERR(myfile);
375 ssize_t vfs_read_retval = 0; 375 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
376 char mybuf[line_size]; 376 __func__, dev->_audiofilename, open_errno);
377 loff_t pos; 377 return PTR_ERR(myfile);
378 loff_t offset = (unsigned long)0; 378 } else {
379 mm_segment_t old_fs; 379 if (!(myfile->f_op)) {
380 380 printk("%s: File has no file operations registered! \n",
381 381 __func__);
382 myfile = filp_open( dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0 ); 382 filp_close(myfile, NULL);
383 383 return -EIO;
384 384 }
385 if (IS_ERR(myfile)) 385
386 { 386 if (!myfile->f_op->read) {
387 const int open_errno = -PTR_ERR(myfile); 387 printk("%s: File has no READ operations registered! \n",
388 printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_audiofilename, open_errno); 388 __func__);
389 return PTR_ERR(myfile); 389 filp_close(myfile, NULL);
390 } 390 return -EIO;
391 else 391 }
392 { 392
393 if( !(myfile->f_op) ) 393 pos = myfile->f_pos;
394 { 394 old_fs = get_fs();
395 printk("%s: File has no file operations registered! \n", __func__); 395 set_fs(KERNEL_DS);
396 filp_close(myfile, NULL); 396
397 return -EIO; 397 for (j = 0; j < NUM_AUDIO_FRAMES; j++) {
398 } 398 for (i = 0; i < dev->_audio_lines_count; i++) {
399 399 pos = offset;
400 400
401 if( !myfile->f_op->read ) 401 vfs_read_retval =
402 { 402 vfs_read(myfile, mybuf, line_size, &pos);
403 printk("%s: File has no READ operations registered! \n", __func__); 403
404 filp_close(myfile, NULL); 404 if (vfs_read_retval > 0
405 return -EIO; 405 && vfs_read_retval == line_size
406 } 406 && dev->_audiodata_buf_virt_addr != NULL) {
407 407 memcpy((void *)(dev->
408 pos = myfile->f_pos; 408 _audiodata_buf_virt_addr
409 old_fs = get_fs(); 409 + offset / 4), mybuf,
410 set_fs(KERNEL_DS); 410 vfs_read_retval);
411 411 }
412 412
413 for( j = 0; j < NUM_AUDIO_FRAMES; j++ ) 413 offset += vfs_read_retval;
414 { 414
415 for( i = 0; i < dev->_audio_lines_count; i++ ) 415 if (vfs_read_retval < line_size) {
416 { 416 printk(KERN_INFO
417 pos = offset; 417 "Done: exit %s() since no more bytes to read from Audio file.\n",
418 418 __func__);
419 vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos); 419 break;
420 420 }
421 421 }
422 if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_audiodata_buf_virt_addr != NULL ) 422
423 { 423 if (i > 0) {
424 memcpy( (void*)(dev->_audiodata_buf_virt_addr+offset/4), mybuf, vfs_read_retval); 424 dev->_audioframe_count++;
425 } 425 }
426 426
427 offset += vfs_read_retval; 427 if (vfs_read_retval < line_size) {
428 428 break;
429 if( vfs_read_retval < line_size ) 429 }
430 { 430 }
431 printk(KERN_INFO "Done: exit %s() since no more bytes to read from Audio file.\n", __func__ ); 431
432 break; 432 dev->_audiofile_status =
433 } 433 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
434 } 434
435 435 set_fs(old_fs);
436 if( i > 0 ) 436 myfile->f_pos = 0;
437 { 437 filp_close(myfile, NULL);
438 dev->_audioframe_count++; 438 }
439 } 439
440 440 return 0;
441 if( vfs_read_retval < line_size ) 441}
442 { 442
443 break; 443static int cx25821_audio_upstream_buffer_prepare(struct cx25821_dev *dev,
444 } 444 struct sram_channel *sram_ch,
445 } 445 int bpl)
446 446{
447 dev->_audiofile_status = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 447 int ret = 0;
448 448 dma_addr_t dma_addr;
449 set_fs(old_fs); 449 dma_addr_t data_dma_addr;
450 myfile->f_pos = 0; 450
451 filp_close(myfile, NULL); 451 cx25821_free_memory_audio(dev);
452 } 452
453 453 dev->_risc_virt_addr =
454 return 0; 454 pci_alloc_consistent(dev->pci, dev->audio_upstream_riscbuf_size,
455} 455 &dma_addr);
456 456 dev->_risc_virt_start_addr = dev->_risc_virt_addr;
457static int cx25821_audio_upstream_buffer_prepare(struct cx25821_dev *dev, 457 dev->_risc_phys_start_addr = dma_addr;
458 struct sram_channel *sram_ch, 458 dev->_risc_phys_addr = dma_addr;
459 int bpl) 459 dev->_audiorisc_size = dev->audio_upstream_riscbuf_size;
460{ 460
461 int ret = 0; 461 if (!dev->_risc_virt_addr) {
462 dma_addr_t dma_addr; 462 printk
463 dma_addr_t data_dma_addr; 463 ("cx25821 ERROR: pci_alloc_consistent() FAILED to allocate memory for RISC program! Returning.\n");
464 464 return -ENOMEM;
465 465 }
466 cx25821_free_memory_audio(dev); 466 //Clear out memory at address
467 467 memset(dev->_risc_virt_addr, 0, dev->_audiorisc_size);
468 dev->_risc_virt_addr = pci_alloc_consistent(dev->pci, dev->audio_upstream_riscbuf_size, &dma_addr); 468
469 dev->_risc_virt_start_addr = dev->_risc_virt_addr; 469 //For Audio Data buffer allocation
470 dev->_risc_phys_start_addr = dma_addr; 470 dev->_audiodata_buf_virt_addr =
471 dev->_risc_phys_addr = dma_addr; 471 pci_alloc_consistent(dev->pci, dev->audio_upstream_databuf_size,
472 dev->_audiorisc_size = dev->audio_upstream_riscbuf_size; 472 &data_dma_addr);
473 473 dev->_audiodata_buf_phys_addr = data_dma_addr;
474 474 dev->_audiodata_buf_size = dev->audio_upstream_databuf_size;
475 if (!dev->_risc_virt_addr) 475
476 { 476 if (!dev->_audiodata_buf_virt_addr) {
477 printk("cx25821 ERROR: pci_alloc_consistent() FAILED to allocate memory for RISC program! Returning.\n"); 477 printk
478 return -ENOMEM; 478 ("cx25821 ERROR: pci_alloc_consistent() FAILED to allocate memory for data buffer! Returning. \n");
479 } 479 return -ENOMEM;
480 480 }
481 //Clear out memory at address 481 //Clear out memory at address
482 memset( dev->_risc_virt_addr, 0, dev->_audiorisc_size ); 482 memset(dev->_audiodata_buf_virt_addr, 0, dev->_audiodata_buf_size);
483 483
484 484 ret = cx25821_openfile_audio(dev, sram_ch);
485 //For Audio Data buffer allocation 485 if (ret < 0)
486 dev->_audiodata_buf_virt_addr = pci_alloc_consistent(dev->pci, dev->audio_upstream_databuf_size, &data_dma_addr); 486 return ret;
487 dev->_audiodata_buf_phys_addr = data_dma_addr; 487
488 dev->_audiodata_buf_size = dev->audio_upstream_databuf_size; 488 //Creating RISC programs
489 489 ret =
490 if (!dev->_audiodata_buf_virt_addr) 490 cx25821_risc_buffer_upstream_audio(dev, dev->pci, bpl,
491 { 491 dev->_audio_lines_count);
492 printk("cx25821 ERROR: pci_alloc_consistent() FAILED to allocate memory for data buffer! Returning. \n"); 492 if (ret < 0) {
493 return -ENOMEM; 493 printk(KERN_DEBUG
494 } 494 "cx25821 ERROR creating audio upstream RISC programs! \n");
495 495 goto error;
496 //Clear out memory at address 496 }
497 memset( dev->_audiodata_buf_virt_addr, 0, dev->_audiodata_buf_size ); 497
498 498 return 0;
499 499
500 ret = cx25821_openfile_audio(dev, sram_ch); 500 error:
501 if( ret < 0 ) 501 return ret;
502 return ret; 502}
503 503
504 504int cx25821_audio_upstream_irq(struct cx25821_dev *dev, int chan_num,
505 //Creating RISC programs 505 u32 status)
506 ret = cx25821_risc_buffer_upstream_audio(dev, dev->pci, bpl, dev->_audio_lines_count ); 506{
507 if (ret < 0) 507 int i = 0;
508 { 508 u32 int_msk_tmp;
509 printk(KERN_DEBUG "cx25821 ERROR creating audio upstream RISC programs! \n"); 509 struct sram_channel *channel = &dev->sram_channels[chan_num];
510 goto error; 510 dma_addr_t risc_phys_jump_addr;
511 } 511 __le32 *rp;
512 512
513 return 0; 513 if (status & FLD_AUD_SRC_RISCI1) {
514 514 //Get interrupt_index of the program that interrupted
515error: 515 u32 prog_cnt = cx_read(channel->gpcnt);
516 return ret; 516
517} 517 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
518 518 cx_write(channel->int_msk, 0);
519int cx25821_audio_upstream_irq(struct cx25821_dev *dev, int chan_num, u32 status) 519 cx_write(channel->int_stat, cx_read(channel->int_stat));
520{ 520
521 int i = 0; 521 spin_lock(&dev->slock);
522 u32 int_msk_tmp; 522
523 struct sram_channel *channel = &dev->sram_channels[chan_num]; 523 while (prog_cnt != dev->_last_index_irq) {
524 dma_addr_t risc_phys_jump_addr; 524 //Update _last_index_irq
525 __le32 * rp; 525 if (dev->_last_index_irq < (NUMBER_OF_PROGRAMS - 1)) {
526 526 dev->_last_index_irq++;
527 527 } else {
528 if (status & FLD_AUD_SRC_RISCI1) 528 dev->_last_index_irq = 0;
529 { 529 }
530 //Get interrupt_index of the program that interrupted 530
531 u32 prog_cnt = cx_read( channel->gpcnt ); 531 dev->_audioframe_index = dev->_last_index_irq;
532 532
533 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers 533 queue_work(dev->_irq_audio_queues,
534 cx_write(channel->int_msk, 0); 534 &dev->_audio_work_entry);
535 cx_write(channel->int_stat, cx_read(channel->int_stat) ); 535 }
536 536
537 spin_lock(&dev->slock); 537 if (dev->_is_first_audio_frame) {
538 538 dev->_is_first_audio_frame = 0;
539 539
540 while(prog_cnt != dev->_last_index_irq) 540 if (dev->_risc_virt_start_addr != NULL) {
541 { 541 risc_phys_jump_addr =
542 //Update _last_index_irq 542 dev->_risc_phys_start_addr +
543 if(dev->_last_index_irq < (NUMBER_OF_PROGRAMS-1)) 543 RISC_SYNC_INSTRUCTION_SIZE +
544 { 544 AUDIO_RISC_DMA_BUF_SIZE;
545 dev->_last_index_irq++; 545
546 } 546 rp = cx25821_risc_field_upstream_audio(dev,
547 else 547 dev->
548 { 548 _risc_virt_start_addr
549 dev->_last_index_irq = 0; 549 + 1,
550 } 550 dev->
551 551 _audiodata_buf_phys_addr,
552 dev->_audioframe_index = dev->_last_index_irq; 552 AUDIO_LINE_SIZE,
553 553 FIFO_DISABLE);
554 queue_work(dev->_irq_audio_queues, &dev->_audio_work_entry); 554
555 } 555 if (USE_RISC_NOOP_AUDIO) {
556 556 for (i = 0; i < NUM_NO_OPS; i++) {
557 557 *(rp++) =
558 if ( dev->_is_first_audio_frame ) 558 cpu_to_le32(RISC_NOOP);
559 { 559 }
560 dev->_is_first_audio_frame = 0; 560 }
561 561 // Jump to 2nd Audio Frame
562 if( dev->_risc_virt_start_addr != NULL ) 562 *(rp++) =
563 { 563 cpu_to_le32(RISC_JUMP | RISC_IRQ1 |
564 risc_phys_jump_addr = dev->_risc_phys_start_addr + RISC_SYNC_INSTRUCTION_SIZE + AUDIO_RISC_DMA_BUF_SIZE; 564 RISC_CNT_RESET);
565 565 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
566 rp = cx25821_risc_field_upstream_audio(dev, dev->_risc_virt_start_addr+1, dev->_audiodata_buf_phys_addr, AUDIO_LINE_SIZE, FIFO_DISABLE); 566 *(rp++) = cpu_to_le32(0);
567 567 }
568 if( USE_RISC_NOOP_AUDIO ) 568 }
569 { 569
570 for( i = 0; i < NUM_NO_OPS; i++ ) 570 spin_unlock(&dev->slock);
571 { 571 } else {
572 *(rp++) = cpu_to_le32(RISC_NOOP); 572 if (status & FLD_AUD_SRC_OF)
573 } 573 printk("%s: Audio Received Overflow Error Interrupt!\n",
574 } 574 __func__);
575 575
576 // Jump to 2nd Audio Frame 576 if (status & FLD_AUD_SRC_SYNC)
577 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_RESET); 577 printk("%s: Audio Received Sync Error Interrupt!\n",
578 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 578 __func__);
579 *(rp++) = cpu_to_le32(0); 579
580 } 580 if (status & FLD_AUD_SRC_OPC_ERR)
581 } 581 printk("%s: Audio Received OpCode Error Interrupt!\n",
582 582 __func__);
583 spin_unlock(&dev->slock); 583
584 } 584 // Read and write back the interrupt status register to clear our bits
585 else 585 cx_write(channel->int_stat, cx_read(channel->int_stat));
586 { 586 }
587 if(status & FLD_AUD_SRC_OF) 587
588 printk("%s: Audio Received Overflow Error Interrupt!\n", __func__); 588 if (dev->_audiofile_status == END_OF_FILE) {
589 589 printk("cx25821: EOF Channel Audio Framecount = %d\n",
590 if(status & FLD_AUD_SRC_SYNC) 590 dev->_audioframe_count);
591 printk("%s: Audio Received Sync Error Interrupt!\n", __func__); 591 return -1;
592 592 }
593 if(status & FLD_AUD_SRC_OPC_ERR) 593 //ElSE, set the interrupt mask register, re-enable irq.
594 printk("%s: Audio Received OpCode Error Interrupt!\n", __func__); 594 int_msk_tmp = cx_read(channel->int_msk);
595 595 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
596 // Read and write back the interrupt status register to clear our bits 596
597 cx_write(channel->int_stat, cx_read(channel->int_stat) ); 597 return 0;
598 } 598}
599 599
600 600static irqreturn_t cx25821_upstream_irq_audio(int irq, void *dev_id)
601 if( dev->_audiofile_status == END_OF_FILE ) 601{
602 { 602 struct cx25821_dev *dev = dev_id;
603 printk("cx25821: EOF Channel Audio Framecount = %d\n", dev->_audioframe_count ); 603 u32 msk_stat, audio_status;
604 return -1; 604 int handled = 0;
605 } 605 struct sram_channel *sram_ch;
606 606
607 //ElSE, set the interrupt mask register, re-enable irq. 607 if (!dev)
608 int_msk_tmp = cx_read( channel->int_msk ); 608 return -1;
609 cx_write( channel->int_msk, int_msk_tmp |= _intr_msk ); 609
610 610 sram_ch = &dev->sram_channels[dev->_audio_upstream_channel_select];
611 return 0; 611
612} 612 msk_stat = cx_read(sram_ch->int_mstat);
613 613 audio_status = cx_read(sram_ch->int_stat);
614static irqreturn_t cx25821_upstream_irq_audio(int irq, void *dev_id) 614
615{ 615 // Only deal with our interrupt
616 struct cx25821_dev *dev = dev_id; 616 if (audio_status) {
617 u32 msk_stat, audio_status; 617 handled =
618 int handled = 0; 618 cx25821_audio_upstream_irq(dev,
619 struct sram_channel *sram_ch; 619 dev->
620 620 _audio_upstream_channel_select,
621 621 audio_status);
622 if( !dev ) 622 }
623 return -1; 623
624 624 if (handled < 0) {
625 625 cx25821_stop_upstream_audio(dev);
626 sram_ch = &dev->sram_channels[dev->_audio_upstream_channel_select]; 626 } else {
627 627 handled += handled;
628 msk_stat = cx_read(sram_ch->int_mstat); 628 }
629 audio_status = cx_read(sram_ch->int_stat); 629
630 630 return IRQ_RETVAL(handled);
631 // Only deal with our interrupt 631}
632 if(audio_status) 632
633 { 633static void cx25821_wait_fifo_enable(struct cx25821_dev *dev,
634 handled = cx25821_audio_upstream_irq(dev, dev->_audio_upstream_channel_select, audio_status); 634 struct sram_channel *sram_ch)
635 } 635{
636 636 int count = 0;
637 637 u32 tmp;
638 if( handled < 0 ) 638
639 { 639 do {
640 cx25821_stop_upstream_audio(dev); 640 //Wait 10 microsecond before checking to see if the FIFO is turned ON.
641 } 641 udelay(10);
642 else 642
643 { 643 tmp = cx_read(sram_ch->dma_ctl);
644 handled += handled; 644
645 } 645 if (count++ > 1000) //10 millisecond timeout
646 646 {
647 return IRQ_RETVAL(handled); 647 printk
648} 648 ("cx25821 ERROR: %s() fifo is NOT turned on. Timeout!\n",
649 649 __func__);
650 650 return;
651static void cx25821_wait_fifo_enable(struct cx25821_dev *dev, struct sram_channel *sram_ch) 651 }
652{ 652
653 int count = 0; 653 } while (!(tmp & sram_ch->fld_aud_fifo_en));
654 u32 tmp; 654
655 655}
656 do 656
657 { 657int cx25821_start_audio_dma_upstream(struct cx25821_dev *dev,
658 //Wait 10 microsecond before checking to see if the FIFO is turned ON. 658 struct sram_channel *sram_ch)
659 udelay(10); 659{
660 660 u32 tmp = 0;
661 tmp = cx_read( sram_ch->dma_ctl ); 661 int err = 0;
662 662
663 if(count++ > 1000) //10 millisecond timeout 663 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the CMDS.
664 { 664 cx_write(sram_ch->cmds_start + 0, dev->_risc_phys_addr);
665 printk("cx25821 ERROR: %s() fifo is NOT turned on. Timeout!\n", __func__); 665 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
666 return; 666
667 } 667 /* reset counter */
668 668 cx_write(sram_ch->gpcnt_ctl, 3);
669 } while( !(tmp & sram_ch->fld_aud_fifo_en) ); 669
670 670 //Set the line length (It looks like we do not need to set the line length)
671} 671 cx_write(sram_ch->aud_length, AUDIO_LINE_SIZE & FLD_AUD_DST_LN_LNGTH);
672 672
673 673 //Set the input mode to 16-bit
674int cx25821_start_audio_dma_upstream(struct cx25821_dev *dev, 674 tmp = cx_read(sram_ch->aud_cfg);
675 struct sram_channel *sram_ch) 675 tmp |=
676{ 676 FLD_AUD_SRC_ENABLE | FLD_AUD_DST_PK_MODE | FLD_AUD_CLK_ENABLE |
677 u32 tmp = 0; 677 FLD_AUD_MASTER_MODE | FLD_AUD_CLK_SELECT_PLL_D | FLD_AUD_SONY_MODE;
678 int err = 0; 678 cx_write(sram_ch->aud_cfg, tmp);
679 679
680 680 // Read and write back the interrupt status register to clear it
681 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the CMDS. 681 tmp = cx_read(sram_ch->int_stat);
682 cx_write(sram_ch->cmds_start + 0, dev->_risc_phys_addr); 682 cx_write(sram_ch->int_stat, tmp);
683 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ 683
684 684 // Clear our bits from the interrupt status register.
685 685 cx_write(sram_ch->int_stat, _intr_msk);
686 /* reset counter */ 686
687 cx_write(sram_ch->gpcnt_ctl, 3); 687 //Set the interrupt mask register, enable irq.
688 688 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
689 //Set the line length (It looks like we do not need to set the line length) 689 tmp = cx_read(sram_ch->int_msk);
690 cx_write(sram_ch->aud_length, AUDIO_LINE_SIZE & FLD_AUD_DST_LN_LNGTH); 690 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
691 691
692 //Set the input mode to 16-bit 692 err =
693 tmp = cx_read( sram_ch->aud_cfg ); 693 request_irq(dev->pci->irq, cx25821_upstream_irq_audio,
694 tmp |= FLD_AUD_SRC_ENABLE | FLD_AUD_DST_PK_MODE | FLD_AUD_CLK_ENABLE | FLD_AUD_MASTER_MODE | FLD_AUD_CLK_SELECT_PLL_D | FLD_AUD_SONY_MODE; 694 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
695 cx_write( sram_ch->aud_cfg, tmp ); 695 if (err < 0) {
696 696 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
697 // Read and write back the interrupt status register to clear it 697 dev->pci->irq);
698 tmp = cx_read( sram_ch->int_stat); 698 goto fail_irq;
699 cx_write( sram_ch->int_stat, tmp); 699 }
700 700
701 // Clear our bits from the interrupt status register. 701 // Start the DMA engine
702 cx_write( sram_ch->int_stat, _intr_msk ); 702 tmp = cx_read(sram_ch->dma_ctl);
703 703 cx_set(sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en);
704 704
705 //Set the interrupt mask register, enable irq. 705 dev->_audio_is_running = 1;
706 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); 706 dev->_is_first_audio_frame = 1;
707 tmp = cx_read( sram_ch->int_msk ); 707
708 cx_write( sram_ch->int_msk, tmp |= _intr_msk ); 708 // The fifo_en bit turns on by the first Risc program
709 709 cx25821_wait_fifo_enable(dev, sram_ch);
710 710
711 err = request_irq(dev->pci->irq, cx25821_upstream_irq_audio, IRQF_SHARED | IRQF_DISABLED, dev->name, dev); 711 return 0;
712 if (err < 0) 712
713 { 713 fail_irq:
714 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, dev->pci->irq); 714 cx25821_dev_unregister(dev);
715 goto fail_irq; 715 return err;
716 } 716}
717 717
718 718int cx25821_audio_upstream_init(struct cx25821_dev *dev, int channel_select)
719 // Start the DMA engine 719{
720 tmp = cx_read( sram_ch->dma_ctl ); 720 struct sram_channel *sram_ch;
721 cx_set( sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en ); 721 int retval = 0;
722 722 int err = 0;
723 dev->_audio_is_running = 1; 723 int str_length = 0;
724 dev->_is_first_audio_frame = 1; 724
725 725 if (dev->_audio_is_running) {
726 // The fifo_en bit turns on by the first Risc program 726 printk("Audio Channel is still running so return!\n");
727 cx25821_wait_fifo_enable(dev, sram_ch); 727 return 0;
728 728 }
729 return 0; 729
730 730 dev->_audio_upstream_channel_select = channel_select;
731 731 sram_ch = &dev->sram_channels[channel_select];
732fail_irq: 732
733 cx25821_dev_unregister(dev); 733 //Work queue
734 return err; 734 INIT_WORK(&dev->_audio_work_entry, cx25821_audioups_handler);
735} 735 dev->_irq_audio_queues =
736 736 create_singlethread_workqueue("cx25821_audioworkqueue");
737 737
738int cx25821_audio_upstream_init(struct cx25821_dev *dev, int channel_select) 738 if (!dev->_irq_audio_queues) {
739{ 739 printk
740 struct sram_channel *sram_ch; 740 ("cx25821 ERROR: create_singlethread_workqueue() for Audio FAILED!\n");
741 int retval = 0; 741 return -ENOMEM;
742 int err = 0; 742 }
743 int str_length = 0; 743
744 744 dev->_last_index_irq = 0;
745 if( dev->_audio_is_running ) 745 dev->_audio_is_running = 0;
746 { 746 dev->_audioframe_count = 0;
747 printk("Audio Channel is still running so return!\n"); 747 dev->_audiofile_status = RESET_STATUS;
748 return 0; 748 dev->_audio_lines_count = LINES_PER_AUDIO_BUFFER;
749 } 749 _line_size = AUDIO_LINE_SIZE;
750 750
751 dev->_audio_upstream_channel_select = channel_select; 751 if (dev->input_audiofilename) {
752 sram_ch = &dev->sram_channels[channel_select]; 752 str_length = strlen(dev->input_audiofilename);
753 753 dev->_audiofilename =
754 //Work queue 754 (char *)kmalloc(str_length + 1, GFP_KERNEL);
755 INIT_WORK(&dev->_audio_work_entry, cx25821_audioups_handler); 755
756 dev->_irq_audio_queues = create_singlethread_workqueue("cx25821_audioworkqueue"); 756 if (!dev->_audiofilename)
757 757 goto error;
758 if(!dev->_irq_audio_queues) 758
759 { 759 memcpy(dev->_audiofilename, dev->input_audiofilename,
760 printk("cx25821 ERROR: create_singlethread_workqueue() for Audio FAILED!\n"); 760 str_length + 1);
761 return -ENOMEM; 761
762 } 762 //Default if filename is empty string
763 763 if (strcmp(dev->input_audiofilename, "") == 0) {
764 764 dev->_audiofilename = "/root/audioGOOD.wav";
765 dev->_last_index_irq = 0; 765 }
766 dev->_audio_is_running = 0; 766 } else {
767 dev->_audioframe_count = 0; 767 str_length = strlen(_defaultAudioName);
768 dev->_audiofile_status = RESET_STATUS; 768 dev->_audiofilename =
769 dev->_audio_lines_count = LINES_PER_AUDIO_BUFFER; 769 (char *)kmalloc(str_length + 1, GFP_KERNEL);
770 _line_size = AUDIO_LINE_SIZE; 770
771 771 if (!dev->_audiofilename)
772 772 goto error;
773 if( dev->input_audiofilename ) 773
774 { 774 memcpy(dev->_audiofilename, _defaultAudioName, str_length + 1);
775 str_length = strlen(dev->input_audiofilename); 775 }
776 dev->_audiofilename = (char *) kmalloc(str_length + 1, GFP_KERNEL); 776
777 777 retval =
778 if( !dev->_audiofilename ) 778 cx25821_sram_channel_setup_upstream_audio(dev, sram_ch, _line_size,
779 goto error; 779 0);
780 780
781 memcpy(dev->_audiofilename, dev->input_audiofilename, str_length + 1); 781 dev->audio_upstream_riscbuf_size =
782 782 AUDIO_RISC_DMA_BUF_SIZE * NUM_AUDIO_PROGS +
783 //Default if filename is empty string 783 RISC_SYNC_INSTRUCTION_SIZE;
784 if( strcmp(dev->input_audiofilename,"") == 0) 784 dev->audio_upstream_databuf_size = AUDIO_DATA_BUF_SZ * NUM_AUDIO_PROGS;
785 { 785
786 dev->_audiofilename = "/root/audioGOOD.wav"; 786 //Allocating buffers and prepare RISC program
787 } 787 retval =
788 } 788 cx25821_audio_upstream_buffer_prepare(dev, sram_ch, _line_size);
789 else 789 if (retval < 0) {
790 { 790 printk(KERN_ERR
791 str_length = strlen(_defaultAudioName); 791 "%s: Failed to set up Audio upstream buffers!\n",
792 dev->_audiofilename = (char *) kmalloc(str_length + 1, GFP_KERNEL); 792 dev->name);
793 793 goto error;
794 if( !dev->_audiofilename ) 794 }
795 goto error; 795 //Start RISC engine
796 796 cx25821_start_audio_dma_upstream(dev, sram_ch);
797 memcpy(dev->_audiofilename, _defaultAudioName, str_length + 1); 797
798 } 798 return 0;
799 799
800 800 error:
801 retval = cx25821_sram_channel_setup_upstream_audio(dev, sram_ch, _line_size, 0); 801 cx25821_dev_unregister(dev);
802 802
803 dev->audio_upstream_riscbuf_size = AUDIO_RISC_DMA_BUF_SIZE * NUM_AUDIO_PROGS + RISC_SYNC_INSTRUCTION_SIZE; 803 return err;
804 dev->audio_upstream_databuf_size = AUDIO_DATA_BUF_SZ * NUM_AUDIO_PROGS; 804}
805
806
807 //Allocating buffers and prepare RISC program
808 retval = cx25821_audio_upstream_buffer_prepare(dev, sram_ch, _line_size);
809 if (retval < 0)
810 {
811 printk(KERN_ERR "%s: Failed to set up Audio upstream buffers!\n", dev->name);
812 goto error;
813 }
814
815 //Start RISC engine
816 cx25821_start_audio_dma_upstream(dev, sram_ch);
817
818 return 0;
819
820error:
821 cx25821_dev_unregister(dev);
822
823 return err;
824}
diff --git a/drivers/staging/cx25821/cx25821-audio-upstream.h b/drivers/staging/cx25821/cx25821-audio-upstream.h
index 7bb136b003bb..ca987addf815 100644
--- a/drivers/staging/cx25821/cx25821-audio-upstream.h
+++ b/drivers/staging/cx25821/cx25821-audio-upstream.h
@@ -1,62 +1,57 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/workqueue.h> 24#include <linux/workqueue.h>
25 25
26 26#define NUM_AUDIO_PROGS 8
27#define NUM_AUDIO_PROGS 8 27#define NUM_AUDIO_FRAMES 8
28#define NUM_AUDIO_FRAMES 8 28#define END_OF_FILE 0
29#define END_OF_FILE 0 29#define IN_PROGRESS 1
30#define IN_PROGRESS 1 30#define RESET_STATUS -1
31#define RESET_STATUS -1 31#define FIFO_DISABLE 0
32#define FIFO_DISABLE 0 32#define FIFO_ENABLE 1
33#define FIFO_ENABLE 1 33#define NUM_NO_OPS 4
34#define NUM_NO_OPS 4 34
35 35#define RISC_READ_INSTRUCTION_SIZE 12
36 36#define RISC_JUMP_INSTRUCTION_SIZE 12
37#define RISC_READ_INSTRUCTION_SIZE 12 37#define RISC_WRITECR_INSTRUCTION_SIZE 16
38#define RISC_JUMP_INSTRUCTION_SIZE 12 38#define RISC_SYNC_INSTRUCTION_SIZE 4
39#define RISC_WRITECR_INSTRUCTION_SIZE 16 39#define DWORD_SIZE 4
40#define RISC_SYNC_INSTRUCTION_SIZE 4 40#define AUDIO_SYNC_LINE 4
41#define DWORD_SIZE 4 41
42#define AUDIO_SYNC_LINE 4 42#define LINES_PER_AUDIO_BUFFER 15
43 43#define AUDIO_LINE_SIZE 128
44 44#define AUDIO_DATA_BUF_SZ (AUDIO_LINE_SIZE * LINES_PER_AUDIO_BUFFER)
45#define LINES_PER_AUDIO_BUFFER 15 45
46#define AUDIO_LINE_SIZE 128 46#define USE_RISC_NOOP_AUDIO 1
47#define AUDIO_DATA_BUF_SZ (AUDIO_LINE_SIZE * LINES_PER_AUDIO_BUFFER) 47
48 48#ifdef USE_RISC_NOOP_AUDIO
49#define USE_RISC_NOOP_AUDIO 1 49#define AUDIO_RISC_DMA_BUF_SIZE ( LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE + RISC_JUMP_INSTRUCTION_SIZE)
50 50#endif
51#ifdef USE_RISC_NOOP_AUDIO 51
52#define AUDIO_RISC_DMA_BUF_SIZE ( LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE + RISC_JUMP_INSTRUCTION_SIZE) 52#ifndef USE_RISC_NOOP_AUDIO
53#endif 53#define AUDIO_RISC_DMA_BUF_SIZE ( LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + RISC_JUMP_INSTRUCTION_SIZE)
54 54#endif
55 55
56#ifndef USE_RISC_NOOP_AUDIO 56static int _line_size;
57#define AUDIO_RISC_DMA_BUF_SIZE ( LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + RISC_JUMP_INSTRUCTION_SIZE) 57char *_defaultAudioName = "/root/audioGOOD.wav";
58#endif
59
60static int _line_size;
61char * _defaultAudioName = "/root/audioGOOD.wav";
62
diff --git a/drivers/staging/cx25821/cx25821-audio.h b/drivers/staging/cx25821/cx25821-audio.h
index 1e1351800ba0..503f42f036a8 100644
--- a/drivers/staging/cx25821/cx25821-audio.h
+++ b/drivers/staging/cx25821/cx25821-audio.h
@@ -1,60 +1,57 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef __CX25821_AUDIO_H__ 23#ifndef __CX25821_AUDIO_H__
24#define __CX25821_AUDIO_H__ 24#define __CX25821_AUDIO_H__
25 25
26 26#define USE_RISC_NOOP 1
27#define USE_RISC_NOOP 1 27#define LINES_PER_BUFFER 15
28#define LINES_PER_BUFFER 15 28#define AUDIO_LINE_SIZE 128
29#define AUDIO_LINE_SIZE 128 29
30 30//Number of buffer programs to use at once.
31//Number of buffer programs to use at once. 31#define NUMBER_OF_PROGRAMS 8
32#define NUMBER_OF_PROGRAMS 8 32
33 33//Max size of the RISC program for a buffer. - worst case is 2 writes per line
34//Max size of the RISC program for a buffer. - worst case is 2 writes per line 34// Space is also added for the 4 no-op instructions added on the end.
35// Space is also added for the 4 no-op instructions added on the end. 35
36 36#ifndef USE_RISC_NOOP
37#ifndef USE_RISC_NOOP 37#define MAX_BUFFER_PROGRAM_SIZE \
38#define MAX_BUFFER_PROGRAM_SIZE \ 38 (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE*4)
39 (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE*4) 39#endif
40#endif 40
41 41// MAE 12 July 2005 Try to use NOOP RISC instruction instead
42// MAE 12 July 2005 Try to use NOOP RISC instruction instead 42#ifdef USE_RISC_NOOP
43#ifdef USE_RISC_NOOP 43#define MAX_BUFFER_PROGRAM_SIZE \
44#define MAX_BUFFER_PROGRAM_SIZE \ 44 (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_NOOP_INSTRUCTION_SIZE*4)
45 (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_NOOP_INSTRUCTION_SIZE*4) 45#endif
46#endif 46
47 47//Sizes of various instructions in bytes. Used when adding instructions.
48 48#define RISC_WRITE_INSTRUCTION_SIZE 12
49//Sizes of various instructions in bytes. Used when adding instructions. 49#define RISC_JUMP_INSTRUCTION_SIZE 12
50#define RISC_WRITE_INSTRUCTION_SIZE 12 50#define RISC_SKIP_INSTRUCTION_SIZE 4
51#define RISC_JUMP_INSTRUCTION_SIZE 12 51#define RISC_SYNC_INSTRUCTION_SIZE 4
52#define RISC_SKIP_INSTRUCTION_SIZE 4 52#define RISC_WRITECR_INSTRUCTION_SIZE 16
53#define RISC_SYNC_INSTRUCTION_SIZE 4 53#define RISC_NOOP_INSTRUCTION_SIZE 4
54#define RISC_WRITECR_INSTRUCTION_SIZE 16 54
55#define RISC_NOOP_INSTRUCTION_SIZE 4 55#define MAX_AUDIO_DMA_BUFFER_SIZE (MAX_BUFFER_PROGRAM_SIZE * NUMBER_OF_PROGRAMS + RISC_SYNC_INSTRUCTION_SIZE)
56 56
57#define MAX_AUDIO_DMA_BUFFER_SIZE (MAX_BUFFER_PROGRAM_SIZE * NUMBER_OF_PROGRAMS + RISC_SYNC_INSTRUCTION_SIZE) 57#endif
58
59#endif
60
diff --git a/drivers/staging/cx25821/cx25821-audups11.c b/drivers/staging/cx25821/cx25821-audups11.c
index 4a60be2f688d..f78b8912d905 100644
--- a/drivers/staging/cx25821/cx25821-audups11.c
+++ b/drivers/staging/cx25821/cx25821-audups11.c
@@ -23,419 +23,412 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH11]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH11];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH11]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[SRAM_CH11]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 102
99 lock_kernel(); 103 lock_kernel();
100 list_for_each(list, &cx25821_devlist) 104 list_for_each(list, &cx25821_devlist) {
101 { 105 h = list_entry(list, struct cx25821_dev, devlist);
102 h = list_entry(list, struct cx25821_dev, devlist); 106
103 107 if (h->video_dev[SRAM_CH11]
104 if (h->video_dev[SRAM_CH11] && h->video_dev[SRAM_CH11]->minor == minor) 108 && h->video_dev[SRAM_CH11]->minor == minor) {
105 { 109 dev = h;
106 dev = h; 110 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
107 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 }
108 } 112 }
109 }
110 113
111 if (NULL == dev) { 114 if (NULL == dev) {
112 unlock_kernel(); 115 unlock_kernel();
113 return -ENODEV; 116 return -ENODEV;
114 } 117 }
115 118
116 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 119 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
117 120
118 /* allocate + initialize per filehandle data */ 121 /* allocate + initialize per filehandle data */
119 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 122 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
120 if (NULL == fh) { 123 if (NULL == fh) {
121 unlock_kernel(); 124 unlock_kernel();
122 return -ENOMEM; 125 return -ENOMEM;
123 } 126 }
124 127
125 file->private_data = fh; 128 file->private_data = fh;
126 fh->dev = dev; 129 fh->dev = dev;
127 fh->type = type; 130 fh->type = type;
128 fh->width = 720; 131 fh->width = 720;
129 132
130 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
131 fh->height = 576; 134 fh->height = 576;
132 else 135 else
133 fh->height = 480; 136 fh->height = 480;
134 137
135 dev->channel_opened = 10; 138 dev->channel_opened = 10;
136 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); 139 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV);
137 140
138 v4l2_prio_open(&dev->prio,&fh->prio); 141 v4l2_prio_open(&dev->prio, &fh->prio);
139 142
140 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, 143 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
141 &dev->pci->dev, &dev->slock, 144 &dev->pci->dev, &dev->slock,
142 V4L2_BUF_TYPE_VIDEO_CAPTURE, 145 V4L2_BUF_TYPE_VIDEO_CAPTURE,
143 V4L2_FIELD_INTERLACED, 146 V4L2_FIELD_INTERLACED,
144 sizeof(struct cx25821_buffer), 147 sizeof(struct cx25821_buffer), fh);
145 fh);
146 148
147 dprintk(1, "post videobuf_queue_init()\n"); 149 dprintk(1, "post videobuf_queue_init()\n");
148 unlock_kernel(); 150 unlock_kernel();
149 151
150 return 0; 152 return 0;
151} 153}
152 154
153static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 155static ssize_t video_read(struct file *file, char __user * data, size_t count,
156 loff_t * ppos)
154{ 157{
155 struct cx25821_fh *fh = file->private_data; 158 struct cx25821_fh *fh = file->private_data;
156 159
157 switch (fh->type) 160 switch (fh->type) {
158 {
159 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 161 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
160 if (res_locked(fh->dev, RESOURCE_VIDEO11)) 162 if (res_locked(fh->dev, RESOURCE_VIDEO11))
161 return -EBUSY; 163 return -EBUSY;
162 164
163 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 165 return videobuf_read_one(&fh->vidq, data, count, ppos,
166 file->f_flags & O_NONBLOCK);
164 167
165 default: 168 default:
166 BUG(); 169 BUG();
167 return 0; 170 return 0;
168 } 171 }
169} 172}
170 173
171static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 174static unsigned int video_poll(struct file *file,
175 struct poll_table_struct *wait)
172{ 176{
173 struct cx25821_fh *fh = file->private_data; 177 struct cx25821_fh *fh = file->private_data;
174 struct cx25821_buffer *buf; 178 struct cx25821_buffer *buf;
175 179
176 if (res_check(fh, RESOURCE_VIDEO11)) { 180 if (res_check(fh, RESOURCE_VIDEO11)) {
177 /* streaming capture */ 181 /* streaming capture */
178 if (list_empty(&fh->vidq.stream)) 182 if (list_empty(&fh->vidq.stream))
179 return POLLERR; 183 return POLLERR;
180 buf = list_entry(fh->vidq.stream.next, 184 buf = list_entry(fh->vidq.stream.next,
181 struct cx25821_buffer, vb.stream); 185 struct cx25821_buffer, vb.stream);
182 } else { 186 } else {
183 /* read() capture */ 187 /* read() capture */
184 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 188 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
185 if (NULL == buf) 189 if (NULL == buf)
186 return POLLERR; 190 return POLLERR;
187 } 191 }
188
189 poll_wait(file, &buf->vb.done, wait);
190 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
191 return POLLIN|POLLRDNORM;
192 return 0;
193}
194 192
193 poll_wait(file, &buf->vb.done, wait);
194 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
195 return POLLIN | POLLRDNORM;
196 return 0;
197}
195 198
196static int video_release(struct file *file) 199static int video_release(struct file *file)
197{ 200{
198 struct cx25821_fh *fh = file->private_data; 201 struct cx25821_fh *fh = file->private_data;
199 struct cx25821_dev *dev = fh->dev; 202 struct cx25821_dev *dev = fh->dev;
200 203
201 //stop the risc engine and fifo 204 //stop the risc engine and fifo
202 //cx_write(channel11->dma_ctl, 0); 205 //cx_write(channel11->dma_ctl, 0);
203 206
204 /* stop video capture */ 207 /* stop video capture */
205 if (res_check(fh, RESOURCE_VIDEO11)) { 208 if (res_check(fh, RESOURCE_VIDEO11)) {
206 videobuf_queue_cancel(&fh->vidq); 209 videobuf_queue_cancel(&fh->vidq);
207 res_free(dev, fh, RESOURCE_VIDEO11); 210 res_free(dev, fh, RESOURCE_VIDEO11);
208 } 211 }
209 212
210 if (fh->vidq.read_buf) { 213 if (fh->vidq.read_buf) {
211 buffer_release(&fh->vidq, fh->vidq.read_buf); 214 buffer_release(&fh->vidq, fh->vidq.read_buf);
212 kfree(fh->vidq.read_buf); 215 kfree(fh->vidq.read_buf);
213 } 216 }
214 217
215 videobuf_mmap_free(&fh->vidq); 218 videobuf_mmap_free(&fh->vidq);
216 219
217 v4l2_prio_close(&dev->prio,&fh->prio); 220 v4l2_prio_close(&dev->prio, &fh->prio);
218 221
219 file->private_data = NULL; 222 file->private_data = NULL;
220 kfree(fh); 223 kfree(fh);
221 224
222 return 0; 225 return 0;
223} 226}
224 227
225
226static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 228static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
227{ 229{
228 struct cx25821_fh *fh = priv; 230 struct cx25821_fh *fh = priv;
229 struct cx25821_dev *dev = fh->dev; 231 struct cx25821_dev *dev = fh->dev;
230 232
231 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 233 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
232 { 234 return -EINVAL;
233 return -EINVAL; 235 }
234 }
235 236
236 if (unlikely(i != fh->type)) 237 if (unlikely(i != fh->type)) {
237 { 238 return -EINVAL;
238 return -EINVAL; 239 }
239 }
240 240
241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO11)))) 241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO11)))) {
242 { 242 return -EBUSY;
243 return -EBUSY; 243 }
244 }
245 244
246 return videobuf_streamon(get_queue(fh)); 245 return videobuf_streamon(get_queue(fh));
247} 246}
248 247
249static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 248static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
250{ 249{
251 struct cx25821_fh *fh = priv; 250 struct cx25821_fh *fh = priv;
252 struct cx25821_dev *dev = fh->dev; 251 struct cx25821_dev *dev = fh->dev;
253 int err, res; 252 int err, res;
254 253
255 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 254 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
256 return -EINVAL; 255 return -EINVAL;
257 if (i != fh->type) 256 if (i != fh->type)
258 return -EINVAL; 257 return -EINVAL;
259 258
260 res = get_resource(fh, RESOURCE_VIDEO11); 259 res = get_resource(fh, RESOURCE_VIDEO11);
261 err = videobuf_streamoff(get_queue(fh)); 260 err = videobuf_streamoff(get_queue(fh));
262 if (err < 0) 261 if (err < 0)
263 return err; 262 return err;
264 res_free(dev, fh, res); 263 res_free(dev, fh, res);
265 return 0; 264 return 0;
266} 265}
267 266
268 267static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
269static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 268 struct v4l2_format *f)
270{ 269{
271 struct cx25821_fh *fh = priv; 270 struct cx25821_fh *fh = priv;
272 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 271 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
273 int err; 272 int err;
273
274 if (fh) {
275 err = v4l2_prio_check(&dev->prio, &fh->prio);
276 if (0 != err)
277 return err;
278 }
279
280 dprintk(2, "%s()\n", __func__);
281 err = vidioc_try_fmt_vid_cap(file, priv, f);
274 282
275 if (fh)
276 {
277 err = v4l2_prio_check(&dev->prio, &fh->prio);
278 if (0 != err) 283 if (0 != err)
279 return err; 284 return err;
280 } 285 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
281 286 fh->width = f->fmt.pix.width;
282 dprintk(2, "%s()\n", __func__); 287 fh->height = f->fmt.pix.height;
283 err = vidioc_try_fmt_vid_cap(file, priv, f); 288 fh->vidq.field = f->fmt.pix.field;
284 289 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
285 if (0 != err) 290 fh->height, fh->vidq.field);
286 return err; 291 cx25821_call_all(dev, video, s_fmt, f);
287 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 292 return 0;
288 fh->width = f->fmt.pix.width;
289 fh->height = f->fmt.pix.height;
290 fh->vidq.field = f->fmt.pix.field;
291 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
292 cx25821_call_all(dev, video, s_fmt, f);
293 return 0;
294} 293}
295 294
296static long video_ioctl_upstream11(struct file *file, unsigned int cmd, unsigned long arg) 295static long video_ioctl_upstream11(struct file *file, unsigned int cmd,
296 unsigned long arg)
297{ 297{
298 struct cx25821_fh *fh = file->private_data; 298 struct cx25821_fh *fh = file->private_data;
299 struct cx25821_dev *dev = fh->dev; 299 struct cx25821_dev *dev = fh->dev;
300 int command = 0; 300 int command = 0;
301 struct upstream_user_struct *data_from_user; 301 struct upstream_user_struct *data_from_user;
302 302
303 303 data_from_user = (struct upstream_user_struct *)arg;
304 data_from_user = (struct upstream_user_struct *)arg; 304
305 305 if (!data_from_user) {
306 if( !data_from_user ) 306 printk
307 { 307 ("cx25821 in %s(): Upstream data is INVALID. Returning.\n",
308 printk("cx25821 in %s(): Upstream data is INVALID. Returning.\n", __func__); 308 __func__);
309 return 0; 309 return 0;
310 } 310 }
311
312 command = data_from_user->command;
313
314 if( command != UPSTREAM_START_AUDIO && command != UPSTREAM_STOP_AUDIO )
315 {
316 return 0;
317 }
318 311
312 command = data_from_user->command;
319 313
320 dev->input_filename = data_from_user->input_filename; 314 if (command != UPSTREAM_START_AUDIO && command != UPSTREAM_STOP_AUDIO) {
321 dev->input_audiofilename = data_from_user->input_filename; 315 return 0;
322 dev->vid_stdname = data_from_user->vid_stdname; 316 }
323 dev->pixel_format = data_from_user->pixel_format;
324 dev->channel_select = data_from_user->channel_select;
325 dev->command = data_from_user->command;
326 317
318 dev->input_filename = data_from_user->input_filename;
319 dev->input_audiofilename = data_from_user->input_filename;
320 dev->vid_stdname = data_from_user->vid_stdname;
321 dev->pixel_format = data_from_user->pixel_format;
322 dev->channel_select = data_from_user->channel_select;
323 dev->command = data_from_user->command;
327 324
328 switch(command) 325 switch (command) {
329 {
330 case UPSTREAM_START_AUDIO: 326 case UPSTREAM_START_AUDIO:
331 cx25821_start_upstream_audio(dev, data_from_user); 327 cx25821_start_upstream_audio(dev, data_from_user);
332 break; 328 break;
333 329
334 case UPSTREAM_STOP_AUDIO: 330 case UPSTREAM_STOP_AUDIO:
335 cx25821_stop_upstream_audio(dev); 331 cx25821_stop_upstream_audio(dev);
336 break; 332 break;
337 } 333 }
338 334
339 return 0; 335 return 0;
340} 336}
341 337
342static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 338static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
343{ 339{
344 struct cx25821_fh *fh = priv; 340 struct cx25821_fh *fh = priv;
345 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 341 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
346} 342}
347 343
348static int vidioc_log_status (struct file *file, void *priv) 344static int vidioc_log_status(struct file *file, void *priv)
349{ 345{
350 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 346 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
351 char name[32 + 2]; 347 char name[32 + 2];
352 348
353 snprintf(name, sizeof(name), "%s/2", dev->name); 349 snprintf(name, sizeof(name), "%s/2", dev->name);
354 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 350 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
355 dev->name); 351 dev->name);
356 cx25821_call_all(dev, core, log_status); 352 cx25821_call_all(dev, core, log_status);
357 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 353 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
358 dev->name); 354 dev->name);
359 return 0; 355 return 0;
360} 356}
361 357
362static int vidioc_s_ctrl(struct file *file, void *priv, 358static int vidioc_s_ctrl(struct file *file, void *priv,
363 struct v4l2_control *ctl) 359 struct v4l2_control *ctl)
364{ 360{
365 struct cx25821_fh *fh = priv; 361 struct cx25821_fh *fh = priv;
366 struct cx25821_dev *dev = fh->dev; 362 struct cx25821_dev *dev = fh->dev;
367 int err; 363 int err;
368 364
369 if (fh) 365 if (fh) {
370 { 366 err = v4l2_prio_check(&dev->prio, &fh->prio);
371 err = v4l2_prio_check(&dev->prio, &fh->prio); 367 if (0 != err)
372 if (0 != err) 368 return err;
373 return err; 369 }
374 } 370 return 0;
375 return 0;
376} 371}
372
377// exported stuff 373// exported stuff
378static const struct v4l2_file_operations video_fops = { 374static const struct v4l2_file_operations video_fops = {
379 .owner = THIS_MODULE, 375 .owner = THIS_MODULE,
380 .open = video_open, 376 .open = video_open,
381 .release = video_release, 377 .release = video_release,
382 .read = video_read, 378 .read = video_read,
383 .poll = video_poll, 379 .poll = video_poll,
384 .mmap = video_mmap, 380 .mmap = video_mmap,
385 .ioctl = video_ioctl_upstream11, 381 .ioctl = video_ioctl_upstream11,
386}; 382};
387 383
388static const struct v4l2_ioctl_ops video_ioctl_ops = { 384static const struct v4l2_ioctl_ops video_ioctl_ops = {
389 .vidioc_querycap = vidioc_querycap, 385 .vidioc_querycap = vidioc_querycap,
390 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 386 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
391 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 387 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
392 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 388 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
393 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 389 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
394 .vidioc_reqbufs = vidioc_reqbufs, 390 .vidioc_reqbufs = vidioc_reqbufs,
395 .vidioc_querybuf = vidioc_querybuf, 391 .vidioc_querybuf = vidioc_querybuf,
396 .vidioc_qbuf = vidioc_qbuf, 392 .vidioc_qbuf = vidioc_qbuf,
397 .vidioc_dqbuf = vidioc_dqbuf, 393 .vidioc_dqbuf = vidioc_dqbuf,
398#ifdef TUNER_FLAG 394#ifdef TUNER_FLAG
399 .vidioc_s_std = vidioc_s_std, 395 .vidioc_s_std = vidioc_s_std,
400 .vidioc_querystd = vidioc_querystd, 396 .vidioc_querystd = vidioc_querystd,
401#endif 397#endif
402 .vidioc_cropcap = vidioc_cropcap, 398 .vidioc_cropcap = vidioc_cropcap,
403 .vidioc_s_crop = vidioc_s_crop, 399 .vidioc_s_crop = vidioc_s_crop,
404 .vidioc_g_crop = vidioc_g_crop, 400 .vidioc_g_crop = vidioc_g_crop,
405 .vidioc_enum_input = vidioc_enum_input, 401 .vidioc_enum_input = vidioc_enum_input,
406 .vidioc_g_input = vidioc_g_input, 402 .vidioc_g_input = vidioc_g_input,
407 .vidioc_s_input = vidioc_s_input, 403 .vidioc_s_input = vidioc_s_input,
408 .vidioc_g_ctrl = vidioc_g_ctrl, 404 .vidioc_g_ctrl = vidioc_g_ctrl,
409 .vidioc_s_ctrl = vidioc_s_ctrl, 405 .vidioc_s_ctrl = vidioc_s_ctrl,
410 .vidioc_queryctrl = vidioc_queryctrl, 406 .vidioc_queryctrl = vidioc_queryctrl,
411 .vidioc_streamon = vidioc_streamon, 407 .vidioc_streamon = vidioc_streamon,
412 .vidioc_streamoff = vidioc_streamoff, 408 .vidioc_streamoff = vidioc_streamoff,
413 .vidioc_log_status = vidioc_log_status, 409 .vidioc_log_status = vidioc_log_status,
414 .vidioc_g_priority = vidioc_g_priority, 410 .vidioc_g_priority = vidioc_g_priority,
415 .vidioc_s_priority = vidioc_s_priority, 411 .vidioc_s_priority = vidioc_s_priority,
416#ifdef CONFIG_VIDEO_V4L1_COMPAT 412#ifdef CONFIG_VIDEO_V4L1_COMPAT
417 .vidiocgmbuf = vidiocgmbuf, 413 .vidiocgmbuf = vidiocgmbuf,
418#endif 414#endif
419#ifdef TUNER_FLAG 415#ifdef TUNER_FLAG
420 .vidioc_g_tuner = vidioc_g_tuner, 416 .vidioc_g_tuner = vidioc_g_tuner,
421 .vidioc_s_tuner = vidioc_s_tuner, 417 .vidioc_s_tuner = vidioc_s_tuner,
422 .vidioc_g_frequency = vidioc_g_frequency, 418 .vidioc_g_frequency = vidioc_g_frequency,
423 .vidioc_s_frequency = vidioc_s_frequency, 419 .vidioc_s_frequency = vidioc_s_frequency,
424#endif 420#endif
425#ifdef CONFIG_VIDEO_ADV_DEBUG 421#ifdef CONFIG_VIDEO_ADV_DEBUG
426 .vidioc_g_register = vidioc_g_register, 422 .vidioc_g_register = vidioc_g_register,
427 .vidioc_s_register = vidioc_s_register, 423 .vidioc_s_register = vidioc_s_register,
428#endif 424#endif
429}; 425};
430 426
431struct video_device cx25821_video_template11 = { 427struct video_device cx25821_video_template11 = {
432 .name = "cx25821-audioupstream", 428 .name = "cx25821-audioupstream",
433 .fops = &video_fops, 429 .fops = &video_fops,
434 .minor = -1, 430 .minor = -1,
435 .ioctl_ops = &video_ioctl_ops, 431 .ioctl_ops = &video_ioctl_ops,
436 .tvnorms = CX25821_NORMS, 432 .tvnorms = CX25821_NORMS,
437 .current_norm = V4L2_STD_NTSC_M, 433 .current_norm = V4L2_STD_NTSC_M,
438}; 434};
439
440
441
diff --git a/drivers/staging/cx25821/cx25821-biffuncs.h b/drivers/staging/cx25821/cx25821-biffuncs.h
index a5c053507a42..9326a7c729ec 100644
--- a/drivers/staging/cx25821/cx25821-biffuncs.h
+++ b/drivers/staging/cx25821/cx25821-biffuncs.h
@@ -1,45 +1,45 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef _BITFUNCS_H 23#ifndef _BITFUNCS_H
24#define _BITFUNCS_H 24#define _BITFUNCS_H
25 25
26#define SetBit(Bit) (1 << Bit) 26#define SetBit(Bit) (1 << Bit)
27 27
28inline u8 getBit(u32 sample, u8 index) 28inline u8 getBit(u32 sample, u8 index)
29{ 29{
30 return (u8) ((sample >> index) & 1); 30 return (u8) ((sample >> index) & 1);
31} 31}
32 32
33inline u32 clearBitAtPos(u32 value, u8 bit) 33inline u32 clearBitAtPos(u32 value, u8 bit)
34{ 34{
35 return value & ~(1 << bit); 35 return value & ~(1 << bit);
36} 36}
37 37
38inline u32 setBitAtPos(u32 sample, u8 bit) 38inline u32 setBitAtPos(u32 sample, u8 bit)
39{ 39{
40 sample |= (1 << bit); 40 sample |= (1 << bit);
41 return sample; 41 return sample;
42 42
43} 43}
44 44
45#endif 45#endif
diff --git a/drivers/staging/cx25821/cx25821-cards.c b/drivers/staging/cx25821/cx25821-cards.c
index f8f3c3279168..4d0b9eac3e49 100644
--- a/drivers/staging/cx25821/cx25821-cards.c
+++ b/drivers/staging/cx25821/cx25821-cards.c
@@ -1,26 +1,26 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver 6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * 16 *
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */ 22 */
23 23
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/pci.h> 26#include <linux/pci.h>
@@ -34,39 +34,37 @@
34 34
35struct cx25821_board cx25821_boards[] = { 35struct cx25821_board cx25821_boards[] = {
36 [UNKNOWN_BOARD] = { 36 [UNKNOWN_BOARD] = {
37 .name = "UNKNOWN/GENERIC", 37 .name = "UNKNOWN/GENERIC",
38 // Ensure safe default for unknown boards 38 // Ensure safe default for unknown boards
39 .clk_freq = 0, 39 .clk_freq = 0,
40 }, 40 },
41 41
42 [CX25821_BOARD] = { 42 [CX25821_BOARD] = {
43 .name = "CX25821", 43 .name = "CX25821",
44 .portb = CX25821_RAW, 44 .portb = CX25821_RAW,
45 .portc = CX25821_264, 45 .portc = CX25821_264,
46 .input[0].type = CX25821_VMUX_COMPOSITE, 46 .input[0].type = CX25821_VMUX_COMPOSITE,
47 }, 47 },
48 48
49}; 49};
50 50
51const unsigned int cx25821_bcount = ARRAY_SIZE(cx25821_boards); 51const unsigned int cx25821_bcount = ARRAY_SIZE(cx25821_boards);
52 52
53struct cx25821_subid cx25821_subids[]={ 53struct cx25821_subid cx25821_subids[] = {
54 { 54 {
55 .subvendor = 0x14f1, 55 .subvendor = 0x14f1,
56 .subdevice = 0x0920, 56 .subdevice = 0x0920,
57 .card = CX25821_BOARD, 57 .card = CX25821_BOARD,
58 }, 58 },
59}; 59};
60 60
61
62void cx25821_card_setup(struct cx25821_dev *dev) 61void cx25821_card_setup(struct cx25821_dev *dev)
63{ 62{
64 static u8 eeprom[256]; 63 static u8 eeprom[256];
65 64
66 if (dev->i2c_bus[0].i2c_rc == 0) 65 if (dev->i2c_bus[0].i2c_rc == 0) {
67 {
68 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 66 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
69 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); 67 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
68 sizeof(eeprom));
70 } 69 }
71} 70}
72
diff --git a/drivers/staging/cx25821/cx25821-core.c b/drivers/staging/cx25821/cx25821-core.c
index 6f2970c1d25a..4d1ee06fb918 100644
--- a/drivers/staging/cx25821/cx25821-core.c
+++ b/drivers/staging/cx25821/cx25821-core.c
@@ -36,287 +36,283 @@ static unsigned int debug;
36module_param(debug, int, 0644); 36module_param(debug, int, 0644);
37MODULE_PARM_DESC(debug, "enable debug messages"); 37MODULE_PARM_DESC(debug, "enable debug messages");
38 38
39static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; 39static unsigned int card[] = {[0...(CX25821_MAXBOARDS - 1)] = UNSET };
40module_param_array(card, int, NULL, 0444); 40module_param_array(card, int, NULL, 0444);
41MODULE_PARM_DESC(card, "card type"); 41MODULE_PARM_DESC(card, "card type");
42 42
43
44static unsigned int cx25821_devcount = 0; 43static unsigned int cx25821_devcount = 0;
45 44
46static DEFINE_MUTEX(devlist); 45static DEFINE_MUTEX(devlist);
47LIST_HEAD(cx25821_devlist); 46LIST_HEAD(cx25821_devlist);
48 47
49
50struct sram_channel cx25821_sram_channels[] = { 48struct sram_channel cx25821_sram_channels[] = {
51 [SRAM_CH00] = { 49 [SRAM_CH00] = {
52 .i = SRAM_CH00, 50 .i = SRAM_CH00,
53 .name = "VID A", 51 .name = "VID A",
54 .cmds_start = VID_A_DOWN_CMDS, 52 .cmds_start = VID_A_DOWN_CMDS,
55 .ctrl_start = VID_A_IQ, 53 .ctrl_start = VID_A_IQ,
56 .cdt = VID_A_CDT, 54 .cdt = VID_A_CDT,
57 .fifo_start = VID_A_DOWN_CLUSTER_1, 55 .fifo_start = VID_A_DOWN_CLUSTER_1,
58 .fifo_size = (VID_CLUSTER_SIZE<<2), 56 .fifo_size = (VID_CLUSTER_SIZE << 2),
59 .ptr1_reg = DMA1_PTR1, 57 .ptr1_reg = DMA1_PTR1,
60 .ptr2_reg = DMA1_PTR2, 58 .ptr2_reg = DMA1_PTR2,
61 .cnt1_reg = DMA1_CNT1, 59 .cnt1_reg = DMA1_CNT1,
62 .cnt2_reg = DMA1_CNT2, 60 .cnt2_reg = DMA1_CNT2,
63 .int_msk = VID_A_INT_MSK, 61 .int_msk = VID_A_INT_MSK,
64 .int_stat = VID_A_INT_STAT, 62 .int_stat = VID_A_INT_STAT,
65 .int_mstat = VID_A_INT_MSTAT, 63 .int_mstat = VID_A_INT_MSTAT,
66 .dma_ctl = VID_DST_A_DMA_CTL, 64 .dma_ctl = VID_DST_A_DMA_CTL,
67 .gpcnt_ctl = VID_DST_A_GPCNT_CTL, 65 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
68 .gpcnt = VID_DST_A_GPCNT, 66 .gpcnt = VID_DST_A_GPCNT,
69 .vip_ctl = VID_DST_A_VIP_CTL, 67 .vip_ctl = VID_DST_A_VIP_CTL,
70 .pix_frmt = VID_DST_A_PIX_FRMT, 68 .pix_frmt = VID_DST_A_PIX_FRMT,
71 }, 69 },
72 70
73 [SRAM_CH01] = { 71 [SRAM_CH01] = {
74 .i = SRAM_CH01, 72 .i = SRAM_CH01,
75 .name = "VID B", 73 .name = "VID B",
76 .cmds_start = VID_B_DOWN_CMDS, 74 .cmds_start = VID_B_DOWN_CMDS,
77 .ctrl_start = VID_B_IQ, 75 .ctrl_start = VID_B_IQ,
78 .cdt = VID_B_CDT, 76 .cdt = VID_B_CDT,
79 .fifo_start = VID_B_DOWN_CLUSTER_1, 77 .fifo_start = VID_B_DOWN_CLUSTER_1,
80 .fifo_size = (VID_CLUSTER_SIZE<<2), 78 .fifo_size = (VID_CLUSTER_SIZE << 2),
81 .ptr1_reg = DMA2_PTR1, 79 .ptr1_reg = DMA2_PTR1,
82 .ptr2_reg = DMA2_PTR2, 80 .ptr2_reg = DMA2_PTR2,
83 .cnt1_reg = DMA2_CNT1, 81 .cnt1_reg = DMA2_CNT1,
84 .cnt2_reg = DMA2_CNT2, 82 .cnt2_reg = DMA2_CNT2,
85 .int_msk = VID_B_INT_MSK, 83 .int_msk = VID_B_INT_MSK,
86 .int_stat = VID_B_INT_STAT, 84 .int_stat = VID_B_INT_STAT,
87 .int_mstat = VID_B_INT_MSTAT, 85 .int_mstat = VID_B_INT_MSTAT,
88 .dma_ctl = VID_DST_B_DMA_CTL, 86 .dma_ctl = VID_DST_B_DMA_CTL,
89 .gpcnt_ctl = VID_DST_B_GPCNT_CTL, 87 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
90 .gpcnt = VID_DST_B_GPCNT, 88 .gpcnt = VID_DST_B_GPCNT,
91 .vip_ctl = VID_DST_B_VIP_CTL, 89 .vip_ctl = VID_DST_B_VIP_CTL,
92 .pix_frmt = VID_DST_B_PIX_FRMT, 90 .pix_frmt = VID_DST_B_PIX_FRMT,
93 }, 91 },
94 92
95 [SRAM_CH02] = { 93 [SRAM_CH02] = {
96 .i = SRAM_CH02, 94 .i = SRAM_CH02,
97 .name = "VID C", 95 .name = "VID C",
98 .cmds_start = VID_C_DOWN_CMDS, 96 .cmds_start = VID_C_DOWN_CMDS,
99 .ctrl_start = VID_C_IQ, 97 .ctrl_start = VID_C_IQ,
100 .cdt = VID_C_CDT, 98 .cdt = VID_C_CDT,
101 .fifo_start = VID_C_DOWN_CLUSTER_1, 99 .fifo_start = VID_C_DOWN_CLUSTER_1,
102 .fifo_size = (VID_CLUSTER_SIZE<<2), 100 .fifo_size = (VID_CLUSTER_SIZE << 2),
103 .ptr1_reg = DMA3_PTR1, 101 .ptr1_reg = DMA3_PTR1,
104 .ptr2_reg = DMA3_PTR2, 102 .ptr2_reg = DMA3_PTR2,
105 .cnt1_reg = DMA3_CNT1, 103 .cnt1_reg = DMA3_CNT1,
106 .cnt2_reg = DMA3_CNT2, 104 .cnt2_reg = DMA3_CNT2,
107 .int_msk = VID_C_INT_MSK, 105 .int_msk = VID_C_INT_MSK,
108 .int_stat = VID_C_INT_STAT, 106 .int_stat = VID_C_INT_STAT,
109 .int_mstat = VID_C_INT_MSTAT, 107 .int_mstat = VID_C_INT_MSTAT,
110 .dma_ctl = VID_DST_C_DMA_CTL, 108 .dma_ctl = VID_DST_C_DMA_CTL,
111 .gpcnt_ctl = VID_DST_C_GPCNT_CTL, 109 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
112 .gpcnt = VID_DST_C_GPCNT, 110 .gpcnt = VID_DST_C_GPCNT,
113 .vip_ctl = VID_DST_C_VIP_CTL, 111 .vip_ctl = VID_DST_C_VIP_CTL,
114 .pix_frmt = VID_DST_C_PIX_FRMT, 112 .pix_frmt = VID_DST_C_PIX_FRMT,
115 }, 113 },
116 114
117 [SRAM_CH03] = { 115 [SRAM_CH03] = {
118 .i = SRAM_CH03, 116 .i = SRAM_CH03,
119 .name = "VID D", 117 .name = "VID D",
120 .cmds_start = VID_D_DOWN_CMDS, 118 .cmds_start = VID_D_DOWN_CMDS,
121 .ctrl_start = VID_D_IQ, 119 .ctrl_start = VID_D_IQ,
122 .cdt = VID_D_CDT, 120 .cdt = VID_D_CDT,
123 .fifo_start = VID_D_DOWN_CLUSTER_1, 121 .fifo_start = VID_D_DOWN_CLUSTER_1,
124 .fifo_size = (VID_CLUSTER_SIZE<<2), 122 .fifo_size = (VID_CLUSTER_SIZE << 2),
125 .ptr1_reg = DMA4_PTR1, 123 .ptr1_reg = DMA4_PTR1,
126 .ptr2_reg = DMA4_PTR2, 124 .ptr2_reg = DMA4_PTR2,
127 .cnt1_reg = DMA4_CNT1, 125 .cnt1_reg = DMA4_CNT1,
128 .cnt2_reg = DMA4_CNT2, 126 .cnt2_reg = DMA4_CNT2,
129 .int_msk = VID_D_INT_MSK, 127 .int_msk = VID_D_INT_MSK,
130 .int_stat = VID_D_INT_STAT, 128 .int_stat = VID_D_INT_STAT,
131 .int_mstat = VID_D_INT_MSTAT, 129 .int_mstat = VID_D_INT_MSTAT,
132 .dma_ctl = VID_DST_D_DMA_CTL, 130 .dma_ctl = VID_DST_D_DMA_CTL,
133 .gpcnt_ctl = VID_DST_D_GPCNT_CTL, 131 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
134 .gpcnt = VID_DST_D_GPCNT, 132 .gpcnt = VID_DST_D_GPCNT,
135 .vip_ctl = VID_DST_D_VIP_CTL, 133 .vip_ctl = VID_DST_D_VIP_CTL,
136 .pix_frmt = VID_DST_D_PIX_FRMT, 134 .pix_frmt = VID_DST_D_PIX_FRMT,
137 }, 135 },
138 136
139 [SRAM_CH04] = { 137 [SRAM_CH04] = {
140 .i = SRAM_CH04, 138 .i = SRAM_CH04,
141 .name = "VID E", 139 .name = "VID E",
142 .cmds_start = VID_E_DOWN_CMDS, 140 .cmds_start = VID_E_DOWN_CMDS,
143 .ctrl_start = VID_E_IQ, 141 .ctrl_start = VID_E_IQ,
144 .cdt = VID_E_CDT, 142 .cdt = VID_E_CDT,
145 .fifo_start = VID_E_DOWN_CLUSTER_1, 143 .fifo_start = VID_E_DOWN_CLUSTER_1,
146 .fifo_size = (VID_CLUSTER_SIZE<<2), 144 .fifo_size = (VID_CLUSTER_SIZE << 2),
147 .ptr1_reg = DMA5_PTR1, 145 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2, 146 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1, 147 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2, 148 .cnt2_reg = DMA5_CNT2,
151 .int_msk = VID_E_INT_MSK, 149 .int_msk = VID_E_INT_MSK,
152 .int_stat = VID_E_INT_STAT, 150 .int_stat = VID_E_INT_STAT,
153 .int_mstat = VID_E_INT_MSTAT, 151 .int_mstat = VID_E_INT_MSTAT,
154 .dma_ctl = VID_DST_E_DMA_CTL, 152 .dma_ctl = VID_DST_E_DMA_CTL,
155 .gpcnt_ctl = VID_DST_E_GPCNT_CTL, 153 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
156 .gpcnt = VID_DST_E_GPCNT, 154 .gpcnt = VID_DST_E_GPCNT,
157 .vip_ctl = VID_DST_E_VIP_CTL, 155 .vip_ctl = VID_DST_E_VIP_CTL,
158 .pix_frmt = VID_DST_E_PIX_FRMT, 156 .pix_frmt = VID_DST_E_PIX_FRMT,
159 }, 157 },
160 158
161 [SRAM_CH05] = { 159 [SRAM_CH05] = {
162 .i = SRAM_CH05, 160 .i = SRAM_CH05,
163 .name = "VID F", 161 .name = "VID F",
164 .cmds_start = VID_F_DOWN_CMDS, 162 .cmds_start = VID_F_DOWN_CMDS,
165 .ctrl_start = VID_F_IQ, 163 .ctrl_start = VID_F_IQ,
166 .cdt = VID_F_CDT, 164 .cdt = VID_F_CDT,
167 .fifo_start = VID_F_DOWN_CLUSTER_1, 165 .fifo_start = VID_F_DOWN_CLUSTER_1,
168 .fifo_size = (VID_CLUSTER_SIZE<<2), 166 .fifo_size = (VID_CLUSTER_SIZE << 2),
169 .ptr1_reg = DMA6_PTR1, 167 .ptr1_reg = DMA6_PTR1,
170 .ptr2_reg = DMA6_PTR2, 168 .ptr2_reg = DMA6_PTR2,
171 .cnt1_reg = DMA6_CNT1, 169 .cnt1_reg = DMA6_CNT1,
172 .cnt2_reg = DMA6_CNT2, 170 .cnt2_reg = DMA6_CNT2,
173 .int_msk = VID_F_INT_MSK, 171 .int_msk = VID_F_INT_MSK,
174 .int_stat = VID_F_INT_STAT, 172 .int_stat = VID_F_INT_STAT,
175 .int_mstat = VID_F_INT_MSTAT, 173 .int_mstat = VID_F_INT_MSTAT,
176 .dma_ctl = VID_DST_F_DMA_CTL, 174 .dma_ctl = VID_DST_F_DMA_CTL,
177 .gpcnt_ctl = VID_DST_F_GPCNT_CTL, 175 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
178 .gpcnt = VID_DST_F_GPCNT, 176 .gpcnt = VID_DST_F_GPCNT,
179 .vip_ctl = VID_DST_F_VIP_CTL, 177 .vip_ctl = VID_DST_F_VIP_CTL,
180 .pix_frmt = VID_DST_F_PIX_FRMT, 178 .pix_frmt = VID_DST_F_PIX_FRMT,
181 }, 179 },
182 180
183 [SRAM_CH06] = { 181 [SRAM_CH06] = {
184 .i = SRAM_CH06, 182 .i = SRAM_CH06,
185 .name = "VID G", 183 .name = "VID G",
186 .cmds_start = VID_G_DOWN_CMDS, 184 .cmds_start = VID_G_DOWN_CMDS,
187 .ctrl_start = VID_G_IQ, 185 .ctrl_start = VID_G_IQ,
188 .cdt = VID_G_CDT, 186 .cdt = VID_G_CDT,
189 .fifo_start = VID_G_DOWN_CLUSTER_1, 187 .fifo_start = VID_G_DOWN_CLUSTER_1,
190 .fifo_size = (VID_CLUSTER_SIZE<<2), 188 .fifo_size = (VID_CLUSTER_SIZE << 2),
191 .ptr1_reg = DMA7_PTR1, 189 .ptr1_reg = DMA7_PTR1,
192 .ptr2_reg = DMA7_PTR2, 190 .ptr2_reg = DMA7_PTR2,
193 .cnt1_reg = DMA7_CNT1, 191 .cnt1_reg = DMA7_CNT1,
194 .cnt2_reg = DMA7_CNT2, 192 .cnt2_reg = DMA7_CNT2,
195 .int_msk = VID_G_INT_MSK, 193 .int_msk = VID_G_INT_MSK,
196 .int_stat = VID_G_INT_STAT, 194 .int_stat = VID_G_INT_STAT,
197 .int_mstat = VID_G_INT_MSTAT, 195 .int_mstat = VID_G_INT_MSTAT,
198 .dma_ctl = VID_DST_G_DMA_CTL, 196 .dma_ctl = VID_DST_G_DMA_CTL,
199 .gpcnt_ctl = VID_DST_G_GPCNT_CTL, 197 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
200 .gpcnt = VID_DST_G_GPCNT, 198 .gpcnt = VID_DST_G_GPCNT,
201 .vip_ctl = VID_DST_G_VIP_CTL, 199 .vip_ctl = VID_DST_G_VIP_CTL,
202 .pix_frmt = VID_DST_G_PIX_FRMT, 200 .pix_frmt = VID_DST_G_PIX_FRMT,
203 }, 201 },
204 202
205 [SRAM_CH07] = { 203 [SRAM_CH07] = {
206 .i = SRAM_CH07, 204 .i = SRAM_CH07,
207 .name = "VID H", 205 .name = "VID H",
208 .cmds_start = VID_H_DOWN_CMDS, 206 .cmds_start = VID_H_DOWN_CMDS,
209 .ctrl_start = VID_H_IQ, 207 .ctrl_start = VID_H_IQ,
210 .cdt = VID_H_CDT, 208 .cdt = VID_H_CDT,
211 .fifo_start = VID_H_DOWN_CLUSTER_1, 209 .fifo_start = VID_H_DOWN_CLUSTER_1,
212 .fifo_size = (VID_CLUSTER_SIZE<<2), 210 .fifo_size = (VID_CLUSTER_SIZE << 2),
213 .ptr1_reg = DMA8_PTR1, 211 .ptr1_reg = DMA8_PTR1,
214 .ptr2_reg = DMA8_PTR2, 212 .ptr2_reg = DMA8_PTR2,
215 .cnt1_reg = DMA8_CNT1, 213 .cnt1_reg = DMA8_CNT1,
216 .cnt2_reg = DMA8_CNT2, 214 .cnt2_reg = DMA8_CNT2,
217 .int_msk = VID_H_INT_MSK, 215 .int_msk = VID_H_INT_MSK,
218 .int_stat = VID_H_INT_STAT, 216 .int_stat = VID_H_INT_STAT,
219 .int_mstat = VID_H_INT_MSTAT, 217 .int_mstat = VID_H_INT_MSTAT,
220 .dma_ctl = VID_DST_H_DMA_CTL, 218 .dma_ctl = VID_DST_H_DMA_CTL,
221 .gpcnt_ctl = VID_DST_H_GPCNT_CTL, 219 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
222 .gpcnt = VID_DST_H_GPCNT, 220 .gpcnt = VID_DST_H_GPCNT,
223 .vip_ctl = VID_DST_H_VIP_CTL, 221 .vip_ctl = VID_DST_H_VIP_CTL,
224 .pix_frmt = VID_DST_H_PIX_FRMT, 222 .pix_frmt = VID_DST_H_PIX_FRMT,
225 }, 223 },
226 224
227 [SRAM_CH08] = { 225 [SRAM_CH08] = {
228 .name = "audio from", 226 .name = "audio from",
229 .cmds_start = AUD_A_DOWN_CMDS, 227 .cmds_start = AUD_A_DOWN_CMDS,
230 .ctrl_start = AUD_A_IQ, 228 .ctrl_start = AUD_A_IQ,
231 .cdt = AUD_A_CDT, 229 .cdt = AUD_A_CDT,
232 .fifo_start = AUD_A_DOWN_CLUSTER_1, 230 .fifo_start = AUD_A_DOWN_CLUSTER_1,
233 .fifo_size = AUDIO_CLUSTER_SIZE * 3, 231 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
234 .ptr1_reg = DMA17_PTR1, 232 .ptr1_reg = DMA17_PTR1,
235 .ptr2_reg = DMA17_PTR2, 233 .ptr2_reg = DMA17_PTR2,
236 .cnt1_reg = DMA17_CNT1, 234 .cnt1_reg = DMA17_CNT1,
237 .cnt2_reg = DMA17_CNT2, 235 .cnt2_reg = DMA17_CNT2,
238 }, 236 },
239 237
240 [SRAM_CH09] = { 238 [SRAM_CH09] = {
241 .i = SRAM_CH09, 239 .i = SRAM_CH09,
242 .name = "VID Upstream I", 240 .name = "VID Upstream I",
243 .cmds_start = VID_I_UP_CMDS, 241 .cmds_start = VID_I_UP_CMDS,
244 .ctrl_start = VID_I_IQ, 242 .ctrl_start = VID_I_IQ,
245 .cdt = VID_I_CDT, 243 .cdt = VID_I_CDT,
246 .fifo_start = VID_I_UP_CLUSTER_1, 244 .fifo_start = VID_I_UP_CLUSTER_1,
247 .fifo_size = (VID_CLUSTER_SIZE<<2), 245 .fifo_size = (VID_CLUSTER_SIZE << 2),
248 .ptr1_reg = DMA15_PTR1, 246 .ptr1_reg = DMA15_PTR1,
249 .ptr2_reg = DMA15_PTR2, 247 .ptr2_reg = DMA15_PTR2,
250 .cnt1_reg = DMA15_CNT1, 248 .cnt1_reg = DMA15_CNT1,
251 .cnt2_reg = DMA15_CNT2, 249 .cnt2_reg = DMA15_CNT2,
252 .int_msk = VID_I_INT_MSK, 250 .int_msk = VID_I_INT_MSK,
253 .int_stat = VID_I_INT_STAT, 251 .int_stat = VID_I_INT_STAT,
254 .int_mstat = VID_I_INT_MSTAT, 252 .int_mstat = VID_I_INT_MSTAT,
255 .dma_ctl = VID_SRC_I_DMA_CTL, 253 .dma_ctl = VID_SRC_I_DMA_CTL,
256 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL, 254 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
257 .gpcnt = VID_SRC_I_GPCNT, 255 .gpcnt = VID_SRC_I_GPCNT,
258 256
259 .vid_fmt_ctl = VID_SRC_I_FMT_CTL, 257 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
260 .vid_active_ctl1= VID_SRC_I_ACTIVE_CTL1, 258 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
261 .vid_active_ctl2= VID_SRC_I_ACTIVE_CTL2, 259 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
262 .vid_cdt_size = VID_SRC_I_CDT_SZ, 260 .vid_cdt_size = VID_SRC_I_CDT_SZ,
263 .irq_bit = 8, 261 .irq_bit = 8,
264 }, 262 },
265 263
266 [SRAM_CH10] = { 264 [SRAM_CH10] = {
267 .i = SRAM_CH10, 265 .i = SRAM_CH10,
268 .name = "VID Upstream J", 266 .name = "VID Upstream J",
269 .cmds_start = VID_J_UP_CMDS, 267 .cmds_start = VID_J_UP_CMDS,
270 .ctrl_start = VID_J_IQ, 268 .ctrl_start = VID_J_IQ,
271 .cdt = VID_J_CDT, 269 .cdt = VID_J_CDT,
272 .fifo_start = VID_J_UP_CLUSTER_1, 270 .fifo_start = VID_J_UP_CLUSTER_1,
273 .fifo_size = (VID_CLUSTER_SIZE<<2), 271 .fifo_size = (VID_CLUSTER_SIZE << 2),
274 .ptr1_reg = DMA16_PTR1, 272 .ptr1_reg = DMA16_PTR1,
275 .ptr2_reg = DMA16_PTR2, 273 .ptr2_reg = DMA16_PTR2,
276 .cnt1_reg = DMA16_CNT1, 274 .cnt1_reg = DMA16_CNT1,
277 .cnt2_reg = DMA16_CNT2, 275 .cnt2_reg = DMA16_CNT2,
278 .int_msk = VID_J_INT_MSK, 276 .int_msk = VID_J_INT_MSK,
279 .int_stat = VID_J_INT_STAT, 277 .int_stat = VID_J_INT_STAT,
280 .int_mstat = VID_J_INT_MSTAT, 278 .int_mstat = VID_J_INT_MSTAT,
281 .dma_ctl = VID_SRC_J_DMA_CTL, 279 .dma_ctl = VID_SRC_J_DMA_CTL,
282 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL, 280 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
283 .gpcnt = VID_SRC_J_GPCNT, 281 .gpcnt = VID_SRC_J_GPCNT,
284 282
285 .vid_fmt_ctl = VID_SRC_J_FMT_CTL, 283 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
286 .vid_active_ctl1= VID_SRC_J_ACTIVE_CTL1, 284 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
287 .vid_active_ctl2= VID_SRC_J_ACTIVE_CTL2, 285 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
288 .vid_cdt_size = VID_SRC_J_CDT_SZ, 286 .vid_cdt_size = VID_SRC_J_CDT_SZ,
289 .irq_bit = 9, 287 .irq_bit = 9,
290 }, 288 },
291 289
292 290 [SRAM_CH11] = {
293 [SRAM_CH11] = { 291 .i = SRAM_CH11,
294 .i = SRAM_CH11, 292 .name = "Audio Upstream Channel B",
295 .name = "Audio Upstream Channel B", 293 .cmds_start = AUD_B_UP_CMDS,
296 .cmds_start = AUD_B_UP_CMDS, 294 .ctrl_start = AUD_B_IQ,
297 .ctrl_start = AUD_B_IQ, 295 .cdt = AUD_B_CDT,
298 .cdt = AUD_B_CDT, 296 .fifo_start = AUD_B_UP_CLUSTER_1,
299 .fifo_start = AUD_B_UP_CLUSTER_1, 297 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
300 .fifo_size = (AUDIO_CLUSTER_SIZE*3), 298 .ptr1_reg = DMA22_PTR1,
301 .ptr1_reg = DMA22_PTR1, 299 .ptr2_reg = DMA22_PTR2,
302 .ptr2_reg = DMA22_PTR2, 300 .cnt1_reg = DMA22_CNT1,
303 .cnt1_reg = DMA22_CNT1, 301 .cnt2_reg = DMA22_CNT2,
304 .cnt2_reg = DMA22_CNT2, 302 .int_msk = AUD_B_INT_MSK,
305 .int_msk = AUD_B_INT_MSK, 303 .int_stat = AUD_B_INT_STAT,
306 .int_stat = AUD_B_INT_STAT, 304 .int_mstat = AUD_B_INT_MSTAT,
307 .int_mstat = AUD_B_INT_MSTAT, 305 .dma_ctl = AUD_INT_DMA_CTL,
308 .dma_ctl = AUD_INT_DMA_CTL, 306 .gpcnt_ctl = AUD_B_GPCNT_CTL,
309 .gpcnt_ctl = AUD_B_GPCNT_CTL, 307 .gpcnt = AUD_B_GPCNT,
310 .gpcnt = AUD_B_GPCNT, 308 .aud_length = AUD_B_LNGTH,
311 .aud_length = AUD_B_LNGTH, 309 .aud_cfg = AUD_B_CFG,
312 .aud_cfg = AUD_B_CFG, 310 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
313 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN, 311 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
314 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN, 312 .irq_bit = 11,
315 .irq_bit = 11, 313 },
316 },
317}; 314};
318 315
319
320struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00]; 316struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
321struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01]; 317struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
322struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02]; 318struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
@@ -333,1221 +329,1212 @@ struct cx25821_dmaqueue mpegq;
333 329
334static int cx25821_risc_decode(u32 risc) 330static int cx25821_risc_decode(u32 risc)
335{ 331{
336 static char *instr[16] = { 332 static char *instr[16] = {
337 [RISC_SYNC >> 28] = "sync", 333 [RISC_SYNC >> 28] = "sync",
338 [RISC_WRITE >> 28] = "write", 334 [RISC_WRITE >> 28] = "write",
339 [RISC_WRITEC >> 28] = "writec", 335 [RISC_WRITEC >> 28] = "writec",
340 [RISC_READ >> 28] = "read", 336 [RISC_READ >> 28] = "read",
341 [RISC_READC >> 28] = "readc", 337 [RISC_READC >> 28] = "readc",
342 [RISC_JUMP >> 28] = "jump", 338 [RISC_JUMP >> 28] = "jump",
343 [RISC_SKIP >> 28] = "skip", 339 [RISC_SKIP >> 28] = "skip",
344 [RISC_WRITERM >> 28] = "writerm", 340 [RISC_WRITERM >> 28] = "writerm",
345 [RISC_WRITECM >> 28] = "writecm", 341 [RISC_WRITECM >> 28] = "writecm",
346 [RISC_WRITECR >> 28] = "writecr", 342 [RISC_WRITECR >> 28] = "writecr",
347 }; 343 };
348 static int incr[16] = { 344 static int incr[16] = {
349 [RISC_WRITE >> 28] = 3, 345 [RISC_WRITE >> 28] = 3,
350 [RISC_JUMP >> 28] = 3, 346 [RISC_JUMP >> 28] = 3,
351 [RISC_SKIP >> 28] = 1, 347 [RISC_SKIP >> 28] = 1,
352 [RISC_SYNC >> 28] = 1, 348 [RISC_SYNC >> 28] = 1,
353 [RISC_WRITERM >> 28] = 3, 349 [RISC_WRITERM >> 28] = 3,
354 [RISC_WRITECM >> 28] = 3, 350 [RISC_WRITECM >> 28] = 3,
355 [RISC_WRITECR >> 28] = 4, 351 [RISC_WRITECR >> 28] = 4,
356 }; 352 };
357 static char *bits[] = { 353 static char *bits[] = {
358 "12", "13", "14", "resync", 354 "12", "13", "14", "resync",
359 "cnt0", "cnt1", "18", "19", 355 "cnt0", "cnt1", "18", "19",
360 "20", "21", "22", "23", 356 "20", "21", "22", "23",
361 "irq1", "irq2", "eol", "sol", 357 "irq1", "irq2", "eol", "sol",
362 }; 358 };
363 int i; 359 int i;
364 360
365 printk("0x%08x [ %s", risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); 361 printk("0x%08x [ %s", risc,
366 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) 362 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
367 { 363 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
368 if (risc & (1 << (i + 12))) 364 if (risc & (1 << (i + 12)))
369 printk(" %s", bits[i]); 365 printk(" %s", bits[i]);
370 } 366 }
371 printk(" count=%d ]\n", risc & 0xfff); 367 printk(" count=%d ]\n", risc & 0xfff);
372 return incr[risc >> 28] ? incr[risc >> 28] : 1; 368 return incr[risc >> 28] ? incr[risc >> 28] : 1;
373} 369}
374 370
375static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) 371static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
376{ 372{
377 struct cx25821_i2c *bus = i2c_adap->algo_data; 373 struct cx25821_i2c *bus = i2c_adap->algo_data;
378 struct cx25821_dev *dev = bus->dev; 374 struct cx25821_dev *dev = bus->dev;
379 return cx_read(bus->reg_stat) & 0x01; 375 return cx_read(bus->reg_stat) & 0x01;
380} 376}
381 377
382 378void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string)
383void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char* reg_string)
384{ 379{
385 int tmp = 0; 380 int tmp = 0;
386 u32 value = 0; 381 u32 value = 0;
387 382
388 value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp); 383 value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp);
389} 384}
390 385
391static void cx25821_registers_init(struct cx25821_dev *dev) 386static void cx25821_registers_init(struct cx25821_dev *dev)
392{ 387{
393 u32 tmp; 388 u32 tmp;
394 389
395 // enable RUN_RISC in Pecos 390 // enable RUN_RISC in Pecos
396 cx_write( DEV_CNTRL2, 0x20 ); 391 cx_write(DEV_CNTRL2, 0x20);
397 392
398 // Set the master PCI interrupt masks to enable video, audio, MBIF, and GPIO interrupts 393 // Set the master PCI interrupt masks to enable video, audio, MBIF, and GPIO interrupts
399 // I2C interrupt masking is handled by the I2C objects themselves. 394 // I2C interrupt masking is handled by the I2C objects themselves.
400 cx_write( PCI_INT_MSK, 0x2001FFFF ); 395 cx_write(PCI_INT_MSK, 0x2001FFFF);
401 396
402 tmp = cx_read( RDR_TLCTL0 ); 397 tmp = cx_read(RDR_TLCTL0);
403 tmp &= ~FLD_CFG_RCB_CK_EN; // Clear the RCB_CK_EN bit 398 tmp &= ~FLD_CFG_RCB_CK_EN; // Clear the RCB_CK_EN bit
404 cx_write( RDR_TLCTL0, tmp); 399 cx_write(RDR_TLCTL0, tmp);
405 400
406 // PLL-A setting for the Audio Master Clock 401 // PLL-A setting for the Audio Master Clock
407 cx_write( PLL_A_INT_FRAC, 0x9807A58B ); 402 cx_write(PLL_A_INT_FRAC, 0x9807A58B);
408 403
409 // PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 404 // PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1
410 cx_write( PLL_A_POST_STAT_BIST, 0x8000019C); 405 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
411 406
412 // clear reset bit [31] 407 // clear reset bit [31]
413 tmp = cx_read( PLL_A_INT_FRAC ); 408 tmp = cx_read(PLL_A_INT_FRAC);
414 cx_write( PLL_A_INT_FRAC, tmp & 0x7FFFFFFF); 409 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
415 410
416 // PLL-B setting for Mobilygen Host Bus Interface 411 // PLL-B setting for Mobilygen Host Bus Interface
417 cx_write( PLL_B_INT_FRAC, 0x9883A86F); 412 cx_write(PLL_B_INT_FRAC, 0x9883A86F);
418 413
419 // PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 414 // PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0
420 cx_write( PLL_B_POST_STAT_BIST, 0x8000018D); 415 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
421 416
422 // clear reset bit [31] 417 // clear reset bit [31]
423 tmp = cx_read( PLL_B_INT_FRAC ); 418 tmp = cx_read(PLL_B_INT_FRAC);
424 cx_write( PLL_B_INT_FRAC, tmp & 0x7FFFFFFF); 419 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
425 420
426 // PLL-C setting for video upstream channel 421 // PLL-C setting for video upstream channel
427 cx_write( PLL_C_INT_FRAC, 0x96A0EA3F); 422 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
428 423
429 // PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 424 // PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0
430 cx_write( PLL_C_POST_STAT_BIST, 0x80000103); 425 cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
431 426
432 // clear reset bit [31] 427 // clear reset bit [31]
433 tmp = cx_read( PLL_C_INT_FRAC ); 428 tmp = cx_read(PLL_C_INT_FRAC);
434 cx_write( PLL_C_INT_FRAC, tmp & 0x7FFFFFFF); 429 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
435 430
436 // PLL-D setting for audio upstream channel 431 // PLL-D setting for audio upstream channel
437 cx_write( PLL_D_INT_FRAC, 0x98757F5B); 432 cx_write(PLL_D_INT_FRAC, 0x98757F5B);
438 433
439 // PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 434 // PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0
440 cx_write( PLL_D_POST_STAT_BIST, 0x80000113); 435 cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
441 436
442 // clear reset bit [31] 437 // clear reset bit [31]
443 tmp = cx_read( PLL_D_INT_FRAC ); 438 tmp = cx_read(PLL_D_INT_FRAC);
444 cx_write( PLL_D_INT_FRAC, tmp & 0x7FFFFFFF); 439 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
445 440
441 // This selects the PLL C clock source for the video upstream channel I and J
442 tmp = cx_read(VID_CH_CLK_SEL);
443 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
446 444
447 // This selects the PLL C clock source for the video upstream channel I and J 445 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
448 tmp = cx_read( VID_CH_CLK_SEL ); 446 //select 656/VIP DST for downstream Channel A - C
449 cx_write( VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000); 447 tmp = cx_read(VID_CH_MODE_SEL);
448 //cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF);
449 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
450 450
451 // enables 656 port I and J as output
452 tmp = cx_read(CLK_RST);
453 tmp |= FLD_USE_ALT_PLL_REF; // use external ALT_PLL_REF pin as its reference clock instead
454 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
451 455
452 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C 456 mdelay(100);
453 //select 656/VIP DST for downstream Channel A - C 457}
454 tmp = cx_read( VID_CH_MODE_SEL );
455 //cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF);
456 cx_write( VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
457 458
459int cx25821_sram_channel_setup(struct cx25821_dev *dev,
460 struct sram_channel *ch,
461 unsigned int bpl, u32 risc)
462{
463 unsigned int i, lines;
464 u32 cdt;
465
466 if (ch->cmds_start == 0) {
467 cx_write(ch->ptr1_reg, 0);
468 cx_write(ch->ptr2_reg, 0);
469 cx_write(ch->cnt2_reg, 0);
470 cx_write(ch->cnt1_reg, 0);
471 return 0;
472 }
458 473
459 // enables 656 port I and J as output 474 bpl = (bpl + 7) & ~7; /* alignment */
460 tmp = cx_read( CLK_RST ); 475 cdt = ch->cdt;
461 tmp |= FLD_USE_ALT_PLL_REF; // use external ALT_PLL_REF pin as its reference clock instead 476 lines = ch->fifo_size / bpl;
462 cx_write( CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE) );
463 477
464 mdelay(100); 478 if (lines > 4) {
465} 479 lines = 4;
480 }
466 481
482 BUG_ON(lines < 2);
483
484 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
485 cx_write(8 + 4, 8);
486 cx_write(8 + 8, 0);
487
488 /* write CDT */
489 for (i = 0; i < lines; i++) {
490 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
491 cx_write(cdt + 16 * i + 4, 0);
492 cx_write(cdt + 16 * i + 8, 0);
493 cx_write(cdt + 16 * i + 12, 0);
494 }
495
496 //init the first cdt buffer
497 for (i = 0; i < 128; i++)
498 cx_write(ch->fifo_start + 4 * i, i);
499
500 /* write CMDS */
501 if (ch->jumponly) {
502 cx_write(ch->cmds_start + 0, 8);
503 } else {
504 cx_write(ch->cmds_start + 0, risc);
505 }
506
507 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
508 cx_write(ch->cmds_start + 8, cdt);
509 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
510 cx_write(ch->cmds_start + 16, ch->ctrl_start);
511
512 if (ch->jumponly)
513 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
514 else
515 cx_write(ch->cmds_start + 20, 64 >> 2);
516
517 for (i = 24; i < 80; i += 4)
518 cx_write(ch->cmds_start + i, 0);
519
520 /* fill registers */
521 cx_write(ch->ptr1_reg, ch->fifo_start);
522 cx_write(ch->ptr2_reg, cdt);
523 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
524 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
467 525
468int cx25821_sram_channel_setup(struct cx25821_dev *dev,
469 struct sram_channel *ch,
470 unsigned int bpl, u32 risc)
471{
472 unsigned int i, lines;
473 u32 cdt;
474
475 if (ch->cmds_start == 0) {
476 cx_write(ch->ptr1_reg, 0);
477 cx_write(ch->ptr2_reg, 0);
478 cx_write(ch->cnt2_reg, 0);
479 cx_write(ch->cnt1_reg, 0);
480 return 0; 526 return 0;
481 }
482
483 bpl = (bpl + 7) & ~7; /* alignment */
484 cdt = ch->cdt;
485 lines = ch->fifo_size / bpl;
486
487 if (lines > 4)
488 {
489 lines = 4;
490 }
491
492 BUG_ON(lines < 2);
493
494 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
495 cx_write(8 + 4, 8);
496 cx_write(8 + 8, 0);
497
498 /* write CDT */
499 for (i = 0; i < lines; i++) {
500 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
501 cx_write(cdt + 16*i + 4, 0);
502 cx_write(cdt + 16*i + 8, 0);
503 cx_write(cdt + 16*i + 12, 0);
504 }
505
506 //init the first cdt buffer
507 for(i=0; i<128; i++)
508 cx_write(ch->fifo_start+4*i, i);
509
510 /* write CMDS */
511 if (ch->jumponly)
512 {
513 cx_write(ch->cmds_start + 0, 8);
514 }
515 else
516 {
517 cx_write(ch->cmds_start + 0, risc);
518 }
519
520 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
521 cx_write(ch->cmds_start + 8, cdt);
522 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
523 cx_write(ch->cmds_start + 16, ch->ctrl_start);
524
525 if (ch->jumponly)
526 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
527 else
528 cx_write(ch->cmds_start + 20, 64 >> 2);
529
530 for (i = 24; i < 80; i += 4)
531 cx_write(ch->cmds_start + i, 0);
532
533 /* fill registers */
534 cx_write(ch->ptr1_reg, ch->fifo_start);
535 cx_write(ch->ptr2_reg, cdt);
536 cx_write(ch->cnt2_reg, (lines*16) >> 3);
537 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
538
539 return 0;
540} 527}
541 528
542int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, 529int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
543 struct sram_channel *ch, 530 struct sram_channel *ch,
544 unsigned int bpl, u32 risc) 531 unsigned int bpl, u32 risc)
545{ 532{
546 unsigned int i, lines; 533 unsigned int i, lines;
547 u32 cdt; 534 u32 cdt;
535
536 if (ch->cmds_start == 0) {
537 cx_write(ch->ptr1_reg, 0);
538 cx_write(ch->ptr2_reg, 0);
539 cx_write(ch->cnt2_reg, 0);
540 cx_write(ch->cnt1_reg, 0);
541 return 0;
542 }
543
544 bpl = (bpl + 7) & ~7; /* alignment */
545 cdt = ch->cdt;
546 lines = ch->fifo_size / bpl;
547
548 if (lines > 3) {
549 lines = 3; //for AUDIO
550 }
548 551
552 BUG_ON(lines < 2);
553
554 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
555 cx_write(8 + 4, 8);
556 cx_write(8 + 8, 0);
557
558 /* write CDT */
559 for (i = 0; i < lines; i++) {
560 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
561 cx_write(cdt + 16 * i + 4, 0);
562 cx_write(cdt + 16 * i + 8, 0);
563 cx_write(cdt + 16 * i + 12, 0);
564 }
565
566 /* write CMDS */
567 if (ch->jumponly) {
568 cx_write(ch->cmds_start + 0, 8);
569 } else {
570 cx_write(ch->cmds_start + 0, risc);
571 }
572
573 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
574 cx_write(ch->cmds_start + 8, cdt);
575 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
576 cx_write(ch->cmds_start + 16, ch->ctrl_start);
577
578 //IQ size
579 if (ch->jumponly) {
580 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
581 } else {
582 cx_write(ch->cmds_start + 20, 64 >> 2);
583 }
584
585 //zero out
586 for (i = 24; i < 80; i += 4)
587 cx_write(ch->cmds_start + i, 0);
588
589 /* fill registers */
590 cx_write(ch->ptr1_reg, ch->fifo_start);
591 cx_write(ch->ptr2_reg, cdt);
592 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
593 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
549 594
550 if (ch->cmds_start == 0) {
551 cx_write(ch->ptr1_reg, 0);
552 cx_write(ch->ptr2_reg, 0);
553 cx_write(ch->cnt2_reg, 0);
554 cx_write(ch->cnt1_reg, 0);
555 return 0; 595 return 0;
556 }
557
558 bpl = (bpl + 7) & ~7; /* alignment */
559 cdt = ch->cdt;
560 lines = ch->fifo_size / bpl;
561
562 if (lines > 3)
563 {
564 lines = 3; //for AUDIO
565 }
566
567 BUG_ON(lines < 2);
568
569
570 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
571 cx_write(8 + 4, 8);
572 cx_write(8 + 8, 0);
573
574 /* write CDT */
575 for (i = 0; i < lines; i++) {
576 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
577 cx_write(cdt + 16*i + 4, 0);
578 cx_write(cdt + 16*i + 8, 0);
579 cx_write(cdt + 16*i + 12, 0);
580 }
581
582 /* write CMDS */
583 if (ch->jumponly)
584 {
585 cx_write(ch->cmds_start + 0, 8);
586 }
587 else
588 {
589 cx_write(ch->cmds_start + 0, risc);
590 }
591
592 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
593 cx_write(ch->cmds_start + 8, cdt);
594 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
595 cx_write(ch->cmds_start + 16, ch->ctrl_start);
596
597 //IQ size
598 if (ch->jumponly)
599 {
600 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
601 }
602 else
603 {
604 cx_write(ch->cmds_start + 20, 64 >> 2);
605 }
606
607 //zero out
608 for (i = 24; i < 80; i += 4)
609 cx_write(ch->cmds_start + i, 0);
610
611 /* fill registers */
612 cx_write(ch->ptr1_reg, ch->fifo_start);
613 cx_write(ch->ptr2_reg, cdt);
614 cx_write(ch->cnt2_reg, (lines*16) >> 3);
615 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
616
617 return 0;
618} 596}
619 597
620
621void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch) 598void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
622{ 599{
623 static char *name[] = { 600 static char *name[] = {
624 "init risc lo", 601 "init risc lo",
625 "init risc hi", 602 "init risc hi",
626 "cdt base", 603 "cdt base",
627 "cdt size", 604 "cdt size",
628 "iq base", 605 "iq base",
629 "iq size", 606 "iq size",
630 "risc pc lo", 607 "risc pc lo",
631 "risc pc hi", 608 "risc pc hi",
632 "iq wr ptr", 609 "iq wr ptr",
633 "iq rd ptr", 610 "iq rd ptr",
634 "cdt current", 611 "cdt current",
635 "pci target lo", 612 "pci target lo",
636 "pci target hi", 613 "pci target hi",
637 "line / byte", 614 "line / byte",
638 }; 615 };
639 u32 risc; 616 u32 risc;
640 unsigned int i, j, n; 617 unsigned int i, j, n;
641 618
642 printk(KERN_WARNING "%s: %s - dma channel status dump\n", dev->name, ch->name); 619 printk(KERN_WARNING "%s: %s - dma channel status dump\n", dev->name,
643 for (i = 0; i < ARRAY_SIZE(name); i++) 620 ch->name);
644 printk(KERN_WARNING "cmds + 0x%2x: %-15s: 0x%08x\n", i*4, name[i], 621 for (i = 0; i < ARRAY_SIZE(name); i++)
645 cx_read(ch->cmds_start + 4*i)); 622 printk(KERN_WARNING "cmds + 0x%2x: %-15s: 0x%08x\n", i * 4,
646 623 name[i], cx_read(ch->cmds_start + 4 * i));
647 j=i*4; 624
648 for (i = 0; i < 4; ) { 625 j = i * 4;
649 risc = cx_read(ch->cmds_start + 4 * (i + 14)); 626 for (i = 0; i < 4;) {
650 printk(KERN_WARNING "cmds + 0x%2x: risc%d: ", j+i*4, i); 627 risc = cx_read(ch->cmds_start + 4 * (i + 14));
651 i +=cx25821_risc_decode(risc); 628 printk(KERN_WARNING "cmds + 0x%2x: risc%d: ", j + i * 4, i);
652 } 629 i += cx25821_risc_decode(risc);
653 630 }
654 for (i = 0; i < (64 >> 2); i += n) { 631
655 risc = cx_read(ch->ctrl_start + 4 * i); 632 for (i = 0; i < (64 >> 2); i += n) {
656 /* No consideration for bits 63-32 */ 633 risc = cx_read(ch->ctrl_start + 4 * i);
657 634 /* No consideration for bits 63-32 */
658 printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i*4, ch->ctrl_start + 4 * i, i); 635
659 n = cx25821_risc_decode(risc); 636 printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i * 4,
660 for (j = 1; j < n; j++) { 637 ch->ctrl_start + 4 * i, i);
661 risc = cx_read(ch->ctrl_start + 4 * (i + j)); 638 n = cx25821_risc_decode(risc);
662 printk(KERN_WARNING "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", 4*(i+j), i+j, risc, j); 639 for (j = 1; j < n; j++) {
640 risc = cx_read(ch->ctrl_start + 4 * (i + j));
641 printk(KERN_WARNING
642 "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
643 4 * (i + j), i + j, risc, j);
644 }
663 } 645 }
664 } 646
665 647 printk(KERN_WARNING " : fifo: 0x%08x -> 0x%x\n",
666 printk(KERN_WARNING " : fifo: 0x%08x -> 0x%x\n", ch->fifo_start, ch->fifo_start+ch->fifo_size); 648 ch->fifo_start, ch->fifo_start + ch->fifo_size);
667 printk(KERN_WARNING " : ctrl: 0x%08x -> 0x%x\n", ch->ctrl_start, ch->ctrl_start + 6*16); 649 printk(KERN_WARNING " : ctrl: 0x%08x -> 0x%x\n",
668 printk(KERN_WARNING " : ptr1_reg: 0x%08x\n", cx_read(ch->ptr1_reg)); 650 ch->ctrl_start, ch->ctrl_start + 6 * 16);
669 printk(KERN_WARNING " : ptr2_reg: 0x%08x\n", cx_read(ch->ptr2_reg)); 651 printk(KERN_WARNING " : ptr1_reg: 0x%08x\n",
670 printk(KERN_WARNING " : cnt1_reg: 0x%08x\n", cx_read(ch->cnt1_reg)); 652 cx_read(ch->ptr1_reg));
671 printk(KERN_WARNING " : cnt2_reg: 0x%08x\n", cx_read(ch->cnt2_reg)); 653 printk(KERN_WARNING " : ptr2_reg: 0x%08x\n",
654 cx_read(ch->ptr2_reg));
655 printk(KERN_WARNING " : cnt1_reg: 0x%08x\n",
656 cx_read(ch->cnt1_reg));
657 printk(KERN_WARNING " : cnt2_reg: 0x%08x\n",
658 cx_read(ch->cnt2_reg));
672} 659}
673 660
674void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, struct sram_channel *ch) 661void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
662 struct sram_channel *ch)
675{ 663{
676 static char *name[] = { 664 static char *name[] = {
677 "init risc lo", 665 "init risc lo",
678 "init risc hi", 666 "init risc hi",
679 "cdt base", 667 "cdt base",
680 "cdt size", 668 "cdt size",
681 "iq base", 669 "iq base",
682 "iq size", 670 "iq size",
683 "risc pc lo", 671 "risc pc lo",
684 "risc pc hi", 672 "risc pc hi",
685 "iq wr ptr", 673 "iq wr ptr",
686 "iq rd ptr", 674 "iq rd ptr",
687 "cdt current", 675 "cdt current",
688 "pci target lo", 676 "pci target lo",
689 "pci target hi", 677 "pci target hi",
690 "line / byte", 678 "line / byte",
691 }; 679 };
692 680
693 u32 risc, value, tmp; 681 u32 risc, value, tmp;
694 unsigned int i, j, n; 682 unsigned int i, j, n;
695 683
684 printk(KERN_INFO "\n%s: %s - dma Audio channel status dump\n",
685 dev->name, ch->name);
696 686
697 printk(KERN_INFO "\n%s: %s - dma Audio channel status dump\n", dev->name, ch->name); 687 for (i = 0; i < ARRAY_SIZE(name); i++)
688 printk(KERN_INFO "%s: cmds + 0x%2x: %-15s: 0x%08x\n",
689 dev->name, i * 4, name[i],
690 cx_read(ch->cmds_start + 4 * i));
698 691
699 for (i = 0; i < ARRAY_SIZE(name); i++) 692 j = i * 4;
700 printk(KERN_INFO "%s: cmds + 0x%2x: %-15s: 0x%08x\n", dev->name, i*4, name[i], cx_read(ch->cmds_start + 4*i)); 693 for (i = 0; i < 4;) {
694 risc = cx_read(ch->cmds_start + 4 * (i + 14));
695 printk(KERN_WARNING "cmds + 0x%2x: risc%d: ", j + i * 4, i);
696 i += cx25821_risc_decode(risc);
697 }
701 698
699 for (i = 0; i < (64 >> 2); i += n) {
700 risc = cx_read(ch->ctrl_start + 4 * i);
701 /* No consideration for bits 63-32 */
702 702
703 j=i*4; 703 printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i * 4,
704 for (i = 0; i < 4; ) { 704 ch->ctrl_start + 4 * i, i);
705 risc = cx_read(ch->cmds_start + 4 * (i + 14)); 705 n = cx25821_risc_decode(risc);
706 printk(KERN_WARNING "cmds + 0x%2x: risc%d: ", j+i*4, i);
707 i += cx25821_risc_decode(risc);
708 }
709 706
710 for (i = 0; i < (64 >> 2); i += n) { 707 for (j = 1; j < n; j++) {
711 risc = cx_read(ch->ctrl_start + 4 * i); 708 risc = cx_read(ch->ctrl_start + 4 * (i + j));
712 /* No consideration for bits 63-32 */ 709 printk(KERN_WARNING
710 "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
711 4 * (i + j), i + j, risc, j);
712 }
713 }
713 714
714 printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i*4, ch->ctrl_start + 4 * i, i); 715 printk(KERN_WARNING " : fifo: 0x%08x -> 0x%x\n",
715 n = cx25821_risc_decode(risc); 716 ch->fifo_start, ch->fifo_start + ch->fifo_size);
717 printk(KERN_WARNING " : ctrl: 0x%08x -> 0x%x\n",
718 ch->ctrl_start, ch->ctrl_start + 6 * 16);
719 printk(KERN_WARNING " : ptr1_reg: 0x%08x\n",
720 cx_read(ch->ptr1_reg));
721 printk(KERN_WARNING " : ptr2_reg: 0x%08x\n",
722 cx_read(ch->ptr2_reg));
723 printk(KERN_WARNING " : cnt1_reg: 0x%08x\n",
724 cx_read(ch->cnt1_reg));
725 printk(KERN_WARNING " : cnt2_reg: 0x%08x\n",
726 cx_read(ch->cnt2_reg));
727
728 for (i = 0; i < 4; i++) {
729 risc = cx_read(ch->cmds_start + 56 + (i * 4));
730 printk(KERN_WARNING "instruction %d = 0x%x\n", i, risc);
731 }
716 732
717 for (j = 1; j < n; j++) { 733 //read data from the first cdt buffer
718 risc = cx_read(ch->ctrl_start + 4 * (i + j)); 734 risc = cx_read(AUD_A_CDT);
719 printk(KERN_WARNING "ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", 4*(i+j), i+j, risc, j); 735 printk(KERN_WARNING "\nread cdt loc=0x%x\n", risc);
736 for (i = 0; i < 8; i++) {
737 n = cx_read(risc + i * 4);
738 printk(KERN_WARNING "0x%x ", n);
720 } 739 }
721 } 740 printk(KERN_WARNING "\n\n");
722 741
723 printk(KERN_WARNING " : fifo: 0x%08x -> 0x%x\n", ch->fifo_start, ch->fifo_start+ch->fifo_size); 742 value = cx_read(CLK_RST);
724 printk(KERN_WARNING " : ctrl: 0x%08x -> 0x%x\n", ch->ctrl_start, ch->ctrl_start + 6*16); 743 CX25821_INFO(" CLK_RST = 0x%x \n\n", value);
725 printk(KERN_WARNING " : ptr1_reg: 0x%08x\n", cx_read(ch->ptr1_reg)); 744
726 printk(KERN_WARNING " : ptr2_reg: 0x%08x\n", cx_read(ch->ptr2_reg)); 745 value = cx_read(PLL_A_POST_STAT_BIST);
727 printk(KERN_WARNING " : cnt1_reg: 0x%08x\n", cx_read(ch->cnt1_reg)); 746 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x \n\n", value);
728 printk(KERN_WARNING " : cnt2_reg: 0x%08x\n", cx_read(ch->cnt2_reg)); 747 value = cx_read(PLL_A_INT_FRAC);
729 748 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x \n\n", value);
730 for( i=0; i < 4; i++) 749
731 { 750 value = cx_read(PLL_B_POST_STAT_BIST);
732 risc = cx_read(ch->cmds_start + 56 + (i*4)); 751 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x \n\n", value);
733 printk(KERN_WARNING "instruction %d = 0x%x\n", i, risc); 752 value = cx_read(PLL_B_INT_FRAC);
734 } 753 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x \n\n", value);
735 754
736 //read data from the first cdt buffer 755 value = cx_read(PLL_C_POST_STAT_BIST);
737 risc = cx_read(AUD_A_CDT); 756 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x \n\n", value);
738 printk(KERN_WARNING "\nread cdt loc=0x%x\n", risc); 757 value = cx_read(PLL_C_INT_FRAC);
739 for(i=0; i<8; i++) 758 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x \n\n", value);
740 { 759
741 n = cx_read(risc+i*4); 760 value = cx_read(PLL_D_POST_STAT_BIST);
742 printk(KERN_WARNING "0x%x ", n); 761 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x \n\n", value);
743 } 762 value = cx_read(PLL_D_INT_FRAC);
744 printk(KERN_WARNING "\n\n"); 763 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x \n\n", value);
745 764
746 765 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
747 value = cx_read(CLK_RST); 766 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x \n\n", value);
748 CX25821_INFO(" CLK_RST = 0x%x \n\n", value);
749
750 value = cx_read(PLL_A_POST_STAT_BIST);
751 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x \n\n", value);
752 value = cx_read(PLL_A_INT_FRAC);
753 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x \n\n", value);
754
755 value = cx_read(PLL_B_POST_STAT_BIST);
756 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x \n\n", value);
757 value = cx_read(PLL_B_INT_FRAC);
758 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x \n\n", value);
759
760 value = cx_read(PLL_C_POST_STAT_BIST);
761 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x \n\n", value);
762 value = cx_read(PLL_C_INT_FRAC);
763 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x \n\n", value);
764
765 value = cx_read(PLL_D_POST_STAT_BIST);
766 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x \n\n", value);
767 value = cx_read(PLL_D_INT_FRAC);
768 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x \n\n", value);
769
770 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
771 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x \n\n", value);
772} 767}
773 768
774static void cx25821_shutdown(struct cx25821_dev *dev) 769static void cx25821_shutdown(struct cx25821_dev *dev)
775{ 770{
776 int i; 771 int i;
777 772
778 /* disable RISC controller */ 773 /* disable RISC controller */
779 cx_write(DEV_CNTRL2, 0); 774 cx_write(DEV_CNTRL2, 0);
780 775
781 /* Disable Video A/B activity */ 776 /* Disable Video A/B activity */
782 for(i=0; i<VID_CHANNEL_NUM; i++) 777 for (i = 0; i < VID_CHANNEL_NUM; i++) {
783 { 778 cx_write(dev->sram_channels[i].dma_ctl, 0);
784 cx_write(dev->sram_channels[i].dma_ctl, 0); 779 cx_write(dev->sram_channels[i].int_msk, 0);
785 cx_write(dev->sram_channels[i].int_msk, 0); 780 }
786 }
787 781
788 for( i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) 782 for (i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= VID_UPSTREAM_SRAM_CHANNEL_J;
789 { 783 i++) {
790 cx_write(dev->sram_channels[i].dma_ctl, 0); 784 cx_write(dev->sram_channels[i].dma_ctl, 0);
791 cx_write(dev->sram_channels[i].int_msk, 0); 785 cx_write(dev->sram_channels[i].int_msk, 0);
792 } 786 }
793 787
794 /* Disable Audio activity */ 788 /* Disable Audio activity */
795 cx_write(AUD_INT_DMA_CTL, 0); 789 cx_write(AUD_INT_DMA_CTL, 0);
796 790
797 /* Disable Serial port */ 791 /* Disable Serial port */
798 cx_write(UART_CTL, 0); 792 cx_write(UART_CTL, 0);
799 793
800 /* Disable Interrupts */ 794 /* Disable Interrupts */
801 cx_write(PCI_INT_MSK, 0); 795 cx_write(PCI_INT_MSK, 0);
802 cx_write(AUD_A_INT_MSK, 0); 796 cx_write(AUD_A_INT_MSK, 0);
803} 797}
804 798
805void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select, u32 format) 799void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
800 u32 format)
806{ 801{
807 struct sram_channel *ch; 802 struct sram_channel *ch;
808 803
809 if( channel_select <= 7 && channel_select >= 0 ) 804 if (channel_select <= 7 && channel_select >= 0) {
810 { 805 ch = &cx25821_sram_channels[channel_select];
811 ch = &cx25821_sram_channels[channel_select]; 806 cx_write(ch->pix_frmt, format);
812 cx_write(ch->pix_frmt, format); 807 dev->pixel_formats[channel_select] = format;
813 dev->pixel_formats[channel_select] = format; 808 }
814 }
815} 809}
816 810
817static void cx25821_set_vip_mode(struct cx25821_dev *dev, struct sram_channel *ch) 811static void cx25821_set_vip_mode(struct cx25821_dev *dev,
812 struct sram_channel *ch)
818{ 813{
819 cx_write(ch->pix_frmt, PIXEL_FRMT_422); 814 cx_write(ch->pix_frmt, PIXEL_FRMT_422);
820 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1); 815 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
821} 816}
822 817
823static void cx25821_initialize(struct cx25821_dev *dev) 818static void cx25821_initialize(struct cx25821_dev *dev)
824{ 819{
825 int i; 820 int i;
826
827 dprintk(1, "%s()\n", __func__);
828 821
829 cx25821_shutdown(dev); 822 dprintk(1, "%s()\n", __func__);
830 cx_write(PCI_INT_STAT, 0xffffffff);
831 823
832 for(i=0; i<VID_CHANNEL_NUM; i++) 824 cx25821_shutdown(dev);
833 cx_write(dev->sram_channels[i].int_stat, 0xffffffff); 825 cx_write(PCI_INT_STAT, 0xffffffff);
834 826
827 for (i = 0; i < VID_CHANNEL_NUM; i++)
828 cx_write(dev->sram_channels[i].int_stat, 0xffffffff);
835 829
836 cx_write(AUD_A_INT_STAT, 0xffffffff); 830 cx_write(AUD_A_INT_STAT, 0xffffffff);
837 cx_write(AUD_B_INT_STAT, 0xffffffff); 831 cx_write(AUD_B_INT_STAT, 0xffffffff);
838 cx_write(AUD_C_INT_STAT, 0xffffffff); 832 cx_write(AUD_C_INT_STAT, 0xffffffff);
839 cx_write(AUD_D_INT_STAT, 0xffffffff); 833 cx_write(AUD_D_INT_STAT, 0xffffffff);
840 cx_write(AUD_E_INT_STAT, 0xffffffff); 834 cx_write(AUD_E_INT_STAT, 0xffffffff);
841 835
842 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000); 836 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
843 cx_write(PAD_CTRL, 0x12); //for I2C 837 cx_write(PAD_CTRL, 0x12); //for I2C
844 cx25821_registers_init(dev); //init Pecos registers 838 cx25821_registers_init(dev); //init Pecos registers
845 mdelay(100); 839 mdelay(100);
846 840
841 for (i = 0; i < VID_CHANNEL_NUM; i++) {
842 cx25821_set_vip_mode(dev, &dev->sram_channels[i]);
843 cx25821_sram_channel_setup(dev, &dev->sram_channels[i], 1440,
844 0);
845 dev->pixel_formats[i] = PIXEL_FRMT_422;
846 dev->use_cif_resolution[i] = FALSE;
847 }
847 848
848 for(i=0; i<VID_CHANNEL_NUM; i++) 849 //Probably only affect Downstream
849 { 850 for (i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= VID_UPSTREAM_SRAM_CHANNEL_J;
850 cx25821_set_vip_mode(dev, &dev->sram_channels[i]); 851 i++) {
851 cx25821_sram_channel_setup(dev, &dev->sram_channels[i], 1440, 0); 852 cx25821_set_vip_mode(dev, &dev->sram_channels[i]);
852 dev->pixel_formats[i] = PIXEL_FRMT_422; 853 }
853 dev->use_cif_resolution[i] = FALSE;
854 }
855
856 //Probably only affect Downstream
857 for( i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++)
858 {
859 cx25821_set_vip_mode(dev, &dev->sram_channels[i]);
860 }
861 854
862 cx25821_sram_channel_setup_audio(dev, &dev->sram_channels[SRAM_CH08], 128, 0); 855 cx25821_sram_channel_setup_audio(dev, &dev->sram_channels[SRAM_CH08],
856 128, 0);
863 857
864 cx25821_gpio_init(dev); 858 cx25821_gpio_init(dev);
865} 859}
866 860
867static int get_resources(struct cx25821_dev *dev) 861static int get_resources(struct cx25821_dev *dev)
868{ 862{
869 if (request_mem_region(pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0), dev->name)) 863 if (request_mem_region
870 return 0; 864 (pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0),
865 dev->name))
866 return 0;
871 867
872 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n", 868 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
873 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0)); 869 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
874 870
875 return -EBUSY; 871 return -EBUSY;
876} 872}
877 873
878
879static void cx25821_dev_checkrevision(struct cx25821_dev *dev) 874static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
880{ 875{
881 dev->hwrevision = cx_read(RDR_CFG2) & 0xff; 876 dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
882 877
883 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n", __func__, dev->hwrevision); 878 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n", __func__,
879 dev->hwrevision);
884} 880}
885 881
886static void cx25821_iounmap(struct cx25821_dev *dev) 882static void cx25821_iounmap(struct cx25821_dev *dev)
887{ 883{
888 if (dev == NULL) 884 if (dev == NULL)
889 return; 885 return;
890 886
891 /* Releasing IO memory */ 887 /* Releasing IO memory */
892 if (dev->lmmio != NULL) 888 if (dev->lmmio != NULL) {
893 { 889 CX25821_INFO("Releasing lmmio.\n");
894 CX25821_INFO("Releasing lmmio.\n"); 890 iounmap(dev->lmmio);
895 iounmap(dev->lmmio); 891 dev->lmmio = NULL;
896 dev->lmmio = NULL; 892 }
897 }
898} 893}
899 894
900
901static int cx25821_dev_setup(struct cx25821_dev *dev) 895static int cx25821_dev_setup(struct cx25821_dev *dev)
902{ 896{
903 int io_size = 0, i; 897 int io_size = 0, i;
904 898
905 struct video_device *video_template[] = { 899 struct video_device *video_template[] = {
906 &cx25821_video_template0, 900 &cx25821_video_template0,
907 &cx25821_video_template1, 901 &cx25821_video_template1,
908 &cx25821_video_template2, 902 &cx25821_video_template2,
909 &cx25821_video_template3, 903 &cx25821_video_template3,
910 &cx25821_video_template4, 904 &cx25821_video_template4,
911 &cx25821_video_template5, 905 &cx25821_video_template5,
912 &cx25821_video_template6, 906 &cx25821_video_template6,
913 &cx25821_video_template7, 907 &cx25821_video_template7,
914 &cx25821_video_template9, 908 &cx25821_video_template9,
915 &cx25821_video_template10, 909 &cx25821_video_template10,
916 &cx25821_video_template11, 910 &cx25821_video_template11,
917 &cx25821_videoioctl_template, 911 &cx25821_videoioctl_template,
918 }; 912 };
919 913
920 printk(KERN_INFO "\n***********************************\n"); 914 printk(KERN_INFO "\n***********************************\n");
921 printk(KERN_INFO "cx25821 set up\n"); 915 printk(KERN_INFO "cx25821 set up\n");
922 printk(KERN_INFO "***********************************\n\n"); 916 printk(KERN_INFO "***********************************\n\n");
923 917
924 mutex_init(&dev->lock); 918 mutex_init(&dev->lock);
925 919
926 atomic_inc(&dev->refcount); 920 atomic_inc(&dev->refcount);
927 921
928 dev->nr = ++cx25821_devcount; 922 dev->nr = ++cx25821_devcount;
929 sprintf(dev->name, "cx25821[%d]", dev->nr); 923 sprintf(dev->name, "cx25821[%d]", dev->nr);
930 924
931 mutex_lock(&devlist); 925 mutex_lock(&devlist);
932 list_add_tail(&dev->devlist, &cx25821_devlist); 926 list_add_tail(&dev->devlist, &cx25821_devlist);
933 mutex_unlock(&devlist); 927 mutex_unlock(&devlist);
934 928
935 strcpy(cx25821_boards[UNKNOWN_BOARD].name, "unknown"); 929 strcpy(cx25821_boards[UNKNOWN_BOARD].name, "unknown");
936 strcpy(cx25821_boards[CX25821_BOARD].name, "cx25821"); 930 strcpy(cx25821_boards[CX25821_BOARD].name, "cx25821");
937 931
938 932 if (dev->pci->device != 0x8210) {
939 if( dev->pci->device != 0x8210 ) 933 printk(KERN_INFO
940 { 934 "%s() Exiting. Incorrect Hardware device = 0x%02x\n",
941 printk(KERN_INFO "%s() Exiting. Incorrect Hardware device = 0x%02x\n", 935 __func__, dev->pci->device);
942 __func__, dev->pci->device); 936 return -1;
943 return -1; 937 } else {
944 } 938 printk(KERN_INFO "Athena Hardware device = 0x%02x\n",
945 else 939 dev->pci->device);
946 { 940 }
947 printk(KERN_INFO "Athena Hardware device = 0x%02x\n", dev->pci->device);
948 }
949
950 /* Apply a sensible clock frequency for the PCIe bridge */
951 dev->clk_freq = 28000000;
952 dev->sram_channels = cx25821_sram_channels;
953
954 if(dev->nr > 1)
955 {
956 CX25821_INFO("dev->nr > 1!");
957 }
958
959 /* board config */
960 dev->board = 1; //card[dev->nr];
961 dev->_max_num_decoders = MAX_DECODERS;
962
963
964 dev->pci_bus = dev->pci->bus->number;
965 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
966 dev->pci_irqmask = 0x001f00;
967
968 /* External Master 1 Bus */
969 dev->i2c_bus[0].nr = 0;
970 dev->i2c_bus[0].dev = dev;
971 dev->i2c_bus[0].reg_stat = I2C1_STAT;
972 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
973 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
974 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
975 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
976 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */
977
978
979
980 if (get_resources(dev) < 0)
981 {
982 printk(KERN_ERR "%s No more PCIe resources for "
983 "subsystem: %04x:%04x\n",
984 dev->name, dev->pci->subsystem_vendor,
985 dev->pci->subsystem_device);
986 941
987 cx25821_devcount--; 942 /* Apply a sensible clock frequency for the PCIe bridge */
988 return -ENODEV; 943 dev->clk_freq = 28000000;
989 } 944 dev->sram_channels = cx25821_sram_channels;
990 945
991 /* PCIe stuff */ 946 if (dev->nr > 1) {
992 dev->base_io_addr = pci_resource_start(dev->pci, 0); 947 CX25821_INFO("dev->nr > 1!");
993 io_size = pci_resource_len(dev->pci, 0); 948 }
994 949
995 if (!dev->base_io_addr) { 950 /* board config */
996 CX25821_ERR("No PCI Memory resources, exiting!\n"); 951 dev->board = 1; //card[dev->nr];
997 return -ENODEV; 952 dev->_max_num_decoders = MAX_DECODERS;
998 } 953
954 dev->pci_bus = dev->pci->bus->number;
955 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
956 dev->pci_irqmask = 0x001f00;
957
958 /* External Master 1 Bus */
959 dev->i2c_bus[0].nr = 0;
960 dev->i2c_bus[0].dev = dev;
961 dev->i2c_bus[0].reg_stat = I2C1_STAT;
962 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
963 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
964 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
965 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
966 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */
967
968
969 if (get_resources(dev) < 0) {
970 printk(KERN_ERR "%s No more PCIe resources for "
971 "subsystem: %04x:%04x\n",
972 dev->name, dev->pci->subsystem_vendor,
973 dev->pci->subsystem_device);
974
975 cx25821_devcount--;
976 return -ENODEV;
977 }
999 978
1000 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0)); 979 /* PCIe stuff */
980 dev->base_io_addr = pci_resource_start(dev->pci, 0);
981 io_size = pci_resource_len(dev->pci, 0);
1001 982
1002 if (!dev->lmmio) { 983 if (!dev->base_io_addr) {
1003 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n"); 984 CX25821_ERR("No PCI Memory resources, exiting!\n");
1004 cx25821_iounmap(dev); 985 return -ENODEV;
1005 return -ENOMEM; 986 }
1006 }
1007 987
988 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1008 989
1009 dev->bmmio = (u8 __iomem *)dev->lmmio; 990 if (!dev->lmmio) {
991 CX25821_ERR
992 ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
993 cx25821_iounmap(dev);
994 return -ENOMEM;
995 }
996
997 dev->bmmio = (u8 __iomem *) dev->lmmio;
1010 998
1011 printk(KERN_INFO "%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", 999 printk(KERN_INFO "%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
1012 dev->name, dev->pci->subsystem_vendor, 1000 dev->name, dev->pci->subsystem_vendor,
1013 dev->pci->subsystem_device, cx25821_boards[dev->board].name, 1001 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
1014 dev->board, card[dev->nr] == dev->board ? 1002 dev->board, card[dev->nr] == dev->board ?
1015 "insmod option" : "autodetected"); 1003 "insmod option" : "autodetected");
1016 1004
1017 /* init hardware */ 1005 /* init hardware */
1018 cx25821_initialize(dev); 1006 cx25821_initialize(dev);
1019 1007
1020 cx25821_i2c_register(&dev->i2c_bus[0]); 1008 cx25821_i2c_register(&dev->i2c_bus[0]);
1021// cx25821_i2c_register(&dev->i2c_bus[1]); 1009// cx25821_i2c_register(&dev->i2c_bus[1]);
1022// cx25821_i2c_register(&dev->i2c_bus[2]); 1010// cx25821_i2c_register(&dev->i2c_bus[2]);
1023 1011
1024 CX25821_INFO("i2c register! bus->i2c_rc = %d\n", dev->i2c_bus[0].i2c_rc); 1012 CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
1013 dev->i2c_bus[0].i2c_rc);
1025 1014
1026 cx25821_card_setup(dev); 1015 cx25821_card_setup(dev);
1027 medusa_video_init(dev); 1016 medusa_video_init(dev);
1028 1017
1029 for(i = 0; i < VID_CHANNEL_NUM; i++) 1018 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1030 { 1019 if (cx25821_video_register(dev, i, video_template[i]) < 0) {
1031 if (cx25821_video_register(dev, i, video_template[i]) < 0) { 1020 printk(KERN_ERR
1032 printk(KERN_ERR "%s() Failed to register analog video adapters on VID channel %d\n", __func__, i); 1021 "%s() Failed to register analog video adapters on VID channel %d\n",
1022 __func__, i);
1023 }
1033 } 1024 }
1034 }
1035
1036 1025
1037 for(i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) 1026 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1038 { 1027 i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1039 //Since we don't have template8 for Audio Downstream 1028 //Since we don't have template8 for Audio Downstream
1040 if (cx25821_video_register(dev, i, video_template[i-1]) < 0) { 1029 if (cx25821_video_register(dev, i, video_template[i - 1]) < 0) {
1041 printk(KERN_ERR "%s() Failed to register analog video adapters for Upstream channel %d.\n", __func__, i); 1030 printk(KERN_ERR
1031 "%s() Failed to register analog video adapters for Upstream channel %d.\n",
1032 __func__, i);
1033 }
1042 } 1034 }
1043 }
1044 1035
1045 // register IOCTL device 1036 // register IOCTL device
1046 dev->ioctl_dev = cx25821_vdev_init(dev, dev->pci, video_template[VIDEO_IOCTL_CH], "video"); 1037 dev->ioctl_dev =
1047 1038 cx25821_vdev_init(dev, dev->pci, video_template[VIDEO_IOCTL_CH],
1048 if( video_register_device(dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0 ) 1039 "video");
1049 { 1040
1050 cx25821_videoioctl_unregister(dev); 1041 if (video_register_device
1051 printk(KERN_ERR "%s() Failed to register video adapter for IOCTL so releasing.\n", __func__); 1042 (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) {
1052 } 1043 cx25821_videoioctl_unregister(dev);
1044 printk(KERN_ERR
1045 "%s() Failed to register video adapter for IOCTL so releasing.\n",
1046 __func__);
1047 }
1053 1048
1054 cx25821_dev_checkrevision(dev); 1049 cx25821_dev_checkrevision(dev);
1055 CX25821_INFO("cx25821 setup done!\n"); 1050 CX25821_INFO("cx25821 setup done!\n");
1056 1051
1057 return 0; 1052 return 0;
1058} 1053}
1059 1054
1060 1055void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
1061void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev, struct upstream_user_struct *up_data) 1056 struct upstream_user_struct *up_data)
1062{ 1057{
1063 dev->_isNTSC = !strcmp(dev->vid_stdname,"NTSC") ? 1 : 0; 1058 dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1064 1059
1065 dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M; 1060 dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1066 medusa_set_videostandard(dev); 1061 medusa_set_videostandard(dev);
1067 1062
1068 cx25821_vidupstream_init_ch1(dev, dev->channel_select, dev->pixel_format); 1063 cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1064 dev->pixel_format);
1069} 1065}
1070 1066
1071 1067void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1072void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev, struct upstream_user_struct *up_data) 1068 struct upstream_user_struct *up_data)
1073{ 1069{
1074 dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2,"NTSC") ? 1 : 0; 1070 dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1075 1071
1076 dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M; 1072 dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1077 medusa_set_videostandard(dev); 1073 medusa_set_videostandard(dev);
1078 1074
1079 cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2, dev->pixel_format_ch2); 1075 cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1076 dev->pixel_format_ch2);
1080} 1077}
1081 1078
1082 1079void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1083void cx25821_start_upstream_audio(struct cx25821_dev *dev, struct upstream_user_struct *up_data) 1080 struct upstream_user_struct *up_data)
1084{ 1081{
1085 cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B); 1082 cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1086} 1083}
1087 1084
1088void cx25821_dev_unregister(struct cx25821_dev *dev) 1085void cx25821_dev_unregister(struct cx25821_dev *dev)
1089{ 1086{
1090 int i; 1087 int i;
1091
1092 if (!dev->base_io_addr)
1093 return;
1094 1088
1095 cx25821_free_mem_upstream_ch1(dev); 1089 if (!dev->base_io_addr)
1096 cx25821_free_mem_upstream_ch2(dev); 1090 return;
1097 cx25821_free_mem_upstream_audio(dev);
1098 1091
1099 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0)); 1092 cx25821_free_mem_upstream_ch1(dev);
1093 cx25821_free_mem_upstream_ch2(dev);
1094 cx25821_free_mem_upstream_audio(dev);
1100 1095
1101 if (!atomic_dec_and_test(&dev->refcount)) 1096 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1102 return;
1103 1097
1104 for(i=0; i < VID_CHANNEL_NUM; i++) 1098 if (!atomic_dec_and_test(&dev->refcount))
1105 cx25821_video_unregister(dev, i); 1099 return;
1106 1100
1101 for (i = 0; i < VID_CHANNEL_NUM; i++)
1102 cx25821_video_unregister(dev, i);
1107 1103
1108 for(i = VID_UPSTREAM_SRAM_CHANNEL_I; i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) 1104 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1109 { 1105 i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1110 cx25821_video_unregister(dev, i); 1106 cx25821_video_unregister(dev, i);
1111 } 1107 }
1112 1108
1113 cx25821_videoioctl_unregister(dev); 1109 cx25821_videoioctl_unregister(dev);
1114 1110
1115 cx25821_i2c_unregister( &dev->i2c_bus[0] ); 1111 cx25821_i2c_unregister(&dev->i2c_bus[0]);
1116 cx25821_iounmap(dev); 1112 cx25821_iounmap(dev);
1117} 1113}
1118 1114
1119 1115static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1120 1116 unsigned int offset, u32 sync_line,
1121static __le32 *cx25821_risc_field(__le32 *rp, struct scatterlist *sglist, 1117 unsigned int bpl, unsigned int padding,
1122 unsigned int offset, u32 sync_line, 1118 unsigned int lines)
1123 unsigned int bpl, unsigned int padding,
1124 unsigned int lines)
1125{ 1119{
1126 struct scatterlist *sg; 1120 struct scatterlist *sg;
1127 unsigned int line, todo; 1121 unsigned int line, todo;
1128 1122
1129 /* sync instruction */ 1123 /* sync instruction */
1130 if (sync_line != NO_SYNC_LINE) 1124 if (sync_line != NO_SYNC_LINE) {
1131 { 1125 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1132 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1133 }
1134
1135 /* scan lines */
1136 sg = sglist;
1137 for (line = 0; line < lines; line++) {
1138 while (offset && offset >= sg_dma_len(sg)) {
1139 offset -= sg_dma_len(sg);
1140 sg++;
1141 }
1142 if (bpl <= sg_dma_len(sg)-offset) {
1143 /* fits into current chunk */
1144 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
1145 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1146 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1147 offset += bpl;
1148 } else {
1149 /* scanline needs to be split */
1150 todo = bpl;
1151 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|(sg_dma_len(sg)-offset));
1152 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1153 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1154 todo -= (sg_dma_len(sg)-offset);
1155 offset = 0;
1156 sg++;
1157 while (todo > sg_dma_len(sg)) {
1158 *(rp++) = cpu_to_le32(RISC_WRITE|sg_dma_len(sg));
1159 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1160 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1161 todo -= sg_dma_len(sg);
1162 sg++;
1163 }
1164 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1165 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1166 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1167 offset += todo;
1168 } 1126 }
1169 1127
1170 offset += padding; 1128 /* scan lines */
1171 } 1129 sg = sglist;
1130 for (line = 0; line < lines; line++) {
1131 while (offset && offset >= sg_dma_len(sg)) {
1132 offset -= sg_dma_len(sg);
1133 sg++;
1134 }
1135 if (bpl <= sg_dma_len(sg) - offset) {
1136 /* fits into current chunk */
1137 *(rp++) =
1138 cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | bpl);
1139 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1140 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1141 offset += bpl;
1142 } else {
1143 /* scanline needs to be split */
1144 todo = bpl;
1145 *(rp++) =
1146 cpu_to_le32(RISC_WRITE | RISC_SOL |
1147 (sg_dma_len(sg) - offset));
1148 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1149 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1150 todo -= (sg_dma_len(sg) - offset);
1151 offset = 0;
1152 sg++;
1153 while (todo > sg_dma_len(sg)) {
1154 *(rp++) =
1155 cpu_to_le32(RISC_WRITE | sg_dma_len(sg));
1156 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1157 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1158 todo -= sg_dma_len(sg);
1159 sg++;
1160 }
1161 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1162 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1163 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1164 offset += todo;
1165 }
1166
1167 offset += padding;
1168 }
1172 1169
1173 return rp; 1170 return rp;
1174} 1171}
1175 1172
1176int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, 1173int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1177 struct scatterlist *sglist, unsigned int top_offset, 1174 struct scatterlist *sglist, unsigned int top_offset,
1178 unsigned int bottom_offset, unsigned int bpl, 1175 unsigned int bottom_offset, unsigned int bpl,
1179 unsigned int padding, unsigned int lines) 1176 unsigned int padding, unsigned int lines)
1180{ 1177{
1181 u32 instructions; 1178 u32 instructions;
1182 u32 fields; 1179 u32 fields;
1183 __le32 *rp; 1180 __le32 *rp;
1184 int rc; 1181 int rc;
1185 1182
1186 fields = 0; 1183 fields = 0;
1187 if (UNSET != top_offset) 1184 if (UNSET != top_offset)
1188 fields++; 1185 fields++;
1189 if (UNSET != bottom_offset) 1186 if (UNSET != bottom_offset)
1190 fields++; 1187 fields++;
1191 1188
1192 /* estimate risc mem: worst case is one write per page border + 1189 /* estimate risc mem: worst case is one write per page border +
1193 one write per scan line + syncs + jump (all 2 dwords). Padding 1190 one write per scan line + syncs + jump (all 2 dwords). Padding
1194 can cause next bpl to start close to a page border. First DMA 1191 can cause next bpl to start close to a page border. First DMA
1195 region may be smaller than PAGE_SIZE */ 1192 region may be smaller than PAGE_SIZE */
1196 /* write and jump need and extra dword */ 1193 /* write and jump need and extra dword */
1197 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines); 1194 instructions =
1198 instructions += 2; 1195 fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1199 rc = btcx_riscmem_alloc(pci, risc, instructions*12); 1196 instructions += 2;
1200 1197 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1201 if (rc < 0) 1198
1202 return rc; 1199 if (rc < 0)
1203 1200 return rc;
1204 /* write risc instructions */ 1201
1205 rp = risc->cpu; 1202 /* write risc instructions */
1206 1203 rp = risc->cpu;
1207 if (UNSET != top_offset) 1204
1208 { 1205 if (UNSET != top_offset) {
1209 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding, lines); 1206 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1210 } 1207 lines);
1211 1208 }
1212 if (UNSET != bottom_offset)
1213 {
1214 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl, padding, lines);
1215 }
1216
1217 /* save pointer to jmp instruction address */
1218 risc->jmp = rp;
1219 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1220
1221 return 0;
1222}
1223
1224 1209
1225static __le32* cx25821_risc_field_audio(__le32 *rp, struct scatterlist *sglist, 1210 if (UNSET != bottom_offset) {
1226 unsigned int offset, u32 sync_line, 1211 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1227 unsigned int bpl, unsigned int padding, 1212 padding, lines);
1228 unsigned int lines, unsigned int lpi)
1229{
1230 struct scatterlist *sg;
1231 unsigned int line, todo, sol;
1232
1233 /* sync instruction */
1234 if (sync_line != NO_SYNC_LINE)
1235 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1236
1237 /* scan lines */
1238 sg = sglist;
1239 for (line = 0; line < lines; line++) {
1240 while (offset && offset >= sg_dma_len(sg)) {
1241 offset -= sg_dma_len(sg);
1242 sg++;
1243 } 1213 }
1244 1214
1245 if (lpi && line > 0 && !(line % lpi)) 1215 /* save pointer to jmp instruction address */
1246 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; 1216 risc->jmp = rp;
1247 else 1217 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1248 sol = RISC_SOL; 1218
1249 1219 return 0;
1250 if (bpl <= sg_dma_len(sg)-offset) { 1220}
1251 /* fits into current chunk */ 1221
1252 *(rp++) = cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl); 1222static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1253 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); 1223 unsigned int offset, u32 sync_line,
1254 *(rp++)=cpu_to_le32(0); /* bits 63-32 */ 1224 unsigned int bpl, unsigned int padding,
1255 offset+=bpl; 1225 unsigned int lines, unsigned int lpi)
1256 } else { 1226{
1257 /* scanline needs to be split */ 1227 struct scatterlist *sg;
1258 todo = bpl; 1228 unsigned int line, todo, sol;
1259 *(rp++) = cpu_to_le32(RISC_WRITE|sol| 1229
1260 (sg_dma_len(sg)-offset)); 1230 /* sync instruction */
1261 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); 1231 if (sync_line != NO_SYNC_LINE)
1262 *(rp++)=cpu_to_le32(0); /* bits 63-32 */ 1232 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1263 todo -= (sg_dma_len(sg)-offset); 1233
1264 offset = 0; 1234 /* scan lines */
1265 sg++; 1235 sg = sglist;
1266 while (todo > sg_dma_len(sg)) { 1236 for (line = 0; line < lines; line++) {
1267 *(rp++)=cpu_to_le32(RISC_WRITE| 1237 while (offset && offset >= sg_dma_len(sg)) {
1268 sg_dma_len(sg)); 1238 offset -= sg_dma_len(sg);
1269 *(rp++)=cpu_to_le32(sg_dma_address(sg)); 1239 sg++;
1270 *(rp++)=cpu_to_le32(0); /* bits 63-32 */ 1240 }
1271 todo -= sg_dma_len(sg); 1241
1272 sg++; 1242 if (lpi && line > 0 && !(line % lpi))
1273 } 1243 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1274 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo); 1244 else
1275 *(rp++)=cpu_to_le32(sg_dma_address(sg)); 1245 sol = RISC_SOL;
1276 *(rp++)=cpu_to_le32(0); /* bits 63-32 */ 1246
1277 offset += todo; 1247 if (bpl <= sg_dma_len(sg) - offset) {
1248 /* fits into current chunk */
1249 *(rp++) =
1250 cpu_to_le32(RISC_WRITE | sol | RISC_EOL | bpl);
1251 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1252 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1253 offset += bpl;
1254 } else {
1255 /* scanline needs to be split */
1256 todo = bpl;
1257 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1258 (sg_dma_len(sg) - offset));
1259 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1260 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1261 todo -= (sg_dma_len(sg) - offset);
1262 offset = 0;
1263 sg++;
1264 while (todo > sg_dma_len(sg)) {
1265 *(rp++) = cpu_to_le32(RISC_WRITE |
1266 sg_dma_len(sg));
1267 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1268 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1269 todo -= sg_dma_len(sg);
1270 sg++;
1271 }
1272 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1273 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1274 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1275 offset += todo;
1276 }
1277 offset += padding;
1278 } 1278 }
1279 offset += padding;
1280 }
1281 1279
1282 return rp; 1280 return rp;
1283} 1281}
1284 1282
1285int cx25821_risc_databuffer_audio(struct pci_dev *pci, 1283int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1286 struct btcx_riscmem *risc, 1284 struct btcx_riscmem *risc,
1287 struct scatterlist *sglist, 1285 struct scatterlist *sglist,
1288 unsigned int bpl, 1286 unsigned int bpl,
1289 unsigned int lines, 1287 unsigned int lines, unsigned int lpi)
1290 unsigned int lpi)
1291{ 1288{
1292 u32 instructions; 1289 u32 instructions;
1293 __le32 *rp; 1290 __le32 *rp;
1294 int rc; 1291 int rc;
1295 1292
1296 /* estimate risc mem: worst case is one write per page border + 1293 /* estimate risc mem: worst case is one write per page border +
1297 one write per scan line + syncs + jump (all 2 dwords). Here 1294 one write per scan line + syncs + jump (all 2 dwords). Here
1298 there is no padding and no sync. First DMA region may be smaller 1295 there is no padding and no sync. First DMA region may be smaller
1299 than PAGE_SIZE */ 1296 than PAGE_SIZE */
1300 /* Jump and write need an extra dword */ 1297 /* Jump and write need an extra dword */
1301 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; 1298 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1302 instructions += 1; 1299 instructions += 1;
1303 1300
1304 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0) 1301 if ((rc = btcx_riscmem_alloc(pci, risc, instructions * 12)) < 0)
1305 return rc; 1302 return rc;
1306 1303
1307 1304 /* write risc instructions */
1308 /* write risc instructions */ 1305 rp = risc->cpu;
1309 rp = risc->cpu; 1306 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1310 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines, lpi); 1307 lines, lpi);
1311 1308
1312 /* save pointer to jmp instruction address */ 1309 /* save pointer to jmp instruction address */
1313 risc->jmp = rp; 1310 risc->jmp = rp;
1314 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); 1311 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1315 return 0; 1312 return 0;
1316} 1313}
1317 1314
1318 1315int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1319int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,u32 reg, u32 mask, u32 value) 1316 u32 reg, u32 mask, u32 value)
1320{ 1317{
1321 __le32 *rp; 1318 __le32 *rp;
1322 int rc; 1319 int rc;
1323 1320
1324 rc = btcx_riscmem_alloc(pci, risc, 4*16); 1321 rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1325 1322
1326 if (rc < 0) 1323 if (rc < 0)
1327 return rc; 1324 return rc;
1328 1325
1329 /* write risc instructions */ 1326 /* write risc instructions */
1330 rp = risc->cpu; 1327 rp = risc->cpu;
1331 1328
1332 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1); 1329 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1333 *(rp++) = cpu_to_le32(reg); 1330 *(rp++) = cpu_to_le32(reg);
1334 *(rp++) = cpu_to_le32(value); 1331 *(rp++) = cpu_to_le32(value);
1335 *(rp++) = cpu_to_le32(mask); 1332 *(rp++) = cpu_to_le32(mask);
1336 *(rp++) = cpu_to_le32(RISC_JUMP); 1333 *(rp++) = cpu_to_le32(RISC_JUMP);
1337 *(rp++) = cpu_to_le32(risc->dma); 1334 *(rp++) = cpu_to_le32(risc->dma);
1338 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1335 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1339 return 0; 1336 return 0;
1340} 1337}
1341 1338
1342void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf) 1339void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1343{ 1340{
1344 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); 1341 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1345 1342
1346 BUG_ON(in_interrupt()); 1343 BUG_ON(in_interrupt());
1347 videobuf_waiton(&buf->vb, 0, 0); 1344 videobuf_waiton(&buf->vb, 0, 0);
1348 videobuf_dma_unmap(q, dma); 1345 videobuf_dma_unmap(q, dma);
1349 videobuf_dma_free(dma); 1346 videobuf_dma_free(dma);
1350 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc); 1347 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1351 buf->vb.state = VIDEOBUF_NEEDS_INIT; 1348 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1352} 1349}
1353 1350
1354
1355static irqreturn_t cx25821_irq(int irq, void *dev_id) 1351static irqreturn_t cx25821_irq(int irq, void *dev_id)
1356{ 1352{
1357 struct cx25821_dev *dev = dev_id; 1353 struct cx25821_dev *dev = dev_id;
1358 u32 pci_status, pci_mask; 1354 u32 pci_status, pci_mask;
1359 u32 vid_status; 1355 u32 vid_status;
1360 int i, handled = 0; 1356 int i, handled = 0;
1361 u32 mask[8] = {1, 2, 4, 8, 16, 32, 64, 128}; 1357 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1362 1358
1363 pci_status = cx_read(PCI_INT_STAT); 1359 pci_status = cx_read(PCI_INT_STAT);
1364 pci_mask = cx_read(PCI_INT_MSK); 1360 pci_mask = cx_read(PCI_INT_MSK);
1365 1361
1362 if (pci_status == 0)
1363 goto out;
1366 1364
1367 if (pci_status == 0) 1365 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1368 goto out; 1366 if (pci_status & mask[i]) {
1367 vid_status = cx_read(dev->sram_channels[i].int_stat);
1369 1368
1370 for(i = 0; i < VID_CHANNEL_NUM; i++) 1369 if (vid_status)
1371 { 1370 handled +=
1372 if(pci_status & mask[i]) 1371 cx25821_video_irq(dev, i, vid_status);
1373 {
1374 vid_status = cx_read(dev->sram_channels[i].int_stat);
1375
1376 if(vid_status)
1377 handled += cx25821_video_irq(dev, i, vid_status);
1378 1372
1379 cx_write(PCI_INT_STAT, mask[i]); 1373 cx_write(PCI_INT_STAT, mask[i]);
1374 }
1380 } 1375 }
1381 }
1382 1376
1383out: 1377 out:
1384 return IRQ_RETVAL(handled); 1378 return IRQ_RETVAL(handled);
1385} 1379}
1386 1380
1387void cx25821_print_irqbits(char *name, char *tag, char **strings, 1381void cx25821_print_irqbits(char *name, char *tag, char **strings,
1388 int len, u32 bits, u32 mask) 1382 int len, u32 bits, u32 mask)
1389{ 1383{
1390 unsigned int i; 1384 unsigned int i;
1391 1385
1392 printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits); 1386 printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits);
1393 1387
1394 for (i = 0; i < len; i++) { 1388 for (i = 0; i < len; i++) {
1395 if (!(bits & (1 << i))) 1389 if (!(bits & (1 << i)))
1396 continue; 1390 continue;
1397 if (strings[i]) 1391 if (strings[i])
1398 printk(" %s", strings[i]); 1392 printk(" %s", strings[i]);
1399 else 1393 else
1400 printk(" %d", i); 1394 printk(" %d", i);
1401 if (!(mask & (1 << i))) 1395 if (!(mask & (1 << i)))
1402 continue; 1396 continue;
1403 printk("*"); 1397 printk("*");
1404 } 1398 }
1405 printk("\n"); 1399 printk("\n");
1406} 1400}
1407 1401
1408struct cx25821_dev* cx25821_dev_get(struct pci_dev *pci) 1402struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1409{ 1403{
1410 struct cx25821_dev *dev = pci_get_drvdata(pci); 1404 struct cx25821_dev *dev = pci_get_drvdata(pci);
1411 return dev; 1405 return dev;
1412} 1406}
1413 1407
1414static int __devinit cx25821_initdev(struct pci_dev *pci_dev, const struct pci_device_id *pci_id) 1408static int __devinit cx25821_initdev(struct pci_dev *pci_dev,
1409 const struct pci_device_id *pci_id)
1415{ 1410{
1416 struct cx25821_dev *dev; 1411 struct cx25821_dev *dev;
1417 int err = 0; 1412 int err = 0;
1418
1419 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1420 if (NULL == dev)
1421 return -ENOMEM;
1422
1423 1413
1424 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); 1414 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1425 if (err < 0) 1415 if (NULL == dev)
1426 goto fail_free; 1416 return -ENOMEM;
1427 1417
1428 /* pci init */ 1418 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1429 dev->pci = pci_dev; 1419 if (err < 0)
1430 if (pci_enable_device(pci_dev)) 1420 goto fail_free;
1431 {
1432 err = -EIO;
1433 1421
1434 printk(KERN_INFO "pci enable failed! "); 1422 /* pci init */
1423 dev->pci = pci_dev;
1424 if (pci_enable_device(pci_dev)) {
1425 err = -EIO;
1435 1426
1436 goto fail_unregister_device; 1427 printk(KERN_INFO "pci enable failed! ");
1437 }
1438 1428
1439 printk(KERN_INFO "cx25821 Athena pci enable ! \n"); 1429 goto fail_unregister_device;
1440 1430 }
1441 if (cx25821_dev_setup(dev) < 0)
1442 {
1443 err = -EINVAL;
1444 goto fail_unregister_device;
1445 }
1446 1431
1447 /* print pci info */ 1432 printk(KERN_INFO "cx25821 Athena pci enable ! \n");
1448 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1449 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1450 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1451 "latency: %d, mmio: 0x%llx\n", dev->name,
1452 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1453 dev->pci_lat,
1454 (unsigned long long)dev->base_io_addr );
1455 1433
1434 if (cx25821_dev_setup(dev) < 0) {
1435 err = -EINVAL;
1436 goto fail_unregister_device;
1437 }
1456 1438
1457 pci_set_master(pci_dev); 1439 /* print pci info */
1458 if (!pci_dma_supported(pci_dev, 0xffffffff)) 1440 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1459 { 1441 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1460 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); 1442 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1461 err = -EIO; 1443 "latency: %d, mmio: 0x%llx\n", dev->name,
1462 goto fail_irq; 1444 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1463 } 1445 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1446
1447 pci_set_master(pci_dev);
1448 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1449 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1450 err = -EIO;
1451 goto fail_irq;
1452 }
1464 1453
1465 err = request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED | IRQF_DISABLED, dev->name, dev); 1454 err =
1455 request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED | IRQF_DISABLED,
1456 dev->name, dev);
1466 1457
1467 if (err < 0) 1458 if (err < 0) {
1468 { 1459 printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name,
1469 printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name, pci_dev->irq); 1460 pci_dev->irq);
1470 goto fail_irq; 1461 goto fail_irq;
1471 } 1462 }
1472 1463
1473 return 0; 1464 return 0;
1474 1465
1475fail_irq: 1466 fail_irq:
1476 printk(KERN_INFO "cx25821 cx25821_initdev() can't get IRQ ! \n"); 1467 printk(KERN_INFO "cx25821 cx25821_initdev() can't get IRQ ! \n");
1477 cx25821_dev_unregister(dev); 1468 cx25821_dev_unregister(dev);
1478 1469
1479fail_unregister_device: 1470 fail_unregister_device:
1480 v4l2_device_unregister(&dev->v4l2_dev); 1471 v4l2_device_unregister(&dev->v4l2_dev);
1481 1472
1482fail_free: 1473 fail_free:
1483 kfree(dev); 1474 kfree(dev);
1484 return err; 1475 return err;
1485} 1476}
1486 1477
1487static void __devexit cx25821_finidev(struct pci_dev *pci_dev) 1478static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
1488{ 1479{
1489 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); 1480 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1490 struct cx25821_dev *dev = get_cx25821(v4l2_dev); 1481 struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1491 1482
1492 cx25821_shutdown(dev); 1483 cx25821_shutdown(dev);
1493 pci_disable_device(pci_dev); 1484 pci_disable_device(pci_dev);
1494 1485
1495 /* unregister stuff */ 1486 /* unregister stuff */
1496 if( pci_dev->irq ) 1487 if (pci_dev->irq)
1497 free_irq(pci_dev->irq, dev); 1488 free_irq(pci_dev->irq, dev);
1498 1489
1490 mutex_lock(&devlist);
1491 list_del(&dev->devlist);
1492 mutex_unlock(&devlist);
1499 1493
1500 mutex_lock(&devlist); 1494 cx25821_dev_unregister(dev);
1501 list_del(&dev->devlist); 1495 v4l2_device_unregister(v4l2_dev);
1502 mutex_unlock(&devlist); 1496 kfree(dev);
1503
1504 cx25821_dev_unregister(dev);
1505 v4l2_device_unregister(v4l2_dev);
1506 kfree(dev);
1507} 1497}
1508 1498
1509static struct pci_device_id cx25821_pci_tbl[] = { 1499static struct pci_device_id cx25821_pci_tbl[] = {
1510 { 1500 {
1511 /* CX25821 Athena*/ 1501 /* CX25821 Athena */
1512 .vendor = 0x14f1, 1502 .vendor = 0x14f1,
1513 .device = 0x8210, 1503 .device = 0x8210,
1514 .subvendor = 0x14f1, 1504 .subvendor = 0x14f1,
1515 .subdevice = 0x0920, 1505 .subdevice = 0x0920,
1516 }, 1506 },
1517 { 1507 {
1518 /* --- end of list --- */ 1508 /* --- end of list --- */
1519 } 1509 }
1520}; 1510};
1521 1511
1522MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl); 1512MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1523 1513
1524static struct pci_driver cx25821_pci_driver = 1514static struct pci_driver cx25821_pci_driver = {
1525{ 1515 .name = "cx25821",
1526 .name = "cx25821", 1516 .id_table = cx25821_pci_tbl,
1527 .id_table = cx25821_pci_tbl, 1517 .probe = cx25821_initdev,
1528 .probe = cx25821_initdev, 1518 .remove = __devexit_p(cx25821_finidev),
1529 .remove = __devexit_p(cx25821_finidev), 1519 /* TODO */
1530 /* TODO */ 1520 .suspend = NULL,
1531 .suspend = NULL, 1521 .resume = NULL,
1532 .resume = NULL,
1533}; 1522};
1534 1523
1535static int cx25821_init(void) 1524static int cx25821_init(void)
1536{ 1525{
1537 INIT_LIST_HEAD(&cx25821_devlist); 1526 INIT_LIST_HEAD(&cx25821_devlist);
1538 printk(KERN_INFO "cx25821 driver version %d.%d.%d loaded\n", 1527 printk(KERN_INFO "cx25821 driver version %d.%d.%d loaded\n",
1539 (CX25821_VERSION_CODE >> 16) & 0xff, 1528 (CX25821_VERSION_CODE >> 16) & 0xff,
1540 (CX25821_VERSION_CODE >> 8) & 0xff, 1529 (CX25821_VERSION_CODE >> 8) & 0xff, CX25821_VERSION_CODE & 0xff);
1541 CX25821_VERSION_CODE & 0xff); 1530 return pci_register_driver(&cx25821_pci_driver);
1542 return pci_register_driver(&cx25821_pci_driver);
1543} 1531}
1544 1532
1545static void cx25821_fini(void) 1533static void cx25821_fini(void)
1546{ 1534{
1547 pci_unregister_driver(&cx25821_pci_driver); 1535 pci_unregister_driver(&cx25821_pci_driver);
1548} 1536}
1549 1537
1550
1551EXPORT_SYMBOL(cx25821_devlist); 1538EXPORT_SYMBOL(cx25821_devlist);
1552EXPORT_SYMBOL(cx25821_sram_channels); 1539EXPORT_SYMBOL(cx25821_sram_channels);
1553EXPORT_SYMBOL(cx25821_print_irqbits); 1540EXPORT_SYMBOL(cx25821_print_irqbits);
@@ -1562,4 +1549,3 @@ EXPORT_SYMBOL(cx25821_set_gpiopin_direction);
1562 1549
1563module_init(cx25821_init); 1550module_init(cx25821_init);
1564module_exit(cx25821_fini); 1551module_exit(cx25821_fini);
1565
diff --git a/drivers/staging/cx25821/cx25821-gpio.c b/drivers/staging/cx25821/cx25821-gpio.c
index 074c19682af8..e8a37b47e437 100644
--- a/drivers/staging/cx25821/cx25821-gpio.c
+++ b/drivers/staging/cx25821/cx25821-gpio.c
@@ -1,116 +1,98 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22
23#include "cx25821.h"
24 22
23#include "cx25821.h"
25 24
26/********************* GPIO stuffs *********************/ 25/********************* GPIO stuffs *********************/
27void cx25821_set_gpiopin_direction( struct cx25821_dev *dev, 26void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
28 int pin_number, 27 int pin_number, int pin_logic_value)
29 int pin_logic_value)
30{ 28{
31 int bit = pin_number; 29 int bit = pin_number;
32 u32 gpio_oe_reg = GPIO_LO_OE; 30 u32 gpio_oe_reg = GPIO_LO_OE;
33 u32 gpio_register = 0; 31 u32 gpio_register = 0;
34 u32 value = 0; 32 u32 value = 0;
35
36 // Check for valid pinNumber
37 if ( pin_number >= 47 )
38 return;
39 33
34 // Check for valid pinNumber
35 if (pin_number >= 47)
36 return;
40 37
41 if ( pin_number > 31 ) 38 if (pin_number > 31) {
42 { 39 bit = pin_number - 31;
43 bit = pin_number - 31; 40 gpio_oe_reg = GPIO_HI_OE;
44 gpio_oe_reg = GPIO_HI_OE;
45 } 41 }
42 // Here we will make sure that the GPIOs 0 and 1 are output. keep the rest as is
43 gpio_register = cx_read(gpio_oe_reg);
46 44
47 // Here we will make sure that the GPIOs 0 and 1 are output. keep the rest as is 45 if (pin_logic_value == 1) {
48 gpio_register = cx_read( gpio_oe_reg ); 46 value = gpio_register | Set_GPIO_Bit(bit);
49 47 } else {
50 if (pin_logic_value == 1) 48 value = gpio_register & Clear_GPIO_Bit(bit);
51 { 49 }
52 value = gpio_register | Set_GPIO_Bit(bit) ;
53 }
54 else
55 {
56 value = gpio_register & Clear_GPIO_Bit(bit) ;
57 }
58 50
59 cx_write( gpio_oe_reg, value ); 51 cx_write(gpio_oe_reg, value);
60} 52}
61 53
62static void cx25821_set_gpiopin_logicvalue( struct cx25821_dev *dev, 54static void cx25821_set_gpiopin_logicvalue(struct cx25821_dev *dev,
63 int pin_number, 55 int pin_number, int pin_logic_value)
64 int pin_logic_value)
65{ 56{
66 int bit = pin_number; 57 int bit = pin_number;
67 u32 gpio_reg = GPIO_LO; 58 u32 gpio_reg = GPIO_LO;
68 u32 value = 0; 59 u32 value = 0;
69
70 60
71 // Check for valid pinNumber 61 // Check for valid pinNumber
72 if (pin_number >= 47) 62 if (pin_number >= 47)
73 return; 63 return;
74
75 cx25821_set_gpiopin_direction(dev, pin_number, 0); // change to output direction
76 64
65 cx25821_set_gpiopin_direction(dev, pin_number, 0); // change to output direction
77 66
78 if ( pin_number > 31 ) 67 if (pin_number > 31) {
79 { 68 bit = pin_number - 31;
80 bit = pin_number - 31; 69 gpio_reg = GPIO_HI;
81 gpio_reg = GPIO_HI;
82 } 70 }
83 71
84 value = cx_read( gpio_reg ); 72 value = cx_read(gpio_reg);
85 73
74 if (pin_logic_value == 0) {
75 value &= Clear_GPIO_Bit(bit);
76 } else {
77 value |= Set_GPIO_Bit(bit);
78 }
86 79
87 if (pin_logic_value == 0) 80 cx_write(gpio_reg, value);
88 {
89 value &= Clear_GPIO_Bit(bit);
90 }
91 else
92 {
93 value |= Set_GPIO_Bit(bit);
94 }
95
96 cx_write( gpio_reg, value);
97} 81}
98 82
99void cx25821_gpio_init(struct cx25821_dev *dev) 83void cx25821_gpio_init(struct cx25821_dev *dev)
100{ 84{
101 if( dev == NULL ) 85 if (dev == NULL) {
102 { 86 return;
103 return;
104 } 87 }
105 88
106 switch (dev->board) 89 switch (dev->board) {
107 { 90 case CX25821_BOARD_CONEXANT_ATHENA10:
108 case CX25821_BOARD_CONEXANT_ATHENA10: 91 default:
109 default: 92 //set GPIO 5 to select the path for Medusa/Athena
110 //set GPIO 5 to select the path for Medusa/Athena 93 cx25821_set_gpiopin_logicvalue(dev, 5, 1);
111 cx25821_set_gpiopin_logicvalue(dev, 5, 1); 94 mdelay(20);
112 mdelay(20); 95 break;
113 break;
114 } 96 }
115 97
116} 98}
diff --git a/drivers/staging/cx25821/cx25821-gpio.h b/drivers/staging/cx25821/cx25821-gpio.h
index 2dd938dbdc4c..ca07644154af 100644
--- a/drivers/staging/cx25821/cx25821-gpio.h
+++ b/drivers/staging/cx25821/cx25821-gpio.h
@@ -1,3 +1,2 @@
1 1
2void cx25821_gpio_init(struct athena_dev *dev); 2void cx25821_gpio_init(struct athena_dev *dev);
3
diff --git a/drivers/staging/cx25821/cx25821-i2c.c b/drivers/staging/cx25821/cx25821-i2c.c
index 0667b3f8eb91..cb260fa6f346 100644
--- a/drivers/staging/cx25821/cx25821-i2c.c
+++ b/drivers/staging/cx25821/cx25821-i2c.c
@@ -1,35 +1,34 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver 6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * 16 *
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */ 22 */
23 23
24#include "cx25821.h" 24#include "cx25821.h"
25#include <linux/i2c.h> 25#include <linux/i2c.h>
26 26
27
28static unsigned int i2c_debug; 27static unsigned int i2c_debug;
29module_param(i2c_debug, int, 0644); 28module_param(i2c_debug, int, 0644);
30MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]"); 29MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
31 30
32static unsigned int i2c_scan=0; 31static unsigned int i2c_scan = 0;
33module_param(i2c_scan, int, 0444); 32module_param(i2c_scan, int, 0444);
34MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time"); 33MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
35 34
@@ -44,7 +43,6 @@ MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
44#define I2C_EXTEND (1 << 3) 43#define I2C_EXTEND (1 << 3)
45#define I2C_NOSTOP (1 << 4) 44#define I2C_NOSTOP (1 << 4)
46 45
47
48static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) 46static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
49{ 47{
50 struct cx25821_i2c *bus = i2c_adap->algo_data; 48 struct cx25821_i2c *bus = i2c_adap->algo_data;
@@ -75,7 +73,8 @@ static int i2c_wait_done(struct i2c_adapter *i2c_adap)
75 return 1; 73 return 1;
76} 74}
77 75
78static int i2c_sendbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg, int joined_rlen) 76static int i2c_sendbytes(struct i2c_adapter *i2c_adap,
77 const struct i2c_msg *msg, int joined_rlen)
79{ 78{
80 struct cx25821_i2c *bus = i2c_adap->algo_data; 79 struct cx25821_i2c *bus = i2c_adap->algo_data;
81 struct cx25821_dev *dev = bus->dev; 80 struct cx25821_dev *dev = bus->dev;
@@ -83,13 +82,13 @@ static int i2c_sendbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
83 int retval, cnt; 82 int retval, cnt;
84 83
85 if (joined_rlen) 84 if (joined_rlen)
86 dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __func__, msg->len, joined_rlen); 85 dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __func__,
86 msg->len, joined_rlen);
87 else 87 else
88 dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len); 88 dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);
89 89
90 /* Deal with i2c probe functions with zero payload */ 90 /* Deal with i2c probe functions with zero payload */
91 if (msg->len == 0) 91 if (msg->len == 0) {
92 {
93 cx_write(bus->reg_addr, msg->addr << 25); 92 cx_write(bus->reg_addr, msg->addr << 25);
94 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2)); 93 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2));
95 94
@@ -125,8 +124,7 @@ static int i2c_sendbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
125 if (retval == 0) 124 if (retval == 0)
126 goto eio; 125 goto eio;
127 126
128 if (i2c_debug) 127 if (i2c_debug) {
129 {
130 if (!(ctrl & I2C_NOSTOP)) 128 if (!(ctrl & I2C_NOSTOP))
131 printk(" >\n"); 129 printk(" >\n");
132 } 130 }
@@ -152,8 +150,7 @@ static int i2c_sendbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
152 if (retval == 0) 150 if (retval == 0)
153 goto eio; 151 goto eio;
154 152
155 if (i2c_debug) 153 if (i2c_debug) {
156 {
157 dprintk(1, " %02x", msg->buf[cnt]); 154 dprintk(1, " %02x", msg->buf[cnt]);
158 if (!(ctrl & I2C_NOSTOP)) 155 if (!(ctrl & I2C_NOSTOP))
159 dprintk(1, " >\n"); 156 dprintk(1, " >\n");
@@ -162,22 +159,22 @@ static int i2c_sendbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
162 159
163 return msg->len; 160 return msg->len;
164 161
165 eio: 162 eio:
166 retval = -EIO; 163 retval = -EIO;
167 err: 164 err:
168 if (i2c_debug) 165 if (i2c_debug)
169 printk(KERN_ERR " ERR: %d\n", retval); 166 printk(KERN_ERR " ERR: %d\n", retval);
170 return retval; 167 return retval;
171} 168}
172 169
173static int i2c_readbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg, int joined) 170static int i2c_readbytes(struct i2c_adapter *i2c_adap,
171 const struct i2c_msg *msg, int joined)
174{ 172{
175 struct cx25821_i2c *bus = i2c_adap->algo_data; 173 struct cx25821_i2c *bus = i2c_adap->algo_data;
176 struct cx25821_dev *dev = bus->dev; 174 struct cx25821_dev *dev = bus->dev;
177 u32 ctrl, cnt; 175 u32 ctrl, cnt;
178 int retval; 176 int retval;
179 177
180
181 if (i2c_debug && !joined) 178 if (i2c_debug && !joined)
182 dprintk(1, "6-%s(msg->len=%d)\n", __func__, msg->len); 179 dprintk(1, "6-%s(msg->len=%d)\n", __func__, msg->len);
183 180
@@ -190,7 +187,6 @@ static int i2c_readbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
190 if (!i2c_slave_did_ack(i2c_adap)) 187 if (!i2c_slave_did_ack(i2c_adap))
191 return -EIO; 188 return -EIO;
192 189
193
194 dprintk(1, "%s() returns 0\n", __func__); 190 dprintk(1, "%s() returns 0\n", __func__);
195 return 0; 191 return 0;
196 } 192 }
@@ -209,7 +205,6 @@ static int i2c_readbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
209 if (cnt < msg->len - 1) 205 if (cnt < msg->len - 1)
210 ctrl |= I2C_NOSTOP | I2C_EXTEND; 206 ctrl |= I2C_NOSTOP | I2C_EXTEND;
211 207
212
213 cx_write(bus->reg_addr, msg->addr << 25); 208 cx_write(bus->reg_addr, msg->addr << 25);
214 cx_write(bus->reg_ctrl, ctrl); 209 cx_write(bus->reg_ctrl, ctrl);
215 210
@@ -228,9 +223,9 @@ static int i2c_readbytes(struct i2c_adapter *i2c_adap, const struct i2c_msg *msg
228 } 223 }
229 224
230 return msg->len; 225 return msg->len;
231 eio: 226 eio:
232 retval = -EIO; 227 retval = -EIO;
233 err: 228 err:
234 if (i2c_debug) 229 if (i2c_debug)
235 printk(KERN_ERR " ERR: %d\n", retval); 230 printk(KERN_ERR " ERR: %d\n", retval);
236 return retval; 231 return retval;
@@ -244,29 +239,24 @@ static int i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
244 239
245 dprintk(1, "%s(num = %d)\n", __func__, num); 240 dprintk(1, "%s(num = %d)\n", __func__, num);
246 241
247 for (i = 0 ; i < num; i++) 242 for (i = 0; i < num; i++) {
248 {
249 dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n", 243 dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n",
250 __func__, num, msgs[i].addr, msgs[i].len); 244 __func__, num, msgs[i].addr, msgs[i].len);
251 245
252 if (msgs[i].flags & I2C_M_RD) 246 if (msgs[i].flags & I2C_M_RD) {
253 {
254 /* read */ 247 /* read */
255 retval = i2c_readbytes(i2c_adap, &msgs[i], 0); 248 retval = i2c_readbytes(i2c_adap, &msgs[i], 0);
256 } 249 } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
257 else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) && 250 msgs[i].addr == msgs[i + 1].addr) {
258 msgs[i].addr == msgs[i + 1].addr)
259 {
260 /* write then read from same address */ 251 /* write then read from same address */
261 retval = i2c_sendbytes(i2c_adap, &msgs[i], msgs[i + 1].len); 252 retval =
253 i2c_sendbytes(i2c_adap, &msgs[i], msgs[i + 1].len);
262 254
263 if (retval < 0) 255 if (retval < 0)
264 goto err; 256 goto err;
265 i++; 257 i++;
266 retval = i2c_readbytes(i2c_adap, &msgs[i], 1); 258 retval = i2c_readbytes(i2c_adap, &msgs[i], 1);
267 } 259 } else {
268 else
269 {
270 /* write */ 260 /* write */
271 retval = i2c_sendbytes(i2c_adap, &msgs[i], 0); 261 retval = i2c_sendbytes(i2c_adap, &msgs[i], 0);
272 } 262 }
@@ -276,35 +266,33 @@ static int i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
276 } 266 }
277 return num; 267 return num;
278 268
279 err: 269 err:
280 return retval; 270 return retval;
281} 271}
282 272
283 273
284static u32 cx25821_functionality(struct i2c_adapter *adap) 274static u32 cx25821_functionality(struct i2c_adapter *adap)
285{ 275{
286 return I2C_FUNC_SMBUS_EMUL | 276 return I2C_FUNC_SMBUS_EMUL |
287 I2C_FUNC_I2C | 277 I2C_FUNC_I2C |
288 I2C_FUNC_SMBUS_WORD_DATA | 278 I2C_FUNC_SMBUS_WORD_DATA |
289 I2C_FUNC_SMBUS_READ_WORD_DATA | 279 I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA;
290 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
291} 280}
292 281
293static struct i2c_algorithm cx25821_i2c_algo_template = { 282static struct i2c_algorithm cx25821_i2c_algo_template = {
294 .master_xfer = i2c_xfer, 283 .master_xfer = i2c_xfer,
295 .functionality = cx25821_functionality, 284 .functionality = cx25821_functionality,
296}; 285};
297 286
298
299static struct i2c_adapter cx25821_i2c_adap_template = { 287static struct i2c_adapter cx25821_i2c_adap_template = {
300 .name = "cx25821", 288 .name = "cx25821",
301 .owner = THIS_MODULE, 289 .owner = THIS_MODULE,
302 .id = I2C_HW_B_CX25821, 290 .id = I2C_HW_B_CX25821,
303 .algo = &cx25821_i2c_algo_template, 291 .algo = &cx25821_i2c_algo_template,
304}; 292};
305 293
306static struct i2c_client cx25821_i2c_client_template = { 294static struct i2c_client cx25821_i2c_client_template = {
307 .name = "cx25821 internal", 295 .name = "cx25821 internal",
308}; 296};
309 297
310/* init + register i2c algo-bit adapter */ 298/* init + register i2c algo-bit adapter */
@@ -326,14 +314,14 @@ int cx25821_i2c_register(struct cx25821_i2c *bus)
326 strlcpy(bus->i2c_adap.name, bus->dev->name, sizeof(bus->i2c_adap.name)); 314 strlcpy(bus->i2c_adap.name, bus->dev->name, sizeof(bus->i2c_adap.name));
327 315
328 bus->i2c_algo.data = bus; 316 bus->i2c_algo.data = bus;
329 bus->i2c_adap.algo_data = bus; 317 bus->i2c_adap.algo_data = bus;
330 i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev); 318 i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev);
331 i2c_add_adapter(&bus->i2c_adap); 319 i2c_add_adapter(&bus->i2c_adap);
332 320
333 bus->i2c_client.adapter = &bus->i2c_adap; 321 bus->i2c_client.adapter = &bus->i2c_adap;
334 322
335 //set up the I2c 323 //set up the I2c
336 bus->i2c_client.addr = (0x88>>1); 324 bus->i2c_client.addr = (0x88 >> 1);
337 325
338 return bus->i2c_rc; 326 return bus->i2c_rc;
339} 327}
@@ -367,71 +355,66 @@ void cx25821_av_clk(struct cx25821_dev *dev, int enable)
367 i2c_xfer(&dev->i2c_bus[0].i2c_adap, &msg, 1); 355 i2c_xfer(&dev->i2c_bus[0].i2c_adap, &msg, 1);
368} 356}
369 357
370
371int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value) 358int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value)
372{ 359{
373 struct i2c_client *client = &bus->i2c_client; 360 struct i2c_client *client = &bus->i2c_client;
374 int retval = 0; 361 int retval = 0;
375 int v = 0; 362 int v = 0;
376 u8 addr[2] = {0, 0}; 363 u8 addr[2] = { 0, 0 };
377 u8 buf[4] = {0,0,0,0}; 364 u8 buf[4] = { 0, 0, 0, 0 };
378
379 struct i2c_msg msgs[2]={
380 {
381 .addr = client->addr,
382 .flags = 0,
383 .len = 2,
384 .buf = addr,
385 }, {
386 .addr = client->addr,
387 .flags = I2C_M_RD,
388 .len = 4,
389 .buf = buf,
390 }
391 };
392
393
394 addr[0] = (reg_addr>>8);
395 addr[1] = (reg_addr & 0xff);
396 msgs[0].addr = 0x44;
397 msgs[1].addr = 0x44;
398
399 retval = i2c_xfer(client->adapter, msgs, 2);
400
401 v = (buf[3]<<24) | (buf[2]<<16) | (buf[1]<<8) | buf[0];
402 *value = v;
403
404 return v;
405}
406 365
366 struct i2c_msg msgs[2] = {
367 {
368 .addr = client->addr,
369 .flags = 0,
370 .len = 2,
371 .buf = addr,
372 }, {
373 .addr = client->addr,
374 .flags = I2C_M_RD,
375 .len = 4,
376 .buf = buf,
377 }
378 };
379
380 addr[0] = (reg_addr >> 8);
381 addr[1] = (reg_addr & 0xff);
382 msgs[0].addr = 0x44;
383 msgs[1].addr = 0x44;
384
385 retval = i2c_xfer(client->adapter, msgs, 2);
386
387 v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
388 *value = v;
389
390 return v;
391}
407 392
408int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value) 393int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value)
409{ 394{
410 struct i2c_client *client = &bus->i2c_client; 395 struct i2c_client *client = &bus->i2c_client;
411 int retval = 0; 396 int retval = 0;
412 u8 buf[6] = {0, 0, 0, 0, 0, 0}; 397 u8 buf[6] = { 0, 0, 0, 0, 0, 0 };
413 398
414 struct i2c_msg msgs[1]={ 399 struct i2c_msg msgs[1] = {
415 { 400 {
416 .addr = client->addr, 401 .addr = client->addr,
417 .flags = 0, 402 .flags = 0,
418 .len = 6, 403 .len = 6,
419 .buf = buf, 404 .buf = buf,
420 } 405 }
421 }; 406 };
422 407
423 408 buf[0] = reg_addr >> 8;
424 buf[0] = reg_addr>>8; 409 buf[1] = reg_addr & 0xff;
425 buf[1] = reg_addr & 0xff; 410 buf[5] = (value >> 24) & 0xff;
426 buf[5] = (value>>24) & 0xff; 411 buf[4] = (value >> 16) & 0xff;
427 buf[4] = (value>>16) & 0xff; 412 buf[3] = (value >> 8) & 0xff;
428 buf[3] = (value>>8) & 0xff; 413 buf[2] = value & 0xff;
429 buf[2] = value & 0xff; 414 client->flags = 0;
430 client->flags = 0; 415 msgs[0].addr = 0x44;
431 msgs[0].addr = 0x44; 416
432 417 retval = i2c_xfer(client->adapter, msgs, 1);
433 retval = i2c_xfer(client->adapter, msgs, 1);
434
435 return retval;
436}
437 418
419 return retval;
420}
diff --git a/drivers/staging/cx25821/cx25821-medusa-defines.h b/drivers/staging/cx25821/cx25821-medusa-defines.h
index 75161e488e12..b0d216ba7f81 100644
--- a/drivers/staging/cx25821/cx25821-medusa-defines.h
+++ b/drivers/staging/cx25821/cx25821-medusa-defines.h
@@ -1,51 +1,51 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef _MEDUSA_DEF_H_ 23#ifndef _MEDUSA_DEF_H_
24#define _MEDUSA_DEF_H_ 24#define _MEDUSA_DEF_H_
25 25
26// Video deocder that we supported 26// Video deocder that we supported
27#define VDEC_A 0 27#define VDEC_A 0
28#define VDEC_B 1 28#define VDEC_B 1
29#define VDEC_C 2 29#define VDEC_C 2
30#define VDEC_D 3 30#define VDEC_D 3
31#define VDEC_E 4 31#define VDEC_E 4
32#define VDEC_F 5 32#define VDEC_F 5
33#define VDEC_G 6 33#define VDEC_G 6
34#define VDEC_H 7 34#define VDEC_H 7
35 35
36//#define AUTO_SWITCH_BIT[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; 36//#define AUTO_SWITCH_BIT[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
37 37
38// The following bit position enables automatic source switching for decoder A-H. 38// The following bit position enables automatic source switching for decoder A-H.
39// Display index per camera. 39// Display index per camera.
40//#define VDEC_INDEX[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}; 40//#define VDEC_INDEX[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7};
41 41
42// Select input bit to video decoder A-H. 42// Select input bit to video decoder A-H.
43//#define CH_SRC_SEL_BIT[] = {24, 25, 26, 27, 28, 29, 30, 31}; 43//#define CH_SRC_SEL_BIT[] = {24, 25, 26, 27, 28, 29, 30, 31};
44 44
45// end of display sequence 45// end of display sequence
46#define END_OF_SEQ 0xF; 46#define END_OF_SEQ 0xF;
47 47
48// registry string size 48// registry string size
49#define MAX_REGISTRY_SZ 40; 49#define MAX_REGISTRY_SZ 40;
50 50
51#endif 51#endif
diff --git a/drivers/staging/cx25821/cx25821-medusa-reg.h b/drivers/staging/cx25821/cx25821-medusa-reg.h
index b877cd284aaf..12c90f831b22 100644
--- a/drivers/staging/cx25821/cx25821-medusa-reg.h
+++ b/drivers/staging/cx25821/cx25821-medusa-reg.h
@@ -1,456 +1,455 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef __MEDUSA_REGISTERS__ 23#ifndef __MEDUSA_REGISTERS__
24#define __MEDUSA_REGISTERS__ 24#define __MEDUSA_REGISTERS__
25 25
26// Serial Slave Registers 26// Serial Slave Registers
27#define HOST_REGISTER1 0x0000 27#define HOST_REGISTER1 0x0000
28#define HOST_REGISTER2 0x0001 28#define HOST_REGISTER2 0x0001
29 29
30// Chip Configuration Registers 30// Chip Configuration Registers
31#define CHIP_CTRL 0x0100 31#define CHIP_CTRL 0x0100
32#define AFE_AB_CTRL 0x0104 32#define AFE_AB_CTRL 0x0104
33#define AFE_CD_CTRL 0x0108 33#define AFE_CD_CTRL 0x0108
34#define AFE_EF_CTRL 0x010C 34#define AFE_EF_CTRL 0x010C
35#define AFE_GH_CTRL 0x0110 35#define AFE_GH_CTRL 0x0110
36#define DENC_AB_CTRL 0x0114 36#define DENC_AB_CTRL 0x0114
37#define BYP_AB_CTRL 0x0118 37#define BYP_AB_CTRL 0x0118
38#define MON_A_CTRL 0x011C 38#define MON_A_CTRL 0x011C
39#define DISP_SEQ_A 0x0120 39#define DISP_SEQ_A 0x0120
40#define DISP_SEQ_B 0x0124 40#define DISP_SEQ_B 0x0124
41#define DISP_AB_CNT 0x0128 41#define DISP_AB_CNT 0x0128
42#define DISP_CD_CNT 0x012C 42#define DISP_CD_CNT 0x012C
43#define DISP_EF_CNT 0x0130 43#define DISP_EF_CNT 0x0130
44#define DISP_GH_CNT 0x0134 44#define DISP_GH_CNT 0x0134
45#define DISP_IJ_CNT 0x0138 45#define DISP_IJ_CNT 0x0138
46#define PIN_OE_CTRL 0x013C 46#define PIN_OE_CTRL 0x013C
47#define PIN_SPD_CTRL 0x0140 47#define PIN_SPD_CTRL 0x0140
48#define PIN_SPD_CTRL2 0x0144 48#define PIN_SPD_CTRL2 0x0144
49#define IRQ_STAT_CTRL 0x0148 49#define IRQ_STAT_CTRL 0x0148
50#define POWER_CTRL_AB 0x014C 50#define POWER_CTRL_AB 0x014C
51#define POWER_CTRL_CD 0x0150 51#define POWER_CTRL_CD 0x0150
52#define POWER_CTRL_EF 0x0154 52#define POWER_CTRL_EF 0x0154
53#define POWER_CTRL_GH 0x0158 53#define POWER_CTRL_GH 0x0158
54#define TUNE_CTRL 0x015C 54#define TUNE_CTRL 0x015C
55#define BIAS_CTRL 0x0160 55#define BIAS_CTRL 0x0160
56#define AFE_AB_DIAG_CTRL 0x0164 56#define AFE_AB_DIAG_CTRL 0x0164
57#define AFE_CD_DIAG_CTRL 0x0168 57#define AFE_CD_DIAG_CTRL 0x0168
58#define AFE_EF_DIAG_CTRL 0x016C 58#define AFE_EF_DIAG_CTRL 0x016C
59#define AFE_GH_DIAG_CTRL 0x0170 59#define AFE_GH_DIAG_CTRL 0x0170
60#define PLL_AB_DIAG_CTRL 0x0174 60#define PLL_AB_DIAG_CTRL 0x0174
61#define PLL_CD_DIAG_CTRL 0x0178 61#define PLL_CD_DIAG_CTRL 0x0178
62#define PLL_EF_DIAG_CTRL 0x017C 62#define PLL_EF_DIAG_CTRL 0x017C
63#define PLL_GH_DIAG_CTRL 0x0180 63#define PLL_GH_DIAG_CTRL 0x0180
64#define TEST_CTRL 0x0184 64#define TEST_CTRL 0x0184
65#define BIST_STAT 0x0188 65#define BIST_STAT 0x0188
66#define BIST_STAT2 0x018C 66#define BIST_STAT2 0x018C
67#define BIST_VID_PLL_AB_STAT 0x0190 67#define BIST_VID_PLL_AB_STAT 0x0190
68#define BIST_VID_PLL_CD_STAT 0x0194 68#define BIST_VID_PLL_CD_STAT 0x0194
69#define BIST_VID_PLL_EF_STAT 0x0198 69#define BIST_VID_PLL_EF_STAT 0x0198
70#define BIST_VID_PLL_GH_STAT 0x019C 70#define BIST_VID_PLL_GH_STAT 0x019C
71#define DLL_DIAG_CTRL 0x01A0 71#define DLL_DIAG_CTRL 0x01A0
72#define DEV_CH_ID_CTRL 0x01A4 72#define DEV_CH_ID_CTRL 0x01A4
73#define ABIST_CTRL_STATUS 0x01A8 73#define ABIST_CTRL_STATUS 0x01A8
74#define ABIST_FREQ 0x01AC 74#define ABIST_FREQ 0x01AC
75#define ABIST_GOERT_SHIFT 0x01B0 75#define ABIST_GOERT_SHIFT 0x01B0
76#define ABIST_COEF12 0x01B4 76#define ABIST_COEF12 0x01B4
77#define ABIST_COEF34 0x01B8 77#define ABIST_COEF34 0x01B8
78#define ABIST_COEF56 0x01BC 78#define ABIST_COEF56 0x01BC
79#define ABIST_COEF7_SNR 0x01C0 79#define ABIST_COEF7_SNR 0x01C0
80#define ABIST_ADC_CAL 0x01C4 80#define ABIST_ADC_CAL 0x01C4
81#define ABIST_BIN1_VGA0 0x01C8 81#define ABIST_BIN1_VGA0 0x01C8
82#define ABIST_BIN2_VGA1 0x01CC 82#define ABIST_BIN2_VGA1 0x01CC
83#define ABIST_BIN3_VGA2 0x01D0 83#define ABIST_BIN3_VGA2 0x01D0
84#define ABIST_BIN4_VGA3 0x01D4 84#define ABIST_BIN4_VGA3 0x01D4
85#define ABIST_BIN5_VGA4 0x01D8 85#define ABIST_BIN5_VGA4 0x01D8
86#define ABIST_BIN6_VGA5 0x01DC 86#define ABIST_BIN6_VGA5 0x01DC
87#define ABIST_BIN7_VGA6 0x0x1E0 87#define ABIST_BIN7_VGA6 0x0x1E0
88#define ABIST_CLAMP_A 0x0x1E4 88#define ABIST_CLAMP_A 0x0x1E4
89#define ABIST_CLAMP_B 0x0x1E8 89#define ABIST_CLAMP_B 0x0x1E8
90#define ABIST_CLAMP_C 0x01EC 90#define ABIST_CLAMP_C 0x01EC
91#define ABIST_CLAMP_D 0x01F0 91#define ABIST_CLAMP_D 0x01F0
92#define ABIST_CLAMP_E 0x01F4 92#define ABIST_CLAMP_E 0x01F4
93#define ABIST_CLAMP_F 0x01F8 93#define ABIST_CLAMP_F 0x01F8
94 94
95// Digital Video Encoder A Registers 95// Digital Video Encoder A Registers
96#define DENC_A_REG_1 0x0200 96#define DENC_A_REG_1 0x0200
97#define DENC_A_REG_2 0x0204 97#define DENC_A_REG_2 0x0204
98#define DENC_A_REG_3 0x0208 98#define DENC_A_REG_3 0x0208
99#define DENC_A_REG_4 0x020C 99#define DENC_A_REG_4 0x020C
100#define DENC_A_REG_5 0x0210 100#define DENC_A_REG_5 0x0210
101#define DENC_A_REG_6 0x0214 101#define DENC_A_REG_6 0x0214
102#define DENC_A_REG_7 0x0218 102#define DENC_A_REG_7 0x0218
103#define DENC_A_REG_8 0x021C 103#define DENC_A_REG_8 0x021C
104 104
105// Digital Video Encoder B Registers 105// Digital Video Encoder B Registers
106#define DENC_B_REG_1 0x0300 106#define DENC_B_REG_1 0x0300
107#define DENC_B_REG_2 0x0304 107#define DENC_B_REG_2 0x0304
108#define DENC_B_REG_3 0x0308 108#define DENC_B_REG_3 0x0308
109#define DENC_B_REG_4 0x030C 109#define DENC_B_REG_4 0x030C
110#define DENC_B_REG_5 0x0310 110#define DENC_B_REG_5 0x0310
111#define DENC_B_REG_6 0x0314 111#define DENC_B_REG_6 0x0314
112#define DENC_B_REG_7 0x0318 112#define DENC_B_REG_7 0x0318
113#define DENC_B_REG_8 0x031C 113#define DENC_B_REG_8 0x031C
114 114
115// Video Decoder A Registers 115// Video Decoder A Registers
116#define MODE_CTRL 0x1000 116#define MODE_CTRL 0x1000
117#define OUT_CTRL1 0x1004 117#define OUT_CTRL1 0x1004
118#define OUT_CTRL_NS 0x1008 118#define OUT_CTRL_NS 0x1008
119#define GEN_STAT 0x100C 119#define GEN_STAT 0x100C
120#define INT_STAT_MASK 0x1010 120#define INT_STAT_MASK 0x1010
121#define LUMA_CTRL 0x1014 121#define LUMA_CTRL 0x1014
122#define CHROMA_CTRL 0x1018 122#define CHROMA_CTRL 0x1018
123#define CRUSH_CTRL 0x101C 123#define CRUSH_CTRL 0x101C
124#define HORIZ_TIM_CTRL 0x1020 124#define HORIZ_TIM_CTRL 0x1020
125#define VERT_TIM_CTRL 0x1024 125#define VERT_TIM_CTRL 0x1024
126#define MISC_TIM_CTRL 0x1028 126#define MISC_TIM_CTRL 0x1028
127#define FIELD_COUNT 0x102C 127#define FIELD_COUNT 0x102C
128#define HSCALE_CTRL 0x1030 128#define HSCALE_CTRL 0x1030
129#define VSCALE_CTRL 0x1034 129#define VSCALE_CTRL 0x1034
130#define MAN_VGA_CTRL 0x1038 130#define MAN_VGA_CTRL 0x1038
131#define MAN_AGC_CTRL 0x103C 131#define MAN_AGC_CTRL 0x103C
132#define DFE_CTRL1 0x1040 132#define DFE_CTRL1 0x1040
133#define DFE_CTRL2 0x1044 133#define DFE_CTRL2 0x1044
134#define DFE_CTRL3 0x1048 134#define DFE_CTRL3 0x1048
135#define PLL_CTRL 0x104C 135#define PLL_CTRL 0x104C
136#define PLL_CTRL_FAST 0x1050 136#define PLL_CTRL_FAST 0x1050
137#define HTL_CTRL 0x1054 137#define HTL_CTRL 0x1054
138#define SRC_CFG 0x1058 138#define SRC_CFG 0x1058
139#define SC_STEP_SIZE 0x105C 139#define SC_STEP_SIZE 0x105C
140#define SC_CONVERGE_CTRL 0x1060 140#define SC_CONVERGE_CTRL 0x1060
141#define SC_LOOP_CTRL 0x1064 141#define SC_LOOP_CTRL 0x1064
142#define COMB_2D_HFS_CFG 0x1068 142#define COMB_2D_HFS_CFG 0x1068
143#define COMB_2D_HFD_CFG 0x106C 143#define COMB_2D_HFD_CFG 0x106C
144#define COMB_2D_LF_CFG 0x1070 144#define COMB_2D_LF_CFG 0x1070
145#define COMB_2D_BLEND 0x1074 145#define COMB_2D_BLEND 0x1074
146#define COMB_MISC_CTRL 0x1078 146#define COMB_MISC_CTRL 0x1078
147#define COMB_FLAT_THRESH_CTRL 0x107C 147#define COMB_FLAT_THRESH_CTRL 0x107C
148#define COMB_TEST 0x1080 148#define COMB_TEST 0x1080
149#define BP_MISC_CTRL 0x1084 149#define BP_MISC_CTRL 0x1084
150#define VCR_DET_CTRL 0x1088 150#define VCR_DET_CTRL 0x1088
151#define NOISE_DET_CTRL 0x108C 151#define NOISE_DET_CTRL 0x108C
152#define COMB_FLAT_NOISE_CTRL 0x1090 152#define COMB_FLAT_NOISE_CTRL 0x1090
153#define VERSION 0x11F8 153#define VERSION 0x11F8
154#define SOFT_RST_CTRL 0x11FC 154#define SOFT_RST_CTRL 0x11FC
155 155
156// Video Decoder B Registers 156// Video Decoder B Registers
157#define VDEC_B_MODE_CTRL 0x1200 157#define VDEC_B_MODE_CTRL 0x1200
158#define VDEC_B_OUT_CTRL1 0x1204 158#define VDEC_B_OUT_CTRL1 0x1204
159#define VDEC_B_OUT_CTRL_NS 0x1208 159#define VDEC_B_OUT_CTRL_NS 0x1208
160#define VDEC_B_GEN_STAT 0x120C 160#define VDEC_B_GEN_STAT 0x120C
161#define VDEC_B_INT_STAT_MASK 0x1210 161#define VDEC_B_INT_STAT_MASK 0x1210
162#define VDEC_B_LUMA_CTRL 0x1214 162#define VDEC_B_LUMA_CTRL 0x1214
163#define VDEC_B_CHROMA_CTRL 0x1218 163#define VDEC_B_CHROMA_CTRL 0x1218
164#define VDEC_B_CRUSH_CTRL 0x121C 164#define VDEC_B_CRUSH_CTRL 0x121C
165#define VDEC_B_HORIZ_TIM_CTRL 0x1220 165#define VDEC_B_HORIZ_TIM_CTRL 0x1220
166#define VDEC_B_VERT_TIM_CTRL 0x1224 166#define VDEC_B_VERT_TIM_CTRL 0x1224
167#define VDEC_B_MISC_TIM_CTRL 0x1228 167#define VDEC_B_MISC_TIM_CTRL 0x1228
168#define VDEC_B_FIELD_COUNT 0x122C 168#define VDEC_B_FIELD_COUNT 0x122C
169#define VDEC_B_HSCALE_CTRL 0x1230 169#define VDEC_B_HSCALE_CTRL 0x1230
170#define VDEC_B_VSCALE_CTRL 0x1234 170#define VDEC_B_VSCALE_CTRL 0x1234
171#define VDEC_B_MAN_VGA_CTRL 0x1238 171#define VDEC_B_MAN_VGA_CTRL 0x1238
172#define VDEC_B_MAN_AGC_CTRL 0x123C 172#define VDEC_B_MAN_AGC_CTRL 0x123C
173#define VDEC_B_DFE_CTRL1 0x1240 173#define VDEC_B_DFE_CTRL1 0x1240
174#define VDEC_B_DFE_CTRL2 0x1244 174#define VDEC_B_DFE_CTRL2 0x1244
175#define VDEC_B_DFE_CTRL3 0x1248 175#define VDEC_B_DFE_CTRL3 0x1248
176#define VDEC_B_PLL_CTRL 0x124C 176#define VDEC_B_PLL_CTRL 0x124C
177#define VDEC_B_PLL_CTRL_FAST 0x1250 177#define VDEC_B_PLL_CTRL_FAST 0x1250
178#define VDEC_B_HTL_CTRL 0x1254 178#define VDEC_B_HTL_CTRL 0x1254
179#define VDEC_B_SRC_CFG 0x1258 179#define VDEC_B_SRC_CFG 0x1258
180#define VDEC_B_SC_STEP_SIZE 0x125C 180#define VDEC_B_SC_STEP_SIZE 0x125C
181#define VDEC_B_SC_CONVERGE_CTRL 0x1260 181#define VDEC_B_SC_CONVERGE_CTRL 0x1260
182#define VDEC_B_SC_LOOP_CTRL 0x1264 182#define VDEC_B_SC_LOOP_CTRL 0x1264
183#define VDEC_B_COMB_2D_HFS_CFG 0x1268 183#define VDEC_B_COMB_2D_HFS_CFG 0x1268
184#define VDEC_B_COMB_2D_HFD_CFG 0x126C 184#define VDEC_B_COMB_2D_HFD_CFG 0x126C
185#define VDEC_B_COMB_2D_LF_CFG 0x1270 185#define VDEC_B_COMB_2D_LF_CFG 0x1270
186#define VDEC_B_COMB_2D_BLEND 0x1274 186#define VDEC_B_COMB_2D_BLEND 0x1274
187#define VDEC_B_COMB_MISC_CTRL 0x1278 187#define VDEC_B_COMB_MISC_CTRL 0x1278
188#define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C 188#define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C
189#define VDEC_B_COMB_TEST 0x1280 189#define VDEC_B_COMB_TEST 0x1280
190#define VDEC_B_BP_MISC_CTRL 0x1284 190#define VDEC_B_BP_MISC_CTRL 0x1284
191#define VDEC_B_VCR_DET_CTRL 0x1288 191#define VDEC_B_VCR_DET_CTRL 0x1288
192#define VDEC_B_NOISE_DET_CTRL 0x128C 192#define VDEC_B_NOISE_DET_CTRL 0x128C
193#define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290 193#define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290
194#define VDEC_B_VERSION 0x13F8 194#define VDEC_B_VERSION 0x13F8
195#define VDEC_B_SOFT_RST_CTRL 0x13FC 195#define VDEC_B_SOFT_RST_CTRL 0x13FC
196 196
197// Video Decoder C Registers 197// Video Decoder C Registers
198#define VDEC_C_MODE_CTRL 0x1400 198#define VDEC_C_MODE_CTRL 0x1400
199#define VDEC_C_OUT_CTRL1 0x1404 199#define VDEC_C_OUT_CTRL1 0x1404
200#define VDEC_C_OUT_CTRL_NS 0x1408 200#define VDEC_C_OUT_CTRL_NS 0x1408
201#define VDEC_C_GEN_STAT 0x140C 201#define VDEC_C_GEN_STAT 0x140C
202#define VDEC_C_INT_STAT_MASK 0x1410 202#define VDEC_C_INT_STAT_MASK 0x1410
203#define VDEC_C_LUMA_CTRL 0x1414 203#define VDEC_C_LUMA_CTRL 0x1414
204#define VDEC_C_CHROMA_CTRL 0x1418 204#define VDEC_C_CHROMA_CTRL 0x1418
205#define VDEC_C_CRUSH_CTRL 0x141C 205#define VDEC_C_CRUSH_CTRL 0x141C
206#define VDEC_C_HORIZ_TIM_CTRL 0x1420 206#define VDEC_C_HORIZ_TIM_CTRL 0x1420
207#define VDEC_C_VERT_TIM_CTRL 0x1424 207#define VDEC_C_VERT_TIM_CTRL 0x1424
208#define VDEC_C_MISC_TIM_CTRL 0x1428 208#define VDEC_C_MISC_TIM_CTRL 0x1428
209#define VDEC_C_FIELD_COUNT 0x142C 209#define VDEC_C_FIELD_COUNT 0x142C
210#define VDEC_C_HSCALE_CTRL 0x1430 210#define VDEC_C_HSCALE_CTRL 0x1430
211#define VDEC_C_VSCALE_CTRL 0x1434 211#define VDEC_C_VSCALE_CTRL 0x1434
212#define VDEC_C_MAN_VGA_CTRL 0x1438 212#define VDEC_C_MAN_VGA_CTRL 0x1438
213#define VDEC_C_MAN_AGC_CTRL 0x143C 213#define VDEC_C_MAN_AGC_CTRL 0x143C
214#define VDEC_C_DFE_CTRL1 0x1440 214#define VDEC_C_DFE_CTRL1 0x1440
215#define VDEC_C_DFE_CTRL2 0x1444 215#define VDEC_C_DFE_CTRL2 0x1444
216#define VDEC_C_DFE_CTRL3 0x1448 216#define VDEC_C_DFE_CTRL3 0x1448
217#define VDEC_C_PLL_CTRL 0x144C 217#define VDEC_C_PLL_CTRL 0x144C
218#define VDEC_C_PLL_CTRL_FAST 0x1450 218#define VDEC_C_PLL_CTRL_FAST 0x1450
219#define VDEC_C_HTL_CTRL 0x1454 219#define VDEC_C_HTL_CTRL 0x1454
220#define VDEC_C_SRC_CFG 0x1458 220#define VDEC_C_SRC_CFG 0x1458
221#define VDEC_C_SC_STEP_SIZE 0x145C 221#define VDEC_C_SC_STEP_SIZE 0x145C
222#define VDEC_C_SC_CONVERGE_CTRL 0x1460 222#define VDEC_C_SC_CONVERGE_CTRL 0x1460
223#define VDEC_C_SC_LOOP_CTRL 0x1464 223#define VDEC_C_SC_LOOP_CTRL 0x1464
224#define VDEC_C_COMB_2D_HFS_CFG 0x1468 224#define VDEC_C_COMB_2D_HFS_CFG 0x1468
225#define VDEC_C_COMB_2D_HFD_CFG 0x146C 225#define VDEC_C_COMB_2D_HFD_CFG 0x146C
226#define VDEC_C_COMB_2D_LF_CFG 0x1470 226#define VDEC_C_COMB_2D_LF_CFG 0x1470
227#define VDEC_C_COMB_2D_BLEND 0x1474 227#define VDEC_C_COMB_2D_BLEND 0x1474
228#define VDEC_C_COMB_MISC_CTRL 0x1478 228#define VDEC_C_COMB_MISC_CTRL 0x1478
229#define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C 229#define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C
230#define VDEC_C_COMB_TEST 0x1480 230#define VDEC_C_COMB_TEST 0x1480
231#define VDEC_C_BP_MISC_CTRL 0x1484 231#define VDEC_C_BP_MISC_CTRL 0x1484
232#define VDEC_C_VCR_DET_CTRL 0x1488 232#define VDEC_C_VCR_DET_CTRL 0x1488
233#define VDEC_C_NOISE_DET_CTRL 0x148C 233#define VDEC_C_NOISE_DET_CTRL 0x148C
234#define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490 234#define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490
235#define VDEC_C_VERSION 0x15F8 235#define VDEC_C_VERSION 0x15F8
236#define VDEC_C_SOFT_RST_CTRL 0x15FC 236#define VDEC_C_SOFT_RST_CTRL 0x15FC
237 237
238// Video Decoder D Registers 238// Video Decoder D Registers
239#define VDEC_D_MODE_CTRL 0x1600 239#define VDEC_D_MODE_CTRL 0x1600
240#define VDEC_D_OUT_CTRL1 0x1604 240#define VDEC_D_OUT_CTRL1 0x1604
241#define VDEC_D_OUT_CTRL_NS 0x1608 241#define VDEC_D_OUT_CTRL_NS 0x1608
242#define VDEC_D_GEN_STAT 0x160C 242#define VDEC_D_GEN_STAT 0x160C
243#define VDEC_D_INT_STAT_MASK 0x1610 243#define VDEC_D_INT_STAT_MASK 0x1610
244#define VDEC_D_LUMA_CTRL 0x1614 244#define VDEC_D_LUMA_CTRL 0x1614
245#define VDEC_D_CHROMA_CTRL 0x1618 245#define VDEC_D_CHROMA_CTRL 0x1618
246#define VDEC_D_CRUSH_CTRL 0x161C 246#define VDEC_D_CRUSH_CTRL 0x161C
247#define VDEC_D_HORIZ_TIM_CTRL 0x1620 247#define VDEC_D_HORIZ_TIM_CTRL 0x1620
248#define VDEC_D_VERT_TIM_CTRL 0x1624 248#define VDEC_D_VERT_TIM_CTRL 0x1624
249#define VDEC_D_MISC_TIM_CTRL 0x1628 249#define VDEC_D_MISC_TIM_CTRL 0x1628
250#define VDEC_D_FIELD_COUNT 0x162C 250#define VDEC_D_FIELD_COUNT 0x162C
251#define VDEC_D_HSCALE_CTRL 0x1630 251#define VDEC_D_HSCALE_CTRL 0x1630
252#define VDEC_D_VSCALE_CTRL 0x1634 252#define VDEC_D_VSCALE_CTRL 0x1634
253#define VDEC_D_MAN_VGA_CTRL 0x1638 253#define VDEC_D_MAN_VGA_CTRL 0x1638
254#define VDEC_D_MAN_AGC_CTRL 0x163C 254#define VDEC_D_MAN_AGC_CTRL 0x163C
255#define VDEC_D_DFE_CTRL1 0x1640 255#define VDEC_D_DFE_CTRL1 0x1640
256#define VDEC_D_DFE_CTRL2 0x1644 256#define VDEC_D_DFE_CTRL2 0x1644
257#define VDEC_D_DFE_CTRL3 0x1648 257#define VDEC_D_DFE_CTRL3 0x1648
258#define VDEC_D_PLL_CTRL 0x164C 258#define VDEC_D_PLL_CTRL 0x164C
259#define VDEC_D_PLL_CTRL_FAST 0x1650 259#define VDEC_D_PLL_CTRL_FAST 0x1650
260#define VDEC_D_HTL_CTRL 0x1654 260#define VDEC_D_HTL_CTRL 0x1654
261#define VDEC_D_SRC_CFG 0x1658 261#define VDEC_D_SRC_CFG 0x1658
262#define VDEC_D_SC_STEP_SIZE 0x165C 262#define VDEC_D_SC_STEP_SIZE 0x165C
263#define VDEC_D_SC_CONVERGE_CTRL 0x1660 263#define VDEC_D_SC_CONVERGE_CTRL 0x1660
264#define VDEC_D_SC_LOOP_CTRL 0x1664 264#define VDEC_D_SC_LOOP_CTRL 0x1664
265#define VDEC_D_COMB_2D_HFS_CFG 0x1668 265#define VDEC_D_COMB_2D_HFS_CFG 0x1668
266#define VDEC_D_COMB_2D_HFD_CFG 0x166C 266#define VDEC_D_COMB_2D_HFD_CFG 0x166C
267#define VDEC_D_COMB_2D_LF_CFG 0x1670 267#define VDEC_D_COMB_2D_LF_CFG 0x1670
268#define VDEC_D_COMB_2D_BLEND 0x1674 268#define VDEC_D_COMB_2D_BLEND 0x1674
269#define VDEC_D_COMB_MISC_CTRL 0x1678 269#define VDEC_D_COMB_MISC_CTRL 0x1678
270#define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C 270#define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C
271#define VDEC_D_COMB_TEST 0x1680 271#define VDEC_D_COMB_TEST 0x1680
272#define VDEC_D_BP_MISC_CTRL 0x1684 272#define VDEC_D_BP_MISC_CTRL 0x1684
273#define VDEC_D_VCR_DET_CTRL 0x1688 273#define VDEC_D_VCR_DET_CTRL 0x1688
274#define VDEC_D_NOISE_DET_CTRL 0x168C 274#define VDEC_D_NOISE_DET_CTRL 0x168C
275#define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690 275#define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690
276#define VDEC_D_VERSION 0x17F8 276#define VDEC_D_VERSION 0x17F8
277#define VDEC_D_SOFT_RST_CTRL 0x17FC 277#define VDEC_D_SOFT_RST_CTRL 0x17FC
278 278
279// Video Decoder E Registers 279// Video Decoder E Registers
280#define VDEC_E_MODE_CTRL 0x1800 280#define VDEC_E_MODE_CTRL 0x1800
281#define VDEC_E_OUT_CTRL1 0x1804 281#define VDEC_E_OUT_CTRL1 0x1804
282#define VDEC_E_OUT_CTRL_NS 0x1808 282#define VDEC_E_OUT_CTRL_NS 0x1808
283#define VDEC_E_GEN_STAT 0x180C 283#define VDEC_E_GEN_STAT 0x180C
284#define VDEC_E_INT_STAT_MASK 0x1810 284#define VDEC_E_INT_STAT_MASK 0x1810
285#define VDEC_E_LUMA_CTRL 0x1814 285#define VDEC_E_LUMA_CTRL 0x1814
286#define VDEC_E_CHROMA_CTRL 0x1818 286#define VDEC_E_CHROMA_CTRL 0x1818
287#define VDEC_E_CRUSH_CTRL 0x181C 287#define VDEC_E_CRUSH_CTRL 0x181C
288#define VDEC_E_HORIZ_TIM_CTRL 0x1820 288#define VDEC_E_HORIZ_TIM_CTRL 0x1820
289#define VDEC_E_VERT_TIM_CTRL 0x1824 289#define VDEC_E_VERT_TIM_CTRL 0x1824
290#define VDEC_E_MISC_TIM_CTRL 0x1828 290#define VDEC_E_MISC_TIM_CTRL 0x1828
291#define VDEC_E_FIELD_COUNT 0x182C 291#define VDEC_E_FIELD_COUNT 0x182C
292#define VDEC_E_HSCALE_CTRL 0x1830 292#define VDEC_E_HSCALE_CTRL 0x1830
293#define VDEC_E_VSCALE_CTRL 0x1834 293#define VDEC_E_VSCALE_CTRL 0x1834
294#define VDEC_E_MAN_VGA_CTRL 0x1838 294#define VDEC_E_MAN_VGA_CTRL 0x1838
295#define VDEC_E_MAN_AGC_CTRL 0x183C 295#define VDEC_E_MAN_AGC_CTRL 0x183C
296#define VDEC_E_DFE_CTRL1 0x1840 296#define VDEC_E_DFE_CTRL1 0x1840
297#define VDEC_E_DFE_CTRL2 0x1844 297#define VDEC_E_DFE_CTRL2 0x1844
298#define VDEC_E_DFE_CTRL3 0x1848 298#define VDEC_E_DFE_CTRL3 0x1848
299#define VDEC_E_PLL_CTRL 0x184C 299#define VDEC_E_PLL_CTRL 0x184C
300#define VDEC_E_PLL_CTRL_FAST 0x1850 300#define VDEC_E_PLL_CTRL_FAST 0x1850
301#define VDEC_E_HTL_CTRL 0x1854 301#define VDEC_E_HTL_CTRL 0x1854
302#define VDEC_E_SRC_CFG 0x1858 302#define VDEC_E_SRC_CFG 0x1858
303#define VDEC_E_SC_STEP_SIZE 0x185C 303#define VDEC_E_SC_STEP_SIZE 0x185C
304#define VDEC_E_SC_CONVERGE_CTRL 0x1860 304#define VDEC_E_SC_CONVERGE_CTRL 0x1860
305#define VDEC_E_SC_LOOP_CTRL 0x1864 305#define VDEC_E_SC_LOOP_CTRL 0x1864
306#define VDEC_E_COMB_2D_HFS_CFG 0x1868 306#define VDEC_E_COMB_2D_HFS_CFG 0x1868
307#define VDEC_E_COMB_2D_HFD_CFG 0x186C 307#define VDEC_E_COMB_2D_HFD_CFG 0x186C
308#define VDEC_E_COMB_2D_LF_CFG 0x1870 308#define VDEC_E_COMB_2D_LF_CFG 0x1870
309#define VDEC_E_COMB_2D_BLEND 0x1874 309#define VDEC_E_COMB_2D_BLEND 0x1874
310#define VDEC_E_COMB_MISC_CTRL 0x1878 310#define VDEC_E_COMB_MISC_CTRL 0x1878
311#define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C 311#define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C
312#define VDEC_E_COMB_TEST 0x1880 312#define VDEC_E_COMB_TEST 0x1880
313#define VDEC_E_BP_MISC_CTRL 0x1884 313#define VDEC_E_BP_MISC_CTRL 0x1884
314#define VDEC_E_VCR_DET_CTRL 0x1888 314#define VDEC_E_VCR_DET_CTRL 0x1888
315#define VDEC_E_NOISE_DET_CTRL 0x188C 315#define VDEC_E_NOISE_DET_CTRL 0x188C
316#define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890 316#define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890
317#define VDEC_E_VERSION 0x19F8 317#define VDEC_E_VERSION 0x19F8
318#define VDEC_E_SOFT_RST_CTRL 0x19FC 318#define VDEC_E_SOFT_RST_CTRL 0x19FC
319 319
320// Video Decoder F Registers 320// Video Decoder F Registers
321#define VDEC_F_MODE_CTRL 0x1A00 321#define VDEC_F_MODE_CTRL 0x1A00
322#define VDEC_F_OUT_CTRL1 0x1A04 322#define VDEC_F_OUT_CTRL1 0x1A04
323#define VDEC_F_OUT_CTRL_NS 0x1A08 323#define VDEC_F_OUT_CTRL_NS 0x1A08
324#define VDEC_F_GEN_STAT 0x1A0C 324#define VDEC_F_GEN_STAT 0x1A0C
325#define VDEC_F_INT_STAT_MASK 0x1A10 325#define VDEC_F_INT_STAT_MASK 0x1A10
326#define VDEC_F_LUMA_CTRL 0x1A14 326#define VDEC_F_LUMA_CTRL 0x1A14
327#define VDEC_F_CHROMA_CTRL 0x1A18 327#define VDEC_F_CHROMA_CTRL 0x1A18
328#define VDEC_F_CRUSH_CTRL 0x1A1C 328#define VDEC_F_CRUSH_CTRL 0x1A1C
329#define VDEC_F_HORIZ_TIM_CTRL 0x1A20 329#define VDEC_F_HORIZ_TIM_CTRL 0x1A20
330#define VDEC_F_VERT_TIM_CTRL 0x1A24 330#define VDEC_F_VERT_TIM_CTRL 0x1A24
331#define VDEC_F_MISC_TIM_CTRL 0x1A28 331#define VDEC_F_MISC_TIM_CTRL 0x1A28
332#define VDEC_F_FIELD_COUNT 0x1A2C 332#define VDEC_F_FIELD_COUNT 0x1A2C
333#define VDEC_F_HSCALE_CTRL 0x1A30 333#define VDEC_F_HSCALE_CTRL 0x1A30
334#define VDEC_F_VSCALE_CTRL 0x1A34 334#define VDEC_F_VSCALE_CTRL 0x1A34
335#define VDEC_F_MAN_VGA_CTRL 0x1A38 335#define VDEC_F_MAN_VGA_CTRL 0x1A38
336#define VDEC_F_MAN_AGC_CTRL 0x1A3C 336#define VDEC_F_MAN_AGC_CTRL 0x1A3C
337#define VDEC_F_DFE_CTRL1 0x1A40 337#define VDEC_F_DFE_CTRL1 0x1A40
338#define VDEC_F_DFE_CTRL2 0x1A44 338#define VDEC_F_DFE_CTRL2 0x1A44
339#define VDEC_F_DFE_CTRL3 0x1A48 339#define VDEC_F_DFE_CTRL3 0x1A48
340#define VDEC_F_PLL_CTRL 0x1A4C 340#define VDEC_F_PLL_CTRL 0x1A4C
341#define VDEC_F_PLL_CTRL_FAST 0x1A50 341#define VDEC_F_PLL_CTRL_FAST 0x1A50
342#define VDEC_F_HTL_CTRL 0x1A54 342#define VDEC_F_HTL_CTRL 0x1A54
343#define VDEC_F_SRC_CFG 0x1A58 343#define VDEC_F_SRC_CFG 0x1A58
344#define VDEC_F_SC_STEP_SIZE 0x1A5C 344#define VDEC_F_SC_STEP_SIZE 0x1A5C
345#define VDEC_F_SC_CONVERGE_CTRL 0x1A60 345#define VDEC_F_SC_CONVERGE_CTRL 0x1A60
346#define VDEC_F_SC_LOOP_CTRL 0x1A64 346#define VDEC_F_SC_LOOP_CTRL 0x1A64
347#define VDEC_F_COMB_2D_HFS_CFG 0x1A68 347#define VDEC_F_COMB_2D_HFS_CFG 0x1A68
348#define VDEC_F_COMB_2D_HFD_CFG 0x1A6C 348#define VDEC_F_COMB_2D_HFD_CFG 0x1A6C
349#define VDEC_F_COMB_2D_LF_CFG 0x1A70 349#define VDEC_F_COMB_2D_LF_CFG 0x1A70
350#define VDEC_F_COMB_2D_BLEND 0x1A74 350#define VDEC_F_COMB_2D_BLEND 0x1A74
351#define VDEC_F_COMB_MISC_CTRL 0x1A78 351#define VDEC_F_COMB_MISC_CTRL 0x1A78
352#define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C 352#define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C
353#define VDEC_F_COMB_TEST 0x1A80 353#define VDEC_F_COMB_TEST 0x1A80
354#define VDEC_F_BP_MISC_CTRL 0x1A84 354#define VDEC_F_BP_MISC_CTRL 0x1A84
355#define VDEC_F_VCR_DET_CTRL 0x1A88 355#define VDEC_F_VCR_DET_CTRL 0x1A88
356#define VDEC_F_NOISE_DET_CTRL 0x1A8C 356#define VDEC_F_NOISE_DET_CTRL 0x1A8C
357#define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90 357#define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90
358#define VDEC_F_VERSION 0x1BF8 358#define VDEC_F_VERSION 0x1BF8
359#define VDEC_F_SOFT_RST_CTRL 0x1BFC 359#define VDEC_F_SOFT_RST_CTRL 0x1BFC
360 360
361// Video Decoder G Registers 361// Video Decoder G Registers
362#define VDEC_G_MODE_CTRL 0x1C00 362#define VDEC_G_MODE_CTRL 0x1C00
363#define VDEC_G_OUT_CTRL1 0x1C04 363#define VDEC_G_OUT_CTRL1 0x1C04
364#define VDEC_G_OUT_CTRL_NS 0x1C08 364#define VDEC_G_OUT_CTRL_NS 0x1C08
365#define VDEC_G_GEN_STAT 0x1C0C 365#define VDEC_G_GEN_STAT 0x1C0C
366#define VDEC_G_INT_STAT_MASK 0x1C10 366#define VDEC_G_INT_STAT_MASK 0x1C10
367#define VDEC_G_LUMA_CTRL 0x1C14 367#define VDEC_G_LUMA_CTRL 0x1C14
368#define VDEC_G_CHROMA_CTRL 0x1C18 368#define VDEC_G_CHROMA_CTRL 0x1C18
369#define VDEC_G_CRUSH_CTRL 0x1C1C 369#define VDEC_G_CRUSH_CTRL 0x1C1C
370#define VDEC_G_HORIZ_TIM_CTRL 0x1C20 370#define VDEC_G_HORIZ_TIM_CTRL 0x1C20
371#define VDEC_G_VERT_TIM_CTRL 0x1C24 371#define VDEC_G_VERT_TIM_CTRL 0x1C24
372#define VDEC_G_MISC_TIM_CTRL 0x1C28 372#define VDEC_G_MISC_TIM_CTRL 0x1C28
373#define VDEC_G_FIELD_COUNT 0x1C2C 373#define VDEC_G_FIELD_COUNT 0x1C2C
374#define VDEC_G_HSCALE_CTRL 0x1C30 374#define VDEC_G_HSCALE_CTRL 0x1C30
375#define VDEC_G_VSCALE_CTRL 0x1C34 375#define VDEC_G_VSCALE_CTRL 0x1C34
376#define VDEC_G_MAN_VGA_CTRL 0x1C38 376#define VDEC_G_MAN_VGA_CTRL 0x1C38
377#define VDEC_G_MAN_AGC_CTRL 0x1C3C 377#define VDEC_G_MAN_AGC_CTRL 0x1C3C
378#define VDEC_G_DFE_CTRL1 0x1C40 378#define VDEC_G_DFE_CTRL1 0x1C40
379#define VDEC_G_DFE_CTRL2 0x1C44 379#define VDEC_G_DFE_CTRL2 0x1C44
380#define VDEC_G_DFE_CTRL3 0x1C48 380#define VDEC_G_DFE_CTRL3 0x1C48
381#define VDEC_G_PLL_CTRL 0x1C4C 381#define VDEC_G_PLL_CTRL 0x1C4C
382#define VDEC_G_PLL_CTRL_FAST 0x1C50 382#define VDEC_G_PLL_CTRL_FAST 0x1C50
383#define VDEC_G_HTL_CTRL 0x1C54 383#define VDEC_G_HTL_CTRL 0x1C54
384#define VDEC_G_SRC_CFG 0x1C58 384#define VDEC_G_SRC_CFG 0x1C58
385#define VDEC_G_SC_STEP_SIZE 0x1C5C 385#define VDEC_G_SC_STEP_SIZE 0x1C5C
386#define VDEC_G_SC_CONVERGE_CTRL 0x1C60 386#define VDEC_G_SC_CONVERGE_CTRL 0x1C60
387#define VDEC_G_SC_LOOP_CTRL 0x1C64 387#define VDEC_G_SC_LOOP_CTRL 0x1C64
388#define VDEC_G_COMB_2D_HFS_CFG 0x1C68 388#define VDEC_G_COMB_2D_HFS_CFG 0x1C68
389#define VDEC_G_COMB_2D_HFD_CFG 0x1C6C 389#define VDEC_G_COMB_2D_HFD_CFG 0x1C6C
390#define VDEC_G_COMB_2D_LF_CFG 0x1C70 390#define VDEC_G_COMB_2D_LF_CFG 0x1C70
391#define VDEC_G_COMB_2D_BLEND 0x1C74 391#define VDEC_G_COMB_2D_BLEND 0x1C74
392#define VDEC_G_COMB_MISC_CTRL 0x1C78 392#define VDEC_G_COMB_MISC_CTRL 0x1C78
393#define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C 393#define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C
394#define VDEC_G_COMB_TEST 0x1C80 394#define VDEC_G_COMB_TEST 0x1C80
395#define VDEC_G_BP_MISC_CTRL 0x1C84 395#define VDEC_G_BP_MISC_CTRL 0x1C84
396#define VDEC_G_VCR_DET_CTRL 0x1C88 396#define VDEC_G_VCR_DET_CTRL 0x1C88
397#define VDEC_G_NOISE_DET_CTRL 0x1C8C 397#define VDEC_G_NOISE_DET_CTRL 0x1C8C
398#define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90 398#define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90
399#define VDEC_G_VERSION 0x1DF8 399#define VDEC_G_VERSION 0x1DF8
400#define VDEC_G_SOFT_RST_CTRL 0x1DFC 400#define VDEC_G_SOFT_RST_CTRL 0x1DFC
401 401
402// Video Decoder H Registers 402// Video Decoder H Registers
403#define VDEC_H_MODE_CTRL 0x1E00 403#define VDEC_H_MODE_CTRL 0x1E00
404#define VDEC_H_OUT_CTRL1 0x1E04 404#define VDEC_H_OUT_CTRL1 0x1E04
405#define VDEC_H_OUT_CTRL_NS 0x1E08 405#define VDEC_H_OUT_CTRL_NS 0x1E08
406#define VDEC_H_GEN_STAT 0x1E0C 406#define VDEC_H_GEN_STAT 0x1E0C
407#define VDEC_H_INT_STAT_MASK 0x1E1E 407#define VDEC_H_INT_STAT_MASK 0x1E1E
408#define VDEC_H_LUMA_CTRL 0x1E14 408#define VDEC_H_LUMA_CTRL 0x1E14
409#define VDEC_H_CHROMA_CTRL 0x1E18 409#define VDEC_H_CHROMA_CTRL 0x1E18
410#define VDEC_H_CRUSH_CTRL 0x1E1C 410#define VDEC_H_CRUSH_CTRL 0x1E1C
411#define VDEC_H_HORIZ_TIM_CTRL 0x1E20 411#define VDEC_H_HORIZ_TIM_CTRL 0x1E20
412#define VDEC_H_VERT_TIM_CTRL 0x1E24 412#define VDEC_H_VERT_TIM_CTRL 0x1E24
413#define VDEC_H_MISC_TIM_CTRL 0x1E28 413#define VDEC_H_MISC_TIM_CTRL 0x1E28
414#define VDEC_H_FIELD_COUNT 0x1E2C 414#define VDEC_H_FIELD_COUNT 0x1E2C
415#define VDEC_H_HSCALE_CTRL 0x1E30 415#define VDEC_H_HSCALE_CTRL 0x1E30
416#define VDEC_H_VSCALE_CTRL 0x1E34 416#define VDEC_H_VSCALE_CTRL 0x1E34
417#define VDEC_H_MAN_VGA_CTRL 0x1E38 417#define VDEC_H_MAN_VGA_CTRL 0x1E38
418#define VDEC_H_MAN_AGC_CTRL 0x1E3C 418#define VDEC_H_MAN_AGC_CTRL 0x1E3C
419#define VDEC_H_DFE_CTRL1 0x1E40 419#define VDEC_H_DFE_CTRL1 0x1E40
420#define VDEC_H_DFE_CTRL2 0x1E44 420#define VDEC_H_DFE_CTRL2 0x1E44
421#define VDEC_H_DFE_CTRL3 0x1E48 421#define VDEC_H_DFE_CTRL3 0x1E48
422#define VDEC_H_PLL_CTRL 0x1E4C 422#define VDEC_H_PLL_CTRL 0x1E4C
423#define VDEC_H_PLL_CTRL_FAST 0x1E50 423#define VDEC_H_PLL_CTRL_FAST 0x1E50
424#define VDEC_H_HTL_CTRL 0x1E54 424#define VDEC_H_HTL_CTRL 0x1E54
425#define VDEC_H_SRC_CFG 0x1E58 425#define VDEC_H_SRC_CFG 0x1E58
426#define VDEC_H_SC_STEP_SIZE 0x1E5C 426#define VDEC_H_SC_STEP_SIZE 0x1E5C
427#define VDEC_H_SC_CONVERGE_CTRL 0x1E60 427#define VDEC_H_SC_CONVERGE_CTRL 0x1E60
428#define VDEC_H_SC_LOOP_CTRL 0x1E64 428#define VDEC_H_SC_LOOP_CTRL 0x1E64
429#define VDEC_H_COMB_2D_HFS_CFG 0x1E68 429#define VDEC_H_COMB_2D_HFS_CFG 0x1E68
430#define VDEC_H_COMB_2D_HFD_CFG 0x1E6C 430#define VDEC_H_COMB_2D_HFD_CFG 0x1E6C
431#define VDEC_H_COMB_2D_LF_CFG 0x1E70 431#define VDEC_H_COMB_2D_LF_CFG 0x1E70
432#define VDEC_H_COMB_2D_BLEND 0x1E74 432#define VDEC_H_COMB_2D_BLEND 0x1E74
433#define VDEC_H_COMB_MISC_CTRL 0x1E78 433#define VDEC_H_COMB_MISC_CTRL 0x1E78
434#define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C 434#define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C
435#define VDEC_H_COMB_TEST 0x1E80 435#define VDEC_H_COMB_TEST 0x1E80
436#define VDEC_H_BP_MISC_CTRL 0x1E84 436#define VDEC_H_BP_MISC_CTRL 0x1E84
437#define VDEC_H_VCR_DET_CTRL 0x1E88 437#define VDEC_H_VCR_DET_CTRL 0x1E88
438#define VDEC_H_NOISE_DET_CTRL 0x1E8C 438#define VDEC_H_NOISE_DET_CTRL 0x1E8C
439#define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90 439#define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90
440#define VDEC_H_VERSION 0x1FF8 440#define VDEC_H_VERSION 0x1FF8
441#define VDEC_H_SOFT_RST_CTRL 0x1FFC 441#define VDEC_H_SOFT_RST_CTRL 0x1FFC
442 442
443//***************************************************************************** 443//*****************************************************************************
444// LUMA_CTRL register fields 444// LUMA_CTRL register fields
445#define VDEC_A_BRITE_CTRL 0x1014 445#define VDEC_A_BRITE_CTRL 0x1014
446#define VDEC_A_CNTRST_CTRL 0x1015 446#define VDEC_A_CNTRST_CTRL 0x1015
447#define VDEC_A_PEAK_SEL 0x1016 447#define VDEC_A_PEAK_SEL 0x1016
448 448
449//***************************************************************************** 449//*****************************************************************************
450// CHROMA_CTRL register fields 450// CHROMA_CTRL register fields
451#define VDEC_A_USAT_CTRL 0x1018 451#define VDEC_A_USAT_CTRL 0x1018
452#define VDEC_A_VSAT_CTRL 0x1019 452#define VDEC_A_VSAT_CTRL 0x1019
453#define VDEC_A_HUE_CTRL 0x101A 453#define VDEC_A_HUE_CTRL 0x101A
454 454
455
456#endif 455#endif
diff --git a/drivers/staging/cx25821/cx25821-medusa-video.c b/drivers/staging/cx25821/cx25821-medusa-video.c
index 84c68b3c5b59..e4df8134f059 100644
--- a/drivers/staging/cx25821/cx25821-medusa-video.c
+++ b/drivers/staging/cx25821/cx25821-medusa-video.c
@@ -24,746 +24,846 @@
24#include "cx25821-medusa-video.h" 24#include "cx25821-medusa-video.h"
25#include "cx25821-biffuncs.h" 25#include "cx25821-biffuncs.h"
26 26
27
28///////////////////////////////////////////////////////////////////////////////////////// 27/////////////////////////////////////////////////////////////////////////////////////////
29//medusa_enable_bluefield_output() 28//medusa_enable_bluefield_output()
30// 29//
31// Enable the generation of blue filed output if no video 30// Enable the generation of blue filed output if no video
32// 31//
33static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel, int enable) 32static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
33 int enable)
34{ 34{
35 int ret_val = 1; 35 int ret_val = 1;
36 u32 value = 0; 36 u32 value = 0;
37 u32 tmp = 0; 37 u32 tmp = 0;
38 int out_ctrl = OUT_CTRL1; 38 int out_ctrl = OUT_CTRL1;
39 int out_ctrl_ns = OUT_CTRL_NS; 39 int out_ctrl_ns = OUT_CTRL_NS;
40
41 40
42 switch (channel) 41 switch (channel) {
43 {
44 default: 42 default:
45 case VDEC_A: 43 case VDEC_A:
46 break; 44 break;
47 case VDEC_B: 45 case VDEC_B:
48 out_ctrl = VDEC_B_OUT_CTRL1; 46 out_ctrl = VDEC_B_OUT_CTRL1;
49 out_ctrl_ns = VDEC_B_OUT_CTRL_NS; 47 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
50 break; 48 break;
51 case VDEC_C: 49 case VDEC_C:
52 out_ctrl = VDEC_C_OUT_CTRL1; 50 out_ctrl = VDEC_C_OUT_CTRL1;
53 out_ctrl_ns = VDEC_C_OUT_CTRL_NS; 51 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
54 break; 52 break;
55 case VDEC_D: 53 case VDEC_D:
56 out_ctrl = VDEC_D_OUT_CTRL1; 54 out_ctrl = VDEC_D_OUT_CTRL1;
57 out_ctrl_ns = VDEC_D_OUT_CTRL_NS; 55 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
58 break; 56 break;
59 case VDEC_E: 57 case VDEC_E:
60 out_ctrl = VDEC_E_OUT_CTRL1; 58 out_ctrl = VDEC_E_OUT_CTRL1;
61 out_ctrl_ns = VDEC_E_OUT_CTRL_NS; 59 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
62 return; 60 return;
63 case VDEC_F: 61 case VDEC_F:
64 out_ctrl = VDEC_F_OUT_CTRL1; 62 out_ctrl = VDEC_F_OUT_CTRL1;
65 out_ctrl_ns = VDEC_F_OUT_CTRL_NS; 63 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
66 return; 64 return;
67 case VDEC_G: 65 case VDEC_G:
68 out_ctrl = VDEC_G_OUT_CTRL1; 66 out_ctrl = VDEC_G_OUT_CTRL1;
69 out_ctrl_ns = VDEC_G_OUT_CTRL_NS; 67 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
70 return; 68 return;
71 case VDEC_H: 69 case VDEC_H:
72 out_ctrl = VDEC_H_OUT_CTRL1; 70 out_ctrl = VDEC_H_OUT_CTRL1;
73 out_ctrl_ns = VDEC_H_OUT_CTRL_NS; 71 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
74 return; 72 return;
75 } 73 }
76 74
77 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); 75 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
78 value &= 0xFFFFFF7F; // clear BLUE_FIELD_EN 76 value &= 0xFFFFFF7F; // clear BLUE_FIELD_EN
79 if (enable) 77 if (enable)
80 value |= 0x00000080; // set BLUE_FIELD_EN 78 value |= 0x00000080; // set BLUE_FIELD_EN
81 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); 79 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
82 80
83 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); 81 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
84 value &= 0xFFFFFF7F; 82 value &= 0xFFFFFF7F;
85 if (enable) 83 if (enable)
86 value |= 0x00000080; // set BLUE_FIELD_EN 84 value |= 0x00000080; // set BLUE_FIELD_EN
87 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); 85 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
88} 86}
89 87
90
91static int medusa_initialize_ntsc(struct cx25821_dev *dev) 88static int medusa_initialize_ntsc(struct cx25821_dev *dev)
92{ 89{
93 int ret_val = 0; 90 int ret_val = 0;
94 int i = 0; 91 int i = 0;
95 u32 value = 0; 92 u32 value = 0;
96 u32 tmp = 0; 93 u32 tmp = 0;
97 94
98 mutex_lock(&dev->lock); 95 mutex_lock(&dev->lock);
99 96
100 97 for (i = 0; i < MAX_DECODERS; i++) {
101 for (i=0; i < MAX_DECODERS; i++) 98 // set video format NTSC-M
102 { 99 value =
103 // set video format NTSC-M 100 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
104 value = cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL+(0x200*i), &tmp); 101 &tmp);
105 value &= 0xFFFFFFF0; 102 value &= 0xFFFFFFF0;
106 value |= 0x10001; // enable the fast locking mode bit[16] 103 value |= 0x10001; // enable the fast locking mode bit[16]
107 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL+(0x200*i), value); 104 ret_val =
108 105 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
109 // resolution NTSC 720x480 106 value);
110 value = cx25821_i2c_read(&dev->i2c_bus[0], HORIZ_TIM_CTRL+(0x200*i), &tmp); 107
111 value &= 0x00C00C00; 108 // resolution NTSC 720x480
112 value |= 0x612D0074; 109 value =
113 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HORIZ_TIM_CTRL+(0x200*i), value); 110 cx25821_i2c_read(&dev->i2c_bus[0],
114 111 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
115 value = cx25821_i2c_read(&dev->i2c_bus[0], VERT_TIM_CTRL+(0x200*i), &tmp); 112 value &= 0x00C00C00;
116 value &= 0x00C00C00; 113 value |= 0x612D0074;
117 value |= 0x1C1E001A; // vblank_cnt + 2 to get camera ID 114 ret_val =
118 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VERT_TIM_CTRL+(0x200*i), value); 115 cx25821_i2c_write(&dev->i2c_bus[0],
119 116 HORIZ_TIM_CTRL + (0x200 * i), value);
120 // chroma subcarrier step size 117
121 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], SC_STEP_SIZE+(0x200*i), 0x43E00000); 118 value =
122 119 cx25821_i2c_read(&dev->i2c_bus[0],
123 // enable VIP optional active 120 VERT_TIM_CTRL + (0x200 * i), &tmp);
124 value = cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL_NS+(0x200*i), &tmp); 121 value &= 0x00C00C00;
125 value &= 0xFFFBFFFF; 122 value |= 0x1C1E001A; // vblank_cnt + 2 to get camera ID
126 value |= 0x00040000; 123 ret_val =
127 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL_NS+(0x200*i), value); 124 cx25821_i2c_write(&dev->i2c_bus[0],
128 125 VERT_TIM_CTRL + (0x200 * i), value);
129 // enable VIP optional active (VIP_OPT_AL) for direct output. 126
130 value = cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1+(0x200*i), &tmp); 127 // chroma subcarrier step size
131 value &= 0xFFFBFFFF; 128 ret_val =
132 value |= 0x00040000; 129 cx25821_i2c_write(&dev->i2c_bus[0],
133 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1+(0x200*i), value); 130 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
134 131
135 // clear VPRES_VERT_EN bit, fixes the chroma run away problem 132 // enable VIP optional active
136 // when the input switching rate < 16 fields 133 value =
137 // 134 cx25821_i2c_read(&dev->i2c_bus[0],
138 value = cx25821_i2c_read(&dev->i2c_bus[0], MISC_TIM_CTRL+(0x200*i), &tmp); 135 OUT_CTRL_NS + (0x200 * i), &tmp);
139 value = setBitAtPos(value, 14); // disable special play detection 136 value &= 0xFFFBFFFF;
140 value = clearBitAtPos(value, 15); 137 value |= 0x00040000;
141 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MISC_TIM_CTRL+(0x200*i), value); 138 ret_val =
142 139 cx25821_i2c_write(&dev->i2c_bus[0],
143 // set vbi_gate_en to 0 140 OUT_CTRL_NS + (0x200 * i), value);
144 value = cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1+(0x200*i), &tmp); 141
145 value = clearBitAtPos(value, 29); 142 // enable VIP optional active (VIP_OPT_AL) for direct output.
146 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1+(0x200*i), value); 143 value =
147 144 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
148 // Enable the generation of blue field output if no video 145 &tmp);
149 medusa_enable_bluefield_output(dev, i, 1); 146 value &= 0xFFFBFFFF;
150 } 147 value |= 0x00040000;
151 148 ret_val =
152 149 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
153 for (i=0; i < MAX_ENCODERS; i++) 150 value);
154 { 151
155 // NTSC hclock 152 // clear VPRES_VERT_EN bit, fixes the chroma run away problem
156 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_1+(0x100*i), &tmp); 153 // when the input switching rate < 16 fields
157 value &= 0xF000FC00; 154 //
158 value |= 0x06B402D0; 155 value =
159 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_1+(0x100*i), value); 156 cx25821_i2c_read(&dev->i2c_bus[0],
160 157 MISC_TIM_CTRL + (0x200 * i), &tmp);
161 // burst begin and burst end 158 value = setBitAtPos(value, 14); // disable special play detection
162 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_2+(0x100*i), &tmp); 159 value = clearBitAtPos(value, 15);
163 value &= 0xFF000000; 160 ret_val =
164 value |= 0x007E9054; 161 cx25821_i2c_write(&dev->i2c_bus[0],
165 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_2+(0x100*i), value); 162 MISC_TIM_CTRL + (0x200 * i), value);
166 163
167 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_3+(0x100*i), &tmp); 164 // set vbi_gate_en to 0
168 value &= 0xFC00FE00; 165 value =
169 value |= 0x00EC00F0; 166 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
170 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_3+(0x100*i), value); 167 &tmp);
171 168 value = clearBitAtPos(value, 29);
172 // set NTSC vblank, no phase alternation, 7.5 IRE pedestal 169 ret_val =
173 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4+(0x100*i), &tmp); 170 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
174 value &= 0x00FCFFFF; 171 value);
175 value |= 0x13020000; 172
176 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4+(0x100*i), value); 173 // Enable the generation of blue field output if no video
177 174 medusa_enable_bluefield_output(dev, i, 1);
178 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_5+(0x100*i), &tmp); 175 }
179 value &= 0xFFFF0000; 176
180 value |= 0x0000E575; 177 for (i = 0; i < MAX_ENCODERS; i++) {
181 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_5+(0x100*i), value); 178 // NTSC hclock
182 179 value =
183 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_6+(0x100*i), 0x009A89C1); 180 cx25821_i2c_read(&dev->i2c_bus[0],
184 181 DENC_A_REG_1 + (0x100 * i), &tmp);
185 // Subcarrier Increment 182 value &= 0xF000FC00;
186 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_7+(0x100*i), 0x21F07C1F); 183 value |= 0x06B402D0;
187 } 184 ret_val =
188 185 cx25821_i2c_write(&dev->i2c_bus[0],
189 186 DENC_A_REG_1 + (0x100 * i), value);
190 //set picture resolutions 187
191 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720 188 // burst begin and burst end
192 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 480 189 value =
193 190 cx25821_i2c_read(&dev->i2c_bus[0],
194 // set Bypass input format to NTSC 525 lines 191 DENC_A_REG_2 + (0x100 * i), &tmp);
195 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 192 value &= 0xFF000000;
196 value |= 0x00080200; 193 value |= 0x007E9054;
197 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 194 ret_val =
198 195 cx25821_i2c_write(&dev->i2c_bus[0],
199 mutex_unlock(&dev->lock); 196 DENC_A_REG_2 + (0x100 * i), value);
200 197
201 return ret_val; 198 value =
202} 199 cx25821_i2c_read(&dev->i2c_bus[0],
200 DENC_A_REG_3 + (0x100 * i), &tmp);
201 value &= 0xFC00FE00;
202 value |= 0x00EC00F0;
203 ret_val =
204 cx25821_i2c_write(&dev->i2c_bus[0],
205 DENC_A_REG_3 + (0x100 * i), value);
206
207 // set NTSC vblank, no phase alternation, 7.5 IRE pedestal
208 value =
209 cx25821_i2c_read(&dev->i2c_bus[0],
210 DENC_A_REG_4 + (0x100 * i), &tmp);
211 value &= 0x00FCFFFF;
212 value |= 0x13020000;
213 ret_val =
214 cx25821_i2c_write(&dev->i2c_bus[0],
215 DENC_A_REG_4 + (0x100 * i), value);
216
217 value =
218 cx25821_i2c_read(&dev->i2c_bus[0],
219 DENC_A_REG_5 + (0x100 * i), &tmp);
220 value &= 0xFFFF0000;
221 value |= 0x0000E575;
222 ret_val =
223 cx25821_i2c_write(&dev->i2c_bus[0],
224 DENC_A_REG_5 + (0x100 * i), value);
225
226 ret_val =
227 cx25821_i2c_write(&dev->i2c_bus[0],
228 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
229
230 // Subcarrier Increment
231 ret_val =
232 cx25821_i2c_write(&dev->i2c_bus[0],
233 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
234 }
235
236 //set picture resolutions
237 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720
238 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 480
239
240 // set Bypass input format to NTSC 525 lines
241 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
242 value |= 0x00080200;
243 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
203 244
245 mutex_unlock(&dev->lock);
246
247 return ret_val;
248}
204 249
205static int medusa_PALCombInit(struct cx25821_dev *dev, int dec) 250static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
206{ 251{
207 int ret_val = -1; 252 int ret_val = -1;
208 u32 value = 0, tmp = 0; 253 u32 value = 0, tmp = 0;
209 254
210 // Setup for 2D threshold 255 // Setup for 2D threshold
211 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG+(0x200*dec), 0x20002861); 256 ret_val =
212 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG+(0x200*dec), 0x20002861); 257 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec),
213 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG+(0x200*dec), 0x200A1023); 258 0x20002861);
214 259 ret_val =
215 // Setup flat chroma and luma thresholds 260 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG + (0x200 * dec),
216 value = cx25821_i2c_read(&dev->i2c_bus[0], COMB_FLAT_THRESH_CTRL+(0x200*dec), &tmp); 261 0x20002861);
217 value &= 0x06230000; 262 ret_val =
218 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], COMB_FLAT_THRESH_CTRL+(0x200*dec), value); 263 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec),
219 264 0x200A1023);
220 // set comb 2D blend 265
221 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND+(0x200*dec), 0x210F0F0F); 266 // Setup flat chroma and luma thresholds
222 267 value =
223 // COMB MISC CONTROL 268 cx25821_i2c_read(&dev->i2c_bus[0],
224 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL+(0x200*dec), 0x41120A7F); 269 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
225 270 value &= 0x06230000;
226 return ret_val; 271 ret_val =
272 cx25821_i2c_write(&dev->i2c_bus[0],
273 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
274
275 // set comb 2D blend
276 ret_val =
277 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec),
278 0x210F0F0F);
279
280 // COMB MISC CONTROL
281 ret_val =
282 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec),
283 0x41120A7F);
284
285 return ret_val;
227} 286}
228 287
229
230static int medusa_initialize_pal(struct cx25821_dev *dev) 288static int medusa_initialize_pal(struct cx25821_dev *dev)
231{ 289{
232 int ret_val = 0; 290 int ret_val = 0;
233 int i = 0; 291 int i = 0;
234 u32 value = 0; 292 u32 value = 0;
235 u32 tmp = 0; 293 u32 tmp = 0;
236 294
237 mutex_lock(&dev->lock); 295 mutex_lock(&dev->lock);
238 296
239 for (i=0; i < MAX_DECODERS; i++) 297 for (i = 0; i < MAX_DECODERS; i++) {
240 { 298 // set video format PAL-BDGHI
241 // set video format PAL-BDGHI 299 value =
242 value = cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL+(0x200*i), &tmp); 300 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
243 value &= 0xFFFFFFF0; 301 &tmp);
244 value |= 0x10004; // enable the fast locking mode bit[16] 302 value &= 0xFFFFFFF0;
245 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL+(0x200*i), value); 303 value |= 0x10004; // enable the fast locking mode bit[16]
246 304 ret_val =
247 305 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
248 // resolution PAL 720x576 306 value);
249 value = cx25821_i2c_read(&dev->i2c_bus[0], HORIZ_TIM_CTRL+(0x200*i), &tmp); 307
250 value &= 0x00C00C00; 308 // resolution PAL 720x576
251 value |= 0x632D007D; 309 value =
252 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HORIZ_TIM_CTRL+(0x200*i), value); 310 cx25821_i2c_read(&dev->i2c_bus[0],
253 311 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
254 // vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 312 value &= 0x00C00C00;
255 value = cx25821_i2c_read(&dev->i2c_bus[0], VERT_TIM_CTRL+(0x200*i), &tmp); 313 value |= 0x632D007D;
256 value &= 0x00C00C00; 314 ret_val =
257 value |= 0x28240026; // vblank_cnt + 2 to get camera ID 315 cx25821_i2c_write(&dev->i2c_bus[0],
258 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VERT_TIM_CTRL+(0x200*i), value); 316 HORIZ_TIM_CTRL + (0x200 * i), value);
259 317
260 // chroma subcarrier step size 318 // vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24
261 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], SC_STEP_SIZE+(0x200*i), 0x5411E2D0); 319 value =
262 320 cx25821_i2c_read(&dev->i2c_bus[0],
263 // enable VIP optional active 321 VERT_TIM_CTRL + (0x200 * i), &tmp);
264 value = cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL_NS+(0x200*i), &tmp); 322 value &= 0x00C00C00;
265 value &= 0xFFFBFFFF; 323 value |= 0x28240026; // vblank_cnt + 2 to get camera ID
266 value |= 0x00040000; 324 ret_val =
267 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL_NS+(0x200*i), value); 325 cx25821_i2c_write(&dev->i2c_bus[0],
268 326 VERT_TIM_CTRL + (0x200 * i), value);
269 // enable VIP optional active (VIP_OPT_AL) for direct output. 327
270 value = cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1+(0x200*i), &tmp); 328 // chroma subcarrier step size
271 value &= 0xFFFBFFFF; 329 ret_val =
272 value |= 0x00040000; 330 cx25821_i2c_write(&dev->i2c_bus[0],
273 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1+(0x200*i), value); 331 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
274 332
275 // clear VPRES_VERT_EN bit, fixes the chroma run away problem 333 // enable VIP optional active
276 // when the input switching rate < 16 fields 334 value =
277 value = cx25821_i2c_read(&dev->i2c_bus[0], MISC_TIM_CTRL+(0x200*i), &tmp); 335 cx25821_i2c_read(&dev->i2c_bus[0],
278 value = setBitAtPos(value, 14); // disable special play detection 336 OUT_CTRL_NS + (0x200 * i), &tmp);
279 value = clearBitAtPos(value, 15); 337 value &= 0xFFFBFFFF;
280 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MISC_TIM_CTRL+(0x200*i), value); 338 value |= 0x00040000;
281 339 ret_val =
282 // set vbi_gate_en to 0 340 cx25821_i2c_write(&dev->i2c_bus[0],
283 value = cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1+(0x200*i), &tmp); 341 OUT_CTRL_NS + (0x200 * i), value);
284 value = clearBitAtPos(value, 29); 342
285 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1+(0x200*i), value); 343 // enable VIP optional active (VIP_OPT_AL) for direct output.
286 344 value =
287 medusa_PALCombInit(dev, i); 345 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
288 346 &tmp);
289 // Enable the generation of blue field output if no video 347 value &= 0xFFFBFFFF;
290 medusa_enable_bluefield_output(dev, i, 1); 348 value |= 0x00040000;
291 } 349 ret_val =
292 350 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
293 351 value);
294 for (i=0; i < MAX_ENCODERS; i++) 352
295 { 353 // clear VPRES_VERT_EN bit, fixes the chroma run away problem
296 // PAL hclock 354 // when the input switching rate < 16 fields
297 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_1+(0x100*i), &tmp); 355 value =
298 value &= 0xF000FC00; 356 cx25821_i2c_read(&dev->i2c_bus[0],
299 value |= 0x06C002D0; 357 MISC_TIM_CTRL + (0x200 * i), &tmp);
300 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_1+(0x100*i), value); 358 value = setBitAtPos(value, 14); // disable special play detection
301 359 value = clearBitAtPos(value, 15);
302 // burst begin and burst end 360 ret_val =
303 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_2+(0x100*i), &tmp); 361 cx25821_i2c_write(&dev->i2c_bus[0],
304 value &= 0xFF000000; 362 MISC_TIM_CTRL + (0x200 * i), value);
305 value |= 0x007E9754; 363
306 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_2+(0x100*i), value); 364 // set vbi_gate_en to 0
307 365 value =
308 // hblank and vactive 366 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
309 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_3+(0x100*i), &tmp); 367 &tmp);
310 value &= 0xFC00FE00; 368 value = clearBitAtPos(value, 29);
311 value |= 0x00FC0120; 369 ret_val =
312 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_3+(0x100*i), value); 370 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
313 371 value);
314 // set PAL vblank, phase alternation, 0 IRE pedestal 372
315 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4+(0x100*i), &tmp); 373 medusa_PALCombInit(dev, i);
316 value &= 0x00FCFFFF; 374
317 value |= 0x14010000; 375 // Enable the generation of blue field output if no video
318 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4+(0x100*i), value); 376 medusa_enable_bluefield_output(dev, i, 1);
319 377 }
320 378
321 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_5+(0x100*i), &tmp); 379 for (i = 0; i < MAX_ENCODERS; i++) {
322 value &= 0xFFFF0000; 380 // PAL hclock
323 value |= 0x0000F078; 381 value =
324 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_5+(0x100*i), value); 382 cx25821_i2c_read(&dev->i2c_bus[0],
325 383 DENC_A_REG_1 + (0x100 * i), &tmp);
326 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_6+(0x100*i), 0x00A493CF); 384 value &= 0xF000FC00;
327 385 value |= 0x06C002D0;
328 // Subcarrier Increment 386 ret_val =
329 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_7+(0x100*i), 0x2A098ACB); 387 cx25821_i2c_write(&dev->i2c_bus[0],
330 } 388 DENC_A_REG_1 + (0x100 * i), value);
331 389
332 390 // burst begin and burst end
333 //set picture resolutions 391 value =
334 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720 392 cx25821_i2c_read(&dev->i2c_bus[0],
335 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 576 393 DENC_A_REG_2 + (0x100 * i), &tmp);
336 394 value &= 0xFF000000;
337 // set Bypass input format to PAL 625 lines 395 value |= 0x007E9754;
338 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 396 ret_val =
339 value &= 0xFFF7FDFF; 397 cx25821_i2c_write(&dev->i2c_bus[0],
340 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 398 DENC_A_REG_2 + (0x100 * i), value);
341 399
342 mutex_unlock(&dev->lock); 400 // hblank and vactive
343 401 value =
344 return ret_val; 402 cx25821_i2c_read(&dev->i2c_bus[0],
345} 403 DENC_A_REG_3 + (0x100 * i), &tmp);
404 value &= 0xFC00FE00;
405 value |= 0x00FC0120;
406 ret_val =
407 cx25821_i2c_write(&dev->i2c_bus[0],
408 DENC_A_REG_3 + (0x100 * i), value);
409
410 // set PAL vblank, phase alternation, 0 IRE pedestal
411 value =
412 cx25821_i2c_read(&dev->i2c_bus[0],
413 DENC_A_REG_4 + (0x100 * i), &tmp);
414 value &= 0x00FCFFFF;
415 value |= 0x14010000;
416 ret_val =
417 cx25821_i2c_write(&dev->i2c_bus[0],
418 DENC_A_REG_4 + (0x100 * i), value);
419
420 value =
421 cx25821_i2c_read(&dev->i2c_bus[0],
422 DENC_A_REG_5 + (0x100 * i), &tmp);
423 value &= 0xFFFF0000;
424 value |= 0x0000F078;
425 ret_val =
426 cx25821_i2c_write(&dev->i2c_bus[0],
427 DENC_A_REG_5 + (0x100 * i), value);
428
429 ret_val =
430 cx25821_i2c_write(&dev->i2c_bus[0],
431 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
432
433 // Subcarrier Increment
434 ret_val =
435 cx25821_i2c_write(&dev->i2c_bus[0],
436 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
437 }
438
439 //set picture resolutions
440 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); //0 - 720
441 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); //0 - 576
442
443 // set Bypass input format to PAL 625 lines
444 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
445 value &= 0xFFF7FDFF;
446 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
447
448 mutex_unlock(&dev->lock);
346 449
450 return ret_val;
451}
347 452
348int medusa_set_videostandard(struct cx25821_dev *dev) 453int medusa_set_videostandard(struct cx25821_dev *dev)
349{ 454{
350 int status = STATUS_SUCCESS; 455 int status = STATUS_SUCCESS;
351 u32 value = 0, tmp = 0; 456 u32 value = 0, tmp = 0;
352 457
353 458 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) {
354 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 459 status = medusa_initialize_pal(dev);
355 { 460 } else {
356 status = medusa_initialize_pal(dev); 461 status = medusa_initialize_ntsc(dev);
357 } 462 }
358 else 463
359 { 464 // Enable DENC_A output
360 status = medusa_initialize_ntsc(dev); 465 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
361 } 466 value = setBitAtPos(value, 4);
362 467 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
363 // Enable DENC_A output 468
364 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp); 469 // Enable DENC_B output
365 value = setBitAtPos(value, 4); 470 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
366 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value); 471 value = setBitAtPos(value, 4);
367 472 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
368 // Enable DENC_B output 473
369 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp); 474 return status;
370 value = setBitAtPos(value, 4);
371 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
372
373 return status;
374} 475}
375 476
376 477void medusa_set_resolution(struct cx25821_dev *dev, int width,
377void medusa_set_resolution(struct cx25821_dev *dev, int width, int decoder_select) 478 int decoder_select)
378{ 479{
379 int decoder = 0; 480 int decoder = 0;
380 int decoder_count = 0; 481 int decoder_count = 0;
381 int ret_val = 0; 482 int ret_val = 0;
382 u32 hscale = 0x0; 483 u32 hscale = 0x0;
383 u32 vscale = 0x0; 484 u32 vscale = 0x0;
384 const int MAX_WIDTH = 720; 485 const int MAX_WIDTH = 720;
385 486
386 mutex_lock(&dev->lock); 487 mutex_lock(&dev->lock);
387 488
388 // validate the width - cannot be negative 489 // validate the width - cannot be negative
389 if (width > MAX_WIDTH) 490 if (width > MAX_WIDTH) {
390 { 491 printk
391 printk("cx25821 %s() : width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH \n", __func__, width, MAX_WIDTH); 492 ("cx25821 %s() : width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH \n",
392 width = MAX_WIDTH; 493 __func__, width, MAX_WIDTH);
393 } 494 width = MAX_WIDTH;
394 495 }
395 if( decoder_select <= 7 && decoder_select >= 0 ) 496
396 { 497 if (decoder_select <= 7 && decoder_select >= 0) {
397 decoder = decoder_select; 498 decoder = decoder_select;
398 decoder_count = decoder_select + 1; 499 decoder_count = decoder_select + 1;
399 } 500 } else {
400 else 501 decoder = 0;
401 { 502 decoder_count = _num_decoders;
402 decoder = 0; 503 }
403 decoder_count = _num_decoders; 504
404 } 505 switch (width) {
405
406
407 switch( width )
408 {
409 case 320: 506 case 320:
410 hscale = 0x13E34B; 507 hscale = 0x13E34B;
411 vscale = 0x0; 508 vscale = 0x0;
412 break; 509 break;
413 510
414 case 352: 511 case 352:
415 hscale = 0x10A273; 512 hscale = 0x10A273;
416 vscale = 0x0; 513 vscale = 0x0;
417 break; 514 break;
418 515
419 case 176: 516 case 176:
420 hscale = 0x3115B2; 517 hscale = 0x3115B2;
421 vscale = 0x1E00; 518 vscale = 0x1E00;
422 break; 519 break;
423 520
424 case 160: 521 case 160:
425 hscale = 0x378D84; 522 hscale = 0x378D84;
426 vscale = 0x1E00; 523 vscale = 0x1E00;
427 break; 524 break;
428 525
429 default: //720 526 default: //720
430 hscale = 0x0; 527 hscale = 0x0;
431 vscale = 0x0; 528 vscale = 0x0;
432 break; 529 break;
433 } 530 }
434 531
435 for( ; decoder < decoder_count; decoder++) 532 for (; decoder < decoder_count; decoder++) {
436 { 533 // write scaling values for each decoder
437 // write scaling values for each decoder 534 ret_val =
438 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL+(0x200*decoder), hscale); 535 cx25821_i2c_write(&dev->i2c_bus[0],
439 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL+(0x200*decoder), vscale); 536 HSCALE_CTRL + (0x200 * decoder), hscale);
440 } 537 ret_val =
441 538 cx25821_i2c_write(&dev->i2c_bus[0],
442 mutex_unlock(&dev->lock); 539 VSCALE_CTRL + (0x200 * decoder), vscale);
540 }
541
542 mutex_unlock(&dev->lock);
443} 543}
444 544
445static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder, int duration) 545static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
546 int duration)
446{ 547{
447 int ret_val = 0; 548 int ret_val = 0;
448 u32 fld_cnt = 0; 549 u32 fld_cnt = 0;
449 u32 tmp = 0; 550 u32 tmp = 0;
450 u32 disp_cnt_reg = DISP_AB_CNT; 551 u32 disp_cnt_reg = DISP_AB_CNT;
451 552
452 mutex_lock(&dev->lock); 553 mutex_lock(&dev->lock);
453 554
454 // no support 555 // no support
455 if (decoder < VDEC_A && decoder > VDEC_H) 556 if (decoder < VDEC_A && decoder > VDEC_H) {
456 { 557 mutex_unlock(&dev->lock);
457 mutex_unlock(&dev->lock); 558 return;
458 return; 559 }
459 }
460 560
461 switch (decoder) 561 switch (decoder) {
462 {
463 default: 562 default:
464 break; 563 break;
465 case VDEC_C: 564 case VDEC_C:
466 case VDEC_D: 565 case VDEC_D:
467 disp_cnt_reg = DISP_CD_CNT; 566 disp_cnt_reg = DISP_CD_CNT;
468 break; 567 break;
469 case VDEC_E: 568 case VDEC_E:
470 case VDEC_F: 569 case VDEC_F:
471 disp_cnt_reg = DISP_EF_CNT; 570 disp_cnt_reg = DISP_EF_CNT;
472 break; 571 break;
473 case VDEC_G: 572 case VDEC_G:
474 case VDEC_H: 573 case VDEC_H:
475 disp_cnt_reg = DISP_GH_CNT; 574 disp_cnt_reg = DISP_GH_CNT;
476 break; 575 break;
477 } 576 }
478 577
479 _display_field_cnt[decoder] = duration; 578 _display_field_cnt[decoder] = duration;
480 579
481 // update hardware 580 // update hardware
482 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp); 581 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
483 582
484 if (!(decoder % 2)) // EVEN decoder 583 if (!(decoder % 2)) // EVEN decoder
485 { 584 {
486 fld_cnt &= 0xFFFF0000; 585 fld_cnt &= 0xFFFF0000;
487 fld_cnt |= duration; 586 fld_cnt |= duration;
488 } 587 } else {
489 else 588 fld_cnt &= 0x0000FFFF;
490 { 589 fld_cnt |= ((u32) duration) << 16;
491 fld_cnt &= 0x0000FFFF; 590 }
492 fld_cnt |= ((u32)duration) << 16;
493 }
494 591
495 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt); 592 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
496 593
497 mutex_unlock(&dev->lock); 594 mutex_unlock(&dev->lock);
498} 595}
499 596
500///////////////////////////////////////////////////////////////////////////////////////// 597/////////////////////////////////////////////////////////////////////////////////////////
501// Map to Medusa register setting 598// Map to Medusa register setting
502static int mapM( 599static int mapM(int srcMin,
503 int srcMin, 600 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal)
504 int srcMax,
505 int srcVal,
506 int dstMin,
507 int dstMax,
508 int* dstVal
509)
510{ 601{
511 int numerator; 602 int numerator;
512 int denominator; 603 int denominator;
513 int quotient; 604 int quotient;
514 605
515 if((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax)) 606 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax)) {
516 { 607 return -1;
517 return -1; 608 }
518 } 609 // This is the overall expression used:
519 610 // *dstVal = (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
520 // This is the overall expression used: 611 // but we need to account for rounding so below we use the modulus
521 // *dstVal = (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin; 612 // operator to find the remainder and increment if necessary.
522 // but we need to account for rounding so below we use the modulus 613 numerator = (srcVal - srcMin) * (dstMax - dstMin);
523 // operator to find the remainder and increment if necessary. 614 denominator = srcMax - srcMin;
524 numerator = (srcVal - srcMin)*(dstMax - dstMin); 615 quotient = numerator / denominator;
525 denominator = srcMax - srcMin; 616
526 quotient = numerator/denominator; 617 if (2 * (numerator % denominator) >= denominator) {
527 618 quotient++;
528 if(2 * ( numerator % denominator ) >= denominator) 619 }
529 { 620
530 quotient++; 621 *dstVal = quotient + dstMin;
531 } 622
532 623 return 0;
533 *dstVal = quotient + dstMin;
534
535 return 0;
536} 624}
537 625
538static unsigned long convert_to_twos(long numeric, unsigned long bits_len) 626static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
539{ 627{
540 unsigned char temp; 628 unsigned char temp;
541 629
542 if (numeric >= 0) 630 if (numeric >= 0)
543 return numeric; 631 return numeric;
544 else 632 else {
545 { 633 temp = ~(abs(numeric) & 0xFF);
546 temp = ~(abs(numeric) & 0xFF); 634 temp += 1;
547 temp += 1; 635 return temp;
548 return temp; 636 }
549 }
550} 637}
638
551///////////////////////////////////////////////////////////////////////////////////////// 639/////////////////////////////////////////////////////////////////////////////////////////
552int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder) 640int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
553{ 641{
554 int ret_val = 0; 642 int ret_val = 0;
555 int value = 0; 643 int value = 0;
556 u32 val = 0, tmp = 0; 644 u32 val = 0, tmp = 0;
557 645
558 mutex_lock(&dev->lock); 646 mutex_lock(&dev->lock);
559 if((brightness > VIDEO_PROCAMP_MAX) || (brightness < VIDEO_PROCAMP_MIN)) 647 if ((brightness > VIDEO_PROCAMP_MAX)
560 { 648 || (brightness < VIDEO_PROCAMP_MIN)) {
649 mutex_unlock(&dev->lock);
650 return -1;
651 }
652 ret_val =
653 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
654 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
655 value = convert_to_twos(value, 8);
656 val =
657 cx25821_i2c_read(&dev->i2c_bus[0],
658 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
659 val &= 0xFFFFFF00;
660 ret_val |=
661 cx25821_i2c_write(&dev->i2c_bus[0],
662 VDEC_A_BRITE_CTRL + (0x200 * decoder),
663 val | value);
561 mutex_unlock(&dev->lock); 664 mutex_unlock(&dev->lock);
562 return -1; 665 return ret_val;
563 }
564 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness, SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
565 value = convert_to_twos(value, 8);
566 val = cx25821_i2c_read(&dev->i2c_bus[0], VDEC_A_BRITE_CTRL+(0x200*decoder), &tmp);
567 val &= 0xFFFFFF00;
568 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], VDEC_A_BRITE_CTRL+(0x200*decoder), val | value);
569 mutex_unlock(&dev->lock);
570 return ret_val;
571} 666}
572 667
573///////////////////////////////////////////////////////////////////////////////////////// 668/////////////////////////////////////////////////////////////////////////////////////////
574int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder) 669int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
575{ 670{
576 int ret_val = 0; 671 int ret_val = 0;
577 int value = 0; 672 int value = 0;
578 u32 val = 0, tmp = 0; 673 u32 val = 0, tmp = 0;
579 674
580 mutex_lock(&dev->lock); 675 mutex_lock(&dev->lock);
676
677 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
678 mutex_unlock(&dev->lock);
679 return -1;
680 }
681
682 ret_val =
683 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
684 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
685 val =
686 cx25821_i2c_read(&dev->i2c_bus[0],
687 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
688 val &= 0xFFFFFF00;
689 ret_val |=
690 cx25821_i2c_write(&dev->i2c_bus[0],
691 VDEC_A_CNTRST_CTRL + (0x200 * decoder),
692 val | value);
581 693
582 if((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN))
583 {
584 mutex_unlock(&dev->lock); 694 mutex_unlock(&dev->lock);
585 return -1; 695 return ret_val;
586 }
587
588 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast, UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
589 val = cx25821_i2c_read(&dev->i2c_bus[0], VDEC_A_CNTRST_CTRL+(0x200*decoder), &tmp);
590 val &= 0xFFFFFF00;
591 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], VDEC_A_CNTRST_CTRL+(0x200*decoder), val | value);
592
593 mutex_unlock(&dev->lock);
594 return ret_val;
595} 696}
596 697
597///////////////////////////////////////////////////////////////////////////////////////// 698/////////////////////////////////////////////////////////////////////////////////////////
598int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder) 699int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
599{ 700{
600 int ret_val = 0; 701 int ret_val = 0;
601 int value = 0; 702 int value = 0;
602 u32 val = 0, tmp = 0; 703 u32 val = 0, tmp = 0;
603 704
604 mutex_lock(&dev->lock); 705 mutex_lock(&dev->lock);
605 706
606 if((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) 707 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
607 { 708 mutex_unlock(&dev->lock);
608 mutex_unlock(&dev->lock); 709 return -1;
609 return -1; 710 }
610 }
611 711
612 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value); 712 ret_val =
713 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN,
714 SIGNED_BYTE_MAX, &value);
613 715
614 value = convert_to_twos(value, 8); 716 value = convert_to_twos(value, 8);
615 val = cx25821_i2c_read(&dev->i2c_bus[0], VDEC_A_HUE_CTRL+(0x200*decoder), &tmp); 717 val =
616 val &= 0xFFFFFF00; 718 cx25821_i2c_read(&dev->i2c_bus[0],
719 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
720 val &= 0xFFFFFF00;
617 721
618 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], VDEC_A_HUE_CTRL+(0x200*decoder), val | value); 722 ret_val |=
723 cx25821_i2c_write(&dev->i2c_bus[0],
724 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
619 725
620 mutex_unlock(&dev->lock); 726 mutex_unlock(&dev->lock);
621 return ret_val; 727 return ret_val;
622} 728}
623 729
624
625///////////////////////////////////////////////////////////////////////////////////////// 730/////////////////////////////////////////////////////////////////////////////////////////
626int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder) 731int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
627{ 732{
628 int ret_val = 0; 733 int ret_val = 0;
629 int value = 0; 734 int value = 0;
630 u32 val = 0, tmp = 0; 735 u32 val = 0, tmp = 0;
736
737 mutex_lock(&dev->lock);
738
739 if ((saturation > VIDEO_PROCAMP_MAX)
740 || (saturation < VIDEO_PROCAMP_MIN)) {
741 mutex_unlock(&dev->lock);
742 return -1;
743 }
744
745 ret_val =
746 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
747 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
748
749 val =
750 cx25821_i2c_read(&dev->i2c_bus[0],
751 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
752 val &= 0xFFFFFF00;
753 ret_val |=
754 cx25821_i2c_write(&dev->i2c_bus[0],
755 VDEC_A_USAT_CTRL + (0x200 * decoder),
756 val | value);
757
758 val =
759 cx25821_i2c_read(&dev->i2c_bus[0],
760 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
761 val &= 0xFFFFFF00;
762 ret_val |=
763 cx25821_i2c_write(&dev->i2c_bus[0],
764 VDEC_A_VSAT_CTRL + (0x200 * decoder),
765 val | value);
631 766
632 mutex_lock(&dev->lock);
633
634 if((saturation > VIDEO_PROCAMP_MAX) || (saturation < VIDEO_PROCAMP_MIN))
635 {
636 mutex_unlock(&dev->lock); 767 mutex_unlock(&dev->lock);
637 return -1; 768 return ret_val;
638 }
639
640 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation, UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
641
642 val = cx25821_i2c_read(&dev->i2c_bus[0], VDEC_A_USAT_CTRL+(0x200*decoder), &tmp);
643 val &= 0xFFFFFF00;
644 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], VDEC_A_USAT_CTRL+(0x200*decoder), val | value);
645
646 val = cx25821_i2c_read(&dev->i2c_bus[0], VDEC_A_VSAT_CTRL+(0x200*decoder), &tmp);
647 val &= 0xFFFFFF00;
648 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], VDEC_A_VSAT_CTRL+(0x200*decoder), val | value);
649
650 mutex_unlock(&dev->lock);
651 return ret_val;
652} 769}
653 770
654
655///////////////////////////////////////////////////////////////////////////////////////// 771/////////////////////////////////////////////////////////////////////////////////////////
656// Program the display sequence and monitor output. 772// Program the display sequence and monitor output.
657// 773//
658int medusa_video_init(struct cx25821_dev *dev) 774int medusa_video_init(struct cx25821_dev *dev)
659{ 775{
660 u32 value = 0, tmp = 0; 776 u32 value = 0, tmp = 0;
661 int ret_val = 0; 777 int ret_val = 0;
662 int i=0; 778 int i = 0;
663
664 mutex_lock(&dev->lock);
665
666 _num_decoders = dev->_max_num_decoders;
667
668 779
669 // disable Auto source selection on all video decoders 780 mutex_lock(&dev->lock);
670 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
671 value &= 0xFFFFF0FF;
672 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
673 781
674 if (ret_val < 0) 782 _num_decoders = dev->_max_num_decoders;
675 {
676 mutex_unlock(&dev->lock);
677 return -EINVAL;
678 }
679
680 // Turn off Master source switch enable
681 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
682 value &= 0xFFFFFFDF;
683 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
684
685 if (ret_val < 0)
686 {
687 mutex_unlock(&dev->lock);
688 return -EINVAL;
689 }
690 783
691 mutex_unlock(&dev->lock); 784 // disable Auto source selection on all video decoders
785 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
786 value &= 0xFFFFF0FF;
787 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
692 788
693 for (i=0; i < _num_decoders; i++) 789 if (ret_val < 0) {
694 { 790 mutex_unlock(&dev->lock);
695 medusa_set_decoderduration(dev, i, _display_field_cnt[i]); 791 return -EINVAL;
696 } 792 }
793 // Turn off Master source switch enable
794 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
795 value &= 0xFFFFFFDF;
796 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
697 797
698 mutex_lock(&dev->lock); 798 if (ret_val < 0) {
799 mutex_unlock(&dev->lock);
800 return -EINVAL;
801 }
699 802
700 // Select monitor as DENC A input, power up the DAC
701 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
702 value &= 0xFF70FF70;
703 value |= 0x00090008; // set en_active
704 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
705
706 if (ret_val < 0)
707 {
708 mutex_unlock(&dev->lock); 803 mutex_unlock(&dev->lock);
709 return -EINVAL;
710 }
711 804
712 // enable input is VIP/656 805 for (i = 0; i < _num_decoders; i++) {
713 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 806 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
714 value |= 0x00040100; // enable VIP 807 }
715 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 808
809 mutex_lock(&dev->lock);
810
811 // Select monitor as DENC A input, power up the DAC
812 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
813 value &= 0xFF70FF70;
814 value |= 0x00090008; // set en_active
815 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
816
817 if (ret_val < 0) {
818 mutex_unlock(&dev->lock);
819 return -EINVAL;
820 }
821 // enable input is VIP/656
822 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
823 value |= 0x00040100; // enable VIP
824 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
825
826 if (ret_val < 0) {
827 mutex_unlock(&dev->lock);
828 return -EINVAL;
829 }
830 // select AFE clock to output mode
831 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
832 value &= 0x83FFFFFF;
833 ret_val =
834 cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
835 value | 0x10000000);
836
837 if (ret_val < 0) {
838 mutex_unlock(&dev->lock);
839 return -EINVAL;
840 }
841 // Turn on all of the data out and control output pins.
842 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
843 value &= 0xFEF0FE00;
844 if (_num_decoders == MAX_DECODERS) {
845 // Note: The octal board does not support control pins(bit16-19).
846 // These bits are ignored in the octal board.
847 value |= 0x010001F8; // disable VDEC A-C port, default to Mobilygen Interface
848 } else {
849 value |= 0x010F0108; // disable VDEC A-C port, default to Mobilygen Interface
850 }
851
852 value |= 7;
853 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
854 if (ret_val < 0) {
855 mutex_unlock(&dev->lock);
856 return -EINVAL;
857 }
716 858
717 if (ret_val < 0)
718 {
719 mutex_unlock(&dev->lock); 859 mutex_unlock(&dev->lock);
720 return -EINVAL;
721 }
722 860
723 // select AFE clock to output mode 861 ret_val = medusa_set_videostandard(dev);
724 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
725 value &= 0x83FFFFFF;
726 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, value | 0x10000000);
727 862
728 if (ret_val < 0) 863 if (ret_val < 0) {
729 { 864 mutex_unlock(&dev->lock);
730 mutex_unlock(&dev->lock); 865 return -EINVAL;
731 return -EINVAL; 866 }
732 }
733
734 // Turn on all of the data out and control output pins.
735 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
736 value &= 0xFEF0FE00;
737 if (_num_decoders == MAX_DECODERS)
738 {
739 // Note: The octal board does not support control pins(bit16-19).
740 // These bits are ignored in the octal board.
741 value |= 0x010001F8; // disable VDEC A-C port, default to Mobilygen Interface
742 }
743 else
744 {
745 value |= 0x010F0108; // disable VDEC A-C port, default to Mobilygen Interface
746 }
747
748 value |= 7;
749 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
750 if (ret_val < 0)
751 {
752 mutex_unlock(&dev->lock);
753 return -EINVAL;
754 }
755
756 mutex_unlock(&dev->lock);
757
758
759 ret_val = medusa_set_videostandard(dev);
760
761
762 if (ret_val < 0)
763 {
764 mutex_unlock(&dev->lock);
765 return -EINVAL;
766 }
767 867
768 return 1; 868 return 1;
769} 869}
diff --git a/drivers/staging/cx25821/cx25821-medusa-video.h b/drivers/staging/cx25821/cx25821-medusa-video.h
index f7cb16a70895..2fab4b2f251c 100644
--- a/drivers/staging/cx25821/cx25821-medusa-video.h
+++ b/drivers/staging/cx25821/cx25821-medusa-video.h
@@ -1,30 +1,29 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef _MEDUSA_VIDEO_H 23#ifndef _MEDUSA_VIDEO_H
24#define _MEDUSA_VIDEO_H 24#define _MEDUSA_VIDEO_H
25
26#include "cx25821-medusa-defines.h"
27 25
26#include "cx25821-medusa-defines.h"
28 27
29// Color control constants 28// Color control constants
30#define VIDEO_PROCAMP_MIN 0 29#define VIDEO_PROCAMP_MIN 0
@@ -41,11 +40,10 @@
41#define CONTRAST_DEFAULT 5000 40#define CONTRAST_DEFAULT 5000
42#define HUE_DEFAULT 5000 41#define HUE_DEFAULT 5000
43 42
43unsigned short _num_decoders;
44unsigned short _num_cameras;
44 45
45unsigned short _num_decoders; 46unsigned int _video_standard;
46unsigned short _num_cameras; 47int _display_field_cnt[MAX_DECODERS];
47 48
48unsigned int _video_standard;
49int _display_field_cnt[MAX_DECODERS];
50
51#endif 49#endif
diff --git a/drivers/staging/cx25821/cx25821-reg.h b/drivers/staging/cx25821/cx25821-reg.h
index 3d98124650c5..7241e7ee3fd3 100644
--- a/drivers/staging/cx25821/cx25821-reg.h
+++ b/drivers/staging/cx25821/cx25821-reg.h
@@ -1,24 +1,24 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef __CX25821_REGISTERS__ 23#ifndef __CX25821_REGISTERS__
24#define __CX25821_REGISTERS__ 24#define __CX25821_REGISTERS__
@@ -47,25 +47,25 @@
47#define RISC_SYNC_ODD_VBI 0x00000006 47#define RISC_SYNC_ODD_VBI 0x00000006
48#define RISC_SYNC_EVEN_VBI 0x00000207 48#define RISC_SYNC_EVEN_VBI 0x00000207
49#define RISC_NOOP 0xF0000000 49#define RISC_NOOP 0xF0000000
50 50
51//***************************************************************************** 51//*****************************************************************************
52// ASB SRAM 52// ASB SRAM
53//***************************************************************************** 53//*****************************************************************************
54#define TX_SRAM 0x000000 // Transmit SRAM 54#define TX_SRAM 0x000000 // Transmit SRAM
55 55
56//***************************************************************************** 56//*****************************************************************************
57#define RX_RAM 0x010000 // Receive SRAM 57#define RX_RAM 0x010000 // Receive SRAM
58 58
59//***************************************************************************** 59//*****************************************************************************
60// Application Layer (AL) 60// Application Layer (AL)
61//***************************************************************************** 61//*****************************************************************************
62#define DEV_CNTRL2 0x040000 // Device control 62#define DEV_CNTRL2 0x040000 // Device control
63#define FLD_RUN_RISC 0x00000020 63#define FLD_RUN_RISC 0x00000020
64 64
65//***************************************************************************** 65//*****************************************************************************
66#define PCI_INT_MSK 0x040010 // PCI interrupt mask 66#define PCI_INT_MSK 0x040010 // PCI interrupt mask
67#define PCI_INT_STAT 0x040014 // PCI interrupt status 67#define PCI_INT_STAT 0x040014 // PCI interrupt status
68#define PCI_INT_MSTAT 0x040018 // PCI interrupt masked status 68#define PCI_INT_MSTAT 0x040018 // PCI interrupt masked status
69#define FLD_HAMMERHEAD_INT (1 << 27) 69#define FLD_HAMMERHEAD_INT (1 << 27)
70#define FLD_UART_INT (1 << 26) 70#define FLD_UART_INT (1 << 26)
71#define FLD_IRQN_INT (1 << 25) 71#define FLD_IRQN_INT (1 << 25)
@@ -94,1499 +94,1484 @@
94#define FLD_VID_A_INT (1 << 0) 94#define FLD_VID_A_INT (1 << 0)
95 95
96//***************************************************************************** 96//*****************************************************************************
97#define VID_A_INT_MSK 0x040020 // Video A interrupt mask 97#define VID_A_INT_MSK 0x040020 // Video A interrupt mask
98#define VID_A_INT_STAT 0x040024 // Video A interrupt status 98#define VID_A_INT_STAT 0x040024 // Video A interrupt status
99#define VID_A_INT_MSTAT 0x040028 // Video A interrupt masked status 99#define VID_A_INT_MSTAT 0x040028 // Video A interrupt masked status
100#define VID_A_INT_SSTAT 0x04002C // Video A interrupt set status 100#define VID_A_INT_SSTAT 0x04002C // Video A interrupt set status
101 101
102//***************************************************************************** 102//*****************************************************************************
103#define VID_B_INT_MSK 0x040030 // Video B interrupt mask 103#define VID_B_INT_MSK 0x040030 // Video B interrupt mask
104#define VID_B_INT_STAT 0x040034 // Video B interrupt status 104#define VID_B_INT_STAT 0x040034 // Video B interrupt status
105#define VID_B_INT_MSTAT 0x040038 // Video B interrupt masked status 105#define VID_B_INT_MSTAT 0x040038 // Video B interrupt masked status
106#define VID_B_INT_SSTAT 0x04003C // Video B interrupt set status 106#define VID_B_INT_SSTAT 0x04003C // Video B interrupt set status
107 107
108//***************************************************************************** 108//*****************************************************************************
109#define VID_C_INT_MSK 0x040040 // Video C interrupt mask 109#define VID_C_INT_MSK 0x040040 // Video C interrupt mask
110#define VID_C_INT_STAT 0x040044 // Video C interrupt status 110#define VID_C_INT_STAT 0x040044 // Video C interrupt status
111#define VID_C_INT_MSTAT 0x040048 // Video C interrupt masked status 111#define VID_C_INT_MSTAT 0x040048 // Video C interrupt masked status
112#define VID_C_INT_SSTAT 0x04004C // Video C interrupt set status 112#define VID_C_INT_SSTAT 0x04004C // Video C interrupt set status
113 113
114//***************************************************************************** 114//*****************************************************************************
115#define VID_D_INT_MSK 0x040050 // Video D interrupt mask 115#define VID_D_INT_MSK 0x040050 // Video D interrupt mask
116#define VID_D_INT_STAT 0x040054 // Video D interrupt status 116#define VID_D_INT_STAT 0x040054 // Video D interrupt status
117#define VID_D_INT_MSTAT 0x040058 // Video D interrupt masked status 117#define VID_D_INT_MSTAT 0x040058 // Video D interrupt masked status
118#define VID_D_INT_SSTAT 0x04005C // Video D interrupt set status 118#define VID_D_INT_SSTAT 0x04005C // Video D interrupt set status
119 119
120//***************************************************************************** 120//*****************************************************************************
121#define VID_E_INT_MSK 0x040060 // Video E interrupt mask 121#define VID_E_INT_MSK 0x040060 // Video E interrupt mask
122#define VID_E_INT_STAT 0x040064 // Video E interrupt status 122#define VID_E_INT_STAT 0x040064 // Video E interrupt status
123#define VID_E_INT_MSTAT 0x040068 // Video E interrupt masked status 123#define VID_E_INT_MSTAT 0x040068 // Video E interrupt masked status
124#define VID_E_INT_SSTAT 0x04006C // Video E interrupt set status 124#define VID_E_INT_SSTAT 0x04006C // Video E interrupt set status
125 125
126//***************************************************************************** 126//*****************************************************************************
127#define VID_F_INT_MSK 0x040070 // Video F interrupt mask 127#define VID_F_INT_MSK 0x040070 // Video F interrupt mask
128#define VID_F_INT_STAT 0x040074 // Video F interrupt status 128#define VID_F_INT_STAT 0x040074 // Video F interrupt status
129#define VID_F_INT_MSTAT 0x040078 // Video F interrupt masked status 129#define VID_F_INT_MSTAT 0x040078 // Video F interrupt masked status
130#define VID_F_INT_SSTAT 0x04007C // Video F interrupt set status 130#define VID_F_INT_SSTAT 0x04007C // Video F interrupt set status
131 131
132//***************************************************************************** 132//*****************************************************************************
133#define VID_G_INT_MSK 0x040080 // Video G interrupt mask 133#define VID_G_INT_MSK 0x040080 // Video G interrupt mask
134#define VID_G_INT_STAT 0x040084 // Video G interrupt status 134#define VID_G_INT_STAT 0x040084 // Video G interrupt status
135#define VID_G_INT_MSTAT 0x040088 // Video G interrupt masked status 135#define VID_G_INT_MSTAT 0x040088 // Video G interrupt masked status
136#define VID_G_INT_SSTAT 0x04008C // Video G interrupt set status 136#define VID_G_INT_SSTAT 0x04008C // Video G interrupt set status
137 137
138//***************************************************************************** 138//*****************************************************************************
139#define VID_H_INT_MSK 0x040090 // Video H interrupt mask 139#define VID_H_INT_MSK 0x040090 // Video H interrupt mask
140#define VID_H_INT_STAT 0x040094 // Video H interrupt status 140#define VID_H_INT_STAT 0x040094 // Video H interrupt status
141#define VID_H_INT_MSTAT 0x040098 // Video H interrupt masked status 141#define VID_H_INT_MSTAT 0x040098 // Video H interrupt masked status
142#define VID_H_INT_SSTAT 0x04009C // Video H interrupt set status 142#define VID_H_INT_SSTAT 0x04009C // Video H interrupt set status
143 143
144//***************************************************************************** 144//*****************************************************************************
145#define VID_I_INT_MSK 0x0400A0 // Video I interrupt mask 145#define VID_I_INT_MSK 0x0400A0 // Video I interrupt mask
146#define VID_I_INT_STAT 0x0400A4 // Video I interrupt status 146#define VID_I_INT_STAT 0x0400A4 // Video I interrupt status
147#define VID_I_INT_MSTAT 0x0400A8 // Video I interrupt masked status 147#define VID_I_INT_MSTAT 0x0400A8 // Video I interrupt masked status
148#define VID_I_INT_SSTAT 0x0400AC // Video I interrupt set status 148#define VID_I_INT_SSTAT 0x0400AC // Video I interrupt set status
149 149
150//***************************************************************************** 150//*****************************************************************************
151#define VID_J_INT_MSK 0x0400B0 // Video J interrupt mask 151#define VID_J_INT_MSK 0x0400B0 // Video J interrupt mask
152#define VID_J_INT_STAT 0x0400B4 // Video J interrupt status 152#define VID_J_INT_STAT 0x0400B4 // Video J interrupt status
153#define VID_J_INT_MSTAT 0x0400B8 // Video J interrupt masked status 153#define VID_J_INT_MSTAT 0x0400B8 // Video J interrupt masked status
154#define VID_J_INT_SSTAT 0x0400BC // Video J interrupt set status 154#define VID_J_INT_SSTAT 0x0400BC // Video J interrupt set status
155 155
156#define FLD_VID_SRC_OPC_ERR 0x00020000 156#define FLD_VID_SRC_OPC_ERR 0x00020000
157#define FLD_VID_DST_OPC_ERR 0x00010000 157#define FLD_VID_DST_OPC_ERR 0x00010000
158#define FLD_VID_SRC_SYNC 0x00002000 158#define FLD_VID_SRC_SYNC 0x00002000
159#define FLD_VID_DST_SYNC 0x00001000 159#define FLD_VID_DST_SYNC 0x00001000
160#define FLD_VID_SRC_UF 0x00000200 160#define FLD_VID_SRC_UF 0x00000200
161#define FLD_VID_DST_OF 0x00000100 161#define FLD_VID_DST_OF 0x00000100
162#define FLD_VID_SRC_RISC2 0x00000020 162#define FLD_VID_SRC_RISC2 0x00000020
163#define FLD_VID_DST_RISC2 0x00000010 163#define FLD_VID_DST_RISC2 0x00000010
164#define FLD_VID_SRC_RISC1 0x00000002 164#define FLD_VID_SRC_RISC1 0x00000002
165#define FLD_VID_DST_RISC1 0x00000001 165#define FLD_VID_DST_RISC1 0x00000001
166#define FLD_VID_SRC_ERRORS FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF 166#define FLD_VID_SRC_ERRORS FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF
167#define FLD_VID_DST_ERRORS FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF 167#define FLD_VID_DST_ERRORS FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF
168 168
169 169//*****************************************************************************
170//***************************************************************************** 170#define AUD_A_INT_MSK 0x0400C0 // Audio Int interrupt mask
171#define AUD_A_INT_MSK 0x0400C0 // Audio Int interrupt mask 171#define AUD_A_INT_STAT 0x0400C4 // Audio Int interrupt status
172#define AUD_A_INT_STAT 0x0400C4 // Audio Int interrupt status 172#define AUD_A_INT_MSTAT 0x0400C8 // Audio Int interrupt masked status
173#define AUD_A_INT_MSTAT 0x0400C8 // Audio Int interrupt masked status 173#define AUD_A_INT_SSTAT 0x0400CC // Audio Int interrupt set status
174#define AUD_A_INT_SSTAT 0x0400CC // Audio Int interrupt set status 174
175 175//*****************************************************************************
176//***************************************************************************** 176#define AUD_B_INT_MSK 0x0400D0 // Audio Int interrupt mask
177#define AUD_B_INT_MSK 0x0400D0 // Audio Int interrupt mask 177#define AUD_B_INT_STAT 0x0400D4 // Audio Int interrupt status
178#define AUD_B_INT_STAT 0x0400D4 // Audio Int interrupt status 178#define AUD_B_INT_MSTAT 0x0400D8 // Audio Int interrupt masked status
179#define AUD_B_INT_MSTAT 0x0400D8 // Audio Int interrupt masked status 179#define AUD_B_INT_SSTAT 0x0400DC // Audio Int interrupt set status
180#define AUD_B_INT_SSTAT 0x0400DC // Audio Int interrupt set status 180
181 181//*****************************************************************************
182//***************************************************************************** 182#define AUD_C_INT_MSK 0x0400E0 // Audio Int interrupt mask
183#define AUD_C_INT_MSK 0x0400E0 // Audio Int interrupt mask 183#define AUD_C_INT_STAT 0x0400E4 // Audio Int interrupt status
184#define AUD_C_INT_STAT 0x0400E4 // Audio Int interrupt status 184#define AUD_C_INT_MSTAT 0x0400E8 // Audio Int interrupt masked status
185#define AUD_C_INT_MSTAT 0x0400E8 // Audio Int interrupt masked status 185#define AUD_C_INT_SSTAT 0x0400EC // Audio Int interrupt set status
186#define AUD_C_INT_SSTAT 0x0400EC // Audio Int interrupt set status 186
187 187//*****************************************************************************
188//***************************************************************************** 188#define AUD_D_INT_MSK 0x0400F0 // Audio Int interrupt mask
189#define AUD_D_INT_MSK 0x0400F0 // Audio Int interrupt mask 189#define AUD_D_INT_STAT 0x0400F4 // Audio Int interrupt status
190#define AUD_D_INT_STAT 0x0400F4 // Audio Int interrupt status 190#define AUD_D_INT_MSTAT 0x0400F8 // Audio Int interrupt masked status
191#define AUD_D_INT_MSTAT 0x0400F8 // Audio Int interrupt masked status 191#define AUD_D_INT_SSTAT 0x0400FC // Audio Int interrupt set status
192#define AUD_D_INT_SSTAT 0x0400FC // Audio Int interrupt set status 192
193 193//*****************************************************************************
194//***************************************************************************** 194#define AUD_E_INT_MSK 0x040100 // Audio Int interrupt mask
195#define AUD_E_INT_MSK 0x040100 // Audio Int interrupt mask 195#define AUD_E_INT_STAT 0x040104 // Audio Int interrupt status
196#define AUD_E_INT_STAT 0x040104 // Audio Int interrupt status 196#define AUD_E_INT_MSTAT 0x040108 // Audio Int interrupt masked status
197#define AUD_E_INT_MSTAT 0x040108 // Audio Int interrupt masked status 197#define AUD_E_INT_SSTAT 0x04010C // Audio Int interrupt set status
198#define AUD_E_INT_SSTAT 0x04010C // Audio Int interrupt set status 198
199 199#define FLD_AUD_SRC_OPC_ERR 0x00020000
200#define FLD_AUD_SRC_OPC_ERR 0x00020000 200#define FLD_AUD_DST_OPC_ERR 0x00010000
201#define FLD_AUD_DST_OPC_ERR 0x00010000 201#define FLD_AUD_SRC_SYNC 0x00002000
202#define FLD_AUD_SRC_SYNC 0x00002000 202#define FLD_AUD_DST_SYNC 0x00001000
203#define FLD_AUD_DST_SYNC 0x00001000 203#define FLD_AUD_SRC_OF 0x00000200
204#define FLD_AUD_SRC_OF 0x00000200 204#define FLD_AUD_DST_OF 0x00000100
205#define FLD_AUD_DST_OF 0x00000100 205#define FLD_AUD_SRC_RISCI2 0x00000020
206#define FLD_AUD_SRC_RISCI2 0x00000020 206#define FLD_AUD_DST_RISCI2 0x00000010
207#define FLD_AUD_DST_RISCI2 0x00000010 207#define FLD_AUD_SRC_RISCI1 0x00000002
208#define FLD_AUD_SRC_RISCI1 0x00000002 208#define FLD_AUD_DST_RISCI1 0x00000001
209#define FLD_AUD_DST_RISCI1 0x00000001 209
210 210//*****************************************************************************
211//***************************************************************************** 211#define MBIF_A_INT_MSK 0x040110 // MBIF Int interrupt mask
212#define MBIF_A_INT_MSK 0x040110 // MBIF Int interrupt mask 212#define MBIF_A_INT_STAT 0x040114 // MBIF Int interrupt status
213#define MBIF_A_INT_STAT 0x040114 // MBIF Int interrupt status 213#define MBIF_A_INT_MSTAT 0x040118 // MBIF Int interrupt masked status
214#define MBIF_A_INT_MSTAT 0x040118 // MBIF Int interrupt masked status 214#define MBIF_A_INT_SSTAT 0x04011C // MBIF Int interrupt set status
215#define MBIF_A_INT_SSTAT 0x04011C // MBIF Int interrupt set status 215
216 216//*****************************************************************************
217//***************************************************************************** 217#define MBIF_B_INT_MSK 0x040120 // MBIF Int interrupt mask
218#define MBIF_B_INT_MSK 0x040120 // MBIF Int interrupt mask 218#define MBIF_B_INT_STAT 0x040124 // MBIF Int interrupt status
219#define MBIF_B_INT_STAT 0x040124 // MBIF Int interrupt status 219#define MBIF_B_INT_MSTAT 0x040128 // MBIF Int interrupt masked status
220#define MBIF_B_INT_MSTAT 0x040128 // MBIF Int interrupt masked status 220#define MBIF_B_INT_SSTAT 0x04012C // MBIF Int interrupt set status
221#define MBIF_B_INT_SSTAT 0x04012C // MBIF Int interrupt set status 221
222 222#define FLD_MBIF_DST_OPC_ERR 0x00010000
223#define FLD_MBIF_DST_OPC_ERR 0x00010000 223#define FLD_MBIF_DST_SYNC 0x00001000
224#define FLD_MBIF_DST_SYNC 0x00001000 224#define FLD_MBIF_DST_OF 0x00000100
225#define FLD_MBIF_DST_OF 0x00000100 225#define FLD_MBIF_DST_RISCI2 0x00000010
226#define FLD_MBIF_DST_RISCI2 0x00000010 226#define FLD_MBIF_DST_RISCI1 0x00000001
227#define FLD_MBIF_DST_RISCI1 0x00000001 227
228 228//*****************************************************************************
229//***************************************************************************** 229#define AUD_EXT_INT_MSK 0x040060 // Audio Ext interrupt mask
230#define AUD_EXT_INT_MSK 0x040060 // Audio Ext interrupt mask 230#define AUD_EXT_INT_STAT 0x040064 // Audio Ext interrupt status
231#define AUD_EXT_INT_STAT 0x040064 // Audio Ext interrupt status 231#define AUD_EXT_INT_MSTAT 0x040068 // Audio Ext interrupt masked status
232#define AUD_EXT_INT_MSTAT 0x040068 // Audio Ext interrupt masked status 232#define AUD_EXT_INT_SSTAT 0x04006C // Audio Ext interrupt set status
233#define AUD_EXT_INT_SSTAT 0x04006C // Audio Ext interrupt set status 233#define FLD_AUD_EXT_OPC_ERR 0x00010000
234#define FLD_AUD_EXT_OPC_ERR 0x00010000 234#define FLD_AUD_EXT_SYNC 0x00001000
235#define FLD_AUD_EXT_SYNC 0x00001000 235#define FLD_AUD_EXT_OF 0x00000100
236#define FLD_AUD_EXT_OF 0x00000100 236#define FLD_AUD_EXT_RISCI2 0x00000010
237#define FLD_AUD_EXT_RISCI2 0x00000010 237#define FLD_AUD_EXT_RISCI1 0x00000001
238#define FLD_AUD_EXT_RISCI1 0x00000001 238
239 239//*****************************************************************************
240 240#define GPIO_LO 0x110010 // Lower of GPIO pins [31:0]
241//***************************************************************************** 241#define GPIO_HI 0x110014 // Upper WORD of GPIO pins [47:31]
242#define GPIO_LO 0x110010 // Lower of GPIO pins [31:0] 242
243#define GPIO_HI 0x110014 // Upper WORD of GPIO pins [47:31] 243#define GPIO_LO_OE 0x110018 // Lower of GPIO output enable [31:0]
244 244#define GPIO_HI_OE 0x11001C // Upper word of GPIO output enable [47:32]
245#define GPIO_LO_OE 0x110018 // Lower of GPIO output enable [31:0] 245
246#define GPIO_HI_OE 0x11001C // Upper word of GPIO output enable [47:32] 246#define GPIO_LO_INT_MSK 0x11003C // GPIO interrupt mask
247 247#define GPIO_LO_INT_STAT 0x110044 // GPIO interrupt status
248#define GPIO_LO_INT_MSK 0x11003C // GPIO interrupt mask 248#define GPIO_LO_INT_MSTAT 0x11004C // GPIO interrupt masked status
249#define GPIO_LO_INT_STAT 0x110044 // GPIO interrupt status 249#define GPIO_LO_ISM_SNS 0x110054 // GPIO interrupt sensitivity
250#define GPIO_LO_INT_MSTAT 0x11004C // GPIO interrupt masked status 250#define GPIO_LO_ISM_POL 0x11005C // GPIO interrupt polarity
251#define GPIO_LO_ISM_SNS 0x110054 // GPIO interrupt sensitivity 251
252#define GPIO_LO_ISM_POL 0x11005C // GPIO interrupt polarity 252#define GPIO_HI_INT_MSK 0x110040 // GPIO interrupt mask
253 253#define GPIO_HI_INT_STAT 0x110048 // GPIO interrupt status
254#define GPIO_HI_INT_MSK 0x110040 // GPIO interrupt mask 254#define GPIO_HI_INT_MSTAT 0x110050 // GPIO interrupt masked status
255#define GPIO_HI_INT_STAT 0x110048 // GPIO interrupt status 255#define GPIO_HI_ISM_SNS 0x110058 // GPIO interrupt sensitivity
256#define GPIO_HI_INT_MSTAT 0x110050 // GPIO interrupt masked status 256#define GPIO_HI_ISM_POL 0x110060 // GPIO interrupt polarity
257#define GPIO_HI_ISM_SNS 0x110058 // GPIO interrupt sensitivity 257
258#define GPIO_HI_ISM_POL 0x110060 // GPIO interrupt polarity 258#define FLD_GPIO43_INT (1 << 11)
259 259#define FLD_GPIO42_INT (1 << 10)
260#define FLD_GPIO43_INT (1 << 11) 260#define FLD_GPIO41_INT (1 << 9)
261#define FLD_GPIO42_INT (1 << 10) 261#define FLD_GPIO40_INT (1 << 8)
262#define FLD_GPIO41_INT (1 << 9) 262
263#define FLD_GPIO40_INT (1 << 8) 263#define FLD_GPIO9_INT (1 << 9)
264 264#define FLD_GPIO8_INT (1 << 8)
265#define FLD_GPIO9_INT (1 << 9) 265#define FLD_GPIO7_INT (1 << 7)
266#define FLD_GPIO8_INT (1 << 8) 266#define FLD_GPIO6_INT (1 << 6)
267#define FLD_GPIO7_INT (1 << 7) 267#define FLD_GPIO5_INT (1 << 5)
268#define FLD_GPIO6_INT (1 << 6) 268#define FLD_GPIO4_INT (1 << 4)
269#define FLD_GPIO5_INT (1 << 5) 269#define FLD_GPIO3_INT (1 << 3)
270#define FLD_GPIO4_INT (1 << 4) 270#define FLD_GPIO2_INT (1 << 2)
271#define FLD_GPIO3_INT (1 << 3) 271#define FLD_GPIO1_INT (1 << 1)
272#define FLD_GPIO2_INT (1 << 2) 272#define FLD_GPIO0_INT (1 << 0)
273#define FLD_GPIO1_INT (1 << 1) 273
274#define FLD_GPIO0_INT (1 << 0) 274//*****************************************************************************
275 275#define TC_REQ 0x040090 // Rider PCI Express traFFic class request
276//***************************************************************************** 276
277#define TC_REQ 0x040090 // Rider PCI Express traFFic class request 277//*****************************************************************************
278 278#define TC_REQ_SET 0x040094 // Rider PCI Express traFFic class request set
279//***************************************************************************** 279
280#define TC_REQ_SET 0x040094 // Rider PCI Express traFFic class request set 280//*****************************************************************************
281 281// Rider
282 282//*****************************************************************************
283//***************************************************************************** 283
284// Rider 284// PCI Compatible Header
285//***************************************************************************** 285//*****************************************************************************
286 286#define RDR_CFG0 0x050000
287// PCI Compatible Header 287#define RDR_VENDOR_DEVICE_ID_CFG 0x050000
288//***************************************************************************** 288
289#define RDR_CFG0 0x050000 289//*****************************************************************************
290#define RDR_VENDOR_DEVICE_ID_CFG 0x050000 290#define RDR_CFG1 0x050004
291 291
292//***************************************************************************** 292//*****************************************************************************
293#define RDR_CFG1 0x050004 293#define RDR_CFG2 0x050008
294 294
295//***************************************************************************** 295//*****************************************************************************
296#define RDR_CFG2 0x050008 296#define RDR_CFG3 0x05000C
297 297
298//***************************************************************************** 298//*****************************************************************************
299#define RDR_CFG3 0x05000C 299#define RDR_CFG4 0x050010
300 300
301//***************************************************************************** 301//*****************************************************************************
302#define RDR_CFG4 0x050010 302#define RDR_CFG5 0x050014
303 303
304//***************************************************************************** 304//*****************************************************************************
305#define RDR_CFG5 0x050014 305#define RDR_CFG6 0x050018
306 306
307//***************************************************************************** 307//*****************************************************************************
308#define RDR_CFG6 0x050018 308#define RDR_CFG7 0x05001C
309 309
310//***************************************************************************** 310//*****************************************************************************
311#define RDR_CFG7 0x05001C 311#define RDR_CFG8 0x050020
312 312
313//***************************************************************************** 313//*****************************************************************************
314#define RDR_CFG8 0x050020 314#define RDR_CFG9 0x050024
315 315
316//***************************************************************************** 316//*****************************************************************************
317#define RDR_CFG9 0x050024 317#define RDR_CFGA 0x050028
318 318
319//***************************************************************************** 319//*****************************************************************************
320#define RDR_CFGA 0x050028 320#define RDR_CFGB 0x05002C
321 321#define RDR_SUSSYSTEM_ID_CFG 0x05002C
322//***************************************************************************** 322
323#define RDR_CFGB 0x05002C 323//*****************************************************************************
324#define RDR_SUSSYSTEM_ID_CFG 0x05002C 324#define RDR_CFGC 0x050030
325 325
326//***************************************************************************** 326//*****************************************************************************
327#define RDR_CFGC 0x050030 327#define RDR_CFGD 0x050034
328 328
329//***************************************************************************** 329//*****************************************************************************
330#define RDR_CFGD 0x050034 330#define RDR_CFGE 0x050038
331 331
332//***************************************************************************** 332//*****************************************************************************
333#define RDR_CFGE 0x050038 333#define RDR_CFGF 0x05003C
334 334
335//***************************************************************************** 335//*****************************************************************************
336#define RDR_CFGF 0x05003C 336// PCI-Express Capabilities
337 337//*****************************************************************************
338//***************************************************************************** 338#define RDR_PECAP 0x050040
339// PCI-Express Capabilities 339
340//***************************************************************************** 340//*****************************************************************************
341#define RDR_PECAP 0x050040 341#define RDR_PEDEVCAP 0x050044
342 342
343//***************************************************************************** 343//*****************************************************************************
344#define RDR_PEDEVCAP 0x050044 344#define RDR_PEDEVSC 0x050048
345 345
346//***************************************************************************** 346//*****************************************************************************
347#define RDR_PEDEVSC 0x050048 347#define RDR_PELINKCAP 0x05004C
348 348
349//***************************************************************************** 349//*****************************************************************************
350#define RDR_PELINKCAP 0x05004C 350#define RDR_PELINKSC 0x050050
351 351
352//***************************************************************************** 352//*****************************************************************************
353#define RDR_PELINKSC 0x050050 353#define RDR_PMICAP 0x050080
354 354
355//***************************************************************************** 355//*****************************************************************************
356#define RDR_PMICAP 0x050080 356#define RDR_PMCSR 0x050084
357 357
358//***************************************************************************** 358//*****************************************************************************
359#define RDR_PMCSR 0x050084 359#define RDR_VPDCAP 0x050090
360 360
361//***************************************************************************** 361//*****************************************************************************
362#define RDR_VPDCAP 0x050090 362#define RDR_VPDDATA 0x050094
363 363
364//***************************************************************************** 364//*****************************************************************************
365#define RDR_VPDDATA 0x050094 365#define RDR_MSICAP 0x0500A0
366 366
367//***************************************************************************** 367//*****************************************************************************
368#define RDR_MSICAP 0x0500A0 368#define RDR_MSIARL 0x0500A4
369 369
370//***************************************************************************** 370//*****************************************************************************
371#define RDR_MSIARL 0x0500A4 371#define RDR_MSIARU 0x0500A8
372 372
373//***************************************************************************** 373//*****************************************************************************
374#define RDR_MSIARU 0x0500A8 374#define RDR_MSIDATA 0x0500AC
375 375
376//***************************************************************************** 376//*****************************************************************************
377#define RDR_MSIDATA 0x0500AC 377// PCI Express Extended Capabilities
378 378//*****************************************************************************
379//***************************************************************************** 379#define RDR_AERXCAP 0x050100
380// PCI Express Extended Capabilities 380
381//***************************************************************************** 381//*****************************************************************************
382#define RDR_AERXCAP 0x050100 382#define RDR_AERUESTA 0x050104
383 383
384//***************************************************************************** 384//*****************************************************************************
385#define RDR_AERUESTA 0x050104 385#define RDR_AERUEMSK 0x050108
386 386
387//***************************************************************************** 387//*****************************************************************************
388#define RDR_AERUEMSK 0x050108 388#define RDR_AERUESEV 0x05010C
389 389
390//***************************************************************************** 390//*****************************************************************************
391#define RDR_AERUESEV 0x05010C 391#define RDR_AERCESTA 0x050110
392 392
393//***************************************************************************** 393//*****************************************************************************
394#define RDR_AERCESTA 0x050110 394#define RDR_AERCEMSK 0x050114
395 395
396//***************************************************************************** 396//*****************************************************************************
397#define RDR_AERCEMSK 0x050114 397#define RDR_AERCC 0x050118
398 398
399//***************************************************************************** 399//*****************************************************************************
400#define RDR_AERCC 0x050118 400#define RDR_AERHL0 0x05011C
401 401
402//***************************************************************************** 402//*****************************************************************************
403#define RDR_AERHL0 0x05011C 403#define RDR_AERHL1 0x050120
404 404
405//***************************************************************************** 405//*****************************************************************************
406#define RDR_AERHL1 0x050120 406#define RDR_AERHL2 0x050124
407 407
408//***************************************************************************** 408//*****************************************************************************
409#define RDR_AERHL2 0x050124 409#define RDR_AERHL3 0x050128
410 410
411//***************************************************************************** 411//*****************************************************************************
412#define RDR_AERHL3 0x050128 412#define RDR_VCXCAP 0x050200
413 413
414//***************************************************************************** 414//*****************************************************************************
415#define RDR_VCXCAP 0x050200 415#define RDR_VCCAP1 0x050204
416 416
417//***************************************************************************** 417//*****************************************************************************
418#define RDR_VCCAP1 0x050204 418#define RDR_VCCAP2 0x050208
419 419
420//***************************************************************************** 420//*****************************************************************************
421#define RDR_VCCAP2 0x050208 421#define RDR_VCSC 0x05020C
422 422
423//***************************************************************************** 423//*****************************************************************************
424#define RDR_VCSC 0x05020C 424#define RDR_VCR0_CAP 0x050210
425 425
426//***************************************************************************** 426//*****************************************************************************
427#define RDR_VCR0_CAP 0x050210 427#define RDR_VCR0_CTRL 0x050214
428 428
429//***************************************************************************** 429//*****************************************************************************
430#define RDR_VCR0_CTRL 0x050214 430#define RDR_VCR0_STAT 0x050218
431 431
432//***************************************************************************** 432//*****************************************************************************
433#define RDR_VCR0_STAT 0x050218 433#define RDR_VCR1_CAP 0x05021C
434 434
435//***************************************************************************** 435//*****************************************************************************
436#define RDR_VCR1_CAP 0x05021C 436#define RDR_VCR1_CTRL 0x050220
437 437
438//***************************************************************************** 438//*****************************************************************************
439#define RDR_VCR1_CTRL 0x050220 439#define RDR_VCR1_STAT 0x050224
440 440
441//***************************************************************************** 441//*****************************************************************************
442#define RDR_VCR1_STAT 0x050224 442#define RDR_VCR2_CAP 0x050228
443 443
444//***************************************************************************** 444//*****************************************************************************
445#define RDR_VCR2_CAP 0x050228 445#define RDR_VCR2_CTRL 0x05022C
446 446
447//***************************************************************************** 447//*****************************************************************************
448#define RDR_VCR2_CTRL 0x05022C 448#define RDR_VCR2_STAT 0x050230
449 449
450//***************************************************************************** 450//*****************************************************************************
451#define RDR_VCR2_STAT 0x050230 451#define RDR_VCR3_CAP 0x050234
452 452
453//***************************************************************************** 453//*****************************************************************************
454#define RDR_VCR3_CAP 0x050234 454#define RDR_VCR3_CTRL 0x050238
455 455
456//***************************************************************************** 456//*****************************************************************************
457#define RDR_VCR3_CTRL 0x050238 457#define RDR_VCR3_STAT 0x05023C
458 458
459//***************************************************************************** 459//*****************************************************************************
460#define RDR_VCR3_STAT 0x05023C 460#define RDR_VCARB0 0x050240
461 461
462//***************************************************************************** 462//*****************************************************************************
463#define RDR_VCARB0 0x050240 463#define RDR_VCARB1 0x050244
464 464
465//***************************************************************************** 465//*****************************************************************************
466#define RDR_VCARB1 0x050244 466#define RDR_VCARB2 0x050248
467 467
468//***************************************************************************** 468//*****************************************************************************
469#define RDR_VCARB2 0x050248 469#define RDR_VCARB3 0x05024C
470 470
471//***************************************************************************** 471//*****************************************************************************
472#define RDR_VCARB3 0x05024C 472#define RDR_VCARB4 0x050250
473 473
474//***************************************************************************** 474//*****************************************************************************
475#define RDR_VCARB4 0x050250 475#define RDR_VCARB5 0x050254
476 476
477//***************************************************************************** 477//*****************************************************************************
478#define RDR_VCARB5 0x050254 478#define RDR_VCARB6 0x050258
479 479
480//***************************************************************************** 480//*****************************************************************************
481#define RDR_VCARB6 0x050258 481#define RDR_VCARB7 0x05025C
482 482
483//***************************************************************************** 483//*****************************************************************************
484#define RDR_VCARB7 0x05025C 484#define RDR_RDRSTAT0 0x050300
485 485
486//***************************************************************************** 486//*****************************************************************************
487#define RDR_RDRSTAT0 0x050300 487#define RDR_RDRSTAT1 0x050304
488 488
489//***************************************************************************** 489//*****************************************************************************
490#define RDR_RDRSTAT1 0x050304 490#define RDR_RDRCTL0 0x050308
491 491
492//***************************************************************************** 492//*****************************************************************************
493#define RDR_RDRCTL0 0x050308 493#define RDR_RDRCTL1 0x05030C
494 494
495//***************************************************************************** 495//*****************************************************************************
496#define RDR_RDRCTL1 0x05030C 496// Transaction Layer Registers
497 497//*****************************************************************************
498//***************************************************************************** 498#define RDR_TLSTAT0 0x050310
499// Transaction Layer Registers 499
500//***************************************************************************** 500//*****************************************************************************
501#define RDR_TLSTAT0 0x050310 501#define RDR_TLSTAT1 0x050314
502 502
503//***************************************************************************** 503//*****************************************************************************
504#define RDR_TLSTAT1 0x050314 504#define RDR_TLCTL0 0x050318
505 505#define FLD_CFG_UR_CPL_MODE 0x00000040
506//***************************************************************************** 506#define FLD_CFG_CORR_ERR_QUITE 0x00000020
507#define RDR_TLCTL0 0x050318 507#define FLD_CFG_RCB_CK_EN 0x00000010
508#define FLD_CFG_UR_CPL_MODE 0x00000040 508#define FLD_CFG_BNDRY_CK_EN 0x00000008
509#define FLD_CFG_CORR_ERR_QUITE 0x00000020 509#define FLD_CFG_BYTE_EN_CK_EN 0x00000004
510#define FLD_CFG_RCB_CK_EN 0x00000010 510#define FLD_CFG_RELAX_ORDER_MSK 0x00000002
511#define FLD_CFG_BNDRY_CK_EN 0x00000008 511#define FLD_CFG_TAG_ORDER_EN 0x00000001
512#define FLD_CFG_BYTE_EN_CK_EN 0x00000004 512
513#define FLD_CFG_RELAX_ORDER_MSK 0x00000002 513//*****************************************************************************
514#define FLD_CFG_TAG_ORDER_EN 0x00000001 514#define RDR_TLCTL1 0x05031C
515 515
516//***************************************************************************** 516//*****************************************************************************
517#define RDR_TLCTL1 0x05031C 517#define RDR_REQRCAL 0x050320
518 518
519//***************************************************************************** 519//*****************************************************************************
520#define RDR_REQRCAL 0x050320 520#define RDR_REQRCAU 0x050324
521 521
522//***************************************************************************** 522//*****************************************************************************
523#define RDR_REQRCAU 0x050324 523#define RDR_REQEPA 0x050328
524 524
525//***************************************************************************** 525//*****************************************************************************
526#define RDR_REQEPA 0x050328 526#define RDR_REQCTRL 0x05032C
527 527
528//***************************************************************************** 528//*****************************************************************************
529#define RDR_REQCTRL 0x05032C 529#define RDR_REQSTAT 0x050330
530 530
531//***************************************************************************** 531//*****************************************************************************
532#define RDR_REQSTAT 0x050330 532#define RDR_TL_TEST 0x050334
533 533
534//***************************************************************************** 534//*****************************************************************************
535#define RDR_TL_TEST 0x050334 535#define RDR_VCR01_CTL 0x050348
536 536
537//***************************************************************************** 537//*****************************************************************************
538#define RDR_VCR01_CTL 0x050348 538#define RDR_VCR23_CTL 0x05034C
539 539
540//***************************************************************************** 540//*****************************************************************************
541#define RDR_VCR23_CTL 0x05034C 541#define RDR_RX_VCR0_FC 0x050350
542 542
543//***************************************************************************** 543//*****************************************************************************
544#define RDR_RX_VCR0_FC 0x050350 544#define RDR_RX_VCR1_FC 0x050354
545 545
546//***************************************************************************** 546//*****************************************************************************
547#define RDR_RX_VCR1_FC 0x050354 547#define RDR_RX_VCR2_FC 0x050358
548 548
549//***************************************************************************** 549//*****************************************************************************
550#define RDR_RX_VCR2_FC 0x050358 550#define RDR_RX_VCR3_FC 0x05035C
551 551
552//***************************************************************************** 552//*****************************************************************************
553#define RDR_RX_VCR3_FC 0x05035C 553// Data Link Layer Registers
554 554//*****************************************************************************
555//***************************************************************************** 555#define RDR_DLLSTAT 0x050360
556// Data Link Layer Registers 556
557//***************************************************************************** 557//*****************************************************************************
558#define RDR_DLLSTAT 0x050360 558#define RDR_DLLCTRL 0x050364
559 559
560//***************************************************************************** 560//*****************************************************************************
561#define RDR_DLLCTRL 0x050364 561#define RDR_REPLAYTO 0x050368
562 562
563//***************************************************************************** 563//*****************************************************************************
564#define RDR_REPLAYTO 0x050368 564#define RDR_ACKLATTO 0x05036C
565 565
566//***************************************************************************** 566//*****************************************************************************
567#define RDR_ACKLATTO 0x05036C 567// MAC Layer Registers
568 568//*****************************************************************************
569//***************************************************************************** 569#define RDR_MACSTAT0 0x050380
570// MAC Layer Registers 570
571//***************************************************************************** 571//*****************************************************************************
572#define RDR_MACSTAT0 0x050380 572#define RDR_MACSTAT1 0x050384
573 573
574//***************************************************************************** 574//*****************************************************************************
575#define RDR_MACSTAT1 0x050384 575#define RDR_MACCTRL0 0x050388
576 576
577//***************************************************************************** 577//*****************************************************************************
578#define RDR_MACCTRL0 0x050388 578#define RDR_MACCTRL1 0x05038C
579 579
580//***************************************************************************** 580//*****************************************************************************
581#define RDR_MACCTRL1 0x05038C 581#define RDR_MACCTRL2 0x050390
582 582
583//***************************************************************************** 583//*****************************************************************************
584#define RDR_MACCTRL2 0x050390 584#define RDR_MAC_LB_DATA 0x050394
585 585
586//***************************************************************************** 586//*****************************************************************************
587#define RDR_MAC_LB_DATA 0x050394 587#define RDR_L0S_EXIT_LAT 0x050398
588 588
589//***************************************************************************** 589//*****************************************************************************
590#define RDR_L0S_EXIT_LAT 0x050398 590// DMAC
591 591//*****************************************************************************
592//***************************************************************************** 592#define DMA1_PTR1 0x100000 // DMA Current Ptr : Ch#1
593// DMAC 593
594//***************************************************************************** 594//*****************************************************************************
595#define DMA1_PTR1 0x100000 // DMA Current Ptr : Ch#1 595#define DMA2_PTR1 0x100004 // DMA Current Ptr : Ch#2
596 596
597//***************************************************************************** 597//*****************************************************************************
598#define DMA2_PTR1 0x100004 // DMA Current Ptr : Ch#2 598#define DMA3_PTR1 0x100008 // DMA Current Ptr : Ch#3
599 599
600//***************************************************************************** 600//*****************************************************************************
601#define DMA3_PTR1 0x100008 // DMA Current Ptr : Ch#3 601#define DMA4_PTR1 0x10000C // DMA Current Ptr : Ch#4
602 602
603//***************************************************************************** 603//*****************************************************************************
604#define DMA4_PTR1 0x10000C // DMA Current Ptr : Ch#4 604#define DMA5_PTR1 0x100010 // DMA Current Ptr : Ch#5
605 605
606//***************************************************************************** 606//*****************************************************************************
607#define DMA5_PTR1 0x100010 // DMA Current Ptr : Ch#5 607#define DMA6_PTR1 0x100014 // DMA Current Ptr : Ch#6
608 608
609//***************************************************************************** 609//*****************************************************************************
610#define DMA6_PTR1 0x100014 // DMA Current Ptr : Ch#6 610#define DMA7_PTR1 0x100018 // DMA Current Ptr : Ch#7
611 611
612//***************************************************************************** 612//*****************************************************************************
613#define DMA7_PTR1 0x100018 // DMA Current Ptr : Ch#7 613#define DMA8_PTR1 0x10001C // DMA Current Ptr : Ch#8
614 614
615//***************************************************************************** 615//*****************************************************************************
616#define DMA8_PTR1 0x10001C // DMA Current Ptr : Ch#8 616#define DMA9_PTR1 0x100020 // DMA Current Ptr : Ch#9
617 617
618//***************************************************************************** 618//*****************************************************************************
619#define DMA9_PTR1 0x100020 // DMA Current Ptr : Ch#9 619#define DMA10_PTR1 0x100024 // DMA Current Ptr : Ch#10
620 620
621//***************************************************************************** 621//*****************************************************************************
622#define DMA10_PTR1 0x100024 // DMA Current Ptr : Ch#10 622#define DMA11_PTR1 0x100028 // DMA Current Ptr : Ch#11
623 623
624//***************************************************************************** 624//*****************************************************************************
625#define DMA11_PTR1 0x100028 // DMA Current Ptr : Ch#11 625#define DMA12_PTR1 0x10002C // DMA Current Ptr : Ch#12
626 626
627//***************************************************************************** 627//*****************************************************************************
628#define DMA12_PTR1 0x10002C // DMA Current Ptr : Ch#12 628#define DMA13_PTR1 0x100030 // DMA Current Ptr : Ch#13
629 629
630//***************************************************************************** 630//*****************************************************************************
631#define DMA13_PTR1 0x100030 // DMA Current Ptr : Ch#13 631#define DMA14_PTR1 0x100034 // DMA Current Ptr : Ch#14
632 632
633//***************************************************************************** 633//*****************************************************************************
634#define DMA14_PTR1 0x100034 // DMA Current Ptr : Ch#14 634#define DMA15_PTR1 0x100038 // DMA Current Ptr : Ch#15
635 635
636//***************************************************************************** 636//*****************************************************************************
637#define DMA15_PTR1 0x100038 // DMA Current Ptr : Ch#15 637#define DMA16_PTR1 0x10003C // DMA Current Ptr : Ch#16
638 638
639//***************************************************************************** 639//*****************************************************************************
640#define DMA16_PTR1 0x10003C // DMA Current Ptr : Ch#16 640#define DMA17_PTR1 0x100040 // DMA Current Ptr : Ch#17
641 641
642//***************************************************************************** 642//*****************************************************************************
643#define DMA17_PTR1 0x100040 // DMA Current Ptr : Ch#17 643#define DMA18_PTR1 0x100044 // DMA Current Ptr : Ch#18
644 644
645//***************************************************************************** 645//*****************************************************************************
646#define DMA18_PTR1 0x100044 // DMA Current Ptr : Ch#18 646#define DMA19_PTR1 0x100048 // DMA Current Ptr : Ch#19
647 647
648//***************************************************************************** 648//*****************************************************************************
649#define DMA19_PTR1 0x100048 // DMA Current Ptr : Ch#19 649#define DMA20_PTR1 0x10004C // DMA Current Ptr : Ch#20
650 650
651//***************************************************************************** 651//*****************************************************************************
652#define DMA20_PTR1 0x10004C // DMA Current Ptr : Ch#20 652#define DMA21_PTR1 0x100050 // DMA Current Ptr : Ch#21
653 653
654//***************************************************************************** 654//*****************************************************************************
655#define DMA21_PTR1 0x100050 // DMA Current Ptr : Ch#21 655#define DMA22_PTR1 0x100054 // DMA Current Ptr : Ch#22
656 656
657//***************************************************************************** 657//*****************************************************************************
658#define DMA22_PTR1 0x100054 // DMA Current Ptr : Ch#22 658#define DMA23_PTR1 0x100058 // DMA Current Ptr : Ch#23
659 659
660//***************************************************************************** 660//*****************************************************************************
661#define DMA23_PTR1 0x100058 // DMA Current Ptr : Ch#23 661#define DMA24_PTR1 0x10005C // DMA Current Ptr : Ch#24
662 662
663//***************************************************************************** 663//*****************************************************************************
664#define DMA24_PTR1 0x10005C // DMA Current Ptr : Ch#24 664#define DMA25_PTR1 0x100060 // DMA Current Ptr : Ch#25
665 665
666//***************************************************************************** 666//*****************************************************************************
667#define DMA25_PTR1 0x100060 // DMA Current Ptr : Ch#25 667#define DMA26_PTR1 0x100064 // DMA Current Ptr : Ch#26
668 668
669//***************************************************************************** 669//*****************************************************************************
670#define DMA26_PTR1 0x100064 // DMA Current Ptr : Ch#26 670#define DMA1_PTR2 0x100080 // DMA Tab Ptr : Ch#1
671 671
672 672//*****************************************************************************
673//***************************************************************************** 673#define DMA2_PTR2 0x100084 // DMA Tab Ptr : Ch#2
674#define DMA1_PTR2 0x100080 // DMA Tab Ptr : Ch#1 674
675 675//*****************************************************************************
676//***************************************************************************** 676#define DMA3_PTR2 0x100088 // DMA Tab Ptr : Ch#3
677#define DMA2_PTR2 0x100084 // DMA Tab Ptr : Ch#2 677
678 678//*****************************************************************************
679//***************************************************************************** 679#define DMA4_PTR2 0x10008C // DMA Tab Ptr : Ch#4
680#define DMA3_PTR2 0x100088 // DMA Tab Ptr : Ch#3 680
681 681//*****************************************************************************
682//***************************************************************************** 682#define DMA5_PTR2 0x100090 // DMA Tab Ptr : Ch#5
683#define DMA4_PTR2 0x10008C // DMA Tab Ptr : Ch#4 683
684 684//*****************************************************************************
685//***************************************************************************** 685#define DMA6_PTR2 0x100094 // DMA Tab Ptr : Ch#6
686#define DMA5_PTR2 0x100090 // DMA Tab Ptr : Ch#5 686
687 687//*****************************************************************************
688//***************************************************************************** 688#define DMA7_PTR2 0x100098 // DMA Tab Ptr : Ch#7
689#define DMA6_PTR2 0x100094 // DMA Tab Ptr : Ch#6 689
690 690//*****************************************************************************
691//***************************************************************************** 691#define DMA8_PTR2 0x10009C // DMA Tab Ptr : Ch#8
692#define DMA7_PTR2 0x100098 // DMA Tab Ptr : Ch#7 692
693 693//*****************************************************************************
694//***************************************************************************** 694#define DMA9_PTR2 0x1000A0 // DMA Tab Ptr : Ch#9
695#define DMA8_PTR2 0x10009C // DMA Tab Ptr : Ch#8 695
696 696//*****************************************************************************
697//***************************************************************************** 697#define DMA10_PTR2 0x1000A4 // DMA Tab Ptr : Ch#10
698#define DMA9_PTR2 0x1000A0 // DMA Tab Ptr : Ch#9 698
699 699//*****************************************************************************
700//***************************************************************************** 700#define DMA11_PTR2 0x1000A8 // DMA Tab Ptr : Ch#11
701#define DMA10_PTR2 0x1000A4 // DMA Tab Ptr : Ch#10 701
702 702//*****************************************************************************
703//***************************************************************************** 703#define DMA12_PTR2 0x1000AC // DMA Tab Ptr : Ch#12
704#define DMA11_PTR2 0x1000A8 // DMA Tab Ptr : Ch#11 704
705 705//*****************************************************************************
706//***************************************************************************** 706#define DMA13_PTR2 0x1000B0 // DMA Tab Ptr : Ch#13
707#define DMA12_PTR2 0x1000AC // DMA Tab Ptr : Ch#12 707
708 708//*****************************************************************************
709//***************************************************************************** 709#define DMA14_PTR2 0x1000B4 // DMA Tab Ptr : Ch#14
710#define DMA13_PTR2 0x1000B0 // DMA Tab Ptr : Ch#13 710
711 711//*****************************************************************************
712//***************************************************************************** 712#define DMA15_PTR2 0x1000B8 // DMA Tab Ptr : Ch#15
713#define DMA14_PTR2 0x1000B4 // DMA Tab Ptr : Ch#14 713
714 714//*****************************************************************************
715//***************************************************************************** 715#define DMA16_PTR2 0x1000BC // DMA Tab Ptr : Ch#16
716#define DMA15_PTR2 0x1000B8 // DMA Tab Ptr : Ch#15 716
717 717//*****************************************************************************
718//***************************************************************************** 718#define DMA17_PTR2 0x1000C0 // DMA Tab Ptr : Ch#17
719#define DMA16_PTR2 0x1000BC // DMA Tab Ptr : Ch#16 719
720 720//*****************************************************************************
721//***************************************************************************** 721#define DMA18_PTR2 0x1000C4 // DMA Tab Ptr : Ch#18
722#define DMA17_PTR2 0x1000C0 // DMA Tab Ptr : Ch#17 722
723 723//*****************************************************************************
724//***************************************************************************** 724#define DMA19_PTR2 0x1000C8 // DMA Tab Ptr : Ch#19
725#define DMA18_PTR2 0x1000C4 // DMA Tab Ptr : Ch#18 725
726 726//*****************************************************************************
727//***************************************************************************** 727#define DMA20_PTR2 0x1000CC // DMA Tab Ptr : Ch#20
728#define DMA19_PTR2 0x1000C8 // DMA Tab Ptr : Ch#19 728
729 729//*****************************************************************************
730//***************************************************************************** 730#define DMA21_PTR2 0x1000D0 // DMA Tab Ptr : Ch#21
731#define DMA20_PTR2 0x1000CC // DMA Tab Ptr : Ch#20 731
732 732//*****************************************************************************
733//***************************************************************************** 733#define DMA22_PTR2 0x1000D4 // DMA Tab Ptr : Ch#22
734#define DMA21_PTR2 0x1000D0 // DMA Tab Ptr : Ch#21 734
735 735//*****************************************************************************
736//***************************************************************************** 736#define DMA23_PTR2 0x1000D8 // DMA Tab Ptr : Ch#23
737#define DMA22_PTR2 0x1000D4 // DMA Tab Ptr : Ch#22 737
738 738//*****************************************************************************
739//***************************************************************************** 739#define DMA24_PTR2 0x1000DC // DMA Tab Ptr : Ch#24
740#define DMA23_PTR2 0x1000D8 // DMA Tab Ptr : Ch#23 740
741 741//*****************************************************************************
742//***************************************************************************** 742#define DMA25_PTR2 0x1000E0 // DMA Tab Ptr : Ch#25
743#define DMA24_PTR2 0x1000DC // DMA Tab Ptr : Ch#24 743
744 744//*****************************************************************************
745//***************************************************************************** 745#define DMA26_PTR2 0x1000E4 // DMA Tab Ptr : Ch#26
746#define DMA25_PTR2 0x1000E0 // DMA Tab Ptr : Ch#25 746
747 747//*****************************************************************************
748//***************************************************************************** 748#define DMA1_CNT1 0x100100 // DMA BuFFer Size : Ch#1
749#define DMA26_PTR2 0x1000E4 // DMA Tab Ptr : Ch#26 749
750 750//*****************************************************************************
751 751#define DMA2_CNT1 0x100104 // DMA BuFFer Size : Ch#2
752 752
753//***************************************************************************** 753//*****************************************************************************
754#define DMA1_CNT1 0x100100 // DMA BuFFer Size : Ch#1 754#define DMA3_CNT1 0x100108 // DMA BuFFer Size : Ch#3
755 755
756//***************************************************************************** 756//*****************************************************************************
757#define DMA2_CNT1 0x100104 // DMA BuFFer Size : Ch#2 757#define DMA4_CNT1 0x10010C // DMA BuFFer Size : Ch#4
758 758
759//***************************************************************************** 759//*****************************************************************************
760#define DMA3_CNT1 0x100108 // DMA BuFFer Size : Ch#3 760#define DMA5_CNT1 0x100110 // DMA BuFFer Size : Ch#5
761 761
762//***************************************************************************** 762//*****************************************************************************
763#define DMA4_CNT1 0x10010C // DMA BuFFer Size : Ch#4 763#define DMA6_CNT1 0x100114 // DMA BuFFer Size : Ch#6
764 764
765//***************************************************************************** 765//*****************************************************************************
766#define DMA5_CNT1 0x100110 // DMA BuFFer Size : Ch#5 766#define DMA7_CNT1 0x100118 // DMA BuFFer Size : Ch#7
767 767
768//***************************************************************************** 768//*****************************************************************************
769#define DMA6_CNT1 0x100114 // DMA BuFFer Size : Ch#6 769#define DMA8_CNT1 0x10011C // DMA BuFFer Size : Ch#8
770 770
771//***************************************************************************** 771//*****************************************************************************
772#define DMA7_CNT1 0x100118 // DMA BuFFer Size : Ch#7 772#define DMA9_CNT1 0x100120 // DMA BuFFer Size : Ch#9
773 773
774//***************************************************************************** 774//*****************************************************************************
775#define DMA8_CNT1 0x10011C // DMA BuFFer Size : Ch#8 775#define DMA10_CNT1 0x100124 // DMA BuFFer Size : Ch#10
776 776
777//***************************************************************************** 777//*****************************************************************************
778#define DMA9_CNT1 0x100120 // DMA BuFFer Size : Ch#9 778#define DMA11_CNT1 0x100128 // DMA BuFFer Size : Ch#11
779 779
780//***************************************************************************** 780//*****************************************************************************
781#define DMA10_CNT1 0x100124 // DMA BuFFer Size : Ch#10 781#define DMA12_CNT1 0x10012C // DMA BuFFer Size : Ch#12
782 782
783//***************************************************************************** 783//*****************************************************************************
784#define DMA11_CNT1 0x100128 // DMA BuFFer Size : Ch#11 784#define DMA13_CNT1 0x100130 // DMA BuFFer Size : Ch#13
785 785
786//***************************************************************************** 786//*****************************************************************************
787#define DMA12_CNT1 0x10012C // DMA BuFFer Size : Ch#12 787#define DMA14_CNT1 0x100134 // DMA BuFFer Size : Ch#14
788 788
789//***************************************************************************** 789//*****************************************************************************
790#define DMA13_CNT1 0x100130 // DMA BuFFer Size : Ch#13 790#define DMA15_CNT1 0x100138 // DMA BuFFer Size : Ch#15
791 791
792//***************************************************************************** 792//*****************************************************************************
793#define DMA14_CNT1 0x100134 // DMA BuFFer Size : Ch#14 793#define DMA16_CNT1 0x10013C // DMA BuFFer Size : Ch#16
794 794
795//***************************************************************************** 795//*****************************************************************************
796#define DMA15_CNT1 0x100138 // DMA BuFFer Size : Ch#15 796#define DMA17_CNT1 0x100140 // DMA BuFFer Size : Ch#17
797 797
798//***************************************************************************** 798//*****************************************************************************
799#define DMA16_CNT1 0x10013C // DMA BuFFer Size : Ch#16 799#define DMA18_CNT1 0x100144 // DMA BuFFer Size : Ch#18
800 800
801//***************************************************************************** 801//*****************************************************************************
802#define DMA17_CNT1 0x100140 // DMA BuFFer Size : Ch#17 802#define DMA19_CNT1 0x100148 // DMA BuFFer Size : Ch#19
803 803
804//***************************************************************************** 804//*****************************************************************************
805#define DMA18_CNT1 0x100144 // DMA BuFFer Size : Ch#18 805#define DMA20_CNT1 0x10014C // DMA BuFFer Size : Ch#20
806 806
807//***************************************************************************** 807//*****************************************************************************
808#define DMA19_CNT1 0x100148 // DMA BuFFer Size : Ch#19 808#define DMA21_CNT1 0x100150 // DMA BuFFer Size : Ch#21
809 809
810//***************************************************************************** 810//*****************************************************************************
811#define DMA20_CNT1 0x10014C // DMA BuFFer Size : Ch#20 811#define DMA22_CNT1 0x100154 // DMA BuFFer Size : Ch#22
812 812
813//***************************************************************************** 813//*****************************************************************************
814#define DMA21_CNT1 0x100150 // DMA BuFFer Size : Ch#21 814#define DMA23_CNT1 0x100158 // DMA BuFFer Size : Ch#23
815 815
816//***************************************************************************** 816//*****************************************************************************
817#define DMA22_CNT1 0x100154 // DMA BuFFer Size : Ch#22 817#define DMA24_CNT1 0x10015C // DMA BuFFer Size : Ch#24
818 818
819//***************************************************************************** 819//*****************************************************************************
820#define DMA23_CNT1 0x100158 // DMA BuFFer Size : Ch#23 820#define DMA25_CNT1 0x100160 // DMA BuFFer Size : Ch#25
821 821
822//***************************************************************************** 822//*****************************************************************************
823#define DMA24_CNT1 0x10015C // DMA BuFFer Size : Ch#24 823#define DMA26_CNT1 0x100164 // DMA BuFFer Size : Ch#26
824 824
825//***************************************************************************** 825//*****************************************************************************
826#define DMA25_CNT1 0x100160 // DMA BuFFer Size : Ch#25 826#define DMA1_CNT2 0x100180 // DMA Table Size : Ch#1
827 827
828//***************************************************************************** 828//*****************************************************************************
829#define DMA26_CNT1 0x100164 // DMA BuFFer Size : Ch#26 829#define DMA2_CNT2 0x100184 // DMA Table Size : Ch#2
830 830
831 831//*****************************************************************************
832//***************************************************************************** 832#define DMA3_CNT2 0x100188 // DMA Table Size : Ch#3
833#define DMA1_CNT2 0x100180 // DMA Table Size : Ch#1 833
834 834//*****************************************************************************
835//***************************************************************************** 835#define DMA4_CNT2 0x10018C // DMA Table Size : Ch#4
836#define DMA2_CNT2 0x100184 // DMA Table Size : Ch#2 836
837 837//*****************************************************************************
838//***************************************************************************** 838#define DMA5_CNT2 0x100190 // DMA Table Size : Ch#5
839#define DMA3_CNT2 0x100188 // DMA Table Size : Ch#3 839
840 840//*****************************************************************************
841//***************************************************************************** 841#define DMA6_CNT2 0x100194 // DMA Table Size : Ch#6
842#define DMA4_CNT2 0x10018C // DMA Table Size : Ch#4 842
843 843//*****************************************************************************
844//***************************************************************************** 844#define DMA7_CNT2 0x100198 // DMA Table Size : Ch#7
845#define DMA5_CNT2 0x100190 // DMA Table Size : Ch#5 845
846 846//*****************************************************************************
847//***************************************************************************** 847#define DMA8_CNT2 0x10019C // DMA Table Size : Ch#8
848#define DMA6_CNT2 0x100194 // DMA Table Size : Ch#6 848
849 849//*****************************************************************************
850//***************************************************************************** 850#define DMA9_CNT2 0x1001A0 // DMA Table Size : Ch#9
851#define DMA7_CNT2 0x100198 // DMA Table Size : Ch#7 851
852 852//*****************************************************************************
853//***************************************************************************** 853#define DMA10_CNT2 0x1001A4 // DMA Table Size : Ch#10
854#define DMA8_CNT2 0x10019C // DMA Table Size : Ch#8 854
855 855//*****************************************************************************
856//***************************************************************************** 856#define DMA11_CNT2 0x1001A8 // DMA Table Size : Ch#11
857#define DMA9_CNT2 0x1001A0 // DMA Table Size : Ch#9 857
858 858//*****************************************************************************
859//***************************************************************************** 859#define DMA12_CNT2 0x1001AC // DMA Table Size : Ch#12
860#define DMA10_CNT2 0x1001A4 // DMA Table Size : Ch#10 860
861 861//*****************************************************************************
862//***************************************************************************** 862#define DMA13_CNT2 0x1001B0 // DMA Table Size : Ch#13
863#define DMA11_CNT2 0x1001A8 // DMA Table Size : Ch#11 863
864 864//*****************************************************************************
865//***************************************************************************** 865#define DMA14_CNT2 0x1001B4 // DMA Table Size : Ch#14
866#define DMA12_CNT2 0x1001AC // DMA Table Size : Ch#12 866
867 867//*****************************************************************************
868//***************************************************************************** 868#define DMA15_CNT2 0x1001B8 // DMA Table Size : Ch#15
869#define DMA13_CNT2 0x1001B0 // DMA Table Size : Ch#13 869
870 870//*****************************************************************************
871//***************************************************************************** 871#define DMA16_CNT2 0x1001BC // DMA Table Size : Ch#16
872#define DMA14_CNT2 0x1001B4 // DMA Table Size : Ch#14 872
873 873//*****************************************************************************
874//***************************************************************************** 874#define DMA17_CNT2 0x1001C0 // DMA Table Size : Ch#17
875#define DMA15_CNT2 0x1001B8 // DMA Table Size : Ch#15 875
876 876//*****************************************************************************
877//***************************************************************************** 877#define DMA18_CNT2 0x1001C4 // DMA Table Size : Ch#18
878#define DMA16_CNT2 0x1001BC // DMA Table Size : Ch#16 878
879 879//*****************************************************************************
880//***************************************************************************** 880#define DMA19_CNT2 0x1001C8 // DMA Table Size : Ch#19
881#define DMA17_CNT2 0x1001C0 // DMA Table Size : Ch#17 881
882 882//*****************************************************************************
883//***************************************************************************** 883#define DMA20_CNT2 0x1001CC // DMA Table Size : Ch#20
884#define DMA18_CNT2 0x1001C4 // DMA Table Size : Ch#18 884
885 885//*****************************************************************************
886//***************************************************************************** 886#define DMA21_CNT2 0x1001D0 // DMA Table Size : Ch#21
887#define DMA19_CNT2 0x1001C8 // DMA Table Size : Ch#19 887
888 888//*****************************************************************************
889//***************************************************************************** 889#define DMA22_CNT2 0x1001D4 // DMA Table Size : Ch#22
890#define DMA20_CNT2 0x1001CC // DMA Table Size : Ch#20 890
891 891//*****************************************************************************
892//***************************************************************************** 892#define DMA23_CNT2 0x1001D8 // DMA Table Size : Ch#23
893#define DMA21_CNT2 0x1001D0 // DMA Table Size : Ch#21 893
894 894//*****************************************************************************
895//***************************************************************************** 895#define DMA24_CNT2 0x1001DC // DMA Table Size : Ch#24
896#define DMA22_CNT2 0x1001D4 // DMA Table Size : Ch#22 896
897 897//*****************************************************************************
898//***************************************************************************** 898#define DMA25_CNT2 0x1001E0 // DMA Table Size : Ch#25
899#define DMA23_CNT2 0x1001D8 // DMA Table Size : Ch#23 899
900 900//*****************************************************************************
901//***************************************************************************** 901#define DMA26_CNT2 0x1001E4 // DMA Table Size : Ch#26
902#define DMA24_CNT2 0x1001DC // DMA Table Size : Ch#24 902
903 903//*****************************************************************************
904//***************************************************************************** 904 // ITG
905#define DMA25_CNT2 0x1001E0 // DMA Table Size : Ch#25 905//*****************************************************************************
906 906#define TM_CNT_LDW 0x110000 // Timer : Counter low
907//***************************************************************************** 907
908#define DMA26_CNT2 0x1001E4 // DMA Table Size : Ch#26 908//*****************************************************************************
909 909#define TM_CNT_UW 0x110004 // Timer : Counter high word
910 910
911 911//*****************************************************************************
912//***************************************************************************** 912#define TM_LMT_LDW 0x110008 // Timer : Limit low
913 // ITG 913
914//***************************************************************************** 914//*****************************************************************************
915#define TM_CNT_LDW 0x110000 // Timer : Counter low 915#define TM_LMT_UW 0x11000C // Timer : Limit high word
916 916
917//***************************************************************************** 917//*****************************************************************************
918#define TM_CNT_UW 0x110004 // Timer : Counter high word 918#define GP0_IO 0x110010 // GPIO output enables data I/O
919 919#define FLD_GP_OE 0x00FF0000 // GPIO: GP_OE output enable
920//***************************************************************************** 920#define FLD_GP_IN 0x0000FF00 // GPIO: GP_IN status
921#define TM_LMT_LDW 0x110008 // Timer : Limit low 921#define FLD_GP_OUT 0x000000FF // GPIO: GP_OUT control
922 922
923//***************************************************************************** 923//*****************************************************************************
924#define TM_LMT_UW 0x11000C // Timer : Limit high word 924#define GPIO_ISM 0x110014 // GPIO interrupt sensitivity mode
925 925#define FLD_GP_ISM_SNS 0x00000070
926//***************************************************************************** 926#define FLD_GP_ISM_POL 0x00000007
927#define GP0_IO 0x110010 // GPIO output enables data I/O 927
928#define FLD_GP_OE 0x00FF0000 // GPIO: GP_OE output enable 928//*****************************************************************************
929#define FLD_GP_IN 0x0000FF00 // GPIO: GP_IN status 929#define SOFT_RESET 0x11001C // Output system reset reg
930#define FLD_GP_OUT 0x000000FF // GPIO: GP_OUT control 930#define FLD_PECOS_SOFT_RESET 0x00000001
931 931
932//***************************************************************************** 932//*****************************************************************************
933#define GPIO_ISM 0x110014 // GPIO interrupt sensitivity mode 933#define MC416_RWD 0x110020 // MC416 GPIO[18:3] pin
934#define FLD_GP_ISM_SNS 0x00000070 934#define MC416_OEN 0x110024 // Output enable of GPIO[18:3]
935#define FLD_GP_ISM_POL 0x00000007 935#define MC416_CTL 0x110028
936 936
937//***************************************************************************** 937//*****************************************************************************
938#define SOFT_RESET 0x11001C // Output system reset reg 938#define ALT_PIN_OUT_SEL 0x11002C // Alternate GPIO output select
939#define FLD_PECOS_SOFT_RESET 0x00000001 939
940 940#define FLD_ALT_GPIO_OUT_SEL 0xF0000000
941//***************************************************************************** 941// 0 Disabled <-- default
942#define MC416_RWD 0x110020 // MC416 GPIO[18:3] pin 942// 1 GPIO[0]
943#define MC416_OEN 0x110024 // Output enable of GPIO[18:3] 943// 2 GPIO[10]
944#define MC416_CTL 0x110028 944// 3 VIP_656_DATA_VAL
945 945// 4 VIP_656_DATA[0]
946//***************************************************************************** 946// 5 VIP_656_CLK
947#define ALT_PIN_OUT_SEL 0x11002C // Alternate GPIO output select 947// 6 VIP_656_DATA_EXT[1]
948 948// 7 VIP_656_DATA_EXT[0]
949#define FLD_ALT_GPIO_OUT_SEL 0xF0000000 949// 8 ATT_IF
950// 0 Disabled <-- default 950
951// 1 GPIO[0] 951#define FLD_AUX_PLL_CLK_ALT_SEL 0x0F000000
952// 2 GPIO[10] 952// 0 AUX_PLL_CLK<-- default
953// 3 VIP_656_DATA_VAL 953// 1 GPIO[2]
954// 4 VIP_656_DATA[0] 954// 2 GPIO[10]
955// 5 VIP_656_CLK 955// 3 VIP_656_DATA_VAL
956// 6 VIP_656_DATA_EXT[1] 956// 4 VIP_656_DATA[0]
957// 7 VIP_656_DATA_EXT[0] 957// 5 VIP_656_CLK
958// 8 ATT_IF 958// 6 VIP_656_DATA_EXT[1]
959 959// 7 VIP_656_DATA_EXT[0]
960#define FLD_AUX_PLL_CLK_ALT_SEL 0x0F000000 960
961// 0 AUX_PLL_CLK<-- default 961#define FLD_IR_TX_ALT_SEL 0x00F00000
962// 1 GPIO[2] 962// 0 IR_TX <-- default
963// 2 GPIO[10] 963// 1 GPIO[1]
964// 3 VIP_656_DATA_VAL 964// 2 GPIO[10]
965// 4 VIP_656_DATA[0] 965// 3 VIP_656_DATA_VAL
966// 5 VIP_656_CLK 966// 4 VIP_656_DATA[0]
967// 6 VIP_656_DATA_EXT[1] 967// 5 VIP_656_CLK
968// 7 VIP_656_DATA_EXT[0] 968// 6 VIP_656_DATA_EXT[1]
969 969// 7 VIP_656_DATA_EXT[0]
970#define FLD_IR_TX_ALT_SEL 0x00F00000 970
971// 0 IR_TX <-- default 971#define FLD_IR_RX_ALT_SEL 0x000F0000
972// 1 GPIO[1] 972// 0 IR_RX <-- default
973// 2 GPIO[10] 973// 1 GPIO[0]
974// 3 VIP_656_DATA_VAL 974// 2 GPIO[10]
975// 4 VIP_656_DATA[0] 975// 3 VIP_656_DATA_VAL
976// 5 VIP_656_CLK 976// 4 VIP_656_DATA[0]
977// 6 VIP_656_DATA_EXT[1] 977// 5 VIP_656_CLK
978// 7 VIP_656_DATA_EXT[0] 978// 6 VIP_656_DATA_EXT[1]
979 979// 7 VIP_656_DATA_EXT[0]
980#define FLD_IR_RX_ALT_SEL 0x000F0000 980
981// 0 IR_RX <-- default 981#define FLD_GPIO10_ALT_SEL 0x0000F000
982// 1 GPIO[0] 982// 0 GPIO[10] <-- default
983// 2 GPIO[10] 983// 1 GPIO[0]
984// 3 VIP_656_DATA_VAL 984// 2 GPIO[10]
985// 4 VIP_656_DATA[0] 985// 3 VIP_656_DATA_VAL
986// 5 VIP_656_CLK 986// 4 VIP_656_DATA[0]
987// 6 VIP_656_DATA_EXT[1] 987// 5 VIP_656_CLK
988// 7 VIP_656_DATA_EXT[0] 988// 6 VIP_656_DATA_EXT[1]
989 989// 7 VIP_656_DATA_EXT[0]
990#define FLD_GPIO10_ALT_SEL 0x0000F000 990
991// 0 GPIO[10] <-- default 991#define FLD_GPIO2_ALT_SEL 0x00000F00
992// 1 GPIO[0] 992// 0 GPIO[2] <-- default
993// 2 GPIO[10] 993// 1 GPIO[1]
994// 3 VIP_656_DATA_VAL 994// 2 GPIO[10]
995// 4 VIP_656_DATA[0] 995// 3 VIP_656_DATA_VAL
996// 5 VIP_656_CLK 996// 4 VIP_656_DATA[0]
997// 6 VIP_656_DATA_EXT[1] 997// 5 VIP_656_CLK
998// 7 VIP_656_DATA_EXT[0] 998// 6 VIP_656_DATA_EXT[1]
999 999// 7 VIP_656_DATA_EXT[0]
1000#define FLD_GPIO2_ALT_SEL 0x00000F00 1000
1001// 0 GPIO[2] <-- default 1001#define FLD_GPIO1_ALT_SEL 0x000000F0
1002// 1 GPIO[1] 1002// 0 GPIO[1] <-- default
1003// 2 GPIO[10] 1003// 1 GPIO[0]
1004// 3 VIP_656_DATA_VAL 1004// 2 GPIO[10]
1005// 4 VIP_656_DATA[0] 1005// 3 VIP_656_DATA_VAL
1006// 5 VIP_656_CLK 1006// 4 VIP_656_DATA[0]
1007// 6 VIP_656_DATA_EXT[1] 1007// 5 VIP_656_CLK
1008// 7 VIP_656_DATA_EXT[0] 1008// 6 VIP_656_DATA_EXT[1]
1009 1009// 7 VIP_656_DATA_EXT[0]
1010#define FLD_GPIO1_ALT_SEL 0x000000F0 1010
1011// 0 GPIO[1] <-- default 1011#define FLD_GPIO0_ALT_SEL 0x0000000F
1012// 1 GPIO[0] 1012// 0 GPIO[0] <-- default
1013// 2 GPIO[10] 1013// 1 GPIO[1]
1014// 3 VIP_656_DATA_VAL 1014// 2 GPIO[10]
1015// 4 VIP_656_DATA[0] 1015// 3 VIP_656_DATA_VAL
1016// 5 VIP_656_CLK 1016// 4 VIP_656_DATA[0]
1017// 6 VIP_656_DATA_EXT[1] 1017// 5 VIP_656_CLK
1018// 7 VIP_656_DATA_EXT[0] 1018// 6 VIP_656_DATA_EXT[1]
1019 1019// 7 VIP_656_DATA_EXT[0]
1020#define FLD_GPIO0_ALT_SEL 0x0000000F 1020
1021// 0 GPIO[0] <-- default 1021#define ALT_PIN_IN_SEL 0x110030 // Alternate GPIO input select
1022// 1 GPIO[1] 1022
1023// 2 GPIO[10] 1023#define FLD_GPIO10_ALT_IN_SEL 0x0000F000
1024// 3 VIP_656_DATA_VAL 1024// 0 GPIO[10] <-- default
1025// 4 VIP_656_DATA[0] 1025// 1 IR_RX
1026// 5 VIP_656_CLK 1026// 2 IR_TX
1027// 6 VIP_656_DATA_EXT[1] 1027// 3 AUX_PLL_CLK
1028// 7 VIP_656_DATA_EXT[0] 1028// 4 IF_ATT_SEL
1029 1029// 5 GPIO[0]
1030#define ALT_PIN_IN_SEL 0x110030 // Alternate GPIO input select 1030// 6 GPIO[1]
1031 1031// 7 GPIO[2]
1032#define FLD_GPIO10_ALT_IN_SEL 0x0000F000 1032
1033// 0 GPIO[10] <-- default 1033#define FLD_GPIO2_ALT_IN_SEL 0x00000F00
1034// 1 IR_RX 1034// 0 GPIO[2] <-- default
1035// 2 IR_TX 1035// 1 IR_RX
1036// 3 AUX_PLL_CLK 1036// 2 IR_TX
1037// 4 IF_ATT_SEL 1037// 3 AUX_PLL_CLK
1038// 5 GPIO[0] 1038// 4 IF_ATT_SEL
1039// 6 GPIO[1] 1039
1040// 7 GPIO[2] 1040#define FLD_GPIO1_ALT_IN_SEL 0x000000F0
1041 1041// 0 GPIO[1] <-- default
1042#define FLD_GPIO2_ALT_IN_SEL 0x00000F00 1042// 1 IR_RX
1043// 0 GPIO[2] <-- default 1043// 2 IR_TX
1044// 1 IR_RX 1044// 3 AUX_PLL_CLK
1045// 2 IR_TX 1045// 4 IF_ATT_SEL
1046// 3 AUX_PLL_CLK 1046
1047// 4 IF_ATT_SEL 1047#define FLD_GPIO0_ALT_IN_SEL 0x0000000F
1048 1048// 0 GPIO[0] <-- default
1049#define FLD_GPIO1_ALT_IN_SEL 0x000000F0 1049// 1 IR_RX
1050// 0 GPIO[1] <-- default 1050// 2 IR_TX
1051// 1 IR_RX 1051// 3 AUX_PLL_CLK
1052// 2 IR_TX 1052// 4 IF_ATT_SEL
1053// 3 AUX_PLL_CLK 1053
1054// 4 IF_ATT_SEL 1054//*****************************************************************************
1055 1055#define TEST_BUS_CTL1 0x110040 // Test bus control register #1
1056#define FLD_GPIO0_ALT_IN_SEL 0x0000000F 1056
1057// 0 GPIO[0] <-- default 1057//*****************************************************************************
1058// 1 IR_RX 1058#define TEST_BUS_CTL2 0x110044 // Test bus control register #2
1059// 2 IR_TX 1059
1060// 3 AUX_PLL_CLK 1060//*****************************************************************************
1061// 4 IF_ATT_SEL 1061#define CLK_DELAY 0x110048 // Clock delay
1062 1062#define FLD_MOE_CLK_DIS 0x80000000 // Disable MoE clock
1063//***************************************************************************** 1063
1064#define TEST_BUS_CTL1 0x110040 // Test bus control register #1 1064//*****************************************************************************
1065 1065#define PAD_CTRL 0x110068 // Pad drive strength control
1066//***************************************************************************** 1066
1067#define TEST_BUS_CTL2 0x110044 // Test bus control register #2 1067//*****************************************************************************
1068 1068#define MBIST_CTRL 0x110050 // SRAM memory built-in self test control
1069//***************************************************************************** 1069
1070#define CLK_DELAY 0x110048 // Clock delay 1070//*****************************************************************************
1071#define FLD_MOE_CLK_DIS 0x80000000 // Disable MoE clock 1071#define MBIST_STAT 0x110054 // SRAM memory built-in self test status
1072 1072
1073 1073//*****************************************************************************
1074//***************************************************************************** 1074// PLL registers
1075#define PAD_CTRL 0x110068 // Pad drive strength control 1075//*****************************************************************************
1076 1076#define PLL_A_INT_FRAC 0x110088
1077//***************************************************************************** 1077#define PLL_A_POST_STAT_BIST 0x11008C
1078#define MBIST_CTRL 0x110050 // SRAM memory built-in self test control 1078#define PLL_B_INT_FRAC 0x110090
1079 1079#define PLL_B_POST_STAT_BIST 0x110094
1080//***************************************************************************** 1080#define PLL_C_INT_FRAC 0x110098
1081#define MBIST_STAT 0x110054 // SRAM memory built-in self test status 1081#define PLL_C_POST_STAT_BIST 0x11009C
1082 1082#define PLL_D_INT_FRAC 0x1100A0
1083//***************************************************************************** 1083#define PLL_D_POST_STAT_BIST 0x1100A4
1084// PLL registers 1084
1085//***************************************************************************** 1085#define CLK_RST 0x11002C
1086#define PLL_A_INT_FRAC 0x110088 1086#define FLD_VID_I_CLK_NOE 0x00001000
1087#define PLL_A_POST_STAT_BIST 0x11008C 1087#define FLD_VID_J_CLK_NOE 0x00002000
1088#define PLL_B_INT_FRAC 0x110090 1088#define FLD_USE_ALT_PLL_REF 0x00004000
1089#define PLL_B_POST_STAT_BIST 0x110094 1089
1090#define PLL_C_INT_FRAC 0x110098 1090#define VID_CH_MODE_SEL 0x110078
1091#define PLL_C_POST_STAT_BIST 0x11009C 1091#define VID_CH_CLK_SEL 0x11007C
1092#define PLL_D_INT_FRAC 0x1100A0 1092
1093#define PLL_D_POST_STAT_BIST 0x1100A4 1093//*****************************************************************************
1094 1094#define VBI_A_DMA 0x130008 // VBI A DMA data port
1095#define CLK_RST 0x11002C 1095
1096#define FLD_VID_I_CLK_NOE 0x00001000 1096//*****************************************************************************
1097#define FLD_VID_J_CLK_NOE 0x00002000 1097#define VID_A_VIP_CTL 0x130080 // Video A VIP format control
1098#define FLD_USE_ALT_PLL_REF 0x00004000 1098#define FLD_VIP_MODE 0x00000001
1099 1099
1100#define VID_CH_MODE_SEL 0x110078 1100//*****************************************************************************
1101#define VID_CH_CLK_SEL 0x11007C 1101#define VID_A_PIXEL_FRMT 0x130084 // Video A pixel format
1102 1102#define FLD_VID_A_GAMMA_DIS 0x00000008
1103 1103#define FLD_VID_A_FORMAT 0x00000007
1104//***************************************************************************** 1104#define FLD_VID_A_GAMMA_FACTOR 0x00000010
1105#define VBI_A_DMA 0x130008 // VBI A DMA data port 1105
1106 1106//*****************************************************************************
1107//***************************************************************************** 1107#define VID_A_VBI_CTL 0x130088 // Video A VBI miscellaneous control
1108#define VID_A_VIP_CTL 0x130080 // Video A VIP format control 1108#define FLD_VID_A_VIP_EXT 0x00000003
1109#define FLD_VIP_MODE 0x00000001 1109
1110 1110//*****************************************************************************
1111//***************************************************************************** 1111#define VID_B_DMA 0x130100 // Video B DMA data port
1112#define VID_A_PIXEL_FRMT 0x130084 // Video A pixel format 1112
1113#define FLD_VID_A_GAMMA_DIS 0x00000008 1113//*****************************************************************************
1114#define FLD_VID_A_FORMAT 0x00000007 1114#define VBI_B_DMA 0x130108 // VBI B DMA data port
1115#define FLD_VID_A_GAMMA_FACTOR 0x00000010 1115
1116 1116//*****************************************************************************
1117//***************************************************************************** 1117#define VID_B_SRC_SEL 0x130144 // Video B source select
1118#define VID_A_VBI_CTL 0x130088 // Video A VBI miscellaneous control 1118#define FLD_VID_B_SRC_SEL 0x00000000
1119#define FLD_VID_A_VIP_EXT 0x00000003 1119
1120 1120//*****************************************************************************
1121//***************************************************************************** 1121#define VID_B_LNGTH 0x130150 // Video B line length
1122#define VID_B_DMA 0x130100 // Video B DMA data port 1122#define FLD_VID_B_LN_LNGTH 0x00000FFF
1123 1123
1124//***************************************************************************** 1124//*****************************************************************************
1125#define VBI_B_DMA 0x130108 // VBI B DMA data port 1125#define VID_B_VIP_CTL 0x130180 // Video B VIP format control
1126 1126
1127//***************************************************************************** 1127//*****************************************************************************
1128#define VID_B_SRC_SEL 0x130144 // Video B source select 1128#define VID_B_PIXEL_FRMT 0x130184 // Video B pixel format
1129#define FLD_VID_B_SRC_SEL 0x00000000 1129#define FLD_VID_B_GAMMA_DIS 0x00000008
1130 1130#define FLD_VID_B_FORMAT 0x00000007
1131//***************************************************************************** 1131#define FLD_VID_B_GAMMA_FACTOR 0x00000010
1132#define VID_B_LNGTH 0x130150 // Video B line length 1132
1133#define FLD_VID_B_LN_LNGTH 0x00000FFF 1133//*****************************************************************************
1134 1134#define VID_C_DMA 0x130200 // Video C DMA data port
1135//***************************************************************************** 1135
1136#define VID_B_VIP_CTL 0x130180 // Video B VIP format control 1136//*****************************************************************************
1137 1137#define VID_C_LNGTH 0x130250 // Video C line length
1138//***************************************************************************** 1138#define FLD_VID_C_LN_LNGTH 0x00000FFF
1139#define VID_B_PIXEL_FRMT 0x130184 // Video B pixel format 1139
1140#define FLD_VID_B_GAMMA_DIS 0x00000008 1140//*****************************************************************************
1141#define FLD_VID_B_FORMAT 0x00000007 1141// Video Destination Channels
1142#define FLD_VID_B_GAMMA_FACTOR 0x00000010 1142//*****************************************************************************
1143 1143
1144//***************************************************************************** 1144#define VID_DST_A_GPCNT 0x130020 // Video A general purpose counter
1145#define VID_C_DMA 0x130200 // Video C DMA data port 1145#define VID_DST_B_GPCNT 0x130120 // Video B general purpose counter
1146 1146#define VID_DST_C_GPCNT 0x130220 // Video C general purpose counter
1147//***************************************************************************** 1147#define VID_DST_D_GPCNT 0x130320 // Video D general purpose counter
1148#define VID_C_LNGTH 0x130250 // Video C line length 1148#define VID_DST_E_GPCNT 0x130420 // Video E general purpose counter
1149#define FLD_VID_C_LN_LNGTH 0x00000FFF 1149#define VID_DST_F_GPCNT 0x130520 // Video F general purpose counter
1150 1150#define VID_DST_G_GPCNT 0x130620 // Video G general purpose counter
1151 1151#define VID_DST_H_GPCNT 0x130720 // Video H general purpose counter
1152//***************************************************************************** 1152
1153// Video Destination Channels 1153//*****************************************************************************
1154//***************************************************************************** 1154
1155 1155#define VID_DST_A_GPCNT_CTL 0x130030 // Video A general purpose control
1156#define VID_DST_A_GPCNT 0x130020 // Video A general purpose counter 1156#define VID_DST_B_GPCNT_CTL 0x130130 // Video B general purpose control
1157#define VID_DST_B_GPCNT 0x130120 // Video B general purpose counter 1157#define VID_DST_C_GPCNT_CTL 0x130230 // Video C general purpose control
1158#define VID_DST_C_GPCNT 0x130220 // Video C general purpose counter 1158#define VID_DST_D_GPCNT_CTL 0x130330 // Video D general purpose control
1159#define VID_DST_D_GPCNT 0x130320 // Video D general purpose counter 1159#define VID_DST_E_GPCNT_CTL 0x130430 // Video E general purpose control
1160#define VID_DST_E_GPCNT 0x130420 // Video E general purpose counter 1160#define VID_DST_F_GPCNT_CTL 0x130530 // Video F general purpose control
1161#define VID_DST_F_GPCNT 0x130520 // Video F general purpose counter 1161#define VID_DST_G_GPCNT_CTL 0x130630 // Video G general purpose control
1162#define VID_DST_G_GPCNT 0x130620 // Video G general purpose counter 1162#define VID_DST_H_GPCNT_CTL 0x130730 // Video H general purpose control
1163#define VID_DST_H_GPCNT 0x130720 // Video H general purpose counter 1163
1164 1164//*****************************************************************************
1165//***************************************************************************** 1165
1166 1166#define VID_DST_A_DMA_CTL 0x130040 // Video A DMA control
1167#define VID_DST_A_GPCNT_CTL 0x130030 // Video A general purpose control 1167#define VID_DST_B_DMA_CTL 0x130140 // Video B DMA control
1168#define VID_DST_B_GPCNT_CTL 0x130130 // Video B general purpose control 1168#define VID_DST_C_DMA_CTL 0x130240 // Video C DMA control
1169#define VID_DST_C_GPCNT_CTL 0x130230 // Video C general purpose control 1169#define VID_DST_D_DMA_CTL 0x130340 // Video D DMA control
1170#define VID_DST_D_GPCNT_CTL 0x130330 // Video D general purpose control 1170#define VID_DST_E_DMA_CTL 0x130440 // Video E DMA control
1171#define VID_DST_E_GPCNT_CTL 0x130430 // Video E general purpose control 1171#define VID_DST_F_DMA_CTL 0x130540 // Video F DMA control
1172#define VID_DST_F_GPCNT_CTL 0x130530 // Video F general purpose control 1172#define VID_DST_G_DMA_CTL 0x130640 // Video G DMA control
1173#define VID_DST_G_GPCNT_CTL 0x130630 // Video G general purpose control 1173#define VID_DST_H_DMA_CTL 0x130740 // Video H DMA control
1174#define VID_DST_H_GPCNT_CTL 0x130730 // Video H general purpose control 1174
1175 1175#define FLD_VID_RISC_EN 0x00000010
1176 1176#define FLD_VID_FIFO_EN 0x00000001
1177//***************************************************************************** 1177
1178 1178//*****************************************************************************
1179#define VID_DST_A_DMA_CTL 0x130040 // Video A DMA control 1179
1180#define VID_DST_B_DMA_CTL 0x130140 // Video B DMA control 1180#define VID_DST_A_VIP_CTL 0x130080 // Video A VIP control
1181#define VID_DST_C_DMA_CTL 0x130240 // Video C DMA control 1181#define VID_DST_B_VIP_CTL 0x130180 // Video B VIP control
1182#define VID_DST_D_DMA_CTL 0x130340 // Video D DMA control 1182#define VID_DST_C_VIP_CTL 0x130280 // Video C VIP control
1183#define VID_DST_E_DMA_CTL 0x130440 // Video E DMA control 1183#define VID_DST_D_VIP_CTL 0x130380 // Video D VIP control
1184#define VID_DST_F_DMA_CTL 0x130540 // Video F DMA control 1184#define VID_DST_E_VIP_CTL 0x130480 // Video E VIP control
1185#define VID_DST_G_DMA_CTL 0x130640 // Video G DMA control 1185#define VID_DST_F_VIP_CTL 0x130580 // Video F VIP control
1186#define VID_DST_H_DMA_CTL 0x130740 // Video H DMA control 1186#define VID_DST_G_VIP_CTL 0x130680 // Video G VIP control
1187 1187#define VID_DST_H_VIP_CTL 0x130780 // Video H VIP control
1188#define FLD_VID_RISC_EN 0x00000010 1188
1189#define FLD_VID_FIFO_EN 0x00000001 1189//*****************************************************************************
1190 1190
1191//***************************************************************************** 1191#define VID_DST_A_PIX_FRMT 0x130084 // Video A Pixel format
1192 1192#define VID_DST_B_PIX_FRMT 0x130184 // Video B Pixel format
1193#define VID_DST_A_VIP_CTL 0x130080 // Video A VIP control 1193#define VID_DST_C_PIX_FRMT 0x130284 // Video C Pixel format
1194#define VID_DST_B_VIP_CTL 0x130180 // Video B VIP control 1194#define VID_DST_D_PIX_FRMT 0x130384 // Video D Pixel format
1195#define VID_DST_C_VIP_CTL 0x130280 // Video C VIP control 1195#define VID_DST_E_PIX_FRMT 0x130484 // Video E Pixel format
1196#define VID_DST_D_VIP_CTL 0x130380 // Video D VIP control 1196#define VID_DST_F_PIX_FRMT 0x130584 // Video F Pixel format
1197#define VID_DST_E_VIP_CTL 0x130480 // Video E VIP control 1197#define VID_DST_G_PIX_FRMT 0x130684 // Video G Pixel format
1198#define VID_DST_F_VIP_CTL 0x130580 // Video F VIP control 1198#define VID_DST_H_PIX_FRMT 0x130784 // Video H Pixel format
1199#define VID_DST_G_VIP_CTL 0x130680 // Video G VIP control 1199
1200#define VID_DST_H_VIP_CTL 0x130780 // Video H VIP control 1200//*****************************************************************************
1201 1201// Video Source Channels
1202//***************************************************************************** 1202//*****************************************************************************
1203 1203
1204#define VID_DST_A_PIX_FRMT 0x130084 // Video A Pixel format 1204#define VID_SRC_A_GPCNT_CTL 0x130804 // Video A general purpose control
1205#define VID_DST_B_PIX_FRMT 0x130184 // Video B Pixel format 1205#define VID_SRC_B_GPCNT_CTL 0x130904 // Video B general purpose control
1206#define VID_DST_C_PIX_FRMT 0x130284 // Video C Pixel format 1206#define VID_SRC_C_GPCNT_CTL 0x130A04 // Video C general purpose control
1207#define VID_DST_D_PIX_FRMT 0x130384 // Video D Pixel format 1207#define VID_SRC_D_GPCNT_CTL 0x130B04 // Video D general purpose control
1208#define VID_DST_E_PIX_FRMT 0x130484 // Video E Pixel format 1208#define VID_SRC_E_GPCNT_CTL 0x130C04 // Video E general purpose control
1209#define VID_DST_F_PIX_FRMT 0x130584 // Video F Pixel format 1209#define VID_SRC_F_GPCNT_CTL 0x130D04 // Video F general purpose control
1210#define VID_DST_G_PIX_FRMT 0x130684 // Video G Pixel format 1210#define VID_SRC_I_GPCNT_CTL 0x130E04 // Video I general purpose control
1211#define VID_DST_H_PIX_FRMT 0x130784 // Video H Pixel format 1211#define VID_SRC_J_GPCNT_CTL 0x130F04 // Video J general purpose control
1212 1212
1213//***************************************************************************** 1213//*****************************************************************************
1214// Video Source Channels 1214
1215//***************************************************************************** 1215#define VID_SRC_A_GPCNT 0x130808 // Video A general purpose counter
1216 1216#define VID_SRC_B_GPCNT 0x130908 // Video B general purpose counter
1217#define VID_SRC_A_GPCNT_CTL 0x130804 // Video A general purpose control 1217#define VID_SRC_C_GPCNT 0x130A08 // Video C general purpose counter
1218#define VID_SRC_B_GPCNT_CTL 0x130904 // Video B general purpose control 1218#define VID_SRC_D_GPCNT 0x130B08 // Video D general purpose counter
1219#define VID_SRC_C_GPCNT_CTL 0x130A04 // Video C general purpose control 1219#define VID_SRC_E_GPCNT 0x130C08 // Video E general purpose counter
1220#define VID_SRC_D_GPCNT_CTL 0x130B04 // Video D general purpose control 1220#define VID_SRC_F_GPCNT 0x130D08 // Video F general purpose counter
1221#define VID_SRC_E_GPCNT_CTL 0x130C04 // Video E general purpose control 1221#define VID_SRC_I_GPCNT 0x130E08 // Video I general purpose counter
1222#define VID_SRC_F_GPCNT_CTL 0x130D04 // Video F general purpose control 1222#define VID_SRC_J_GPCNT 0x130F08 // Video J general purpose counter
1223#define VID_SRC_I_GPCNT_CTL 0x130E04 // Video I general purpose control 1223
1224#define VID_SRC_J_GPCNT_CTL 0x130F04 // Video J general purpose control 1224//*****************************************************************************
1225 1225
1226//***************************************************************************** 1226#define VID_SRC_A_DMA_CTL 0x13080C // Video A DMA control
1227 1227#define VID_SRC_B_DMA_CTL 0x13090C // Video B DMA control
1228#define VID_SRC_A_GPCNT 0x130808 // Video A general purpose counter 1228#define VID_SRC_C_DMA_CTL 0x130A0C // Video C DMA control
1229#define VID_SRC_B_GPCNT 0x130908 // Video B general purpose counter 1229#define VID_SRC_D_DMA_CTL 0x130B0C // Video D DMA control
1230#define VID_SRC_C_GPCNT 0x130A08 // Video C general purpose counter 1230#define VID_SRC_E_DMA_CTL 0x130C0C // Video E DMA control
1231#define VID_SRC_D_GPCNT 0x130B08 // Video D general purpose counter 1231#define VID_SRC_F_DMA_CTL 0x130D0C // Video F DMA control
1232#define VID_SRC_E_GPCNT 0x130C08 // Video E general purpose counter 1232#define VID_SRC_I_DMA_CTL 0x130E0C // Video I DMA control
1233#define VID_SRC_F_GPCNT 0x130D08 // Video F general purpose counter 1233#define VID_SRC_J_DMA_CTL 0x130F0C // Video J DMA control
1234#define VID_SRC_I_GPCNT 0x130E08 // Video I general purpose counter 1234
1235#define VID_SRC_J_GPCNT 0x130F08 // Video J general purpose counter 1235#define FLD_APB_RISC_EN 0x00000010
1236 1236#define FLD_APB_FIFO_EN 0x00000001
1237//***************************************************************************** 1237
1238 1238//*****************************************************************************
1239#define VID_SRC_A_DMA_CTL 0x13080C // Video A DMA control 1239
1240#define VID_SRC_B_DMA_CTL 0x13090C // Video B DMA control 1240#define VID_SRC_A_FMT_CTL 0x130810 // Video A format control
1241#define VID_SRC_C_DMA_CTL 0x130A0C // Video C DMA control 1241#define VID_SRC_B_FMT_CTL 0x130910 // Video B format control
1242#define VID_SRC_D_DMA_CTL 0x130B0C // Video D DMA control 1242#define VID_SRC_C_FMT_CTL 0x130A10 // Video C format control
1243#define VID_SRC_E_DMA_CTL 0x130C0C // Video E DMA control 1243#define VID_SRC_D_FMT_CTL 0x130B10 // Video D format control
1244#define VID_SRC_F_DMA_CTL 0x130D0C // Video F DMA control 1244#define VID_SRC_E_FMT_CTL 0x130C10 // Video E format control
1245#define VID_SRC_I_DMA_CTL 0x130E0C // Video I DMA control 1245#define VID_SRC_F_FMT_CTL 0x130D10 // Video F format control
1246#define VID_SRC_J_DMA_CTL 0x130F0C // Video J DMA control 1246#define VID_SRC_I_FMT_CTL 0x130E10 // Video I format control
1247 1247#define VID_SRC_J_FMT_CTL 0x130F10 // Video J format control
1248#define FLD_APB_RISC_EN 0x00000010 1248
1249#define FLD_APB_FIFO_EN 0x00000001 1249//*****************************************************************************
1250 1250
1251//***************************************************************************** 1251#define VID_SRC_A_ACTIVE_CTL1 0x130814 // Video A active control 1
1252 1252#define VID_SRC_B_ACTIVE_CTL1 0x130914 // Video B active control 1
1253#define VID_SRC_A_FMT_CTL 0x130810 // Video A format control 1253#define VID_SRC_C_ACTIVE_CTL1 0x130A14 // Video C active control 1
1254#define VID_SRC_B_FMT_CTL 0x130910 // Video B format control 1254#define VID_SRC_D_ACTIVE_CTL1 0x130B14 // Video D active control 1
1255#define VID_SRC_C_FMT_CTL 0x130A10 // Video C format control 1255#define VID_SRC_E_ACTIVE_CTL1 0x130C14 // Video E active control 1
1256#define VID_SRC_D_FMT_CTL 0x130B10 // Video D format control 1256#define VID_SRC_F_ACTIVE_CTL1 0x130D14 // Video F active control 1
1257#define VID_SRC_E_FMT_CTL 0x130C10 // Video E format control 1257#define VID_SRC_I_ACTIVE_CTL1 0x130E14 // Video I active control 1
1258#define VID_SRC_F_FMT_CTL 0x130D10 // Video F format control 1258#define VID_SRC_J_ACTIVE_CTL1 0x130F14 // Video J active control 1
1259#define VID_SRC_I_FMT_CTL 0x130E10 // Video I format control 1259
1260#define VID_SRC_J_FMT_CTL 0x130F10 // Video J format control 1260//*****************************************************************************
1261 1261
1262//***************************************************************************** 1262#define VID_SRC_A_ACTIVE_CTL2 0x130818 // Video A active control 2
1263 1263#define VID_SRC_B_ACTIVE_CTL2 0x130918 // Video B active control 2
1264#define VID_SRC_A_ACTIVE_CTL1 0x130814 // Video A active control 1 1264#define VID_SRC_C_ACTIVE_CTL2 0x130A18 // Video C active control 2
1265#define VID_SRC_B_ACTIVE_CTL1 0x130914 // Video B active control 1 1265#define VID_SRC_D_ACTIVE_CTL2 0x130B18 // Video D active control 2
1266#define VID_SRC_C_ACTIVE_CTL1 0x130A14 // Video C active control 1 1266#define VID_SRC_E_ACTIVE_CTL2 0x130C18 // Video E active control 2
1267#define VID_SRC_D_ACTIVE_CTL1 0x130B14 // Video D active control 1 1267#define VID_SRC_F_ACTIVE_CTL2 0x130D18 // Video F active control 2
1268#define VID_SRC_E_ACTIVE_CTL1 0x130C14 // Video E active control 1 1268#define VID_SRC_I_ACTIVE_CTL2 0x130E18 // Video I active control 2
1269#define VID_SRC_F_ACTIVE_CTL1 0x130D14 // Video F active control 1 1269#define VID_SRC_J_ACTIVE_CTL2 0x130F18 // Video J active control 2
1270#define VID_SRC_I_ACTIVE_CTL1 0x130E14 // Video I active control 1 1270
1271#define VID_SRC_J_ACTIVE_CTL1 0x130F14 // Video J active control 1 1271//*****************************************************************************
1272 1272
1273//***************************************************************************** 1273#define VID_SRC_A_CDT_SZ 0x13081C // Video A CDT size
1274 1274#define VID_SRC_B_CDT_SZ 0x13091C // Video B CDT size
1275#define VID_SRC_A_ACTIVE_CTL2 0x130818 // Video A active control 2 1275#define VID_SRC_C_CDT_SZ 0x130A1C // Video C CDT size
1276#define VID_SRC_B_ACTIVE_CTL2 0x130918 // Video B active control 2 1276#define VID_SRC_D_CDT_SZ 0x130B1C // Video D CDT size
1277#define VID_SRC_C_ACTIVE_CTL2 0x130A18 // Video C active control 2 1277#define VID_SRC_E_CDT_SZ 0x130C1C // Video E CDT size
1278#define VID_SRC_D_ACTIVE_CTL2 0x130B18 // Video D active control 2 1278#define VID_SRC_F_CDT_SZ 0x130D1C // Video F CDT size
1279#define VID_SRC_E_ACTIVE_CTL2 0x130C18 // Video E active control 2 1279#define VID_SRC_I_CDT_SZ 0x130E1C // Video I CDT size
1280#define VID_SRC_F_ACTIVE_CTL2 0x130D18 // Video F active control 2 1280#define VID_SRC_J_CDT_SZ 0x130F1C // Video J CDT size
1281#define VID_SRC_I_ACTIVE_CTL2 0x130E18 // Video I active control 2 1281
1282#define VID_SRC_J_ACTIVE_CTL2 0x130F18 // Video J active control 2 1282//*****************************************************************************
1283 1283// Audio I/F
1284//***************************************************************************** 1284//*****************************************************************************
1285 1285#define AUD_DST_A_DMA 0x140000 // Audio Int A DMA data port
1286#define VID_SRC_A_CDT_SZ 0x13081C // Video A CDT size 1286#define AUD_SRC_A_DMA 0x140008 // Audio Int A DMA data port
1287#define VID_SRC_B_CDT_SZ 0x13091C // Video B CDT size 1287
1288#define VID_SRC_C_CDT_SZ 0x130A1C // Video C CDT size 1288#define AUD_A_GPCNT 0x140010 // Audio Int A gp counter
1289#define VID_SRC_D_CDT_SZ 0x130B1C // Video D CDT size 1289#define FLD_AUD_A_GP_CNT 0x0000FFFF
1290#define VID_SRC_E_CDT_SZ 0x130C1C // Video E CDT size 1290
1291#define VID_SRC_F_CDT_SZ 0x130D1C // Video F CDT size 1291#define AUD_A_GPCNT_CTL 0x140014 // Audio Int A gp control
1292#define VID_SRC_I_CDT_SZ 0x130E1C // Video I CDT size 1292
1293#define VID_SRC_J_CDT_SZ 0x130F1C // Video J CDT size 1293#define AUD_A_LNGTH 0x140018 // Audio Int A line length
1294 1294
1295//***************************************************************************** 1295#define AUD_A_CFG 0x14001C // Audio Int A configuration
1296// Audio I/F 1296
1297//***************************************************************************** 1297//*****************************************************************************
1298#define AUD_DST_A_DMA 0x140000 // Audio Int A DMA data port 1298#define AUD_DST_B_DMA 0x140100 // Audio Int B DMA data port
1299#define AUD_SRC_A_DMA 0x140008 // Audio Int A DMA data port 1299#define AUD_SRC_B_DMA 0x140108 // Audio Int B DMA data port
1300 1300
1301#define AUD_A_GPCNT 0x140010 // Audio Int A gp counter 1301#define AUD_B_GPCNT 0x140110 // Audio Int B gp counter
1302#define FLD_AUD_A_GP_CNT 0x0000FFFF 1302#define FLD_AUD_B_GP_CNT 0x0000FFFF
1303 1303
1304#define AUD_A_GPCNT_CTL 0x140014 // Audio Int A gp control 1304#define AUD_B_GPCNT_CTL 0x140114 // Audio Int B gp control
1305 1305
1306#define AUD_A_LNGTH 0x140018 // Audio Int A line length 1306#define AUD_B_LNGTH 0x140118 // Audio Int B line length
1307 1307
1308#define AUD_A_CFG 0x14001C // Audio Int A configuration 1308#define AUD_B_CFG 0x14011C // Audio Int B configuration
1309 1309
1310//***************************************************************************** 1310//*****************************************************************************
1311#define AUD_DST_B_DMA 0x140100 // Audio Int B DMA data port 1311#define AUD_DST_C_DMA 0x140200 // Audio Int C DMA data port
1312#define AUD_SRC_B_DMA 0x140108 // Audio Int B DMA data port 1312#define AUD_SRC_C_DMA 0x140208 // Audio Int C DMA data port
1313 1313
1314#define AUD_B_GPCNT 0x140110 // Audio Int B gp counter 1314#define AUD_C_GPCNT 0x140210 // Audio Int C gp counter
1315#define FLD_AUD_B_GP_CNT 0x0000FFFF 1315#define FLD_AUD_C_GP_CNT 0x0000FFFF
1316 1316
1317#define AUD_B_GPCNT_CTL 0x140114 // Audio Int B gp control 1317#define AUD_C_GPCNT_CTL 0x140214 // Audio Int C gp control
1318 1318
1319#define AUD_B_LNGTH 0x140118 // Audio Int B line length 1319#define AUD_C_LNGTH 0x140218 // Audio Int C line length
1320 1320
1321#define AUD_B_CFG 0x14011C // Audio Int B configuration 1321#define AUD_C_CFG 0x14021C // Audio Int C configuration
1322 1322
1323//***************************************************************************** 1323//*****************************************************************************
1324#define AUD_DST_C_DMA 0x140200 // Audio Int C DMA data port 1324#define AUD_DST_D_DMA 0x140300 // Audio Int D DMA data port
1325#define AUD_SRC_C_DMA 0x140208 // Audio Int C DMA data port 1325#define AUD_SRC_D_DMA 0x140308 // Audio Int D DMA data port
1326 1326
1327#define AUD_C_GPCNT 0x140210 // Audio Int C gp counter 1327#define AUD_D_GPCNT 0x140310 // Audio Int D gp counter
1328#define FLD_AUD_C_GP_CNT 0x0000FFFF 1328#define FLD_AUD_D_GP_CNT 0x0000FFFF
1329 1329
1330#define AUD_C_GPCNT_CTL 0x140214 // Audio Int C gp control 1330#define AUD_D_GPCNT_CTL 0x140314 // Audio Int D gp control
1331 1331
1332#define AUD_C_LNGTH 0x140218 // Audio Int C line length 1332#define AUD_D_LNGTH 0x140318 // Audio Int D line length
1333 1333
1334#define AUD_C_CFG 0x14021C // Audio Int C configuration 1334#define AUD_D_CFG 0x14031C // Audio Int D configuration
1335 1335
1336//***************************************************************************** 1336//*****************************************************************************
1337#define AUD_DST_D_DMA 0x140300 // Audio Int D DMA data port 1337#define AUD_SRC_E_DMA 0x140400 // Audio Int E DMA data port
1338#define AUD_SRC_D_DMA 0x140308 // Audio Int D DMA data port 1338
1339 1339#define AUD_E_GPCNT 0x140410 // Audio Int E gp counter
1340#define AUD_D_GPCNT 0x140310 // Audio Int D gp counter 1340#define FLD_AUD_E_GP_CNT 0x0000FFFF
1341#define FLD_AUD_D_GP_CNT 0x0000FFFF 1341
1342 1342#define AUD_E_GPCNT_CTL 0x140414 // Audio Int E gp control
1343#define AUD_D_GPCNT_CTL 0x140314 // Audio Int D gp control 1343
1344 1344#define AUD_E_CFG 0x14041C // Audio Int E configuration
1345#define AUD_D_LNGTH 0x140318 // Audio Int D line length 1345
1346 1346//*****************************************************************************
1347#define AUD_D_CFG 0x14031C // Audio Int D configuration 1347
1348 1348#define FLD_AUD_DST_LN_LNGTH 0x00000FFF
1349//***************************************************************************** 1349
1350#define AUD_SRC_E_DMA 0x140400 // Audio Int E DMA data port 1350#define FLD_AUD_DST_PK_MODE 0x00004000
1351 1351
1352#define AUD_E_GPCNT 0x140410 // Audio Int E gp counter 1352#define FLD_AUD_CLK_ENABLE 0x00000200
1353#define FLD_AUD_E_GP_CNT 0x0000FFFF 1353
1354 1354#define FLD_AUD_MASTER_MODE 0x00000002
1355#define AUD_E_GPCNT_CTL 0x140414 // Audio Int E gp control 1355
1356 1356#define FLD_AUD_SONY_MODE 0x00000001
1357#define AUD_E_CFG 0x14041C // Audio Int E configuration 1357
1358 1358#define FLD_AUD_CLK_SELECT_PLL_D 0x00001800
1359//***************************************************************************** 1359
1360 1360#define FLD_AUD_DST_ENABLE 0x00020000
1361#define FLD_AUD_DST_LN_LNGTH 0x00000FFF 1361
1362 1362#define FLD_AUD_SRC_ENABLE 0x00010000
1363#define FLD_AUD_DST_PK_MODE 0x00004000 1363
1364 1364//*****************************************************************************
1365#define FLD_AUD_CLK_ENABLE 0x00000200 1365#define AUD_INT_DMA_CTL 0x140500 // Audio Int DMA control
1366 1366
1367#define FLD_AUD_MASTER_MODE 0x00000002 1367#define FLD_AUD_SRC_E_RISC_EN 0x00008000
1368 1368#define FLD_AUD_SRC_C_RISC_EN 0x00004000
1369#define FLD_AUD_SONY_MODE 0x00000001 1369#define FLD_AUD_SRC_B_RISC_EN 0x00002000
1370 1370#define FLD_AUD_SRC_A_RISC_EN 0x00001000
1371#define FLD_AUD_CLK_SELECT_PLL_D 0x00001800 1371
1372 1372#define FLD_AUD_DST_D_RISC_EN 0x00000800
1373#define FLD_AUD_DST_ENABLE 0x00020000 1373#define FLD_AUD_DST_C_RISC_EN 0x00000400
1374 1374#define FLD_AUD_DST_B_RISC_EN 0x00000200
1375#define FLD_AUD_SRC_ENABLE 0x00010000 1375#define FLD_AUD_DST_A_RISC_EN 0x00000100
1376 1376
1377//***************************************************************************** 1377#define FLD_AUD_SRC_E_FIFO_EN 0x00000080
1378#define AUD_INT_DMA_CTL 0x140500 // Audio Int DMA control 1378#define FLD_AUD_SRC_C_FIFO_EN 0x00000040
1379 1379#define FLD_AUD_SRC_B_FIFO_EN 0x00000020
1380#define FLD_AUD_SRC_E_RISC_EN 0x00008000 1380#define FLD_AUD_SRC_A_FIFO_EN 0x00000010
1381#define FLD_AUD_SRC_C_RISC_EN 0x00004000 1381
1382#define FLD_AUD_SRC_B_RISC_EN 0x00002000 1382#define FLD_AUD_DST_D_FIFO_EN 0x00000008
1383#define FLD_AUD_SRC_A_RISC_EN 0x00001000 1383#define FLD_AUD_DST_C_FIFO_EN 0x00000004
1384 1384#define FLD_AUD_DST_B_FIFO_EN 0x00000002
1385#define FLD_AUD_DST_D_RISC_EN 0x00000800 1385#define FLD_AUD_DST_A_FIFO_EN 0x00000001
1386#define FLD_AUD_DST_C_RISC_EN 0x00000400 1386
1387#define FLD_AUD_DST_B_RISC_EN 0x00000200 1387//*****************************************************************************
1388#define FLD_AUD_DST_A_RISC_EN 0x00000100 1388//
1389 1389// Mobilygen Interface Registers
1390#define FLD_AUD_SRC_E_FIFO_EN 0x00000080 1390//
1391#define FLD_AUD_SRC_C_FIFO_EN 0x00000040 1391//*****************************************************************************
1392#define FLD_AUD_SRC_B_FIFO_EN 0x00000020 1392// Mobilygen Interface A
1393#define FLD_AUD_SRC_A_FIFO_EN 0x00000010 1393//*****************************************************************************
1394 1394#define MB_IF_A_DMA 0x150000 // MBIF A DMA data port
1395#define FLD_AUD_DST_D_FIFO_EN 0x00000008 1395#define MB_IF_A_GPCN 0x150008 // MBIF A GP counter
1396#define FLD_AUD_DST_C_FIFO_EN 0x00000004 1396#define MB_IF_A_GPCN_CTRL 0x15000C
1397#define FLD_AUD_DST_B_FIFO_EN 0x00000002 1397#define MB_IF_A_DMA_CTRL 0x150010
1398#define FLD_AUD_DST_A_FIFO_EN 0x00000001 1398#define MB_IF_A_LENGTH 0x150014
1399 1399#define MB_IF_A_HDMA_XFER_SZ 0x150018
1400 1400#define MB_IF_A_HCMD 0x15001C
1401//***************************************************************************** 1401#define MB_IF_A_HCONFIG 0x150020
1402// 1402#define MB_IF_A_DATA_STRUCT_0 0x150024
1403// Mobilygen Interface Registers 1403#define MB_IF_A_DATA_STRUCT_1 0x150028
1404// 1404#define MB_IF_A_DATA_STRUCT_2 0x15002C
1405//***************************************************************************** 1405#define MB_IF_A_DATA_STRUCT_3 0x150030
1406// Mobilygen Interface A 1406#define MB_IF_A_DATA_STRUCT_4 0x150034
1407//***************************************************************************** 1407#define MB_IF_A_DATA_STRUCT_5 0x150038
1408#define MB_IF_A_DMA 0x150000 // MBIF A DMA data port 1408#define MB_IF_A_DATA_STRUCT_6 0x15003C
1409#define MB_IF_A_GPCN 0x150008 // MBIF A GP counter 1409#define MB_IF_A_DATA_STRUCT_7 0x150040
1410#define MB_IF_A_GPCN_CTRL 0x15000C 1410#define MB_IF_A_DATA_STRUCT_8 0x150044
1411#define MB_IF_A_DMA_CTRL 0x150010 1411#define MB_IF_A_DATA_STRUCT_9 0x150048
1412#define MB_IF_A_LENGTH 0x150014 1412#define MB_IF_A_DATA_STRUCT_A 0x15004C
1413#define MB_IF_A_HDMA_XFER_SZ 0x150018 1413#define MB_IF_A_DATA_STRUCT_B 0x150050
1414#define MB_IF_A_HCMD 0x15001C 1414#define MB_IF_A_DATA_STRUCT_C 0x150054
1415#define MB_IF_A_HCONFIG 0x150020 1415#define MB_IF_A_DATA_STRUCT_D 0x150058
1416#define MB_IF_A_DATA_STRUCT_0 0x150024 1416#define MB_IF_A_DATA_STRUCT_E 0x15005C
1417#define MB_IF_A_DATA_STRUCT_1 0x150028 1417#define MB_IF_A_DATA_STRUCT_F 0x150060
1418#define MB_IF_A_DATA_STRUCT_2 0x15002C 1418//*****************************************************************************
1419#define MB_IF_A_DATA_STRUCT_3 0x150030 1419// Mobilygen Interface B
1420#define MB_IF_A_DATA_STRUCT_4 0x150034 1420//*****************************************************************************
1421#define MB_IF_A_DATA_STRUCT_5 0x150038 1421#define MB_IF_B_DMA 0x160000 // MBIF A DMA data port
1422#define MB_IF_A_DATA_STRUCT_6 0x15003C 1422#define MB_IF_B_GPCN 0x160008 // MBIF A GP counter
1423#define MB_IF_A_DATA_STRUCT_7 0x150040 1423#define MB_IF_B_GPCN_CTRL 0x16000C
1424#define MB_IF_A_DATA_STRUCT_8 0x150044 1424#define MB_IF_B_DMA_CTRL 0x160010
1425#define MB_IF_A_DATA_STRUCT_9 0x150048 1425#define MB_IF_B_LENGTH 0x160014
1426#define MB_IF_A_DATA_STRUCT_A 0x15004C 1426#define MB_IF_B_HDMA_XFER_SZ 0x160018
1427#define MB_IF_A_DATA_STRUCT_B 0x150050 1427#define MB_IF_B_HCMD 0x16001C
1428#define MB_IF_A_DATA_STRUCT_C 0x150054 1428#define MB_IF_B_HCONFIG 0x160020
1429#define MB_IF_A_DATA_STRUCT_D 0x150058 1429#define MB_IF_B_DATA_STRUCT_0 0x160024
1430#define MB_IF_A_DATA_STRUCT_E 0x15005C 1430#define MB_IF_B_DATA_STRUCT_1 0x160028
1431#define MB_IF_A_DATA_STRUCT_F 0x150060 1431#define MB_IF_B_DATA_STRUCT_2 0x16002C
1432//***************************************************************************** 1432#define MB_IF_B_DATA_STRUCT_3 0x160030
1433// Mobilygen Interface B 1433#define MB_IF_B_DATA_STRUCT_4 0x160034
1434//***************************************************************************** 1434#define MB_IF_B_DATA_STRUCT_5 0x160038
1435#define MB_IF_B_DMA 0x160000 // MBIF A DMA data port 1435#define MB_IF_B_DATA_STRUCT_6 0x16003C
1436#define MB_IF_B_GPCN 0x160008 // MBIF A GP counter 1436#define MB_IF_B_DATA_STRUCT_7 0x160040
1437#define MB_IF_B_GPCN_CTRL 0x16000C 1437#define MB_IF_B_DATA_STRUCT_8 0x160044
1438#define MB_IF_B_DMA_CTRL 0x160010 1438#define MB_IF_B_DATA_STRUCT_9 0x160048
1439#define MB_IF_B_LENGTH 0x160014 1439#define MB_IF_B_DATA_STRUCT_A 0x16004C
1440#define MB_IF_B_HDMA_XFER_SZ 0x160018 1440#define MB_IF_B_DATA_STRUCT_B 0x160050
1441#define MB_IF_B_HCMD 0x16001C 1441#define MB_IF_B_DATA_STRUCT_C 0x160054
1442#define MB_IF_B_HCONFIG 0x160020 1442#define MB_IF_B_DATA_STRUCT_D 0x160058
1443#define MB_IF_B_DATA_STRUCT_0 0x160024 1443#define MB_IF_B_DATA_STRUCT_E 0x16005C
1444#define MB_IF_B_DATA_STRUCT_1 0x160028 1444#define MB_IF_B_DATA_STRUCT_F 0x160060
1445#define MB_IF_B_DATA_STRUCT_2 0x16002C 1445
1446#define MB_IF_B_DATA_STRUCT_3 0x160030 1446// MB_DMA_CTRL
1447#define MB_IF_B_DATA_STRUCT_4 0x160034 1447#define FLD_MB_IF_RISC_EN 0x00000010
1448#define MB_IF_B_DATA_STRUCT_5 0x160038 1448#define FLD_MB_IF_FIFO_EN 0x00000001
1449#define MB_IF_B_DATA_STRUCT_6 0x16003C 1449
1450#define MB_IF_B_DATA_STRUCT_7 0x160040 1450// MB_LENGTH
1451#define MB_IF_B_DATA_STRUCT_8 0x160044 1451#define FLD_MB_IF_LN_LNGTH 0x00000FFF
1452#define MB_IF_B_DATA_STRUCT_9 0x160048 1452
1453#define MB_IF_B_DATA_STRUCT_A 0x16004C 1453// MB_HCMD register
1454#define MB_IF_B_DATA_STRUCT_B 0x160050 1454#define FLD_MB_HCMD_H_GO 0x80000000
1455#define MB_IF_B_DATA_STRUCT_C 0x160054 1455#define FLD_MB_HCMD_H_BUSY 0x40000000
1456#define MB_IF_B_DATA_STRUCT_D 0x160058 1456#define FLD_MB_HCMD_H_DMA_HOLD 0x10000000
1457#define MB_IF_B_DATA_STRUCT_E 0x16005C 1457#define FLD_MB_HCMD_H_DMA_BUSY 0x08000000
1458#define MB_IF_B_DATA_STRUCT_F 0x160060 1458#define FLD_MB_HCMD_H_DMA_TYPE 0x04000000
1459 1459#define FLD_MB_HCMD_H_DMA_XACT 0x02000000
1460// MB_DMA_CTRL 1460#define FLD_MB_HCMD_H_RW_N 0x01000000
1461#define FLD_MB_IF_RISC_EN 0x00000010 1461#define FLD_MB_HCMD_H_ADDR 0x00FF0000
1462#define FLD_MB_IF_FIFO_EN 0x00000001 1462#define FLD_MB_HCMD_H_DATA 0x0000FFFF
1463 1463
1464// MB_LENGTH 1464//*****************************************************************************
1465#define FLD_MB_IF_LN_LNGTH 0x00000FFF 1465// I2C #1
1466 1466//*****************************************************************************
1467// MB_HCMD register 1467#define I2C1_ADDR 0x180000 // I2C #1 address
1468#define FLD_MB_HCMD_H_GO 0x80000000 1468#define FLD_I2C_DADDR 0xfe000000 // RW [31:25] I2C Device Address
1469#define FLD_MB_HCMD_H_BUSY 0x40000000 1469 // RO [24] reserved
1470#define FLD_MB_HCMD_H_DMA_HOLD 0x10000000 1470//*****************************************************************************
1471#define FLD_MB_HCMD_H_DMA_BUSY 0x08000000 1471#define FLD_I2C_SADDR 0x00FFFFFF // RW [23:0] I2C Sub-address
1472#define FLD_MB_HCMD_H_DMA_TYPE 0x04000000 1472
1473#define FLD_MB_HCMD_H_DMA_XACT 0x02000000 1473//*****************************************************************************
1474#define FLD_MB_HCMD_H_RW_N 0x01000000 1474#define I2C1_WDATA 0x180004 // I2C #1 write data
1475#define FLD_MB_HCMD_H_ADDR 0x00FF0000 1475#define FLD_I2C_WDATA 0xFFFFFFFF // RW [31:0]
1476#define FLD_MB_HCMD_H_DATA 0x0000FFFF 1476
1477 1477//*****************************************************************************
1478 1478#define I2C1_CTRL 0x180008 // I2C #1 control
1479//***************************************************************************** 1479#define FLD_I2C_PERIOD 0xFF000000 // RW [31:24]
1480// I2C #1 1480#define FLD_I2C_SCL_IN 0x00200000 // RW [21]
1481//***************************************************************************** 1481#define FLD_I2C_SDA_IN 0x00100000 // RW [20]
1482#define I2C1_ADDR 0x180000 // I2C #1 address 1482 // RO [19:18] reserved
1483#define FLD_I2C_DADDR 0xfe000000 // RW [31:25] I2C Device Address 1483#define FLD_I2C_SCL_OUT 0x00020000 // RW [17]
1484 // RO [24] reserved 1484#define FLD_I2C_SDA_OUT 0x00010000 // RW [16]
1485//***************************************************************************** 1485 // RO [15] reserved
1486#define FLD_I2C_SADDR 0x00FFFFFF // RW [23:0] I2C Sub-address 1486#define FLD_I2C_DATA_LEN 0x00007000 // RW [14:12]
1487 1487#define FLD_I2C_SADDR_INC 0x00000800 // RW [11]
1488//***************************************************************************** 1488 // RO [10:9] reserved
1489#define I2C1_WDATA 0x180004 // I2C #1 write data 1489#define FLD_I2C_SADDR_LEN 0x00000300 // RW [9:8]
1490#define FLD_I2C_WDATA 0xFFFFFFFF // RW [31:0] 1490 // RO [7:6] reserved
1491 1491#define FLD_I2C_SOFT 0x00000020 // RW [5]
1492//***************************************************************************** 1492#define FLD_I2C_NOSTOP 0x00000010 // RW [4]
1493#define I2C1_CTRL 0x180008 // I2C #1 control 1493#define FLD_I2C_EXTEND 0x00000008 // RW [3]
1494#define FLD_I2C_PERIOD 0xFF000000 // RW [31:24] 1494#define FLD_I2C_SYNC 0x00000004 // RW [2]
1495#define FLD_I2C_SCL_IN 0x00200000 // RW [21] 1495#define FLD_I2C_READ_SA 0x00000002 // RW [1]
1496#define FLD_I2C_SDA_IN 0x00100000 // RW [20] 1496#define FLD_I2C_READ_WRN 0x00000001 // RW [0]
1497 // RO [19:18] reserved 1497
1498#define FLD_I2C_SCL_OUT 0x00020000 // RW [17] 1498//*****************************************************************************
1499#define FLD_I2C_SDA_OUT 0x00010000 // RW [16] 1499#define I2C1_RDATA 0x18000C // I2C #1 read data
1500 // RO [15] reserved 1500#define FLD_I2C_RDATA 0xFFFFFFFF // RO [31:0]
1501#define FLD_I2C_DATA_LEN 0x00007000 // RW [14:12] 1501
1502#define FLD_I2C_SADDR_INC 0x00000800 // RW [11] 1502//*****************************************************************************
1503 // RO [10:9] reserved 1503#define I2C1_STAT 0x180010 // I2C #1 status
1504#define FLD_I2C_SADDR_LEN 0x00000300 // RW [9:8] 1504#define FLD_I2C_XFER_IN_PROG 0x00000002 // RO [1]
1505 // RO [7:6] reserved 1505#define FLD_I2C_RACK 0x00000001 // RO [0]
1506#define FLD_I2C_SOFT 0x00000020 // RW [5] 1506
1507#define FLD_I2C_NOSTOP 0x00000010 // RW [4] 1507//*****************************************************************************
1508#define FLD_I2C_EXTEND 0x00000008 // RW [3] 1508// I2C #2
1509#define FLD_I2C_SYNC 0x00000004 // RW [2] 1509//*****************************************************************************
1510#define FLD_I2C_READ_SA 0x00000002 // RW [1] 1510#define I2C2_ADDR 0x190000 // I2C #2 address
1511#define FLD_I2C_READ_WRN 0x00000001 // RW [0] 1511
1512 1512//*****************************************************************************
1513//***************************************************************************** 1513#define I2C2_WDATA 0x190004 // I2C #2 write data
1514#define I2C1_RDATA 0x18000C // I2C #1 read data 1514
1515#define FLD_I2C_RDATA 0xFFFFFFFF // RO [31:0] 1515//*****************************************************************************
1516 1516#define I2C2_CTRL 0x190008 // I2C #2 control
1517//***************************************************************************** 1517
1518#define I2C1_STAT 0x180010 // I2C #1 status 1518//*****************************************************************************
1519#define FLD_I2C_XFER_IN_PROG 0x00000002 // RO [1] 1519#define I2C2_RDATA 0x19000C // I2C #2 read data
1520#define FLD_I2C_RACK 0x00000001 // RO [0] 1520
1521 1521//*****************************************************************************
1522//***************************************************************************** 1522#define I2C2_STAT 0x190010 // I2C #2 status
1523// I2C #2 1523
1524//***************************************************************************** 1524//*****************************************************************************
1525#define I2C2_ADDR 0x190000 // I2C #2 address 1525// I2C #3
1526 1526//*****************************************************************************
1527//***************************************************************************** 1527#define I2C3_ADDR 0x1A0000 // I2C #3 address
1528#define I2C2_WDATA 0x190004 // I2C #2 write data 1528
1529 1529//*****************************************************************************
1530//***************************************************************************** 1530#define I2C3_WDATA 0x1A0004 // I2C #3 write data
1531#define I2C2_CTRL 0x190008 // I2C #2 control 1531
1532 1532//*****************************************************************************
1533//***************************************************************************** 1533#define I2C3_CTRL 0x1A0008 // I2C #3 control
1534#define I2C2_RDATA 0x19000C // I2C #2 read data 1534
1535 1535//*****************************************************************************
1536//***************************************************************************** 1536#define I2C3_RDATA 0x1A000C // I2C #3 read data
1537#define I2C2_STAT 0x190010 // I2C #2 status 1537
1538 1538//*****************************************************************************
1539//***************************************************************************** 1539#define I2C3_STAT 0x1A0010 // I2C #3 status
1540// I2C #3 1540
1541//***************************************************************************** 1541//*****************************************************************************
1542#define I2C3_ADDR 0x1A0000 // I2C #3 address 1542// UART
1543 1543//*****************************************************************************
1544//***************************************************************************** 1544#define UART_CTL 0x1B0000 // UART Control Register
1545#define I2C3_WDATA 0x1A0004 // I2C #3 write data 1545#define FLD_LOOP_BACK_EN (1 << 7) // RW field - default 0
1546 1546#define FLD_RX_TRG_SZ (3 << 2) // RW field - default 0
1547//***************************************************************************** 1547#define FLD_RX_EN (1 << 1) // RW field - default 0
1548#define I2C3_CTRL 0x1A0008 // I2C #3 control 1548#define FLD_TX_EN (1 << 0) // RW field - default 0
1549 1549
1550//***************************************************************************** 1550//*****************************************************************************
1551#define I2C3_RDATA 0x1A000C // I2C #3 read data 1551#define UART_BRD 0x1B0004 // UART Baud Rate Divisor
1552 1552#define FLD_BRD 0x0000FFFF // RW field - default 0x197
1553//***************************************************************************** 1553
1554#define I2C3_STAT 0x1A0010 // I2C #3 status 1554//*****************************************************************************
1555 1555#define UART_DBUF 0x1B0008 // UART Tx/Rx Data BuFFer
1556//***************************************************************************** 1556#define FLD_DB 0xFFFFFFFF // RW field - default 0
1557// UART 1557
1558//***************************************************************************** 1558//*****************************************************************************
1559#define UART_CTL 0x1B0000 // UART Control Register 1559#define UART_ISR 0x1B000C // UART Interrupt Status
1560#define FLD_LOOP_BACK_EN (1 << 7) // RW field - default 0 1560#define FLD_RXD_TIMEOUT_EN (1 << 7) // RW field - default 0
1561#define FLD_RX_TRG_SZ (3 << 2) // RW field - default 0 1561#define FLD_FRM_ERR_EN (1 << 6) // RW field - default 0
1562#define FLD_RX_EN (1 << 1) // RW field - default 0 1562#define FLD_RXD_RDY_EN (1 << 5) // RW field - default 0
1563#define FLD_TX_EN (1 << 0) // RW field - default 0 1563#define FLD_TXD_EMPTY_EN (1 << 4) // RW field - default 0
1564 1564#define FLD_RXD_OVERFLOW (1 << 3) // RW field - default 0
1565//***************************************************************************** 1565#define FLD_FRM_ERR (1 << 2) // RW field - default 0
1566#define UART_BRD 0x1B0004 // UART Baud Rate Divisor 1566#define FLD_RXD_RDY (1 << 1) // RW field - default 0
1567#define FLD_BRD 0x0000FFFF // RW field - default 0x197 1567#define FLD_TXD_EMPTY (1 << 0) // RW field - default 0
1568 1568
1569//***************************************************************************** 1569//*****************************************************************************
1570#define UART_DBUF 0x1B0008 // UART Tx/Rx Data BuFFer 1570#define UART_CNT 0x1B0010 // UART Tx/Rx FIFO Byte Count
1571#define FLD_DB 0xFFFFFFFF // RW field - default 0 1571#define FLD_TXD_CNT (0x1F << 8) // RW field - default 0
1572 1572#define FLD_RXD_CNT (0x1F << 0) // RW field - default 0
1573//***************************************************************************** 1573
1574#define UART_ISR 0x1B000C // UART Interrupt Status 1574//*****************************************************************************
1575#define FLD_RXD_TIMEOUT_EN (1 << 7) // RW field - default 0
1576#define FLD_FRM_ERR_EN (1 << 6) // RW field - default 0
1577#define FLD_RXD_RDY_EN (1 << 5) // RW field - default 0
1578#define FLD_TXD_EMPTY_EN (1 << 4) // RW field - default 0
1579#define FLD_RXD_OVERFLOW (1 << 3) // RW field - default 0
1580#define FLD_FRM_ERR (1 << 2) // RW field - default 0
1581#define FLD_RXD_RDY (1 << 1) // RW field - default 0
1582#define FLD_TXD_EMPTY (1 << 0) // RW field - default 0
1583
1584//*****************************************************************************
1585#define UART_CNT 0x1B0010 // UART Tx/Rx FIFO Byte Count
1586#define FLD_TXD_CNT (0x1F << 8) // RW field - default 0
1587#define FLD_RXD_CNT (0x1F << 0) // RW field - default 0
1588
1589//*****************************************************************************
1590// Motion Detection 1575// Motion Detection
1591#define MD_CH0_GRID_BLOCK_YCNT 0x170014 1576#define MD_CH0_GRID_BLOCK_YCNT 0x170014
1592#define MD_CH1_GRID_BLOCK_YCNT 0x170094 1577#define MD_CH1_GRID_BLOCK_YCNT 0x170094
@@ -1604,6 +1589,4 @@
1604#define PIXEL_ENGINE_VIP1 0 1589#define PIXEL_ENGINE_VIP1 0
1605#define PIXEL_ENGINE_VIP2 1 1590#define PIXEL_ENGINE_VIP2 1
1606 1591
1607#endif //Athena_REGISTERS 1592#endif //Athena_REGISTERS
1608
1609
diff --git a/drivers/staging/cx25821/cx25821-sram.h b/drivers/staging/cx25821/cx25821-sram.h
index 813063582260..bd677ee22996 100644
--- a/drivers/staging/cx25821/cx25821-sram.h
+++ b/drivers/staging/cx25821/cx25821-sram.h
@@ -1,266 +1,261 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#ifndef __ATHENA_SRAM_H__ 23#ifndef __ATHENA_SRAM_H__
24#define __ATHENA_SRAM_H__ 24#define __ATHENA_SRAM_H__
25 25
26//#define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM 26//#define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM
27#define VID_CMDS_SIZE 80 // Video CMDS size in bytes 27#define VID_CMDS_SIZE 80 // Video CMDS size in bytes
28#define AUDIO_CMDS_SIZE 80 // AUDIO CMDS size in bytes 28#define AUDIO_CMDS_SIZE 80 // AUDIO CMDS size in bytes
29#define MBIF_CMDS_SIZE 80 // MBIF CMDS size in bytes 29#define MBIF_CMDS_SIZE 80 // MBIF CMDS size in bytes
30 30
31//#define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers 31//#define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers
32#define VID_IQ_SIZE 64 // VID instruction queue size in bytes 32#define VID_IQ_SIZE 64 // VID instruction queue size in bytes
33#define MBIF_IQ_SIZE 64 33#define MBIF_IQ_SIZE 64
34#define AUDIO_IQ_SIZE 64 // AUD instruction queue size in bytes 34#define AUDIO_IQ_SIZE 64 // AUD instruction queue size in bytes
35 35
36#define VID_CDT_SIZE 64 // VID cluster descriptor table size in bytes 36#define VID_CDT_SIZE 64 // VID cluster descriptor table size in bytes
37#define MBIF_CDT_SIZE 64 // MBIF/HBI cluster descriptor table size in bytes 37#define MBIF_CDT_SIZE 64 // MBIF/HBI cluster descriptor table size in bytes
38#define AUDIO_CDT_SIZE 48 // AUD cluster descriptor table size in bytes 38#define AUDIO_CDT_SIZE 48 // AUD cluster descriptor table size in bytes
39 39
40//#define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM 40//#define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM
41//#define RX_SRAM_END_SIZE = 0; // End of RX SRAM 41//#define RX_SRAM_END_SIZE = 0; // End of RX SRAM
42 42
43//#define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM 43//#define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM
44//#define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora 44//#define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora
45 45
46#define VID_CLUSTER_SIZE 1440 // VID cluster data line 46#define VID_CLUSTER_SIZE 1440 // VID cluster data line
47#define AUDIO_CLUSTER_SIZE 128 // AUDIO cluster data line 47#define AUDIO_CLUSTER_SIZE 128 // AUDIO cluster data line
48#define MBIF_CLUSTER_SIZE 1440 // MBIF/HBI cluster data line 48#define MBIF_CLUSTER_SIZE 1440 // MBIF/HBI cluster data line
49 49
50 50//#define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM
51//#define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM 51//#define TX_SRAM_END_SIZE = 0; // End of TX SRAM
52//#define TX_SRAM_END_SIZE = 0; // End of TX SRAM 52
53 53// Receive SRAM
54// Receive SRAM 54#define RX_SRAM_START 0x10000
55#define RX_SRAM_START 0x10000 55#define VID_A_DOWN_CMDS 0x10000
56#define VID_A_DOWN_CMDS 0x10000 56#define VID_B_DOWN_CMDS 0x10050
57#define VID_B_DOWN_CMDS 0x10050 57#define VID_C_DOWN_CMDS 0x100A0
58#define VID_C_DOWN_CMDS 0x100A0 58#define VID_D_DOWN_CMDS 0x100F0
59#define VID_D_DOWN_CMDS 0x100F0 59#define VID_E_DOWN_CMDS 0x10140
60#define VID_E_DOWN_CMDS 0x10140 60#define VID_F_DOWN_CMDS 0x10190
61#define VID_F_DOWN_CMDS 0x10190 61#define VID_G_DOWN_CMDS 0x101E0
62#define VID_G_DOWN_CMDS 0x101E0 62#define VID_H_DOWN_CMDS 0x10230
63#define VID_H_DOWN_CMDS 0x10230 63#define VID_A_UP_CMDS 0x10280
64#define VID_A_UP_CMDS 0x10280 64#define VID_B_UP_CMDS 0x102D0
65#define VID_B_UP_CMDS 0x102D0 65#define VID_C_UP_CMDS 0x10320
66#define VID_C_UP_CMDS 0x10320 66#define VID_D_UP_CMDS 0x10370
67#define VID_D_UP_CMDS 0x10370 67#define VID_E_UP_CMDS 0x103C0
68#define VID_E_UP_CMDS 0x103C0 68#define VID_F_UP_CMDS 0x10410
69#define VID_F_UP_CMDS 0x10410 69#define VID_I_UP_CMDS 0x10460
70#define VID_I_UP_CMDS 0x10460 70#define VID_J_UP_CMDS 0x104B0
71#define VID_J_UP_CMDS 0x104B0 71#define AUD_A_DOWN_CMDS 0x10500
72#define AUD_A_DOWN_CMDS 0x10500 72#define AUD_B_DOWN_CMDS 0x10550
73#define AUD_B_DOWN_CMDS 0x10550 73#define AUD_C_DOWN_CMDS 0x105A0
74#define AUD_C_DOWN_CMDS 0x105A0 74#define AUD_D_DOWN_CMDS 0x105F0
75#define AUD_D_DOWN_CMDS 0x105F0 75#define AUD_A_UP_CMDS 0x10640
76#define AUD_A_UP_CMDS 0x10640 76#define AUD_B_UP_CMDS 0x10690
77#define AUD_B_UP_CMDS 0x10690 77#define AUD_C_UP_CMDS 0x106E0
78#define AUD_C_UP_CMDS 0x106E0 78#define AUD_E_UP_CMDS 0x10730
79#define AUD_E_UP_CMDS 0x10730 79#define MBIF_A_DOWN_CMDS 0x10780
80#define MBIF_A_DOWN_CMDS 0x10780 80#define MBIF_B_DOWN_CMDS 0x107D0
81#define MBIF_B_DOWN_CMDS 0x107D0 81#define DMA_SCRATCH_PAD 0x10820 // Scratch pad area from 0x10820 to 0x10B40
82#define DMA_SCRATCH_PAD 0x10820 // Scratch pad area from 0x10820 to 0x10B40 82
83 83//#define RX_SRAM_POOL_START = 0x105B0;
84//#define RX_SRAM_POOL_START = 0x105B0; 84
85 85#define VID_A_IQ 0x11000
86#define VID_A_IQ 0x11000 86#define VID_B_IQ 0x11040
87#define VID_B_IQ 0x11040 87#define VID_C_IQ 0x11080
88#define VID_C_IQ 0x11080 88#define VID_D_IQ 0x110C0
89#define VID_D_IQ 0x110C0 89#define VID_E_IQ 0x11100
90#define VID_E_IQ 0x11100 90#define VID_F_IQ 0x11140
91#define VID_F_IQ 0x11140 91#define VID_G_IQ 0x11180
92#define VID_G_IQ 0x11180 92#define VID_H_IQ 0x111C0
93#define VID_H_IQ 0x111C0 93#define VID_I_IQ 0x11200
94#define VID_I_IQ 0x11200 94#define VID_J_IQ 0x11240
95#define VID_J_IQ 0x11240 95#define AUD_A_IQ 0x11280
96#define AUD_A_IQ 0x11280 96#define AUD_B_IQ 0x112C0
97#define AUD_B_IQ 0x112C0 97#define AUD_C_IQ 0x11300
98#define AUD_C_IQ 0x11300 98#define AUD_D_IQ 0x11340
99#define AUD_D_IQ 0x11340 99#define AUD_E_IQ 0x11380
100#define AUD_E_IQ 0x11380 100#define MBIF_A_IQ 0x11000
101#define MBIF_A_IQ 0x11000 101#define MBIF_B_IQ 0x110C0
102#define MBIF_B_IQ 0x110C0 102
103 103#define VID_A_CDT 0x10C00
104#define VID_A_CDT 0x10C00 104#define VID_B_CDT 0x10C40
105#define VID_B_CDT 0x10C40 105#define VID_C_CDT 0x10C80
106#define VID_C_CDT 0x10C80 106#define VID_D_CDT 0x10CC0
107#define VID_D_CDT 0x10CC0 107#define VID_E_CDT 0x10D00
108#define VID_E_CDT 0x10D00 108#define VID_F_CDT 0x10D40
109#define VID_F_CDT 0x10D40 109#define VID_G_CDT 0x10D80
110#define VID_G_CDT 0x10D80 110#define VID_H_CDT 0x10DC0
111#define VID_H_CDT 0x10DC0 111#define VID_I_CDT 0x10E00
112#define VID_I_CDT 0x10E00 112#define VID_J_CDT 0x10E40
113#define VID_J_CDT 0x10E40 113#define AUD_A_CDT 0x10E80
114#define AUD_A_CDT 0x10E80 114#define AUD_B_CDT 0x10EB0
115#define AUD_B_CDT 0x10EB0 115#define AUD_C_CDT 0x10EE0
116#define AUD_C_CDT 0x10EE0 116#define AUD_D_CDT 0x10F10
117#define AUD_D_CDT 0x10F10 117#define AUD_E_CDT 0x10F40
118#define AUD_E_CDT 0x10F40 118#define MBIF_A_CDT 0x10C00
119#define MBIF_A_CDT 0x10C00 119#define MBIF_B_CDT 0x10CC0
120#define MBIF_B_CDT 0x10CC0 120
121 121// Cluster Buffer for RX
122// Cluster Buffer for RX 122#define VID_A_UP_CLUSTER_1 0x11400
123#define VID_A_UP_CLUSTER_1 0x11400 123#define VID_A_UP_CLUSTER_2 0x119A0
124#define VID_A_UP_CLUSTER_2 0x119A0 124#define VID_A_UP_CLUSTER_3 0x11F40
125#define VID_A_UP_CLUSTER_3 0x11F40 125#define VID_A_UP_CLUSTER_4 0x124E0
126#define VID_A_UP_CLUSTER_4 0x124E0 126
127 127#define VID_B_UP_CLUSTER_1 0x12A80
128#define VID_B_UP_CLUSTER_1 0x12A80 128#define VID_B_UP_CLUSTER_2 0x13020
129#define VID_B_UP_CLUSTER_2 0x13020 129#define VID_B_UP_CLUSTER_3 0x135C0
130#define VID_B_UP_CLUSTER_3 0x135C0 130#define VID_B_UP_CLUSTER_4 0x13B60
131#define VID_B_UP_CLUSTER_4 0x13B60 131
132 132#define VID_C_UP_CLUSTER_1 0x14100
133#define VID_C_UP_CLUSTER_1 0x14100 133#define VID_C_UP_CLUSTER_2 0x146A0
134#define VID_C_UP_CLUSTER_2 0x146A0 134#define VID_C_UP_CLUSTER_3 0x14C40
135#define VID_C_UP_CLUSTER_3 0x14C40 135#define VID_C_UP_CLUSTER_4 0x151E0
136#define VID_C_UP_CLUSTER_4 0x151E0 136
137 137#define VID_D_UP_CLUSTER_1 0x15780
138#define VID_D_UP_CLUSTER_1 0x15780 138#define VID_D_UP_CLUSTER_2 0x15D20
139#define VID_D_UP_CLUSTER_2 0x15D20 139#define VID_D_UP_CLUSTER_3 0x162C0
140#define VID_D_UP_CLUSTER_3 0x162C0 140#define VID_D_UP_CLUSTER_4 0x16860
141#define VID_D_UP_CLUSTER_4 0x16860 141
142 142#define VID_E_UP_CLUSTER_1 0x16E00
143#define VID_E_UP_CLUSTER_1 0x16E00 143#define VID_E_UP_CLUSTER_2 0x173A0
144#define VID_E_UP_CLUSTER_2 0x173A0 144#define VID_E_UP_CLUSTER_3 0x17940
145#define VID_E_UP_CLUSTER_3 0x17940 145#define VID_E_UP_CLUSTER_4 0x17EE0
146#define VID_E_UP_CLUSTER_4 0x17EE0 146
147 147#define VID_F_UP_CLUSTER_1 0x18480
148#define VID_F_UP_CLUSTER_1 0x18480 148#define VID_F_UP_CLUSTER_2 0x18A20
149#define VID_F_UP_CLUSTER_2 0x18A20 149#define VID_F_UP_CLUSTER_3 0x18FC0
150#define VID_F_UP_CLUSTER_3 0x18FC0 150#define VID_F_UP_CLUSTER_4 0x19560
151#define VID_F_UP_CLUSTER_4 0x19560 151
152 152#define VID_I_UP_CLUSTER_1 0x19B00
153#define VID_I_UP_CLUSTER_1 0x19B00 153#define VID_I_UP_CLUSTER_2 0x1A0A0
154#define VID_I_UP_CLUSTER_2 0x1A0A0 154#define VID_I_UP_CLUSTER_3 0x1A640
155#define VID_I_UP_CLUSTER_3 0x1A640 155#define VID_I_UP_CLUSTER_4 0x1ABE0
156#define VID_I_UP_CLUSTER_4 0x1ABE0 156
157 157#define VID_J_UP_CLUSTER_1 0x1B180
158#define VID_J_UP_CLUSTER_1 0x1B180 158#define VID_J_UP_CLUSTER_2 0x1B720
159#define VID_J_UP_CLUSTER_2 0x1B720 159#define VID_J_UP_CLUSTER_3 0x1BCC0
160#define VID_J_UP_CLUSTER_3 0x1BCC0 160#define VID_J_UP_CLUSTER_4 0x1C260
161#define VID_J_UP_CLUSTER_4 0x1C260 161
162 162#define AUD_A_UP_CLUSTER_1 0x1C800
163#define AUD_A_UP_CLUSTER_1 0x1C800 163#define AUD_A_UP_CLUSTER_2 0x1C880
164#define AUD_A_UP_CLUSTER_2 0x1C880 164#define AUD_A_UP_CLUSTER_3 0x1C900
165#define AUD_A_UP_CLUSTER_3 0x1C900 165
166 166#define AUD_B_UP_CLUSTER_1 0x1C980
167#define AUD_B_UP_CLUSTER_1 0x1C980 167#define AUD_B_UP_CLUSTER_2 0x1CA00
168#define AUD_B_UP_CLUSTER_2 0x1CA00 168#define AUD_B_UP_CLUSTER_3 0x1CA80
169#define AUD_B_UP_CLUSTER_3 0x1CA80 169
170 170#define AUD_C_UP_CLUSTER_1 0x1CB00
171#define AUD_C_UP_CLUSTER_1 0x1CB00 171#define AUD_C_UP_CLUSTER_2 0x1CB80
172#define AUD_C_UP_CLUSTER_2 0x1CB80 172#define AUD_C_UP_CLUSTER_3 0x1CC00
173#define AUD_C_UP_CLUSTER_3 0x1CC00 173
174 174#define AUD_E_UP_CLUSTER_1 0x1CC80
175#define AUD_E_UP_CLUSTER_1 0x1CC80 175#define AUD_E_UP_CLUSTER_2 0x1CD00
176#define AUD_E_UP_CLUSTER_2 0x1CD00 176#define AUD_E_UP_CLUSTER_3 0x1CD80
177#define AUD_E_UP_CLUSTER_3 0x1CD80 177
178 178#define RX_SRAM_POOL_FREE 0x1CE00
179#define RX_SRAM_POOL_FREE 0x1CE00 179#define RX_SRAM_END 0x1D000
180#define RX_SRAM_END 0x1D000 180
181 181// Free Receive SRAM 144 Bytes
182// Free Receive SRAM 144 Bytes 182
183 183// Transmit SRAM
184 184#define TX_SRAM_POOL_START 0x00000
185// Transmit SRAM 185
186#define TX_SRAM_POOL_START 0x00000 186#define VID_A_DOWN_CLUSTER_1 0x00040
187 187#define VID_A_DOWN_CLUSTER_2 0x005E0
188#define VID_A_DOWN_CLUSTER_1 0x00040 188#define VID_A_DOWN_CLUSTER_3 0x00B80
189#define VID_A_DOWN_CLUSTER_2 0x005E0 189#define VID_A_DOWN_CLUSTER_4 0x01120
190#define VID_A_DOWN_CLUSTER_3 0x00B80 190
191#define VID_A_DOWN_CLUSTER_4 0x01120 191#define VID_B_DOWN_CLUSTER_1 0x016C0
192 192#define VID_B_DOWN_CLUSTER_2 0x01C60
193#define VID_B_DOWN_CLUSTER_1 0x016C0 193#define VID_B_DOWN_CLUSTER_3 0x02200
194#define VID_B_DOWN_CLUSTER_2 0x01C60 194#define VID_B_DOWN_CLUSTER_4 0x027A0
195#define VID_B_DOWN_CLUSTER_3 0x02200 195
196#define VID_B_DOWN_CLUSTER_4 0x027A0 196#define VID_C_DOWN_CLUSTER_1 0x02D40
197 197#define VID_C_DOWN_CLUSTER_2 0x032E0
198#define VID_C_DOWN_CLUSTER_1 0x02D40 198#define VID_C_DOWN_CLUSTER_3 0x03880
199#define VID_C_DOWN_CLUSTER_2 0x032E0 199#define VID_C_DOWN_CLUSTER_4 0x03E20
200#define VID_C_DOWN_CLUSTER_3 0x03880 200
201#define VID_C_DOWN_CLUSTER_4 0x03E20 201#define VID_D_DOWN_CLUSTER_1 0x043C0
202 202#define VID_D_DOWN_CLUSTER_2 0x04960
203#define VID_D_DOWN_CLUSTER_1 0x043C0 203#define VID_D_DOWN_CLUSTER_3 0x04F00
204#define VID_D_DOWN_CLUSTER_2 0x04960 204#define VID_D_DOWN_CLUSTER_4 0x054A0
205#define VID_D_DOWN_CLUSTER_3 0x04F00 205
206#define VID_D_DOWN_CLUSTER_4 0x054A0 206#define VID_E_DOWN_CLUSTER_1 0x05a40
207 207#define VID_E_DOWN_CLUSTER_2 0x05FE0
208#define VID_E_DOWN_CLUSTER_1 0x05a40 208#define VID_E_DOWN_CLUSTER_3 0x06580
209#define VID_E_DOWN_CLUSTER_2 0x05FE0 209#define VID_E_DOWN_CLUSTER_4 0x06B20
210#define VID_E_DOWN_CLUSTER_3 0x06580 210
211#define VID_E_DOWN_CLUSTER_4 0x06B20 211#define VID_F_DOWN_CLUSTER_1 0x070C0
212 212#define VID_F_DOWN_CLUSTER_2 0x07660
213#define VID_F_DOWN_CLUSTER_1 0x070C0 213#define VID_F_DOWN_CLUSTER_3 0x07C00
214#define VID_F_DOWN_CLUSTER_2 0x07660 214#define VID_F_DOWN_CLUSTER_4 0x081A0
215#define VID_F_DOWN_CLUSTER_3 0x07C00 215
216#define VID_F_DOWN_CLUSTER_4 0x081A0 216#define VID_G_DOWN_CLUSTER_1 0x08740
217 217#define VID_G_DOWN_CLUSTER_2 0x08CE0
218#define VID_G_DOWN_CLUSTER_1 0x08740 218#define VID_G_DOWN_CLUSTER_3 0x09280
219#define VID_G_DOWN_CLUSTER_2 0x08CE0 219#define VID_G_DOWN_CLUSTER_4 0x09820
220#define VID_G_DOWN_CLUSTER_3 0x09280 220
221#define VID_G_DOWN_CLUSTER_4 0x09820 221#define VID_H_DOWN_CLUSTER_1 0x09DC0
222 222#define VID_H_DOWN_CLUSTER_2 0x0A360
223#define VID_H_DOWN_CLUSTER_1 0x09DC0 223#define VID_H_DOWN_CLUSTER_3 0x0A900
224#define VID_H_DOWN_CLUSTER_2 0x0A360 224#define VID_H_DOWN_CLUSTER_4 0x0AEA0
225#define VID_H_DOWN_CLUSTER_3 0x0A900 225
226#define VID_H_DOWN_CLUSTER_4 0x0AEA0 226#define AUD_A_DOWN_CLUSTER_1 0x0B500
227 227#define AUD_A_DOWN_CLUSTER_2 0x0B580
228#define AUD_A_DOWN_CLUSTER_1 0x0B500 228#define AUD_A_DOWN_CLUSTER_3 0x0B600
229#define AUD_A_DOWN_CLUSTER_2 0x0B580 229
230#define AUD_A_DOWN_CLUSTER_3 0x0B600 230#define AUD_B_DOWN_CLUSTER_1 0x0B680
231 231#define AUD_B_DOWN_CLUSTER_2 0x0B700
232#define AUD_B_DOWN_CLUSTER_1 0x0B680 232#define AUD_B_DOWN_CLUSTER_3 0x0B780
233#define AUD_B_DOWN_CLUSTER_2 0x0B700 233
234#define AUD_B_DOWN_CLUSTER_3 0x0B780 234#define AUD_C_DOWN_CLUSTER_1 0x0B800
235 235#define AUD_C_DOWN_CLUSTER_2 0x0B880
236#define AUD_C_DOWN_CLUSTER_1 0x0B800 236#define AUD_C_DOWN_CLUSTER_3 0x0B900
237#define AUD_C_DOWN_CLUSTER_2 0x0B880 237
238#define AUD_C_DOWN_CLUSTER_3 0x0B900 238#define AUD_D_DOWN_CLUSTER_1 0x0B980
239 239#define AUD_D_DOWN_CLUSTER_2 0x0BA00
240#define AUD_D_DOWN_CLUSTER_1 0x0B980 240#define AUD_D_DOWN_CLUSTER_3 0x0BA80
241#define AUD_D_DOWN_CLUSTER_2 0x0BA00 241
242#define AUD_D_DOWN_CLUSTER_3 0x0BA80 242#define TX_SRAM_POOL_FREE 0x0BB00
243 243#define TX_SRAM_END 0x0C000
244#define TX_SRAM_POOL_FREE 0x0BB00 244
245#define TX_SRAM_END 0x0C000 245#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2)
246 246#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3)
247 247#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4)
248#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2) 248
249#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3) 249#define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE)
250#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4) 250#define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE)
251 251#define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE)
252#define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE) 252
253#define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE) 253#define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE)
254#define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE) 254#define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE)
255 255#define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE)
256#define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE) 256
257#define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE) 257#define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE)
258#define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE) 258#define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE)
259 259#define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)
260#define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE) 260
261#define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE) 261#endif
262#define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)
263
264
265#endif
266
diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.c b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c
index 720729efc316..c8905e0ac509 100644
--- a/drivers/staging/cx25821/cx25821-video-upstream-ch2.c
+++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c
@@ -1,847 +1,835 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23 23#include "cx25821-video.h"
24#include "cx25821-video.h" 24#include "cx25821-video-upstream-ch2.h"
25#include "cx25821-video-upstream-ch2.h" 25
26 26#include <linux/fs.h>
27#include <linux/fs.h> 27#include <linux/errno.h>
28#include <linux/errno.h> 28#include <linux/kernel.h>
29#include <linux/kernel.h> 29#include <linux/init.h>
30#include <linux/init.h> 30#include <linux/module.h>
31#include <linux/module.h> 31#include <linux/syscalls.h>
32#include <linux/syscalls.h> 32#include <linux/file.h>
33#include <linux/file.h> 33#include <linux/fcntl.h>
34#include <linux/fcntl.h> 34#include <asm/uaccess.h>
35#include <asm/uaccess.h> 35
36 36MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
37 37MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
38MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); 38MODULE_LICENSE("GPL");
39MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); 39
40MODULE_LICENSE("GPL"); 40static int _intr_msk =
41 41 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
42 42
43static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR; 43static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
44 44 __le32 * rp, unsigned int offset,
45 45 unsigned int bpl, u32 sync_line,
46static __le32 *cx25821_update_riscprogram_ch2( struct cx25821_dev *dev, 46 unsigned int lines,
47 __le32 *rp, unsigned int offset, unsigned int bpl, 47 int fifo_enable, int field_type)
48 u32 sync_line, unsigned int lines, int fifo_enable, int field_type) 48{
49{ 49 unsigned int line, i;
50 unsigned int line, i; 50 int dist_betwn_starts = bpl * 2;
51 int dist_betwn_starts = bpl * 2; 51
52 52 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
53 53
54 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 54 if (USE_RISC_NOOP_VIDEO) {
55 55 for (i = 0; i < NUM_NO_OPS; i++) {
56 56 *(rp++) = cpu_to_le32(RISC_NOOP);
57 if( USE_RISC_NOOP_VIDEO ) 57 }
58 { 58 }
59 for( i = 0; i < NUM_NO_OPS; i++ ) 59
60 { 60 /* scan lines */
61 *(rp++) = cpu_to_le32(RISC_NOOP); 61 for (line = 0; line < lines; line++) {
62 } 62 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
63 } 63 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
64 64 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
65 /* scan lines */ 65
66 for (line = 0; line < lines; line++) 66 if ((lines <= NTSC_FIELD_HEIGHT)
67 { 67 || (line < (NTSC_FIELD_HEIGHT - 1))
68 *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl); 68 || !(dev->_isNTSC_ch2)) {
69 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2+offset); 69 offset += dist_betwn_starts;
70 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 70 }
71 71 }
72 if ( (lines <= NTSC_FIELD_HEIGHT) || (line < (NTSC_FIELD_HEIGHT-1)) || !(dev->_isNTSC_ch2) ) 72
73 { 73 return rp;
74 offset += dist_betwn_starts; 74}
75 } 75
76 } 76static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
77 77 __le32 * rp,
78 return rp; 78 dma_addr_t databuf_phys_addr,
79} 79 unsigned int offset,
80 80 u32 sync_line, unsigned int bpl,
81static __le32 *cx25821_risc_field_upstream_ch2( struct cx25821_dev *dev, 81 unsigned int lines,
82 __le32 *rp, 82 int fifo_enable, int field_type)
83 dma_addr_t databuf_phys_addr, 83{
84 unsigned int offset, u32 sync_line, unsigned int bpl, 84 unsigned int line, i;
85 unsigned int lines, int fifo_enable, int field_type) 85 struct sram_channel *sram_ch =
86{ 86 &dev->sram_channels[dev->_channel2_upstream_select];
87 unsigned int line, i; 87 int dist_betwn_starts = bpl * 2;
88 struct sram_channel *sram_ch = &dev->sram_channels[dev->_channel2_upstream_select]; 88
89 int dist_betwn_starts = bpl * 2; 89 /* sync instruction */
90 90 if (sync_line != NO_SYNC_LINE) {
91 91 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
92 /* sync instruction */ 92 }
93 if (sync_line != NO_SYNC_LINE) 93
94 { 94 if (USE_RISC_NOOP_VIDEO) {
95 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 95 for (i = 0; i < NUM_NO_OPS; i++) {
96 } 96 *(rp++) = cpu_to_le32(RISC_NOOP);
97 97 }
98 98 }
99 if( USE_RISC_NOOP_VIDEO ) 99
100 { 100 /* scan lines */
101 for( i = 0; i < NUM_NO_OPS; i++ ) 101 for (line = 0; line < lines; line++) {
102 { 102 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
103 *(rp++) = cpu_to_le32(RISC_NOOP); 103 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
104 } 104 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
105 } 105
106 106 if ((lines <= NTSC_FIELD_HEIGHT)
107 /* scan lines */ 107 || (line < (NTSC_FIELD_HEIGHT - 1))
108 for (line = 0; line < lines; line++) 108 || !(dev->_isNTSC_ch2)) {
109 { 109 offset += dist_betwn_starts;
110 *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl); 110 }
111 *(rp++) = cpu_to_le32(databuf_phys_addr+offset); 111
112 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 112 // check if we need to enable the FIFO after the first 4 lines
113 113 // For the upstream video channel, the risc engine will enable the FIFO.
114 114 if (fifo_enable && line == 3) {
115 if ( (lines <= NTSC_FIELD_HEIGHT) || (line < (NTSC_FIELD_HEIGHT-1)) || !(dev->_isNTSC_ch2) ) 115 *(rp++) = RISC_WRITECR;
116 { 116 *(rp++) = sram_ch->dma_ctl;
117 offset += dist_betwn_starts; 117 *(rp++) = FLD_VID_FIFO_EN;
118 } 118 *(rp++) = 0x00000001;
119 119 }
120 120 }
121 // check if we need to enable the FIFO after the first 4 lines 121
122 // For the upstream video channel, the risc engine will enable the FIFO. 122 return rp;
123 if ( fifo_enable && line == 3 ) 123}
124 { 124
125 *(rp++) = RISC_WRITECR; 125int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
126 *(rp++) = sram_ch->dma_ctl; 126 struct pci_dev *pci,
127 *(rp++) = FLD_VID_FIFO_EN; 127 unsigned int top_offset, unsigned int bpl,
128 *(rp++) = 0x00000001; 128 unsigned int lines)
129 } 129{
130 } 130 __le32 *rp;
131 131 int fifo_enable = 0;
132 return rp; 132 int singlefield_lines = lines >> 1; //get line count for single field
133} 133 int odd_num_lines = singlefield_lines;
134 134 int frame = 0;
135int cx25821_risc_buffer_upstream_ch2( struct cx25821_dev *dev, struct pci_dev *pci, 135 int frame_size = 0;
136 unsigned int top_offset, 136 int databuf_offset = 0;
137 unsigned int bpl, unsigned int lines) 137 int risc_program_size = 0;
138{ 138 int risc_flag = RISC_CNT_RESET;
139 __le32 *rp; 139 unsigned int bottom_offset = bpl;
140 int fifo_enable = 0; 140 dma_addr_t risc_phys_jump_addr;
141 int singlefield_lines = lines >> 1; //get line count for single field 141
142 int odd_num_lines = singlefield_lines; 142 if (dev->_isNTSC_ch2) {
143 int frame = 0; 143 odd_num_lines = singlefield_lines + 1;
144 int frame_size = 0; 144 risc_program_size = FRAME1_VID_PROG_SIZE;
145 int databuf_offset = 0; 145 frame_size =
146 int risc_program_size = 0; 146 (bpl ==
147 int risc_flag = RISC_CNT_RESET; 147 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
148 unsigned int bottom_offset = bpl; 148 FRAME_SIZE_NTSC_Y422;
149 dma_addr_t risc_phys_jump_addr; 149 } else {
150 150 risc_program_size = PAL_VID_PROG_SIZE;
151 151 frame_size =
152 if( dev->_isNTSC_ch2 ) 152 (bpl ==
153 { 153 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
154 odd_num_lines = singlefield_lines + 1; 154 }
155 risc_program_size = FRAME1_VID_PROG_SIZE; 155
156 frame_size = (bpl == Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422; 156 /* Virtual address of Risc buffer program */
157 } 157 rp = dev->_dma_virt_addr_ch2;
158 else 158
159 { 159 for (frame = 0; frame < NUM_FRAMES; frame++) {
160 risc_program_size = PAL_VID_PROG_SIZE; 160 databuf_offset = frame_size * frame;
161 frame_size = (bpl == Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 161
162 } 162 if (UNSET != top_offset) {
163 163 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
164 164 rp = cx25821_risc_field_upstream_ch2(dev, rp,
165 /* Virtual address of Risc buffer program */ 165 dev->
166 rp = dev->_dma_virt_addr_ch2; 166 _data_buf_phys_addr_ch2
167 167 + databuf_offset,
168 for( frame = 0; frame < NUM_FRAMES; frame++ ) 168 top_offset, 0, bpl,
169 { 169 odd_num_lines,
170 databuf_offset = frame_size * frame; 170 fifo_enable,
171 171 ODD_FIELD);
172 172 }
173 if (UNSET != top_offset) 173
174 { 174 fifo_enable = FIFO_DISABLE;
175 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE; 175
176 rp = cx25821_risc_field_upstream_ch2(dev, rp, dev->_data_buf_phys_addr_ch2 + databuf_offset, top_offset, 0, bpl, odd_num_lines, fifo_enable, ODD_FIELD); 176 //Even field
177 } 177 rp = cx25821_risc_field_upstream_ch2(dev, rp,
178 178 dev->
179 fifo_enable = FIFO_DISABLE; 179 _data_buf_phys_addr_ch2 +
180 180 databuf_offset,
181 181 bottom_offset, 0x200, bpl,
182 //Even field 182 singlefield_lines,
183 rp = cx25821_risc_field_upstream_ch2(dev, rp, dev->_data_buf_phys_addr_ch2 + databuf_offset, bottom_offset, 0x200, bpl, singlefield_lines, fifo_enable, EVEN_FIELD); 183 fifo_enable, EVEN_FIELD);
184 184
185 185 if (frame == 0) {
186 if( frame == 0 ) 186 risc_flag = RISC_CNT_RESET;
187 { 187 risc_phys_jump_addr =
188 risc_flag = RISC_CNT_RESET; 188 dev->_dma_phys_start_addr_ch2 + risc_program_size;
189 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2 + risc_program_size; 189 } else {
190 } 190 risc_flag = RISC_CNT_INC;
191 else 191 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
192 { 192 }
193 risc_flag = RISC_CNT_INC; 193
194 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2; 194 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
195 } 195 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
196 196 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
197 197 *(rp++) = cpu_to_le32(0);
198 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ 198 }
199 *(rp++) = cpu_to_le32(RISC_JUMP|RISC_IRQ1|risc_flag); 199
200 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 200 return 0;
201 *(rp++) = cpu_to_le32(0); 201}
202 } 202
203 203void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
204 return 0; 204{
205} 205 struct sram_channel *sram_ch =
206 206 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J];
207 207 u32 tmp = 0;
208void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev) 208
209{ 209 if (!dev->_is_running_ch2) {
210 struct sram_channel *sram_ch = &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J]; 210 printk
211 u32 tmp = 0; 211 ("cx25821: No video file is currently running so return!\n");
212 212 return;
213 if( !dev->_is_running_ch2 ) 213 }
214 { 214 //Disable RISC interrupts
215 printk("cx25821: No video file is currently running so return!\n"); 215 tmp = cx_read(sram_ch->int_msk);
216 return; 216 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
217 } 217
218 218 //Turn OFF risc and fifo
219 //Disable RISC interrupts 219 tmp = cx_read(sram_ch->dma_ctl);
220 tmp = cx_read( sram_ch->int_msk ); 220 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
221 cx_write( sram_ch->int_msk, tmp & ~_intr_msk); 221
222 222 //Clear data buffer memory
223 //Turn OFF risc and fifo 223 if (dev->_data_buf_virt_addr_ch2)
224 tmp = cx_read( sram_ch->dma_ctl ); 224 memset(dev->_data_buf_virt_addr_ch2, 0,
225 cx_write( sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN) ); 225 dev->_data_buf_size_ch2);
226 226
227 //Clear data buffer memory 227 dev->_is_running_ch2 = 0;
228 if( dev->_data_buf_virt_addr_ch2 ) 228 dev->_is_first_frame_ch2 = 0;
229 memset( dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2 ); 229 dev->_frame_count_ch2 = 0;
230 230 dev->_file_status_ch2 = END_OF_FILE;
231 dev->_is_running_ch2 = 0; 231
232 dev->_is_first_frame_ch2 = 0; 232 if (dev->_irq_queues_ch2) {
233 dev->_frame_count_ch2 = 0; 233 kfree(dev->_irq_queues_ch2);
234 dev->_file_status_ch2 = END_OF_FILE; 234 dev->_irq_queues_ch2 = NULL;
235 235 }
236 if( dev->_irq_queues_ch2 ) 236
237 { 237 if (dev->_filename_ch2 != NULL)
238 kfree(dev->_irq_queues_ch2); 238 kfree(dev->_filename_ch2);
239 dev->_irq_queues_ch2 = NULL; 239
240 } 240 tmp = cx_read(VID_CH_MODE_SEL);
241 241 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
242 if( dev->_filename_ch2 != NULL ) 242}
243 kfree(dev->_filename_ch2); 243
244 244void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
245 tmp = cx_read( VID_CH_MODE_SEL ); 245{
246 cx_write( VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 246 if (dev->_is_running_ch2) {
247} 247 cx25821_stop_upstream_video_ch2(dev);
248 248 }
249void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev) 249
250{ 250 if (dev->_dma_virt_addr_ch2) {
251 if( dev->_is_running_ch2 ) 251 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
252 { 252 dev->_dma_virt_addr_ch2,
253 cx25821_stop_upstream_video_ch2(dev); 253 dev->_dma_phys_addr_ch2);
254 } 254 dev->_dma_virt_addr_ch2 = NULL;
255 255 }
256 if (dev->_dma_virt_addr_ch2) 256
257 { 257 if (dev->_data_buf_virt_addr_ch2) {
258 pci_free_consistent(dev->pci, dev->_risc_size_ch2, dev->_dma_virt_addr_ch2, dev->_dma_phys_addr_ch2); 258 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
259 dev->_dma_virt_addr_ch2 = NULL; 259 dev->_data_buf_virt_addr_ch2,
260 } 260 dev->_data_buf_phys_addr_ch2);
261 261 dev->_data_buf_virt_addr_ch2 = NULL;
262 if (dev->_data_buf_virt_addr_ch2) 262 }
263 { 263}
264 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2, dev->_data_buf_virt_addr_ch2, dev->_data_buf_phys_addr_ch2); 264
265 dev->_data_buf_virt_addr_ch2 = NULL; 265int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
266 } 266{
267} 267 struct file *myfile;
268 268 int frame_index_temp = dev->_frame_index_ch2;
269 269 int i = 0;
270int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch ) 270 int line_size =
271{ 271 (dev->_pixel_format_ch2 ==
272 struct file * myfile; 272 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
273 int frame_index_temp = dev->_frame_index_ch2; 273 int frame_size = 0;
274 int i = 0; 274 int frame_offset = 0;
275 int line_size = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 275 ssize_t vfs_read_retval = 0;
276 int frame_size = 0; 276 char mybuf[line_size];
277 int frame_offset = 0; 277 loff_t file_offset;
278 ssize_t vfs_read_retval = 0; 278 loff_t pos;
279 char mybuf[line_size]; 279 mm_segment_t old_fs;
280 loff_t file_offset; 280
281 loff_t pos; 281 if (dev->_file_status_ch2 == END_OF_FILE)
282 mm_segment_t old_fs; 282 return 0;
283 283
284 284 if (dev->_isNTSC_ch2) {
285 if( dev->_file_status_ch2 == END_OF_FILE ) 285 frame_size =
286 return 0; 286 (line_size ==
287 287 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
288 if( dev->_isNTSC_ch2 ) 288 FRAME_SIZE_NTSC_Y422;
289 { 289 } else {
290 frame_size = (line_size == Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422; 290 frame_size =
291 } 291 (line_size ==
292 else 292 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
293 { 293 }
294 frame_size = (line_size == Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 294
295 } 295 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
296 296 file_offset = dev->_frame_count_ch2 * frame_size;
297 frame_offset = (frame_index_temp > 0) ? frame_size : 0; 297
298 file_offset = dev->_frame_count_ch2 * frame_size; 298 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
299 299
300 300 if (IS_ERR(myfile)) {
301 myfile = filp_open( dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0 ); 301 const int open_errno = -PTR_ERR(myfile);
302 302 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
303 303 __func__, dev->_filename_ch2, open_errno);
304 if (IS_ERR(myfile)) 304 return PTR_ERR(myfile);
305 { 305 } else {
306 const int open_errno = -PTR_ERR(myfile); 306 if (!(myfile->f_op)) {
307 printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_filename_ch2, open_errno); 307 printk("%s: File has no file operations registered!",
308 return PTR_ERR(myfile); 308 __func__);
309 } 309 filp_close(myfile, NULL);
310 else 310 return -EIO;
311 { 311 }
312 if( !(myfile->f_op) ) 312
313 { 313 if (!myfile->f_op->read) {
314 printk("%s: File has no file operations registered!", __func__); 314 printk("%s: File has no READ operations registered!",
315 filp_close(myfile, NULL); 315 __func__);
316 return -EIO; 316 filp_close(myfile, NULL);
317 } 317 return -EIO;
318 318 }
319 319
320 if( !myfile->f_op->read ) 320 pos = myfile->f_pos;
321 { 321 old_fs = get_fs();
322 printk("%s: File has no READ operations registered!", __func__); 322 set_fs(KERNEL_DS);
323 filp_close(myfile, NULL); 323
324 return -EIO; 324 for (i = 0; i < dev->_lines_count_ch2; i++) {
325 } 325 pos = file_offset;
326 326
327 pos = myfile->f_pos; 327 vfs_read_retval =
328 old_fs = get_fs(); 328 vfs_read(myfile, mybuf, line_size, &pos);
329 set_fs(KERNEL_DS); 329
330 330 if (vfs_read_retval > 0 && vfs_read_retval == line_size
331 331 && dev->_data_buf_virt_addr_ch2 != NULL) {
332 for( i = 0; i < dev->_lines_count_ch2; i++ ) 332 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
333 { 333 frame_offset / 4), mybuf,
334 pos = file_offset; 334 vfs_read_retval);
335 335 }
336 vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos); 336
337 337 file_offset += vfs_read_retval;
338 if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_data_buf_virt_addr_ch2 != NULL ) 338 frame_offset += vfs_read_retval;
339 { 339
340 memcpy( (void*)(dev->_data_buf_virt_addr_ch2+frame_offset/4), mybuf, vfs_read_retval); 340 if (vfs_read_retval < line_size) {
341 } 341 printk(KERN_INFO
342 342 "Done: exit %s() since no more bytes to read from Video file.\n",
343 file_offset += vfs_read_retval; 343 __func__);
344 frame_offset += vfs_read_retval; 344 break;
345 345 }
346 if( vfs_read_retval < line_size ) 346 }
347 { 347
348 printk(KERN_INFO "Done: exit %s() since no more bytes to read from Video file.\n", __func__ ); 348 if (i > 0)
349 break; 349 dev->_frame_count_ch2++;
350 } 350
351 } 351 dev->_file_status_ch2 =
352 352 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
353 if( i > 0 ) 353
354 dev->_frame_count_ch2++; 354 set_fs(old_fs);
355 355 filp_close(myfile, NULL);
356 dev->_file_status_ch2 = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 356 }
357 357
358 358 return 0;
359 set_fs(old_fs); 359}
360 filp_close(myfile, NULL); 360
361 } 361static void cx25821_vidups_handler_ch2(struct work_struct *work)
362 362{
363 return 0; 363 struct cx25821_dev *dev =
364} 364 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
365 365
366static void cx25821_vidups_handler_ch2(struct work_struct *work) 366 if (!dev) {
367{ 367 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
368 struct cx25821_dev *dev = container_of(work, struct cx25821_dev, _irq_work_entry_ch2); 368 __func__);
369 369 return;
370 if( !dev ) 370 }
371 { 371
372 printk("ERROR %s(): since container_of(work_struct) FAILED! \n", __func__ ); 372 cx25821_get_frame_ch2(dev,
373 return; 373 &dev->sram_channels[dev->
374 } 374 _channel2_upstream_select]);
375 375}
376 cx25821_get_frame_ch2( dev, &dev->sram_channels[dev->_channel2_upstream_select] ); 376
377} 377int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
378 378{
379 379 struct file *myfile;
380int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch) 380 int i = 0, j = 0;
381{ 381 int line_size =
382 struct file * myfile; 382 (dev->_pixel_format_ch2 ==
383 int i = 0, j = 0; 383 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
384 int line_size = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 384 ssize_t vfs_read_retval = 0;
385 ssize_t vfs_read_retval = 0; 385 char mybuf[line_size];
386 char mybuf[line_size]; 386 loff_t pos;
387 loff_t pos; 387 loff_t offset = (unsigned long)0;
388 loff_t offset = (unsigned long)0; 388 mm_segment_t old_fs;
389 mm_segment_t old_fs; 389
390 390 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
391 391
392 myfile = filp_open( dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0 ); 392 if (IS_ERR(myfile)) {
393 393 const int open_errno = -PTR_ERR(myfile);
394 394 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
395 if (IS_ERR(myfile)) 395 __func__, dev->_filename_ch2, open_errno);
396 { 396 return PTR_ERR(myfile);
397 const int open_errno = -PTR_ERR(myfile); 397 } else {
398 printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_filename_ch2, open_errno); 398 if (!(myfile->f_op)) {
399 return PTR_ERR(myfile); 399 printk("%s: File has no file operations registered!",
400 } 400 __func__);
401 else 401 filp_close(myfile, NULL);
402 { 402 return -EIO;
403 if( !(myfile->f_op) ) 403 }
404 { 404
405 printk("%s: File has no file operations registered!", __func__); 405 if (!myfile->f_op->read) {
406 filp_close(myfile, NULL); 406 printk
407 return -EIO; 407 ("%s: File has no READ operations registered! Returning.",
408 } 408 __func__);
409 409 filp_close(myfile, NULL);
410 410 return -EIO;
411 if( !myfile->f_op->read ) 411 }
412 { 412
413 printk("%s: File has no READ operations registered! Returning.", __func__); 413 pos = myfile->f_pos;
414 filp_close(myfile, NULL); 414 old_fs = get_fs();
415 return -EIO; 415 set_fs(KERNEL_DS);
416 } 416
417 417 for (j = 0; j < NUM_FRAMES; j++) {
418 pos = myfile->f_pos; 418 for (i = 0; i < dev->_lines_count_ch2; i++) {
419 old_fs = get_fs(); 419 pos = offset;
420 set_fs(KERNEL_DS); 420
421 421 vfs_read_retval =
422 422 vfs_read(myfile, mybuf, line_size, &pos);
423 for( j = 0; j < NUM_FRAMES; j++ ) 423
424 { 424 if (vfs_read_retval > 0
425 for( i = 0; i < dev->_lines_count_ch2; i++ ) 425 && vfs_read_retval == line_size
426 { 426 && dev->_data_buf_virt_addr_ch2 != NULL) {
427 pos = offset; 427 memcpy((void *)(dev->
428 428 _data_buf_virt_addr_ch2
429 vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos); 429 + offset / 4), mybuf,
430 430 vfs_read_retval);
431 if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_data_buf_virt_addr_ch2 != NULL ) 431 }
432 { 432
433 memcpy( (void*)(dev->_data_buf_virt_addr_ch2+offset/4), mybuf, vfs_read_retval); 433 offset += vfs_read_retval;
434 } 434
435 435 if (vfs_read_retval < line_size) {
436 436 printk(KERN_INFO
437 offset += vfs_read_retval; 437 "Done: exit %s() since no more bytes to read from Video file.\n",
438 438 __func__);
439 if( vfs_read_retval < line_size ) 439 break;
440 { 440 }
441 printk(KERN_INFO "Done: exit %s() since no more bytes to read from Video file.\n", __func__ ); 441 }
442 break; 442
443 } 443 if (i > 0)
444 } 444 dev->_frame_count_ch2++;
445 445
446 if( i > 0 ) 446 if (vfs_read_retval < line_size) {
447 dev->_frame_count_ch2++; 447 break;
448 448 }
449 if( vfs_read_retval < line_size ) 449 }
450 { 450
451 break; 451 dev->_file_status_ch2 =
452 } 452 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
453 } 453
454 454 set_fs(old_fs);
455 dev->_file_status_ch2 = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 455 myfile->f_pos = 0;
456 456 filp_close(myfile, NULL);
457 set_fs(old_fs); 457 }
458 myfile->f_pos = 0; 458
459 filp_close(myfile, NULL); 459 return 0;
460 } 460}
461 461
462 return 0; 462static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
463} 463 struct sram_channel *sram_ch,
464 464 int bpl)
465 465{
466static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev, 466 int ret = 0;
467 struct sram_channel *sram_ch, 467 dma_addr_t dma_addr;
468 int bpl) 468 dma_addr_t data_dma_addr;
469{ 469
470 int ret = 0; 470 if (dev->_dma_virt_addr_ch2 != NULL) {
471 dma_addr_t dma_addr; 471 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
472 dma_addr_t data_dma_addr; 472 dev->_dma_virt_addr_ch2,
473 473 dev->_dma_phys_addr_ch2);
474 474 }
475 if( dev->_dma_virt_addr_ch2 != NULL ) 475
476 { 476 dev->_dma_virt_addr_ch2 =
477 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2, dev->_dma_virt_addr_ch2, dev->_dma_phys_addr_ch2); 477 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
478 } 478 &dma_addr);
479 479 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
480 dev->_dma_virt_addr_ch2 = pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2, &dma_addr); 480 dev->_dma_phys_start_addr_ch2 = dma_addr;
481 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2; 481 dev->_dma_phys_addr_ch2 = dma_addr;
482 dev->_dma_phys_start_addr_ch2 = dma_addr; 482 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
483 dev->_dma_phys_addr_ch2 = dma_addr; 483
484 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2; 484 if (!dev->_dma_virt_addr_ch2) {
485 485 printk
486 486 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
487 if (!dev->_dma_virt_addr_ch2) 487 return -ENOMEM;
488 { 488 }
489 printk("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n"); 489
490 return -ENOMEM; 490 //Iniitize at this address until n bytes to 0
491 } 491 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
492 492
493 493 if (dev->_data_buf_virt_addr_ch2 != NULL) {
494 //Iniitize at this address until n bytes to 0 494 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
495 memset( dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2 ); 495 dev->_data_buf_virt_addr_ch2,
496 496 dev->_data_buf_phys_addr_ch2);
497 497 }
498 if( dev->_data_buf_virt_addr_ch2 != NULL ) 498 //For Video Data buffer allocation
499 { 499 dev->_data_buf_virt_addr_ch2 =
500 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2, dev->_data_buf_virt_addr_ch2, dev->_data_buf_phys_addr_ch2); 500 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
501 } 501 &data_dma_addr);
502 502 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
503 //For Video Data buffer allocation 503 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
504 dev->_data_buf_virt_addr_ch2 = pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2, &data_dma_addr); 504
505 dev->_data_buf_phys_addr_ch2 = data_dma_addr; 505 if (!dev->_data_buf_virt_addr_ch2) {
506 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2; 506 printk
507 507 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
508 if (!dev->_data_buf_virt_addr_ch2) 508 return -ENOMEM;
509 { 509 }
510 printk("cx25821: FAILED to allocate memory for data buffer! Returning.\n"); 510
511 return -ENOMEM; 511 //Initialize at this address until n bytes to 0
512 } 512 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
513 513
514 514 ret = cx25821_openfile_ch2(dev, sram_ch);
515 //Initialize at this address until n bytes to 0 515 if (ret < 0)
516 memset( dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2 ); 516 return ret;
517 517
518 518 //Creating RISC programs
519 ret = cx25821_openfile_ch2(dev, sram_ch); 519 ret =
520 if( ret < 0 ) 520 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
521 return ret; 521 dev->_lines_count_ch2);
522 522 if (ret < 0) {
523 523 printk(KERN_INFO
524 //Creating RISC programs 524 "cx25821: Failed creating Video Upstream Risc programs! \n");
525 ret = cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl, dev->_lines_count_ch2 ); 525 goto error;
526 if (ret < 0) 526 }
527 { 527
528 printk(KERN_INFO "cx25821: Failed creating Video Upstream Risc programs! \n"); 528 return 0;
529 goto error; 529
530 } 530 error:
531 531 return ret;
532 return 0; 532}
533 533
534error: 534int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
535 return ret; 535 u32 status)
536} 536{
537 537 u32 int_msk_tmp;
538int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num, u32 status) 538 struct sram_channel *channel = &dev->sram_channels[chan_num];
539{ 539 int singlefield_lines = NTSC_FIELD_HEIGHT;
540 u32 int_msk_tmp; 540 int line_size_in_bytes = Y422_LINE_SZ;
541 struct sram_channel *channel = &dev->sram_channels[chan_num]; 541 int odd_risc_prog_size = 0;
542 int singlefield_lines = NTSC_FIELD_HEIGHT; 542 dma_addr_t risc_phys_jump_addr;
543 int line_size_in_bytes = Y422_LINE_SZ; 543 __le32 *rp;
544 int odd_risc_prog_size = 0; 544
545 dma_addr_t risc_phys_jump_addr; 545 if (status & FLD_VID_SRC_RISC1) {
546 __le32 * rp; 546 // We should only process one program per call
547 547 u32 prog_cnt = cx_read(channel->gpcnt);
548 548
549 549 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
550 if (status & FLD_VID_SRC_RISC1) 550 int_msk_tmp = cx_read(channel->int_msk);
551 { 551 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
552 // We should only process one program per call 552 cx_write(channel->int_stat, _intr_msk);
553 u32 prog_cnt = cx_read( channel->gpcnt ); 553
554 554 spin_lock(&dev->slock);
555 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers 555
556 int_msk_tmp = cx_read(channel->int_msk); 556 dev->_frame_index_ch2 = prog_cnt;
557 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); 557
558 cx_write( channel->int_stat, _intr_msk ); 558 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
559 559
560 spin_lock(&dev->slock); 560 if (dev->_is_first_frame_ch2) {
561 561 dev->_is_first_frame_ch2 = 0;
562 dev->_frame_index_ch2 = prog_cnt; 562
563 563 if (dev->_isNTSC_ch2) {
564 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2); 564 singlefield_lines += 1;
565 565 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
566 566 } else {
567 if ( dev->_is_first_frame_ch2 ) 567 singlefield_lines = PAL_FIELD_HEIGHT;
568 { 568 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
569 dev->_is_first_frame_ch2 = 0; 569 }
570 570
571 if( dev->_isNTSC_ch2 ) 571 if (dev->_dma_virt_start_addr_ch2 != NULL) {
572 { 572 line_size_in_bytes =
573 singlefield_lines += 1; 573 (dev->_pixel_format_ch2 ==
574 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE; 574 PIXEL_FRMT_411) ? Y411_LINE_SZ :
575 } 575 Y422_LINE_SZ;
576 else 576 risc_phys_jump_addr =
577 { 577 dev->_dma_phys_start_addr_ch2 +
578 singlefield_lines = PAL_FIELD_HEIGHT; 578 odd_risc_prog_size;
579 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE; 579
580 } 580 rp = cx25821_update_riscprogram_ch2(dev,
581 581 dev->
582 582 _dma_virt_start_addr_ch2,
583 if( dev->_dma_virt_start_addr_ch2 != NULL ) 583 TOP_OFFSET,
584 { 584 line_size_in_bytes,
585 line_size_in_bytes = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 585 0x0,
586 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2 + odd_risc_prog_size; 586 singlefield_lines,
587 587 FIFO_DISABLE,
588 rp = cx25821_update_riscprogram_ch2(dev, dev->_dma_virt_start_addr_ch2, TOP_OFFSET, line_size_in_bytes, 0x0, singlefield_lines, FIFO_DISABLE, ODD_FIELD); 588 ODD_FIELD);
589 589
590 // Jump to Even Risc program of 1st Frame 590 // Jump to Even Risc program of 1st Frame
591 *(rp++) = cpu_to_le32(RISC_JUMP); 591 *(rp++) = cpu_to_le32(RISC_JUMP);
592 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 592 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
593 *(rp++) = cpu_to_le32(0); 593 *(rp++) = cpu_to_le32(0);
594 } 594 }
595 } 595 }
596 596
597 spin_unlock(&dev->slock); 597 spin_unlock(&dev->slock);
598 } 598 }
599 599
600 600 if (dev->_file_status_ch2 == END_OF_FILE) {
601 if( dev->_file_status_ch2 == END_OF_FILE ) 601 printk("cx25821: EOF Channel 2 Framecount = %d\n",
602 { 602 dev->_frame_count_ch2);
603 printk("cx25821: EOF Channel 2 Framecount = %d\n", dev->_frame_count_ch2 ); 603 return -1;
604 return -1; 604 }
605 } 605 //ElSE, set the interrupt mask register, re-enable irq.
606 606 int_msk_tmp = cx_read(channel->int_msk);
607 //ElSE, set the interrupt mask register, re-enable irq. 607 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
608 int_msk_tmp = cx_read( channel->int_msk ); 608
609 cx_write( channel->int_msk, int_msk_tmp |= _intr_msk ); 609 return 0;
610 610}
611 return 0; 611
612} 612static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
613 613{
614static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id) 614 struct cx25821_dev *dev = dev_id;
615{ 615 u32 msk_stat, vid_status;
616 struct cx25821_dev *dev = dev_id; 616 int handled = 0;
617 u32 msk_stat, vid_status; 617 int channel_num = 0;
618 int handled = 0; 618 struct sram_channel *sram_ch;
619 int channel_num = 0; 619
620 struct sram_channel *sram_ch; 620 if (!dev)
621 621 return -1;
622 622
623 if( !dev ) 623 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
624 return -1; 624
625 625 sram_ch = &dev->sram_channels[channel_num];
626 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J; 626
627 627 msk_stat = cx_read(sram_ch->int_mstat);
628 sram_ch = &dev->sram_channels[channel_num]; 628 vid_status = cx_read(sram_ch->int_stat);
629 629
630 msk_stat = cx_read(sram_ch->int_mstat); 630 // Only deal with our interrupt
631 vid_status = cx_read(sram_ch->int_stat); 631 if (vid_status) {
632 632 handled =
633 // Only deal with our interrupt 633 cx25821_video_upstream_irq_ch2(dev, channel_num,
634 if(vid_status) 634 vid_status);
635 { 635 }
636 handled = cx25821_video_upstream_irq_ch2(dev, channel_num, vid_status); 636
637 } 637 if (handled < 0) {
638 638 cx25821_stop_upstream_video_ch2(dev);
639 639 } else {
640 if( handled < 0 ) 640 handled += handled;
641 { 641 }
642 cx25821_stop_upstream_video_ch2(dev); 642
643 } 643 return IRQ_RETVAL(handled);
644 else 644}
645 { 645
646 handled += handled; 646static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
647 } 647 struct sram_channel *ch, int pix_format)
648 648{
649 return IRQ_RETVAL(handled); 649 int width = WIDTH_D1;
650} 650 int height = dev->_lines_count_ch2;
651 651 int num_lines, odd_num_lines;
652 652 u32 value;
653static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev, struct sram_channel *ch, int pix_format) 653 int vip_mode = PIXEL_ENGINE_VIP1;
654{ 654
655 int width = WIDTH_D1; 655 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
656 int height = dev->_lines_count_ch2; 656 value &= 0xFFFFFFEF;
657 int num_lines, odd_num_lines; 657 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
658 u32 value; 658 cx_write(ch->vid_fmt_ctl, value);
659 int vip_mode = PIXEL_ENGINE_VIP1; 659
660 660 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
661 661 cx_write(ch->vid_active_ctl1, width);
662 value = ( (pix_format & 0x3) << 12 ) | ( vip_mode & 0x7 ); 662
663 value &= 0xFFFFFFEF; 663 num_lines = (height / 2) & 0x3FF;
664 value |= dev->_isNTSC_ch2 ? 0 : 0x10; 664 odd_num_lines = num_lines;
665 cx_write( ch->vid_fmt_ctl, value ); 665
666 666 if (dev->_isNTSC_ch2) {
667 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format 667 odd_num_lines += 1;
668 cx_write( ch->vid_active_ctl1, width ); 668 }
669 669
670 num_lines = (height / 2) & 0x3FF; 670 value = (num_lines << 16) | odd_num_lines;
671 odd_num_lines = num_lines; 671
672 672 // set number of active lines in field 0 (top) and field 1 (bottom)
673 if(dev->_isNTSC_ch2) 673 cx_write(ch->vid_active_ctl2, value);
674 { 674
675 odd_num_lines += 1; 675 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
676 } 676}
677 677
678 value = (num_lines << 16) | odd_num_lines; 678int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
679 679 struct sram_channel *sram_ch)
680 // set number of active lines in field 0 (top) and field 1 (bottom) 680{
681 cx_write( ch->vid_active_ctl2, value ); 681 u32 tmp = 0;
682 682 int err = 0;
683 cx_write( ch->vid_cdt_size, VID_CDT_SIZE >> 3 ); 683
684} 684 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
685 685 tmp = cx_read(VID_CH_MODE_SEL);
686 686 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
687int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev, 687
688 struct sram_channel *sram_ch) 688 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
689{ 689 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
690 u32 tmp = 0; 690 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
691 int err = 0; 691
692 692 /* reset counter */
693 693 cx_write(sram_ch->gpcnt_ctl, 3);
694 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C 694
695 tmp = cx_read( VID_CH_MODE_SEL ); 695 // Clear our bits from the interrupt status register.
696 cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); 696 cx_write(sram_ch->int_stat, _intr_msk);
697 697
698 698 //Set the interrupt mask register, enable irq.
699 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds. 699 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
700 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2); 700 tmp = cx_read(sram_ch->int_msk);
701 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ 701 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
702 702
703 /* reset counter */ 703 err =
704 cx_write(sram_ch->gpcnt_ctl, 3); 704 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
705 705 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
706 // Clear our bits from the interrupt status register. 706 if (err < 0) {
707 cx_write( sram_ch->int_stat, _intr_msk ); 707 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
708 708 dev->pci->irq);
709 709 goto fail_irq;
710 //Set the interrupt mask register, enable irq. 710 }
711 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); 711 // Start the DMA engine
712 tmp = cx_read( sram_ch->int_msk ); 712 tmp = cx_read(sram_ch->dma_ctl);
713 cx_write( sram_ch->int_msk, tmp |= _intr_msk ); 713 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
714 714
715 715 dev->_is_running_ch2 = 1;
716 err = request_irq(dev->pci->irq, cx25821_upstream_irq_ch2, IRQF_SHARED | IRQF_DISABLED, dev->name, dev); 716 dev->_is_first_frame_ch2 = 1;
717 if (err < 0) 717
718 { 718 return 0;
719 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, dev->pci->irq); 719
720 goto fail_irq; 720 fail_irq:
721 } 721 cx25821_dev_unregister(dev);
722 722 return err;
723 // Start the DMA engine 723}
724 tmp = cx_read( sram_ch->dma_ctl ); 724
725 cx_set( sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN ); 725int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
726 726 int pixel_format)
727 dev->_is_running_ch2 = 1; 727{
728 dev->_is_first_frame_ch2 = 1; 728 struct sram_channel *sram_ch;
729 729 u32 tmp;
730 return 0; 730 int retval = 0;
731 731 int err = 0;
732 732 int data_frame_size = 0;
733fail_irq: 733 int risc_buffer_size = 0;
734 cx25821_dev_unregister(dev); 734 int str_length = 0;
735 return err; 735
736} 736 if (dev->_is_running_ch2) {
737 737 printk("Video Channel is still running so return!\n");
738 738 return 0;
739int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, int pixel_format) 739 }
740{ 740
741 struct sram_channel *sram_ch; 741 dev->_channel2_upstream_select = channel_select;
742 u32 tmp; 742 sram_ch = &dev->sram_channels[channel_select];
743 int retval = 0; 743
744 int err = 0; 744 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
745 int data_frame_size = 0; 745 dev->_irq_queues_ch2 =
746 int risc_buffer_size = 0; 746 create_singlethread_workqueue("cx25821_workqueue2");
747 int str_length = 0; 747
748 748 if (!dev->_irq_queues_ch2) {
749 if( dev->_is_running_ch2 ) 749 printk
750 { 750 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
751 printk("Video Channel is still running so return!\n"); 751 return -ENOMEM;
752 return 0; 752 }
753 } 753 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
754 754 tmp = cx_read(VID_CH_MODE_SEL);
755 dev->_channel2_upstream_select = channel_select; 755 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
756 sram_ch = &dev->sram_channels[channel_select]; 756
757 757 dev->_is_running_ch2 = 0;
758 758 dev->_frame_count_ch2 = 0;
759 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2); 759 dev->_file_status_ch2 = RESET_STATUS;
760 dev->_irq_queues_ch2 = create_singlethread_workqueue("cx25821_workqueue2"); 760 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
761 761 dev->_pixel_format_ch2 = pixel_format;
762 if(!dev->_irq_queues_ch2) 762 dev->_line_size_ch2 =
763 { 763 (dev->_pixel_format_ch2 ==
764 printk("cx25821: create_singlethread_workqueue() for Video FAILED!\n"); 764 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
765 return -ENOMEM; 765 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
766 } 766 risc_buffer_size =
767 767 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
768 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C 768
769 tmp = cx_read( VID_CH_MODE_SEL ); 769 if (dev->input_filename_ch2) {
770 cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); 770 str_length = strlen(dev->input_filename_ch2);
771 771 dev->_filename_ch2 =
772 772 (char *)kmalloc(str_length + 1, GFP_KERNEL);
773 dev->_is_running_ch2 = 0; 773
774 dev->_frame_count_ch2 = 0; 774 if (!dev->_filename_ch2)
775 dev->_file_status_ch2 = RESET_STATUS; 775 goto error;
776 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576; 776
777 dev->_pixel_format_ch2 = pixel_format; 777 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
778 dev->_line_size_ch2 = (dev->_pixel_format_ch2 == PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 778 str_length + 1);
779 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ; 779 } else {
780 risc_buffer_size = dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE; 780 str_length = strlen(dev->_defaultname_ch2);
781 781 dev->_filename_ch2 =
782 782 (char *)kmalloc(str_length + 1, GFP_KERNEL);
783 if( dev->input_filename_ch2 ) 783
784 { 784 if (!dev->_filename_ch2)
785 str_length = strlen(dev->input_filename_ch2); 785 goto error;
786 dev->_filename_ch2 = (char *) kmalloc(str_length + 1, GFP_KERNEL); 786
787 787 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
788 if( !dev->_filename_ch2 ) 788 str_length + 1);
789 goto error; 789 }
790 790
791 memcpy(dev->_filename_ch2, dev->input_filename_ch2, str_length + 1); 791 //Default if filename is empty string
792 } 792 if (strcmp(dev->input_filename_ch2, "") == 0) {
793 else 793 if (dev->_isNTSC_ch2) {
794 { 794 dev->_filename_ch2 =
795 str_length = strlen(dev->_defaultname_ch2); 795 (dev->_pixel_format_ch2 ==
796 dev->_filename_ch2 = (char *) kmalloc(str_length + 1, GFP_KERNEL); 796 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
797 797 "/root/vidtest.yuv";
798 if( !dev->_filename_ch2 ) 798 } else {
799 goto error; 799 dev->_filename_ch2 =
800 800 (dev->_pixel_format_ch2 ==
801 memcpy(dev->_filename_ch2, dev->_defaultname_ch2, str_length + 1); 801 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
802 } 802 "/root/pal422.yuv";
803 803 }
804 804 }
805 //Default if filename is empty string 805
806 if( strcmp(dev->input_filename_ch2,"") == 0) 806 retval =
807 { 807 cx25821_sram_channel_setup_upstream(dev, sram_ch,
808 if( dev->_isNTSC_ch2 ) 808 dev->_line_size_ch2, 0);
809 { 809
810 dev->_filename_ch2 = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ? "/root/vid411.yuv" : "/root/vidtest.yuv"; 810 /* setup fifo + format */
811 } 811 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
812 else 812
813 { 813 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
814 dev->_filename_ch2 = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ? "/root/pal411.yuv" : "/root/pal422.yuv"; 814 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
815 } 815
816 } 816 //Allocating buffers and prepare RISC program
817 817 retval =
818 818 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
819 retval = cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size_ch2, 0); 819 dev->_line_size_ch2);
820 820 if (retval < 0) {
821 821 printk(KERN_ERR
822 /* setup fifo + format */ 822 "%s: Failed to set up Video upstream buffers!\n",
823 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2); 823 dev->name);
824 824 goto error;
825 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2; 825 }
826 dev->upstream_databuf_size_ch2 = data_frame_size * 2; 826
827 827 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
828 828
829 //Allocating buffers and prepare RISC program 829 return 0;
830 retval = cx25821_upstream_buffer_prepare_ch2(dev, sram_ch, dev->_line_size_ch2); 830
831 if (retval < 0) 831 error:
832 { 832 cx25821_dev_unregister(dev);
833 printk(KERN_ERR "%s: Failed to set up Video upstream buffers!\n", dev->name); 833
834 goto error; 834 return err;
835 } 835}
836
837
838 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
839
840 return 0;
841
842error:
843 cx25821_dev_unregister(dev);
844
845 return err;
846}
847
diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.h b/drivers/staging/cx25821/cx25821-video-upstream-ch2.h
index 02e5b9ba81c4..73feea114c1c 100644
--- a/drivers/staging/cx25821/cx25821-video-upstream-ch2.h
+++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.h
@@ -1,107 +1,101 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/workqueue.h> 24#include <linux/workqueue.h>
25 25
26 26#define OPEN_FILE_1 0
27#define OPEN_FILE_1 0 27#define NUM_PROGS 8
28#define NUM_PROGS 8 28#define NUM_FRAMES 2
29#define NUM_FRAMES 2 29#define ODD_FIELD 0
30#define ODD_FIELD 0 30#define EVEN_FIELD 1
31#define EVEN_FIELD 1 31#define TOP_OFFSET 0
32#define TOP_OFFSET 0 32#define FIFO_DISABLE 0
33#define FIFO_DISABLE 0 33#define FIFO_ENABLE 1
34#define FIFO_ENABLE 1 34#define TEST_FRAMES 5
35#define TEST_FRAMES 5 35#define END_OF_FILE 0
36#define END_OF_FILE 0 36#define IN_PROGRESS 1
37#define IN_PROGRESS 1 37#define RESET_STATUS -1
38#define RESET_STATUS -1 38#define NUM_NO_OPS 5
39#define NUM_NO_OPS 5 39
40 40// PAL and NTSC line sizes and number of lines.
41 41#define WIDTH_D1 720
42 42#define NTSC_LINES_PER_FRAME 480
43// PAL and NTSC line sizes and number of lines. 43#define PAL_LINES_PER_FRAME 576
44#define WIDTH_D1 720 44#define PAL_LINE_SZ 1440
45#define NTSC_LINES_PER_FRAME 480 45#define Y422_LINE_SZ 1440
46#define PAL_LINES_PER_FRAME 576 46#define Y411_LINE_SZ 1080
47#define PAL_LINE_SZ 1440 47#define NTSC_FIELD_HEIGHT 240
48#define Y422_LINE_SZ 1440 48#define NTSC_ODD_FLD_LINES 241
49#define Y411_LINE_SZ 1080 49#define PAL_FIELD_HEIGHT 288
50#define NTSC_FIELD_HEIGHT 240 50
51#define NTSC_ODD_FLD_LINES 241 51#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ)
52#define PAL_FIELD_HEIGHT 288 52#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ)
53 53#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ)
54#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ) 54#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ)
55#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ) 55
56#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ) 56#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME)
57#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ) 57#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME)
58 58
59#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME) 59#define RISC_WRITECR_INSTRUCTION_SIZE 16
60#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME) 60#define RISC_SYNC_INSTRUCTION_SIZE 4
61 61#define JUMP_INSTRUCTION_SIZE 12
62#define RISC_WRITECR_INSTRUCTION_SIZE 16 62#define MAXSIZE_NO_OPS 36
63#define RISC_SYNC_INSTRUCTION_SIZE 4 63#define DWORD_SIZE 4
64#define JUMP_INSTRUCTION_SIZE 12 64
65#define MAXSIZE_NO_OPS 36 65#define USE_RISC_NOOP_VIDEO 1
66#define DWORD_SIZE 4 66
67 67#ifdef USE_RISC_NOOP_VIDEO
68 68#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
69 69 RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
70#define USE_RISC_NOOP_VIDEO 1 70
71 71#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE)
72#ifdef USE_RISC_NOOP_VIDEO 72
73#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ 73#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
74 RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 74 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
75 75
76#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE) 76#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
77 77 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
78#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ 78
79 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) 79#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
80 80 JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
81#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ 81
82 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 82#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE))
83 83
84#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ 84#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
85 JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 85 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
86 86#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
87#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE)) 87 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
88 88#endif
89#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ 89
90 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) 90#ifndef USE_RISC_NOOP_VIDEO
91#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ 91#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE )
92 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 92#define PAL_RISC_BUF_SIZE ( 2 * (RISC_SYNC_INSTRUCTION_SIZE + PAL_US_VID_PROG_SIZE) )
93#endif 93#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
94 94 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE )
95 95#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE )
96#ifndef USE_RISC_NOOP_VIDEO 96#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE )
97#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) 97#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
98#define PAL_RISC_BUF_SIZE ( 2 * (RISC_SYNC_INSTRUCTION_SIZE + PAL_US_VID_PROG_SIZE) ) 98#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE) )
99#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ 99#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
100 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE ) 100 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE )
101#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) 101#endif
102#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE )
103#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
104#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE) )
105#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
106 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE )
107#endif
diff --git a/drivers/staging/cx25821/cx25821-video-upstream.c b/drivers/staging/cx25821/cx25821-video-upstream.c
index 0f7a6c5bb1c0..3d7dd3f66541 100644
--- a/drivers/staging/cx25821/cx25821-video-upstream.c
+++ b/drivers/staging/cx25821/cx25821-video-upstream.c
@@ -1,923 +1,894 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23 23#include "cx25821-video.h"
24#include "cx25821-video.h" 24#include "cx25821-video-upstream.h"
25#include "cx25821-video-upstream.h" 25
26 26#include <linux/fs.h>
27#include <linux/fs.h> 27#include <linux/errno.h>
28#include <linux/errno.h> 28#include <linux/kernel.h>
29#include <linux/kernel.h> 29#include <linux/init.h>
30#include <linux/init.h> 30#include <linux/module.h>
31#include <linux/module.h> 31#include <linux/syscalls.h>
32#include <linux/syscalls.h> 32#include <linux/file.h>
33#include <linux/file.h> 33#include <linux/fcntl.h>
34#include <linux/fcntl.h> 34#include <asm/uaccess.h>
35#include <asm/uaccess.h> 35
36 36MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
37 37MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
38MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); 38MODULE_LICENSE("GPL");
39MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); 39
40MODULE_LICENSE("GPL"); 40static int _intr_msk =
41 41 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
42 42
43static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR; 43int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
44 44 struct sram_channel *ch,
45int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev, 45 unsigned int bpl, u32 risc)
46 struct sram_channel *ch, 46{
47 unsigned int bpl, u32 risc) 47 unsigned int i, lines;
48{ 48 u32 cdt;
49 unsigned int i, lines; 49
50 u32 cdt; 50 if (ch->cmds_start == 0) {
51 51 cx_write(ch->ptr1_reg, 0);
52 52 cx_write(ch->ptr2_reg, 0);
53 if (ch->cmds_start == 0) { 53 cx_write(ch->cnt2_reg, 0);
54 cx_write(ch->ptr1_reg, 0); 54 cx_write(ch->cnt1_reg, 0);
55 cx_write(ch->ptr2_reg, 0); 55 return 0;
56 cx_write(ch->cnt2_reg, 0); 56 }
57 cx_write(ch->cnt1_reg, 0); 57
58 return 0; 58 bpl = (bpl + 7) & ~7; /* alignment */
59 } 59 cdt = ch->cdt;
60 60 lines = ch->fifo_size / bpl;
61 bpl = (bpl + 7) & ~7; /* alignment */ 61
62 cdt = ch->cdt; 62 if (lines > 4) {
63 lines = ch->fifo_size / bpl; 63 lines = 4;
64 64 }
65 if (lines > 4) 65
66 { 66 BUG_ON(lines < 2);
67 lines = 4; 67
68 } 68 /* write CDT */
69 69 for (i = 0; i < lines; i++) {
70 BUG_ON(lines < 2); 70 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
71 71 cx_write(cdt + 16 * i + 4, 0);
72 72 cx_write(cdt + 16 * i + 8, 0);
73 /* write CDT */ 73 cx_write(cdt + 16 * i + 12, 0);
74 for (i = 0; i < lines; i++) { 74 }
75 cx_write(cdt + 16*i, ch->fifo_start + bpl*i); 75
76 cx_write(cdt + 16*i + 4, 0); 76 /* write CMDS */
77 cx_write(cdt + 16*i + 8, 0); 77 cx_write(ch->cmds_start + 0, risc);
78 cx_write(cdt + 16*i + 12, 0); 78
79 } 79 cx_write(ch->cmds_start + 4, 0);
80 80 cx_write(ch->cmds_start + 8, cdt);
81 /* write CMDS */ 81 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
82 cx_write(ch->cmds_start + 0, risc); 82 cx_write(ch->cmds_start + 16, ch->ctrl_start);
83 83
84 cx_write(ch->cmds_start + 4, 0); 84 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
85 cx_write(ch->cmds_start + 8, cdt); 85
86 cx_write(ch->cmds_start + 12, (lines*16) >> 3); 86 for (i = 24; i < 80; i += 4)
87 cx_write(ch->cmds_start + 16, ch->ctrl_start); 87 cx_write(ch->cmds_start + i, 0);
88 88
89 89 /* fill registers */
90 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW); 90 cx_write(ch->ptr1_reg, ch->fifo_start);
91 91 cx_write(ch->ptr2_reg, cdt);
92 for (i = 24; i < 80; i += 4) 92 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
93 cx_write(ch->cmds_start + i, 0); 93 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
94 94
95 /* fill registers */ 95 return 0;
96 cx_write(ch->ptr1_reg, ch->fifo_start); 96}
97 cx_write(ch->ptr2_reg, cdt); 97
98 cx_write(ch->cnt2_reg, (lines*16) >> 3); 98static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
99 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 99 __le32 * rp, unsigned int offset,
100 100 unsigned int bpl, u32 sync_line,
101 return 0; 101 unsigned int lines, int fifo_enable,
102} 102 int field_type)
103 103{
104static __le32 *cx25821_update_riscprogram( struct cx25821_dev *dev, 104 unsigned int line, i;
105 __le32 *rp, unsigned int offset, unsigned int bpl, 105 int dist_betwn_starts = bpl * 2;
106 u32 sync_line, unsigned int lines, int fifo_enable, int field_type) 106
107{ 107 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
108 unsigned int line, i; 108
109 int dist_betwn_starts = bpl * 2; 109 if (USE_RISC_NOOP_VIDEO) {
110 110 for (i = 0; i < NUM_NO_OPS; i++) {
111 111 *(rp++) = cpu_to_le32(RISC_NOOP);
112 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 112 }
113 113 }
114 114
115 if( USE_RISC_NOOP_VIDEO ) 115 /* scan lines */
116 { 116 for (line = 0; line < lines; line++) {
117 for( i = 0; i < NUM_NO_OPS; i++ ) 117 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
118 { 118 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
119 *(rp++) = cpu_to_le32(RISC_NOOP); 119 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
120 } 120
121 } 121 if ((lines <= NTSC_FIELD_HEIGHT)
122 122 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
123 /* scan lines */ 123 offset += dist_betwn_starts;
124 for (line = 0; line < lines; line++) 124 }
125 { 125 }
126 *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl); 126
127 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr+offset); 127 return rp;
128 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 128}
129 129
130 if ( (lines <= NTSC_FIELD_HEIGHT) || (line < (NTSC_FIELD_HEIGHT-1)) || !(dev->_isNTSC) ) 130static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
131 { 131 dma_addr_t databuf_phys_addr,
132 offset += dist_betwn_starts; 132 unsigned int offset, u32 sync_line,
133 } 133 unsigned int bpl, unsigned int lines,
134 } 134 int fifo_enable, int field_type)
135 135{
136 return rp; 136 unsigned int line, i;
137} 137 struct sram_channel *sram_ch =
138 138 &dev->sram_channels[dev->_channel_upstream_select];
139static __le32 *cx25821_risc_field_upstream( struct cx25821_dev *dev, __le32 *rp, 139 int dist_betwn_starts = bpl * 2;
140 dma_addr_t databuf_phys_addr, 140
141 unsigned int offset, u32 sync_line, 141 /* sync instruction */
142 unsigned int bpl, unsigned int lines, int fifo_enable, int field_type) 142 if (sync_line != NO_SYNC_LINE) {
143{ 143 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
144 unsigned int line, i; 144 }
145 struct sram_channel *sram_ch = &dev->sram_channels[dev->_channel_upstream_select]; 145
146 int dist_betwn_starts = bpl * 2; 146 if (USE_RISC_NOOP_VIDEO) {
147 147 for (i = 0; i < NUM_NO_OPS; i++) {
148 148 *(rp++) = cpu_to_le32(RISC_NOOP);
149 /* sync instruction */ 149 }
150 if (sync_line != NO_SYNC_LINE) 150 }
151 { 151
152 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 152 /* scan lines */
153 } 153 for (line = 0; line < lines; line++) {
154 154 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
155 155 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
156 if( USE_RISC_NOOP_VIDEO ) 156 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
157 { 157
158 for( i = 0; i < NUM_NO_OPS; i++ ) 158 if ((lines <= NTSC_FIELD_HEIGHT)
159 { 159 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
160 *(rp++) = cpu_to_le32(RISC_NOOP); 160 offset += dist_betwn_starts; //to skip the other field line
161 } 161 }
162 } 162
163 163 // check if we need to enable the FIFO after the first 4 lines
164 /* scan lines */ 164 // For the upstream video channel, the risc engine will enable the FIFO.
165 for (line = 0; line < lines; line++) 165 if (fifo_enable && line == 3) {
166 { 166 *(rp++) = RISC_WRITECR;
167 *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl); 167 *(rp++) = sram_ch->dma_ctl;
168 *(rp++) = cpu_to_le32(databuf_phys_addr+offset); 168 *(rp++) = FLD_VID_FIFO_EN;
169 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 169 *(rp++) = 0x00000001;
170 170 }
171 171 }
172 if ( (lines <= NTSC_FIELD_HEIGHT) || (line < (NTSC_FIELD_HEIGHT-1)) || !(dev->_isNTSC) ) 172
173 { 173 return rp;
174 offset += dist_betwn_starts; //to skip the other field line 174}
175 } 175
176 176int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
177 177 struct pci_dev *pci,
178 // check if we need to enable the FIFO after the first 4 lines 178 unsigned int top_offset,
179 // For the upstream video channel, the risc engine will enable the FIFO. 179 unsigned int bpl, unsigned int lines)
180 if ( fifo_enable && line == 3 ) 180{
181 { 181 __le32 *rp;
182 *(rp++) = RISC_WRITECR; 182 int fifo_enable = 0;
183 *(rp++) = sram_ch->dma_ctl; 183 int singlefield_lines = lines >> 1; //get line count for single field
184 *(rp++) = FLD_VID_FIFO_EN; 184 int odd_num_lines = singlefield_lines;
185 *(rp++) = 0x00000001; 185 int frame = 0;
186 } 186 int frame_size = 0;
187 } 187 int databuf_offset = 0;
188 188 int risc_program_size = 0;
189 return rp; 189 int risc_flag = RISC_CNT_RESET;
190} 190 unsigned int bottom_offset = bpl;
191 191 dma_addr_t risc_phys_jump_addr;
192int cx25821_risc_buffer_upstream( struct cx25821_dev *dev, 192
193 struct pci_dev *pci, 193 if (dev->_isNTSC) {
194 unsigned int top_offset, 194 odd_num_lines = singlefield_lines + 1;
195 unsigned int bpl, unsigned int lines) 195 risc_program_size = FRAME1_VID_PROG_SIZE;
196{ 196 frame_size =
197 __le32 *rp; 197 (bpl ==
198 int fifo_enable = 0; 198 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
199 int singlefield_lines = lines >> 1; //get line count for single field 199 FRAME_SIZE_NTSC_Y422;
200 int odd_num_lines = singlefield_lines; 200 } else {
201 int frame = 0; 201 risc_program_size = PAL_VID_PROG_SIZE;
202 int frame_size = 0; 202 frame_size =
203 int databuf_offset = 0; 203 (bpl ==
204 int risc_program_size = 0; 204 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
205 int risc_flag = RISC_CNT_RESET; 205 }
206 unsigned int bottom_offset = bpl; 206
207 dma_addr_t risc_phys_jump_addr; 207 /* Virtual address of Risc buffer program */
208 208 rp = dev->_dma_virt_addr;
209 if( dev->_isNTSC ) 209
210 { 210 for (frame = 0; frame < NUM_FRAMES; frame++) {
211 odd_num_lines = singlefield_lines + 1; 211 databuf_offset = frame_size * frame;
212 risc_program_size = FRAME1_VID_PROG_SIZE; 212
213 frame_size = (bpl == Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422; 213 if (UNSET != top_offset) {
214 } 214 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
215 else 215 rp = cx25821_risc_field_upstream(dev, rp,
216 { 216 dev->
217 risc_program_size = PAL_VID_PROG_SIZE; 217 _data_buf_phys_addr +
218 frame_size = (bpl == Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 218 databuf_offset,
219 } 219 top_offset, 0, bpl,
220 220 odd_num_lines,
221 221 fifo_enable,
222 /* Virtual address of Risc buffer program */ 222 ODD_FIELD);
223 rp = dev->_dma_virt_addr; 223 }
224 224
225 for( frame = 0; frame < NUM_FRAMES; frame++ ) 225 fifo_enable = FIFO_DISABLE;
226 { 226
227 databuf_offset = frame_size * frame; 227 //Even Field
228 228 rp = cx25821_risc_field_upstream(dev, rp,
229 if (UNSET != top_offset) 229 dev->_data_buf_phys_addr +
230 { 230 databuf_offset, bottom_offset,
231 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE; 231 0x200, bpl, singlefield_lines,
232 rp = cx25821_risc_field_upstream(dev, rp, dev->_data_buf_phys_addr+databuf_offset, top_offset, 0, bpl, odd_num_lines, fifo_enable, ODD_FIELD); 232 fifo_enable, EVEN_FIELD);
233 } 233
234 234 if (frame == 0) {
235 235 risc_flag = RISC_CNT_RESET;
236 fifo_enable = FIFO_DISABLE; 236 risc_phys_jump_addr =
237 237 dev->_dma_phys_start_addr + risc_program_size;
238 238 } else {
239 //Even Field 239 risc_phys_jump_addr = dev->_dma_phys_start_addr;
240 rp = cx25821_risc_field_upstream(dev, rp, dev->_data_buf_phys_addr+databuf_offset, bottom_offset, 0x200, bpl, singlefield_lines, fifo_enable, EVEN_FIELD); 240 risc_flag = RISC_CNT_INC;
241 241 }
242 242
243 if( frame == 0 ) 243 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
244 { 244 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
245 risc_flag = RISC_CNT_RESET; 245 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
246 risc_phys_jump_addr = dev->_dma_phys_start_addr + risc_program_size; 246 *(rp++) = cpu_to_le32(0);
247 } 247 }
248 else 248
249 { 249 return 0;
250 risc_phys_jump_addr = dev->_dma_phys_start_addr; 250}
251 risc_flag = RISC_CNT_INC; 251
252 } 252void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
253 253{
254 254 struct sram_channel *sram_ch =
255 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ 255 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I];
256 *(rp++) = cpu_to_le32(RISC_JUMP|RISC_IRQ1|risc_flag); 256 u32 tmp = 0;
257 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 257
258 *(rp++) = cpu_to_le32(0); 258 if (!dev->_is_running) {
259 } 259 printk
260 260 ("cx25821: No video file is currently running so return!\n");
261 return 0; 261 return;
262} 262 }
263 263 //Disable RISC interrupts
264 264 tmp = cx_read(sram_ch->int_msk);
265void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev) 265 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
266{ 266
267 struct sram_channel *sram_ch = &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I]; 267 //Turn OFF risc and fifo enable
268 u32 tmp = 0; 268 tmp = cx_read(sram_ch->dma_ctl);
269 269 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
270 if( !dev->_is_running ) 270
271 { 271 //Clear data buffer memory
272 printk("cx25821: No video file is currently running so return!\n"); 272 if (dev->_data_buf_virt_addr)
273 return; 273 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
274 } 274
275 275 dev->_is_running = 0;
276 //Disable RISC interrupts 276 dev->_is_first_frame = 0;
277 tmp = cx_read( sram_ch->int_msk ); 277 dev->_frame_count = 0;
278 cx_write( sram_ch->int_msk, tmp & ~_intr_msk); 278 dev->_file_status = END_OF_FILE;
279 279
280 //Turn OFF risc and fifo enable 280 if (dev->_irq_queues) {
281 tmp = cx_read( sram_ch->dma_ctl ); 281 kfree(dev->_irq_queues);
282 cx_write( sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN) ); 282 dev->_irq_queues = NULL;
283 283 }
284 //Clear data buffer memory 284
285 if( dev->_data_buf_virt_addr ) 285 if (dev->_filename != NULL)
286 memset( dev->_data_buf_virt_addr, 0, dev->_data_buf_size ); 286 kfree(dev->_filename);
287 287
288 dev->_is_running = 0; 288 tmp = cx_read(VID_CH_MODE_SEL);
289 dev->_is_first_frame = 0; 289 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
290 dev->_frame_count = 0; 290}
291 dev->_file_status = END_OF_FILE; 291
292 292void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
293 if( dev->_irq_queues ) 293{
294 { 294 if (dev->_is_running) {
295 kfree(dev->_irq_queues); 295 cx25821_stop_upstream_video_ch1(dev);
296 dev->_irq_queues = NULL; 296 }
297 } 297
298 298 if (dev->_dma_virt_addr) {
299 if( dev->_filename != NULL ) 299 pci_free_consistent(dev->pci, dev->_risc_size,
300 kfree(dev->_filename); 300 dev->_dma_virt_addr, dev->_dma_phys_addr);
301 301 dev->_dma_virt_addr = NULL;
302 tmp = cx_read( VID_CH_MODE_SEL ); 302 }
303 cx_write( VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 303
304} 304 if (dev->_data_buf_virt_addr) {
305 305 pci_free_consistent(dev->pci, dev->_data_buf_size,
306void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev) 306 dev->_data_buf_virt_addr,
307{ 307 dev->_data_buf_phys_addr);
308 if( dev->_is_running ) 308 dev->_data_buf_virt_addr = NULL;
309 { 309 }
310 cx25821_stop_upstream_video_ch1(dev); 310}
311 } 311
312 312int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
313 if (dev->_dma_virt_addr) 313{
314 { 314 struct file *myfile;
315 pci_free_consistent(dev->pci, dev->_risc_size, dev->_dma_virt_addr, dev->_dma_phys_addr); 315 int frame_index_temp = dev->_frame_index;
316 dev->_dma_virt_addr = NULL; 316 int i = 0;
317 } 317 int line_size =
318 318 (dev->_pixel_format ==
319 if (dev->_data_buf_virt_addr) 319 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
320 { 320 int frame_size = 0;
321 pci_free_consistent(dev->pci, dev->_data_buf_size, dev->_data_buf_virt_addr, dev->_data_buf_phys_addr); 321 int frame_offset = 0;
322 dev->_data_buf_virt_addr = NULL; 322 ssize_t vfs_read_retval = 0;
323 } 323 char mybuf[line_size];
324} 324 loff_t file_offset;
325 325 loff_t pos;
326 326 mm_segment_t old_fs;
327int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch ) 327
328{ 328 if (dev->_file_status == END_OF_FILE)
329 struct file * myfile; 329 return 0;
330 int frame_index_temp = dev->_frame_index; 330
331 int i = 0; 331 if (dev->_isNTSC) {
332 int line_size = (dev->_pixel_format == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 332 frame_size =
333 int frame_size = 0; 333 (line_size ==
334 int frame_offset = 0; 334 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
335 ssize_t vfs_read_retval = 0; 335 FRAME_SIZE_NTSC_Y422;
336 char mybuf[line_size]; 336 } else {
337 loff_t file_offset; 337 frame_size =
338 loff_t pos; 338 (line_size ==
339 mm_segment_t old_fs; 339 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
340 340 }
341 341
342 if( dev->_file_status == END_OF_FILE ) 342 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
343 return 0; 343 file_offset = dev->_frame_count * frame_size;
344 344
345 if( dev->_isNTSC ) 345 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
346 { 346
347 frame_size = (line_size == Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422; 347 if (IS_ERR(myfile)) {
348 } 348 const int open_errno = -PTR_ERR(myfile);
349 else 349 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
350 { 350 __func__, dev->_filename, open_errno);
351 frame_size = (line_size == Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 351 return PTR_ERR(myfile);
352 } 352 } else {
353 353 if (!(myfile->f_op)) {
354 frame_offset = (frame_index_temp > 0) ? frame_size : 0; 354 printk("%s: File has no file operations registered!",
355 file_offset = dev->_frame_count * frame_size; 355 __func__);
356 356 filp_close(myfile, NULL);
357 357 return -EIO;
358 myfile = filp_open( dev->_filename, O_RDONLY | O_LARGEFILE, 0 ); 358 }
359 359
360 360 if (!myfile->f_op->read) {
361 if (IS_ERR(myfile)) 361 printk("%s: File has no READ operations registered!",
362 { 362 __func__);
363 const int open_errno = -PTR_ERR(myfile); 363 filp_close(myfile, NULL);
364 printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_filename, open_errno); 364 return -EIO;
365 return PTR_ERR(myfile); 365 }
366 } 366
367 else 367 pos = myfile->f_pos;
368 { 368 old_fs = get_fs();
369 if( !(myfile->f_op) ) 369 set_fs(KERNEL_DS);
370 { 370
371 printk("%s: File has no file operations registered!", __func__); 371 for (i = 0; i < dev->_lines_count; i++) {
372 filp_close(myfile, NULL); 372 pos = file_offset;
373 return -EIO; 373
374 } 374 vfs_read_retval =
375 375 vfs_read(myfile, mybuf, line_size, &pos);
376 376
377 if( !myfile->f_op->read ) 377 if (vfs_read_retval > 0 && vfs_read_retval == line_size
378 { 378 && dev->_data_buf_virt_addr != NULL) {
379 printk("%s: File has no READ operations registered!", __func__); 379 memcpy((void *)(dev->_data_buf_virt_addr +
380 filp_close(myfile, NULL); 380 frame_offset / 4), mybuf,
381 return -EIO; 381 vfs_read_retval);
382 } 382 }
383 383
384 pos = myfile->f_pos; 384 file_offset += vfs_read_retval;
385 old_fs = get_fs(); 385 frame_offset += vfs_read_retval;
386 set_fs(KERNEL_DS); 386
387 387 if (vfs_read_retval < line_size) {
388 388 printk(KERN_INFO
389 for( i = 0; i < dev->_lines_count; i++ ) 389 "Done: exit %s() since no more bytes to read from Video file.\n",
390 { 390 __func__);
391 pos = file_offset; 391 break;
392 392 }
393 vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos); 393 }
394 394
395 if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_data_buf_virt_addr != NULL ) 395 if (i > 0)
396 { 396 dev->_frame_count++;
397 memcpy( (void*)(dev->_data_buf_virt_addr+frame_offset/4), mybuf, vfs_read_retval); 397
398 } 398 dev->_file_status =
399 399 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
400 file_offset += vfs_read_retval; 400
401 frame_offset += vfs_read_retval; 401 set_fs(old_fs);
402 402 filp_close(myfile, NULL);
403 if( vfs_read_retval < line_size ) 403 }
404 { 404
405 printk(KERN_INFO "Done: exit %s() since no more bytes to read from Video file.\n", __func__ ); 405 return 0;
406 break; 406}
407 } 407
408 } 408static void cx25821_vidups_handler(struct work_struct *work)
409 409{
410 if( i > 0 ) 410 struct cx25821_dev *dev =
411 dev->_frame_count++; 411 container_of(work, struct cx25821_dev, _irq_work_entry);
412 412
413 dev->_file_status = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 413 if (!dev) {
414 414 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
415 415 __func__);
416 set_fs(old_fs); 416 return;
417 filp_close(myfile, NULL); 417 }
418 } 418
419 419 cx25821_get_frame(dev,
420 return 0; 420 &dev->sram_channels[dev->_channel_upstream_select]);
421} 421}
422 422
423static void cx25821_vidups_handler(struct work_struct *work) 423int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
424{ 424{
425 struct cx25821_dev *dev = container_of(work, struct cx25821_dev, _irq_work_entry); 425 struct file *myfile;
426 426 int i = 0, j = 0;
427 if( !dev ) 427 int line_size =
428 { 428 (dev->_pixel_format ==
429 printk("ERROR %s(): since container_of(work_struct) FAILED! \n", __func__ ); 429 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
430 return; 430 ssize_t vfs_read_retval = 0;
431 } 431 char mybuf[line_size];
432 432 loff_t pos;
433 cx25821_get_frame( dev, &dev->sram_channels[dev->_channel_upstream_select] ); 433 loff_t offset = (unsigned long)0;
434} 434 mm_segment_t old_fs;
435 435
436 436 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
437int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch) 437
438{ 438 if (IS_ERR(myfile)) {
439 struct file * myfile; 439 const int open_errno = -PTR_ERR(myfile);
440 int i = 0, j = 0; 440 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
441 int line_size = (dev->_pixel_format == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 441 __func__, dev->_filename, open_errno);
442 ssize_t vfs_read_retval = 0; 442 return PTR_ERR(myfile);
443 char mybuf[line_size]; 443 } else {
444 loff_t pos; 444 if (!(myfile->f_op)) {
445 loff_t offset = (unsigned long)0; 445 printk("%s: File has no file operations registered!",
446 mm_segment_t old_fs; 446 __func__);
447 447 filp_close(myfile, NULL);
448 448 return -EIO;
449 myfile = filp_open( dev->_filename, O_RDONLY | O_LARGEFILE, 0 ); 449 }
450 450
451 451 if (!myfile->f_op->read) {
452 if (IS_ERR(myfile)) 452 printk
453 { 453 ("%s: File has no READ operations registered! Returning.",
454 const int open_errno = -PTR_ERR(myfile); 454 __func__);
455 printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_filename, open_errno); 455 filp_close(myfile, NULL);
456 return PTR_ERR(myfile); 456 return -EIO;
457 } 457 }
458 else 458
459 { 459 pos = myfile->f_pos;
460 if( !(myfile->f_op) ) 460 old_fs = get_fs();
461 { 461 set_fs(KERNEL_DS);
462 printk("%s: File has no file operations registered!", __func__); 462
463 filp_close(myfile, NULL); 463 for (j = 0; j < NUM_FRAMES; j++) {
464 return -EIO; 464 for (i = 0; i < dev->_lines_count; i++) {
465 } 465 pos = offset;
466 466
467 467 vfs_read_retval =
468 if( !myfile->f_op->read ) 468 vfs_read(myfile, mybuf, line_size, &pos);
469 { 469
470 printk("%s: File has no READ operations registered! Returning.", __func__); 470 if (vfs_read_retval > 0
471 filp_close(myfile, NULL); 471 && vfs_read_retval == line_size
472 return -EIO; 472 && dev->_data_buf_virt_addr != NULL) {
473 } 473 memcpy((void *)(dev->
474 474 _data_buf_virt_addr +
475 pos = myfile->f_pos; 475 offset / 4), mybuf,
476 old_fs = get_fs(); 476 vfs_read_retval);
477 set_fs(KERNEL_DS); 477 }
478 478
479 479 offset += vfs_read_retval;
480 for( j = 0; j < NUM_FRAMES; j++ ) 480
481 { 481 if (vfs_read_retval < line_size) {
482 for( i = 0; i < dev->_lines_count; i++ ) 482 printk(KERN_INFO
483 { 483 "Done: exit %s() since no more bytes to read from Video file.\n",
484 pos = offset; 484 __func__);
485 485 break;
486 vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos); 486 }
487 487 }
488 if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_data_buf_virt_addr != NULL ) 488
489 { 489 if (i > 0)
490 memcpy( (void*)(dev->_data_buf_virt_addr+offset/4), mybuf, vfs_read_retval); 490 dev->_frame_count++;
491 } 491
492 492 if (vfs_read_retval < line_size) {
493 493 break;
494 offset += vfs_read_retval; 494 }
495 495 }
496 if( vfs_read_retval < line_size ) 496
497 { 497 dev->_file_status =
498 printk(KERN_INFO "Done: exit %s() since no more bytes to read from Video file.\n", __func__ ); 498 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
499 break; 499
500 } 500 set_fs(old_fs);
501 } 501 myfile->f_pos = 0;
502 502 filp_close(myfile, NULL);
503 if( i > 0 ) 503 }
504 dev->_frame_count++; 504
505 505 return 0;
506 if( vfs_read_retval < line_size ) 506}
507 { 507
508 break; 508int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
509 } 509 struct sram_channel *sram_ch, int bpl)
510 } 510{
511 511 int ret = 0;
512 512 dma_addr_t dma_addr;
513 dev->_file_status = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 513 dma_addr_t data_dma_addr;
514 514
515 set_fs(old_fs); 515 if (dev->_dma_virt_addr != NULL) {
516 myfile->f_pos = 0; 516 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
517 filp_close(myfile, NULL); 517 dev->_dma_virt_addr, dev->_dma_phys_addr);
518 } 518 }
519 519
520 return 0; 520 dev->_dma_virt_addr =
521} 521 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
522 522 &dma_addr);
523 523 dev->_dma_virt_start_addr = dev->_dma_virt_addr;
524int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev, 524 dev->_dma_phys_start_addr = dma_addr;
525 struct sram_channel *sram_ch, 525 dev->_dma_phys_addr = dma_addr;
526 int bpl) 526 dev->_risc_size = dev->upstream_riscbuf_size;
527{ 527
528 int ret = 0; 528 if (!dev->_dma_virt_addr) {
529 dma_addr_t dma_addr; 529 printk
530 dma_addr_t data_dma_addr; 530 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
531 531 return -ENOMEM;
532 if( dev->_dma_virt_addr != NULL ) 532 }
533 { 533
534 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size, dev->_dma_virt_addr, dev->_dma_phys_addr); 534 //Clear memory at address
535 } 535 memset(dev->_dma_virt_addr, 0, dev->_risc_size);
536 536
537 537 if (dev->_data_buf_virt_addr != NULL) {
538 dev->_dma_virt_addr = pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size, &dma_addr); 538 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
539 dev->_dma_virt_start_addr = dev->_dma_virt_addr; 539 dev->_data_buf_virt_addr,
540 dev->_dma_phys_start_addr = dma_addr; 540 dev->_data_buf_phys_addr);
541 dev->_dma_phys_addr = dma_addr; 541 }
542 dev->_risc_size = dev->upstream_riscbuf_size; 542 //For Video Data buffer allocation
543 543 dev->_data_buf_virt_addr =
544 544 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
545 if (!dev->_dma_virt_addr) 545 &data_dma_addr);
546 { 546 dev->_data_buf_phys_addr = data_dma_addr;
547 printk("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n"); 547 dev->_data_buf_size = dev->upstream_databuf_size;
548 return -ENOMEM; 548
549 } 549 if (!dev->_data_buf_virt_addr) {
550 550 printk
551 551 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
552 //Clear memory at address 552 return -ENOMEM;
553 memset( dev->_dma_virt_addr, 0, dev->_risc_size ); 553 }
554 554
555 555 //Clear memory at address
556 if( dev->_data_buf_virt_addr != NULL ) 556 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
557 { 557
558 pci_free_consistent(dev->pci, dev->upstream_databuf_size, dev->_data_buf_virt_addr, dev->_data_buf_phys_addr); 558 ret = cx25821_openfile(dev, sram_ch);
559 } 559 if (ret < 0)
560 560 return ret;
561 //For Video Data buffer allocation 561
562 dev->_data_buf_virt_addr = pci_alloc_consistent(dev->pci, dev->upstream_databuf_size, &data_dma_addr); 562 //Create RISC programs
563 dev->_data_buf_phys_addr = data_dma_addr; 563 ret =
564 dev->_data_buf_size = dev->upstream_databuf_size; 564 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
565 565 dev->_lines_count);
566 if (!dev->_data_buf_virt_addr) 566 if (ret < 0) {
567 { 567 printk(KERN_INFO
568 printk("cx25821: FAILED to allocate memory for data buffer! Returning.\n"); 568 "cx25821: Failed creating Video Upstream Risc programs! \n");
569 return -ENOMEM; 569 goto error;
570 } 570 }
571 571
572 572 return 0;
573 //Clear memory at address 573
574 memset( dev->_data_buf_virt_addr, 0, dev->_data_buf_size ); 574 error:
575 575 return ret;
576 576}
577 ret = cx25821_openfile(dev, sram_ch); 577
578 if( ret < 0 ) 578int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
579 return ret; 579 u32 status)
580 580{
581 581 u32 int_msk_tmp;
582 //Create RISC programs 582 struct sram_channel *channel = &dev->sram_channels[chan_num];
583 ret = cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl, dev->_lines_count ); 583 int singlefield_lines = NTSC_FIELD_HEIGHT;
584 if (ret < 0) 584 int line_size_in_bytes = Y422_LINE_SZ;
585 { 585 int odd_risc_prog_size = 0;
586 printk(KERN_INFO "cx25821: Failed creating Video Upstream Risc programs! \n"); 586 dma_addr_t risc_phys_jump_addr;
587 goto error; 587 __le32 *rp;
588 } 588
589 589 if (status & FLD_VID_SRC_RISC1) {
590 return 0; 590 // We should only process one program per call
591 591 u32 prog_cnt = cx_read(channel->gpcnt);
592error: 592
593 return ret; 593 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
594} 594 int_msk_tmp = cx_read(channel->int_msk);
595 595 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
596int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num, u32 status) 596 cx_write(channel->int_stat, _intr_msk);
597{ 597
598 u32 int_msk_tmp; 598 spin_lock(&dev->slock);
599 struct sram_channel *channel = &dev->sram_channels[chan_num]; 599
600 int singlefield_lines = NTSC_FIELD_HEIGHT; 600 dev->_frame_index = prog_cnt;
601 int line_size_in_bytes = Y422_LINE_SZ; 601
602 int odd_risc_prog_size = 0; 602 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
603 dma_addr_t risc_phys_jump_addr; 603
604 __le32 * rp; 604 if (dev->_is_first_frame) {
605 605 dev->_is_first_frame = 0;
606 606
607 607 if (dev->_isNTSC) {
608 if (status & FLD_VID_SRC_RISC1) 608 singlefield_lines += 1;
609 { 609 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
610 // We should only process one program per call 610 } else {
611 u32 prog_cnt = cx_read( channel->gpcnt ); 611 singlefield_lines = PAL_FIELD_HEIGHT;
612 612 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
613 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers 613 }
614 int_msk_tmp = cx_read(channel->int_msk); 614
615 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); 615 if (dev->_dma_virt_start_addr != NULL) {
616 cx_write( channel->int_stat, _intr_msk ); 616 line_size_in_bytes =
617 617 (dev->_pixel_format ==
618 spin_lock(&dev->slock); 618 PIXEL_FRMT_411) ? Y411_LINE_SZ :
619 619 Y422_LINE_SZ;
620 dev->_frame_index = prog_cnt; 620 risc_phys_jump_addr =
621 621 dev->_dma_phys_start_addr +
622 queue_work(dev->_irq_queues, &dev->_irq_work_entry); 622 odd_risc_prog_size;
623 623
624 624 rp = cx25821_update_riscprogram(dev,
625 if ( dev->_is_first_frame ) 625 dev->
626 { 626 _dma_virt_start_addr,
627 dev->_is_first_frame = 0; 627 TOP_OFFSET,
628 628 line_size_in_bytes,
629 if( dev->_isNTSC ) 629 0x0,
630 { 630 singlefield_lines,
631 singlefield_lines += 1; 631 FIFO_DISABLE,
632 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE; 632 ODD_FIELD);
633 } 633
634 else 634 // Jump to Even Risc program of 1st Frame
635 { 635 *(rp++) = cpu_to_le32(RISC_JUMP);
636 singlefield_lines = PAL_FIELD_HEIGHT; 636 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
637 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE; 637 *(rp++) = cpu_to_le32(0);
638 } 638 }
639 639 }
640 640
641 if( dev->_dma_virt_start_addr != NULL ) 641 spin_unlock(&dev->slock);
642 { 642 } else {
643 line_size_in_bytes = (dev->_pixel_format == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 643 if (status & FLD_VID_SRC_UF)
644 risc_phys_jump_addr = dev->_dma_phys_start_addr + odd_risc_prog_size; 644 printk
645 645 ("%s: Video Received Underflow Error Interrupt!\n",
646 rp = cx25821_update_riscprogram(dev, dev->_dma_virt_start_addr, TOP_OFFSET, line_size_in_bytes, 0x0, singlefield_lines, FIFO_DISABLE, ODD_FIELD); 646 __func__);
647 647
648 // Jump to Even Risc program of 1st Frame 648 if (status & FLD_VID_SRC_SYNC)
649 *(rp++) = cpu_to_le32(RISC_JUMP); 649 printk("%s: Video Received Sync Error Interrupt!\n",
650 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 650 __func__);
651 *(rp++) = cpu_to_le32(0); 651
652 } 652 if (status & FLD_VID_SRC_OPC_ERR)
653 } 653 printk("%s: Video Received OpCode Error Interrupt!\n",
654 654 __func__);
655 spin_unlock(&dev->slock); 655 }
656 } 656
657 else 657 if (dev->_file_status == END_OF_FILE) {
658 { 658 printk("cx25821: EOF Channel 1 Framecount = %d\n",
659 if(status & FLD_VID_SRC_UF) 659 dev->_frame_count);
660 printk("%s: Video Received Underflow Error Interrupt!\n", __func__); 660 return -1;
661 661 }
662 if(status & FLD_VID_SRC_SYNC) 662 //ElSE, set the interrupt mask register, re-enable irq.
663 printk("%s: Video Received Sync Error Interrupt!\n", __func__); 663 int_msk_tmp = cx_read(channel->int_msk);
664 664 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
665 if(status & FLD_VID_SRC_OPC_ERR) 665
666 printk("%s: Video Received OpCode Error Interrupt!\n", __func__); 666 return 0;
667 } 667}
668 668
669 669static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
670 if( dev->_file_status == END_OF_FILE ) 670{
671 { 671 struct cx25821_dev *dev = dev_id;
672 printk("cx25821: EOF Channel 1 Framecount = %d\n", dev->_frame_count ); 672 u32 msk_stat, vid_status;
673 return -1; 673 int handled = 0;
674 } 674 int channel_num = 0;
675 675 struct sram_channel *sram_ch;
676 //ElSE, set the interrupt mask register, re-enable irq. 676
677 int_msk_tmp = cx_read( channel->int_msk ); 677 if (!dev)
678 cx_write( channel->int_msk, int_msk_tmp |= _intr_msk ); 678 return -1;
679 679
680 return 0; 680 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
681} 681
682 682 sram_ch = &dev->sram_channels[channel_num];
683static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id) 683
684{ 684 msk_stat = cx_read(sram_ch->int_mstat);
685 struct cx25821_dev *dev = dev_id; 685 vid_status = cx_read(sram_ch->int_stat);
686 u32 msk_stat, vid_status; 686
687 int handled = 0; 687 // Only deal with our interrupt
688 int channel_num = 0; 688 if (vid_status) {
689 struct sram_channel *sram_ch; 689 handled =
690 690 cx25821_video_upstream_irq(dev, channel_num, vid_status);
691 691 }
692 if( !dev ) 692
693 return -1; 693 if (handled < 0) {
694 694 cx25821_stop_upstream_video_ch1(dev);
695 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I; 695 } else {
696 696 handled += handled;
697 sram_ch = &dev->sram_channels[channel_num]; 697 }
698 698
699 msk_stat = cx_read(sram_ch->int_mstat); 699 return IRQ_RETVAL(handled);
700 vid_status = cx_read(sram_ch->int_stat); 700}
701 701
702 // Only deal with our interrupt 702void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
703 if(vid_status) 703 int pix_format)
704 { 704{
705 handled = cx25821_video_upstream_irq(dev, channel_num, vid_status); 705 int width = WIDTH_D1;
706 } 706 int height = dev->_lines_count;
707 707 int num_lines, odd_num_lines;
708 if( handled < 0 ) 708 u32 value;
709 { 709 int vip_mode = OUTPUT_FRMT_656;
710 cx25821_stop_upstream_video_ch1(dev); 710
711 } 711 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
712 else 712 value &= 0xFFFFFFEF;
713 { 713 value |= dev->_isNTSC ? 0 : 0x10;
714 handled += handled; 714 cx_write(ch->vid_fmt_ctl, value);
715 } 715
716 716 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
717 return IRQ_RETVAL(handled); 717 cx_write(ch->vid_active_ctl1, width);
718} 718
719 719 num_lines = (height / 2) & 0x3FF;
720 720 odd_num_lines = num_lines;
721void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch, int pix_format) 721
722{ 722 if (dev->_isNTSC) {
723 int width = WIDTH_D1; 723 odd_num_lines += 1;
724 int height = dev->_lines_count; 724 }
725 int num_lines, odd_num_lines; 725
726 u32 value; 726 value = (num_lines << 16) | odd_num_lines;
727 int vip_mode = OUTPUT_FRMT_656; 727
728 728 // set number of active lines in field 0 (top) and field 1 (bottom)
729 729 cx_write(ch->vid_active_ctl2, value);
730 value = ( (pix_format & 0x3) << 12 ) | ( vip_mode & 0x7 ); 730
731 value &= 0xFFFFFFEF; 731 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
732 value |= dev->_isNTSC ? 0 : 0x10; 732}
733 cx_write( ch->vid_fmt_ctl, value ); 733
734 734int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
735 735 struct sram_channel *sram_ch)
736 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format 736{
737 cx_write( ch->vid_active_ctl1, width ); 737 u32 tmp = 0;
738 738 int err = 0;
739 num_lines = (height / 2) & 0x3FF; 739
740 odd_num_lines = num_lines; 740 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
741 741 tmp = cx_read(VID_CH_MODE_SEL);
742 if(dev->_isNTSC) 742 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
743 { 743
744 odd_num_lines += 1; 744 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
745 } 745 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
746 746 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
747 value = (num_lines << 16) | odd_num_lines; 747
748 748 /* reset counter */
749 // set number of active lines in field 0 (top) and field 1 (bottom) 749 cx_write(sram_ch->gpcnt_ctl, 3);
750 cx_write( ch->vid_active_ctl2, value ); 750
751 751 // Clear our bits from the interrupt status register.
752 cx_write( ch->vid_cdt_size, VID_CDT_SIZE >> 3 ); 752 cx_write(sram_ch->int_stat, _intr_msk);
753} 753
754 754 //Set the interrupt mask register, enable irq.
755 755 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
756int cx25821_start_video_dma_upstream(struct cx25821_dev *dev, 756 tmp = cx_read(sram_ch->int_msk);
757 struct sram_channel *sram_ch) 757 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
758{ 758
759 u32 tmp = 0; 759 err =
760 int err = 0; 760 request_irq(dev->pci->irq, cx25821_upstream_irq,
761 761 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
762 762 if (err < 0) {
763 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C 763 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
764 tmp = cx_read( VID_CH_MODE_SEL ); 764 dev->pci->irq);
765 cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); 765 goto fail_irq;
766 766 }
767 767
768 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds. 768 // Start the DMA engine
769 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr); 769 tmp = cx_read(sram_ch->dma_ctl);
770 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */ 770 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
771 771
772 /* reset counter */ 772 dev->_is_running = 1;
773 cx_write(sram_ch->gpcnt_ctl, 3); 773 dev->_is_first_frame = 1;
774 774
775 // Clear our bits from the interrupt status register. 775 return 0;
776 cx_write( sram_ch->int_stat, _intr_msk ); 776
777 777 fail_irq:
778 778 cx25821_dev_unregister(dev);
779 //Set the interrupt mask register, enable irq. 779 return err;
780 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); 780}
781 tmp = cx_read( sram_ch->int_msk ); 781
782 cx_write( sram_ch->int_msk, tmp |= _intr_msk ); 782int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
783 783 int pixel_format)
784 784{
785 err = request_irq(dev->pci->irq, cx25821_upstream_irq, IRQF_SHARED | IRQF_DISABLED, dev->name, dev); 785 struct sram_channel *sram_ch;
786 if (err < 0) 786 u32 tmp;
787 { 787 int retval = 0;
788 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, dev->pci->irq); 788 int err = 0;
789 goto fail_irq; 789 int data_frame_size = 0;
790 } 790 int risc_buffer_size = 0;
791 791 int str_length = 0;
792 792
793 // Start the DMA engine 793 if (dev->_is_running) {
794 tmp = cx_read( sram_ch->dma_ctl ); 794 printk("Video Channel is still running so return!\n");
795 cx_set( sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN ); 795 return 0;
796 796 }
797 dev->_is_running = 1; 797
798 dev->_is_first_frame = 1; 798 dev->_channel_upstream_select = channel_select;
799 799 sram_ch = &dev->sram_channels[channel_select];
800 return 0; 800
801 801 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
802fail_irq: 802 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
803 cx25821_dev_unregister(dev); 803
804 return err; 804 if (!dev->_irq_queues) {
805} 805 printk
806 806 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
807 807 return -ENOMEM;
808int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select, int pixel_format) 808 }
809{ 809 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
810 struct sram_channel *sram_ch; 810 tmp = cx_read(VID_CH_MODE_SEL);
811 u32 tmp; 811 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
812 int retval = 0; 812
813 int err = 0; 813 dev->_is_running = 0;
814 int data_frame_size = 0; 814 dev->_frame_count = 0;
815 int risc_buffer_size = 0; 815 dev->_file_status = RESET_STATUS;
816 int str_length = 0; 816 dev->_lines_count = dev->_isNTSC ? 480 : 576;
817 817 dev->_pixel_format = pixel_format;
818 818 dev->_line_size =
819 if( dev->_is_running ) 819 (dev->_pixel_format ==
820 { 820 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
821 printk("Video Channel is still running so return!\n"); 821 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
822 return 0; 822 risc_buffer_size =
823 } 823 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
824 824
825 825 if (dev->input_filename) {
826 dev->_channel_upstream_select = channel_select; 826 str_length = strlen(dev->input_filename);
827 sram_ch = &dev->sram_channels[channel_select]; 827 dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
828 828
829 829 if (!dev->_filename)
830 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler); 830 goto error;
831 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue"); 831
832 832 memcpy(dev->_filename, dev->input_filename, str_length + 1);
833 if(!dev->_irq_queues) 833 } else {
834 { 834 str_length = strlen(dev->_defaultname);
835 printk("cx25821: create_singlethread_workqueue() for Video FAILED!\n"); 835 dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
836 return -ENOMEM; 836
837 } 837 if (!dev->_filename)
838 838 goto error;
839 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C 839
840 tmp = cx_read( VID_CH_MODE_SEL ); 840 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
841 cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); 841 }
842 842
843 843 //Default if filename is empty string
844 dev->_is_running = 0; 844 if (strcmp(dev->input_filename, "") == 0) {
845 dev->_frame_count = 0; 845 if (dev->_isNTSC) {
846 dev->_file_status = RESET_STATUS; 846 dev->_filename =
847 dev->_lines_count = dev->_isNTSC ? 480 : 576; 847 (dev->_pixel_format ==
848 dev->_pixel_format = pixel_format; 848 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
849 dev->_line_size = (dev->_pixel_format == PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 849 "/root/vidtest.yuv";
850 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ; 850 } else {
851 risc_buffer_size = dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE; 851 dev->_filename =
852 852 (dev->_pixel_format ==
853 853 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
854 if( dev->input_filename ) 854 "/root/pal422.yuv";
855 { 855 }
856 str_length = strlen(dev->input_filename); 856 }
857 dev->_filename = (char *) kmalloc(str_length + 1, GFP_KERNEL); 857
858 858 dev->_is_running = 0;
859 if( !dev->_filename ) 859 dev->_frame_count = 0;
860 goto error; 860 dev->_file_status = RESET_STATUS;
861 861 dev->_lines_count = dev->_isNTSC ? 480 : 576;
862 memcpy(dev->_filename, dev->input_filename, str_length + 1); 862 dev->_pixel_format = pixel_format;
863 } 863 dev->_line_size =
864 else 864 (dev->_pixel_format ==
865 { 865 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
866 str_length = strlen(dev->_defaultname); 866
867 dev->_filename = (char *) kmalloc(str_length + 1, GFP_KERNEL); 867 retval =
868 868 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
869 if( !dev->_filename ) 869 0);
870 goto error; 870
871 871 /* setup fifo + format */
872 memcpy(dev->_filename, dev->_defaultname, str_length + 1); 872 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
873 } 873
874 874 dev->upstream_riscbuf_size = risc_buffer_size * 2;
875 875 dev->upstream_databuf_size = data_frame_size * 2;
876 //Default if filename is empty string 876
877 if( strcmp(dev->input_filename,"") == 0) 877 //Allocating buffers and prepare RISC program
878 { 878 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
879 if( dev->_isNTSC ) 879 if (retval < 0) {
880 { 880 printk(KERN_ERR
881 dev->_filename = (dev->_pixel_format == PIXEL_FRMT_411) ? "/root/vid411.yuv" : "/root/vidtest.yuv"; 881 "%s: Failed to set up Video upstream buffers!\n",
882 } 882 dev->name);
883 else 883 goto error;
884 { 884 }
885 dev->_filename = (dev->_pixel_format == PIXEL_FRMT_411) ? "/root/pal411.yuv" : "/root/pal422.yuv"; 885
886 } 886 cx25821_start_video_dma_upstream(dev, sram_ch);
887 } 887
888 888 return 0;
889 dev->_is_running = 0; 889
890 dev->_frame_count = 0; 890 error:
891 dev->_file_status = RESET_STATUS; 891 cx25821_dev_unregister(dev);
892 dev->_lines_count = dev->_isNTSC ? 480 : 576; 892
893 dev->_pixel_format = pixel_format; 893 return err;
894 dev->_line_size = (dev->_pixel_format == PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 894}
895
896 retval = cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size, 0);
897
898 /* setup fifo + format */
899 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
900
901 dev->upstream_riscbuf_size = risc_buffer_size * 2;
902 dev->upstream_databuf_size = data_frame_size * 2;
903
904
905 //Allocating buffers and prepare RISC program
906 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
907 if (retval < 0)
908 {
909 printk(KERN_ERR "%s: Failed to set up Video upstream buffers!\n", dev->name);
910 goto error;
911 }
912
913
914 cx25821_start_video_dma_upstream(dev, sram_ch);
915
916 return 0;
917
918error:
919 cx25821_dev_unregister(dev);
920
921 return err;
922}
923
diff --git a/drivers/staging/cx25821/cx25821-video-upstream.h b/drivers/staging/cx25821/cx25821-video-upstream.h
index c134a1956ee8..cc9f93842514 100644
--- a/drivers/staging/cx25821/cx25821-video-upstream.h
+++ b/drivers/staging/cx25821/cx25821-video-upstream.h
@@ -1,113 +1,109 @@
1/* 1/*
2 * Driver for the Conexant CX25821 PCIe bridge 2 * Driver for the Conexant CX25821 PCIe bridge
3 * 3 *
4 * Copyright (C) 2009 Conexant Systems Inc. 4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * 15 *
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22 22
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/workqueue.h> 24#include <linux/workqueue.h>
25 25
26#define OUTPUT_FRMT_656 0 26#define OUTPUT_FRMT_656 0
27#define OPEN_FILE_1 0 27#define OPEN_FILE_1 0
28#define NUM_PROGS 8 28#define NUM_PROGS 8
29#define NUM_FRAMES 2 29#define NUM_FRAMES 2
30#define ODD_FIELD 0 30#define ODD_FIELD 0
31#define EVEN_FIELD 1 31#define EVEN_FIELD 1
32#define TOP_OFFSET 0 32#define TOP_OFFSET 0
33#define FIFO_DISABLE 0 33#define FIFO_DISABLE 0
34#define FIFO_ENABLE 1 34#define FIFO_ENABLE 1
35#define TEST_FRAMES 5 35#define TEST_FRAMES 5
36#define END_OF_FILE 0 36#define END_OF_FILE 0
37#define IN_PROGRESS 1 37#define IN_PROGRESS 1
38#define RESET_STATUS -1 38#define RESET_STATUS -1
39#define NUM_NO_OPS 5 39#define NUM_NO_OPS 5
40 40
41 41// PAL and NTSC line sizes and number of lines.
42 42#define WIDTH_D1 720
43// PAL and NTSC line sizes and number of lines. 43#define NTSC_LINES_PER_FRAME 480
44#define WIDTH_D1 720 44#define PAL_LINES_PER_FRAME 576
45#define NTSC_LINES_PER_FRAME 480 45#define PAL_LINE_SZ 1440
46#define PAL_LINES_PER_FRAME 576 46#define Y422_LINE_SZ 1440
47#define PAL_LINE_SZ 1440 47#define Y411_LINE_SZ 1080
48#define Y422_LINE_SZ 1440 48#define NTSC_FIELD_HEIGHT 240
49#define Y411_LINE_SZ 1080 49#define NTSC_ODD_FLD_LINES 241
50#define NTSC_FIELD_HEIGHT 240 50#define PAL_FIELD_HEIGHT 288
51#define NTSC_ODD_FLD_LINES 241 51
52#define PAL_FIELD_HEIGHT 288 52#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ)
53 53#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ)
54#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ) 54#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ)
55#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ) 55#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ)
56#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ) 56
57#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ) 57#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME)
58 58#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME)
59#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME) 59
60#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME) 60#define RISC_WRITECR_INSTRUCTION_SIZE 16
61 61#define RISC_SYNC_INSTRUCTION_SIZE 4
62#define RISC_WRITECR_INSTRUCTION_SIZE 16 62#define JUMP_INSTRUCTION_SIZE 12
63#define RISC_SYNC_INSTRUCTION_SIZE 4 63#define MAXSIZE_NO_OPS 36
64#define JUMP_INSTRUCTION_SIZE 12 64#define DWORD_SIZE 4
65#define MAXSIZE_NO_OPS 36 65
66#define DWORD_SIZE 4 66#define USE_RISC_NOOP_VIDEO 1
67 67
68 68#ifdef USE_RISC_NOOP_VIDEO
69#define USE_RISC_NOOP_VIDEO 1 69#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
70 70 RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
71#ifdef USE_RISC_NOOP_VIDEO 71
72#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ 72#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE)
73 RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 73
74 74#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
75#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE) 75 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
76 76
77#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ 77#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
78 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) 78 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
79 79
80#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ 80#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
81 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 81 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
82 82
83#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \ 83#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
84 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 84 JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
85 85
86#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ 86#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE))
87 JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE) 87
88 88#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
89#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE)) 89 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
90 90
91#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ 91#endif
92 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE) 92
93 93#ifndef USE_RISC_NOOP_VIDEO
94#endif 94#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
95 95 RISC_SYNC_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
96 96
97#ifndef USE_RISC_NOOP_VIDEO 97#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE)
98#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \ 98
99 RISC_SYNC_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE) 99#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
100 100 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE )
101#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE) 101
102 102#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE )
103#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \ 103#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE )
104 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE ) 104
105 105#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
106#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) 106#define NTSC_RISC_BUF_SIZE ( 2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE) )
107#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE ) 107#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
108 108 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE )
109#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE) 109#endif
110#define NTSC_RISC_BUF_SIZE ( 2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE) )
111#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
112 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE )
113#endif
diff --git a/drivers/staging/cx25821/cx25821-video.c b/drivers/staging/cx25821/cx25821-video.c
index ba8115b6e0aa..93863531312b 100644
--- a/drivers/staging/cx25821/cx25821-video.c
+++ b/drivers/staging/cx25821/cx25821-video.c
@@ -27,8 +27,8 @@ MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
27MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>"); 27MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
28MODULE_LICENSE("GPL"); 28MODULE_LICENSE("GPL");
29 29
30static unsigned int video_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; 30static unsigned int video_nr[] = {[0...(CX25821_MAXBOARDS - 1)] = UNSET };
31static unsigned int radio_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; 31static unsigned int radio_nr[] = {[0...(CX25821_MAXBOARDS - 1)] = UNSET };
32 32
33module_param_array(video_nr, int, NULL, 0444); 33module_param_array(video_nr, int, NULL, 0444);
34module_param_array(radio_nr, int, NULL, 0444); 34module_param_array(radio_nr, int, NULL, 0444);
@@ -36,7 +36,7 @@ module_param_array(radio_nr, int, NULL, 0444);
36MODULE_PARM_DESC(video_nr, "video device numbers"); 36MODULE_PARM_DESC(video_nr, "video device numbers");
37MODULE_PARM_DESC(radio_nr, "radio device numbers"); 37MODULE_PARM_DESC(radio_nr, "radio device numbers");
38 38
39static unsigned int video_debug=VIDEO_DEBUG; 39static unsigned int video_debug = VIDEO_DEBUG;
40module_param(video_debug, int, 0644); 40module_param(video_debug, int, 0644);
41MODULE_PARM_DESC(video_debug, "enable debug messages [video]"); 41MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
42 42
@@ -53,147 +53,143 @@ static void init_controls(struct cx25821_dev *dev, int chan_num);
53#define FORMAT_FLAGS_PACKED 0x01 53#define FORMAT_FLAGS_PACKED 0x01
54 54
55struct cx25821_fmt formats[] = { 55struct cx25821_fmt formats[] = {
56 { 56 {
57 .name = "8 bpp, gray", 57 .name = "8 bpp, gray",
58 .fourcc = V4L2_PIX_FMT_GREY, 58 .fourcc = V4L2_PIX_FMT_GREY,
59 .depth = 8, 59 .depth = 8,
60 .flags = FORMAT_FLAGS_PACKED, 60 .flags = FORMAT_FLAGS_PACKED,
61 }, { 61 }, {
62 .name = "4:1:1, packed, Y41P", 62 .name = "4:1:1, packed, Y41P",
63 .fourcc = V4L2_PIX_FMT_Y41P, 63 .fourcc = V4L2_PIX_FMT_Y41P,
64 .depth = 12, 64 .depth = 12,
65 .flags = FORMAT_FLAGS_PACKED, 65 .flags = FORMAT_FLAGS_PACKED,
66 }, { 66 }, {
67 .name = "4:2:2, packed, YUYV", 67 .name = "4:2:2, packed, YUYV",
68 .fourcc = V4L2_PIX_FMT_YUYV, 68 .fourcc = V4L2_PIX_FMT_YUYV,
69 .depth = 16, 69 .depth = 16,
70 .flags = FORMAT_FLAGS_PACKED, 70 .flags = FORMAT_FLAGS_PACKED,
71 }, { 71 }, {
72 .name = "4:2:2, packed, UYVY", 72 .name = "4:2:2, packed, UYVY",
73 .fourcc = V4L2_PIX_FMT_UYVY, 73 .fourcc = V4L2_PIX_FMT_UYVY,
74 .depth = 16, 74 .depth = 16,
75 .flags = FORMAT_FLAGS_PACKED, 75 .flags = FORMAT_FLAGS_PACKED,
76 },{ 76 }, {
77 .name = "4:2:0, YUV", 77 .name = "4:2:0, YUV",
78 .fourcc = V4L2_PIX_FMT_YUV420, 78 .fourcc = V4L2_PIX_FMT_YUV420,
79 .depth = 12, 79 .depth = 12,
80 .flags = FORMAT_FLAGS_PACKED, 80 .flags = FORMAT_FLAGS_PACKED,
81 }, 81 },
82}; 82};
83 83
84
85int get_format_size(void) 84int get_format_size(void)
86{ 85{
87 return ARRAY_SIZE(formats); 86 return ARRAY_SIZE(formats);
88} 87}
89 88
90
91struct cx25821_fmt *format_by_fourcc(unsigned int fourcc) 89struct cx25821_fmt *format_by_fourcc(unsigned int fourcc)
92{ 90{
93 unsigned int i; 91 unsigned int i;
94 92
95 if( fourcc == V4L2_PIX_FMT_Y41P || fourcc == V4L2_PIX_FMT_YUV411P ) 93 if (fourcc == V4L2_PIX_FMT_Y41P || fourcc == V4L2_PIX_FMT_YUV411P) {
96 { 94 return formats + 1;
97 return formats+1; 95 }
98 }
99 96
100 for (i = 0; i < ARRAY_SIZE(formats); i++) 97 for (i = 0; i < ARRAY_SIZE(formats); i++)
101 if (formats[i].fourcc == fourcc) 98 if (formats[i].fourcc == fourcc)
102 return formats+i; 99 return formats + i;
103 100
104 printk(KERN_ERR "%s(0x%08x) NOT FOUND\n", __func__, fourcc); 101 printk(KERN_ERR "%s(0x%08x) NOT FOUND\n", __func__, fourcc);
105 return NULL; 102 return NULL;
106} 103}
107 104
108void dump_video_queue(struct cx25821_dev *dev, struct cx25821_dmaqueue *q) 105void dump_video_queue(struct cx25821_dev *dev, struct cx25821_dmaqueue *q)
109{ 106{
110 struct cx25821_buffer *buf; 107 struct cx25821_buffer *buf;
111 struct list_head *item; 108 struct list_head *item;
112 dprintk(1, "%s()\n", __func__); 109 dprintk(1, "%s()\n", __func__);
113 110
114 if (!list_empty(&q->active)) { 111 if (!list_empty(&q->active)) {
115 list_for_each(item, &q->active) 112 list_for_each(item, &q->active)
116 buf = list_entry(item, struct cx25821_buffer, vb.queue); 113 buf = list_entry(item, struct cx25821_buffer, vb.queue);
117 } 114 }
118 115
119 if (!list_empty(&q->queued)) 116 if (!list_empty(&q->queued)) {
120 { 117 list_for_each(item, &q->queued)
121 list_for_each(item, &q->queued) 118 buf = list_entry(item, struct cx25821_buffer, vb.queue);
122 buf = list_entry(item, struct cx25821_buffer, vb.queue); 119 }
123 }
124 120
125} 121}
126 122
127 123void cx25821_video_wakeup(struct cx25821_dev *dev, struct cx25821_dmaqueue *q,
128void cx25821_video_wakeup(struct cx25821_dev *dev, struct cx25821_dmaqueue *q, u32 count) 124 u32 count)
129{ 125{
130 struct cx25821_buffer *buf; 126 struct cx25821_buffer *buf;
131 int bc; 127 int bc;
132 128
133 for (bc = 0;; bc++) { 129 for (bc = 0;; bc++) {
134 if (list_empty(&q->active)) 130 if (list_empty(&q->active)) {
135 { 131 dprintk(1, "bc=%d (=0: active empty)\n", bc);
136 dprintk(1, "bc=%d (=0: active empty)\n", bc); 132 break;
137 break; 133 }
138 }
139 134
140 buf = list_entry(q->active.next, struct cx25821_buffer, vb.queue); 135 buf =
136 list_entry(q->active.next, struct cx25821_buffer, vb.queue);
141 137
142 /* count comes from the hw and it is 16bit wide -- 138 /* count comes from the hw and it is 16bit wide --
143 * this trick handles wrap-arounds correctly for 139 * this trick handles wrap-arounds correctly for
144 * up to 32767 buffers in flight... */ 140 * up to 32767 buffers in flight... */
145 if ((s16) (count - buf->count) < 0) 141 if ((s16) (count - buf->count) < 0) {
146 { 142 break;
147 break; 143 }
148 }
149 144
150 do_gettimeofday(&buf->vb.ts); 145 do_gettimeofday(&buf->vb.ts);
151 buf->vb.state = VIDEOBUF_DONE; 146 buf->vb.state = VIDEOBUF_DONE;
152 list_del(&buf->vb.queue); 147 list_del(&buf->vb.queue);
153 wake_up(&buf->vb.done); 148 wake_up(&buf->vb.done);
154 } 149 }
155 150
156 if (list_empty(&q->active)) 151 if (list_empty(&q->active))
157 del_timer(&q->timeout); 152 del_timer(&q->timeout);
158 else 153 else
159 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 154 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
160 if (bc != 1) 155 if (bc != 1)
161 printk(KERN_ERR "%s: %d buffers handled (should be 1)\n", __func__, bc); 156 printk(KERN_ERR "%s: %d buffers handled (should be 1)\n",
157 __func__, bc);
162} 158}
163 159
164#ifdef TUNER_FLAG 160#ifdef TUNER_FLAG
165int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm) 161int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm)
166{ 162{
167 dprintk(1, "%s(norm = 0x%08x) name: [%s]\n", __func__, 163 dprintk(1, "%s(norm = 0x%08x) name: [%s]\n", __func__,
168 (unsigned int)norm, 164 (unsigned int)norm, v4l2_norm_to_name(norm));
169 v4l2_norm_to_name(norm));
170 165
171 dev->tvnorm = norm; 166 dev->tvnorm = norm;
172 167
173 /* Tell the internal A/V decoder */ 168 /* Tell the internal A/V decoder */
174 cx25821_call_all(dev, core, s_std, norm); 169 cx25821_call_all(dev, core, s_std, norm);
175 170
176 return 0; 171 return 0;
177} 172}
178#endif 173#endif
179 174
180struct video_device *cx25821_vdev_init(struct cx25821_dev *dev, 175struct video_device *cx25821_vdev_init(struct cx25821_dev *dev,
181 struct pci_dev *pci, 176 struct pci_dev *pci,
182 struct video_device *template, 177 struct video_device *template,
183 char *type) 178 char *type)
184{ 179{
185 struct video_device *vfd; 180 struct video_device *vfd;
186 dprintk(1, "%s()\n", __func__); 181 dprintk(1, "%s()\n", __func__);
187 182
188 vfd = video_device_alloc(); 183 vfd = video_device_alloc();
189 if (NULL == vfd) 184 if (NULL == vfd)
190 return NULL; 185 return NULL;
191 *vfd = *template; 186 *vfd = *template;
192 vfd->minor = -1; 187 vfd->minor = -1;
193 vfd->v4l2_dev = &dev->v4l2_dev; 188 vfd->v4l2_dev = &dev->v4l2_dev;
194 vfd->release = video_device_release; 189 vfd->release = video_device_release;
195 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, type, cx25821_boards[dev->board].name); 190 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, type,
196 return vfd; 191 cx25821_boards[dev->board].name);
192 return vfd;
197} 193}
198 194
199/* 195/*
@@ -218,615 +214,609 @@ static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl)
218// resource management 214// resource management
219int res_get(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bit) 215int res_get(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bit)
220{ 216{
221 dprintk(1, "%s()\n", __func__); 217 dprintk(1, "%s()\n", __func__);
222 if (fh->resources & bit) 218 if (fh->resources & bit)
223 /* have it already allocated */ 219 /* have it already allocated */
224 return 1; 220 return 1;
225 221
226 /* is it free? */ 222 /* is it free? */
227 mutex_lock(&dev->lock); 223 mutex_lock(&dev->lock);
228 if (dev->resources & bit) { 224 if (dev->resources & bit) {
229 /* no, someone else uses it */ 225 /* no, someone else uses it */
226 mutex_unlock(&dev->lock);
227 return 0;
228 }
229 /* it's free, grab it */
230 fh->resources |= bit;
231 dev->resources |= bit;
232 dprintk(1, "res: get %d\n", bit);
230 mutex_unlock(&dev->lock); 233 mutex_unlock(&dev->lock);
231 return 0; 234 return 1;
232 }
233 /* it's free, grab it */
234 fh->resources |= bit;
235 dev->resources |= bit;
236 dprintk(1, "res: get %d\n", bit);
237 mutex_unlock(&dev->lock);
238 return 1;
239} 235}
240 236
241int res_check(struct cx25821_fh *fh, unsigned int bit) 237int res_check(struct cx25821_fh *fh, unsigned int bit)
242{ 238{
243 return fh->resources & bit; 239 return fh->resources & bit;
244} 240}
245 241
246int res_locked(struct cx25821_dev *dev, unsigned int bit) 242int res_locked(struct cx25821_dev *dev, unsigned int bit)
247{ 243{
248 return dev->resources & bit; 244 return dev->resources & bit;
249} 245}
250 246
251void res_free(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bits) 247void res_free(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bits)
252{ 248{
253 BUG_ON((fh->resources & bits) != bits); 249 BUG_ON((fh->resources & bits) != bits);
254 dprintk(1, "%s()\n", __func__); 250 dprintk(1, "%s()\n", __func__);
255 251
256 mutex_lock(&dev->lock); 252 mutex_lock(&dev->lock);
257 fh->resources &= ~bits; 253 fh->resources &= ~bits;
258 dev->resources &= ~bits; 254 dev->resources &= ~bits;
259 dprintk(1, "res: put %d\n", bits); 255 dprintk(1, "res: put %d\n", bits);
260 mutex_unlock(&dev->lock); 256 mutex_unlock(&dev->lock);
261} 257}
262 258
263int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input) 259int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input)
264{ 260{
265 struct v4l2_routing route; 261 struct v4l2_routing route;
266 memset(&route, 0, sizeof(route)); 262 memset(&route, 0, sizeof(route));
267 263
268 dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n", __func__, 264 dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n",
269 input, INPUT(input)->vmux, 265 __func__, input, INPUT(input)->vmux, INPUT(input)->gpio0,
270 INPUT(input)->gpio0, INPUT(input)->gpio1, 266 INPUT(input)->gpio1, INPUT(input)->gpio2, INPUT(input)->gpio3);
271 INPUT(input)->gpio2, INPUT(input)->gpio3); 267 dev->input = input;
272 dev->input = input;
273 268
274 route.input = INPUT(input)->vmux; 269 route.input = INPUT(input)->vmux;
275 270
276 /* Tell the internal A/V decoder */ 271 /* Tell the internal A/V decoder */
277 cx25821_call_all(dev, video, s_routing, INPUT(input)->vmux, 0, 0); 272 cx25821_call_all(dev, video, s_routing, INPUT(input)->vmux, 0, 0);
278 273
279 return 0; 274 return 0;
280} 275}
281 276
282int cx25821_start_video_dma(struct cx25821_dev *dev, 277int cx25821_start_video_dma(struct cx25821_dev *dev,
283 struct cx25821_dmaqueue *q, 278 struct cx25821_dmaqueue *q,
284 struct cx25821_buffer *buf, 279 struct cx25821_buffer *buf,
285 struct sram_channel *channel) 280 struct sram_channel *channel)
286{ 281{
287 int tmp = 0; 282 int tmp = 0;
288 283
289 /* setup fifo + format */ 284 /* setup fifo + format */
290 cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma); 285 cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma);
291 286
292 /* reset counter */ 287 /* reset counter */
293 cx_write(channel->gpcnt_ctl, 3); 288 cx_write(channel->gpcnt_ctl, 3);
294 q->count = 1; 289 q->count = 1;
295 290
296 /* enable irq */ 291 /* enable irq */
297 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1<<channel->i)); 292 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i));
298 cx_set(channel->int_msk, 0x11); 293 cx_set(channel->int_msk, 0x11);
299 294
300 /* start dma */ 295 /* start dma */
301 cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */ 296 cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */
302 297
303 /* make sure upstream setting if any is reversed */ 298 /* make sure upstream setting if any is reversed */
304 tmp = cx_read( VID_CH_MODE_SEL ); 299 tmp = cx_read(VID_CH_MODE_SEL);
305 cx_write( VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 300 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
306 301
307 return 0; 302 return 0;
308} 303}
309 304
310 305int cx25821_restart_video_queue(struct cx25821_dev *dev,
311int cx25821_restart_video_queue(struct cx25821_dev *dev, struct cx25821_dmaqueue *q, struct sram_channel *channel) 306 struct cx25821_dmaqueue *q,
307 struct sram_channel *channel)
312{ 308{
313 struct cx25821_buffer *buf, *prev; 309 struct cx25821_buffer *buf, *prev;
314 struct list_head *item; 310 struct list_head *item;
315 311
316 if (!list_empty(&q->active)) { 312 if (!list_empty(&q->active)) {
317 buf = list_entry(q->active.next, struct cx25821_buffer, vb.queue); 313 buf =
314 list_entry(q->active.next, struct cx25821_buffer, vb.queue);
318 315
319 cx25821_start_video_dma(dev, q, buf, channel); 316 cx25821_start_video_dma(dev, q, buf, channel);
320 317
321 list_for_each(item, &q->active) { 318 list_for_each(item, &q->active) {
322 buf = list_entry(item, struct cx25821_buffer, vb.queue); 319 buf = list_entry(item, struct cx25821_buffer, vb.queue);
323 buf->count = q->count++; 320 buf->count = q->count++;
324 } 321 }
325 322
326 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 323 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
327 return 0; 324 return 0;
328 } 325 }
329 326
330 prev = NULL; 327 prev = NULL;
331 for (;;) { 328 for (;;) {
332 if (list_empty(&q->queued)) 329 if (list_empty(&q->queued))
333 return 0; 330 return 0;
334 331
335 buf = list_entry(q->queued.next, struct cx25821_buffer, vb.queue); 332 buf =
336 333 list_entry(q->queued.next, struct cx25821_buffer, vb.queue);
337 if (NULL == prev) { 334
338 list_move_tail(&buf->vb.queue, &q->active); 335 if (NULL == prev) {
339 cx25821_start_video_dma(dev, q, buf, channel); 336 list_move_tail(&buf->vb.queue, &q->active);
340 buf->vb.state = VIDEOBUF_ACTIVE; 337 cx25821_start_video_dma(dev, q, buf, channel);
341 buf->count = q->count++; 338 buf->vb.state = VIDEOBUF_ACTIVE;
342 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 339 buf->count = q->count++;
343 } else if (prev->vb.width == buf->vb.width && 340 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
344 prev->vb.height == buf->vb.height && 341 } else if (prev->vb.width == buf->vb.width &&
345 prev->fmt == buf->fmt) { 342 prev->vb.height == buf->vb.height &&
346 list_move_tail(&buf->vb.queue, &q->active); 343 prev->fmt == buf->fmt) {
347 buf->vb.state = VIDEOBUF_ACTIVE; 344 list_move_tail(&buf->vb.queue, &q->active);
348 buf->count = q->count++; 345 buf->vb.state = VIDEOBUF_ACTIVE;
349 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); 346 buf->count = q->count++;
350 prev->risc.jmp[2] = cpu_to_le32(0); /* Bits 63 - 32 */ 347 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
351 } else { 348 prev->risc.jmp[2] = cpu_to_le32(0); /* Bits 63 - 32 */
352 return 0; 349 } else {
350 return 0;
351 }
352 prev = buf;
353 } 353 }
354 prev = buf;
355 }
356} 354}
357 355
358void cx25821_vid_timeout(unsigned long data) 356void cx25821_vid_timeout(unsigned long data)
359{ 357{
360 struct cx25821_data *timeout_data = (struct cx25821_data *)data; 358 struct cx25821_data *timeout_data = (struct cx25821_data *)data;
361 struct cx25821_dev *dev = timeout_data->dev; 359 struct cx25821_dev *dev = timeout_data->dev;
362 struct sram_channel *channel = timeout_data->channel; 360 struct sram_channel *channel = timeout_data->channel;
363 struct cx25821_dmaqueue *q = &dev->vidq[channel->i]; 361 struct cx25821_dmaqueue *q = &dev->vidq[channel->i];
364 struct cx25821_buffer *buf; 362 struct cx25821_buffer *buf;
365 unsigned long flags; 363 unsigned long flags;
366 364
367 //cx25821_sram_channel_dump(dev, channel); 365 //cx25821_sram_channel_dump(dev, channel);
368 cx_clear(channel->dma_ctl, 0x11); 366 cx_clear(channel->dma_ctl, 0x11);
369 367
370 spin_lock_irqsave(&dev->slock, flags); 368 spin_lock_irqsave(&dev->slock, flags);
371 while (!list_empty(&q->active)) { 369 while (!list_empty(&q->active)) {
372 buf = list_entry(q->active.next, struct cx25821_buffer, vb.queue); 370 buf =
373 list_del(&buf->vb.queue); 371 list_entry(q->active.next, struct cx25821_buffer, vb.queue);
374 372 list_del(&buf->vb.queue);
375 buf->vb.state = VIDEOBUF_ERROR;
376 wake_up(&buf->vb.done);
377 }
378 373
379 cx25821_restart_video_queue(dev, q, channel); 374 buf->vb.state = VIDEOBUF_ERROR;
380 spin_unlock_irqrestore(&dev->slock, flags); 375 wake_up(&buf->vb.done);
376 }
377
378 cx25821_restart_video_queue(dev, q, channel);
379 spin_unlock_irqrestore(&dev->slock, flags);
381} 380}
382 381
383int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status) 382int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status)
384{ 383{
385 u32 count=0; 384 u32 count = 0;
386 int handled = 0; 385 int handled = 0;
387 u32 mask; 386 u32 mask;
388 struct sram_channel *channel = &dev->sram_channels[chan_num]; 387 struct sram_channel *channel = &dev->sram_channels[chan_num];
389 388
390 mask = cx_read(channel->int_msk); 389 mask = cx_read(channel->int_msk);
391 if (0 == (status & mask)) 390 if (0 == (status & mask))
392 return handled; 391 return handled;
393 392
394 cx_write(channel->int_stat, status); 393 cx_write(channel->int_stat, status);
395 394
396 /* risc op code error */ 395 /* risc op code error */
397 if (status & (1 << 16)) { 396 if (status & (1 << 16)) {
398 printk(KERN_WARNING "%s, %s: video risc op code error\n", dev->name, channel->name); 397 printk(KERN_WARNING "%s, %s: video risc op code error\n",
399 cx_clear(channel->dma_ctl, 0x11); 398 dev->name, channel->name);
400 cx25821_sram_channel_dump(dev, channel); 399 cx_clear(channel->dma_ctl, 0x11);
401 } 400 cx25821_sram_channel_dump(dev, channel);
401 }
402 402
403 /* risc1 y */ 403 /* risc1 y */
404 if (status & FLD_VID_DST_RISC1) { 404 if (status & FLD_VID_DST_RISC1) {
405 spin_lock(&dev->slock); 405 spin_lock(&dev->slock);
406 count = cx_read(channel->gpcnt); 406 count = cx_read(channel->gpcnt);
407 cx25821_video_wakeup(dev, &dev->vidq[channel->i], count); 407 cx25821_video_wakeup(dev, &dev->vidq[channel->i], count);
408 spin_unlock(&dev->slock); 408 spin_unlock(&dev->slock);
409 handled++; 409 handled++;
410 } 410 }
411 411
412 /* risc2 y */ 412 /* risc2 y */
413 if (status & 0x10) { 413 if (status & 0x10) {
414 dprintk(2, "stopper video\n"); 414 dprintk(2, "stopper video\n");
415 spin_lock(&dev->slock); 415 spin_lock(&dev->slock);
416 cx25821_restart_video_queue(dev, &dev->vidq[channel->i], channel); 416 cx25821_restart_video_queue(dev, &dev->vidq[channel->i],
417 spin_unlock(&dev->slock); 417 channel);
418 handled++; 418 spin_unlock(&dev->slock);
419 } 419 handled++;
420 return handled; 420 }
421 return handled;
421} 422}
422 423
423void cx25821_videoioctl_unregister(struct cx25821_dev *dev) 424void cx25821_videoioctl_unregister(struct cx25821_dev *dev)
424{ 425{
425 if( dev->ioctl_dev ) 426 if (dev->ioctl_dev) {
426 { 427 if (dev->ioctl_dev->minor != -1)
427 if (dev->ioctl_dev->minor != -1) 428 video_unregister_device(dev->ioctl_dev);
428 video_unregister_device(dev->ioctl_dev); 429 else
429 else 430 video_device_release(dev->ioctl_dev);
430 video_device_release(dev->ioctl_dev);
431 431
432 dev->ioctl_dev = NULL; 432 dev->ioctl_dev = NULL;
433 } 433 }
434} 434}
435 435
436void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num) 436void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num)
437{ 437{
438 cx_clear(PCI_INT_MSK, 1); 438 cx_clear(PCI_INT_MSK, 1);
439 439
440 if (dev->video_dev[chan_num]) { 440 if (dev->video_dev[chan_num]) {
441 if (-1 != dev->video_dev[chan_num]->minor) 441 if (-1 != dev->video_dev[chan_num]->minor)
442 video_unregister_device(dev->video_dev[chan_num]); 442 video_unregister_device(dev->video_dev[chan_num]);
443 else 443 else
444 video_device_release(dev->video_dev[chan_num]); 444 video_device_release(dev->video_dev[chan_num]);
445 445
446 dev->video_dev[chan_num] = NULL; 446 dev->video_dev[chan_num] = NULL;
447 447
448 btcx_riscmem_free(dev->pci, &dev->vidq[chan_num].stopper); 448 btcx_riscmem_free(dev->pci, &dev->vidq[chan_num].stopper);
449 449
450 printk(KERN_WARNING "device %d released!\n", chan_num); 450 printk(KERN_WARNING "device %d released!\n", chan_num);
451 } 451 }
452 452
453} 453}
454 454
455 455int cx25821_video_register(struct cx25821_dev *dev, int chan_num,
456int cx25821_video_register(struct cx25821_dev *dev, int chan_num, struct video_device *video_template) 456 struct video_device *video_template)
457{ 457{
458 int err; 458 int err;
459 459
460 spin_lock_init(&dev->slock); 460 spin_lock_init(&dev->slock);
461 461
462 //printk(KERN_WARNING "Channel %d\n", chan_num); 462 //printk(KERN_WARNING "Channel %d\n", chan_num);
463 463
464#ifdef TUNER_FLAG 464#ifdef TUNER_FLAG
465 dev->tvnorm = video_template->current_norm; 465 dev->tvnorm = video_template->current_norm;
466#endif 466#endif
467 467
468 /* init video dma queues */ 468 /* init video dma queues */
469 dev->timeout_data[chan_num].dev = dev; 469 dev->timeout_data[chan_num].dev = dev;
470 dev->timeout_data[chan_num].channel = &dev->sram_channels[chan_num]; 470 dev->timeout_data[chan_num].channel = &dev->sram_channels[chan_num];
471 INIT_LIST_HEAD(&dev->vidq[chan_num].active); 471 INIT_LIST_HEAD(&dev->vidq[chan_num].active);
472 INIT_LIST_HEAD(&dev->vidq[chan_num].queued); 472 INIT_LIST_HEAD(&dev->vidq[chan_num].queued);
473 dev->vidq[chan_num].timeout.function = cx25821_vid_timeout; 473 dev->vidq[chan_num].timeout.function = cx25821_vid_timeout;
474 dev->vidq[chan_num].timeout.data = (unsigned long)&dev->timeout_data[chan_num]; 474 dev->vidq[chan_num].timeout.data =
475 init_timer(&dev->vidq[chan_num].timeout); 475 (unsigned long)&dev->timeout_data[chan_num];
476 cx25821_risc_stopper(dev->pci, &dev->vidq[chan_num].stopper, dev->sram_channels[chan_num].dma_ctl, 0x11, 0); 476 init_timer(&dev->vidq[chan_num].timeout);
477 477 cx25821_risc_stopper(dev->pci, &dev->vidq[chan_num].stopper,
478 478 dev->sram_channels[chan_num].dma_ctl, 0x11, 0);
479 /* register v4l devices */ 479
480 dev->video_dev[chan_num] = cx25821_vdev_init(dev, dev->pci, video_template, "video"); 480 /* register v4l devices */
481 err = video_register_device(dev->video_dev[chan_num], VFL_TYPE_GRABBER, video_nr[dev->nr]); 481 dev->video_dev[chan_num] =
482 482 cx25821_vdev_init(dev, dev->pci, video_template, "video");
483 if (err < 0) { 483 err =
484 goto fail_unreg; 484 video_register_device(dev->video_dev[chan_num], VFL_TYPE_GRABBER,
485 } 485 video_nr[dev->nr]);
486 486
487 //set PCI interrupt 487 if (err < 0) {
488 cx_set(PCI_INT_MSK, 0xff); 488 goto fail_unreg;
489 489 }
490 //set PCI interrupt
491 cx_set(PCI_INT_MSK, 0xff);
490 492
491 /* initial device configuration */ 493 /* initial device configuration */
492 mutex_lock(&dev->lock); 494 mutex_lock(&dev->lock);
493#ifdef TUNER_FLAG 495#ifdef TUNER_FLAG
494 cx25821_set_tvnorm(dev, dev->tvnorm); 496 cx25821_set_tvnorm(dev, dev->tvnorm);
495#endif 497#endif
496 mutex_unlock(&dev->lock); 498 mutex_unlock(&dev->lock);
497 499
498 init_controls(dev, chan_num); 500 init_controls(dev, chan_num);
499 501
500 return 0; 502 return 0;
501 503
502fail_unreg: 504 fail_unreg:
503 cx25821_video_unregister(dev, chan_num); 505 cx25821_video_unregister(dev, chan_num);
504 return err; 506 return err;
505} 507}
506 508
507int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) 509int buffer_setup(struct videobuf_queue *q, unsigned int *count,
510 unsigned int *size)
508{ 511{
509 struct cx25821_fh *fh = q->priv_data; 512 struct cx25821_fh *fh = q->priv_data;
510
511 *size = fh->fmt->depth*fh->width*fh->height >> 3;
512 513
514 *size = fh->fmt->depth * fh->width * fh->height >> 3;
513 515
514 if (0 == *count) 516 if (0 == *count)
515 *count = 32; 517 *count = 32;
516 518
517 while (*size * *count > vid_limit * 1024 * 1024) 519 while (*size * *count > vid_limit * 1024 * 1024)
518 (*count)--; 520 (*count)--;
519 521
520 return 0; 522 return 0;
521} 523}
522 524
523int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, enum v4l2_field field) 525int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
526 enum v4l2_field field)
524{ 527{
525 struct cx25821_fh *fh = q->priv_data; 528 struct cx25821_fh *fh = q->priv_data;
526 struct cx25821_dev *dev = fh->dev; 529 struct cx25821_dev *dev = fh->dev;
527 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 530 struct cx25821_buffer *buf =
528 int rc, init_buffer = 0; 531 container_of(vb, struct cx25821_buffer, vb);
529 u32 line0_offset, line1_offset; 532 int rc, init_buffer = 0;
530 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); 533 u32 line0_offset, line1_offset;
531 int bpl_local = LINE_SIZE_D1; 534 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
532 int channel_opened = 0; 535 int bpl_local = LINE_SIZE_D1;
533 536 int channel_opened = 0;
534 537
535 BUG_ON(NULL == fh->fmt); 538 BUG_ON(NULL == fh->fmt);
536 if (fh->width < 48 || fh->width > 720 || 539 if (fh->width < 48 || fh->width > 720 ||
537 fh->height < 32 || fh->height > 576) 540 fh->height < 32 || fh->height > 576)
538 return -EINVAL; 541 return -EINVAL;
539
540 buf->vb.size = (fh->width * fh->height * fh->fmt->depth) >> 3;
541
542 if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
543 return -EINVAL;
544
545
546 if (buf->fmt != fh->fmt ||
547 buf->vb.width != fh->width ||
548 buf->vb.height != fh->height ||
549 buf->vb.field != field) {
550 buf->fmt = fh->fmt;
551 buf->vb.width = fh->width;
552 buf->vb.height = fh->height;
553 buf->vb.field = field;
554 init_buffer = 1;
555 }
556
557 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
558 init_buffer = 1;
559 rc = videobuf_iolock(q, &buf->vb, NULL);
560 if (0 != rc)
561 {
562 printk(KERN_DEBUG "videobuf_iolock failed!\n");
563 goto fail;
564 }
565 }
566
567 dprintk(1, "init_buffer=%d\n", init_buffer);
568
569 if (init_buffer) {
570
571 channel_opened = dev->channel_opened;
572 channel_opened = (channel_opened < 0 || channel_opened > 7) ? 7 : channel_opened;
573 542
574 if( dev->pixel_formats[channel_opened] == PIXEL_FRMT_411 ) 543 buf->vb.size = (fh->width * fh->height * fh->fmt->depth) >> 3;
575 buf->bpl = (buf->fmt->depth * buf->vb.width) >> 3;
576 else
577 buf->bpl = (buf->fmt->depth >> 3) * (buf->vb.width);
578 544
545 if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
546 return -EINVAL;
579 547
580 if( dev->pixel_formats[channel_opened] == PIXEL_FRMT_411 ) 548 if (buf->fmt != fh->fmt ||
581 { 549 buf->vb.width != fh->width ||
582 bpl_local = buf->bpl; 550 buf->vb.height != fh->height || buf->vb.field != field) {
551 buf->fmt = fh->fmt;
552 buf->vb.width = fh->width;
553 buf->vb.height = fh->height;
554 buf->vb.field = field;
555 init_buffer = 1;
583 } 556 }
584 else 557
585 { 558 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
586 bpl_local = buf->bpl; //Default 559 init_buffer = 1;
587 560 rc = videobuf_iolock(q, &buf->vb, NULL);
588 if( channel_opened >= 0 && channel_opened <= 7 ) 561 if (0 != rc) {
589 { 562 printk(KERN_DEBUG "videobuf_iolock failed!\n");
590 if( dev->use_cif_resolution[channel_opened] ) 563 goto fail;
591 {
592 if( dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK )
593 bpl_local = 352 << 1;
594 else
595 bpl_local = dev->cif_width[channel_opened] << 1;
596 } 564 }
597 }
598 } 565 }
599 566
567 dprintk(1, "init_buffer=%d\n", init_buffer);
568
569 if (init_buffer) {
570
571 channel_opened = dev->channel_opened;
572 channel_opened = (channel_opened < 0
573 || channel_opened > 7) ? 7 : channel_opened;
574
575 if (dev->pixel_formats[channel_opened] == PIXEL_FRMT_411)
576 buf->bpl = (buf->fmt->depth * buf->vb.width) >> 3;
577 else
578 buf->bpl = (buf->fmt->depth >> 3) * (buf->vb.width);
579
580 if (dev->pixel_formats[channel_opened] == PIXEL_FRMT_411) {
581 bpl_local = buf->bpl;
582 } else {
583 bpl_local = buf->bpl; //Default
584
585 if (channel_opened >= 0 && channel_opened <= 7) {
586 if (dev->use_cif_resolution[channel_opened]) {
587 if (dev->tvnorm & V4L2_STD_PAL_BG
588 || dev->tvnorm & V4L2_STD_PAL_DK)
589 bpl_local = 352 << 1;
590 else
591 bpl_local =
592 dev->
593 cif_width[channel_opened] <<
594 1;
595 }
596 }
597 }
600 598
601 switch (buf->vb.field) { 599 switch (buf->vb.field) {
602 case V4L2_FIELD_TOP: 600 case V4L2_FIELD_TOP:
603 cx25821_risc_buffer(dev->pci, &buf->risc, 601 cx25821_risc_buffer(dev->pci, &buf->risc,
604 dma->sglist, 0, UNSET, 602 dma->sglist, 0, UNSET,
605 buf->bpl, 0, buf->vb.height); 603 buf->bpl, 0, buf->vb.height);
606 break; 604 break;
607 case V4L2_FIELD_BOTTOM: 605 case V4L2_FIELD_BOTTOM:
608 cx25821_risc_buffer(dev->pci, &buf->risc, 606 cx25821_risc_buffer(dev->pci, &buf->risc,
609 dma->sglist, UNSET, 0, 607 dma->sglist, UNSET, 0,
610 buf->bpl, 0, buf->vb.height); 608 buf->bpl, 0, buf->vb.height);
611 break; 609 break;
612 case V4L2_FIELD_INTERLACED: 610 case V4L2_FIELD_INTERLACED:
613 /* All other formats are top field first */ 611 /* All other formats are top field first */
614 line0_offset = 0; 612 line0_offset = 0;
615 line1_offset = buf->bpl; 613 line1_offset = buf->bpl;
616 dprintk(1, "top field first\n"); 614 dprintk(1, "top field first\n");
617 615
618 cx25821_risc_buffer(dev->pci, &buf->risc, 616 cx25821_risc_buffer(dev->pci, &buf->risc,
619 dma->sglist, line0_offset, 617 dma->sglist, line0_offset,
620 bpl_local, bpl_local, bpl_local, 618 bpl_local, bpl_local, bpl_local,
621 buf->vb.height >> 1); 619 buf->vb.height >> 1);
622 break; 620 break;
623 case V4L2_FIELD_SEQ_TB: 621 case V4L2_FIELD_SEQ_TB:
624 cx25821_risc_buffer(dev->pci, &buf->risc, 622 cx25821_risc_buffer(dev->pci, &buf->risc,
625 dma->sglist, 623 dma->sglist,
626 0, buf->bpl * (buf->vb.height >> 1), 624 0, buf->bpl * (buf->vb.height >> 1),
627 buf->bpl, 0, 625 buf->bpl, 0, buf->vb.height >> 1);
628 buf->vb.height >> 1); 626 break;
629 break; 627 case V4L2_FIELD_SEQ_BT:
630 case V4L2_FIELD_SEQ_BT: 628 cx25821_risc_buffer(dev->pci, &buf->risc,
631 cx25821_risc_buffer(dev->pci, &buf->risc, 629 dma->sglist,
632 dma->sglist, 630 buf->bpl * (buf->vb.height >> 1), 0,
633 buf->bpl * (buf->vb.height >> 1), 0, 631 buf->bpl, 0, buf->vb.height >> 1);
634 buf->bpl, 0, 632 break;
635 buf->vb.height >> 1); 633 default:
636 break; 634 BUG();
637 default: 635 }
638 BUG();
639 } 636 }
640 }
641 637
642 dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", 638 dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n",
643 buf, buf->vb.i, fh->width, fh->height, fh->fmt->depth, fh->fmt->name, 639 buf, buf->vb.i, fh->width, fh->height, fh->fmt->depth,
644 (unsigned long)buf->risc.dma); 640 fh->fmt->name, (unsigned long)buf->risc.dma);
645 641
646 buf->vb.state = VIDEOBUF_PREPARED; 642 buf->vb.state = VIDEOBUF_PREPARED;
647 643
648 return 0; 644 return 0;
649 645
650 fail: 646 fail:
651 cx25821_free_buffer(q, buf); 647 cx25821_free_buffer(q, buf);
652 return rc; 648 return rc;
653} 649}
654 650
655
656void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) 651void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
657{ 652{
658 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 653 struct cx25821_buffer *buf =
654 container_of(vb, struct cx25821_buffer, vb);
659 655
660 cx25821_free_buffer(q, buf); 656 cx25821_free_buffer(q, buf);
661} 657}
662 658
663
664struct videobuf_queue *get_queue(struct cx25821_fh *fh) 659struct videobuf_queue *get_queue(struct cx25821_fh *fh)
665{ 660{
666 switch (fh->type) { 661 switch (fh->type) {
667 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 662 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
668 return &fh->vidq; 663 return &fh->vidq;
669 default: 664 default:
670 BUG(); 665 BUG();
671 return NULL; 666 return NULL;
672 } 667 }
673} 668}
674 669
675int get_resource(struct cx25821_fh *fh, int resource) 670int get_resource(struct cx25821_fh *fh, int resource)
676{ 671{
677 switch (fh->type) { 672 switch (fh->type) {
678 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 673 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
679 return resource; 674 return resource;
680 default: 675 default:
681 BUG(); 676 BUG();
682 return 0; 677 return 0;
683 } 678 }
684} 679}
685 680
686
687int video_mmap(struct file *file, struct vm_area_struct *vma) 681int video_mmap(struct file *file, struct vm_area_struct *vma)
688{ 682{
689 struct cx25821_fh *fh = file->private_data; 683 struct cx25821_fh *fh = file->private_data;
690 684
691 return videobuf_mmap_mapper(get_queue(fh), vma); 685 return videobuf_mmap_mapper(get_queue(fh), vma);
692} 686}
693 687
694/* VIDEO IOCTLS */ 688/* VIDEO IOCTLS */
695int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 689int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
696{ 690{
697 struct cx25821_fh *fh = priv; 691 struct cx25821_fh *fh = priv;
698 692
699 f->fmt.pix.width = fh->width; 693 f->fmt.pix.width = fh->width;
700 f->fmt.pix.height = fh->height; 694 f->fmt.pix.height = fh->height;
701 f->fmt.pix.field = fh->vidq.field; 695 f->fmt.pix.field = fh->vidq.field;
702 f->fmt.pix.pixelformat = fh->fmt->fourcc; 696 f->fmt.pix.pixelformat = fh->fmt->fourcc;
703 f->fmt.pix.bytesperline = (f->fmt.pix.width * fh->fmt->depth) >> 3; 697 f->fmt.pix.bytesperline = (f->fmt.pix.width * fh->fmt->depth) >> 3;
704 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; 698 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
705 699
706 return 0; 700 return 0;
707} 701}
708 702
709int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 703int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
710{ 704{
711 struct cx25821_fmt *fmt; 705 struct cx25821_fmt *fmt;
712 enum v4l2_field field; 706 enum v4l2_field field;
713 unsigned int maxw, maxh; 707 unsigned int maxw, maxh;
714 708
715 fmt = format_by_fourcc(f->fmt.pix.pixelformat); 709 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
716 if (NULL == fmt) 710 if (NULL == fmt)
717 return -EINVAL; 711 return -EINVAL;
718 712
719 field = f->fmt.pix.field; 713 field = f->fmt.pix.field;
720 maxw = 720; 714 maxw = 720;
721 maxh = 576; 715 maxh = 576;
722 716
723 if (V4L2_FIELD_ANY == field) { 717 if (V4L2_FIELD_ANY == field) {
724 field = (f->fmt.pix.height > maxh/2) 718 field = (f->fmt.pix.height > maxh / 2)
725 ? V4L2_FIELD_INTERLACED 719 ? V4L2_FIELD_INTERLACED : V4L2_FIELD_TOP;
726 : V4L2_FIELD_TOP; 720 }
727 }
728 721
729 switch (field) { 722 switch (field) {
730 case V4L2_FIELD_TOP: 723 case V4L2_FIELD_TOP:
731 case V4L2_FIELD_BOTTOM: 724 case V4L2_FIELD_BOTTOM:
732 maxh = maxh / 2; 725 maxh = maxh / 2;
733 break; 726 break;
734 case V4L2_FIELD_INTERLACED: 727 case V4L2_FIELD_INTERLACED:
735 break; 728 break;
736 default: 729 default:
737 return -EINVAL; 730 return -EINVAL;
738 } 731 }
739 732
740 f->fmt.pix.field = field; 733 f->fmt.pix.field = field;
741 if (f->fmt.pix.height < 32) 734 if (f->fmt.pix.height < 32)
742 f->fmt.pix.height = 32; 735 f->fmt.pix.height = 32;
743 if (f->fmt.pix.height > maxh) 736 if (f->fmt.pix.height > maxh)
744 f->fmt.pix.height = maxh; 737 f->fmt.pix.height = maxh;
745 if (f->fmt.pix.width < 48) 738 if (f->fmt.pix.width < 48)
746 f->fmt.pix.width = 48; 739 f->fmt.pix.width = 48;
747 if (f->fmt.pix.width > maxw) 740 if (f->fmt.pix.width > maxw)
748 f->fmt.pix.width = maxw; 741 f->fmt.pix.width = maxw;
749 f->fmt.pix.width &= ~0x03; 742 f->fmt.pix.width &= ~0x03;
750 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; 743 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
751 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; 744 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
752 745
753 return 0; 746 return 0;
754} 747}
755 748
756 749int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
757
758int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
759{ 750{
760 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 751 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
761 752
762 strcpy(cap->driver, "cx25821"); 753 strcpy(cap->driver, "cx25821");
763 strlcpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card)); 754 strlcpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card));
764 sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); 755 sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci));
765 cap->version = CX25821_VERSION_CODE; 756 cap->version = CX25821_VERSION_CODE;
766 cap->capabilities = 757 cap->capabilities =
767 V4L2_CAP_VIDEO_CAPTURE | 758 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
768 V4L2_CAP_READWRITE | 759 if (UNSET != dev->tuner_type)
769 V4L2_CAP_STREAMING; 760 cap->capabilities |= V4L2_CAP_TUNER;
770 if (UNSET != dev->tuner_type) 761 return 0;
771 cap->capabilities |= V4L2_CAP_TUNER;
772 return 0;
773} 762}
774 763
775int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *f) 764int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
765 struct v4l2_fmtdesc *f)
776{ 766{
777 if (unlikely(f->index >= ARRAY_SIZE(formats))) 767 if (unlikely(f->index >= ARRAY_SIZE(formats)))
778 return -EINVAL; 768 return -EINVAL;
779 769
780 strlcpy(f->description, formats[f->index].name, sizeof(f->description)); 770 strlcpy(f->description, formats[f->index].name, sizeof(f->description));
781 f->pixelformat = formats[f->index].fourcc; 771 f->pixelformat = formats[f->index].fourcc;
782 772
783 return 0; 773 return 0;
784} 774}
785 775
786#ifdef CONFIG_VIDEO_V4L1_COMPAT 776#ifdef CONFIG_VIDEO_V4L1_COMPAT
787int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf) 777int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf)
788{ 778{
789 struct cx25821_fh *fh = priv; 779 struct cx25821_fh *fh = priv;
790 struct videobuf_queue *q; 780 struct videobuf_queue *q;
791 struct v4l2_requestbuffers req; 781 struct v4l2_requestbuffers req;
792 unsigned int i; 782 unsigned int i;
793 int err; 783 int err;
794
795 q = get_queue(fh);
796 memset(&req, 0, sizeof(req));
797 req.type = q->type;
798 req.count = 8;
799 req.memory = V4L2_MEMORY_MMAP;
800 err = videobuf_reqbufs(q, &req);
801 if (err < 0)
802 return err;
803 784
804 mbuf->frames = req.count; 785 q = get_queue(fh);
805 mbuf->size = 0; 786 memset(&req, 0, sizeof(req));
806 for (i = 0; i < mbuf->frames; i++) { 787 req.type = q->type;
807 mbuf->offsets[i] = q->bufs[i]->boff; 788 req.count = 8;
808 mbuf->size += q->bufs[i]->bsize; 789 req.memory = V4L2_MEMORY_MMAP;
809 } 790 err = videobuf_reqbufs(q, &req);
810 return 0; 791 if (err < 0)
792 return err;
793
794 mbuf->frames = req.count;
795 mbuf->size = 0;
796 for (i = 0; i < mbuf->frames; i++) {
797 mbuf->offsets[i] = q->bufs[i]->boff;
798 mbuf->size += q->bufs[i]->bsize;
799 }
800 return 0;
811} 801}
812#endif 802#endif
813 803
814int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *p) 804int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *p)
815{ 805{
816 struct cx25821_fh *fh = priv; 806 struct cx25821_fh *fh = priv;
817 return videobuf_reqbufs(get_queue(fh), p); 807 return videobuf_reqbufs(get_queue(fh), p);
818} 808}
819 809
820int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) 810int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p)
821{ 811{
822 struct cx25821_fh *fh = priv; 812 struct cx25821_fh *fh = priv;
823 return videobuf_querybuf(get_queue(fh), p); 813 return videobuf_querybuf(get_queue(fh), p);
824} 814}
825 815
826int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) 816int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p)
827{ 817{
828 struct cx25821_fh *fh = priv; 818 struct cx25821_fh *fh = priv;
829 return videobuf_qbuf(get_queue(fh), p); 819 return videobuf_qbuf(get_queue(fh), p);
830} 820}
831 821
832int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p) 822int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p)
@@ -838,8 +828,7 @@ int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p)
838 return 0; 828 return 0;
839} 829}
840 830
841int vidioc_s_priority(struct file *file, void *f, 831int vidioc_s_priority(struct file *file, void *f, enum v4l2_priority prio)
842 enum v4l2_priority prio)
843{ 832{
844 struct cx25821_fh *fh = f; 833 struct cx25821_fh *fh = f;
845 struct cx25821_dev *dev = ((struct cx25821_fh *)f)->dev; 834 struct cx25821_dev *dev = ((struct cx25821_fh *)f)->dev;
@@ -847,266 +836,257 @@ int vidioc_s_priority(struct file *file, void *f,
847 return v4l2_prio_change(&dev->prio, &fh->prio, prio); 836 return v4l2_prio_change(&dev->prio, &fh->prio, prio);
848} 837}
849 838
850
851#ifdef TUNER_FLAG 839#ifdef TUNER_FLAG
852int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *tvnorms) 840int vidioc_s_std(struct file *file, void *priv, v4l2_std_id * tvnorms)
853{ 841{
854 struct cx25821_fh *fh = priv; 842 struct cx25821_fh *fh = priv;
855 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 843 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
856 int err; 844 int err;
857 845
858 dprintk(1, "%s()\n", __func__); 846 dprintk(1, "%s()\n", __func__);
859 847
860 if (fh) 848 if (fh) {
861 { 849 err = v4l2_prio_check(&dev->prio, &fh->prio);
862 err = v4l2_prio_check(&dev->prio, &fh->prio); 850 if (0 != err)
863 if (0 != err) 851 return err;
864 return err; 852 }
865 }
866 853
867 if( dev->tvnorm == *tvnorms ) 854 if (dev->tvnorm == *tvnorms) {
868 { 855 return 0;
869 return 0; 856 }
870 }
871 857
872 mutex_lock(&dev->lock); 858 mutex_lock(&dev->lock);
873 cx25821_set_tvnorm(dev, *tvnorms); 859 cx25821_set_tvnorm(dev, *tvnorms);
874 mutex_unlock(&dev->lock); 860 mutex_unlock(&dev->lock);
875 861
876 medusa_set_videostandard(dev); 862 medusa_set_videostandard(dev);
877 863
878 return 0; 864 return 0;
879} 865}
880#endif 866#endif
881 867
882int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i) 868int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i)
883{ 869{
884 static const char *iname[] = { 870 static const char *iname[] = {
885 [CX25821_VMUX_COMPOSITE] = "Composite", 871 [CX25821_VMUX_COMPOSITE] = "Composite",
886 [CX25821_VMUX_SVIDEO] = "S-Video", 872 [CX25821_VMUX_SVIDEO] = "S-Video",
887 [CX25821_VMUX_DEBUG] = "for debug only", 873 [CX25821_VMUX_DEBUG] = "for debug only",
888 }; 874 };
889 unsigned int n; 875 unsigned int n;
890 dprintk(1, "%s()\n", __func__); 876 dprintk(1, "%s()\n", __func__);
891
892 n = i->index;
893 if (n > 2)
894 return -EINVAL;
895 877
896 if (0 == INPUT(n)->type) 878 n = i->index;
897 return -EINVAL; 879 if (n > 2)
880 return -EINVAL;
881
882 if (0 == INPUT(n)->type)
883 return -EINVAL;
898 884
899 memset(i, 0, sizeof(*i)); 885 memset(i, 0, sizeof(*i));
900 i->index = n; 886 i->index = n;
901 i->type = V4L2_INPUT_TYPE_CAMERA; 887 i->type = V4L2_INPUT_TYPE_CAMERA;
902 strcpy(i->name, iname[INPUT(n)->type]); 888 strcpy(i->name, iname[INPUT(n)->type]);
903 889
904 i->std = CX25821_NORMS; 890 i->std = CX25821_NORMS;
905 return 0; 891 return 0;
906} 892}
907 893
908int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *i) 894int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *i)
909{ 895{
910 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 896 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
911 dprintk(1, "%s()\n", __func__); 897 dprintk(1, "%s()\n", __func__);
912 return cx25821_enum_input(dev, i); 898 return cx25821_enum_input(dev, i);
913} 899}
914 900
915int vidioc_g_input(struct file *file, void *priv, unsigned int *i) 901int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
916{ 902{
917 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 903 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
918 904
919 *i = dev->input; 905 *i = dev->input;
920 dprintk(1, "%s() returns %d\n", __func__, *i); 906 dprintk(1, "%s() returns %d\n", __func__, *i);
921 return 0; 907 return 0;
922} 908}
923 909
924
925int vidioc_s_input(struct file *file, void *priv, unsigned int i) 910int vidioc_s_input(struct file *file, void *priv, unsigned int i)
926{ 911{
927 struct cx25821_fh *fh = priv; 912 struct cx25821_fh *fh = priv;
928 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 913 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
929 int err; 914 int err;
930 915
931 dprintk(1, "%s(%d)\n", __func__, i); 916 dprintk(1, "%s(%d)\n", __func__, i);
932 917
933 if (fh) 918 if (fh) {
934 { 919 err = v4l2_prio_check(&dev->prio, &fh->prio);
935 err = v4l2_prio_check(&dev->prio, &fh->prio); 920 if (0 != err)
936 if (0 != err) 921 return err;
937 return err; 922 }
938 }
939 923
940 if (i > 2) { 924 if (i > 2) {
941 dprintk(1, "%s() -EINVAL\n", __func__); 925 dprintk(1, "%s() -EINVAL\n", __func__);
942 return -EINVAL; 926 return -EINVAL;
943 } 927 }
944 928
945 mutex_lock(&dev->lock); 929 mutex_lock(&dev->lock);
946 cx25821_video_mux(dev, i); 930 cx25821_video_mux(dev, i);
947 mutex_unlock(&dev->lock); 931 mutex_unlock(&dev->lock);
948 return 0; 932 return 0;
949} 933}
950 934
951#ifdef TUNER_FLAG 935#ifdef TUNER_FLAG
952int vidioc_g_frequency(struct file *file, void *priv, struct v4l2_frequency *f) 936int vidioc_g_frequency(struct file *file, void *priv, struct v4l2_frequency *f)
953{ 937{
954 struct cx25821_fh *fh = priv; 938 struct cx25821_fh *fh = priv;
955 struct cx25821_dev *dev = fh->dev; 939 struct cx25821_dev *dev = fh->dev;
956 940
957 f->frequency = dev->freq; 941 f->frequency = dev->freq;
958 942
959 cx25821_call_all(dev, tuner, g_frequency, f); 943 cx25821_call_all(dev, tuner, g_frequency, f);
960 944
961 return 0; 945 return 0;
962} 946}
963 947
964int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f) 948int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f)
965{ 949{
966 mutex_lock(&dev->lock); 950 mutex_lock(&dev->lock);
967 dev->freq = f->frequency; 951 dev->freq = f->frequency;
968 952
969 cx25821_call_all(dev, tuner, s_frequency, f); 953 cx25821_call_all(dev, tuner, s_frequency, f);
970 954
971 /* When changing channels it is required to reset TVAUDIO */ 955 /* When changing channels it is required to reset TVAUDIO */
972 msleep(10); 956 msleep(10);
973 957
974 mutex_unlock(&dev->lock); 958 mutex_unlock(&dev->lock);
975 959
976 return 0; 960 return 0;
977} 961}
978 962
979int vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f) 963int vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f)
980{ 964{
981 struct cx25821_fh *fh = priv; 965 struct cx25821_fh *fh = priv;
982 struct cx25821_dev *dev = fh->dev; 966 struct cx25821_dev *dev = fh->dev;
983 int err; 967 int err;
984
985 if (fh)
986 {
987 err = v4l2_prio_check(&dev->prio, &fh->prio);
988 if (0 != err)
989 return err;
990 }
991 968
992 return cx25821_set_freq(dev, f); 969 if (fh) {
970 err = v4l2_prio_check(&dev->prio, &fh->prio);
971 if (0 != err)
972 return err;
973 }
974
975 return cx25821_set_freq(dev, f);
993} 976}
994#endif 977#endif
995 978
996#ifdef CONFIG_VIDEO_ADV_DEBUG 979#ifdef CONFIG_VIDEO_ADV_DEBUG
997int vidioc_g_register(struct file *file, void *fh, 980int vidioc_g_register(struct file *file, void *fh,
998 struct v4l2_dbg_register *reg) 981 struct v4l2_dbg_register *reg)
999{ 982{
1000 struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev; 983 struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev;
1001 984
1002 if (!v4l2_chip_match_host(&reg->match)) 985 if (!v4l2_chip_match_host(&reg->match))
1003 return -EINVAL; 986 return -EINVAL;
1004 987
1005 cx25821_call_all(dev, core, g_register, reg); 988 cx25821_call_all(dev, core, g_register, reg);
1006 989
1007 return 0; 990 return 0;
1008} 991}
1009 992
1010int vidioc_s_register(struct file *file, void *fh, 993int vidioc_s_register(struct file *file, void *fh,
1011 struct v4l2_dbg_register *reg) 994 struct v4l2_dbg_register *reg)
1012{ 995{
1013 struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev; 996 struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev;
1014 997
1015 if (!v4l2_chip_match_host(&reg->match)) 998 if (!v4l2_chip_match_host(&reg->match))
1016 return -EINVAL; 999 return -EINVAL;
1017 1000
1018 cx25821_call_all(dev, core, s_register, reg); 1001 cx25821_call_all(dev, core, s_register, reg);
1019 1002
1020 return 0; 1003 return 0;
1021} 1004}
1022 1005
1023#endif 1006#endif
1024 1007
1025
1026#ifdef TUNER_FLAG 1008#ifdef TUNER_FLAG
1027int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t) 1009int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1028{ 1010{
1029 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 1011 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1030 1012
1031 if (unlikely(UNSET == dev->tuner_type)) 1013 if (unlikely(UNSET == dev->tuner_type))
1032 return -EINVAL; 1014 return -EINVAL;
1033 if (0 != t->index) 1015 if (0 != t->index)
1034 return -EINVAL; 1016 return -EINVAL;
1035 1017
1036 strcpy(t->name, "Television"); 1018 strcpy(t->name, "Television");
1037 t->type = V4L2_TUNER_ANALOG_TV; 1019 t->type = V4L2_TUNER_ANALOG_TV;
1038 t->capability = V4L2_TUNER_CAP_NORM; 1020 t->capability = V4L2_TUNER_CAP_NORM;
1039 t->rangehigh = 0xffffffffUL; 1021 t->rangehigh = 0xffffffffUL;
1040 1022
1041 t->signal = 0xffff ; /* LOCKED */ 1023 t->signal = 0xffff; /* LOCKED */
1042 return 0; 1024 return 0;
1043} 1025}
1044 1026
1045int vidioc_s_tuner(struct file *file, void *priv, 1027int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1046 struct v4l2_tuner *t)
1047{ 1028{
1048 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 1029 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1049 struct cx25821_fh *fh = priv; 1030 struct cx25821_fh *fh = priv;
1050 int err; 1031 int err;
1051
1052 if (fh)
1053 {
1054 err = v4l2_prio_check(&dev->prio, &fh->prio);
1055 if (0 != err)
1056 return err;
1057 }
1058 1032
1059 dprintk(1, "%s()\n", __func__); 1033 if (fh) {
1060 if (UNSET == dev->tuner_type) 1034 err = v4l2_prio_check(&dev->prio, &fh->prio);
1061 return -EINVAL; 1035 if (0 != err)
1062 if (0 != t->index) 1036 return err;
1063 return -EINVAL; 1037 }
1064 1038
1065 return 0; 1039 dprintk(1, "%s()\n", __func__);
1040 if (UNSET == dev->tuner_type)
1041 return -EINVAL;
1042 if (0 != t->index)
1043 return -EINVAL;
1044
1045 return 0;
1066} 1046}
1067 1047
1068#endif 1048#endif
1069// ****************************************************************************************** 1049// ******************************************************************************************
1070static const struct v4l2_queryctrl no_ctl = { 1050static const struct v4l2_queryctrl no_ctl = {
1071 .name = "42", 1051 .name = "42",
1072 .flags = V4L2_CTRL_FLAG_DISABLED, 1052 .flags = V4L2_CTRL_FLAG_DISABLED,
1073}; 1053};
1074 1054
1075static struct v4l2_queryctrl cx25821_ctls[] = { 1055static struct v4l2_queryctrl cx25821_ctls[] = {
1076 /* --- video --- */ 1056 /* --- video --- */
1077 { 1057 {
1078 .id = V4L2_CID_BRIGHTNESS, 1058 .id = V4L2_CID_BRIGHTNESS,
1079 .name = "Brightness", 1059 .name = "Brightness",
1080 .minimum = 0, 1060 .minimum = 0,
1081 .maximum = 10000, 1061 .maximum = 10000,
1082 .step = 1, 1062 .step = 1,
1083 .default_value = 6200, 1063 .default_value = 6200,
1084 .type = V4L2_CTRL_TYPE_INTEGER, 1064 .type = V4L2_CTRL_TYPE_INTEGER,
1085 },{ 1065 }, {
1086 .id = V4L2_CID_CONTRAST, 1066 .id = V4L2_CID_CONTRAST,
1087 .name = "Contrast", 1067 .name = "Contrast",
1088 .minimum = 0, 1068 .minimum = 0,
1089 .maximum = 10000, 1069 .maximum = 10000,
1090 .step = 1, 1070 .step = 1,
1091 .default_value = 5000, 1071 .default_value = 5000,
1092 .type = V4L2_CTRL_TYPE_INTEGER, 1072 .type = V4L2_CTRL_TYPE_INTEGER,
1093 },{ 1073 }, {
1094 .id = V4L2_CID_SATURATION, 1074 .id = V4L2_CID_SATURATION,
1095 .name = "Saturation", 1075 .name = "Saturation",
1096 .minimum = 0, 1076 .minimum = 0,
1097 .maximum = 10000, 1077 .maximum = 10000,
1098 .step = 1, 1078 .step = 1,
1099 .default_value = 5000, 1079 .default_value = 5000,
1100 .type = V4L2_CTRL_TYPE_INTEGER, 1080 .type = V4L2_CTRL_TYPE_INTEGER,
1101 },{ 1081 }, {
1102 .id = V4L2_CID_HUE, 1082 .id = V4L2_CID_HUE,
1103 .name = "Hue", 1083 .name = "Hue",
1104 .minimum = 0, 1084 .minimum = 0,
1105 .maximum = 10000, 1085 .maximum = 10000,
1106 .step = 1, 1086 .step = 1,
1107 .default_value = 5000, 1087 .default_value = 5000,
1108 .type = V4L2_CTRL_TYPE_INTEGER, 1088 .type = V4L2_CTRL_TYPE_INTEGER,
1109 } 1089 }
1110}; 1090};
1111static const int CX25821_CTLS = ARRAY_SIZE(cx25821_ctls); 1091static const int CX25821_CTLS = ARRAY_SIZE(cx25821_ctls);
1112 1092
@@ -1114,8 +1094,7 @@ static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl)
1114{ 1094{
1115 int i; 1095 int i;
1116 1096
1117 if (qctrl->id < V4L2_CID_BASE || 1097 if (qctrl->id < V4L2_CID_BASE || qctrl->id >= V4L2_CID_LASTP1)
1118 qctrl->id >= V4L2_CID_LASTP1)
1119 return -EINVAL; 1098 return -EINVAL;
1120 for (i = 0; i < CX25821_CTLS; i++) 1099 for (i = 0; i < CX25821_CTLS; i++)
1121 if (cx25821_ctls[i].id == qctrl->id) 1100 if (cx25821_ctls[i].id == qctrl->id)
@@ -1129,7 +1108,7 @@ static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl)
1129} 1108}
1130 1109
1131int vidioc_queryctrl(struct file *file, void *priv, 1110int vidioc_queryctrl(struct file *file, void *priv,
1132 struct v4l2_queryctrl *qctrl) 1111 struct v4l2_queryctrl *qctrl)
1133{ 1112{
1134 return cx25821_ctrl_query(qctrl); 1113 return cx25821_ctrl_query(qctrl);
1135} 1114}
@@ -1137,40 +1116,37 @@ int vidioc_queryctrl(struct file *file, void *priv,
1137/* ------------------------------------------------------------------ */ 1116/* ------------------------------------------------------------------ */
1138/* VIDEO CTRL IOCTLS */ 1117/* VIDEO CTRL IOCTLS */
1139 1118
1140static const struct v4l2_queryctrl* ctrl_by_id(unsigned int id) 1119static const struct v4l2_queryctrl *ctrl_by_id(unsigned int id)
1141{ 1120{
1142 unsigned int i; 1121 unsigned int i;
1143 1122
1144 for (i = 0; i < CX25821_CTLS; i++) 1123 for (i = 0; i < CX25821_CTLS; i++)
1145 if (cx25821_ctls[i].id == id) 1124 if (cx25821_ctls[i].id == id)
1146 return cx25821_ctls+i; 1125 return cx25821_ctls + i;
1147 return NULL; 1126 return NULL;
1148} 1127}
1149 1128
1150int vidioc_g_ctrl(struct file *file, 1129int vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctl)
1151 void *priv,
1152 struct v4l2_control *ctl)
1153{ 1130{
1154 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 1131 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1155 1132
1156 const struct v4l2_queryctrl* ctrl; 1133 const struct v4l2_queryctrl *ctrl;
1157 1134
1158 ctrl = ctrl_by_id(ctl->id); 1135 ctrl = ctrl_by_id(ctl->id);
1159 1136
1160 if (NULL == ctrl) 1137 if (NULL == ctrl)
1161 return -EINVAL; 1138 return -EINVAL;
1162 switch (ctl->id) 1139 switch (ctl->id) {
1163 { 1140 case V4L2_CID_BRIGHTNESS:
1164 case V4L2_CID_BRIGHTNESS:
1165 ctl->value = dev->ctl_bright; 1141 ctl->value = dev->ctl_bright;
1166 break; 1142 break;
1167 case V4L2_CID_HUE: 1143 case V4L2_CID_HUE:
1168 ctl->value = dev->ctl_hue; 1144 ctl->value = dev->ctl_hue;
1169 break; 1145 break;
1170 case V4L2_CID_CONTRAST: 1146 case V4L2_CID_CONTRAST:
1171 ctl->value = dev->ctl_contrast; 1147 ctl->value = dev->ctl_contrast;
1172 break; 1148 break;
1173 case V4L2_CID_SATURATION: 1149 case V4L2_CID_SATURATION:
1174 ctl->value = dev->ctl_saturation; 1150 ctl->value = dev->ctl_saturation;
1175 break; 1151 break;
1176 } 1152 }
@@ -1178,10 +1154,10 @@ int vidioc_g_ctrl(struct file *file,
1178} 1154}
1179 1155
1180int cx25821_set_control(struct cx25821_dev *dev, 1156int cx25821_set_control(struct cx25821_dev *dev,
1181 struct v4l2_control *ctl, int chan_num) 1157 struct v4l2_control *ctl, int chan_num)
1182{ 1158{
1183 int err; 1159 int err;
1184 const struct v4l2_queryctrl* ctrl; 1160 const struct v4l2_queryctrl *ctrl;
1185 1161
1186 err = -EINVAL; 1162 err = -EINVAL;
1187 1163
@@ -1190,35 +1166,33 @@ int cx25821_set_control(struct cx25821_dev *dev,
1190 if (NULL == ctrl) 1166 if (NULL == ctrl)
1191 return err; 1167 return err;
1192 1168
1193 switch (ctrl->type) 1169 switch (ctrl->type) {
1194 { 1170 case V4L2_CTRL_TYPE_BOOLEAN:
1195 case V4L2_CTRL_TYPE_BOOLEAN: 1171 case V4L2_CTRL_TYPE_MENU:
1196 case V4L2_CTRL_TYPE_MENU: 1172 case V4L2_CTRL_TYPE_INTEGER:
1197 case V4L2_CTRL_TYPE_INTEGER:
1198 if (ctl->value < ctrl->minimum) 1173 if (ctl->value < ctrl->minimum)
1199 ctl->value = ctrl->minimum; 1174 ctl->value = ctrl->minimum;
1200 if (ctl->value > ctrl->maximum) 1175 if (ctl->value > ctrl->maximum)
1201 ctl->value = ctrl->maximum; 1176 ctl->value = ctrl->maximum;
1202 break; 1177 break;
1203 default: 1178 default:
1204 /* nothing */; 1179 /* nothing */ ;
1205 }; 1180 };
1206 1181
1207 switch (ctl->id) 1182 switch (ctl->id) {
1208 { 1183 case V4L2_CID_BRIGHTNESS:
1209 case V4L2_CID_BRIGHTNESS:
1210 dev->ctl_bright = ctl->value; 1184 dev->ctl_bright = ctl->value;
1211 medusa_set_brightness(dev, ctl->value, chan_num); 1185 medusa_set_brightness(dev, ctl->value, chan_num);
1212 break; 1186 break;
1213 case V4L2_CID_HUE: 1187 case V4L2_CID_HUE:
1214 dev->ctl_hue = ctl->value; 1188 dev->ctl_hue = ctl->value;
1215 medusa_set_hue(dev, ctl->value, chan_num); 1189 medusa_set_hue(dev, ctl->value, chan_num);
1216 break; 1190 break;
1217 case V4L2_CID_CONTRAST: 1191 case V4L2_CID_CONTRAST:
1218 dev->ctl_contrast = ctl->value; 1192 dev->ctl_contrast = ctl->value;
1219 medusa_set_contrast(dev, ctl->value, chan_num); 1193 medusa_set_contrast(dev, ctl->value, chan_num);
1220 break; 1194 break;
1221 case V4L2_CID_SATURATION: 1195 case V4L2_CID_SATURATION:
1222 dev->ctl_saturation = ctl->value; 1196 dev->ctl_saturation = ctl->value;
1223 medusa_set_saturation(dev, ctl->value, chan_num); 1197 medusa_set_saturation(dev, ctl->value, chan_num);
1224 break; 1198 break;
@@ -1241,9 +1215,7 @@ static void init_controls(struct cx25821_dev *dev, int chan_num)
1241 } 1215 }
1242} 1216}
1243 1217
1244int vidioc_cropcap(struct file *file, 1218int vidioc_cropcap(struct file *file, void *priv, struct v4l2_cropcap *cropcap)
1245 void *priv,
1246 struct v4l2_cropcap *cropcap)
1247{ 1219{
1248 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 1220 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1249 1221
@@ -1252,86 +1224,76 @@ int vidioc_cropcap(struct file *file,
1252 cropcap->bounds.top = cropcap->bounds.left = 0; 1224 cropcap->bounds.top = cropcap->bounds.left = 0;
1253 cropcap->bounds.width = 720; 1225 cropcap->bounds.width = 720;
1254 cropcap->bounds.height = dev->tvnorm == V4L2_STD_PAL_BG ? 576 : 480; 1226 cropcap->bounds.height = dev->tvnorm == V4L2_STD_PAL_BG ? 576 : 480;
1255 cropcap->pixelaspect.numerator = dev->tvnorm == V4L2_STD_PAL_BG ? 59 : 10; 1227 cropcap->pixelaspect.numerator =
1256 cropcap->pixelaspect.denominator = dev->tvnorm == V4L2_STD_PAL_BG ? 54 : 11; 1228 dev->tvnorm == V4L2_STD_PAL_BG ? 59 : 10;
1229 cropcap->pixelaspect.denominator =
1230 dev->tvnorm == V4L2_STD_PAL_BG ? 54 : 11;
1257 cropcap->defrect = cropcap->bounds; 1231 cropcap->defrect = cropcap->bounds;
1258 return 0; 1232 return 0;
1259} 1233}
1260 1234
1261int vidioc_s_crop(struct file *file, 1235int vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop)
1262 void *priv,
1263 struct v4l2_crop *crop)
1264{ 1236{
1265 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 1237 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1266 struct cx25821_fh *fh = priv; 1238 struct cx25821_fh *fh = priv;
1267 int err; 1239 int err;
1268 1240
1269 if (fh) 1241 if (fh) {
1270 { 1242 err = v4l2_prio_check(&dev->prio, &fh->prio);
1271 err = v4l2_prio_check(&dev->prio, &fh->prio); 1243 if (0 != err)
1272 if (0 != err) 1244 return err;
1273 return err; 1245 }
1274 } 1246 // vidioc_s_crop not supported
1275 // vidioc_s_crop not supported 1247 return -EINVAL;
1276 return -EINVAL;
1277} 1248}
1278 1249
1279int vidioc_g_crop(struct file *file, 1250int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop)
1280 void *priv,
1281 struct v4l2_crop *crop)
1282{ 1251{
1283 // vidioc_g_crop not supported 1252 // vidioc_g_crop not supported
1284 return -EINVAL; 1253 return -EINVAL;
1285} 1254}
1286 1255
1287int vidioc_querystd(struct file *file, 1256int vidioc_querystd(struct file *file, void *priv, v4l2_std_id * norm)
1288 void *priv,
1289 v4l2_std_id *norm)
1290{ 1257{
1291 // medusa does not support video standard sensing of current input 1258 // medusa does not support video standard sensing of current input
1292 *norm = CX25821_NORMS; 1259 *norm = CX25821_NORMS;
1293 1260
1294 return 0; 1261 return 0;
1295} 1262}
1296 1263
1297int is_valid_width(u32 width, v4l2_std_id tvnorm) 1264int is_valid_width(u32 width, v4l2_std_id tvnorm)
1298{ 1265{
1299 if(tvnorm == V4L2_STD_PAL_BG) 1266 if (tvnorm == V4L2_STD_PAL_BG) {
1300 { 1267 if (width == 352 || width == 720)
1301 if (width == 352 || width == 720) 1268 return 1;
1302 return 1; 1269 else
1303 else 1270 return 0;
1304 return 0; 1271 }
1305 }
1306 1272
1307 if(tvnorm == V4L2_STD_NTSC_M) 1273 if (tvnorm == V4L2_STD_NTSC_M) {
1308 { 1274 if (width == 320 || width == 352 || width == 720)
1309 if (width == 320 || width == 352 || width == 720) 1275 return 1;
1310 return 1; 1276 else
1311 else 1277 return 0;
1312 return 0; 1278 }
1313 } 1279 return 0;
1314 return 0;
1315} 1280}
1316 1281
1317int is_valid_height(u32 height, v4l2_std_id tvnorm) 1282int is_valid_height(u32 height, v4l2_std_id tvnorm)
1318{ 1283{
1319 if(tvnorm == V4L2_STD_PAL_BG) 1284 if (tvnorm == V4L2_STD_PAL_BG) {
1320 { 1285 if (height == 576 || height == 288)
1321 if (height == 576 || height == 288) 1286 return 1;
1322 return 1; 1287 else
1323 else 1288 return 0;
1324 return 0; 1289 }
1325 }
1326 1290
1327 if(tvnorm == V4L2_STD_NTSC_M) 1291 if (tvnorm == V4L2_STD_NTSC_M) {
1328 { 1292 if (height == 480 || height == 240)
1329 if (height == 480 || height == 240) 1293 return 1;
1330 return 1; 1294 else
1331 else 1295 return 0;
1332 return 0; 1296 }
1333 }
1334 1297
1335 return 0; 1298 return 0;
1336} 1299}
1337
diff --git a/drivers/staging/cx25821/cx25821-video.h b/drivers/staging/cx25821/cx25821-video.h
index 8b162014d8ff..4417ff5d90d4 100644
--- a/drivers/staging/cx25821/cx25821-video.h
+++ b/drivers/staging/cx25821/cx25821-video.h
@@ -24,7 +24,6 @@
24#ifndef CX25821_VIDEO_H_ 24#ifndef CX25821_VIDEO_H_
25#define CX25821_VIDEO_H_ 25#define CX25821_VIDEO_H_
26 26
27
28#include <linux/init.h> 27#include <linux/init.h>
29#include <linux/list.h> 28#include <linux/list.h>
30#include <linux/module.h> 29#include <linux/module.h>
@@ -55,7 +54,6 @@
55 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ 54 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
56 } while (0) 55 } while (0)
57 56
58
59//For IOCTL to identify running upstream 57//For IOCTL to identify running upstream
60#define UPSTREAM_START_VIDEO 700 58#define UPSTREAM_START_VIDEO 700
61#define UPSTREAM_STOP_VIDEO 701 59#define UPSTREAM_STOP_VIDEO 701
@@ -96,62 +94,82 @@ extern struct video_device cx25821_video_template11;
96extern struct video_device cx25821_videoioctl_template; 94extern struct video_device cx25821_videoioctl_template;
97//extern const u32 *ctrl_classes[]; 95//extern const u32 *ctrl_classes[];
98 96
99extern unsigned int vid_limit; 97extern unsigned int vid_limit;
100 98
101#define FORMAT_FLAGS_PACKED 0x01 99#define FORMAT_FLAGS_PACKED 0x01
102extern struct cx25821_fmt formats[]; 100extern struct cx25821_fmt formats[];
103extern struct cx25821_fmt *format_by_fourcc(unsigned int fourcc); 101extern struct cx25821_fmt *format_by_fourcc(unsigned int fourcc);
104extern struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM]; 102extern struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM];
105 103
106extern void dump_video_queue(struct cx25821_dev *dev, struct cx25821_dmaqueue *q); 104extern void dump_video_queue(struct cx25821_dev *dev,
107extern void cx25821_video_wakeup(struct cx25821_dev *dev, struct cx25821_dmaqueue *q, u32 count); 105 struct cx25821_dmaqueue *q);
106extern void cx25821_video_wakeup(struct cx25821_dev *dev,
107 struct cx25821_dmaqueue *q, u32 count);
108 108
109#ifdef TUNER_FLAG 109#ifdef TUNER_FLAG
110extern int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm); 110extern int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm);
111#endif 111#endif
112 112
113 113extern int res_get(struct cx25821_dev *dev, struct cx25821_fh *fh,
114extern int res_get(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bit); 114 unsigned int bit);
115extern int res_check(struct cx25821_fh *fh, unsigned int bit); 115extern int res_check(struct cx25821_fh *fh, unsigned int bit);
116extern int res_locked(struct cx25821_dev *dev, unsigned int bit); 116extern int res_locked(struct cx25821_dev *dev, unsigned int bit);
117extern void res_free(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bits); 117extern void res_free(struct cx25821_dev *dev, struct cx25821_fh *fh,
118 unsigned int bits);
118extern int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input); 119extern int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input);
119extern int cx25821_start_video_dma(struct cx25821_dev *dev, 120extern int cx25821_start_video_dma(struct cx25821_dev *dev,
120 struct cx25821_dmaqueue *q, 121 struct cx25821_dmaqueue *q,
121 struct cx25821_buffer *buf, 122 struct cx25821_buffer *buf,
122 struct sram_channel *channel); 123 struct sram_channel *channel);
123 124
124extern int cx25821_set_scale(struct cx25821_dev *dev, unsigned int width, unsigned int height, enum v4l2_field field); 125extern int cx25821_set_scale(struct cx25821_dev *dev, unsigned int width,
126 unsigned int height, enum v4l2_field field);
125extern int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status); 127extern int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status);
126extern void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num); 128extern void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num);
127extern int cx25821_video_register(struct cx25821_dev *dev, int chan_num, struct video_device *video_template); 129extern int cx25821_video_register(struct cx25821_dev *dev, int chan_num,
130 struct video_device *video_template);
128extern int get_format_size(void); 131extern int get_format_size(void);
129 132
130extern int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size); 133extern int buffer_setup(struct videobuf_queue *q, unsigned int *count,
131extern int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, enum v4l2_field field); 134 unsigned int *size);
132extern void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb); 135extern int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
136 enum v4l2_field field);
137extern void buffer_release(struct videobuf_queue *q,
138 struct videobuf_buffer *vb);
133extern struct videobuf_queue *get_queue(struct cx25821_fh *fh); 139extern struct videobuf_queue *get_queue(struct cx25821_fh *fh);
134extern int get_resource(struct cx25821_fh *fh, int resource); 140extern int get_resource(struct cx25821_fh *fh, int resource);
135extern int video_mmap(struct file *file, struct vm_area_struct *vma); 141extern int video_mmap(struct file *file, struct vm_area_struct *vma);
136extern int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f); 142extern int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
137extern int vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap); 143 struct v4l2_format *f);
138extern int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *f); 144extern int vidioc_querycap(struct file *file, void *priv,
145 struct v4l2_capability *cap);
146extern int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
147 struct v4l2_fmtdesc *f);
139extern int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf); 148extern int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf);
140extern int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *p); 149extern int vidioc_reqbufs(struct file *file, void *priv,
141extern int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p); 150 struct v4l2_requestbuffers *p);
151extern int vidioc_querybuf(struct file *file, void *priv,
152 struct v4l2_buffer *p);
142extern int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p); 153extern int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p);
143extern int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *tvnorms); 154extern int vidioc_s_std(struct file *file, void *priv, v4l2_std_id * tvnorms);
144extern int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i); 155extern int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i);
145extern int vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *i); 156extern int vidioc_enum_input(struct file *file, void *priv,
157 struct v4l2_input *i);
146extern int vidioc_g_input(struct file *file, void *priv, unsigned int *i); 158extern int vidioc_g_input(struct file *file, void *priv, unsigned int *i);
147extern int vidioc_s_input(struct file *file, void *priv, unsigned int i); 159extern int vidioc_s_input(struct file *file, void *priv, unsigned int i);
148extern int vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctl); 160extern int vidioc_g_ctrl(struct file *file, void *priv,
149extern int vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f); 161 struct v4l2_control *ctl);
150extern int vidioc_g_frequency(struct file *file, void *priv, struct v4l2_frequency *f); 162extern int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
163 struct v4l2_format *f);
164extern int vidioc_g_frequency(struct file *file, void *priv,
165 struct v4l2_frequency *f);
151extern int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f); 166extern int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f);
152extern int vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f); 167extern int vidioc_s_frequency(struct file *file, void *priv,
153extern int vidioc_g_register(struct file *file, void *fh, struct v4l2_dbg_register *reg); 168 struct v4l2_frequency *f);
154extern int vidioc_s_register(struct file *file, void *fh, struct v4l2_dbg_register *reg); 169extern int vidioc_g_register(struct file *file, void *fh,
170 struct v4l2_dbg_register *reg);
171extern int vidioc_s_register(struct file *file, void *fh,
172 struct v4l2_dbg_register *reg);
155extern int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t); 173extern int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t);
156extern int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t); 174extern int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t);
157 175
@@ -159,14 +177,18 @@ extern int is_valid_width(u32 width, v4l2_std_id tvnorm);
159extern int is_valid_height(u32 height, v4l2_std_id tvnorm); 177extern int is_valid_height(u32 height, v4l2_std_id tvnorm);
160 178
161extern int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p); 179extern int vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p);
162extern int vidioc_s_priority(struct file *file, void *f, enum v4l2_priority prio); 180extern int vidioc_s_priority(struct file *file, void *f,
181 enum v4l2_priority prio);
163 182
164extern int vidioc_queryctrl(struct file *file, void *priv, struct v4l2_queryctrl *qctrl); 183extern int vidioc_queryctrl(struct file *file, void *priv,
165extern int cx25821_set_control(struct cx25821_dev *dev, struct v4l2_control *ctrl, int chan_num); 184 struct v4l2_queryctrl *qctrl);
185extern int cx25821_set_control(struct cx25821_dev *dev,
186 struct v4l2_control *ctrl, int chan_num);
166 187
167extern int vidioc_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cropcap); 188extern int vidioc_cropcap(struct file *file, void *fh,
189 struct v4l2_cropcap *cropcap);
168extern int vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop); 190extern int vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop);
169extern int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop); 191extern int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop);
170 192
171extern int vidioc_querystd(struct file *file, void *priv, v4l2_std_id *norm); 193extern int vidioc_querystd(struct file *file, void *priv, v4l2_std_id * norm);
172#endif 194#endif
diff --git a/drivers/staging/cx25821/cx25821-video0.c b/drivers/staging/cx25821/cx25821-video0.c
index 92b5eb937d29..950fac1d7003 100644
--- a/drivers/staging/cx25821/cx25821-video0.c
+++ b/drivers/staging/cx25821/cx25821-video0.c
@@ -23,359 +23,356 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH00]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH00];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH00]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[SRAM_CH00]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 u32 pix_format; 102 u32 pix_format;
99 103
100 lock_kernel(); 104 lock_kernel();
101 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
102 { 106 h = list_entry(list, struct cx25821_dev, devlist);
103 h = list_entry(list, struct cx25821_dev, devlist); 107
104 108 if (h->video_dev[SRAM_CH00]
105 if (h->video_dev[SRAM_CH00] && h->video_dev[SRAM_CH00]->minor == minor) 109 && h->video_dev[SRAM_CH00]->minor == minor) {
106 { 110 dev = h;
107 dev = h; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
108 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 112 }
109 } 113 }
110 }
111 114
112 if (NULL == dev) { 115 if (NULL == dev) {
113 unlock_kernel(); 116 unlock_kernel();
114 return -ENODEV; 117 return -ENODEV;
115 } 118 }
116 119
117 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
118 121
119 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
120 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
121 if (NULL == fh) { 124 if (NULL == fh) {
122 unlock_kernel(); 125 unlock_kernel();
123 return -ENOMEM; 126 return -ENOMEM;
124 } 127 }
125 128
126 file->private_data = fh; 129 file->private_data = fh;
127 fh->dev = dev; 130 fh->dev = dev;
128 fh->type = type; 131 fh->type = type;
129 fh->width = 720; 132 fh->width = 720;
130 133
131 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 134 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
132 fh->height = 576; 135 fh->height = 576;
133 else 136 else
134 fh->height = 480; 137 fh->height = 480;
135 138
136 dev->channel_opened = SRAM_CH00; 139 dev->channel_opened = SRAM_CH00;
137 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; 140 pix_format =
138 fh->fmt = format_by_fourcc(pix_format); 141 (dev->pixel_formats[dev->channel_opened] ==
142 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
143 fh->fmt = format_by_fourcc(pix_format);
139 144
140 v4l2_prio_open(&dev->prio,&fh->prio); 145 v4l2_prio_open(&dev->prio, &fh->prio);
141 146
142 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, 147 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
143 &dev->pci->dev, &dev->slock, 148 &dev->pci->dev, &dev->slock,
144 V4L2_BUF_TYPE_VIDEO_CAPTURE, 149 V4L2_BUF_TYPE_VIDEO_CAPTURE,
145 V4L2_FIELD_INTERLACED, 150 V4L2_FIELD_INTERLACED,
146 sizeof(struct cx25821_buffer), 151 sizeof(struct cx25821_buffer), fh);
147 fh);
148 152
149 dprintk(1, "post videobuf_queue_init()\n"); 153 dprintk(1, "post videobuf_queue_init()\n");
150 unlock_kernel(); 154 unlock_kernel();
151 155
152 return 0; 156 return 0;
153} 157}
154 158
155static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 159static ssize_t video_read(struct file *file, char __user * data, size_t count,
160 loff_t * ppos)
156{ 161{
157 struct cx25821_fh *fh = file->private_data; 162 struct cx25821_fh *fh = file->private_data;
158 163
159 switch (fh->type) 164 switch (fh->type) {
160 {
161 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 165 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
162 if (res_locked(fh->dev, RESOURCE_VIDEO0)) 166 if (res_locked(fh->dev, RESOURCE_VIDEO0))
163 return -EBUSY; 167 return -EBUSY;
164 168
165 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 169 return videobuf_read_one(&fh->vidq, data, count, ppos,
170 file->f_flags & O_NONBLOCK);
166 171
167 default: 172 default:
168 BUG(); 173 BUG();
169 return 0; 174 return 0;
170 } 175 }
171} 176}
172 177
173static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 178static unsigned int video_poll(struct file *file,
179 struct poll_table_struct *wait)
174{ 180{
175 struct cx25821_fh *fh = file->private_data; 181 struct cx25821_fh *fh = file->private_data;
176 struct cx25821_buffer *buf; 182 struct cx25821_buffer *buf;
177 183
178 if (res_check(fh, RESOURCE_VIDEO0)) { 184 if (res_check(fh, RESOURCE_VIDEO0)) {
179 /* streaming capture */ 185 /* streaming capture */
180 if (list_empty(&fh->vidq.stream)) 186 if (list_empty(&fh->vidq.stream))
181 return POLLERR; 187 return POLLERR;
182 buf = list_entry(fh->vidq.stream.next, 188 buf = list_entry(fh->vidq.stream.next,
183 struct cx25821_buffer, vb.stream); 189 struct cx25821_buffer, vb.stream);
184 } else { 190 } else {
185 /* read() capture */ 191 /* read() capture */
186 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 192 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
187 if (NULL == buf) 193 if (NULL == buf)
188 return POLLERR; 194 return POLLERR;
189 }
190
191 poll_wait(file, &buf->vb.done, wait);
192 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
193 {
194 if( buf->vb.state == VIDEOBUF_DONE )
195 {
196 struct cx25821_dev *dev = fh->dev;
197
198 if( dev && dev->use_cif_resolution[SRAM_CH00] )
199 {
200 u8 cam_id = *((char*)buf->vb.baddr+3);
201 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
202 *((char*)buf->vb.baddr+3) = cam_id;
203 }
204 } 195 }
205 196
206 return POLLIN|POLLRDNORM; 197 poll_wait(file, &buf->vb.done, wait);
207 } 198 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
199 if (buf->vb.state == VIDEOBUF_DONE) {
200 struct cx25821_dev *dev = fh->dev;
201
202 if (dev && dev->use_cif_resolution[SRAM_CH00]) {
203 u8 cam_id = *((char *)buf->vb.baddr + 3);
204 memcpy((char *)buf->vb.baddr,
205 (char *)buf->vb.baddr + (fh->width * 2),
206 (fh->width * 2));
207 *((char *)buf->vb.baddr + 3) = cam_id;
208 }
209 }
210
211 return POLLIN | POLLRDNORM;
212 }
208 213
209 return 0; 214 return 0;
210} 215}
211 216
212
213static int video_release(struct file *file) 217static int video_release(struct file *file)
214{ 218{
215 struct cx25821_fh *fh = file->private_data; 219 struct cx25821_fh *fh = file->private_data;
216 struct cx25821_dev *dev = fh->dev; 220 struct cx25821_dev *dev = fh->dev;
217 221
218 //stop the risc engine and fifo 222 //stop the risc engine and fifo
219 cx_write(channel0->dma_ctl, 0); /* FIFO and RISC disable */ 223 cx_write(channel0->dma_ctl, 0); /* FIFO and RISC disable */
220 224
221 /* stop video capture */ 225 /* stop video capture */
222 if (res_check(fh, RESOURCE_VIDEO0)) { 226 if (res_check(fh, RESOURCE_VIDEO0)) {
223 videobuf_queue_cancel(&fh->vidq); 227 videobuf_queue_cancel(&fh->vidq);
224 res_free(dev, fh, RESOURCE_VIDEO0); 228 res_free(dev, fh, RESOURCE_VIDEO0);
225 } 229 }
226 230
227 if (fh->vidq.read_buf) { 231 if (fh->vidq.read_buf) {
228 buffer_release(&fh->vidq, fh->vidq.read_buf); 232 buffer_release(&fh->vidq, fh->vidq.read_buf);
229 kfree(fh->vidq.read_buf); 233 kfree(fh->vidq.read_buf);
230 } 234 }
231 235
232 videobuf_mmap_free(&fh->vidq); 236 videobuf_mmap_free(&fh->vidq);
233 237
234 v4l2_prio_close(&dev->prio,&fh->prio); 238 v4l2_prio_close(&dev->prio, &fh->prio);
235 file->private_data = NULL; 239 file->private_data = NULL;
236 kfree(fh); 240 kfree(fh);
237 241
238 return 0; 242 return 0;
239} 243}
240 244
241
242static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 245static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
243{ 246{
244 struct cx25821_fh *fh = priv; 247 struct cx25821_fh *fh = priv;
245 struct cx25821_dev *dev = fh->dev; 248 struct cx25821_dev *dev = fh->dev;
246 249
247 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 250 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
248 { 251 return -EINVAL;
249 return -EINVAL; 252 }
250 }
251 253
252 if (unlikely(i != fh->type)) 254 if (unlikely(i != fh->type)) {
253 { 255 return -EINVAL;
254 return -EINVAL; 256 }
255 }
256 257
257 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO0)))) 258 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO0)))) {
258 { 259 return -EBUSY;
259 return -EBUSY; 260 }
260 }
261 261
262 return videobuf_streamon(get_queue(fh)); 262 return videobuf_streamon(get_queue(fh));
263} 263}
264 264
265static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 265static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
266{ 266{
267 struct cx25821_fh *fh = priv; 267 struct cx25821_fh *fh = priv;
268 struct cx25821_dev *dev = fh->dev; 268 struct cx25821_dev *dev = fh->dev;
269 int err, res; 269 int err, res;
270 270
271 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 271 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
272 return -EINVAL; 272 return -EINVAL;
273 if (i != fh->type) 273 if (i != fh->type)
274 return -EINVAL; 274 return -EINVAL;
275 275
276 res = get_resource(fh, RESOURCE_VIDEO0); 276 res = get_resource(fh, RESOURCE_VIDEO0);
277 err = videobuf_streamoff(get_queue(fh)); 277 err = videobuf_streamoff(get_queue(fh));
278 if (err < 0) 278 if (err < 0)
279 return err; 279 return err;
280 res_free(dev, fh, res); 280 res_free(dev, fh, res);
281 return 0; 281 return 0;
282} 282}
283 283
284 284static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
285static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 285 struct v4l2_format *f)
286{ 286{
287 struct cx25821_fh *fh = priv; 287 struct cx25821_fh *fh = priv;
288 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 288 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
289 int err; 289 int err;
290 int pix_format = PIXEL_FRMT_422; 290 int pix_format = PIXEL_FRMT_422;
291 291
292 if (fh) 292 if (fh) {
293 { 293 err = v4l2_prio_check(&dev->prio, &fh->prio);
294 err = v4l2_prio_check(&dev->prio, &fh->prio); 294 if (0 != err)
295 return err;
296 }
297
298 dprintk(2, "%s()\n", __func__);
299 err = vidioc_try_fmt_vid_cap(file, priv, f);
300
295 if (0 != err) 301 if (0 != err)
296 return err; 302 return err;
297 } 303
298 304 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
299 dprintk(2, "%s()\n", __func__); 305 fh->vidq.field = f->fmt.pix.field;
300 err = vidioc_try_fmt_vid_cap(file, priv, f); 306
301 307 // check if width and height is valid based on set standard
302 if (0 != err) 308 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
303 return err; 309 fh->width = f->fmt.pix.width;
304 310 }
305 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 311
306 fh->vidq.field = f->fmt.pix.field; 312 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
307 313 fh->height = f->fmt.pix.height;
308 // check if width and height is valid based on set standard 314 }
309 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 315
310 { 316 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
311 fh->width = f->fmt.pix.width; 317 pix_format = PIXEL_FRMT_411;
312 } 318 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
313 319 pix_format = PIXEL_FRMT_422;
314 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 320 else
315 { 321 return -EINVAL;
316 fh->height = f->fmt.pix.height; 322
317 } 323 cx25821_set_pixel_format(dev, SRAM_CH00, pix_format);
318 324
319 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 325 // check if cif resolution
320 pix_format = PIXEL_FRMT_411; 326 if (fh->width == 320 || fh->width == 352) {
321 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 327 dev->use_cif_resolution[SRAM_CH00] = 1;
322 pix_format = PIXEL_FRMT_422; 328 } else {
323 else 329 dev->use_cif_resolution[SRAM_CH00] = 0;
324 return -EINVAL; 330 }
325 331 dev->cif_width[SRAM_CH00] = fh->width;
326 cx25821_set_pixel_format( dev, SRAM_CH00, pix_format ); 332 medusa_set_resolution(dev, fh->width, SRAM_CH00);
327 333
328 // check if cif resolution 334 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
329 if (fh->width == 320 || fh->width == 352) 335 fh->height, fh->vidq.field);
330 { 336 cx25821_call_all(dev, video, s_fmt, f);
331 dev->use_cif_resolution[SRAM_CH00] = 1; 337
332 }else 338 return 0;
333 {
334 dev->use_cif_resolution[SRAM_CH00] = 0;
335 }
336 dev->cif_width[SRAM_CH00] = fh->width;
337 medusa_set_resolution( dev, fh->width, SRAM_CH00 );
338
339 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
340 cx25821_call_all(dev, video, s_fmt, f);
341
342 return 0;
343} 339}
344 340
345static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 341static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
346{ 342{
347 int ret_val = 0; 343 int ret_val = 0;
348 struct cx25821_fh *fh = priv; 344 struct cx25821_fh *fh = priv;
349 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 345 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
350 346
351 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 347 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
352 348
353 p->sequence = dev->vidq[SRAM_CH00].count; 349 p->sequence = dev->vidq[SRAM_CH00].count;
354 350
355 return ret_val; 351 return ret_val;
356} 352}
357 353
358static int vidioc_log_status (struct file *file, void *priv) 354static int vidioc_log_status(struct file *file, void *priv)
359{ 355{
360 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 356 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
361 char name[32 + 2]; 357 char name[32 + 2];
362 358
363 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH00]; 359 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH00];
364 u32 tmp = 0; 360 u32 tmp = 0;
365 361
366 snprintf(name, sizeof(name), "%s/2", dev->name); 362 snprintf(name, sizeof(name), "%s/2", dev->name);
367 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 363 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
368 dev->name); 364 dev->name);
369 cx25821_call_all(dev, core, log_status); 365 cx25821_call_all(dev, core, log_status);
370 tmp = cx_read(sram_ch->dma_ctl); 366 tmp = cx_read(sram_ch->dma_ctl);
371 printk(KERN_INFO "Video input 0 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 367 printk(KERN_INFO "Video input 0 is %s\n",
372 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 368 (tmp & 0x11) ? "streaming" : "stopped");
369 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
373 dev->name); 370 dev->name);
374 return 0; 371 return 0;
375} 372}
376 373
377static int vidioc_s_ctrl(struct file *file, void *priv, 374static int vidioc_s_ctrl(struct file *file, void *priv,
378 struct v4l2_control *ctl) 375 struct v4l2_control *ctl)
379{ 376{
380 struct cx25821_fh *fh = priv; 377 struct cx25821_fh *fh = priv;
381 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 378 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -392,66 +389,63 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
392 389
393// exported stuff 390// exported stuff
394static const struct v4l2_file_operations video_fops = { 391static const struct v4l2_file_operations video_fops = {
395 .owner = THIS_MODULE, 392 .owner = THIS_MODULE,
396 .open = video_open, 393 .open = video_open,
397 .release = video_release, 394 .release = video_release,
398 .read = video_read, 395 .read = video_read,
399 .poll = video_poll, 396 .poll = video_poll,
400 .mmap = video_mmap, 397 .mmap = video_mmap,
401 .ioctl = video_ioctl2, 398 .ioctl = video_ioctl2,
402}; 399};
403 400
404static const struct v4l2_ioctl_ops video_ioctl_ops = { 401static const struct v4l2_ioctl_ops video_ioctl_ops = {
405 .vidioc_querycap = vidioc_querycap, 402 .vidioc_querycap = vidioc_querycap,
406 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 403 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
407 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 404 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
408 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 405 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
409 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 406 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
410 .vidioc_reqbufs = vidioc_reqbufs, 407 .vidioc_reqbufs = vidioc_reqbufs,
411 .vidioc_querybuf = vidioc_querybuf, 408 .vidioc_querybuf = vidioc_querybuf,
412 .vidioc_qbuf = vidioc_qbuf, 409 .vidioc_qbuf = vidioc_qbuf,
413 .vidioc_dqbuf = vidioc_dqbuf, 410 .vidioc_dqbuf = vidioc_dqbuf,
414#ifdef TUNER_FLAG 411#ifdef TUNER_FLAG
415 .vidioc_s_std = vidioc_s_std, 412 .vidioc_s_std = vidioc_s_std,
416 .vidioc_querystd = vidioc_querystd, 413 .vidioc_querystd = vidioc_querystd,
417#endif 414#endif
418 .vidioc_cropcap = vidioc_cropcap, 415 .vidioc_cropcap = vidioc_cropcap,
419 .vidioc_s_crop = vidioc_s_crop, 416 .vidioc_s_crop = vidioc_s_crop,
420 .vidioc_g_crop = vidioc_g_crop, 417 .vidioc_g_crop = vidioc_g_crop,
421 .vidioc_enum_input = vidioc_enum_input, 418 .vidioc_enum_input = vidioc_enum_input,
422 .vidioc_g_input = vidioc_g_input, 419 .vidioc_g_input = vidioc_g_input,
423 .vidioc_s_input = vidioc_s_input, 420 .vidioc_s_input = vidioc_s_input,
424 .vidioc_g_ctrl = vidioc_g_ctrl, 421 .vidioc_g_ctrl = vidioc_g_ctrl,
425 .vidioc_s_ctrl = vidioc_s_ctrl, 422 .vidioc_s_ctrl = vidioc_s_ctrl,
426 .vidioc_queryctrl = vidioc_queryctrl, 423 .vidioc_queryctrl = vidioc_queryctrl,
427 .vidioc_streamon = vidioc_streamon, 424 .vidioc_streamon = vidioc_streamon,
428 .vidioc_streamoff = vidioc_streamoff, 425 .vidioc_streamoff = vidioc_streamoff,
429 .vidioc_log_status = vidioc_log_status, 426 .vidioc_log_status = vidioc_log_status,
430 .vidioc_g_priority = vidioc_g_priority, 427 .vidioc_g_priority = vidioc_g_priority,
431 .vidioc_s_priority = vidioc_s_priority, 428 .vidioc_s_priority = vidioc_s_priority,
432#ifdef CONFIG_VIDEO_V4L1_COMPAT 429#ifdef CONFIG_VIDEO_V4L1_COMPAT
433 .vidiocgmbuf = vidiocgmbuf, 430 .vidiocgmbuf = vidiocgmbuf,
434#endif 431#endif
435#ifdef TUNER_FLAG 432#ifdef TUNER_FLAG
436 .vidioc_g_tuner = vidioc_g_tuner, 433 .vidioc_g_tuner = vidioc_g_tuner,
437 .vidioc_s_tuner = vidioc_s_tuner, 434 .vidioc_s_tuner = vidioc_s_tuner,
438 .vidioc_g_frequency = vidioc_g_frequency, 435 .vidioc_g_frequency = vidioc_g_frequency,
439 .vidioc_s_frequency = vidioc_s_frequency, 436 .vidioc_s_frequency = vidioc_s_frequency,
440#endif 437#endif
441#ifdef CONFIG_VIDEO_ADV_DEBUG 438#ifdef CONFIG_VIDEO_ADV_DEBUG
442 .vidioc_g_register = vidioc_g_register, 439 .vidioc_g_register = vidioc_g_register,
443 .vidioc_s_register = vidioc_s_register, 440 .vidioc_s_register = vidioc_s_register,
444#endif 441#endif
445}; 442};
446 443
447struct video_device cx25821_video_template0 = { 444struct video_device cx25821_video_template0 = {
448 .name = "cx25821-video", 445 .name = "cx25821-video",
449 .fops = &video_fops, 446 .fops = &video_fops,
450 .minor = -1, 447 .minor = -1,
451 .ioctl_ops = &video_ioctl_ops, 448 .ioctl_ops = &video_ioctl_ops,
452 .tvnorms = CX25821_NORMS, 449 .tvnorms = CX25821_NORMS,
453 .current_norm = V4L2_STD_NTSC_M, 450 .current_norm = V4L2_STD_NTSC_M,
454}; 451};
455
456
457
diff --git a/drivers/staging/cx25821/cx25821-video1.c b/drivers/staging/cx25821/cx25821-video1.c
index c36f664f6358..a4dddc684adf 100644
--- a/drivers/staging/cx25821/cx25821-video1.c
+++ b/drivers/staging/cx25821/cx25821-video1.c
@@ -23,359 +23,356 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH01]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH01];
35 34
36 /* add jump to stopper */ 35 /* add jump to stopper */
37 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 39
41 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 41
43 if (!list_empty(&q->queued)) { 42 if (!list_empty(&q->queued)) {
44 list_add_tail(&buf->vb.queue, &q->queued); 43 list_add_tail(&buf->vb.queue, &q->queued);
45 buf->vb.state = VIDEOBUF_QUEUED; 44 buf->vb.state = VIDEOBUF_QUEUED;
46 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 46 buf->vb.i);
48 } else if (list_empty(&q->active)) { 47
49 list_add_tail(&buf->vb.queue, &q->active); 48 } else if (list_empty(&q->active)) {
50 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH01]); 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->vb.state = VIDEOBUF_ACTIVE; 50 cx25821_start_video_dma(dev, q, buf,
52 buf->count = q->count++; 51 &dev->sram_channels[SRAM_CH01]);
53 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 53 buf->count = q->count++;
55 buf, buf->vb. i, buf->count, q->count); 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 } else { 55 dprintk(2,
57 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 if (prev->vb.width == buf->vb.width && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->vb.height == buf->vb.height &&
60 prev->fmt == buf->fmt) {
61 list_add_tail(&buf->vb.queue, &q->active);
62 buf->vb.state = VIDEOBUF_ACTIVE;
63 buf->count = q->count++;
64 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
65
66 /* 64 bit bits 63-32 */
67 prev->risc.jmp[2] = cpu_to_le32(0);
68 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
69
70 } else { 58 } else {
71 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
72 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
73 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
74 } 81 }
75 }
76 82
77 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
78 { 84 dprintk(2, "active queue empty!\n");
79 dprintk(2, "active queue empty!\n"); 85 }
80 }
81} 86}
82 87
83
84static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
85 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
86 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
87 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
88 .buf_release = buffer_release, 92 .buf_release = buffer_release,
89}; 93};
90 94
91
92static int video_open(struct file *file) 95static int video_open(struct file *file)
93{ 96{
94 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
95 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
96 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
97 struct list_head *list; 100 struct list_head *list;
98 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
99 u32 pix_format; 102 u32 pix_format;
100 103
101 lock_kernel(); 104 lock_kernel();
102 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
103 { 106 h = list_entry(list, struct cx25821_dev, devlist);
104 h = list_entry(list, struct cx25821_dev, devlist); 107
105 108 if (h->video_dev[SRAM_CH01]
106 if (h->video_dev[SRAM_CH01] && h->video_dev[SRAM_CH01]->minor == minor) { 109 && h->video_dev[SRAM_CH01]->minor == minor) {
107 dev = h; 110 dev = h;
108 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
112 }
109 } 113 }
110 }
111 114
112 if (NULL == dev) { 115 if (NULL == dev) {
113 unlock_kernel(); 116 unlock_kernel();
114 return -ENODEV; 117 return -ENODEV;
115 } 118 }
116 119
117 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
118 121
119 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
120 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
121 if (NULL == fh) { 124 if (NULL == fh) {
122 unlock_kernel(); 125 unlock_kernel();
123 return -ENOMEM; 126 return -ENOMEM;
124 } 127 }
125 128
126 file->private_data = fh; 129 file->private_data = fh;
127 fh->dev = dev; 130 fh->dev = dev;
128 fh->type = type; 131 fh->type = type;
129 fh->width = 720; 132 fh->width = 720;
130 133
131 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 134 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
132 fh->height = 576; 135 fh->height = 576;
133 else 136 else
134 fh->height = 480; 137 fh->height = 480;
135 138
136 dev->channel_opened = SRAM_CH01; 139 dev->channel_opened = SRAM_CH01;
137 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV; 140 pix_format =
138 fh->fmt = format_by_fourcc(pix_format); 141 (dev->pixel_formats[dev->channel_opened] ==
142 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
143 fh->fmt = format_by_fourcc(pix_format);
139 144
140 v4l2_prio_open(&dev->prio,&fh->prio); 145 v4l2_prio_open(&dev->prio, &fh->prio);
141 146
142 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, 147 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
143 &dev->pci->dev, &dev->slock, 148 &dev->pci->dev, &dev->slock,
144 V4L2_BUF_TYPE_VIDEO_CAPTURE, 149 V4L2_BUF_TYPE_VIDEO_CAPTURE,
145 V4L2_FIELD_INTERLACED, 150 V4L2_FIELD_INTERLACED,
146 sizeof(struct cx25821_buffer), 151 sizeof(struct cx25821_buffer), fh);
147 fh);
148 152
149 dprintk(1, "post videobuf_queue_init()\n"); 153 dprintk(1, "post videobuf_queue_init()\n");
150 unlock_kernel(); 154 unlock_kernel();
151 155
152 return 0; 156 return 0;
153} 157}
154 158
155static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 159static ssize_t video_read(struct file *file, char __user * data, size_t count,
160 loff_t * ppos)
156{ 161{
157 struct cx25821_fh *fh = file->private_data; 162 struct cx25821_fh *fh = file->private_data;
158 163
159 switch (fh->type) 164 switch (fh->type) {
160 {
161 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 165 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
162 if (res_locked(fh->dev, RESOURCE_VIDEO1)) 166 if (res_locked(fh->dev, RESOURCE_VIDEO1))
163 return -EBUSY; 167 return -EBUSY;
164 168
165 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 169 return videobuf_read_one(&fh->vidq, data, count, ppos,
170 file->f_flags & O_NONBLOCK);
166 171
167 default: 172 default:
168 BUG(); 173 BUG();
169 return 0; 174 return 0;
170 } 175 }
171} 176}
172 177
173static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 178static unsigned int video_poll(struct file *file,
179 struct poll_table_struct *wait)
174{ 180{
175 struct cx25821_fh *fh = file->private_data; 181 struct cx25821_fh *fh = file->private_data;
176 struct cx25821_buffer *buf; 182 struct cx25821_buffer *buf;
177 183
178 if (res_check(fh, RESOURCE_VIDEO1)) { 184 if (res_check(fh, RESOURCE_VIDEO1)) {
179 /* streaming capture */ 185 /* streaming capture */
180 if (list_empty(&fh->vidq.stream)) 186 if (list_empty(&fh->vidq.stream))
181 return POLLERR; 187 return POLLERR;
182 buf = list_entry(fh->vidq.stream.next, 188 buf = list_entry(fh->vidq.stream.next,
183 struct cx25821_buffer, vb.stream); 189 struct cx25821_buffer, vb.stream);
184 } else { 190 } else {
185 /* read() capture */ 191 /* read() capture */
186 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 192 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
187 if (NULL == buf) 193 if (NULL == buf)
188 return POLLERR; 194 return POLLERR;
189 }
190
191 poll_wait(file, &buf->vb.done, wait);
192 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
193 {
194 if( buf->vb.state == VIDEOBUF_DONE )
195 {
196 struct cx25821_dev *dev = fh->dev;
197
198 if( dev && dev->use_cif_resolution[SRAM_CH01] )
199 {
200 u8 cam_id = *((char*)buf->vb.baddr+3);
201 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
202 *((char*)buf->vb.baddr+3) = cam_id;
203 }
204 } 195 }
205 196
206 return POLLIN|POLLRDNORM; 197 poll_wait(file, &buf->vb.done, wait);
207 } 198 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
199 if (buf->vb.state == VIDEOBUF_DONE) {
200 struct cx25821_dev *dev = fh->dev;
201
202 if (dev && dev->use_cif_resolution[SRAM_CH01]) {
203 u8 cam_id = *((char *)buf->vb.baddr + 3);
204 memcpy((char *)buf->vb.baddr,
205 (char *)buf->vb.baddr + (fh->width * 2),
206 (fh->width * 2));
207 *((char *)buf->vb.baddr + 3) = cam_id;
208 }
209 }
210
211 return POLLIN | POLLRDNORM;
212 }
208 213
209 return 0; 214 return 0;
210} 215}
211 216
212static int video_release(struct file *file) 217static int video_release(struct file *file)
213{ 218{
214 struct cx25821_fh *fh = file->private_data; 219 struct cx25821_fh *fh = file->private_data;
215 struct cx25821_dev *dev = fh->dev; 220 struct cx25821_dev *dev = fh->dev;
216 221
217 //stop the risc engine and fifo 222 //stop the risc engine and fifo
218 cx_write(channel1->dma_ctl, 0); /* FIFO and RISC disable */ 223 cx_write(channel1->dma_ctl, 0); /* FIFO and RISC disable */
219 224
220 /* stop video capture */ 225 /* stop video capture */
221 if (res_check(fh, RESOURCE_VIDEO1)) { 226 if (res_check(fh, RESOURCE_VIDEO1)) {
222 videobuf_queue_cancel(&fh->vidq); 227 videobuf_queue_cancel(&fh->vidq);
223 res_free(dev, fh, RESOURCE_VIDEO1); 228 res_free(dev, fh, RESOURCE_VIDEO1);
224 } 229 }
225 230
226 if (fh->vidq.read_buf) { 231 if (fh->vidq.read_buf) {
227 buffer_release(&fh->vidq, fh->vidq.read_buf); 232 buffer_release(&fh->vidq, fh->vidq.read_buf);
228 kfree(fh->vidq.read_buf); 233 kfree(fh->vidq.read_buf);
229 } 234 }
230 235
231 videobuf_mmap_free(&fh->vidq); 236 videobuf_mmap_free(&fh->vidq);
232 237
233 v4l2_prio_close(&dev->prio,&fh->prio); 238 v4l2_prio_close(&dev->prio, &fh->prio);
234 file->private_data = NULL; 239 file->private_data = NULL;
235 kfree(fh); 240 kfree(fh);
236 241
237 return 0; 242 return 0;
238} 243}
239 244
240
241static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 245static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
242{ 246{
243 struct cx25821_fh *fh = priv; 247 struct cx25821_fh *fh = priv;
244 struct cx25821_dev *dev = fh->dev; 248 struct cx25821_dev *dev = fh->dev;
245 249
246 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 250 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
247 { 251 return -EINVAL;
248 return -EINVAL; 252 }
249 }
250 253
251 if (unlikely(i != fh->type)) 254 if (unlikely(i != fh->type)) {
252 { 255 return -EINVAL;
253 return -EINVAL; 256 }
254 }
255 257
256 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO1)))) 258 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO1)))) {
257 { 259 return -EBUSY;
258 return -EBUSY; 260 }
259 }
260 261
261 return videobuf_streamon(get_queue(fh)); 262 return videobuf_streamon(get_queue(fh));
262} 263}
263 264
264static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 265static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
265{ 266{
266 struct cx25821_fh *fh = priv; 267 struct cx25821_fh *fh = priv;
267 struct cx25821_dev *dev = fh->dev; 268 struct cx25821_dev *dev = fh->dev;
268 int err, res; 269 int err, res;
269 270
270 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 271 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
271 return -EINVAL; 272 return -EINVAL;
272 if (i != fh->type) 273 if (i != fh->type)
273 return -EINVAL; 274 return -EINVAL;
274 275
275 res = get_resource(fh, RESOURCE_VIDEO1); 276 res = get_resource(fh, RESOURCE_VIDEO1);
276 err = videobuf_streamoff(get_queue(fh)); 277 err = videobuf_streamoff(get_queue(fh));
277 if (err < 0) 278 if (err < 0)
278 return err; 279 return err;
279 res_free(dev, fh, res); 280 res_free(dev, fh, res);
280 return 0; 281 return 0;
281} 282}
282 283
284static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
285 struct v4l2_format *f)
286{
287 struct cx25821_fh *fh = priv;
288 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
289 int err;
290 int pix_format = 0;
283 291
292 if (fh) {
293 err = v4l2_prio_check(&dev->prio, &fh->prio);
294 if (0 != err)
295 return err;
296 }
297
298 dprintk(2, "%s()\n", __func__);
299 err = vidioc_try_fmt_vid_cap(file, priv, f);
284 300
285static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
286{
287 struct cx25821_fh *fh = priv;
288 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
289 int err;
290 int pix_format = 0;
291
292 if (fh)
293 {
294 err = v4l2_prio_check(&dev->prio, &fh->prio);
295 if (0 != err) 301 if (0 != err)
296 return err; 302 return err;
297 } 303
298 304 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
299 dprintk(2, "%s()\n", __func__); 305 fh->vidq.field = f->fmt.pix.field;
300 err = vidioc_try_fmt_vid_cap(file, priv, f); 306
301 307 // check if width and height is valid based on set standard
302 if (0 != err) 308 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
303 return err; 309 fh->width = f->fmt.pix.width;
304 310 }
305 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 311
306 fh->vidq.field = f->fmt.pix.field; 312 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
307 313 fh->height = f->fmt.pix.height;
308 // check if width and height is valid based on set standard 314 }
309 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 315
310 { 316 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
311 fh->width = f->fmt.pix.width; 317 pix_format = PIXEL_FRMT_411;
312 } 318 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
313 319 pix_format = PIXEL_FRMT_422;
314 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 320 else
315 { 321 return -EINVAL;
316 fh->height = f->fmt.pix.height; 322
317 } 323 cx25821_set_pixel_format(dev, SRAM_CH01, pix_format);
318 324
319 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 325 // check if cif resolution
320 pix_format = PIXEL_FRMT_411; 326 if (fh->width == 320 || fh->width == 352) {
321 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 327 dev->use_cif_resolution[SRAM_CH01] = 1;
322 pix_format = PIXEL_FRMT_422; 328 } else {
323 else 329 dev->use_cif_resolution[SRAM_CH01] = 0;
324 return -EINVAL; 330 }
325 331 dev->cif_width[SRAM_CH01] = fh->width;
326 cx25821_set_pixel_format( dev, SRAM_CH01, pix_format ); 332 medusa_set_resolution(dev, fh->width, SRAM_CH01);
327 333
328 // check if cif resolution 334 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
329 if (fh->width == 320 || fh->width == 352) 335 fh->height, fh->vidq.field);
330 { 336 cx25821_call_all(dev, video, s_fmt, f);
331 dev->use_cif_resolution[SRAM_CH01] = 1; 337
332 }else 338 return 0;
333 {
334 dev->use_cif_resolution[SRAM_CH01] = 0;
335 }
336 dev->cif_width[SRAM_CH01] = fh->width;
337 medusa_set_resolution( dev, fh->width, SRAM_CH01 );
338
339 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
340 cx25821_call_all(dev, video, s_fmt, f);
341
342 return 0;
343} 339}
344 340
345static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 341static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
346{ 342{
347 int ret_val = 0; 343 int ret_val = 0;
348 struct cx25821_fh *fh = priv; 344 struct cx25821_fh *fh = priv;
349 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 345 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
350 346
351 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 347 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
352 348
353 p->sequence = dev->vidq[SRAM_CH01].count; 349 p->sequence = dev->vidq[SRAM_CH01].count;
354 350
355 return ret_val; 351 return ret_val;
356} 352}
357 353
358static int vidioc_log_status (struct file *file, void *priv) 354static int vidioc_log_status(struct file *file, void *priv)
359{ 355{
360 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 356 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
361 char name[32 + 2]; 357 char name[32 + 2];
362 358
363 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH01]; 359 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH01];
364 u32 tmp = 0; 360 u32 tmp = 0;
365 361
366 snprintf(name, sizeof(name), "%s/2", dev->name); 362 snprintf(name, sizeof(name), "%s/2", dev->name);
367 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 363 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
368 dev->name); 364 dev->name);
369 cx25821_call_all(dev, core, log_status); 365 cx25821_call_all(dev, core, log_status);
370 tmp = cx_read(sram_ch->dma_ctl); 366 tmp = cx_read(sram_ch->dma_ctl);
371 printk(KERN_INFO "Video input 1 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 367 printk(KERN_INFO "Video input 1 is %s\n",
372 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 368 (tmp & 0x11) ? "streaming" : "stopped");
369 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
373 dev->name); 370 dev->name);
374 return 0; 371 return 0;
375} 372}
376 373
377static int vidioc_s_ctrl(struct file *file, void *priv, 374static int vidioc_s_ctrl(struct file *file, void *priv,
378 struct v4l2_control *ctl) 375 struct v4l2_control *ctl)
379{ 376{
380 struct cx25821_fh *fh = priv; 377 struct cx25821_fh *fh = priv;
381 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 378 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -389,68 +386,66 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
389 386
390 return cx25821_set_control(dev, ctl, SRAM_CH01); 387 return cx25821_set_control(dev, ctl, SRAM_CH01);
391} 388}
389
392//exported stuff 390//exported stuff
393static const struct v4l2_file_operations video_fops = { 391static const struct v4l2_file_operations video_fops = {
394 .owner = THIS_MODULE, 392 .owner = THIS_MODULE,
395 .open = video_open, 393 .open = video_open,
396 .release = video_release, 394 .release = video_release,
397 .read = video_read, 395 .read = video_read,
398 .poll = video_poll, 396 .poll = video_poll,
399 .mmap = video_mmap, 397 .mmap = video_mmap,
400 .ioctl = video_ioctl2, 398 .ioctl = video_ioctl2,
401}; 399};
402 400
403static const struct v4l2_ioctl_ops video_ioctl_ops = { 401static const struct v4l2_ioctl_ops video_ioctl_ops = {
404 .vidioc_querycap = vidioc_querycap, 402 .vidioc_querycap = vidioc_querycap,
405 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 403 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
406 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 404 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
407 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 405 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
408 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 406 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
409 .vidioc_reqbufs = vidioc_reqbufs, 407 .vidioc_reqbufs = vidioc_reqbufs,
410 .vidioc_querybuf = vidioc_querybuf, 408 .vidioc_querybuf = vidioc_querybuf,
411 .vidioc_qbuf = vidioc_qbuf, 409 .vidioc_qbuf = vidioc_qbuf,
412 .vidioc_dqbuf = vidioc_dqbuf, 410 .vidioc_dqbuf = vidioc_dqbuf,
413#ifdef TUNER_FLAG 411#ifdef TUNER_FLAG
414 .vidioc_s_std = vidioc_s_std, 412 .vidioc_s_std = vidioc_s_std,
415 .vidioc_querystd = vidioc_querystd, 413 .vidioc_querystd = vidioc_querystd,
416#endif 414#endif
417 .vidioc_cropcap = vidioc_cropcap, 415 .vidioc_cropcap = vidioc_cropcap,
418 .vidioc_s_crop = vidioc_s_crop, 416 .vidioc_s_crop = vidioc_s_crop,
419 .vidioc_g_crop = vidioc_g_crop, 417 .vidioc_g_crop = vidioc_g_crop,
420 .vidioc_enum_input = vidioc_enum_input, 418 .vidioc_enum_input = vidioc_enum_input,
421 .vidioc_g_input = vidioc_g_input, 419 .vidioc_g_input = vidioc_g_input,
422 .vidioc_s_input = vidioc_s_input, 420 .vidioc_s_input = vidioc_s_input,
423 .vidioc_g_ctrl = vidioc_g_ctrl, 421 .vidioc_g_ctrl = vidioc_g_ctrl,
424 .vidioc_s_ctrl = vidioc_s_ctrl, 422 .vidioc_s_ctrl = vidioc_s_ctrl,
425 .vidioc_queryctrl = vidioc_queryctrl, 423 .vidioc_queryctrl = vidioc_queryctrl,
426 .vidioc_streamon = vidioc_streamon, 424 .vidioc_streamon = vidioc_streamon,
427 .vidioc_streamoff = vidioc_streamoff, 425 .vidioc_streamoff = vidioc_streamoff,
428 .vidioc_log_status = vidioc_log_status, 426 .vidioc_log_status = vidioc_log_status,
429 .vidioc_g_priority = vidioc_g_priority, 427 .vidioc_g_priority = vidioc_g_priority,
430 .vidioc_s_priority = vidioc_s_priority, 428 .vidioc_s_priority = vidioc_s_priority,
431#ifdef CONFIG_VIDEO_V4L1_COMPAT 429#ifdef CONFIG_VIDEO_V4L1_COMPAT
432 .vidiocgmbuf = vidiocgmbuf, 430 .vidiocgmbuf = vidiocgmbuf,
433#endif 431#endif
434#ifdef TUNER_FLAG 432#ifdef TUNER_FLAG
435 .vidioc_g_tuner = vidioc_g_tuner, 433 .vidioc_g_tuner = vidioc_g_tuner,
436 .vidioc_s_tuner = vidioc_s_tuner, 434 .vidioc_s_tuner = vidioc_s_tuner,
437 .vidioc_g_frequency = vidioc_g_frequency, 435 .vidioc_g_frequency = vidioc_g_frequency,
438 .vidioc_s_frequency = vidioc_s_frequency, 436 .vidioc_s_frequency = vidioc_s_frequency,
439#endif 437#endif
440#ifdef CONFIG_VIDEO_ADV_DEBUG 438#ifdef CONFIG_VIDEO_ADV_DEBUG
441 .vidioc_g_register = vidioc_g_register, 439 .vidioc_g_register = vidioc_g_register,
442 .vidioc_s_register = vidioc_s_register, 440 .vidioc_s_register = vidioc_s_register,
443#endif 441#endif
444}; 442};
445 443
446struct video_device cx25821_video_template1 = { 444struct video_device cx25821_video_template1 = {
447 .name = "cx25821-video", 445 .name = "cx25821-video",
448 .fops = &video_fops, 446 .fops = &video_fops,
449 .minor = -1, 447 .minor = -1,
450 .ioctl_ops = &video_ioctl_ops, 448 .ioctl_ops = &video_ioctl_ops,
451 .tvnorms = CX25821_NORMS, 449 .tvnorms = CX25821_NORMS,
452 .current_norm = V4L2_STD_NTSC_M, 450 .current_norm = V4L2_STD_NTSC_M,
453}; 451};
454
455
456
diff --git a/drivers/staging/cx25821/cx25821-video2.c b/drivers/staging/cx25821/cx25821-video2.c
index 10df4f981f3a..8e04e253f5d9 100644
--- a/drivers/staging/cx25821/cx25821-video2.c
+++ b/drivers/staging/cx25821/cx25821-video2.c
@@ -23,362 +23,357 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH02]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH02];
35 34
36 /* add jump to stopper */ 35 /* add jump to stopper */
37 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 39
41 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 41
43 if (!list_empty(&q->queued)) { 42 if (!list_empty(&q->queued)) {
44 list_add_tail(&buf->vb.queue, &q->queued); 43 list_add_tail(&buf->vb.queue, &q->queued);
45 buf->vb.state = VIDEOBUF_QUEUED; 44 buf->vb.state = VIDEOBUF_QUEUED;
46 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 46 buf->vb.i);
48 } else if (list_empty(&q->active)) { 47
49 list_add_tail(&buf->vb.queue, &q->active); 48 } else if (list_empty(&q->active)) {
50 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH02]); 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->vb.state = VIDEOBUF_ACTIVE; 50 cx25821_start_video_dma(dev, q, buf,
52 buf->count = q->count++; 51 &dev->sram_channels[SRAM_CH02]);
53 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 53 buf->count = q->count++;
55 buf, buf->vb. i, buf->count, q->count); 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 } else { 55 dprintk(2,
57 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 if (prev->vb.width == buf->vb.width && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->vb.height == buf->vb.height &&
60 prev->fmt == buf->fmt) {
61 list_add_tail(&buf->vb.queue, &q->active);
62 buf->vb.state = VIDEOBUF_ACTIVE;
63 buf->count = q->count++;
64 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
65
66 /* 64 bit bits 63-32 */
67 prev->risc.jmp[2] = cpu_to_le32(0);
68 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
69
70 } else { 58 } else {
71 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
72 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
73 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
74 } 81 }
75 }
76 82
77 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
78 { 84 dprintk(2, "active queue empty!\n");
79 dprintk(2, "active queue empty!\n"); 85 }
80 }
81} 86}
82 87
83
84static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
85 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
86 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
87 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
88 .buf_release = buffer_release, 92 .buf_release = buffer_release,
89}; 93};
90 94
91
92static int video_open(struct file *file) 95static int video_open(struct file *file)
93{ 96{
94 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
95 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
96 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
97 struct list_head *list; 100 struct list_head *list;
98 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
99 u32 pix_format; 102 u32 pix_format;
100 103
101 lock_kernel(); 104 lock_kernel();
102 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
103 { 106 h = list_entry(list, struct cx25821_dev, devlist);
104 h = list_entry(list, struct cx25821_dev, devlist); 107
105 108 if (h->video_dev[SRAM_CH02]
106 if (h->video_dev[SRAM_CH02] && h->video_dev[SRAM_CH02]->minor == minor) { 109 && h->video_dev[SRAM_CH02]->minor == minor) {
107 dev = h; 110 dev = h;
108 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
112 }
109 } 113 }
110 }
111 114
112 if (NULL == dev) { 115 if (NULL == dev) {
113 unlock_kernel(); 116 unlock_kernel();
114 return -ENODEV; 117 return -ENODEV;
115 } 118 }
116 119
117 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
118 121
119 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
120 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
121 if (NULL == fh) { 124 if (NULL == fh) {
125 unlock_kernel();
126 return -ENOMEM;
127 }
128 file->private_data = fh;
129 fh->dev = dev;
130 fh->type = type;
131 fh->width = 720;
132
133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
134 fh->height = 576;
135 else
136 fh->height = 480;
137
138 dev->channel_opened = SRAM_CH02;
139 pix_format =
140 (dev->pixel_formats[dev->channel_opened] ==
141 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
142 fh->fmt = format_by_fourcc(pix_format);
143
144 v4l2_prio_open(&dev->prio, &fh->prio);
145
146 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
147 &dev->pci->dev, &dev->slock,
148 V4L2_BUF_TYPE_VIDEO_CAPTURE,
149 V4L2_FIELD_INTERLACED,
150 sizeof(struct cx25821_buffer), fh);
151
152 dprintk(1, "post videobuf_queue_init()\n");
122 unlock_kernel(); 153 unlock_kernel();
123 return -ENOMEM; 154
124 } 155 return 0;
125 file->private_data = fh;
126 fh->dev = dev;
127 fh->type = type;
128 fh->width = 720;
129
130 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
131 fh->height = 576;
132 else
133 fh->height = 480;
134
135 dev->channel_opened = SRAM_CH02;
136 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
137 fh->fmt = format_by_fourcc(pix_format);
138
139 v4l2_prio_open(&dev->prio,&fh->prio);
140
141 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
142 &dev->pci->dev, &dev->slock,
143 V4L2_BUF_TYPE_VIDEO_CAPTURE,
144 V4L2_FIELD_INTERLACED,
145 sizeof(struct cx25821_buffer),
146 fh);
147
148 dprintk(1, "post videobuf_queue_init()\n");
149 unlock_kernel();
150
151 return 0;
152} 156}
153 157
154static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 158static ssize_t video_read(struct file *file, char __user * data, size_t count,
159 loff_t * ppos)
155{ 160{
156 struct cx25821_fh *fh = file->private_data; 161 struct cx25821_fh *fh = file->private_data;
157 162
158 switch (fh->type) 163 switch (fh->type) {
159 {
160 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 164 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
161 if (res_locked(fh->dev, RESOURCE_VIDEO2)) 165 if (res_locked(fh->dev, RESOURCE_VIDEO2))
162 return -EBUSY; 166 return -EBUSY;
163 167
164 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 168 return videobuf_read_one(&fh->vidq, data, count, ppos,
169 file->f_flags & O_NONBLOCK);
165 170
166 default: 171 default:
167 BUG(); 172 BUG();
168 return 0; 173 return 0;
169 } 174 }
170} 175}
171 176
172static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 177static unsigned int video_poll(struct file *file,
178 struct poll_table_struct *wait)
173{ 179{
174 struct cx25821_fh *fh = file->private_data; 180 struct cx25821_fh *fh = file->private_data;
175 struct cx25821_buffer *buf; 181 struct cx25821_buffer *buf;
176 182
177 if (res_check(fh, RESOURCE_VIDEO2)) { 183 if (res_check(fh, RESOURCE_VIDEO2)) {
178 /* streaming capture */ 184 /* streaming capture */
179 if (list_empty(&fh->vidq.stream)) 185 if (list_empty(&fh->vidq.stream))
180 return POLLERR; 186 return POLLERR;
181 buf = list_entry(fh->vidq.stream.next, 187 buf = list_entry(fh->vidq.stream.next,
182 struct cx25821_buffer, vb.stream); 188 struct cx25821_buffer, vb.stream);
183 } else { 189 } else {
184 /* read() capture */ 190 /* read() capture */
185 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 191 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
186 if (NULL == buf) 192 if (NULL == buf)
187 return POLLERR; 193 return POLLERR;
188 }
189
190 poll_wait(file, &buf->vb.done, wait);
191 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
192 {
193 if( buf->vb.state == VIDEOBUF_DONE )
194 {
195 struct cx25821_dev *dev = fh->dev;
196
197 if( dev && dev->use_cif_resolution[SRAM_CH02] )
198 {
199 u8 cam_id = *((char*)buf->vb.baddr+3);
200 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
201 *((char*)buf->vb.baddr+3) = cam_id;
202 }
203 } 194 }
204 195
205 return POLLIN|POLLRDNORM; 196 poll_wait(file, &buf->vb.done, wait);
206 } 197 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
198 if (buf->vb.state == VIDEOBUF_DONE) {
199 struct cx25821_dev *dev = fh->dev;
200
201 if (dev && dev->use_cif_resolution[SRAM_CH02]) {
202 u8 cam_id = *((char *)buf->vb.baddr + 3);
203 memcpy((char *)buf->vb.baddr,
204 (char *)buf->vb.baddr + (fh->width * 2),
205 (fh->width * 2));
206 *((char *)buf->vb.baddr + 3) = cam_id;
207 }
208 }
209
210 return POLLIN | POLLRDNORM;
211 }
207 212
208 return 0; 213 return 0;
209} 214}
210 215
211
212static int video_release(struct file *file) 216static int video_release(struct file *file)
213{ 217{
214 struct cx25821_fh *fh = file->private_data; 218 struct cx25821_fh *fh = file->private_data;
215 struct cx25821_dev *dev = fh->dev; 219 struct cx25821_dev *dev = fh->dev;
216 220
217 //stop the risc engine and fifo 221 //stop the risc engine and fifo
218 cx_write(channel2->dma_ctl, 0); /* FIFO and RISC disable */ 222 cx_write(channel2->dma_ctl, 0); /* FIFO and RISC disable */
219 223
220 /* stop video capture */ 224 /* stop video capture */
221 if (res_check(fh, RESOURCE_VIDEO2)) { 225 if (res_check(fh, RESOURCE_VIDEO2)) {
222 videobuf_queue_cancel(&fh->vidq); 226 videobuf_queue_cancel(&fh->vidq);
223 res_free(dev, fh, RESOURCE_VIDEO2); 227 res_free(dev, fh, RESOURCE_VIDEO2);
224 } 228 }
225 229
226 if (fh->vidq.read_buf) { 230 if (fh->vidq.read_buf) {
227 buffer_release(&fh->vidq, fh->vidq.read_buf); 231 buffer_release(&fh->vidq, fh->vidq.read_buf);
228 kfree(fh->vidq.read_buf); 232 kfree(fh->vidq.read_buf);
229 } 233 }
230 234
231 videobuf_mmap_free(&fh->vidq); 235 videobuf_mmap_free(&fh->vidq);
232 236
233 v4l2_prio_close(&dev->prio,&fh->prio); 237 v4l2_prio_close(&dev->prio, &fh->prio);
234 file->private_data = NULL; 238 file->private_data = NULL;
235 kfree(fh); 239 kfree(fh);
236 240
237 return 0; 241 return 0;
238} 242}
239 243
240
241static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 244static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
242{ 245{
243 struct cx25821_fh *fh = priv; 246 struct cx25821_fh *fh = priv;
244 struct cx25821_dev *dev = fh->dev; 247 struct cx25821_dev *dev = fh->dev;
245 248
246 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 249 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
247 { 250 return -EINVAL;
248 return -EINVAL; 251 }
249 }
250 252
251 if (unlikely(i != fh->type)) 253 if (unlikely(i != fh->type)) {
252 { 254 return -EINVAL;
253 return -EINVAL; 255 }
254 }
255 256
256 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO2)))) 257 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO2)))) {
257 { 258 return -EBUSY;
258 return -EBUSY; 259 }
259 }
260 260
261 return videobuf_streamon(get_queue(fh)); 261 return videobuf_streamon(get_queue(fh));
262} 262}
263 263
264static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 264static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
265{ 265{
266 struct cx25821_fh *fh = priv; 266 struct cx25821_fh *fh = priv;
267 struct cx25821_dev *dev = fh->dev; 267 struct cx25821_dev *dev = fh->dev;
268 int err, res; 268 int err, res;
269 269
270 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 270 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
271 return -EINVAL; 271 return -EINVAL;
272 if (i != fh->type) 272 if (i != fh->type)
273 return -EINVAL; 273 return -EINVAL;
274 274
275 res = get_resource(fh, RESOURCE_VIDEO2); 275 res = get_resource(fh, RESOURCE_VIDEO2);
276 err = videobuf_streamoff(get_queue(fh)); 276 err = videobuf_streamoff(get_queue(fh));
277 if (err < 0) 277 if (err < 0)
278 return err; 278 return err;
279 res_free(dev, fh, res); 279 res_free(dev, fh, res);
280 return 0; 280 return 0;
281} 281}
282 282
283static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
284 struct v4l2_format *f)
285{
286 struct cx25821_fh *fh = priv;
287 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
288 int err;
289 int pix_format = 0;
283 290
291 if (fh) {
292 err = v4l2_prio_check(&dev->prio, &fh->prio);
293 if (0 != err)
294 return err;
295 }
296
297 dprintk(2, "%s()\n", __func__);
298 err = vidioc_try_fmt_vid_cap(file, priv, f);
284 299
285static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
286{
287 struct cx25821_fh *fh = priv;
288 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
289 int err;
290 int pix_format = 0;
291
292 if (fh)
293 {
294 err = v4l2_prio_check(&dev->prio, &fh->prio);
295 if (0 != err) 300 if (0 != err)
296 return err; 301 return err;
297 } 302
298 303 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
299 dprintk(2, "%s()\n", __func__); 304 fh->vidq.field = f->fmt.pix.field;
300 err = vidioc_try_fmt_vid_cap(file, priv, f); 305
301 306 // check if width and height is valid based on set standard
302 if (0 != err) 307 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
303 return err; 308 fh->width = f->fmt.pix.width;
304 309 }
305 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 310
306 fh->vidq.field = f->fmt.pix.field; 311 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
307 312 fh->height = f->fmt.pix.height;
308 // check if width and height is valid based on set standard 313 }
309 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 314
310 { 315 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
311 fh->width = f->fmt.pix.width; 316 pix_format = PIXEL_FRMT_411;
312 } 317 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
313 318 pix_format = PIXEL_FRMT_422;
314 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 319 else
315 { 320 return -EINVAL;
316 fh->height = f->fmt.pix.height; 321
317 } 322 cx25821_set_pixel_format(dev, SRAM_CH02, pix_format);
318 323
319 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 324 // check if cif resolution
320 pix_format = PIXEL_FRMT_411; 325 if (fh->width == 320 || fh->width == 352) {
321 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 326 dev->use_cif_resolution[SRAM_CH02] = 1;
322 pix_format = PIXEL_FRMT_422; 327 } else {
323 else 328 dev->use_cif_resolution[SRAM_CH02] = 0;
324 return -EINVAL; 329 }
325 330 dev->cif_width[SRAM_CH02] = fh->width;
326 cx25821_set_pixel_format( dev, SRAM_CH02, pix_format ); 331 medusa_set_resolution(dev, fh->width, SRAM_CH02);
327 332
328 // check if cif resolution 333 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
329 if (fh->width == 320 || fh->width == 352) 334 fh->height, fh->vidq.field);
330 { 335 cx25821_call_all(dev, video, s_fmt, f);
331 dev->use_cif_resolution[SRAM_CH02] = 1; 336
332 }else 337 return 0;
333 {
334 dev->use_cif_resolution[SRAM_CH02] = 0;
335 }
336 dev->cif_width[SRAM_CH02] = fh->width;
337 medusa_set_resolution( dev, fh->width, SRAM_CH02 );
338
339
340 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
341 cx25821_call_all(dev, video, s_fmt, f);
342
343 return 0;
344} 338}
345 339
346static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 340static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
347{ 341{
348 int ret_val = 0; 342 int ret_val = 0;
349 struct cx25821_fh *fh = priv; 343 struct cx25821_fh *fh = priv;
350 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 344 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
351 345
352 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 346 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
353 347
354 p->sequence = dev->vidq[SRAM_CH02].count; 348 p->sequence = dev->vidq[SRAM_CH02].count;
355 349
356 return ret_val; 350 return ret_val;
357} 351}
358 352
359static int vidioc_log_status (struct file *file, void *priv) 353static int vidioc_log_status(struct file *file, void *priv)
360{ 354{
361 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 355 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
362 char name[32 + 2]; 356 char name[32 + 2];
363 357
364 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH02]; 358 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH02];
365 u32 tmp = 0; 359 u32 tmp = 0;
366 360
367 snprintf(name, sizeof(name), "%s/2", dev->name); 361 snprintf(name, sizeof(name), "%s/2", dev->name);
368 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 362 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
369 dev->name); 363 dev->name);
370 364
371 cx25821_call_all(dev, core, log_status); 365 cx25821_call_all(dev, core, log_status);
372 366
373 tmp = cx_read(sram_ch->dma_ctl); 367 tmp = cx_read(sram_ch->dma_ctl);
374 printk(KERN_INFO "Video input 2 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 368 printk(KERN_INFO "Video input 2 is %s\n",
375 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 369 (tmp & 0x11) ? "streaming" : "stopped");
370 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
376 dev->name); 371 dev->name);
377 return 0; 372 return 0;
378} 373}
379 374
380static int vidioc_s_ctrl(struct file *file, void *priv, 375static int vidioc_s_ctrl(struct file *file, void *priv,
381 struct v4l2_control *ctl) 376 struct v4l2_control *ctl)
382{ 377{
383 struct cx25821_fh *fh = priv; 378 struct cx25821_fh *fh = priv;
384 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 379 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -392,68 +387,66 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
392 387
393 return cx25821_set_control(dev, ctl, SRAM_CH02); 388 return cx25821_set_control(dev, ctl, SRAM_CH02);
394} 389}
390
395// exported stuff 391// exported stuff
396static const struct v4l2_file_operations video_fops = { 392static const struct v4l2_file_operations video_fops = {
397 .owner = THIS_MODULE, 393 .owner = THIS_MODULE,
398 .open = video_open, 394 .open = video_open,
399 .release = video_release, 395 .release = video_release,
400 .read = video_read, 396 .read = video_read,
401 .poll = video_poll, 397 .poll = video_poll,
402 .mmap = video_mmap, 398 .mmap = video_mmap,
403 .ioctl = video_ioctl2, 399 .ioctl = video_ioctl2,
404}; 400};
405 401
406static const struct v4l2_ioctl_ops video_ioctl_ops = { 402static const struct v4l2_ioctl_ops video_ioctl_ops = {
407 .vidioc_querycap = vidioc_querycap, 403 .vidioc_querycap = vidioc_querycap,
408 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 404 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
409 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 405 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
410 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 406 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
411 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 407 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
412 .vidioc_reqbufs = vidioc_reqbufs, 408 .vidioc_reqbufs = vidioc_reqbufs,
413 .vidioc_querybuf = vidioc_querybuf, 409 .vidioc_querybuf = vidioc_querybuf,
414 .vidioc_qbuf = vidioc_qbuf, 410 .vidioc_qbuf = vidioc_qbuf,
415 .vidioc_dqbuf = vidioc_dqbuf, 411 .vidioc_dqbuf = vidioc_dqbuf,
416#ifdef TUNER_FLAG 412#ifdef TUNER_FLAG
417 .vidioc_s_std = vidioc_s_std, 413 .vidioc_s_std = vidioc_s_std,
418 .vidioc_querystd = vidioc_querystd, 414 .vidioc_querystd = vidioc_querystd,
419#endif 415#endif
420 .vidioc_cropcap = vidioc_cropcap, 416 .vidioc_cropcap = vidioc_cropcap,
421 .vidioc_s_crop = vidioc_s_crop, 417 .vidioc_s_crop = vidioc_s_crop,
422 .vidioc_g_crop = vidioc_g_crop, 418 .vidioc_g_crop = vidioc_g_crop,
423 .vidioc_enum_input = vidioc_enum_input, 419 .vidioc_enum_input = vidioc_enum_input,
424 .vidioc_g_input = vidioc_g_input, 420 .vidioc_g_input = vidioc_g_input,
425 .vidioc_s_input = vidioc_s_input, 421 .vidioc_s_input = vidioc_s_input,
426 .vidioc_g_ctrl = vidioc_g_ctrl, 422 .vidioc_g_ctrl = vidioc_g_ctrl,
427 .vidioc_s_ctrl = vidioc_s_ctrl, 423 .vidioc_s_ctrl = vidioc_s_ctrl,
428 .vidioc_queryctrl = vidioc_queryctrl, 424 .vidioc_queryctrl = vidioc_queryctrl,
429 .vidioc_streamon = vidioc_streamon, 425 .vidioc_streamon = vidioc_streamon,
430 .vidioc_streamoff = vidioc_streamoff, 426 .vidioc_streamoff = vidioc_streamoff,
431 .vidioc_log_status = vidioc_log_status, 427 .vidioc_log_status = vidioc_log_status,
432 .vidioc_g_priority = vidioc_g_priority, 428 .vidioc_g_priority = vidioc_g_priority,
433 .vidioc_s_priority = vidioc_s_priority, 429 .vidioc_s_priority = vidioc_s_priority,
434#ifdef CONFIG_VIDEO_V4L1_COMPAT 430#ifdef CONFIG_VIDEO_V4L1_COMPAT
435 .vidiocgmbuf = vidiocgmbuf, 431 .vidiocgmbuf = vidiocgmbuf,
436#endif 432#endif
437#ifdef TUNER_FLAG 433#ifdef TUNER_FLAG
438 .vidioc_g_tuner = vidioc_g_tuner, 434 .vidioc_g_tuner = vidioc_g_tuner,
439 .vidioc_s_tuner = vidioc_s_tuner, 435 .vidioc_s_tuner = vidioc_s_tuner,
440 .vidioc_g_frequency = vidioc_g_frequency, 436 .vidioc_g_frequency = vidioc_g_frequency,
441 .vidioc_s_frequency = vidioc_s_frequency, 437 .vidioc_s_frequency = vidioc_s_frequency,
442#endif 438#endif
443#ifdef CONFIG_VIDEO_ADV_DEBUG 439#ifdef CONFIG_VIDEO_ADV_DEBUG
444 .vidioc_g_register = vidioc_g_register, 440 .vidioc_g_register = vidioc_g_register,
445 .vidioc_s_register = vidioc_s_register, 441 .vidioc_s_register = vidioc_s_register,
446#endif 442#endif
447}; 443};
448 444
449struct video_device cx25821_video_template2 = { 445struct video_device cx25821_video_template2 = {
450 .name = "cx25821-video", 446 .name = "cx25821-video",
451 .fops = &video_fops, 447 .fops = &video_fops,
452 .minor = -1, 448 .minor = -1,
453 .ioctl_ops = &video_ioctl_ops, 449 .ioctl_ops = &video_ioctl_ops,
454 .tvnorms = CX25821_NORMS, 450 .tvnorms = CX25821_NORMS,
455 .current_norm = V4L2_STD_NTSC_M, 451 .current_norm = V4L2_STD_NTSC_M,
456}; 452};
457
458
459
diff --git a/drivers/staging/cx25821/cx25821-video3.c b/drivers/staging/cx25821/cx25821-video3.c
index 2191152d78ca..8801a8ead904 100644
--- a/drivers/staging/cx25821/cx25821-video3.c
+++ b/drivers/staging/cx25821/cx25821-video3.c
@@ -23,360 +23,356 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH03]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH03];
35 34
36 /* add jump to stopper */ 35 /* add jump to stopper */
37 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 39
41 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 41
43 if (!list_empty(&q->queued)) { 42 if (!list_empty(&q->queued)) {
44 list_add_tail(&buf->vb.queue, &q->queued); 43 list_add_tail(&buf->vb.queue, &q->queued);
45 buf->vb.state = VIDEOBUF_QUEUED; 44 buf->vb.state = VIDEOBUF_QUEUED;
46 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 46 buf->vb.i);
48 } else if (list_empty(&q->active)) { 47
49 list_add_tail(&buf->vb.queue, &q->active); 48 } else if (list_empty(&q->active)) {
50 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH03]); 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->vb.state = VIDEOBUF_ACTIVE; 50 cx25821_start_video_dma(dev, q, buf,
52 buf->count = q->count++; 51 &dev->sram_channels[SRAM_CH03]);
53 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 53 buf->count = q->count++;
55 buf, buf->vb. i, buf->count, q->count); 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 } else { 55 dprintk(2,
57 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 if (prev->vb.width == buf->vb.width && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->vb.height == buf->vb.height &&
60 prev->fmt == buf->fmt) {
61 list_add_tail(&buf->vb.queue, &q->active);
62 buf->vb.state = VIDEOBUF_ACTIVE;
63 buf->count = q->count++;
64 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
65
66 /* 64 bit bits 63-32 */
67 prev->risc.jmp[2] = cpu_to_le32(0);
68 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
69
70 } else { 58 } else {
71 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
72 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
73 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
74 } 81 }
75 }
76 82
77 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
78 { 84 dprintk(2, "active queue empty!\n");
79 dprintk(2, "active queue empty!\n"); 85 }
80 }
81} 86}
82 87
83
84static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
85 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
86 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
87 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
88 .buf_release = buffer_release, 92 .buf_release = buffer_release,
89}; 93};
90 94
91
92static int video_open(struct file *file) 95static int video_open(struct file *file)
93{ 96{
94 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
95 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
96 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
97 struct list_head *list; 100 struct list_head *list;
98 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
99 u32 pix_format; 102 u32 pix_format;
100 103
101 lock_kernel(); 104 lock_kernel();
102 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
103 { 106 h = list_entry(list, struct cx25821_dev, devlist);
104 h = list_entry(list, struct cx25821_dev, devlist); 107
105 108 if (h->video_dev[SRAM_CH03]
106 if (h->video_dev[SRAM_CH03] && h->video_dev[SRAM_CH03]->minor == minor) { 109 && h->video_dev[SRAM_CH03]->minor == minor) {
107 dev = h; 110 dev = h;
108 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
112 }
109 } 113 }
110 }
111 114
112 if (NULL == dev) { 115 if (NULL == dev) {
113 unlock_kernel(); 116 unlock_kernel();
114 return -ENODEV; 117 return -ENODEV;
115 } 118 }
116 119
117 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
118 121
119 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
120 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
121 if (NULL == fh) { 124 if (NULL == fh) {
125 unlock_kernel();
126 return -ENOMEM;
127 }
128 file->private_data = fh;
129 fh->dev = dev;
130 fh->type = type;
131 fh->width = 720;
132
133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
134 fh->height = 576;
135 else
136 fh->height = 480;
137
138 dev->channel_opened = SRAM_CH03;
139 pix_format =
140 (dev->pixel_formats[dev->channel_opened] ==
141 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
142 fh->fmt = format_by_fourcc(pix_format);
143
144 v4l2_prio_open(&dev->prio, &fh->prio);
145
146 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
147 &dev->pci->dev, &dev->slock,
148 V4L2_BUF_TYPE_VIDEO_CAPTURE,
149 V4L2_FIELD_INTERLACED,
150 sizeof(struct cx25821_buffer), fh);
151
152 dprintk(1, "post videobuf_queue_init()\n");
122 unlock_kernel(); 153 unlock_kernel();
123 return -ENOMEM; 154
124 } 155 return 0;
125 file->private_data = fh;
126 fh->dev = dev;
127 fh->type = type;
128 fh->width = 720;
129
130 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
131 fh->height = 576;
132 else
133 fh->height = 480;
134
135 dev->channel_opened = SRAM_CH03;
136 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
137 fh->fmt = format_by_fourcc(pix_format);
138
139 v4l2_prio_open(&dev->prio,&fh->prio);
140
141 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
142 &dev->pci->dev, &dev->slock,
143 V4L2_BUF_TYPE_VIDEO_CAPTURE,
144 V4L2_FIELD_INTERLACED,
145 sizeof(struct cx25821_buffer),
146 fh);
147
148 dprintk(1, "post videobuf_queue_init()\n");
149 unlock_kernel();
150
151 return 0;
152} 156}
153 157
154static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 158static ssize_t video_read(struct file *file, char __user * data, size_t count,
159 loff_t * ppos)
155{ 160{
156 struct cx25821_fh *fh = file->private_data; 161 struct cx25821_fh *fh = file->private_data;
157 162
158 switch (fh->type) 163 switch (fh->type) {
159 {
160 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 164 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
161 if (res_locked(fh->dev, RESOURCE_VIDEO3)) 165 if (res_locked(fh->dev, RESOURCE_VIDEO3))
162 return -EBUSY; 166 return -EBUSY;
163 167
164 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 168 return videobuf_read_one(&fh->vidq, data, count, ppos,
169 file->f_flags & O_NONBLOCK);
165 170
166 default: 171 default:
167 BUG(); 172 BUG();
168 return 0; 173 return 0;
169 } 174 }
170} 175}
171 176
172static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 177static unsigned int video_poll(struct file *file,
178 struct poll_table_struct *wait)
173{ 179{
174 struct cx25821_fh *fh = file->private_data; 180 struct cx25821_fh *fh = file->private_data;
175 struct cx25821_buffer *buf; 181 struct cx25821_buffer *buf;
176 182
177 if (res_check(fh, RESOURCE_VIDEO3)) { 183 if (res_check(fh, RESOURCE_VIDEO3)) {
178 /* streaming capture */ 184 /* streaming capture */
179 if (list_empty(&fh->vidq.stream)) 185 if (list_empty(&fh->vidq.stream))
180 return POLLERR; 186 return POLLERR;
181 buf = list_entry(fh->vidq.stream.next, 187 buf = list_entry(fh->vidq.stream.next,
182 struct cx25821_buffer, vb.stream); 188 struct cx25821_buffer, vb.stream);
183 } else { 189 } else {
184 /* read() capture */ 190 /* read() capture */
185 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 191 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
186 if (NULL == buf) 192 if (NULL == buf)
187 return POLLERR; 193 return POLLERR;
188 }
189
190 poll_wait(file, &buf->vb.done, wait);
191 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
192 {
193 if( buf->vb.state == VIDEOBUF_DONE )
194 {
195 struct cx25821_dev *dev = fh->dev;
196
197 if( dev && dev->use_cif_resolution[SRAM_CH03] )
198 {
199 u8 cam_id = *((char*)buf->vb.baddr+3);
200 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
201 *((char*)buf->vb.baddr+3) = cam_id;
202 }
203 } 194 }
204 195
205 return POLLIN|POLLRDNORM; 196 poll_wait(file, &buf->vb.done, wait);
206 } 197 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
198 if (buf->vb.state == VIDEOBUF_DONE) {
199 struct cx25821_dev *dev = fh->dev;
200
201 if (dev && dev->use_cif_resolution[SRAM_CH03]) {
202 u8 cam_id = *((char *)buf->vb.baddr + 3);
203 memcpy((char *)buf->vb.baddr,
204 (char *)buf->vb.baddr + (fh->width * 2),
205 (fh->width * 2));
206 *((char *)buf->vb.baddr + 3) = cam_id;
207 }
208 }
209
210 return POLLIN | POLLRDNORM;
211 }
207 212
208 return 0; 213 return 0;
209} 214}
210 215
211
212static int video_release(struct file *file) 216static int video_release(struct file *file)
213{ 217{
214 struct cx25821_fh *fh = file->private_data; 218 struct cx25821_fh *fh = file->private_data;
215 struct cx25821_dev *dev = fh->dev; 219 struct cx25821_dev *dev = fh->dev;
216 220
217 //stop the risc engine and fifo 221 //stop the risc engine and fifo
218 cx_write(channel3->dma_ctl, 0); /* FIFO and RISC disable */ 222 cx_write(channel3->dma_ctl, 0); /* FIFO and RISC disable */
219 223
220 /* stop video capture */ 224 /* stop video capture */
221 if (res_check(fh, RESOURCE_VIDEO3)) { 225 if (res_check(fh, RESOURCE_VIDEO3)) {
222 videobuf_queue_cancel(&fh->vidq); 226 videobuf_queue_cancel(&fh->vidq);
223 res_free(dev, fh, RESOURCE_VIDEO3); 227 res_free(dev, fh, RESOURCE_VIDEO3);
224 } 228 }
225 229
226 if (fh->vidq.read_buf) { 230 if (fh->vidq.read_buf) {
227 buffer_release(&fh->vidq, fh->vidq.read_buf); 231 buffer_release(&fh->vidq, fh->vidq.read_buf);
228 kfree(fh->vidq.read_buf); 232 kfree(fh->vidq.read_buf);
229 } 233 }
230 234
231 videobuf_mmap_free(&fh->vidq); 235 videobuf_mmap_free(&fh->vidq);
232 236
233 v4l2_prio_close(&dev->prio,&fh->prio); 237 v4l2_prio_close(&dev->prio, &fh->prio);
234 file->private_data = NULL; 238 file->private_data = NULL;
235 kfree(fh); 239 kfree(fh);
236 240
237 return 0; 241 return 0;
238} 242}
239 243
240
241static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 244static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
242{ 245{
243 struct cx25821_fh *fh = priv; 246 struct cx25821_fh *fh = priv;
244 struct cx25821_dev *dev = fh->dev; 247 struct cx25821_dev *dev = fh->dev;
245 248
246 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 249 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
247 { 250 return -EINVAL;
248 return -EINVAL; 251 }
249 }
250 252
251 if (unlikely(i != fh->type)) 253 if (unlikely(i != fh->type)) {
252 { 254 return -EINVAL;
253 return -EINVAL; 255 }
254 }
255 256
256 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO3)))) 257 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO3)))) {
257 { 258 return -EBUSY;
258 return -EBUSY; 259 }
259 }
260 260
261 return videobuf_streamon(get_queue(fh)); 261 return videobuf_streamon(get_queue(fh));
262} 262}
263 263
264static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 264static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
265{ 265{
266 struct cx25821_fh *fh = priv; 266 struct cx25821_fh *fh = priv;
267 struct cx25821_dev *dev = fh->dev; 267 struct cx25821_dev *dev = fh->dev;
268 int err, res; 268 int err, res;
269 269
270 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 270 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
271 return -EINVAL; 271 return -EINVAL;
272 if (i != fh->type) 272 if (i != fh->type)
273 return -EINVAL; 273 return -EINVAL;
274 274
275 res = get_resource(fh, RESOURCE_VIDEO3); 275 res = get_resource(fh, RESOURCE_VIDEO3);
276 err = videobuf_streamoff(get_queue(fh)); 276 err = videobuf_streamoff(get_queue(fh));
277 if (err < 0) 277 if (err < 0)
278 return err; 278 return err;
279 res_free(dev, fh, res); 279 res_free(dev, fh, res);
280 return 0; 280 return 0;
281} 281}
282 282
283static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
284 struct v4l2_format *f)
285{
286 struct cx25821_fh *fh = priv;
287 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
288 int err;
289 int pix_format = 0;
290
291 if (fh) {
292 err = v4l2_prio_check(&dev->prio, &fh->prio);
293 if (0 != err)
294 return err;
295 }
283 296
297 dprintk(2, "%s()\n", __func__);
298 err = vidioc_try_fmt_vid_cap(file, priv, f);
284 299
285static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
286{
287 struct cx25821_fh *fh = priv;
288 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
289 int err;
290 int pix_format = 0;
291
292 if (fh)
293 {
294 err = v4l2_prio_check(&dev->prio, &fh->prio);
295 if (0 != err) 300 if (0 != err)
296 return err; 301 return err;
297 } 302
298 303 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
299 dprintk(2, "%s()\n", __func__); 304 fh->vidq.field = f->fmt.pix.field;
300 err = vidioc_try_fmt_vid_cap(file, priv, f); 305
301 306 // check if width and height is valid based on set standard
302 if (0 != err) 307 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
303 return err; 308 fh->width = f->fmt.pix.width;
304 309 }
305 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 310
306 fh->vidq.field = f->fmt.pix.field; 311 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
307 312 fh->height = f->fmt.pix.height;
308 // check if width and height is valid based on set standard 313 }
309 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 314
310 { 315 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
311 fh->width = f->fmt.pix.width; 316 pix_format = PIXEL_FRMT_411;
312 } 317 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
313 318 pix_format = PIXEL_FRMT_422;
314 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 319 else
315 { 320 return -EINVAL;
316 fh->height = f->fmt.pix.height; 321
317 } 322 cx25821_set_pixel_format(dev, SRAM_CH03, pix_format);
318 323
319 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 324 // check if cif resolution
320 pix_format = PIXEL_FRMT_411; 325 if (fh->width == 320 || fh->width == 352) {
321 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 326 dev->use_cif_resolution[SRAM_CH03] = 1;
322 pix_format = PIXEL_FRMT_422; 327 } else {
323 else 328 dev->use_cif_resolution[SRAM_CH03] = 0;
324 return -EINVAL; 329 }
325 330 dev->cif_width[SRAM_CH03] = fh->width;
326 cx25821_set_pixel_format( dev, SRAM_CH03, pix_format ); 331 medusa_set_resolution(dev, fh->width, SRAM_CH03);
327 332
328 // check if cif resolution 333 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
329 if (fh->width == 320 || fh->width == 352) 334 fh->height, fh->vidq.field);
330 { 335 cx25821_call_all(dev, video, s_fmt, f);
331 dev->use_cif_resolution[SRAM_CH03] = 1; 336
332 }else 337 return 0;
333 {
334 dev->use_cif_resolution[SRAM_CH03] = 0;
335 }
336 dev->cif_width[SRAM_CH03] = fh->width;
337 medusa_set_resolution( dev, fh->width, SRAM_CH03 );
338
339 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
340 cx25821_call_all(dev, video, s_fmt, f);
341
342 return 0;
343} 338}
344 339
345static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 340static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
346{ 341{
347 int ret_val = 0; 342 int ret_val = 0;
348 struct cx25821_fh *fh = priv; 343 struct cx25821_fh *fh = priv;
349 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 344 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
350 345
351 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 346 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
352 347
353 p->sequence = dev->vidq[SRAM_CH03].count; 348 p->sequence = dev->vidq[SRAM_CH03].count;
354 349
355 return ret_val; 350 return ret_val;
356} 351}
357 352
358static int vidioc_log_status (struct file *file, void *priv) 353static int vidioc_log_status(struct file *file, void *priv)
359{ 354{
360 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 355 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
361 char name[32 + 2]; 356 char name[32 + 2];
362 357
363 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH03]; 358 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH03];
364 u32 tmp = 0; 359 u32 tmp = 0;
365 360
366 snprintf(name, sizeof(name), "%s/2", dev->name); 361 snprintf(name, sizeof(name), "%s/2", dev->name);
367 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 362 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
368 dev->name); 363 dev->name);
369 cx25821_call_all(dev, core, log_status); 364 cx25821_call_all(dev, core, log_status);
370 365
371 tmp = cx_read(sram_ch->dma_ctl); 366 tmp = cx_read(sram_ch->dma_ctl);
372 printk(KERN_INFO "Video input 3 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 367 printk(KERN_INFO "Video input 3 is %s\n",
373 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 368 (tmp & 0x11) ? "streaming" : "stopped");
369 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
374 dev->name); 370 dev->name);
375 return 0; 371 return 0;
376} 372}
377 373
378static int vidioc_s_ctrl(struct file *file, void *priv, 374static int vidioc_s_ctrl(struct file *file, void *priv,
379 struct v4l2_control *ctl) 375 struct v4l2_control *ctl)
380{ 376{
381 struct cx25821_fh *fh = priv; 377 struct cx25821_fh *fh = priv;
382 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 378 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -393,66 +389,63 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
393 389
394// exported stuff 390// exported stuff
395static const struct v4l2_file_operations video_fops = { 391static const struct v4l2_file_operations video_fops = {
396 .owner = THIS_MODULE, 392 .owner = THIS_MODULE,
397 .open = video_open, 393 .open = video_open,
398 .release = video_release, 394 .release = video_release,
399 .read = video_read, 395 .read = video_read,
400 .poll = video_poll, 396 .poll = video_poll,
401 .mmap = video_mmap, 397 .mmap = video_mmap,
402 .ioctl = video_ioctl2, 398 .ioctl = video_ioctl2,
403}; 399};
404 400
405static const struct v4l2_ioctl_ops video_ioctl_ops = { 401static const struct v4l2_ioctl_ops video_ioctl_ops = {
406 .vidioc_querycap = vidioc_querycap, 402 .vidioc_querycap = vidioc_querycap,
407 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 403 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
408 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 404 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
409 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 405 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
410 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 406 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
411 .vidioc_reqbufs = vidioc_reqbufs, 407 .vidioc_reqbufs = vidioc_reqbufs,
412 .vidioc_querybuf = vidioc_querybuf, 408 .vidioc_querybuf = vidioc_querybuf,
413 .vidioc_qbuf = vidioc_qbuf, 409 .vidioc_qbuf = vidioc_qbuf,
414 .vidioc_dqbuf = vidioc_dqbuf, 410 .vidioc_dqbuf = vidioc_dqbuf,
415#ifdef TUNER_FLAG 411#ifdef TUNER_FLAG
416 .vidioc_s_std = vidioc_s_std, 412 .vidioc_s_std = vidioc_s_std,
417 .vidioc_querystd = vidioc_querystd, 413 .vidioc_querystd = vidioc_querystd,
418#endif 414#endif
419 .vidioc_cropcap = vidioc_cropcap, 415 .vidioc_cropcap = vidioc_cropcap,
420 .vidioc_s_crop = vidioc_s_crop, 416 .vidioc_s_crop = vidioc_s_crop,
421 .vidioc_g_crop = vidioc_g_crop, 417 .vidioc_g_crop = vidioc_g_crop,
422 .vidioc_enum_input = vidioc_enum_input, 418 .vidioc_enum_input = vidioc_enum_input,
423 .vidioc_g_input = vidioc_g_input, 419 .vidioc_g_input = vidioc_g_input,
424 .vidioc_s_input = vidioc_s_input, 420 .vidioc_s_input = vidioc_s_input,
425 .vidioc_g_ctrl = vidioc_g_ctrl, 421 .vidioc_g_ctrl = vidioc_g_ctrl,
426 .vidioc_s_ctrl = vidioc_s_ctrl, 422 .vidioc_s_ctrl = vidioc_s_ctrl,
427 .vidioc_queryctrl = vidioc_queryctrl, 423 .vidioc_queryctrl = vidioc_queryctrl,
428 .vidioc_streamon = vidioc_streamon, 424 .vidioc_streamon = vidioc_streamon,
429 .vidioc_streamoff = vidioc_streamoff, 425 .vidioc_streamoff = vidioc_streamoff,
430 .vidioc_log_status = vidioc_log_status, 426 .vidioc_log_status = vidioc_log_status,
431 .vidioc_g_priority = vidioc_g_priority, 427 .vidioc_g_priority = vidioc_g_priority,
432 .vidioc_s_priority = vidioc_s_priority, 428 .vidioc_s_priority = vidioc_s_priority,
433#ifdef CONFIG_VIDEO_V4L1_COMPAT 429#ifdef CONFIG_VIDEO_V4L1_COMPAT
434 .vidiocgmbuf = vidiocgmbuf, 430 .vidiocgmbuf = vidiocgmbuf,
435#endif 431#endif
436#ifdef TUNER_FLAG 432#ifdef TUNER_FLAG
437 .vidioc_g_tuner = vidioc_g_tuner, 433 .vidioc_g_tuner = vidioc_g_tuner,
438 .vidioc_s_tuner = vidioc_s_tuner, 434 .vidioc_s_tuner = vidioc_s_tuner,
439 .vidioc_g_frequency = vidioc_g_frequency, 435 .vidioc_g_frequency = vidioc_g_frequency,
440 .vidioc_s_frequency = vidioc_s_frequency, 436 .vidioc_s_frequency = vidioc_s_frequency,
441#endif 437#endif
442#ifdef CONFIG_VIDEO_ADV_DEBUG 438#ifdef CONFIG_VIDEO_ADV_DEBUG
443 .vidioc_g_register = vidioc_g_register, 439 .vidioc_g_register = vidioc_g_register,
444 .vidioc_s_register = vidioc_s_register, 440 .vidioc_s_register = vidioc_s_register,
445#endif 441#endif
446}; 442};
447 443
448struct video_device cx25821_video_template3 = { 444struct video_device cx25821_video_template3 = {
449 .name = "cx25821-video", 445 .name = "cx25821-video",
450 .fops = &video_fops, 446 .fops = &video_fops,
451 .minor = -1, 447 .minor = -1,
452 .ioctl_ops = &video_ioctl_ops, 448 .ioctl_ops = &video_ioctl_ops,
453 .tvnorms = CX25821_NORMS, 449 .tvnorms = CX25821_NORMS,
454 .current_norm = V4L2_STD_NTSC_M, 450 .current_norm = V4L2_STD_NTSC_M,
455}; 451};
456
457
458
diff --git a/drivers/staging/cx25821/cx25821-video4.c b/drivers/staging/cx25821/cx25821-video4.c
index c1799d981359..ab0d747138ad 100644
--- a/drivers/staging/cx25821/cx25821-video4.c
+++ b/drivers/staging/cx25821/cx25821-video4.c
@@ -23,358 +23,355 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH04]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH04];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH04]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[SRAM_CH04]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 u32 pix_format; 102 u32 pix_format;
99 103
100 lock_kernel(); 104 lock_kernel();
101 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
102 { 106 h = list_entry(list, struct cx25821_dev, devlist);
103 h = list_entry(list, struct cx25821_dev, devlist); 107
104 108 if (h->video_dev[SRAM_CH04]
105 if (h->video_dev[SRAM_CH04] && h->video_dev[SRAM_CH04]->minor == minor) { 109 && h->video_dev[SRAM_CH04]->minor == minor) {
106 dev = h; 110 dev = h;
107 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
112 }
108 } 113 }
109 }
110 114
111 if (NULL == dev) { 115 if (NULL == dev) {
112 unlock_kernel(); 116 unlock_kernel();
113 return -ENODEV; 117 return -ENODEV;
114 } 118 }
115 119
116 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
117 121
118 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
119 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
120 if (NULL == fh) { 124 if (NULL == fh) {
125 unlock_kernel();
126 return -ENOMEM;
127 }
128 file->private_data = fh;
129 fh->dev = dev;
130 fh->type = type;
131 fh->width = 720;
132
133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
134 fh->height = 576;
135 else
136 fh->height = 480;
137
138 dev->channel_opened = SRAM_CH04;
139 pix_format =
140 (dev->pixel_formats[dev->channel_opened] ==
141 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
142 fh->fmt = format_by_fourcc(pix_format);
143
144 v4l2_prio_open(&dev->prio, &fh->prio);
145 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
146 &dev->pci->dev, &dev->slock,
147 V4L2_BUF_TYPE_VIDEO_CAPTURE,
148 V4L2_FIELD_INTERLACED,
149 sizeof(struct cx25821_buffer), fh);
150
151 dprintk(1, "post videobuf_queue_init()\n");
121 unlock_kernel(); 152 unlock_kernel();
122 return -ENOMEM; 153
123 } 154 return 0;
124 file->private_data = fh;
125 fh->dev = dev;
126 fh->type = type;
127 fh->width = 720;
128
129 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
130 fh->height = 576;
131 else
132 fh->height = 480;
133
134 dev->channel_opened = SRAM_CH04;
135 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
136 fh->fmt = format_by_fourcc(pix_format);
137
138 v4l2_prio_open(&dev->prio,&fh->prio);
139 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
140 &dev->pci->dev, &dev->slock,
141 V4L2_BUF_TYPE_VIDEO_CAPTURE,
142 V4L2_FIELD_INTERLACED,
143 sizeof(struct cx25821_buffer),
144 fh);
145
146 dprintk(1, "post videobuf_queue_init()\n");
147 unlock_kernel();
148
149 return 0;
150} 155}
151 156
152static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 157static ssize_t video_read(struct file *file, char __user * data, size_t count,
158 loff_t * ppos)
153{ 159{
154 struct cx25821_fh *fh = file->private_data; 160 struct cx25821_fh *fh = file->private_data;
155 161
156 switch (fh->type) 162 switch (fh->type) {
157 {
158 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 163 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
159 if (res_locked(fh->dev, RESOURCE_VIDEO4)) 164 if (res_locked(fh->dev, RESOURCE_VIDEO4))
160 return -EBUSY; 165 return -EBUSY;
161 166
162 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 167 return videobuf_read_one(&fh->vidq, data, count, ppos,
168 file->f_flags & O_NONBLOCK);
163 169
164 default: 170 default:
165 BUG(); 171 BUG();
166 return 0; 172 return 0;
167 } 173 }
168} 174}
169 175
170static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 176static unsigned int video_poll(struct file *file,
177 struct poll_table_struct *wait)
171{ 178{
172 struct cx25821_fh *fh = file->private_data; 179 struct cx25821_fh *fh = file->private_data;
173 struct cx25821_buffer *buf; 180 struct cx25821_buffer *buf;
174 181
175 if (res_check(fh, RESOURCE_VIDEO4)) { 182 if (res_check(fh, RESOURCE_VIDEO4)) {
176 /* streaming capture */ 183 /* streaming capture */
177 if (list_empty(&fh->vidq.stream)) 184 if (list_empty(&fh->vidq.stream))
178 return POLLERR; 185 return POLLERR;
179 buf = list_entry(fh->vidq.stream.next, 186 buf = list_entry(fh->vidq.stream.next,
180 struct cx25821_buffer, vb.stream); 187 struct cx25821_buffer, vb.stream);
181 } else { 188 } else {
182 /* read() capture */ 189 /* read() capture */
183 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 190 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
184 if (NULL == buf) 191 if (NULL == buf)
185 return POLLERR; 192 return POLLERR;
186 }
187
188 poll_wait(file, &buf->vb.done, wait);
189 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
190 {
191 if( buf->vb.state == VIDEOBUF_DONE )
192 {
193 struct cx25821_dev *dev = fh->dev;
194
195 if( dev && dev->use_cif_resolution[SRAM_CH04] )
196 {
197 u8 cam_id = *((char*)buf->vb.baddr+3);
198 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
199 *((char*)buf->vb.baddr+3) = cam_id;
200 }
201 } 193 }
202 194
203 return POLLIN|POLLRDNORM; 195 poll_wait(file, &buf->vb.done, wait);
204 } 196 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
197 if (buf->vb.state == VIDEOBUF_DONE) {
198 struct cx25821_dev *dev = fh->dev;
199
200 if (dev && dev->use_cif_resolution[SRAM_CH04]) {
201 u8 cam_id = *((char *)buf->vb.baddr + 3);
202 memcpy((char *)buf->vb.baddr,
203 (char *)buf->vb.baddr + (fh->width * 2),
204 (fh->width * 2));
205 *((char *)buf->vb.baddr + 3) = cam_id;
206 }
207 }
208
209 return POLLIN | POLLRDNORM;
210 }
205 211
206 return 0; 212 return 0;
207} 213}
208 214
209
210static int video_release(struct file *file) 215static int video_release(struct file *file)
211{ 216{
212 struct cx25821_fh *fh = file->private_data; 217 struct cx25821_fh *fh = file->private_data;
213 struct cx25821_dev *dev = fh->dev; 218 struct cx25821_dev *dev = fh->dev;
214 219
215 //stop the risc engine and fifo 220 //stop the risc engine and fifo
216 cx_write(channel4->dma_ctl, 0); /* FIFO and RISC disable */ 221 cx_write(channel4->dma_ctl, 0); /* FIFO and RISC disable */
217 222
218 /* stop video capture */ 223 /* stop video capture */
219 if (res_check(fh, RESOURCE_VIDEO4)) { 224 if (res_check(fh, RESOURCE_VIDEO4)) {
220 videobuf_queue_cancel(&fh->vidq); 225 videobuf_queue_cancel(&fh->vidq);
221 res_free(dev, fh, RESOURCE_VIDEO4); 226 res_free(dev, fh, RESOURCE_VIDEO4);
222 } 227 }
223 228
224 if (fh->vidq.read_buf) { 229 if (fh->vidq.read_buf) {
225 buffer_release(&fh->vidq, fh->vidq.read_buf); 230 buffer_release(&fh->vidq, fh->vidq.read_buf);
226 kfree(fh->vidq.read_buf); 231 kfree(fh->vidq.read_buf);
227 } 232 }
228 233
229 videobuf_mmap_free(&fh->vidq); 234 videobuf_mmap_free(&fh->vidq);
230 235
231 v4l2_prio_close(&dev->prio,&fh->prio); 236 v4l2_prio_close(&dev->prio, &fh->prio);
232 file->private_data = NULL; 237 file->private_data = NULL;
233 kfree(fh); 238 kfree(fh);
234 239
235 return 0; 240 return 0;
236} 241}
237 242
238
239static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 243static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
240{ 244{
241 struct cx25821_fh *fh = priv; 245 struct cx25821_fh *fh = priv;
242 struct cx25821_dev *dev = fh->dev; 246 struct cx25821_dev *dev = fh->dev;
243 247
244 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 248 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
245 { 249 return -EINVAL;
246 return -EINVAL; 250 }
247 }
248 251
249 if (unlikely(i != fh->type)) 252 if (unlikely(i != fh->type)) {
250 { 253 return -EINVAL;
251 return -EINVAL; 254 }
252 }
253 255
254 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO4)))) 256 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO4)))) {
255 { 257 return -EBUSY;
256 return -EBUSY; 258 }
257 }
258 259
259 return videobuf_streamon(get_queue(fh)); 260 return videobuf_streamon(get_queue(fh));
260} 261}
261 262
262static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 263static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
263{ 264{
264 struct cx25821_fh *fh = priv; 265 struct cx25821_fh *fh = priv;
265 struct cx25821_dev *dev = fh->dev; 266 struct cx25821_dev *dev = fh->dev;
266 int err, res; 267 int err, res;
267 268
268 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 269 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
269 return -EINVAL; 270 return -EINVAL;
270 if (i != fh->type) 271 if (i != fh->type)
271 return -EINVAL; 272 return -EINVAL;
272 273
273 res = get_resource(fh, RESOURCE_VIDEO4); 274 res = get_resource(fh, RESOURCE_VIDEO4);
274 err = videobuf_streamoff(get_queue(fh)); 275 err = videobuf_streamoff(get_queue(fh));
275 if (err < 0) 276 if (err < 0)
276 return err; 277 return err;
277 res_free(dev, fh, res); 278 res_free(dev, fh, res);
278 return 0; 279 return 0;
279} 280}
280 281
282static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
283 struct v4l2_format *f)
284{
285 struct cx25821_fh *fh = priv;
286 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
287 int err;
288 int pix_format = 0;
281 289
290 // check priority
291 if (fh) {
292 err = v4l2_prio_check(&dev->prio, &fh->prio);
293 if (0 != err)
294 return err;
295 }
296 dprintk(2, "%s()\n", __func__);
297 err = vidioc_try_fmt_vid_cap(file, priv, f);
282 298
283static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
284{
285 struct cx25821_fh *fh = priv;
286 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
287 int err;
288 int pix_format = 0;
289
290 // check priority
291 if (fh)
292 {
293 err = v4l2_prio_check(&dev->prio, &fh->prio);
294 if (0 != err) 299 if (0 != err)
295 return err; 300 return err;
296 } 301
297 dprintk(2, "%s()\n", __func__); 302 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
298 err = vidioc_try_fmt_vid_cap(file, priv, f); 303 fh->vidq.field = f->fmt.pix.field;
299 304
300 if (0 != err) 305 // check if width and height is valid based on set standard
301 return err; 306 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
302 307 fh->width = f->fmt.pix.width;
303 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 308 }
304 fh->vidq.field = f->fmt.pix.field; 309
305 310 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
306 // check if width and height is valid based on set standard 311 fh->height = f->fmt.pix.height;
307 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 312 }
308 { 313
309 fh->width = f->fmt.pix.width; 314 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
310 } 315 pix_format = PIXEL_FRMT_411;
311 316 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
312 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 317 pix_format = PIXEL_FRMT_422;
313 { 318 else
314 fh->height = f->fmt.pix.height; 319 return -EINVAL;
315 } 320
316 321 cx25821_set_pixel_format(dev, SRAM_CH04, pix_format);
317 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 322
318 pix_format = PIXEL_FRMT_411; 323 // check if cif resolution
319 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 324 if (fh->width == 320 || fh->width == 352) {
320 pix_format = PIXEL_FRMT_422; 325 dev->use_cif_resolution[SRAM_CH04] = 1;
321 else 326 } else {
322 return -EINVAL; 327 dev->use_cif_resolution[SRAM_CH04] = 0;
323 328 }
324 cx25821_set_pixel_format( dev, SRAM_CH04, pix_format ); 329 dev->cif_width[SRAM_CH04] = fh->width;
325 330 medusa_set_resolution(dev, fh->width, SRAM_CH04);
326 // check if cif resolution 331
327 if (fh->width == 320 || fh->width == 352) 332 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
328 { 333 fh->height, fh->vidq.field);
329 dev->use_cif_resolution[SRAM_CH04] = 1; 334 cx25821_call_all(dev, video, s_fmt, f);
330 }else 335
331 { 336 return 0;
332 dev->use_cif_resolution[SRAM_CH04] = 0;
333 }
334 dev->cif_width[SRAM_CH04] = fh->width;
335 medusa_set_resolution( dev, fh->width, SRAM_CH04);
336
337 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
338 cx25821_call_all(dev, video, s_fmt, f);
339
340 return 0;
341} 337}
342 338
343static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 339static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
344{ 340{
345 int ret_val = 0; 341 int ret_val = 0;
346 struct cx25821_fh *fh = priv; 342 struct cx25821_fh *fh = priv;
347 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 343 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
348 344
349 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 345 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
350 346
351 p->sequence = dev->vidq[SRAM_CH04].count; 347 p->sequence = dev->vidq[SRAM_CH04].count;
352 348
353 return ret_val; 349 return ret_val;
354} 350}
355 351
356static int vidioc_log_status (struct file *file, void *priv) 352static int vidioc_log_status(struct file *file, void *priv)
357{ 353{
358 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 354 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
359 char name[32 + 2]; 355 char name[32 + 2];
360 356
361 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH04]; 357 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH04];
362 u32 tmp = 0; 358 u32 tmp = 0;
363 359
364 snprintf(name, sizeof(name), "%s/2", dev->name); 360 snprintf(name, sizeof(name), "%s/2", dev->name);
365 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 361 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
366 dev->name); 362 dev->name);
367 cx25821_call_all(dev, core, log_status); 363 cx25821_call_all(dev, core, log_status);
368 364
369 tmp = cx_read(sram_ch->dma_ctl); 365 tmp = cx_read(sram_ch->dma_ctl);
370 printk(KERN_INFO "Video input 4 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 366 printk(KERN_INFO "Video input 4 is %s\n",
371 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 367 (tmp & 0x11) ? "streaming" : "stopped");
368 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
372 dev->name); 369 dev->name);
373 return 0; 370 return 0;
374} 371}
375 372
376static int vidioc_s_ctrl(struct file *file, void *priv, 373static int vidioc_s_ctrl(struct file *file, void *priv,
377 struct v4l2_control *ctl) 374 struct v4l2_control *ctl)
378{ 375{
379 struct cx25821_fh *fh = priv; 376 struct cx25821_fh *fh = priv;
380 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 377 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -391,66 +388,63 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
391 388
392// exported stuff 389// exported stuff
393static const struct v4l2_file_operations video_fops = { 390static const struct v4l2_file_operations video_fops = {
394 .owner = THIS_MODULE, 391 .owner = THIS_MODULE,
395 .open = video_open, 392 .open = video_open,
396 .release = video_release, 393 .release = video_release,
397 .read = video_read, 394 .read = video_read,
398 .poll = video_poll, 395 .poll = video_poll,
399 .mmap = video_mmap, 396 .mmap = video_mmap,
400 .ioctl = video_ioctl2, 397 .ioctl = video_ioctl2,
401}; 398};
402 399
403static const struct v4l2_ioctl_ops video_ioctl_ops = { 400static const struct v4l2_ioctl_ops video_ioctl_ops = {
404 .vidioc_querycap = vidioc_querycap, 401 .vidioc_querycap = vidioc_querycap,
405 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 402 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
406 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 403 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
407 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 404 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
408 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 405 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
409 .vidioc_reqbufs = vidioc_reqbufs, 406 .vidioc_reqbufs = vidioc_reqbufs,
410 .vidioc_querybuf = vidioc_querybuf, 407 .vidioc_querybuf = vidioc_querybuf,
411 .vidioc_qbuf = vidioc_qbuf, 408 .vidioc_qbuf = vidioc_qbuf,
412 .vidioc_dqbuf = vidioc_dqbuf, 409 .vidioc_dqbuf = vidioc_dqbuf,
413#ifdef TUNER_FLAG 410#ifdef TUNER_FLAG
414 .vidioc_s_std = vidioc_s_std, 411 .vidioc_s_std = vidioc_s_std,
415 .vidioc_querystd = vidioc_querystd, 412 .vidioc_querystd = vidioc_querystd,
416#endif 413#endif
417 .vidioc_cropcap = vidioc_cropcap, 414 .vidioc_cropcap = vidioc_cropcap,
418 .vidioc_s_crop = vidioc_s_crop, 415 .vidioc_s_crop = vidioc_s_crop,
419 .vidioc_g_crop = vidioc_g_crop, 416 .vidioc_g_crop = vidioc_g_crop,
420 .vidioc_enum_input = vidioc_enum_input, 417 .vidioc_enum_input = vidioc_enum_input,
421 .vidioc_g_input = vidioc_g_input, 418 .vidioc_g_input = vidioc_g_input,
422 .vidioc_s_input = vidioc_s_input, 419 .vidioc_s_input = vidioc_s_input,
423 .vidioc_g_ctrl = vidioc_g_ctrl, 420 .vidioc_g_ctrl = vidioc_g_ctrl,
424 .vidioc_s_ctrl = vidioc_s_ctrl, 421 .vidioc_s_ctrl = vidioc_s_ctrl,
425 .vidioc_queryctrl = vidioc_queryctrl, 422 .vidioc_queryctrl = vidioc_queryctrl,
426 .vidioc_streamon = vidioc_streamon, 423 .vidioc_streamon = vidioc_streamon,
427 .vidioc_streamoff = vidioc_streamoff, 424 .vidioc_streamoff = vidioc_streamoff,
428 .vidioc_log_status = vidioc_log_status, 425 .vidioc_log_status = vidioc_log_status,
429 .vidioc_g_priority = vidioc_g_priority, 426 .vidioc_g_priority = vidioc_g_priority,
430 .vidioc_s_priority = vidioc_s_priority, 427 .vidioc_s_priority = vidioc_s_priority,
431#ifdef CONFIG_VIDEO_V4L1_COMPAT 428#ifdef CONFIG_VIDEO_V4L1_COMPAT
432 .vidiocgmbuf = vidiocgmbuf, 429 .vidiocgmbuf = vidiocgmbuf,
433#endif 430#endif
434#ifdef TUNER_FLAG 431#ifdef TUNER_FLAG
435 .vidioc_g_tuner = vidioc_g_tuner, 432 .vidioc_g_tuner = vidioc_g_tuner,
436 .vidioc_s_tuner = vidioc_s_tuner, 433 .vidioc_s_tuner = vidioc_s_tuner,
437 .vidioc_g_frequency = vidioc_g_frequency, 434 .vidioc_g_frequency = vidioc_g_frequency,
438 .vidioc_s_frequency = vidioc_s_frequency, 435 .vidioc_s_frequency = vidioc_s_frequency,
439#endif 436#endif
440#ifdef CONFIG_VIDEO_ADV_DEBUG 437#ifdef CONFIG_VIDEO_ADV_DEBUG
441 .vidioc_g_register = vidioc_g_register, 438 .vidioc_g_register = vidioc_g_register,
442 .vidioc_s_register = vidioc_s_register, 439 .vidioc_s_register = vidioc_s_register,
443#endif 440#endif
444}; 441};
445 442
446struct video_device cx25821_video_template4 = { 443struct video_device cx25821_video_template4 = {
447 .name = "cx25821-video", 444 .name = "cx25821-video",
448 .fops = &video_fops, 445 .fops = &video_fops,
449 .minor = -1, 446 .minor = -1,
450 .ioctl_ops = &video_ioctl_ops, 447 .ioctl_ops = &video_ioctl_ops,
451 .tvnorms = CX25821_NORMS, 448 .tvnorms = CX25821_NORMS,
452 .current_norm = V4L2_STD_NTSC_M, 449 .current_norm = V4L2_STD_NTSC_M,
453}; 450};
454
455
456
diff --git a/drivers/staging/cx25821/cx25821-video5.c b/drivers/staging/cx25821/cx25821-video5.c
index f1b4742586ec..7ef0b971f5cf 100644
--- a/drivers/staging/cx25821/cx25821-video5.c
+++ b/drivers/staging/cx25821/cx25821-video5.c
@@ -23,357 +23,355 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH05]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH05];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH05]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[SRAM_CH05]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 u32 pix_format; 102 u32 pix_format;
99 103
100 lock_kernel(); 104 lock_kernel();
101 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
102 { 106 h = list_entry(list, struct cx25821_dev, devlist);
103 h = list_entry(list, struct cx25821_dev, devlist); 107
104 108 if (h->video_dev[SRAM_CH05]
105 if (h->video_dev[SRAM_CH05] && h->video_dev[SRAM_CH05]->minor == minor) { 109 && h->video_dev[SRAM_CH05]->minor == minor) {
106 dev = h; 110 dev = h;
107 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
112 }
108 } 113 }
109 }
110 114
111 if (NULL == dev) { 115 if (NULL == dev) {
112 unlock_kernel(); 116 unlock_kernel();
113 return -ENODEV; 117 return -ENODEV;
114 } 118 }
115 119
116 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
117 121
118 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
119 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
120 if (NULL == fh) { 124 if (NULL == fh) {
125 unlock_kernel();
126 return -ENOMEM;
127 }
128 file->private_data = fh;
129 fh->dev = dev;
130 fh->type = type;
131 fh->width = 720;
132
133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
134 fh->height = 576;
135 else
136 fh->height = 480;
137
138 dev->channel_opened = SRAM_CH05;
139 pix_format =
140 (dev->pixel_formats[dev->channel_opened] ==
141 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
142 fh->fmt = format_by_fourcc(pix_format);
143
144 v4l2_prio_open(&dev->prio, &fh->prio);
145
146 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
147 &dev->pci->dev, &dev->slock,
148 V4L2_BUF_TYPE_VIDEO_CAPTURE,
149 V4L2_FIELD_INTERLACED,
150 sizeof(struct cx25821_buffer), fh);
151
152 dprintk(1, "post videobuf_queue_init()\n");
121 unlock_kernel(); 153 unlock_kernel();
122 return -ENOMEM; 154
123 } 155 return 0;
124 file->private_data = fh;
125 fh->dev = dev;
126 fh->type = type;
127 fh->width = 720;
128
129 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
130 fh->height = 576;
131 else
132 fh->height = 480;
133
134 dev->channel_opened = SRAM_CH05;
135 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
136 fh->fmt = format_by_fourcc(pix_format);
137
138 v4l2_prio_open(&dev->prio,&fh->prio);
139
140 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
141 &dev->pci->dev, &dev->slock,
142 V4L2_BUF_TYPE_VIDEO_CAPTURE,
143 V4L2_FIELD_INTERLACED,
144 sizeof(struct cx25821_buffer),
145 fh);
146
147 dprintk(1, "post videobuf_queue_init()\n");
148 unlock_kernel();
149
150 return 0;
151} 156}
152 157
153static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 158static ssize_t video_read(struct file *file, char __user * data, size_t count,
159 loff_t * ppos)
154{ 160{
155 struct cx25821_fh *fh = file->private_data; 161 struct cx25821_fh *fh = file->private_data;
156 162
157 switch (fh->type) 163 switch (fh->type) {
158 {
159 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 164 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
160 if (res_locked(fh->dev, RESOURCE_VIDEO5)) 165 if (res_locked(fh->dev, RESOURCE_VIDEO5))
161 return -EBUSY; 166 return -EBUSY;
162 167
163 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 168 return videobuf_read_one(&fh->vidq, data, count, ppos,
169 file->f_flags & O_NONBLOCK);
164 170
165 default: 171 default:
166 BUG(); 172 BUG();
167 return 0; 173 return 0;
168 } 174 }
169} 175}
170 176
171static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 177static unsigned int video_poll(struct file *file,
178 struct poll_table_struct *wait)
172{ 179{
173 struct cx25821_fh *fh = file->private_data; 180 struct cx25821_fh *fh = file->private_data;
174 struct cx25821_buffer *buf; 181 struct cx25821_buffer *buf;
175 182
176 if (res_check(fh, RESOURCE_VIDEO5)) { 183 if (res_check(fh, RESOURCE_VIDEO5)) {
177 /* streaming capture */ 184 /* streaming capture */
178 if (list_empty(&fh->vidq.stream)) 185 if (list_empty(&fh->vidq.stream))
179 return POLLERR; 186 return POLLERR;
180 buf = list_entry(fh->vidq.stream.next, 187 buf = list_entry(fh->vidq.stream.next,
181 struct cx25821_buffer, vb.stream); 188 struct cx25821_buffer, vb.stream);
182 } else { 189 } else {
183 /* read() capture */ 190 /* read() capture */
184 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 191 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
185 if (NULL == buf) 192 if (NULL == buf)
186 return POLLERR; 193 return POLLERR;
187 }
188
189 poll_wait(file, &buf->vb.done, wait);
190 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
191 {
192 if( buf->vb.state == VIDEOBUF_DONE )
193 {
194 struct cx25821_dev *dev = fh->dev;
195
196 if( dev && dev->use_cif_resolution[SRAM_CH05] )
197 {
198 u8 cam_id = *((char*)buf->vb.baddr+3);
199 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
200 *((char*)buf->vb.baddr+3) = cam_id;
201 }
202 } 194 }
203 195
204 return POLLIN|POLLRDNORM; 196 poll_wait(file, &buf->vb.done, wait);
205 } 197 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
198 if (buf->vb.state == VIDEOBUF_DONE) {
199 struct cx25821_dev *dev = fh->dev;
200
201 if (dev && dev->use_cif_resolution[SRAM_CH05]) {
202 u8 cam_id = *((char *)buf->vb.baddr + 3);
203 memcpy((char *)buf->vb.baddr,
204 (char *)buf->vb.baddr + (fh->width * 2),
205 (fh->width * 2));
206 *((char *)buf->vb.baddr + 3) = cam_id;
207 }
208 }
209
210 return POLLIN | POLLRDNORM;
211 }
206 212
207 return 0; 213 return 0;
208} 214}
209 215
210
211static int video_release(struct file *file) 216static int video_release(struct file *file)
212{ 217{
213 struct cx25821_fh *fh = file->private_data; 218 struct cx25821_fh *fh = file->private_data;
214 struct cx25821_dev *dev = fh->dev; 219 struct cx25821_dev *dev = fh->dev;
215 220
216 //stop the risc engine and fifo 221 //stop the risc engine and fifo
217 cx_write(channel5->dma_ctl, 0); /* FIFO and RISC disable */ 222 cx_write(channel5->dma_ctl, 0); /* FIFO and RISC disable */
218 223
219 /* stop video capture */ 224 /* stop video capture */
220 if (res_check(fh, RESOURCE_VIDEO5)) { 225 if (res_check(fh, RESOURCE_VIDEO5)) {
221 videobuf_queue_cancel(&fh->vidq); 226 videobuf_queue_cancel(&fh->vidq);
222 res_free(dev, fh, RESOURCE_VIDEO5); 227 res_free(dev, fh, RESOURCE_VIDEO5);
223 } 228 }
224 229
225 if (fh->vidq.read_buf) { 230 if (fh->vidq.read_buf) {
226 buffer_release(&fh->vidq, fh->vidq.read_buf); 231 buffer_release(&fh->vidq, fh->vidq.read_buf);
227 kfree(fh->vidq.read_buf); 232 kfree(fh->vidq.read_buf);
228 } 233 }
229 234
230 videobuf_mmap_free(&fh->vidq); 235 videobuf_mmap_free(&fh->vidq);
231 236
232 v4l2_prio_close(&dev->prio,&fh->prio); 237 v4l2_prio_close(&dev->prio, &fh->prio);
233 file->private_data = NULL; 238 file->private_data = NULL;
234 kfree(fh); 239 kfree(fh);
235 240
236 return 0; 241 return 0;
237} 242}
238 243
239
240static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 244static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
241{ 245{
242 struct cx25821_fh *fh = priv; 246 struct cx25821_fh *fh = priv;
243 struct cx25821_dev *dev = fh->dev; 247 struct cx25821_dev *dev = fh->dev;
244 248
245 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 249 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
246 { 250 return -EINVAL;
247 return -EINVAL; 251 }
248 }
249 252
250 if (unlikely(i != fh->type)) 253 if (unlikely(i != fh->type)) {
251 { 254 return -EINVAL;
252 return -EINVAL; 255 }
253 }
254 256
255 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO5)))) 257 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO5)))) {
256 { 258 return -EBUSY;
257 return -EBUSY; 259 }
258 }
259 260
260 return videobuf_streamon(get_queue(fh)); 261 return videobuf_streamon(get_queue(fh));
261} 262}
262 263
263static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 264static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
264{ 265{
265 struct cx25821_fh *fh = priv; 266 struct cx25821_fh *fh = priv;
266 struct cx25821_dev *dev = fh->dev; 267 struct cx25821_dev *dev = fh->dev;
267 int err, res; 268 int err, res;
268 269
269 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 270 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
270 return -EINVAL; 271 return -EINVAL;
271 if (i != fh->type) 272 if (i != fh->type)
272 return -EINVAL; 273 return -EINVAL;
273 274
274 res = get_resource(fh, RESOURCE_VIDEO5); 275 res = get_resource(fh, RESOURCE_VIDEO5);
275 err = videobuf_streamoff(get_queue(fh)); 276 err = videobuf_streamoff(get_queue(fh));
276 if (err < 0) 277 if (err < 0)
277 return err; 278 return err;
278 res_free(dev, fh, res); 279 res_free(dev, fh, res);
279 return 0; 280 return 0;
280} 281}
281 282
282 283static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
283static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 284 struct v4l2_format *f)
284{ 285{
285 struct cx25821_fh *fh = priv; 286 struct cx25821_fh *fh = priv;
286 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 287 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
287 int err; 288 int err;
288 int pix_format = 0; 289 int pix_format = 0;
289 290
290 if (fh) 291 if (fh) {
291 { 292 err = v4l2_prio_check(&dev->prio, &fh->prio);
292 err = v4l2_prio_check(&dev->prio, &fh->prio); 293 if (0 != err)
294 return err;
295 }
296
297 dprintk(2, "%s()\n", __func__);
298 err = vidioc_try_fmt_vid_cap(file, priv, f);
299
293 if (0 != err) 300 if (0 != err)
294 return err; 301 return err;
295 } 302
296 303 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
297 dprintk(2, "%s()\n", __func__); 304 fh->vidq.field = f->fmt.pix.field;
298 err = vidioc_try_fmt_vid_cap(file, priv, f); 305
299 306 // check if width and height is valid based on set standard
300 if (0 != err) 307 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
301 return err; 308 fh->width = f->fmt.pix.width;
302 309 }
303 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 310
304 fh->vidq.field = f->fmt.pix.field; 311 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
305 312 fh->height = f->fmt.pix.height;
306 // check if width and height is valid based on set standard 313 }
307 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 314
308 { 315 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
309 fh->width = f->fmt.pix.width; 316 pix_format = PIXEL_FRMT_411;
310 } 317 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
311 318 pix_format = PIXEL_FRMT_422;
312 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 319 else
313 { 320 return -EINVAL;
314 fh->height = f->fmt.pix.height; 321
315 } 322 cx25821_set_pixel_format(dev, SRAM_CH05, pix_format);
316 323
317 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 324 // check if cif resolution
318 pix_format = PIXEL_FRMT_411; 325 if (fh->width == 320 || fh->width == 352) {
319 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 326 dev->use_cif_resolution[SRAM_CH05] = 1;
320 pix_format = PIXEL_FRMT_422; 327 } else {
321 else 328 dev->use_cif_resolution[SRAM_CH05] = 0;
322 return -EINVAL; 329 }
323 330 dev->cif_width[SRAM_CH05] = fh->width;
324 cx25821_set_pixel_format( dev, SRAM_CH05, pix_format ); 331 medusa_set_resolution(dev, fh->width, SRAM_CH05);
325 332
326 // check if cif resolution 333 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
327 if (fh->width == 320 || fh->width == 352) 334 fh->height, fh->vidq.field);
328 { 335 cx25821_call_all(dev, video, s_fmt, f);
329 dev->use_cif_resolution[SRAM_CH05] = 1; 336
330 }else 337 return 0;
331 {
332 dev->use_cif_resolution[SRAM_CH05] = 0;
333 }
334 dev->cif_width[SRAM_CH05] = fh->width;
335 medusa_set_resolution( dev, fh->width, SRAM_CH05 );
336
337 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
338 cx25821_call_all(dev, video, s_fmt, f);
339
340 return 0;
341} 338}
342 339
343static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 340static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
344{ 341{
345 int ret_val = 0; 342 int ret_val = 0;
346 struct cx25821_fh *fh = priv; 343 struct cx25821_fh *fh = priv;
347 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 344 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
348 345
349 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 346 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
350 347
351 p->sequence = dev->vidq[SRAM_CH05].count; 348 p->sequence = dev->vidq[SRAM_CH05].count;
352 349
353 return ret_val; 350 return ret_val;
354} 351}
355static int vidioc_log_status (struct file *file, void *priv) 352static int vidioc_log_status(struct file *file, void *priv)
356{ 353{
357 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 354 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
358 char name[32 + 2]; 355 char name[32 + 2];
359 356
360 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH05]; 357 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH05];
361 u32 tmp = 0; 358 u32 tmp = 0;
362 359
363 snprintf(name, sizeof(name), "%s/2", dev->name); 360 snprintf(name, sizeof(name), "%s/2", dev->name);
364 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 361 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
365 dev->name); 362 dev->name);
366 cx25821_call_all(dev, core, log_status); 363 cx25821_call_all(dev, core, log_status);
367 364
368 tmp = cx_read(sram_ch->dma_ctl); 365 tmp = cx_read(sram_ch->dma_ctl);
369 printk(KERN_INFO "Video input 5 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 366 printk(KERN_INFO "Video input 5 is %s\n",
370 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 367 (tmp & 0x11) ? "streaming" : "stopped");
368 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
371 dev->name); 369 dev->name);
372 return 0; 370 return 0;
373} 371}
374 372
375static int vidioc_s_ctrl(struct file *file, void *priv, 373static int vidioc_s_ctrl(struct file *file, void *priv,
376 struct v4l2_control *ctl) 374 struct v4l2_control *ctl)
377{ 375{
378 struct cx25821_fh *fh = priv; 376 struct cx25821_fh *fh = priv;
379 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 377 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -390,66 +388,63 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
390 388
391// exported stuff 389// exported stuff
392static const struct v4l2_file_operations video_fops = { 390static const struct v4l2_file_operations video_fops = {
393 .owner = THIS_MODULE, 391 .owner = THIS_MODULE,
394 .open = video_open, 392 .open = video_open,
395 .release = video_release, 393 .release = video_release,
396 .read = video_read, 394 .read = video_read,
397 .poll = video_poll, 395 .poll = video_poll,
398 .mmap = video_mmap, 396 .mmap = video_mmap,
399 .ioctl = video_ioctl2, 397 .ioctl = video_ioctl2,
400}; 398};
401 399
402static const struct v4l2_ioctl_ops video_ioctl_ops = { 400static const struct v4l2_ioctl_ops video_ioctl_ops = {
403 .vidioc_querycap = vidioc_querycap, 401 .vidioc_querycap = vidioc_querycap,
404 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 402 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
405 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 403 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
406 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 404 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
407 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 405 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
408 .vidioc_reqbufs = vidioc_reqbufs, 406 .vidioc_reqbufs = vidioc_reqbufs,
409 .vidioc_querybuf = vidioc_querybuf, 407 .vidioc_querybuf = vidioc_querybuf,
410 .vidioc_qbuf = vidioc_qbuf, 408 .vidioc_qbuf = vidioc_qbuf,
411 .vidioc_dqbuf = vidioc_dqbuf, 409 .vidioc_dqbuf = vidioc_dqbuf,
412#ifdef TUNER_FLAG 410#ifdef TUNER_FLAG
413 .vidioc_s_std = vidioc_s_std, 411 .vidioc_s_std = vidioc_s_std,
414 .vidioc_querystd = vidioc_querystd, 412 .vidioc_querystd = vidioc_querystd,
415#endif 413#endif
416 .vidioc_cropcap = vidioc_cropcap, 414 .vidioc_cropcap = vidioc_cropcap,
417 .vidioc_s_crop = vidioc_s_crop, 415 .vidioc_s_crop = vidioc_s_crop,
418 .vidioc_g_crop = vidioc_g_crop, 416 .vidioc_g_crop = vidioc_g_crop,
419 .vidioc_enum_input = vidioc_enum_input, 417 .vidioc_enum_input = vidioc_enum_input,
420 .vidioc_g_input = vidioc_g_input, 418 .vidioc_g_input = vidioc_g_input,
421 .vidioc_s_input = vidioc_s_input, 419 .vidioc_s_input = vidioc_s_input,
422 .vidioc_g_ctrl = vidioc_g_ctrl, 420 .vidioc_g_ctrl = vidioc_g_ctrl,
423 .vidioc_s_ctrl = vidioc_s_ctrl, 421 .vidioc_s_ctrl = vidioc_s_ctrl,
424 .vidioc_queryctrl = vidioc_queryctrl, 422 .vidioc_queryctrl = vidioc_queryctrl,
425 .vidioc_streamon = vidioc_streamon, 423 .vidioc_streamon = vidioc_streamon,
426 .vidioc_streamoff = vidioc_streamoff, 424 .vidioc_streamoff = vidioc_streamoff,
427 .vidioc_log_status = vidioc_log_status, 425 .vidioc_log_status = vidioc_log_status,
428 .vidioc_g_priority = vidioc_g_priority, 426 .vidioc_g_priority = vidioc_g_priority,
429 .vidioc_s_priority = vidioc_s_priority, 427 .vidioc_s_priority = vidioc_s_priority,
430#ifdef CONFIG_VIDEO_V4L1_COMPAT 428#ifdef CONFIG_VIDEO_V4L1_COMPAT
431 .vidiocgmbuf = vidiocgmbuf, 429 .vidiocgmbuf = vidiocgmbuf,
432#endif 430#endif
433#ifdef TUNER_FLAG 431#ifdef TUNER_FLAG
434 .vidioc_g_tuner = vidioc_g_tuner, 432 .vidioc_g_tuner = vidioc_g_tuner,
435 .vidioc_s_tuner = vidioc_s_tuner, 433 .vidioc_s_tuner = vidioc_s_tuner,
436 .vidioc_g_frequency = vidioc_g_frequency, 434 .vidioc_g_frequency = vidioc_g_frequency,
437 .vidioc_s_frequency = vidioc_s_frequency, 435 .vidioc_s_frequency = vidioc_s_frequency,
438#endif 436#endif
439#ifdef CONFIG_VIDEO_ADV_DEBUG 437#ifdef CONFIG_VIDEO_ADV_DEBUG
440 .vidioc_g_register = vidioc_g_register, 438 .vidioc_g_register = vidioc_g_register,
441 .vidioc_s_register = vidioc_s_register, 439 .vidioc_s_register = vidioc_s_register,
442#endif 440#endif
443}; 441};
444 442
445struct video_device cx25821_video_template5 = { 443struct video_device cx25821_video_template5 = {
446 .name = "cx25821-video", 444 .name = "cx25821-video",
447 .fops = &video_fops, 445 .fops = &video_fops,
448 .minor = -1, 446 .minor = -1,
449 .ioctl_ops = &video_ioctl_ops, 447 .ioctl_ops = &video_ioctl_ops,
450 .tvnorms = CX25821_NORMS, 448 .tvnorms = CX25821_NORMS,
451 .current_norm = V4L2_STD_NTSC_M, 449 .current_norm = V4L2_STD_NTSC_M,
452}; 450};
453
454
455
diff --git a/drivers/staging/cx25821/cx25821-video6.c b/drivers/staging/cx25821/cx25821-video6.c
index 1c0319c7ade9..3c41b49e2ea9 100644
--- a/drivers/staging/cx25821/cx25821-video6.c
+++ b/drivers/staging/cx25821/cx25821-video6.c
@@ -23,357 +23,355 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH06]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH06];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH06]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[SRAM_CH06]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 u32 pix_format; 102 u32 pix_format;
99 103
100 lock_kernel(); 104 lock_kernel();
101 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
102 { 106 h = list_entry(list, struct cx25821_dev, devlist);
103 h = list_entry(list, struct cx25821_dev, devlist); 107
104 108 if (h->video_dev[SRAM_CH06]
105 if (h->video_dev[SRAM_CH06] && h->video_dev[SRAM_CH06]->minor == minor) { 109 && h->video_dev[SRAM_CH06]->minor == minor) {
106 dev = h; 110 dev = h;
107 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
112 }
108 } 113 }
109 }
110 114
111 if (NULL == dev) { 115 if (NULL == dev) {
112 unlock_kernel(); 116 unlock_kernel();
113 return -ENODEV; 117 return -ENODEV;
114 } 118 }
115 119
116 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 120 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
117 121
118 /* allocate + initialize per filehandle data */ 122 /* allocate + initialize per filehandle data */
119 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 123 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
120 if (NULL == fh) { 124 if (NULL == fh) {
125 unlock_kernel();
126 return -ENOMEM;
127 }
128 file->private_data = fh;
129 fh->dev = dev;
130 fh->type = type;
131 fh->width = 720;
132
133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
134 fh->height = 576;
135 else
136 fh->height = 480;
137
138 dev->channel_opened = SRAM_CH06;
139 pix_format =
140 (dev->pixel_formats[dev->channel_opened] ==
141 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
142 fh->fmt = format_by_fourcc(pix_format);
143
144 v4l2_prio_open(&dev->prio, &fh->prio);
145
146 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
147 &dev->pci->dev, &dev->slock,
148 V4L2_BUF_TYPE_VIDEO_CAPTURE,
149 V4L2_FIELD_INTERLACED,
150 sizeof(struct cx25821_buffer), fh);
151
152 dprintk(1, "post videobuf_queue_init()\n");
121 unlock_kernel(); 153 unlock_kernel();
122 return -ENOMEM; 154
123 } 155 return 0;
124 file->private_data = fh;
125 fh->dev = dev;
126 fh->type = type;
127 fh->width = 720;
128
129 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
130 fh->height = 576;
131 else
132 fh->height = 480;
133
134 dev->channel_opened = SRAM_CH06;
135 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
136 fh->fmt = format_by_fourcc(pix_format);
137
138 v4l2_prio_open(&dev->prio,&fh->prio);
139
140 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
141 &dev->pci->dev, &dev->slock,
142 V4L2_BUF_TYPE_VIDEO_CAPTURE,
143 V4L2_FIELD_INTERLACED,
144 sizeof(struct cx25821_buffer),
145 fh);
146
147 dprintk(1, "post videobuf_queue_init()\n");
148 unlock_kernel();
149
150 return 0;
151} 156}
152 157
153static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 158static ssize_t video_read(struct file *file, char __user * data, size_t count,
159 loff_t * ppos)
154{ 160{
155 struct cx25821_fh *fh = file->private_data; 161 struct cx25821_fh *fh = file->private_data;
156 162
157 switch (fh->type) 163 switch (fh->type) {
158 {
159 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 164 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
160 if (res_locked(fh->dev, RESOURCE_VIDEO6)) 165 if (res_locked(fh->dev, RESOURCE_VIDEO6))
161 return -EBUSY; 166 return -EBUSY;
162 167
163 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 168 return videobuf_read_one(&fh->vidq, data, count, ppos,
169 file->f_flags & O_NONBLOCK);
164 170
165 default: 171 default:
166 BUG(); 172 BUG();
167 return 0; 173 return 0;
168 } 174 }
169} 175}
170 176
171static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 177static unsigned int video_poll(struct file *file,
178 struct poll_table_struct *wait)
172{ 179{
173 struct cx25821_fh *fh = file->private_data; 180 struct cx25821_fh *fh = file->private_data;
174 struct cx25821_buffer *buf; 181 struct cx25821_buffer *buf;
175 182
176 if (res_check(fh, RESOURCE_VIDEO6)) { 183 if (res_check(fh, RESOURCE_VIDEO6)) {
177 /* streaming capture */ 184 /* streaming capture */
178 if (list_empty(&fh->vidq.stream)) 185 if (list_empty(&fh->vidq.stream))
179 return POLLERR; 186 return POLLERR;
180 buf = list_entry(fh->vidq.stream.next, 187 buf = list_entry(fh->vidq.stream.next,
181 struct cx25821_buffer, vb.stream); 188 struct cx25821_buffer, vb.stream);
182 } else { 189 } else {
183 /* read() capture */ 190 /* read() capture */
184 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 191 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
185 if (NULL == buf) 192 if (NULL == buf)
186 return POLLERR; 193 return POLLERR;
187 }
188
189 poll_wait(file, &buf->vb.done, wait);
190 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
191 {
192 if( buf->vb.state == VIDEOBUF_DONE )
193 {
194 struct cx25821_dev *dev = fh->dev;
195
196 if( dev && dev->use_cif_resolution[SRAM_CH06] )
197 {
198 u8 cam_id = *((char*)buf->vb.baddr+3);
199 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
200 *((char*)buf->vb.baddr+3) = cam_id;
201 }
202 } 194 }
203 195
204 return POLLIN|POLLRDNORM; 196 poll_wait(file, &buf->vb.done, wait);
205 } 197 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
198 if (buf->vb.state == VIDEOBUF_DONE) {
199 struct cx25821_dev *dev = fh->dev;
200
201 if (dev && dev->use_cif_resolution[SRAM_CH06]) {
202 u8 cam_id = *((char *)buf->vb.baddr + 3);
203 memcpy((char *)buf->vb.baddr,
204 (char *)buf->vb.baddr + (fh->width * 2),
205 (fh->width * 2));
206 *((char *)buf->vb.baddr + 3) = cam_id;
207 }
208 }
209
210 return POLLIN | POLLRDNORM;
211 }
206 212
207 return 0; 213 return 0;
208} 214}
209 215
210
211static int video_release(struct file *file) 216static int video_release(struct file *file)
212{ 217{
213 struct cx25821_fh *fh = file->private_data; 218 struct cx25821_fh *fh = file->private_data;
214 struct cx25821_dev *dev = fh->dev; 219 struct cx25821_dev *dev = fh->dev;
215 220
216 //stop the risc engine and fifo 221 //stop the risc engine and fifo
217 cx_write(channel6->dma_ctl, 0); /* FIFO and RISC disable */ 222 cx_write(channel6->dma_ctl, 0); /* FIFO and RISC disable */
218 223
219 /* stop video capture */ 224 /* stop video capture */
220 if (res_check(fh, RESOURCE_VIDEO6)) { 225 if (res_check(fh, RESOURCE_VIDEO6)) {
221 videobuf_queue_cancel(&fh->vidq); 226 videobuf_queue_cancel(&fh->vidq);
222 res_free(dev, fh, RESOURCE_VIDEO6); 227 res_free(dev, fh, RESOURCE_VIDEO6);
223 } 228 }
224 if (fh->vidq.read_buf) { 229 if (fh->vidq.read_buf) {
225 buffer_release(&fh->vidq, fh->vidq.read_buf); 230 buffer_release(&fh->vidq, fh->vidq.read_buf);
226 kfree(fh->vidq.read_buf); 231 kfree(fh->vidq.read_buf);
227 } 232 }
228 233
229 videobuf_mmap_free(&fh->vidq); 234 videobuf_mmap_free(&fh->vidq);
230 235
231 v4l2_prio_close(&dev->prio,&fh->prio); 236 v4l2_prio_close(&dev->prio, &fh->prio);
232 file->private_data = NULL; 237 file->private_data = NULL;
233 kfree(fh); 238 kfree(fh);
234 239
235 return 0; 240 return 0;
236} 241}
237 242
238
239static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 243static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
240{ 244{
241 struct cx25821_fh *fh = priv; 245 struct cx25821_fh *fh = priv;
242 struct cx25821_dev *dev = fh->dev; 246 struct cx25821_dev *dev = fh->dev;
243 247
244 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 248 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
245 { 249 return -EINVAL;
246 return -EINVAL; 250 }
247 }
248 251
249 if (unlikely(i != fh->type)) 252 if (unlikely(i != fh->type)) {
250 { 253 return -EINVAL;
251 return -EINVAL; 254 }
252 }
253 255
254 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO6)))) 256 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO6)))) {
255 { 257 return -EBUSY;
256 return -EBUSY; 258 }
257 }
258 259
259 return videobuf_streamon(get_queue(fh)); 260 return videobuf_streamon(get_queue(fh));
260} 261}
261 262
262static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 263static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
263{ 264{
264 struct cx25821_fh *fh = priv; 265 struct cx25821_fh *fh = priv;
265 struct cx25821_dev *dev = fh->dev; 266 struct cx25821_dev *dev = fh->dev;
266 int err, res; 267 int err, res;
267 268
268 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 269 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
269 return -EINVAL; 270 return -EINVAL;
270 if (i != fh->type) 271 if (i != fh->type)
271 return -EINVAL; 272 return -EINVAL;
272 273
273 res = get_resource(fh, RESOURCE_VIDEO6); 274 res = get_resource(fh, RESOURCE_VIDEO6);
274 err = videobuf_streamoff(get_queue(fh)); 275 err = videobuf_streamoff(get_queue(fh));
275 if (err < 0) 276 if (err < 0)
276 return err; 277 return err;
277 res_free(dev, fh, res); 278 res_free(dev, fh, res);
278 return 0; 279 return 0;
279} 280}
280 281
281 282static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
282static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 283 struct v4l2_format *f)
283{ 284{
284 struct cx25821_fh *fh = priv; 285 struct cx25821_fh *fh = priv;
285 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 286 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
286 int err; 287 int err;
287 int pix_format = 0; 288 int pix_format = 0;
288 289
289 if (fh) 290 if (fh) {
290 { 291 err = v4l2_prio_check(&dev->prio, &fh->prio);
291 err = v4l2_prio_check(&dev->prio, &fh->prio); 292 if (0 != err)
293 return err;
294 }
295
296 dprintk(2, "%s()\n", __func__);
297 err = vidioc_try_fmt_vid_cap(file, priv, f);
298
292 if (0 != err) 299 if (0 != err)
293 return err; 300 return err;
294 } 301
295 302 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
296 dprintk(2, "%s()\n", __func__); 303 fh->vidq.field = f->fmt.pix.field;
297 err = vidioc_try_fmt_vid_cap(file, priv, f); 304
298 305 // check if width and height is valid based on set standard
299 if (0 != err) 306 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
300 return err; 307 fh->width = f->fmt.pix.width;
301 308 }
302 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 309
303 fh->vidq.field = f->fmt.pix.field; 310 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
304 311 fh->height = f->fmt.pix.height;
305 // check if width and height is valid based on set standard 312 }
306 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 313
307 { 314 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
308 fh->width = f->fmt.pix.width; 315 pix_format = PIXEL_FRMT_411;
309 } 316 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
310 317 pix_format = PIXEL_FRMT_422;
311 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 318 else
312 { 319 return -EINVAL;
313 fh->height = f->fmt.pix.height; 320
314 } 321 cx25821_set_pixel_format(dev, SRAM_CH06, pix_format);
315 322
316 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 323 // check if cif resolution
317 pix_format = PIXEL_FRMT_411; 324 if (fh->width == 320 || fh->width == 352) {
318 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 325 dev->use_cif_resolution[SRAM_CH06] = 1;
319 pix_format = PIXEL_FRMT_422; 326 } else {
320 else 327 dev->use_cif_resolution[SRAM_CH06] = 0;
321 return -EINVAL; 328 }
322 329 dev->cif_width[SRAM_CH06] = fh->width;
323 cx25821_set_pixel_format( dev, SRAM_CH06, pix_format ); 330 medusa_set_resolution(dev, fh->width, SRAM_CH06);
324 331
325 // check if cif resolution 332 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
326 if (fh->width == 320 || fh->width == 352) 333 fh->height, fh->vidq.field);
327 { 334 cx25821_call_all(dev, video, s_fmt, f);
328 dev->use_cif_resolution[SRAM_CH06] = 1; 335
329 }else 336 return 0;
330 {
331 dev->use_cif_resolution[SRAM_CH06] = 0;
332 }
333 dev->cif_width[SRAM_CH06] = fh->width;
334 medusa_set_resolution( dev, fh->width, SRAM_CH06 );
335
336 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
337 cx25821_call_all(dev, video, s_fmt, f);
338
339 return 0;
340} 337}
341 338
342static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 339static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
343{ 340{
344 int ret_val = 0; 341 int ret_val = 0;
345 struct cx25821_fh *fh = priv; 342 struct cx25821_fh *fh = priv;
346 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 343 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
347 344
348 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 345 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
349 346
350 p->sequence = dev->vidq[SRAM_CH06].count; 347 p->sequence = dev->vidq[SRAM_CH06].count;
351 348
352 return ret_val; 349 return ret_val;
353} 350}
354 351
355static int vidioc_log_status (struct file *file, void *priv) 352static int vidioc_log_status(struct file *file, void *priv)
356{ 353{
357 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 354 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
358 char name[32 + 2]; 355 char name[32 + 2];
359 356
360 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH06]; 357 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH06];
361 u32 tmp = 0; 358 u32 tmp = 0;
362 359
363 snprintf(name, sizeof(name), "%s/2", dev->name); 360 snprintf(name, sizeof(name), "%s/2", dev->name);
364 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 361 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
365 dev->name); 362 dev->name);
366 cx25821_call_all(dev, core, log_status); 363 cx25821_call_all(dev, core, log_status);
367 364
368 tmp = cx_read(sram_ch->dma_ctl); 365 tmp = cx_read(sram_ch->dma_ctl);
369 printk(KERN_INFO "Video input 6 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 366 printk(KERN_INFO "Video input 6 is %s\n",
370 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 367 (tmp & 0x11) ? "streaming" : "stopped");
368 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
371 dev->name); 369 dev->name);
372 return 0; 370 return 0;
373} 371}
374 372
375static int vidioc_s_ctrl(struct file *file, void *priv, 373static int vidioc_s_ctrl(struct file *file, void *priv,
376 struct v4l2_control *ctl) 374 struct v4l2_control *ctl)
377{ 375{
378 struct cx25821_fh *fh = priv; 376 struct cx25821_fh *fh = priv;
379 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 377 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -390,66 +388,63 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
390 388
391// exported stuff 389// exported stuff
392static const struct v4l2_file_operations video_fops = { 390static const struct v4l2_file_operations video_fops = {
393 .owner = THIS_MODULE, 391 .owner = THIS_MODULE,
394 .open = video_open, 392 .open = video_open,
395 .release = video_release, 393 .release = video_release,
396 .read = video_read, 394 .read = video_read,
397 .poll = video_poll, 395 .poll = video_poll,
398 .mmap = video_mmap, 396 .mmap = video_mmap,
399 .ioctl = video_ioctl2, 397 .ioctl = video_ioctl2,
400}; 398};
401 399
402static const struct v4l2_ioctl_ops video_ioctl_ops = { 400static const struct v4l2_ioctl_ops video_ioctl_ops = {
403 .vidioc_querycap = vidioc_querycap, 401 .vidioc_querycap = vidioc_querycap,
404 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 402 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
405 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 403 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
406 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 404 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
407 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 405 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
408 .vidioc_reqbufs = vidioc_reqbufs, 406 .vidioc_reqbufs = vidioc_reqbufs,
409 .vidioc_querybuf = vidioc_querybuf, 407 .vidioc_querybuf = vidioc_querybuf,
410 .vidioc_qbuf = vidioc_qbuf, 408 .vidioc_qbuf = vidioc_qbuf,
411 .vidioc_dqbuf = vidioc_dqbuf, 409 .vidioc_dqbuf = vidioc_dqbuf,
412#ifdef TUNER_FLAG 410#ifdef TUNER_FLAG
413 .vidioc_s_std = vidioc_s_std, 411 .vidioc_s_std = vidioc_s_std,
414 .vidioc_querystd = vidioc_querystd, 412 .vidioc_querystd = vidioc_querystd,
415#endif 413#endif
416 .vidioc_cropcap = vidioc_cropcap, 414 .vidioc_cropcap = vidioc_cropcap,
417 .vidioc_s_crop = vidioc_s_crop, 415 .vidioc_s_crop = vidioc_s_crop,
418 .vidioc_g_crop = vidioc_g_crop, 416 .vidioc_g_crop = vidioc_g_crop,
419 .vidioc_enum_input = vidioc_enum_input, 417 .vidioc_enum_input = vidioc_enum_input,
420 .vidioc_g_input = vidioc_g_input, 418 .vidioc_g_input = vidioc_g_input,
421 .vidioc_s_input = vidioc_s_input, 419 .vidioc_s_input = vidioc_s_input,
422 .vidioc_g_ctrl = vidioc_g_ctrl, 420 .vidioc_g_ctrl = vidioc_g_ctrl,
423 .vidioc_s_ctrl = vidioc_s_ctrl, 421 .vidioc_s_ctrl = vidioc_s_ctrl,
424 .vidioc_queryctrl = vidioc_queryctrl, 422 .vidioc_queryctrl = vidioc_queryctrl,
425 .vidioc_streamon = vidioc_streamon, 423 .vidioc_streamon = vidioc_streamon,
426 .vidioc_streamoff = vidioc_streamoff, 424 .vidioc_streamoff = vidioc_streamoff,
427 .vidioc_log_status = vidioc_log_status, 425 .vidioc_log_status = vidioc_log_status,
428 .vidioc_g_priority = vidioc_g_priority, 426 .vidioc_g_priority = vidioc_g_priority,
429 .vidioc_s_priority = vidioc_s_priority, 427 .vidioc_s_priority = vidioc_s_priority,
430#ifdef CONFIG_VIDEO_V4L1_COMPAT 428#ifdef CONFIG_VIDEO_V4L1_COMPAT
431 .vidiocgmbuf = vidiocgmbuf, 429 .vidiocgmbuf = vidiocgmbuf,
432#endif 430#endif
433#ifdef TUNER_FLAG 431#ifdef TUNER_FLAG
434 .vidioc_g_tuner = vidioc_g_tuner, 432 .vidioc_g_tuner = vidioc_g_tuner,
435 .vidioc_s_tuner = vidioc_s_tuner, 433 .vidioc_s_tuner = vidioc_s_tuner,
436 .vidioc_g_frequency = vidioc_g_frequency, 434 .vidioc_g_frequency = vidioc_g_frequency,
437 .vidioc_s_frequency = vidioc_s_frequency, 435 .vidioc_s_frequency = vidioc_s_frequency,
438#endif 436#endif
439#ifdef CONFIG_VIDEO_ADV_DEBUG 437#ifdef CONFIG_VIDEO_ADV_DEBUG
440 .vidioc_g_register = vidioc_g_register, 438 .vidioc_g_register = vidioc_g_register,
441 .vidioc_s_register = vidioc_s_register, 439 .vidioc_s_register = vidioc_s_register,
442#endif 440#endif
443}; 441};
444 442
445struct video_device cx25821_video_template6 = { 443struct video_device cx25821_video_template6 = {
446 .name = "cx25821-video", 444 .name = "cx25821-video",
447 .fops = &video_fops, 445 .fops = &video_fops,
448 .minor = -1, 446 .minor = -1,
449 .ioctl_ops = &video_ioctl_ops, 447 .ioctl_ops = &video_ioctl_ops,
450 .tvnorms = CX25821_NORMS, 448 .tvnorms = CX25821_NORMS,
451 .current_norm = V4L2_STD_NTSC_M, 449 .current_norm = V4L2_STD_NTSC_M,
452}; 450};
453
454
455
diff --git a/drivers/staging/cx25821/cx25821-video7.c b/drivers/staging/cx25821/cx25821-video7.c
index 71da80992b6d..625c9b78a9cf 100644
--- a/drivers/staging/cx25821/cx25821-video7.c
+++ b/drivers/staging/cx25821/cx25821-video7.c
@@ -23,356 +23,354 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH07]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH07];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
39 39
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
41 if (!list_empty(&q->queued)) { 41 if (!list_empty(&q->queued)) {
42 list_add_tail(&buf->vb.queue, &q->queued); 42 list_add_tail(&buf->vb.queue, &q->queued);
43 buf->vb.state = VIDEOBUF_QUEUED; 43 buf->vb.state = VIDEOBUF_QUEUED;
44 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
45 45 buf->vb.i);
46 } else if (list_empty(&q->active)) { 46
47 list_add_tail(&buf->vb.queue, &q->active); 47 } else if (list_empty(&q->active)) {
48 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH07]); 48 list_add_tail(&buf->vb.queue, &q->active);
49 buf->vb.state = VIDEOBUF_ACTIVE; 49 cx25821_start_video_dma(dev, q, buf,
50 buf->count = q->count++; 50 &dev->sram_channels[SRAM_CH07]);
51 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 buf->vb.state = VIDEOBUF_ACTIVE;
52 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->count = q->count++;
53 buf, buf->vb. i, buf->count, q->count); 53 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
54 } else { 54 dprintk(2,
55 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
56 if (prev->vb.width == buf->vb.width && 56 buf, buf->vb.i, buf->count, q->count);
57 prev->vb.height == buf->vb.height &&
58 prev->fmt == buf->fmt) {
59 list_add_tail(&buf->vb.queue, &q->active);
60 buf->vb.state = VIDEOBUF_ACTIVE;
61 buf->count = q->count++;
62 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
63
64 /* 64 bit bits 63-32 */
65 prev->risc.jmp[2] = cpu_to_le32(0);
66 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
67
68 } else { 57 } else {
69 list_add_tail(&buf->vb.queue, &q->queued); 58 prev =
70 buf->vb.state = VIDEOBUF_QUEUED; 59 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
71 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 60 if (prev->vb.width == buf->vb.width
61 && prev->vb.height == buf->vb.height
62 && prev->fmt == buf->fmt) {
63 list_add_tail(&buf->vb.queue, &q->active);
64 buf->vb.state = VIDEOBUF_ACTIVE;
65 buf->count = q->count++;
66 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
67
68 /* 64 bit bits 63-32 */
69 prev->risc.jmp[2] = cpu_to_le32(0);
70 dprintk(2,
71 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
72 buf, buf->vb.i, buf->count);
73
74 } else {
75 list_add_tail(&buf->vb.queue, &q->queued);
76 buf->vb.state = VIDEOBUF_QUEUED;
77 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
78 buf->vb.i);
79 }
72 } 80 }
73 }
74 81
75 if (list_empty(&q->active)) 82 if (list_empty(&q->active)) {
76 { 83 dprintk(2, "active queue empty!\n");
77 dprintk(2, "active queue empty!\n"); 84 }
78 }
79} 85}
80 86
81
82static struct videobuf_queue_ops cx25821_video_qops = { 87static struct videobuf_queue_ops cx25821_video_qops = {
83 .buf_setup = buffer_setup, 88 .buf_setup = buffer_setup,
84 .buf_prepare = buffer_prepare, 89 .buf_prepare = buffer_prepare,
85 .buf_queue = buffer_queue, 90 .buf_queue = buffer_queue,
86 .buf_release = buffer_release, 91 .buf_release = buffer_release,
87}; 92};
88 93
89
90static int video_open(struct file *file) 94static int video_open(struct file *file)
91{ 95{
92 int minor = video_devdata(file)->minor; 96 int minor = video_devdata(file)->minor;
93 struct cx25821_dev *h, *dev = NULL; 97 struct cx25821_dev *h, *dev = NULL;
94 struct cx25821_fh *fh; 98 struct cx25821_fh *fh;
95 struct list_head *list; 99 struct list_head *list;
96 enum v4l2_buf_type type = 0; 100 enum v4l2_buf_type type = 0;
97 u32 pix_format; 101 u32 pix_format;
98 102
99 lock_kernel(); 103 lock_kernel();
100 list_for_each(list, &cx25821_devlist) 104 list_for_each(list, &cx25821_devlist) {
101 { 105 h = list_entry(list, struct cx25821_dev, devlist);
102 h = list_entry(list, struct cx25821_dev, devlist); 106
103 107 if (h->video_dev[SRAM_CH07]
104 if (h->video_dev[SRAM_CH07] && h->video_dev[SRAM_CH07]->minor == minor) { 108 && h->video_dev[SRAM_CH07]->minor == minor) {
105 dev = h; 109 dev = h;
106 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 110 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
111 }
107 } 112 }
108 }
109 113
110 if (NULL == dev) { 114 if (NULL == dev) {
111 unlock_kernel(); 115 unlock_kernel();
112 return -ENODEV; 116 return -ENODEV;
113 } 117 }
114 118
115 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 119 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
116 120
117 /* allocate + initialize per filehandle data */ 121 /* allocate + initialize per filehandle data */
118 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 122 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
119 if (NULL == fh) { 123 if (NULL == fh) {
124 unlock_kernel();
125 return -ENOMEM;
126 }
127 file->private_data = fh;
128 fh->dev = dev;
129 fh->type = type;
130 fh->width = 720;
131
132 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
133 fh->height = 576;
134 else
135 fh->height = 480;
136
137 dev->channel_opened = SRAM_CH07;
138 pix_format =
139 (dev->pixel_formats[dev->channel_opened] ==
140 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
141 fh->fmt = format_by_fourcc(pix_format);
142
143 v4l2_prio_open(&dev->prio, &fh->prio);
144
145 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
146 &dev->pci->dev, &dev->slock,
147 V4L2_BUF_TYPE_VIDEO_CAPTURE,
148 V4L2_FIELD_INTERLACED,
149 sizeof(struct cx25821_buffer), fh);
150
151 dprintk(1, "post videobuf_queue_init()\n");
120 unlock_kernel(); 152 unlock_kernel();
121 return -ENOMEM; 153
122 } 154 return 0;
123 file->private_data = fh;
124 fh->dev = dev;
125 fh->type = type;
126 fh->width = 720;
127
128 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
129 fh->height = 576;
130 else
131 fh->height = 480;
132
133 dev->channel_opened = SRAM_CH07;
134 pix_format = (dev->pixel_formats[dev->channel_opened] == PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
135 fh->fmt = format_by_fourcc(pix_format);
136
137 v4l2_prio_open(&dev->prio,&fh->prio);
138
139 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
140 &dev->pci->dev, &dev->slock,
141 V4L2_BUF_TYPE_VIDEO_CAPTURE,
142 V4L2_FIELD_INTERLACED,
143 sizeof(struct cx25821_buffer),
144 fh);
145
146 dprintk(1, "post videobuf_queue_init()\n");
147 unlock_kernel();
148
149 return 0;
150} 155}
151 156
152static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 157static ssize_t video_read(struct file *file, char __user * data, size_t count,
158 loff_t * ppos)
153{ 159{
154 struct cx25821_fh *fh = file->private_data; 160 struct cx25821_fh *fh = file->private_data;
155 161
156 switch (fh->type) 162 switch (fh->type) {
157 {
158 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 163 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
159 if (res_locked(fh->dev, RESOURCE_VIDEO7)) 164 if (res_locked(fh->dev, RESOURCE_VIDEO7))
160 return -EBUSY; 165 return -EBUSY;
161 166
162 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 167 return videobuf_read_one(&fh->vidq, data, count, ppos,
168 file->f_flags & O_NONBLOCK);
163 169
164 default: 170 default:
165 BUG(); 171 BUG();
166 return 0; 172 return 0;
167 } 173 }
168} 174}
169 175
170static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 176static unsigned int video_poll(struct file *file,
177 struct poll_table_struct *wait)
171{ 178{
172 struct cx25821_fh *fh = file->private_data; 179 struct cx25821_fh *fh = file->private_data;
173 struct cx25821_buffer *buf; 180 struct cx25821_buffer *buf;
174 181
175 if (res_check(fh, RESOURCE_VIDEO7)) { 182 if (res_check(fh, RESOURCE_VIDEO7)) {
176 /* streaming capture */ 183 /* streaming capture */
177 if (list_empty(&fh->vidq.stream)) 184 if (list_empty(&fh->vidq.stream))
178 return POLLERR; 185 return POLLERR;
179 buf = list_entry(fh->vidq.stream.next, 186 buf = list_entry(fh->vidq.stream.next,
180 struct cx25821_buffer, vb.stream); 187 struct cx25821_buffer, vb.stream);
181 } else { 188 } else {
182 /* read() capture */ 189 /* read() capture */
183 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 190 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
184 if (NULL == buf) 191 if (NULL == buf)
185 return POLLERR; 192 return POLLERR;
186 }
187
188 poll_wait(file, &buf->vb.done, wait);
189 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
190 {
191 if( buf->vb.state == VIDEOBUF_DONE )
192 {
193 struct cx25821_dev *dev = fh->dev;
194
195 if( dev && dev->use_cif_resolution[SRAM_CH07] )
196 {
197 u8 cam_id = *((char*)buf->vb.baddr+3);
198 memcpy((char*)buf->vb.baddr, (char*)buf->vb.baddr + (fh->width * 2), (fh->width * 2));
199 *((char*)buf->vb.baddr+3) = cam_id;
200 }
201 } 193 }
202 194
203 return POLLIN|POLLRDNORM; 195 poll_wait(file, &buf->vb.done, wait);
204 } 196 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
197 if (buf->vb.state == VIDEOBUF_DONE) {
198 struct cx25821_dev *dev = fh->dev;
199
200 if (dev && dev->use_cif_resolution[SRAM_CH07]) {
201 u8 cam_id = *((char *)buf->vb.baddr + 3);
202 memcpy((char *)buf->vb.baddr,
203 (char *)buf->vb.baddr + (fh->width * 2),
204 (fh->width * 2));
205 *((char *)buf->vb.baddr + 3) = cam_id;
206 }
207 }
208
209 return POLLIN | POLLRDNORM;
210 }
205 211
206 return 0; 212 return 0;
207} 213}
208 214
209
210static int video_release(struct file *file) 215static int video_release(struct file *file)
211{ 216{
212 struct cx25821_fh *fh = file->private_data; 217 struct cx25821_fh *fh = file->private_data;
213 struct cx25821_dev *dev = fh->dev; 218 struct cx25821_dev *dev = fh->dev;
214 219
215 //stop the risc engine and fifo 220 //stop the risc engine and fifo
216 cx_write(channel7->dma_ctl, 0); /* FIFO and RISC disable */ 221 cx_write(channel7->dma_ctl, 0); /* FIFO and RISC disable */
217 222
218 /* stop video capture */ 223 /* stop video capture */
219 if (res_check(fh, RESOURCE_VIDEO7)) { 224 if (res_check(fh, RESOURCE_VIDEO7)) {
220 videobuf_queue_cancel(&fh->vidq); 225 videobuf_queue_cancel(&fh->vidq);
221 res_free(dev, fh, RESOURCE_VIDEO7); 226 res_free(dev, fh, RESOURCE_VIDEO7);
222 } 227 }
223 228
224 if (fh->vidq.read_buf) { 229 if (fh->vidq.read_buf) {
225 buffer_release(&fh->vidq, fh->vidq.read_buf); 230 buffer_release(&fh->vidq, fh->vidq.read_buf);
226 kfree(fh->vidq.read_buf); 231 kfree(fh->vidq.read_buf);
227 } 232 }
228 233
229 videobuf_mmap_free(&fh->vidq); 234 videobuf_mmap_free(&fh->vidq);
230 235
231 v4l2_prio_close(&dev->prio,&fh->prio); 236 v4l2_prio_close(&dev->prio, &fh->prio);
232 file->private_data = NULL; 237 file->private_data = NULL;
233 kfree(fh); 238 kfree(fh);
234 239
235 return 0; 240 return 0;
236} 241}
237 242
238
239static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 243static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
240{ 244{
241 struct cx25821_fh *fh = priv; 245 struct cx25821_fh *fh = priv;
242 struct cx25821_dev *dev = fh->dev; 246 struct cx25821_dev *dev = fh->dev;
243 247
244 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 248 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
245 { 249 return -EINVAL;
246 return -EINVAL; 250 }
247 }
248 251
249 if (unlikely(i != fh->type)) 252 if (unlikely(i != fh->type)) {
250 { 253 return -EINVAL;
251 return -EINVAL; 254 }
252 }
253 255
254 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO7)))) 256 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO7)))) {
255 { 257 return -EBUSY;
256 return -EBUSY; 258 }
257 }
258 259
259 return videobuf_streamon(get_queue(fh)); 260 return videobuf_streamon(get_queue(fh));
260} 261}
261 262
262static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 263static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
263{ 264{
264 struct cx25821_fh *fh = priv; 265 struct cx25821_fh *fh = priv;
265 struct cx25821_dev *dev = fh->dev; 266 struct cx25821_dev *dev = fh->dev;
266 int err, res; 267 int err, res;
267 268
268 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 269 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
269 return -EINVAL; 270 return -EINVAL;
270 if (i != fh->type) 271 if (i != fh->type)
271 return -EINVAL; 272 return -EINVAL;
272 273
273 res = get_resource(fh, RESOURCE_VIDEO7); 274 res = get_resource(fh, RESOURCE_VIDEO7);
274 err = videobuf_streamoff(get_queue(fh)); 275 err = videobuf_streamoff(get_queue(fh));
275 if (err < 0) 276 if (err < 0)
276 return err; 277 return err;
277 res_free(dev, fh, res); 278 res_free(dev, fh, res);
278 return 0; 279 return 0;
279} 280}
280 281
281 282static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
282static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 283 struct v4l2_format *f)
283{ 284{
284 struct cx25821_fh *fh = priv; 285 struct cx25821_fh *fh = priv;
285 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 286 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
286 int err; 287 int err;
287 int pix_format = 0; 288 int pix_format = 0;
288 289
289 if (fh) 290 if (fh) {
290 { 291 err = v4l2_prio_check(&dev->prio, &fh->prio);
291 err = v4l2_prio_check(&dev->prio, &fh->prio); 292 if (0 != err)
293 return err;
294 }
295
296 dprintk(2, "%s()\n", __func__);
297 err = vidioc_try_fmt_vid_cap(file, priv, f);
298
292 if (0 != err) 299 if (0 != err)
293 return err; 300 return err;
294 } 301
295 302 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
296 dprintk(2, "%s()\n", __func__); 303 fh->vidq.field = f->fmt.pix.field;
297 err = vidioc_try_fmt_vid_cap(file, priv, f); 304
298 305 // check if width and height is valid based on set standard
299 if (0 != err) 306 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) {
300 return err; 307 fh->width = f->fmt.pix.width;
301 308 }
302 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 309
303 fh->vidq.field = f->fmt.pix.field; 310 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) {
304 311 fh->height = f->fmt.pix.height;
305 // check if width and height is valid based on set standard 312 }
306 if (is_valid_width(f->fmt.pix.width, dev->tvnorm)) 313
307 { 314 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
308 fh->width = f->fmt.pix.width; 315 pix_format = PIXEL_FRMT_411;
309 } 316 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
310 317 pix_format = PIXEL_FRMT_422;
311 if (is_valid_height(f->fmt.pix.height, dev->tvnorm)) 318 else
312 { 319 return -EINVAL;
313 fh->height = f->fmt.pix.height; 320
314 } 321 cx25821_set_pixel_format(dev, SRAM_CH07, pix_format);
315 322
316 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) 323 // check if cif resolution
317 pix_format = PIXEL_FRMT_411; 324 if (fh->width == 320 || fh->width == 352) {
318 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) 325 dev->use_cif_resolution[SRAM_CH07] = 1;
319 pix_format = PIXEL_FRMT_422; 326 } else {
320 else 327 dev->use_cif_resolution[SRAM_CH07] = 0;
321 return -EINVAL; 328 }
322 329 dev->cif_width[SRAM_CH07] = fh->width;
323 cx25821_set_pixel_format( dev, SRAM_CH07, pix_format ); 330 medusa_set_resolution(dev, fh->width, SRAM_CH07);
324 331
325 // check if cif resolution 332 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
326 if (fh->width == 320 || fh->width == 352) 333 fh->height, fh->vidq.field);
327 { 334 cx25821_call_all(dev, video, s_fmt, f);
328 dev->use_cif_resolution[SRAM_CH07] = 1; 335
329 }else 336 return 0;
330 {
331 dev->use_cif_resolution[SRAM_CH07] = 0;
332 }
333 dev->cif_width[SRAM_CH07] = fh->width;
334 medusa_set_resolution( dev, fh->width, SRAM_CH07 );
335
336 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
337 cx25821_call_all(dev, video, s_fmt, f);
338
339 return 0;
340} 337}
341 338
342static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 339static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
343{ 340{
344 int ret_val = 0; 341 int ret_val = 0;
345 struct cx25821_fh *fh = priv; 342 struct cx25821_fh *fh = priv;
346 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 343 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
347 344
348 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 345 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
349 346
350 p->sequence = dev->vidq[SRAM_CH07].count; 347 p->sequence = dev->vidq[SRAM_CH07].count;
351 348
352 return ret_val; 349 return ret_val;
353} 350}
354static int vidioc_log_status (struct file *file, void *priv) 351static int vidioc_log_status(struct file *file, void *priv)
355{ 352{
356 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 353 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
357 char name[32 + 2]; 354 char name[32 + 2];
358 355
359 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH07]; 356 struct sram_channel *sram_ch = &dev->sram_channels[SRAM_CH07];
360 u32 tmp = 0; 357 u32 tmp = 0;
361 358
362 snprintf(name, sizeof(name), "%s/2", dev->name); 359 snprintf(name, sizeof(name), "%s/2", dev->name);
363 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 360 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
364 dev->name); 361 dev->name);
365 cx25821_call_all(dev, core, log_status); 362 cx25821_call_all(dev, core, log_status);
366 363
367 tmp = cx_read(sram_ch->dma_ctl); 364 tmp = cx_read(sram_ch->dma_ctl);
368 printk(KERN_INFO "Video input 7 is %s\n", (tmp & 0x11)?"streaming" : "stopped"); 365 printk(KERN_INFO "Video input 7 is %s\n",
369 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 366 (tmp & 0x11) ? "streaming" : "stopped");
367 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
370 dev->name); 368 dev->name);
371 return 0; 369 return 0;
372} 370}
373 371
374static int vidioc_s_ctrl(struct file *file, void *priv, 372static int vidioc_s_ctrl(struct file *file, void *priv,
375 struct v4l2_control *ctl) 373 struct v4l2_control *ctl)
376{ 374{
377 struct cx25821_fh *fh = priv; 375 struct cx25821_fh *fh = priv;
378 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 376 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
@@ -389,66 +387,63 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
389 387
390// exported stuff 388// exported stuff
391static const struct v4l2_file_operations video_fops = { 389static const struct v4l2_file_operations video_fops = {
392 .owner = THIS_MODULE, 390 .owner = THIS_MODULE,
393 .open = video_open, 391 .open = video_open,
394 .release = video_release, 392 .release = video_release,
395 .read = video_read, 393 .read = video_read,
396 .poll = video_poll, 394 .poll = video_poll,
397 .mmap = video_mmap, 395 .mmap = video_mmap,
398 .ioctl = video_ioctl2, 396 .ioctl = video_ioctl2,
399}; 397};
400 398
401static const struct v4l2_ioctl_ops video_ioctl_ops = { 399static const struct v4l2_ioctl_ops video_ioctl_ops = {
402 .vidioc_querycap = vidioc_querycap, 400 .vidioc_querycap = vidioc_querycap,
403 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 401 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
404 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 402 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
405 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 403 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
406 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 404 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
407 .vidioc_reqbufs = vidioc_reqbufs, 405 .vidioc_reqbufs = vidioc_reqbufs,
408 .vidioc_querybuf = vidioc_querybuf, 406 .vidioc_querybuf = vidioc_querybuf,
409 .vidioc_qbuf = vidioc_qbuf, 407 .vidioc_qbuf = vidioc_qbuf,
410 .vidioc_dqbuf = vidioc_dqbuf, 408 .vidioc_dqbuf = vidioc_dqbuf,
411#ifdef TUNER_FLAG 409#ifdef TUNER_FLAG
412 .vidioc_s_std = vidioc_s_std, 410 .vidioc_s_std = vidioc_s_std,
413 .vidioc_querystd = vidioc_querystd, 411 .vidioc_querystd = vidioc_querystd,
414#endif 412#endif
415 .vidioc_cropcap = vidioc_cropcap, 413 .vidioc_cropcap = vidioc_cropcap,
416 .vidioc_s_crop = vidioc_s_crop, 414 .vidioc_s_crop = vidioc_s_crop,
417 .vidioc_g_crop = vidioc_g_crop, 415 .vidioc_g_crop = vidioc_g_crop,
418 .vidioc_enum_input = vidioc_enum_input, 416 .vidioc_enum_input = vidioc_enum_input,
419 .vidioc_g_input = vidioc_g_input, 417 .vidioc_g_input = vidioc_g_input,
420 .vidioc_s_input = vidioc_s_input, 418 .vidioc_s_input = vidioc_s_input,
421 .vidioc_g_ctrl = vidioc_g_ctrl, 419 .vidioc_g_ctrl = vidioc_g_ctrl,
422 .vidioc_s_ctrl = vidioc_s_ctrl, 420 .vidioc_s_ctrl = vidioc_s_ctrl,
423 .vidioc_queryctrl = vidioc_queryctrl, 421 .vidioc_queryctrl = vidioc_queryctrl,
424 .vidioc_streamon = vidioc_streamon, 422 .vidioc_streamon = vidioc_streamon,
425 .vidioc_streamoff = vidioc_streamoff, 423 .vidioc_streamoff = vidioc_streamoff,
426 .vidioc_log_status = vidioc_log_status, 424 .vidioc_log_status = vidioc_log_status,
427 .vidioc_g_priority = vidioc_g_priority, 425 .vidioc_g_priority = vidioc_g_priority,
428 .vidioc_s_priority = vidioc_s_priority, 426 .vidioc_s_priority = vidioc_s_priority,
429#ifdef CONFIG_VIDEO_V4L1_COMPAT 427#ifdef CONFIG_VIDEO_V4L1_COMPAT
430 .vidiocgmbuf = vidiocgmbuf, 428 .vidiocgmbuf = vidiocgmbuf,
431#endif 429#endif
432#ifdef TUNER_FLAG 430#ifdef TUNER_FLAG
433 .vidioc_g_tuner = vidioc_g_tuner, 431 .vidioc_g_tuner = vidioc_g_tuner,
434 .vidioc_s_tuner = vidioc_s_tuner, 432 .vidioc_s_tuner = vidioc_s_tuner,
435 .vidioc_g_frequency = vidioc_g_frequency, 433 .vidioc_g_frequency = vidioc_g_frequency,
436 .vidioc_s_frequency = vidioc_s_frequency, 434 .vidioc_s_frequency = vidioc_s_frequency,
437#endif 435#endif
438#ifdef CONFIG_VIDEO_ADV_DEBUG 436#ifdef CONFIG_VIDEO_ADV_DEBUG
439 .vidioc_g_register = vidioc_g_register, 437 .vidioc_g_register = vidioc_g_register,
440 .vidioc_s_register = vidioc_s_register, 438 .vidioc_s_register = vidioc_s_register,
441#endif 439#endif
442}; 440};
443 441
444struct video_device cx25821_video_template7 = { 442struct video_device cx25821_video_template7 = {
445 .name = "cx25821-video", 443 .name = "cx25821-video",
446 .fops = &video_fops, 444 .fops = &video_fops,
447 .minor = -1, 445 .minor = -1,
448 .ioctl_ops = &video_ioctl_ops, 446 .ioctl_ops = &video_ioctl_ops,
449 .tvnorms = CX25821_NORMS, 447 .tvnorms = CX25821_NORMS,
450 .current_norm = V4L2_STD_NTSC_M, 448 .current_norm = V4L2_STD_NTSC_M,
451}; 449};
452
453
454
diff --git a/drivers/staging/cx25821/cx25821-videoioctl.c b/drivers/staging/cx25821/cx25821-videoioctl.c
index ca93cd2af2d8..2a312ce78c63 100644
--- a/drivers/staging/cx25821/cx25821-videoioctl.c
+++ b/drivers/staging/cx25821/cx25821-videoioctl.c
@@ -23,478 +23,474 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[VIDEO_IOCTL_CH]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[VIDEO_IOCTL_CH];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[VIDEO_IOCTL_CH]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[VIDEO_IOCTL_CH]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 u32 pix_format; 102 u32 pix_format;
99 103
100 lock_kernel(); 104 lock_kernel();
101 list_for_each(list, &cx25821_devlist) 105 list_for_each(list, &cx25821_devlist) {
102 { 106 h = list_entry(list, struct cx25821_dev, devlist);
103 h = list_entry(list, struct cx25821_dev, devlist); 107
104 108 if (h->ioctl_dev && h->ioctl_dev->minor == minor) {
105 if (h->ioctl_dev && h->ioctl_dev->minor == minor) 109 dev = h;
106 { 110 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
107 dev = h; 111 }
108 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
109 } 112 }
110 }
111 113
112 if (NULL == dev) { 114 if (NULL == dev) {
113 unlock_kernel(); 115 unlock_kernel();
114 return -ENODEV; 116 return -ENODEV;
115 } 117 }
116 118
117 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 119 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
118 120
119 /* allocate + initialize per filehandle data */ 121 /* allocate + initialize per filehandle data */
120 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 122 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
121 if (NULL == fh) { 123 if (NULL == fh) {
122 unlock_kernel(); 124 unlock_kernel();
123 return -ENOMEM; 125 return -ENOMEM;
124 } 126 }
125 127
126 file->private_data = fh; 128 file->private_data = fh;
127 fh->dev = dev; 129 fh->dev = dev;
128 fh->type = type; 130 fh->type = type;
129 fh->width = 720; 131 fh->width = 720;
130 132
131 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
132 fh->height = 576; 134 fh->height = 576;
133 else 135 else
134 fh->height = 480; 136 fh->height = 480;
135 137
136 dev->channel_opened = VIDEO_IOCTL_CH; 138 dev->channel_opened = VIDEO_IOCTL_CH;
137 pix_format = V4L2_PIX_FMT_YUYV; 139 pix_format = V4L2_PIX_FMT_YUYV;
138 fh->fmt = format_by_fourcc(pix_format); 140 fh->fmt = format_by_fourcc(pix_format);
139 141
140 v4l2_prio_open(&dev->prio,&fh->prio); 142 v4l2_prio_open(&dev->prio, &fh->prio);
141 143
142 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, 144 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
143 &dev->pci->dev, &dev->slock, 145 &dev->pci->dev, &dev->slock,
144 V4L2_BUF_TYPE_VIDEO_CAPTURE, 146 V4L2_BUF_TYPE_VIDEO_CAPTURE,
145 V4L2_FIELD_INTERLACED, 147 V4L2_FIELD_INTERLACED,
146 sizeof(struct cx25821_buffer), 148 sizeof(struct cx25821_buffer), fh);
147 fh);
148 149
149 dprintk(1, "post videobuf_queue_init()\n"); 150 dprintk(1, "post videobuf_queue_init()\n");
150 unlock_kernel(); 151 unlock_kernel();
151 152
152 return 0; 153 return 0;
153} 154}
154 155
155static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 156static ssize_t video_read(struct file *file, char __user * data, size_t count,
157 loff_t * ppos)
156{ 158{
157 struct cx25821_fh *fh = file->private_data; 159 struct cx25821_fh *fh = file->private_data;
158 160
159 switch (fh->type) 161 switch (fh->type) {
160 {
161 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 162 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
162 if (res_locked(fh->dev, RESOURCE_VIDEO_IOCTL)) 163 if (res_locked(fh->dev, RESOURCE_VIDEO_IOCTL))
163 return -EBUSY; 164 return -EBUSY;
164 165
165 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 166 return videobuf_read_one(&fh->vidq, data, count, ppos,
167 file->f_flags & O_NONBLOCK);
166 168
167 default: 169 default:
168 BUG(); 170 BUG();
169 return 0; 171 return 0;
170 } 172 }
171} 173}
172 174
173static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 175static unsigned int video_poll(struct file *file,
176 struct poll_table_struct *wait)
174{ 177{
175 struct cx25821_fh *fh = file->private_data; 178 struct cx25821_fh *fh = file->private_data;
176 struct cx25821_buffer *buf; 179 struct cx25821_buffer *buf;
177 180
178 if (res_check(fh, RESOURCE_VIDEO_IOCTL)) { 181 if (res_check(fh, RESOURCE_VIDEO_IOCTL)) {
179 /* streaming capture */ 182 /* streaming capture */
180 if (list_empty(&fh->vidq.stream)) 183 if (list_empty(&fh->vidq.stream))
181 return POLLERR; 184 return POLLERR;
182 buf = list_entry(fh->vidq.stream.next, 185 buf = list_entry(fh->vidq.stream.next,
183 struct cx25821_buffer, vb.stream); 186 struct cx25821_buffer, vb.stream);
184 } else { 187 } else {
185 /* read() capture */ 188 /* read() capture */
186 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 189 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
187 if (NULL == buf) 190 if (NULL == buf)
188 return POLLERR; 191 return POLLERR;
189 } 192 }
190
191 poll_wait(file, &buf->vb.done, wait);
192 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
193 return POLLIN|POLLRDNORM;
194
195 return 0;
196}
197 193
194 poll_wait(file, &buf->vb.done, wait);
195 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
196 return POLLIN | POLLRDNORM;
197
198 return 0;
199}
198 200
199static int video_release(struct file *file) 201static int video_release(struct file *file)
200{ 202{
201 struct cx25821_fh *fh = file->private_data; 203 struct cx25821_fh *fh = file->private_data;
202 struct cx25821_dev *dev = fh->dev; 204 struct cx25821_dev *dev = fh->dev;
203 205
204 /* stop video capture */ 206 /* stop video capture */
205 if (res_check(fh, RESOURCE_VIDEO_IOCTL)) { 207 if (res_check(fh, RESOURCE_VIDEO_IOCTL)) {
206 videobuf_queue_cancel(&fh->vidq); 208 videobuf_queue_cancel(&fh->vidq);
207 res_free(dev, fh, RESOURCE_VIDEO_IOCTL); 209 res_free(dev, fh, RESOURCE_VIDEO_IOCTL);
208 } 210 }
209 211
210 if (fh->vidq.read_buf) { 212 if (fh->vidq.read_buf) {
211 buffer_release(&fh->vidq, fh->vidq.read_buf); 213 buffer_release(&fh->vidq, fh->vidq.read_buf);
212 kfree(fh->vidq.read_buf); 214 kfree(fh->vidq.read_buf);
213 } 215 }
214 216
215 videobuf_mmap_free(&fh->vidq); 217 videobuf_mmap_free(&fh->vidq);
216 218
217 v4l2_prio_close(&dev->prio,&fh->prio); 219 v4l2_prio_close(&dev->prio, &fh->prio);
218 220
219 file->private_data = NULL; 221 file->private_data = NULL;
220 kfree(fh); 222 kfree(fh);
221 223
222 return 0; 224 return 0;
223} 225}
224 226
225
226static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 227static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
227{ 228{
228 struct cx25821_fh *fh = priv; 229 struct cx25821_fh *fh = priv;
229 struct cx25821_dev *dev = fh->dev; 230 struct cx25821_dev *dev = fh->dev;
230 231
231 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 232 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
232 { 233 return -EINVAL;
233 return -EINVAL; 234 }
234 }
235 235
236 if (unlikely(i != fh->type)) 236 if (unlikely(i != fh->type)) {
237 { 237 return -EINVAL;
238 return -EINVAL; 238 }
239 }
240 239
241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO_IOCTL)))) 240 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO_IOCTL)))) {
242 { 241 return -EBUSY;
243 return -EBUSY; 242 }
244 }
245 243
246 return videobuf_streamon(get_queue(fh)); 244 return videobuf_streamon(get_queue(fh));
247} 245}
248 246
249static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 247static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
250{ 248{
251 struct cx25821_fh *fh = priv; 249 struct cx25821_fh *fh = priv;
252 struct cx25821_dev *dev = fh->dev; 250 struct cx25821_dev *dev = fh->dev;
253 int err, res; 251 int err, res;
254 252
255 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 253 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
256 return -EINVAL; 254 return -EINVAL;
257 if (i != fh->type) 255 if (i != fh->type)
258 return -EINVAL; 256 return -EINVAL;
259 257
260 res = get_resource(fh, RESOURCE_VIDEO_IOCTL); 258 res = get_resource(fh, RESOURCE_VIDEO_IOCTL);
261 err = videobuf_streamoff(get_queue(fh)); 259 err = videobuf_streamoff(get_queue(fh));
262 if (err < 0) 260 if (err < 0)
263 return err; 261 return err;
264 res_free(dev, fh, res); 262 res_free(dev, fh, res);
265 return 0; 263 return 0;
266} 264}
267 265
268 266static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
269static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 267 struct v4l2_format *f)
270{ 268{
271 struct cx25821_fh *fh = priv; 269 struct cx25821_fh *fh = priv;
272 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 270 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
273 int err; 271 int err;
272
273 if (fh) {
274 err = v4l2_prio_check(&dev->prio, &fh->prio);
275 if (0 != err)
276 return err;
277 }
278
279 dprintk(2, "%s()\n", __func__);
280 err = vidioc_try_fmt_vid_cap(file, priv, f);
274 281
275 if (fh)
276 {
277 err = v4l2_prio_check(&dev->prio, &fh->prio);
278 if (0 != err) 282 if (0 != err)
279 return err; 283 return err;
280 } 284 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
281 285 fh->width = f->fmt.pix.width;
282 dprintk(2, "%s()\n", __func__); 286 fh->height = f->fmt.pix.height;
283 err = vidioc_try_fmt_vid_cap(file, priv, f); 287 fh->vidq.field = f->fmt.pix.field;
284 288 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
285 if (0 != err) 289 fh->height, fh->vidq.field);
286 return err; 290 cx25821_call_all(dev, video, s_fmt, f);
287 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 291 return 0;
288 fh->width = f->fmt.pix.width;
289 fh->height = f->fmt.pix.height;
290 fh->vidq.field = f->fmt.pix.field;
291 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
292 cx25821_call_all(dev, video, s_fmt, f);
293 return 0;
294} 292}
295 293
296static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 294static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
297{ 295{
298 struct cx25821_fh *fh = priv; 296 struct cx25821_fh *fh = priv;
299 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 297 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
300} 298}
301 299
302static long video_ioctl_set(struct file *file, unsigned int cmd, unsigned long arg) 300static long video_ioctl_set(struct file *file, unsigned int cmd,
301 unsigned long arg)
303{ 302{
304 struct cx25821_fh *fh = file->private_data; 303 struct cx25821_fh *fh = file->private_data;
305 struct cx25821_dev *dev = fh->dev; 304 struct cx25821_dev *dev = fh->dev;
306 struct downstream_user_struct *data_from_user; 305 struct downstream_user_struct *data_from_user;
307 int command; 306 int command;
308 int width = 720; 307 int width = 720;
309 int selected_channel = 0, pix_format = 0, i = 0; 308 int selected_channel = 0, pix_format = 0, i = 0;
310 int cif_enable = 0, cif_width = 0; 309 int cif_enable = 0, cif_width = 0;
311 u32 value = 0; 310 u32 value = 0;
312 311
313 312 data_from_user = (struct downstream_user_struct *)arg;
314 data_from_user = (struct downstream_user_struct *)arg; 313
315 314 if (!data_from_user) {
316 if( !data_from_user ) 315 printk("cx25821 in %s(): User data is INVALID. Returning.\n",
317 { 316 __func__);
318 printk("cx25821 in %s(): User data is INVALID. Returning.\n", __func__); 317 return 0;
319 return 0; 318 }
320 }
321 319
322 command = data_from_user->command; 320 command = data_from_user->command;
323
324 if( command != SET_VIDEO_STD && command != SET_PIXEL_FORMAT && command != ENABLE_CIF_RESOLUTION &&
325 command != REG_READ && command != REG_WRITE && command != MEDUSA_READ && command != MEDUSA_WRITE)
326 {
327 return 0;
328 }
329 321
322 if (command != SET_VIDEO_STD && command != SET_PIXEL_FORMAT
323 && command != ENABLE_CIF_RESOLUTION && command != REG_READ
324 && command != REG_WRITE && command != MEDUSA_READ
325 && command != MEDUSA_WRITE) {
326 return 0;
327 }
330 328
331 switch(command) 329 switch (command) {
332 {
333 case SET_VIDEO_STD: 330 case SET_VIDEO_STD:
334 dev->tvnorm = !strcmp(data_from_user->vid_stdname,"PAL") ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M; 331 dev->tvnorm =
335 medusa_set_videostandard(dev); 332 !strcmp(data_from_user->vid_stdname,
336 break; 333 "PAL") ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
334 medusa_set_videostandard(dev);
335 break;
337 336
338 case SET_PIXEL_FORMAT: 337 case SET_PIXEL_FORMAT:
339 selected_channel = data_from_user->decoder_select; 338 selected_channel = data_from_user->decoder_select;
340 pix_format = data_from_user->pixel_format; 339 pix_format = data_from_user->pixel_format;
341 340
342 if( !(selected_channel <= 7 && selected_channel >= 0) ) 341 if (!(selected_channel <= 7 && selected_channel >= 0)) {
343 { 342 selected_channel -= 4;
344 selected_channel -= 4; 343 selected_channel = selected_channel % 8;
345 selected_channel = selected_channel % 8; 344 }
346 }
347 345
348 if( selected_channel >= 0 ) 346 if (selected_channel >= 0)
349 cx25821_set_pixel_format( dev, selected_channel, pix_format ); 347 cx25821_set_pixel_format(dev, selected_channel,
348 pix_format);
350 349
351 break; 350 break;
352 351
353 case ENABLE_CIF_RESOLUTION: 352 case ENABLE_CIF_RESOLUTION:
354 selected_channel = data_from_user->decoder_select; 353 selected_channel = data_from_user->decoder_select;
355 cif_enable = data_from_user->cif_resolution_enable; 354 cif_enable = data_from_user->cif_resolution_enable;
356 cif_width = data_from_user->cif_width; 355 cif_width = data_from_user->cif_width;
357 356
358 if( cif_enable ) 357 if (cif_enable) {
359 { 358 if (dev->tvnorm & V4L2_STD_PAL_BG
360 if( dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK ) 359 || dev->tvnorm & V4L2_STD_PAL_DK)
361 width = 352; 360 width = 352;
362 else 361 else
363 width = (cif_width == 320 || cif_width == 352) ? cif_width : 320; 362 width = (cif_width == 320
364 } 363 || cif_width == 352) ? cif_width : 320;
365
366 if( !(selected_channel <= 7 && selected_channel >= 0) )
367 {
368 selected_channel -= 4;
369 selected_channel = selected_channel % 8;
370 }
371
372
373 if( selected_channel <= 7 && selected_channel >= 0 )
374 {
375 dev->use_cif_resolution[selected_channel] = cif_enable;
376 dev->cif_width[selected_channel] = width;
377 }
378 else
379 {
380 for( i=0; i < VID_CHANNEL_NUM; i++ )
381 {
382 dev->use_cif_resolution[i] = cif_enable;
383 dev->cif_width[i] = width;
384 } 364 }
385 }
386 365
387 medusa_set_resolution( dev, width, selected_channel ); 366 if (!(selected_channel <= 7 && selected_channel >= 0)) {
388 break; 367 selected_channel -= 4;
368 selected_channel = selected_channel % 8;
369 }
370
371 if (selected_channel <= 7 && selected_channel >= 0) {
372 dev->use_cif_resolution[selected_channel] = cif_enable;
373 dev->cif_width[selected_channel] = width;
374 } else {
375 for (i = 0; i < VID_CHANNEL_NUM; i++) {
376 dev->use_cif_resolution[i] = cif_enable;
377 dev->cif_width[i] = width;
378 }
379 }
380
381 medusa_set_resolution(dev, width, selected_channel);
382 break;
389 case REG_READ: 383 case REG_READ:
390 data_from_user->reg_data = cx_read(data_from_user->reg_address); 384 data_from_user->reg_data = cx_read(data_from_user->reg_address);
391 break; 385 break;
392 case REG_WRITE: 386 case REG_WRITE:
393 cx_write(data_from_user->reg_address, data_from_user->reg_data); 387 cx_write(data_from_user->reg_address, data_from_user->reg_data);
394 break; 388 break;
395 case MEDUSA_READ: 389 case MEDUSA_READ:
396 value = cx25821_i2c_read(&dev->i2c_bus[0], (u16)data_from_user->reg_address, &data_from_user->reg_data); 390 value =
397 break; 391 cx25821_i2c_read(&dev->i2c_bus[0],
392 (u16) data_from_user->reg_address,
393 &data_from_user->reg_data);
394 break;
398 case MEDUSA_WRITE: 395 case MEDUSA_WRITE:
399 cx25821_i2c_write(&dev->i2c_bus[0], (u16)data_from_user->reg_address, data_from_user->reg_data); 396 cx25821_i2c_write(&dev->i2c_bus[0],
400 break; 397 (u16) data_from_user->reg_address,
401 } 398 data_from_user->reg_data);
399 break;
400 }
402 401
403 return 0; 402 return 0;
404} 403}
405 404
406static int vidioc_log_status (struct file *file, void *priv) 405static int vidioc_log_status(struct file *file, void *priv)
407{ 406{
408 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 407 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
409 char name[32 + 2]; 408 char name[32 + 2];
410 409
411 snprintf(name, sizeof(name), "%s/2", dev->name); 410 snprintf(name, sizeof(name), "%s/2", dev->name);
412 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 411 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
413 dev->name); 412 dev->name);
414 cx25821_call_all(dev, core, log_status); 413 cx25821_call_all(dev, core, log_status);
415 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 414 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
416 dev->name); 415 dev->name);
417 return 0; 416 return 0;
418} 417}
419 418
420static int vidioc_s_ctrl(struct file *file, void *priv, 419static int vidioc_s_ctrl(struct file *file, void *priv,
421 struct v4l2_control *ctl) 420 struct v4l2_control *ctl)
422{ 421{
423 struct cx25821_fh *fh = priv; 422 struct cx25821_fh *fh = priv;
424 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 423 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
425 int err; 424 int err;
426 425
427 if (fh) 426 if (fh) {
428 { 427 err = v4l2_prio_check(&dev->prio, &fh->prio);
429 err = v4l2_prio_check(&dev->prio, &fh->prio); 428 if (0 != err)
430 if (0 != err) 429 return err;
431 return err; 430 }
432 }
433 431
434 return 0; 432 return 0;
435} 433}
434
436// exported stuff 435// exported stuff
437static const struct v4l2_file_operations video_fops = { 436static const struct v4l2_file_operations video_fops = {
438 .owner = THIS_MODULE, 437 .owner = THIS_MODULE,
439 .open = video_open, 438 .open = video_open,
440 .release = video_release, 439 .release = video_release,
441 .read = video_read, 440 .read = video_read,
442 .poll = video_poll, 441 .poll = video_poll,
443 .mmap = video_mmap, 442 .mmap = video_mmap,
444 .ioctl = video_ioctl_set, 443 .ioctl = video_ioctl_set,
445}; 444};
446 445
447static const struct v4l2_ioctl_ops video_ioctl_ops = { 446static const struct v4l2_ioctl_ops video_ioctl_ops = {
448 .vidioc_querycap = vidioc_querycap, 447 .vidioc_querycap = vidioc_querycap,
449 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 448 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
450 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 449 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
451 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 450 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
452 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 451 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
453 .vidioc_reqbufs = vidioc_reqbufs, 452 .vidioc_reqbufs = vidioc_reqbufs,
454 .vidioc_querybuf = vidioc_querybuf, 453 .vidioc_querybuf = vidioc_querybuf,
455 .vidioc_qbuf = vidioc_qbuf, 454 .vidioc_qbuf = vidioc_qbuf,
456 .vidioc_dqbuf = vidioc_dqbuf, 455 .vidioc_dqbuf = vidioc_dqbuf,
457#ifdef TUNER_FLAG 456#ifdef TUNER_FLAG
458 .vidioc_s_std = vidioc_s_std, 457 .vidioc_s_std = vidioc_s_std,
459 .vidioc_querystd = vidioc_querystd, 458 .vidioc_querystd = vidioc_querystd,
460#endif 459#endif
461 .vidioc_cropcap = vidioc_cropcap, 460 .vidioc_cropcap = vidioc_cropcap,
462 .vidioc_s_crop = vidioc_s_crop, 461 .vidioc_s_crop = vidioc_s_crop,
463 .vidioc_g_crop = vidioc_g_crop, 462 .vidioc_g_crop = vidioc_g_crop,
464 .vidioc_enum_input = vidioc_enum_input, 463 .vidioc_enum_input = vidioc_enum_input,
465 .vidioc_g_input = vidioc_g_input, 464 .vidioc_g_input = vidioc_g_input,
466 .vidioc_s_input = vidioc_s_input, 465 .vidioc_s_input = vidioc_s_input,
467 .vidioc_g_ctrl = vidioc_g_ctrl, 466 .vidioc_g_ctrl = vidioc_g_ctrl,
468 .vidioc_s_ctrl = vidioc_s_ctrl, 467 .vidioc_s_ctrl = vidioc_s_ctrl,
469 .vidioc_queryctrl = vidioc_queryctrl, 468 .vidioc_queryctrl = vidioc_queryctrl,
470 .vidioc_streamon = vidioc_streamon, 469 .vidioc_streamon = vidioc_streamon,
471 .vidioc_streamoff = vidioc_streamoff, 470 .vidioc_streamoff = vidioc_streamoff,
472 .vidioc_log_status = vidioc_log_status, 471 .vidioc_log_status = vidioc_log_status,
473 .vidioc_g_priority = vidioc_g_priority, 472 .vidioc_g_priority = vidioc_g_priority,
474 .vidioc_s_priority = vidioc_s_priority, 473 .vidioc_s_priority = vidioc_s_priority,
475#ifdef CONFIG_VIDEO_V4L1_COMPAT 474#ifdef CONFIG_VIDEO_V4L1_COMPAT
476 .vidiocgmbuf = vidiocgmbuf, 475 .vidiocgmbuf = vidiocgmbuf,
477#endif 476#endif
478#ifdef TUNER_FLAG 477#ifdef TUNER_FLAG
479 .vidioc_g_tuner = vidioc_g_tuner, 478 .vidioc_g_tuner = vidioc_g_tuner,
480 .vidioc_s_tuner = vidioc_s_tuner, 479 .vidioc_s_tuner = vidioc_s_tuner,
481 .vidioc_g_frequency = vidioc_g_frequency, 480 .vidioc_g_frequency = vidioc_g_frequency,
482 .vidioc_s_frequency = vidioc_s_frequency, 481 .vidioc_s_frequency = vidioc_s_frequency,
483#endif 482#endif
484#ifdef CONFIG_VIDEO_ADV_DEBUG 483#ifdef CONFIG_VIDEO_ADV_DEBUG
485 .vidioc_g_register = vidioc_g_register, 484 .vidioc_g_register = vidioc_g_register,
486 .vidioc_s_register = vidioc_s_register, 485 .vidioc_s_register = vidioc_s_register,
487#endif 486#endif
488}; 487};
489 488
490struct video_device cx25821_videoioctl_template = { 489struct video_device cx25821_videoioctl_template = {
491 .name = "cx25821-videoioctl", 490 .name = "cx25821-videoioctl",
492 .fops = &video_fops, 491 .fops = &video_fops,
493 .minor = -1, 492 .minor = -1,
494 .ioctl_ops = &video_ioctl_ops, 493 .ioctl_ops = &video_ioctl_ops,
495 .tvnorms = CX25821_NORMS, 494 .tvnorms = CX25821_NORMS,
496 .current_norm = V4L2_STD_NTSC_M, 495 .current_norm = V4L2_STD_NTSC_M,
497}; 496};
498
499
500
diff --git a/drivers/staging/cx25821/cx25821-vidups10.c b/drivers/staging/cx25821/cx25821-vidups10.c
index 1e18a87669b2..77b63b060405 100644
--- a/drivers/staging/cx25821/cx25821-vidups10.c
+++ b/drivers/staging/cx25821/cx25821-vidups10.c
@@ -23,421 +23,413 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH10]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH10];
35 34
36 /* add jump to stopper */ 35 /* add jump to stopper */
37 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 39
41 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 41
43 if (!list_empty(&q->queued)) { 42 if (!list_empty(&q->queued)) {
44 list_add_tail(&buf->vb.queue, &q->queued); 43 list_add_tail(&buf->vb.queue, &q->queued);
45 buf->vb.state = VIDEOBUF_QUEUED; 44 buf->vb.state = VIDEOBUF_QUEUED;
46 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 46 buf->vb.i);
48 } else if (list_empty(&q->active)) { 47
49 list_add_tail(&buf->vb.queue, &q->active); 48 } else if (list_empty(&q->active)) {
50 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH10]); 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->vb.state = VIDEOBUF_ACTIVE; 50 cx25821_start_video_dma(dev, q, buf,
52 buf->count = q->count++; 51 &dev->sram_channels[SRAM_CH10]);
53 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 53 buf->count = q->count++;
55 buf, buf->vb. i, buf->count, q->count); 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 } else { 55 dprintk(2,
57 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 if (prev->vb.width == buf->vb.width && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->vb.height == buf->vb.height &&
60 prev->fmt == buf->fmt) {
61 list_add_tail(&buf->vb.queue, &q->active);
62 buf->vb.state = VIDEOBUF_ACTIVE;
63 buf->count = q->count++;
64 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
65
66 /* 64 bit bits 63-32 */
67 prev->risc.jmp[2] = cpu_to_le32(0);
68 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
69
70 } else { 58 } else {
71 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
72 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
73 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
74 } 81 }
75 }
76 82
77 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
78 { 84 dprintk(2, "active queue empty!\n");
79 dprintk(2, "active queue empty!\n"); 85 }
80 }
81} 86}
82 87
83
84static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
85 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
86 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
87 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
88 .buf_release = buffer_release, 92 .buf_release = buffer_release,
89}; 93};
90 94
91
92static int video_open(struct file *file) 95static int video_open(struct file *file)
93{ 96{
94 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
95 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
96 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
97 struct list_head *list; 100 struct list_head *list;
98 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
99 102
100 lock_kernel(); 103 lock_kernel();
101 list_for_each(list, &cx25821_devlist) 104 list_for_each(list, &cx25821_devlist) {
102 { 105 h = list_entry(list, struct cx25821_dev, devlist);
103 h = list_entry(list, struct cx25821_dev, devlist); 106
104 107 if (h->video_dev[SRAM_CH10]
105 if (h->video_dev[SRAM_CH10] && h->video_dev[SRAM_CH10]->minor == minor) { 108 && h->video_dev[SRAM_CH10]->minor == minor) {
106 dev = h; 109 dev = h;
107 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 110 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
111 }
108 } 112 }
109 }
110
111 if (NULL == dev) {
112 unlock_kernel();
113 return -ENODEV;
114 }
115 113
116 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 114 if (NULL == dev) {
115 unlock_kernel();
116 return -ENODEV;
117 }
117 118
118 /* allocate + initialize per filehandle data */ 119 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
119 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
120 if (NULL == fh) {
121 unlock_kernel();
122 return -ENOMEM;
123 }
124 120
125 file->private_data = fh; 121 /* allocate + initialize per filehandle data */
126 fh->dev = dev; 122 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
127 fh->type = type; 123 if (NULL == fh) {
128 fh->width = 720; 124 unlock_kernel();
125 return -ENOMEM;
126 }
129 127
130 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 128 file->private_data = fh;
131 fh->height = 576; 129 fh->dev = dev;
132 else 130 fh->type = type;
133 fh->height = 480; 131 fh->width = 720;
134 132
133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
134 fh->height = 576;
135 else
136 fh->height = 480;
135 137
136 dev->channel_opened = 9; 138 dev->channel_opened = 9;
137 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); 139 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV);
138 140
139 v4l2_prio_open(&dev->prio,&fh->prio); 141 v4l2_prio_open(&dev->prio, &fh->prio);
140 142
141 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, 143 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
142 &dev->pci->dev, &dev->slock, 144 &dev->pci->dev, &dev->slock,
143 V4L2_BUF_TYPE_VIDEO_CAPTURE, 145 V4L2_BUF_TYPE_VIDEO_CAPTURE,
144 V4L2_FIELD_INTERLACED, 146 V4L2_FIELD_INTERLACED,
145 sizeof(struct cx25821_buffer), 147 sizeof(struct cx25821_buffer), fh);
146 fh);
147 148
148 dprintk(1, "post videobuf_queue_init()\n"); 149 dprintk(1, "post videobuf_queue_init()\n");
149 unlock_kernel(); 150 unlock_kernel();
150 151
151 return 0; 152 return 0;
152} 153}
153 154
154static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 155static ssize_t video_read(struct file *file, char __user * data, size_t count,
156 loff_t * ppos)
155{ 157{
156 struct cx25821_fh *fh = file->private_data; 158 struct cx25821_fh *fh = file->private_data;
157 159
158 switch (fh->type) 160 switch (fh->type) {
159 {
160 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 161 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
161 if (res_locked(fh->dev, RESOURCE_VIDEO10)) 162 if (res_locked(fh->dev, RESOURCE_VIDEO10))
162 return -EBUSY; 163 return -EBUSY;
163 164
164 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 165 return videobuf_read_one(&fh->vidq, data, count, ppos,
166 file->f_flags & O_NONBLOCK);
165 167
166 default: 168 default:
167 BUG(); 169 BUG();
168 return 0; 170 return 0;
169 } 171 }
170} 172}
171 173
172static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 174static unsigned int video_poll(struct file *file,
175 struct poll_table_struct *wait)
173{ 176{
174 struct cx25821_fh *fh = file->private_data; 177 struct cx25821_fh *fh = file->private_data;
175 struct cx25821_buffer *buf; 178 struct cx25821_buffer *buf;
176 179
177 if (res_check(fh, RESOURCE_VIDEO10)) { 180 if (res_check(fh, RESOURCE_VIDEO10)) {
178 /* streaming capture */ 181 /* streaming capture */
179 if (list_empty(&fh->vidq.stream)) 182 if (list_empty(&fh->vidq.stream))
180 return POLLERR; 183 return POLLERR;
181 buf = list_entry(fh->vidq.stream.next, 184 buf = list_entry(fh->vidq.stream.next,
182 struct cx25821_buffer, vb.stream); 185 struct cx25821_buffer, vb.stream);
183 } else { 186 } else {
184 /* read() capture */ 187 /* read() capture */
185 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 188 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
186 if (NULL == buf) 189 if (NULL == buf)
187 return POLLERR; 190 return POLLERR;
188 } 191 }
189 192
190 poll_wait(file, &buf->vb.done, wait); 193 poll_wait(file, &buf->vb.done, wait);
191 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) 194 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
192 return POLLIN|POLLRDNORM; 195 return POLLIN | POLLRDNORM;
193 return 0; 196 return 0;
194} 197}
195 198
196static int video_release(struct file *file) 199static int video_release(struct file *file)
197{ 200{
198 struct cx25821_fh *fh = file->private_data; 201 struct cx25821_fh *fh = file->private_data;
199 struct cx25821_dev *dev = fh->dev; 202 struct cx25821_dev *dev = fh->dev;
200 203
201 //stop the risc engine and fifo 204 //stop the risc engine and fifo
202 //cx_write(channel10->dma_ctl, 0); 205 //cx_write(channel10->dma_ctl, 0);
203 206
204 /* stop video capture */ 207 /* stop video capture */
205 if (res_check(fh, RESOURCE_VIDEO10)) { 208 if (res_check(fh, RESOURCE_VIDEO10)) {
206 videobuf_queue_cancel(&fh->vidq); 209 videobuf_queue_cancel(&fh->vidq);
207 res_free(dev, fh, RESOURCE_VIDEO10); 210 res_free(dev, fh, RESOURCE_VIDEO10);
208 } 211 }
209 212
210 if (fh->vidq.read_buf) { 213 if (fh->vidq.read_buf) {
211 buffer_release(&fh->vidq, fh->vidq.read_buf); 214 buffer_release(&fh->vidq, fh->vidq.read_buf);
212 kfree(fh->vidq.read_buf); 215 kfree(fh->vidq.read_buf);
213 } 216 }
214 217
215 videobuf_mmap_free(&fh->vidq); 218 videobuf_mmap_free(&fh->vidq);
216 219
217 v4l2_prio_close(&dev->prio,&fh->prio); 220 v4l2_prio_close(&dev->prio, &fh->prio);
218 221
219 file->private_data = NULL; 222 file->private_data = NULL;
220 kfree(fh); 223 kfree(fh);
221 224
222 return 0; 225 return 0;
223} 226}
224 227
225
226static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 228static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
227{ 229{
228 struct cx25821_fh *fh = priv; 230 struct cx25821_fh *fh = priv;
229 struct cx25821_dev *dev = fh->dev; 231 struct cx25821_dev *dev = fh->dev;
230 232
231 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 233 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
232 { 234 return -EINVAL;
233 return -EINVAL; 235 }
234 }
235 236
236 if (unlikely(i != fh->type)) 237 if (unlikely(i != fh->type)) {
237 { 238 return -EINVAL;
238 return -EINVAL; 239 }
239 }
240 240
241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO10)))) 241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO10)))) {
242 { 242 return -EBUSY;
243 return -EBUSY; 243 }
244 }
245 244
246 return videobuf_streamon(get_queue(fh)); 245 return videobuf_streamon(get_queue(fh));
247} 246}
248 247
249static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 248static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
250{ 249{
251 struct cx25821_fh *fh = priv; 250 struct cx25821_fh *fh = priv;
252 struct cx25821_dev *dev = fh->dev; 251 struct cx25821_dev *dev = fh->dev;
253 int err, res; 252 int err, res;
254 253
255 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 254 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
256 return -EINVAL; 255 return -EINVAL;
257 if (i != fh->type) 256 if (i != fh->type)
258 return -EINVAL; 257 return -EINVAL;
259 258
260 res = get_resource(fh, RESOURCE_VIDEO10); 259 res = get_resource(fh, RESOURCE_VIDEO10);
261 err = videobuf_streamoff(get_queue(fh)); 260 err = videobuf_streamoff(get_queue(fh));
262 if (err < 0) 261 if (err < 0)
263 return err; 262 return err;
264 res_free(dev, fh, res); 263 res_free(dev, fh, res);
265 return 0; 264 return 0;
266} 265}
267 266
268 267static long video_ioctl_upstream10(struct file *file, unsigned int cmd,
269static long video_ioctl_upstream10(struct file *file, unsigned int cmd, unsigned long arg) 268 unsigned long arg)
270{ 269{
271 struct cx25821_fh *fh = file->private_data; 270 struct cx25821_fh *fh = file->private_data;
272 struct cx25821_dev *dev = fh->dev; 271 struct cx25821_dev *dev = fh->dev;
273 int command = 0; 272 int command = 0;
274 struct upstream_user_struct *data_from_user; 273 struct upstream_user_struct *data_from_user;
275 274
276 275 data_from_user = (struct upstream_user_struct *)arg;
277 data_from_user = (struct upstream_user_struct *)arg; 276
278 277 if (!data_from_user) {
279 if( !data_from_user ) 278 printk
280 { 279 ("cx25821 in %s(): Upstream data is INVALID. Returning.\n",
281 printk("cx25821 in %s(): Upstream data is INVALID. Returning.\n", __func__); 280 __func__);
282 return 0; 281 return 0;
283 } 282 }
284
285 command = data_from_user->command;
286 283
287 if( command != UPSTREAM_START_VIDEO && command != UPSTREAM_STOP_VIDEO ) 284 command = data_from_user->command;
288 {
289 return 0;
290 }
291 285
292 dev->input_filename_ch2 = data_from_user->input_filename; 286 if (command != UPSTREAM_START_VIDEO && command != UPSTREAM_STOP_VIDEO) {
293 dev->input_audiofilename = data_from_user->input_filename; 287 return 0;
294 dev->vid_stdname_ch2 = data_from_user->vid_stdname; 288 }
295 dev->pixel_format_ch2 = data_from_user->pixel_format;
296 dev->channel_select_ch2 = data_from_user->channel_select;
297 dev->command_ch2 = data_from_user->command;
298 289
290 dev->input_filename_ch2 = data_from_user->input_filename;
291 dev->input_audiofilename = data_from_user->input_filename;
292 dev->vid_stdname_ch2 = data_from_user->vid_stdname;
293 dev->pixel_format_ch2 = data_from_user->pixel_format;
294 dev->channel_select_ch2 = data_from_user->channel_select;
295 dev->command_ch2 = data_from_user->command;
299 296
300 switch(command) 297 switch (command) {
301 {
302 case UPSTREAM_START_VIDEO: 298 case UPSTREAM_START_VIDEO:
303 cx25821_start_upstream_video_ch2(dev, data_from_user); 299 cx25821_start_upstream_video_ch2(dev, data_from_user);
304 break; 300 break;
305 301
306 case UPSTREAM_STOP_VIDEO: 302 case UPSTREAM_STOP_VIDEO:
307 cx25821_stop_upstream_video_ch2(dev); 303 cx25821_stop_upstream_video_ch2(dev);
308 break; 304 break;
309 } 305 }
310 306
311 return 0; 307 return 0;
312} 308}
313 309
314 310static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
315static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 311 struct v4l2_format *f)
316{ 312{
317 struct cx25821_fh *fh = priv; 313 struct cx25821_fh *fh = priv;
318 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 314 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
319 int err; 315 int err;
316
317 if (fh) {
318 err = v4l2_prio_check(&dev->prio, &fh->prio);
319 if (0 != err)
320 return err;
321 }
322
323 dprintk(2, "%s()\n", __func__);
324 err = vidioc_try_fmt_vid_cap(file, priv, f);
320 325
321 if (fh)
322 {
323 err = v4l2_prio_check(&dev->prio, &fh->prio);
324 if (0 != err) 326 if (0 != err)
325 return err; 327 return err;
326 } 328 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
327 329 fh->width = f->fmt.pix.width;
328 dprintk(2, "%s()\n", __func__); 330 fh->height = f->fmt.pix.height;
329 err = vidioc_try_fmt_vid_cap(file, priv, f); 331 fh->vidq.field = f->fmt.pix.field;
330 332 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
331 if (0 != err) 333 fh->height, fh->vidq.field);
332 return err; 334 cx25821_call_all(dev, video, s_fmt, f);
333 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 335 return 0;
334 fh->width = f->fmt.pix.width;
335 fh->height = f->fmt.pix.height;
336 fh->vidq.field = f->fmt.pix.field;
337 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
338 cx25821_call_all(dev, video, s_fmt, f);
339 return 0;
340} 336}
341 337
342static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 338static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
343{ 339{
344 struct cx25821_fh *fh = priv; 340 struct cx25821_fh *fh = priv;
345 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 341 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
346} 342}
347 343
348static int vidioc_log_status (struct file *file, void *priv) 344static int vidioc_log_status(struct file *file, void *priv)
349{ 345{
350 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 346 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
351 char name[32 + 2]; 347 char name[32 + 2];
352 348
353 snprintf(name, sizeof(name), "%s/2", dev->name); 349 snprintf(name, sizeof(name), "%s/2", dev->name);
354 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 350 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
355 dev->name); 351 dev->name);
356 cx25821_call_all(dev, core, log_status); 352 cx25821_call_all(dev, core, log_status);
357 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 353 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
358 dev->name); 354 dev->name);
359 return 0; 355 return 0;
360} 356}
361 357
362static int vidioc_s_ctrl(struct file *file, void *priv, 358static int vidioc_s_ctrl(struct file *file, void *priv,
363 struct v4l2_control *ctl) 359 struct v4l2_control *ctl)
364{ 360{
365 struct cx25821_fh *fh = priv; 361 struct cx25821_fh *fh = priv;
366 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 362 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
367 int err; 363 int err;
368 364
369 if (fh) 365 if (fh) {
370 { 366 err = v4l2_prio_check(&dev->prio, &fh->prio);
371 err = v4l2_prio_check(&dev->prio, &fh->prio); 367 if (0 != err)
372 if (0 != err) 368 return err;
373 return err; 369 }
374 }
375 370
376 return 0; 371 return 0;
377} 372}
378 373
379//exported stuff 374//exported stuff
380static const struct v4l2_file_operations video_fops = { 375static const struct v4l2_file_operations video_fops = {
381 .owner = THIS_MODULE, 376 .owner = THIS_MODULE,
382 .open = video_open, 377 .open = video_open,
383 .release = video_release, 378 .release = video_release,
384 .read = video_read, 379 .read = video_read,
385 .poll = video_poll, 380 .poll = video_poll,
386 .mmap = video_mmap, 381 .mmap = video_mmap,
387 .ioctl = video_ioctl_upstream10, 382 .ioctl = video_ioctl_upstream10,
388}; 383};
389 384
390static const struct v4l2_ioctl_ops video_ioctl_ops = { 385static const struct v4l2_ioctl_ops video_ioctl_ops = {
391 .vidioc_querycap = vidioc_querycap, 386 .vidioc_querycap = vidioc_querycap,
392 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 387 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
393 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 388 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
394 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 389 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
395 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 390 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
396 .vidioc_reqbufs = vidioc_reqbufs, 391 .vidioc_reqbufs = vidioc_reqbufs,
397 .vidioc_querybuf = vidioc_querybuf, 392 .vidioc_querybuf = vidioc_querybuf,
398 .vidioc_qbuf = vidioc_qbuf, 393 .vidioc_qbuf = vidioc_qbuf,
399 .vidioc_dqbuf = vidioc_dqbuf, 394 .vidioc_dqbuf = vidioc_dqbuf,
400#ifdef TUNER_FLAG 395#ifdef TUNER_FLAG
401 .vidioc_s_std = vidioc_s_std, 396 .vidioc_s_std = vidioc_s_std,
402 .vidioc_querystd = vidioc_querystd, 397 .vidioc_querystd = vidioc_querystd,
403#endif 398#endif
404 .vidioc_cropcap = vidioc_cropcap, 399 .vidioc_cropcap = vidioc_cropcap,
405 .vidioc_s_crop = vidioc_s_crop, 400 .vidioc_s_crop = vidioc_s_crop,
406 .vidioc_g_crop = vidioc_g_crop, 401 .vidioc_g_crop = vidioc_g_crop,
407 .vidioc_enum_input = vidioc_enum_input, 402 .vidioc_enum_input = vidioc_enum_input,
408 .vidioc_g_input = vidioc_g_input, 403 .vidioc_g_input = vidioc_g_input,
409 .vidioc_s_input = vidioc_s_input, 404 .vidioc_s_input = vidioc_s_input,
410 .vidioc_g_ctrl = vidioc_g_ctrl, 405 .vidioc_g_ctrl = vidioc_g_ctrl,
411 .vidioc_s_ctrl = vidioc_s_ctrl, 406 .vidioc_s_ctrl = vidioc_s_ctrl,
412 .vidioc_queryctrl = vidioc_queryctrl, 407 .vidioc_queryctrl = vidioc_queryctrl,
413 .vidioc_streamon = vidioc_streamon, 408 .vidioc_streamon = vidioc_streamon,
414 .vidioc_streamoff = vidioc_streamoff, 409 .vidioc_streamoff = vidioc_streamoff,
415 .vidioc_log_status = vidioc_log_status, 410 .vidioc_log_status = vidioc_log_status,
416 .vidioc_g_priority = vidioc_g_priority, 411 .vidioc_g_priority = vidioc_g_priority,
417 .vidioc_s_priority = vidioc_s_priority, 412 .vidioc_s_priority = vidioc_s_priority,
418#ifdef CONFIG_VIDEO_V4L1_COMPAT 413#ifdef CONFIG_VIDEO_V4L1_COMPAT
419 .vidiocgmbuf = vidiocgmbuf, 414 .vidiocgmbuf = vidiocgmbuf,
420#endif 415#endif
421#ifdef TUNER_FLAG 416#ifdef TUNER_FLAG
422 .vidioc_g_tuner = vidioc_g_tuner, 417 .vidioc_g_tuner = vidioc_g_tuner,
423 .vidioc_s_tuner = vidioc_s_tuner, 418 .vidioc_s_tuner = vidioc_s_tuner,
424 .vidioc_g_frequency = vidioc_g_frequency, 419 .vidioc_g_frequency = vidioc_g_frequency,
425 .vidioc_s_frequency = vidioc_s_frequency, 420 .vidioc_s_frequency = vidioc_s_frequency,
426#endif 421#endif
427#ifdef CONFIG_VIDEO_ADV_DEBUG 422#ifdef CONFIG_VIDEO_ADV_DEBUG
428 .vidioc_g_register = vidioc_g_register, 423 .vidioc_g_register = vidioc_g_register,
429 .vidioc_s_register = vidioc_s_register, 424 .vidioc_s_register = vidioc_s_register,
430#endif 425#endif
431}; 426};
432 427
433struct video_device cx25821_video_template10 = { 428struct video_device cx25821_video_template10 = {
434 .name = "cx25821-upstream10", 429 .name = "cx25821-upstream10",
435 .fops = &video_fops, 430 .fops = &video_fops,
436 .minor = -1, 431 .minor = -1,
437 .ioctl_ops = &video_ioctl_ops, 432 .ioctl_ops = &video_ioctl_ops,
438 .tvnorms = CX25821_NORMS, 433 .tvnorms = CX25821_NORMS,
439 .current_norm = V4L2_STD_NTSC_M, 434 .current_norm = V4L2_STD_NTSC_M,
440}; 435};
441
442
443
diff --git a/drivers/staging/cx25821/cx25821-vidups9.c b/drivers/staging/cx25821/cx25821-vidups9.c
index 947ea5bc8f66..75c8c1eed2da 100644
--- a/drivers/staging/cx25821/cx25821-vidups9.c
+++ b/drivers/staging/cx25821/cx25821-vidups9.c
@@ -23,419 +23,411 @@
23 23
24#include "cx25821-video.h" 24#include "cx25821-video.h"
25 25
26
27static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb) 26static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
28{ 27{
29 struct cx25821_buffer *buf = container_of(vb, struct cx25821_buffer, vb); 28 struct cx25821_buffer *buf =
30 struct cx25821_buffer *prev; 29 container_of(vb, struct cx25821_buffer, vb);
31 struct cx25821_fh *fh = vq->priv_data; 30 struct cx25821_buffer *prev;
32 struct cx25821_dev *dev = fh->dev; 31 struct cx25821_fh *fh = vq->priv_data;
33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH09]; 32 struct cx25821_dev *dev = fh->dev;
34 33 struct cx25821_dmaqueue *q = &dev->vidq[SRAM_CH09];
35 /* add jump to stopper */ 34
36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 35 /* add jump to stopper */
37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); 36 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ 37 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
39 38 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]); 39
41 40 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
42 if (!list_empty(&q->queued)) { 41
43 list_add_tail(&buf->vb.queue, &q->queued); 42 if (!list_empty(&q->queued)) {
44 buf->vb.state = VIDEOBUF_QUEUED; 43 list_add_tail(&buf->vb.queue, &q->queued);
45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf, buf->vb.i); 44 buf->vb.state = VIDEOBUF_QUEUED;
46 45 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
47 } else if (list_empty(&q->active)) { 46 buf->vb.i);
48 list_add_tail(&buf->vb.queue, &q->active); 47
49 cx25821_start_video_dma(dev, q, buf, &dev->sram_channels[SRAM_CH09]); 48 } else if (list_empty(&q->active)) {
50 buf->vb.state = VIDEOBUF_ACTIVE; 49 list_add_tail(&buf->vb.queue, &q->active);
51 buf->count = q->count++; 50 cx25821_start_video_dma(dev, q, buf,
52 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); 51 &dev->sram_channels[SRAM_CH09]);
53 dprintk(2, "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n", 52 buf->vb.state = VIDEOBUF_ACTIVE;
54 buf, buf->vb. i, buf->count, q->count); 53 buf->count = q->count++;
55 } else { 54 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
56 prev = list_entry(q->active.prev, struct cx25821_buffer, vb.queue); 55 dprintk(2,
57 if (prev->vb.width == buf->vb.width && 56 "[%p/%d] buffer_queue - first active, buf cnt = %d, q->count = %d\n",
58 prev->vb.height == buf->vb.height && 57 buf, buf->vb.i, buf->count, q->count);
59 prev->fmt == buf->fmt) {
60 list_add_tail(&buf->vb.queue, &q->active);
61 buf->vb.state = VIDEOBUF_ACTIVE;
62 buf->count = q->count++;
63 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
64
65 /* 64 bit bits 63-32 */
66 prev->risc.jmp[2] = cpu_to_le32(0);
67 dprintk(2, "[%p/%d] buffer_queue - append to active, buf->count=%d\n", buf, buf->vb.i, buf->count);
68
69 } else { 58 } else {
70 list_add_tail(&buf->vb.queue, &q->queued); 59 prev =
71 buf->vb.state = VIDEOBUF_QUEUED; 60 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
72 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf, buf->vb.i); 61 if (prev->vb.width == buf->vb.width
62 && prev->vb.height == buf->vb.height
63 && prev->fmt == buf->fmt) {
64 list_add_tail(&buf->vb.queue, &q->active);
65 buf->vb.state = VIDEOBUF_ACTIVE;
66 buf->count = q->count++;
67 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
68
69 /* 64 bit bits 63-32 */
70 prev->risc.jmp[2] = cpu_to_le32(0);
71 dprintk(2,
72 "[%p/%d] buffer_queue - append to active, buf->count=%d\n",
73 buf, buf->vb.i, buf->count);
74
75 } else {
76 list_add_tail(&buf->vb.queue, &q->queued);
77 buf->vb.state = VIDEOBUF_QUEUED;
78 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
79 buf->vb.i);
80 }
73 } 81 }
74 }
75 82
76 if (list_empty(&q->active)) 83 if (list_empty(&q->active)) {
77 { 84 dprintk(2, "active queue empty!\n");
78 dprintk(2, "active queue empty!\n"); 85 }
79 }
80} 86}
81 87
82
83static struct videobuf_queue_ops cx25821_video_qops = { 88static struct videobuf_queue_ops cx25821_video_qops = {
84 .buf_setup = buffer_setup, 89 .buf_setup = buffer_setup,
85 .buf_prepare = buffer_prepare, 90 .buf_prepare = buffer_prepare,
86 .buf_queue = buffer_queue, 91 .buf_queue = buffer_queue,
87 .buf_release = buffer_release, 92 .buf_release = buffer_release,
88}; 93};
89 94
90
91static int video_open(struct file *file) 95static int video_open(struct file *file)
92{ 96{
93 int minor = video_devdata(file)->minor; 97 int minor = video_devdata(file)->minor;
94 struct cx25821_dev *h, *dev = NULL; 98 struct cx25821_dev *h, *dev = NULL;
95 struct cx25821_fh *fh; 99 struct cx25821_fh *fh;
96 struct list_head *list; 100 struct list_head *list;
97 enum v4l2_buf_type type = 0; 101 enum v4l2_buf_type type = 0;
98 102
99 lock_kernel(); 103 lock_kernel();
100 list_for_each(list, &cx25821_devlist) 104 list_for_each(list, &cx25821_devlist) {
101 { 105 h = list_entry(list, struct cx25821_dev, devlist);
102 h = list_entry(list, struct cx25821_dev, devlist); 106
103 107 if (h->video_dev[SRAM_CH09]
104 if (h->video_dev[SRAM_CH09] && h->video_dev[SRAM_CH09]->minor == minor) 108 && h->video_dev[SRAM_CH09]->minor == minor) {
105 { 109 dev = h;
106 dev = h; 110 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
107 type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 111 }
108 } 112 }
109 }
110 113
111 if (NULL == dev) { 114 if (NULL == dev) {
112 unlock_kernel(); 115 unlock_kernel();
113 return -ENODEV; 116 return -ENODEV;
114 } 117 }
115 118
116 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]); 119 printk("open minor=%d type=%s\n", minor, v4l2_type_names[type]);
117 120
118 /* allocate + initialize per filehandle data */ 121 /* allocate + initialize per filehandle data */
119 fh = kzalloc(sizeof(*fh), GFP_KERNEL); 122 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
120 if (NULL == fh) { 123 if (NULL == fh) {
121 unlock_kernel(); 124 unlock_kernel();
122 return -ENOMEM; 125 return -ENOMEM;
123 } 126 }
124 127
125 file->private_data = fh; 128 file->private_data = fh;
126 fh->dev = dev; 129 fh->dev = dev;
127 fh->type = type; 130 fh->type = type;
128 fh->width = 720; 131 fh->width = 720;
129 132
130 if(dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 133 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
131 fh->height = 576; 134 fh->height = 576;
132 else 135 else
133 fh->height = 480; 136 fh->height = 480;
134 137
135 dev->channel_opened = 8; 138 dev->channel_opened = 8;
136 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); 139 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV);
137 140
138 v4l2_prio_open(&dev->prio,&fh->prio); 141 v4l2_prio_open(&dev->prio, &fh->prio);
139 142
140 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops, 143 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
141 &dev->pci->dev, &dev->slock, 144 &dev->pci->dev, &dev->slock,
142 V4L2_BUF_TYPE_VIDEO_CAPTURE, 145 V4L2_BUF_TYPE_VIDEO_CAPTURE,
143 V4L2_FIELD_INTERLACED, 146 V4L2_FIELD_INTERLACED,
144 sizeof(struct cx25821_buffer), 147 sizeof(struct cx25821_buffer), fh);
145 fh);
146 148
147 dprintk(1, "post videobuf_queue_init()\n"); 149 dprintk(1, "post videobuf_queue_init()\n");
148 unlock_kernel(); 150 unlock_kernel();
149 151
150 return 0; 152 return 0;
151} 153}
152 154
153static ssize_t video_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 155static ssize_t video_read(struct file *file, char __user * data, size_t count,
156 loff_t * ppos)
154{ 157{
155 struct cx25821_fh *fh = file->private_data; 158 struct cx25821_fh *fh = file->private_data;
156 159
157 switch (fh->type) 160 switch (fh->type) {
158 {
159 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 161 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
160 if (res_locked(fh->dev, RESOURCE_VIDEO9)) 162 if (res_locked(fh->dev, RESOURCE_VIDEO9))
161 return -EBUSY; 163 return -EBUSY;
162 164
163 return videobuf_read_one(&fh->vidq, data, count, ppos, file->f_flags & O_NONBLOCK); 165 return videobuf_read_one(&fh->vidq, data, count, ppos,
166 file->f_flags & O_NONBLOCK);
164 167
165 default: 168 default:
166 BUG(); 169 BUG();
167 return 0; 170 return 0;
168 } 171 }
169} 172}
170 173
171static unsigned int video_poll(struct file *file, struct poll_table_struct *wait) 174static unsigned int video_poll(struct file *file,
175 struct poll_table_struct *wait)
172{ 176{
173 struct cx25821_fh *fh = file->private_data; 177 struct cx25821_fh *fh = file->private_data;
174 struct cx25821_buffer *buf; 178 struct cx25821_buffer *buf;
175 179
176 if (res_check(fh, RESOURCE_VIDEO9)) { 180 if (res_check(fh, RESOURCE_VIDEO9)) {
177 /* streaming capture */ 181 /* streaming capture */
178 if (list_empty(&fh->vidq.stream)) 182 if (list_empty(&fh->vidq.stream))
179 return POLLERR; 183 return POLLERR;
180 buf = list_entry(fh->vidq.stream.next, 184 buf = list_entry(fh->vidq.stream.next,
181 struct cx25821_buffer, vb.stream); 185 struct cx25821_buffer, vb.stream);
182 } else { 186 } else {
183 /* read() capture */ 187 /* read() capture */
184 buf = (struct cx25821_buffer *)fh->vidq.read_buf; 188 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
185 if (NULL == buf) 189 if (NULL == buf)
186 return POLLERR; 190 return POLLERR;
187 } 191 }
188
189 poll_wait(file, &buf->vb.done, wait);
190 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
191 return POLLIN|POLLRDNORM;
192 return 0;
193}
194 192
193 poll_wait(file, &buf->vb.done, wait);
194 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR)
195 return POLLIN | POLLRDNORM;
196 return 0;
197}
195 198
196static int video_release(struct file *file) 199static int video_release(struct file *file)
197{ 200{
198 struct cx25821_fh *fh = file->private_data; 201 struct cx25821_fh *fh = file->private_data;
199 struct cx25821_dev *dev = fh->dev; 202 struct cx25821_dev *dev = fh->dev;
200 203
201 //stop the risc engine and fifo 204 //stop the risc engine and fifo
202 //cx_write(channel9->dma_ctl, 0); 205 //cx_write(channel9->dma_ctl, 0);
203 206
204 /* stop video capture */ 207 /* stop video capture */
205 if (res_check(fh, RESOURCE_VIDEO9)) { 208 if (res_check(fh, RESOURCE_VIDEO9)) {
206 videobuf_queue_cancel(&fh->vidq); 209 videobuf_queue_cancel(&fh->vidq);
207 res_free(dev, fh, RESOURCE_VIDEO9); 210 res_free(dev, fh, RESOURCE_VIDEO9);
208 } 211 }
209 212
210 if (fh->vidq.read_buf) { 213 if (fh->vidq.read_buf) {
211 buffer_release(&fh->vidq, fh->vidq.read_buf); 214 buffer_release(&fh->vidq, fh->vidq.read_buf);
212 kfree(fh->vidq.read_buf); 215 kfree(fh->vidq.read_buf);
213 } 216 }
214 217
215 videobuf_mmap_free(&fh->vidq); 218 videobuf_mmap_free(&fh->vidq);
216 219
217 v4l2_prio_close(&dev->prio,&fh->prio); 220 v4l2_prio_close(&dev->prio, &fh->prio);
218 221
219 file->private_data = NULL; 222 file->private_data = NULL;
220 kfree(fh); 223 kfree(fh);
221 224
222 return 0; 225 return 0;
223} 226}
224 227
225
226static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) 228static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
227{ 229{
228 struct cx25821_fh *fh = priv; 230 struct cx25821_fh *fh = priv;
229 struct cx25821_dev *dev = fh->dev; 231 struct cx25821_dev *dev = fh->dev;
230 232
231 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 233 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
232 { 234 return -EINVAL;
233 return -EINVAL; 235 }
234 }
235 236
236 if (unlikely(i != fh->type)) 237 if (unlikely(i != fh->type)) {
237 { 238 return -EINVAL;
238 return -EINVAL; 239 }
239 }
240 240
241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO9)))) 241 if (unlikely(!res_get(dev, fh, get_resource(fh, RESOURCE_VIDEO9)))) {
242 { 242 return -EBUSY;
243 return -EBUSY; 243 }
244 }
245 244
246 return videobuf_streamon(get_queue(fh)); 245 return videobuf_streamon(get_queue(fh));
247} 246}
248 247
249static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) 248static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
250{ 249{
251 struct cx25821_fh *fh = priv; 250 struct cx25821_fh *fh = priv;
252 struct cx25821_dev *dev = fh->dev; 251 struct cx25821_dev *dev = fh->dev;
253 int err, res; 252 int err, res;
254 253
255 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 254 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
256 return -EINVAL; 255 return -EINVAL;
257 if (i != fh->type) 256 if (i != fh->type)
258 return -EINVAL; 257 return -EINVAL;
259 258
260 res = get_resource(fh, RESOURCE_VIDEO9); 259 res = get_resource(fh, RESOURCE_VIDEO9);
261 err = videobuf_streamoff(get_queue(fh)); 260 err = videobuf_streamoff(get_queue(fh));
262 if (err < 0) 261 if (err < 0)
263 return err; 262 return err;
264 res_free(dev, fh, res); 263 res_free(dev, fh, res);
265 return 0; 264 return 0;
266} 265}
267 266
268 267static long video_ioctl_upstream9(struct file *file, unsigned int cmd,
269static long video_ioctl_upstream9(struct file *file, unsigned int cmd, unsigned long arg) 268 unsigned long arg)
270{ 269{
271 struct cx25821_fh *fh = file->private_data; 270 struct cx25821_fh *fh = file->private_data;
272 struct cx25821_dev *dev = fh->dev; 271 struct cx25821_dev *dev = fh->dev;
273 int command = 0; 272 int command = 0;
274 struct upstream_user_struct *data_from_user; 273 struct upstream_user_struct *data_from_user;
275 274
276 275 data_from_user = (struct upstream_user_struct *)arg;
277 data_from_user = (struct upstream_user_struct *)arg; 276
278 277 if (!data_from_user) {
279 if( !data_from_user ) 278 printk
280 { 279 ("cx25821 in %s(): Upstream data is INVALID. Returning.\n",
281 printk("cx25821 in %s(): Upstream data is INVALID. Returning.\n", __func__); 280 __func__);
282 return 0; 281 return 0;
283 } 282 }
284
285 command = data_from_user->command;
286
287 if( command != UPSTREAM_START_VIDEO && command != UPSTREAM_STOP_VIDEO )
288 {
289 return 0;
290 }
291 283
284 command = data_from_user->command;
292 285
293 dev->input_filename = data_from_user->input_filename; 286 if (command != UPSTREAM_START_VIDEO && command != UPSTREAM_STOP_VIDEO) {
294 dev->input_audiofilename = data_from_user->input_filename; 287 return 0;
295 dev->vid_stdname = data_from_user->vid_stdname; 288 }
296 dev->pixel_format = data_from_user->pixel_format;
297 dev->channel_select = data_from_user->channel_select;
298 dev->command = data_from_user->command;
299 289
290 dev->input_filename = data_from_user->input_filename;
291 dev->input_audiofilename = data_from_user->input_filename;
292 dev->vid_stdname = data_from_user->vid_stdname;
293 dev->pixel_format = data_from_user->pixel_format;
294 dev->channel_select = data_from_user->channel_select;
295 dev->command = data_from_user->command;
300 296
301 switch(command) 297 switch (command) {
302 {
303 case UPSTREAM_START_VIDEO: 298 case UPSTREAM_START_VIDEO:
304 cx25821_start_upstream_video_ch1(dev, data_from_user); 299 cx25821_start_upstream_video_ch1(dev, data_from_user);
305 break; 300 break;
306 301
307 case UPSTREAM_STOP_VIDEO: 302 case UPSTREAM_STOP_VIDEO:
308 cx25821_stop_upstream_video_ch1(dev); 303 cx25821_stop_upstream_video_ch1(dev);
309 break; 304 break;
310 } 305 }
311 306
312 return 0; 307 return 0;
313} 308}
314 309
315 310static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
316static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) 311 struct v4l2_format *f)
317{ 312{
318 struct cx25821_fh *fh = priv; 313 struct cx25821_fh *fh = priv;
319 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 314 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
320 int err; 315 int err;
316
317 if (fh) {
318 err = v4l2_prio_check(&dev->prio, &fh->prio);
319 if (0 != err)
320 return err;
321 }
322
323 dprintk(2, "%s()\n", __func__);
324 err = vidioc_try_fmt_vid_cap(file, priv, f);
321 325
322 if (fh)
323 {
324 err = v4l2_prio_check(&dev->prio, &fh->prio);
325 if (0 != err) 326 if (0 != err)
326 return err; 327 return err;
327 } 328 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
328 329 fh->width = f->fmt.pix.width;
329 dprintk(2, "%s()\n", __func__); 330 fh->height = f->fmt.pix.height;
330 err = vidioc_try_fmt_vid_cap(file, priv, f); 331 fh->vidq.field = f->fmt.pix.field;
331 332 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width,
332 if (0 != err) 333 fh->height, fh->vidq.field);
333 return err; 334 cx25821_call_all(dev, video, s_fmt, f);
334 fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 335 return 0;
335 fh->width = f->fmt.pix.width;
336 fh->height = f->fmt.pix.height;
337 fh->vidq.field = f->fmt.pix.field;
338 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__, fh->width, fh->height, fh->vidq.field);
339 cx25821_call_all(dev, video, s_fmt, f);
340 return 0;
341} 336}
342 337
343static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) 338static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
344{ 339{
345 struct cx25821_fh *fh = priv; 340 struct cx25821_fh *fh = priv;
346 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK); 341 return videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
347} 342}
348static int vidioc_log_status (struct file *file, void *priv) 343static int vidioc_log_status(struct file *file, void *priv)
349{ 344{
350 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 345 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
351 char name[32 + 2]; 346 char name[32 + 2];
352 347
353 snprintf(name, sizeof(name), "%s/2", dev->name); 348 snprintf(name, sizeof(name), "%s/2", dev->name);
354 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n", 349 printk(KERN_INFO "%s/2: ============ START LOG STATUS ============\n",
355 dev->name); 350 dev->name);
356 cx25821_call_all(dev, core, log_status); 351 cx25821_call_all(dev, core, log_status);
357 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n", 352 printk(KERN_INFO "%s/2: ============= END LOG STATUS =============\n",
358 dev->name); 353 dev->name);
359 return 0; 354 return 0;
360} 355}
361 356
362static int vidioc_s_ctrl(struct file *file, void *priv, 357static int vidioc_s_ctrl(struct file *file, void *priv,
363 struct v4l2_control *ctl) 358 struct v4l2_control *ctl)
364{ 359{
365 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev; 360 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
366 struct cx25821_fh *fh = priv; 361 struct cx25821_fh *fh = priv;
367 int err; 362 int err;
368 if (fh) 363 if (fh) {
369 { 364 err = v4l2_prio_check(&dev->prio, &fh->prio);
370 err = v4l2_prio_check(&dev->prio, &fh->prio); 365 if (0 != err)
371 if (0 != err) 366 return err;
372 return err; 367 }
373 }
374 368
375 return 0; 369 return 0;
376} 370}
371
377// exported stuff 372// exported stuff
378static const struct v4l2_file_operations video_fops = { 373static const struct v4l2_file_operations video_fops = {
379 .owner = THIS_MODULE, 374 .owner = THIS_MODULE,
380 .open = video_open, 375 .open = video_open,
381 .release = video_release, 376 .release = video_release,
382 .read = video_read, 377 .read = video_read,
383 .poll = video_poll, 378 .poll = video_poll,
384 .mmap = video_mmap, 379 .mmap = video_mmap,
385 .ioctl = video_ioctl_upstream9, 380 .ioctl = video_ioctl_upstream9,
386}; 381};
387 382
388static const struct v4l2_ioctl_ops video_ioctl_ops = { 383static const struct v4l2_ioctl_ops video_ioctl_ops = {
389 .vidioc_querycap = vidioc_querycap, 384 .vidioc_querycap = vidioc_querycap,
390 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 385 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
391 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 386 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
392 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 387 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
393 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 388 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
394 .vidioc_reqbufs = vidioc_reqbufs, 389 .vidioc_reqbufs = vidioc_reqbufs,
395 .vidioc_querybuf = vidioc_querybuf, 390 .vidioc_querybuf = vidioc_querybuf,
396 .vidioc_qbuf = vidioc_qbuf, 391 .vidioc_qbuf = vidioc_qbuf,
397 .vidioc_dqbuf = vidioc_dqbuf, 392 .vidioc_dqbuf = vidioc_dqbuf,
398#ifdef TUNER_FLAG 393#ifdef TUNER_FLAG
399 .vidioc_s_std = vidioc_s_std, 394 .vidioc_s_std = vidioc_s_std,
400 .vidioc_querystd = vidioc_querystd, 395 .vidioc_querystd = vidioc_querystd,
401#endif 396#endif
402 .vidioc_cropcap = vidioc_cropcap, 397 .vidioc_cropcap = vidioc_cropcap,
403 .vidioc_s_crop = vidioc_s_crop, 398 .vidioc_s_crop = vidioc_s_crop,
404 .vidioc_g_crop = vidioc_g_crop, 399 .vidioc_g_crop = vidioc_g_crop,
405 .vidioc_enum_input = vidioc_enum_input, 400 .vidioc_enum_input = vidioc_enum_input,
406 .vidioc_g_input = vidioc_g_input, 401 .vidioc_g_input = vidioc_g_input,
407 .vidioc_s_input = vidioc_s_input, 402 .vidioc_s_input = vidioc_s_input,
408 .vidioc_g_ctrl = vidioc_g_ctrl, 403 .vidioc_g_ctrl = vidioc_g_ctrl,
409 .vidioc_s_ctrl = vidioc_s_ctrl, 404 .vidioc_s_ctrl = vidioc_s_ctrl,
410 .vidioc_queryctrl = vidioc_queryctrl, 405 .vidioc_queryctrl = vidioc_queryctrl,
411 .vidioc_streamon = vidioc_streamon, 406 .vidioc_streamon = vidioc_streamon,
412 .vidioc_streamoff = vidioc_streamoff, 407 .vidioc_streamoff = vidioc_streamoff,
413 .vidioc_log_status = vidioc_log_status, 408 .vidioc_log_status = vidioc_log_status,
414 .vidioc_g_priority = vidioc_g_priority, 409 .vidioc_g_priority = vidioc_g_priority,
415 .vidioc_s_priority = vidioc_s_priority, 410 .vidioc_s_priority = vidioc_s_priority,
416#ifdef CONFIG_VIDEO_V4L1_COMPAT 411#ifdef CONFIG_VIDEO_V4L1_COMPAT
417 .vidiocgmbuf = vidiocgmbuf, 412 .vidiocgmbuf = vidiocgmbuf,
418#endif 413#endif
419#ifdef TUNER_FLAG 414#ifdef TUNER_FLAG
420 .vidioc_g_tuner = vidioc_g_tuner, 415 .vidioc_g_tuner = vidioc_g_tuner,
421 .vidioc_s_tuner = vidioc_s_tuner, 416 .vidioc_s_tuner = vidioc_s_tuner,
422 .vidioc_g_frequency = vidioc_g_frequency, 417 .vidioc_g_frequency = vidioc_g_frequency,
423 .vidioc_s_frequency = vidioc_s_frequency, 418 .vidioc_s_frequency = vidioc_s_frequency,
424#endif 419#endif
425#ifdef CONFIG_VIDEO_ADV_DEBUG 420#ifdef CONFIG_VIDEO_ADV_DEBUG
426 .vidioc_g_register = vidioc_g_register, 421 .vidioc_g_register = vidioc_g_register,
427 .vidioc_s_register = vidioc_s_register, 422 .vidioc_s_register = vidioc_s_register,
428#endif 423#endif
429}; 424};
430 425
431struct video_device cx25821_video_template9 = { 426struct video_device cx25821_video_template9 = {
432 .name = "cx25821-upstream9", 427 .name = "cx25821-upstream9",
433 .fops = &video_fops, 428 .fops = &video_fops,
434 .minor = -1, 429 .minor = -1,
435 .ioctl_ops = &video_ioctl_ops, 430 .ioctl_ops = &video_ioctl_ops,
436 .tvnorms = CX25821_NORMS, 431 .tvnorms = CX25821_NORMS,
437 .current_norm = V4L2_STD_NTSC_M, 432 .current_norm = V4L2_STD_NTSC_M,
438}; 433};
439
440
441
diff --git a/drivers/staging/cx25821/cx25821.h b/drivers/staging/cx25821/cx25821.h
index 94f16cec1f44..cf2286d83b6a 100644
--- a/drivers/staging/cx25821/cx25821.h
+++ b/drivers/staging/cx25821/cx25821.h
@@ -21,7 +21,6 @@
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */ 22 */
23 23
24
25#ifndef CX25821_H_ 24#ifndef CX25821_H_
26#define CX25821_H_ 25#define CX25821_H_
27 26
@@ -85,8 +84,7 @@
85#define RESOURCE_VIDEO11 2048 84#define RESOURCE_VIDEO11 2048
86#define RESOURCE_VIDEO_IOCTL 4096 85#define RESOURCE_VIDEO_IOCTL 4096
87 86
88 87#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
89#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
90 88
91#define UNKNOWN_BOARD 0 89#define UNKNOWN_BOARD 0
92#define CX25821_BOARD 1 90#define CX25821_BOARD 1
@@ -103,338 +101,336 @@
103#define VID_CHANNEL_NUM 8 101#define VID_CHANNEL_NUM 8
104 102
105struct cx25821_fmt { 103struct cx25821_fmt {
106 char *name; 104 char *name;
107 u32 fourcc; /* v4l2 format id */ 105 u32 fourcc; /* v4l2 format id */
108 int depth; 106 int depth;
109 int flags; 107 int flags;
110 u32 cxformat; 108 u32 cxformat;
111}; 109};
112 110
113struct cx25821_ctrl { 111struct cx25821_ctrl {
114 struct v4l2_queryctrl v; 112 struct v4l2_queryctrl v;
115 u32 off; 113 u32 off;
116 u32 reg; 114 u32 reg;
117 u32 mask; 115 u32 mask;
118 u32 shift; 116 u32 shift;
119}; 117};
120 118
121struct cx25821_tvnorm { 119struct cx25821_tvnorm {
122 char *name; 120 char *name;
123 v4l2_std_id id; 121 v4l2_std_id id;
124 u32 cxiformat; 122 u32 cxiformat;
125 u32 cxoformat; 123 u32 cxoformat;
126}; 124};
127 125
128struct cx25821_fh { 126struct cx25821_fh {
129 struct cx25821_dev *dev; 127 struct cx25821_dev *dev;
130 enum v4l2_buf_type type; 128 enum v4l2_buf_type type;
131 int radio; 129 int radio;
132 u32 resources; 130 u32 resources;
133 131
134 enum v4l2_priority prio; 132 enum v4l2_priority prio;
135 133
136 /* video overlay */ 134 /* video overlay */
137 struct v4l2_window win; 135 struct v4l2_window win;
138 struct v4l2_clip *clips; 136 struct v4l2_clip *clips;
139 unsigned int nclips; 137 unsigned int nclips;
140 138
141 /* video capture */ 139 /* video capture */
142 struct cx25821_fmt *fmt; 140 struct cx25821_fmt *fmt;
143 unsigned int width, height; 141 unsigned int width, height;
144 142
145 /* vbi capture */ 143 /* vbi capture */
146 struct videobuf_queue vidq; 144 struct videobuf_queue vidq;
147 struct videobuf_queue vbiq; 145 struct videobuf_queue vbiq;
148 146
149 /* H264 Encoder specifics ONLY */ 147 /* H264 Encoder specifics ONLY */
150 struct videobuf_queue mpegq; 148 struct videobuf_queue mpegq;
151 atomic_t v4l_reading; 149 atomic_t v4l_reading;
152}; 150};
153 151
154enum cx25821_itype { 152enum cx25821_itype {
155 CX25821_VMUX_COMPOSITE = 1, 153 CX25821_VMUX_COMPOSITE = 1,
156 CX25821_VMUX_SVIDEO, 154 CX25821_VMUX_SVIDEO,
157 CX25821_VMUX_DEBUG, 155 CX25821_VMUX_DEBUG,
158 CX25821_RADIO, 156 CX25821_RADIO,
159}; 157};
160 158
161enum cx25821_src_sel_type { 159enum cx25821_src_sel_type {
162 CX25821_SRC_SEL_EXT_656_VIDEO = 0, 160 CX25821_SRC_SEL_EXT_656_VIDEO = 0,
163 CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO 161 CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
164}; 162};
165 163
166/* buffer for one video frame */ 164/* buffer for one video frame */
167struct cx25821_buffer { 165struct cx25821_buffer {
168 /* common v4l buffer stuff -- must be first */ 166 /* common v4l buffer stuff -- must be first */
169 struct videobuf_buffer vb; 167 struct videobuf_buffer vb;
170 168
171 /* cx25821 specific */ 169 /* cx25821 specific */
172 unsigned int bpl; 170 unsigned int bpl;
173 struct btcx_riscmem risc; 171 struct btcx_riscmem risc;
174 struct cx25821_fmt *fmt; 172 struct cx25821_fmt *fmt;
175 u32 count; 173 u32 count;
176}; 174};
177 175
178struct cx25821_input { 176struct cx25821_input {
179 enum cx25821_itype type; 177 enum cx25821_itype type;
180 unsigned int vmux; 178 unsigned int vmux;
181 u32 gpio0, gpio1, gpio2, gpio3; 179 u32 gpio0, gpio1, gpio2, gpio3;
182}; 180};
183 181
184typedef enum { 182typedef enum {
185 CX25821_UNDEFINED = 0, 183 CX25821_UNDEFINED = 0,
186 CX25821_RAW, 184 CX25821_RAW,
187 CX25821_264 185 CX25821_264
188} port_t; 186} port_t;
189 187
190struct cx25821_board { 188struct cx25821_board {
191 char *name; 189 char *name;
192 port_t porta, portb, portc; 190 port_t porta, portb, portc;
193 unsigned int tuner_type; 191 unsigned int tuner_type;
194 unsigned int radio_type; 192 unsigned int radio_type;
195 unsigned char tuner_addr; 193 unsigned char tuner_addr;
196 unsigned char radio_addr; 194 unsigned char radio_addr;
197 195
198 u32 clk_freq; 196 u32 clk_freq;
199 struct cx25821_input input[2]; 197 struct cx25821_input input[2];
200}; 198};
201 199
202struct cx25821_subid { 200struct cx25821_subid {
203 u16 subvendor; 201 u16 subvendor;
204 u16 subdevice; 202 u16 subdevice;
205 u32 card; 203 u32 card;
206}; 204};
207 205
208struct cx25821_i2c { 206struct cx25821_i2c {
209 struct cx25821_dev *dev; 207 struct cx25821_dev *dev;
210 208
211 int nr; 209 int nr;
212 210
213 /* i2c i/o */ 211 /* i2c i/o */
214 struct i2c_adapter i2c_adap; 212 struct i2c_adapter i2c_adap;
215 struct i2c_algo_bit_data i2c_algo; 213 struct i2c_algo_bit_data i2c_algo;
216 struct i2c_client i2c_client; 214 struct i2c_client i2c_client;
217 u32 i2c_rc; 215 u32 i2c_rc;
218 216
219 /* cx25821 registers used for raw addess */ 217 /* cx25821 registers used for raw addess */
220 u32 i2c_period; 218 u32 i2c_period;
221 u32 reg_ctrl; 219 u32 reg_ctrl;
222 u32 reg_stat; 220 u32 reg_stat;
223 u32 reg_addr; 221 u32 reg_addr;
224 u32 reg_rdata; 222 u32 reg_rdata;
225 u32 reg_wdata; 223 u32 reg_wdata;
226}; 224};
227 225
228struct cx25821_dmaqueue { 226struct cx25821_dmaqueue {
229 struct list_head active; 227 struct list_head active;
230 struct list_head queued; 228 struct list_head queued;
231 struct timer_list timeout; 229 struct timer_list timeout;
232 struct btcx_riscmem stopper; 230 struct btcx_riscmem stopper;
233 u32 count; 231 u32 count;
234}; 232};
235 233
236struct cx25821_data { 234struct cx25821_data {
237 struct cx25821_dev *dev; 235 struct cx25821_dev *dev;
238 struct sram_channel *channel; 236 struct sram_channel *channel;
239}; 237};
240 238
241struct cx25821_dev { 239struct cx25821_dev {
242 struct list_head devlist; 240 struct list_head devlist;
243 atomic_t refcount; 241 atomic_t refcount;
244 struct v4l2_device v4l2_dev; 242 struct v4l2_device v4l2_dev;
245 243
246 struct v4l2_prio_state prio; 244 struct v4l2_prio_state prio;
247 245
248 /* pci stuff */ 246 /* pci stuff */
249 struct pci_dev *pci; 247 struct pci_dev *pci;
250 unsigned char pci_rev, pci_lat; 248 unsigned char pci_rev, pci_lat;
251 int pci_bus, pci_slot; 249 int pci_bus, pci_slot;
252 u32 base_io_addr; 250 u32 base_io_addr;
253 u32 __iomem *lmmio; 251 u32 __iomem *lmmio;
254 u8 __iomem *bmmio; 252 u8 __iomem *bmmio;
255 int pci_irqmask; 253 int pci_irqmask;
256 int hwrevision; 254 int hwrevision;
257 255
258 u32 clk_freq; 256 u32 clk_freq;
259 257
260 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ 258 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
261 struct cx25821_i2c i2c_bus[3]; 259 struct cx25821_i2c i2c_bus[3];
262 260
263 int nr; 261 int nr;
264 struct mutex lock; 262 struct mutex lock;
265 263
266 /* board details */ 264 /* board details */
267 unsigned int board; 265 unsigned int board;
268 char name[32]; 266 char name[32];
269 267
270 /* sram configuration */ 268 /* sram configuration */
271 struct sram_channel *sram_channels; 269 struct sram_channel *sram_channels;
272 270
273 /* Analog video */ 271 /* Analog video */
274 u32 resources; 272 u32 resources;
275 unsigned int input; 273 unsigned int input;
276 u32 tvaudio; 274 u32 tvaudio;
277 v4l2_std_id tvnorm; 275 v4l2_std_id tvnorm;
278 unsigned int tuner_type; 276 unsigned int tuner_type;
279 unsigned char tuner_addr; 277 unsigned char tuner_addr;
280 unsigned int radio_type; 278 unsigned int radio_type;
281 unsigned char radio_addr; 279 unsigned char radio_addr;
282 unsigned int has_radio; 280 unsigned int has_radio;
283 unsigned int videc_type; 281 unsigned int videc_type;
284 unsigned char videc_addr; 282 unsigned char videc_addr;
285 unsigned short _max_num_decoders; 283 unsigned short _max_num_decoders;
286 284
287 int ctl_bright; 285 int ctl_bright;
288 int ctl_contrast; 286 int ctl_contrast;
289 int ctl_hue; 287 int ctl_hue;
290 int ctl_saturation; 288 int ctl_saturation;
291 289
292 struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM]; 290 struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM];
293 291
294 /* Analog Audio Upstream */ 292 /* Analog Audio Upstream */
295 int _audio_is_running; 293 int _audio_is_running;
296 int _audiopixel_format; 294 int _audiopixel_format;
297 int _is_first_audio_frame; 295 int _is_first_audio_frame;
298 int _audiofile_status; 296 int _audiofile_status;
299 int _audio_lines_count; 297 int _audio_lines_count;
300 int _audioframe_count; 298 int _audioframe_count;
301 int _audio_upstream_channel_select; 299 int _audio_upstream_channel_select;
302 int _last_index_irq; //The last interrupt index processed. 300 int _last_index_irq; //The last interrupt index processed.
303 301
304 __le32 * _risc_audio_jmp_addr; 302 __le32 *_risc_audio_jmp_addr;
305 __le32 * _risc_virt_start_addr; 303 __le32 *_risc_virt_start_addr;
306 __le32 * _risc_virt_addr; 304 __le32 *_risc_virt_addr;
307 dma_addr_t _risc_phys_addr; 305 dma_addr_t _risc_phys_addr;
308 dma_addr_t _risc_phys_start_addr; 306 dma_addr_t _risc_phys_start_addr;
309 307
310 unsigned int _audiorisc_size; 308 unsigned int _audiorisc_size;
311 unsigned int _audiodata_buf_size; 309 unsigned int _audiodata_buf_size;
312 __le32 * _audiodata_buf_virt_addr; 310 __le32 *_audiodata_buf_virt_addr;
313 dma_addr_t _audiodata_buf_phys_addr; 311 dma_addr_t _audiodata_buf_phys_addr;
314 char *_audiofilename; 312 char *_audiofilename;
315 313
316 /* V4l */ 314 /* V4l */
317 u32 freq; 315 u32 freq;
318 struct video_device *video_dev[MAX_VID_CHANNEL_NUM]; 316 struct video_device *video_dev[MAX_VID_CHANNEL_NUM];
319 struct video_device *vbi_dev; 317 struct video_device *vbi_dev;
320 struct video_device *radio_dev; 318 struct video_device *radio_dev;
321 struct video_device *ioctl_dev; 319 struct video_device *ioctl_dev;
322 320
323 struct cx25821_dmaqueue vidq[MAX_VID_CHANNEL_NUM]; 321 struct cx25821_dmaqueue vidq[MAX_VID_CHANNEL_NUM];
324 spinlock_t slock; 322 spinlock_t slock;
325 323
326 /* Video Upstream */ 324 /* Video Upstream */
327 int _line_size; 325 int _line_size;
328 int _prog_cnt; 326 int _prog_cnt;
329 int _pixel_format; 327 int _pixel_format;
330 int _is_first_frame; 328 int _is_first_frame;
331 int _is_running; 329 int _is_running;
332 int _file_status; 330 int _file_status;
333 int _lines_count; 331 int _lines_count;
334 int _frame_count; 332 int _frame_count;
335 int _channel_upstream_select; 333 int _channel_upstream_select;
336 unsigned int _risc_size; 334 unsigned int _risc_size;
337 335
338 __le32 * _dma_virt_start_addr; 336 __le32 *_dma_virt_start_addr;
339 __le32 * _dma_virt_addr; 337 __le32 *_dma_virt_addr;
340 dma_addr_t _dma_phys_addr; 338 dma_addr_t _dma_phys_addr;
341 dma_addr_t _dma_phys_start_addr; 339 dma_addr_t _dma_phys_start_addr;
342 340
343 unsigned int _data_buf_size; 341 unsigned int _data_buf_size;
344 __le32 * _data_buf_virt_addr; 342 __le32 *_data_buf_virt_addr;
345 dma_addr_t _data_buf_phys_addr; 343 dma_addr_t _data_buf_phys_addr;
346 char * _filename; 344 char *_filename;
347 char * _defaultname; 345 char *_defaultname;
348 346
349 347 int _line_size_ch2;
350 int _line_size_ch2; 348 int _prog_cnt_ch2;
351 int _prog_cnt_ch2; 349 int _pixel_format_ch2;
352 int _pixel_format_ch2; 350 int _is_first_frame_ch2;
353 int _is_first_frame_ch2; 351 int _is_running_ch2;
354 int _is_running_ch2; 352 int _file_status_ch2;
355 int _file_status_ch2; 353 int _lines_count_ch2;
356 int _lines_count_ch2; 354 int _frame_count_ch2;
357 int _frame_count_ch2; 355 int _channel2_upstream_select;
358 int _channel2_upstream_select; 356 unsigned int _risc_size_ch2;
359 unsigned int _risc_size_ch2; 357
360 358 __le32 *_dma_virt_start_addr_ch2;
361 __le32 * _dma_virt_start_addr_ch2; 359 __le32 *_dma_virt_addr_ch2;
362 __le32 * _dma_virt_addr_ch2; 360 dma_addr_t _dma_phys_addr_ch2;
363 dma_addr_t _dma_phys_addr_ch2; 361 dma_addr_t _dma_phys_start_addr_ch2;
364 dma_addr_t _dma_phys_start_addr_ch2; 362
365 363 unsigned int _data_buf_size_ch2;
366 unsigned int _data_buf_size_ch2; 364 __le32 *_data_buf_virt_addr_ch2;
367 __le32 * _data_buf_virt_addr_ch2; 365 dma_addr_t _data_buf_phys_addr_ch2;
368 dma_addr_t _data_buf_phys_addr_ch2; 366 char *_filename_ch2;
369 char * _filename_ch2; 367 char *_defaultname_ch2;
370 char * _defaultname_ch2; 368
371 369 /* MPEG Encoder ONLY settings */
372 /* MPEG Encoder ONLY settings */ 370 u32 cx23417_mailbox;
373 u32 cx23417_mailbox; 371 struct cx2341x_mpeg_params mpeg_params;
374 struct cx2341x_mpeg_params mpeg_params; 372 struct video_device *v4l_device;
375 struct video_device *v4l_device; 373 atomic_t v4l_reader_count;
376 atomic_t v4l_reader_count; 374 struct cx25821_tvnorm encodernorm;
377 struct cx25821_tvnorm encodernorm; 375
378 376 u32 upstream_riscbuf_size;
379 u32 upstream_riscbuf_size; 377 u32 upstream_databuf_size;
380 u32 upstream_databuf_size; 378 u32 upstream_riscbuf_size_ch2;
381 u32 upstream_riscbuf_size_ch2; 379 u32 upstream_databuf_size_ch2;
382 u32 upstream_databuf_size_ch2; 380 u32 audio_upstream_riscbuf_size;
383 u32 audio_upstream_riscbuf_size; 381 u32 audio_upstream_databuf_size;
384 u32 audio_upstream_databuf_size; 382 int _isNTSC;
385 int _isNTSC; 383 int _frame_index;
386 int _frame_index; 384 int _audioframe_index;
387 int _audioframe_index; 385 struct workqueue_struct *_irq_queues;
388 struct workqueue_struct * _irq_queues; 386 struct work_struct _irq_work_entry;
389 struct work_struct _irq_work_entry; 387 struct workqueue_struct *_irq_queues_ch2;
390 struct workqueue_struct * _irq_queues_ch2; 388 struct work_struct _irq_work_entry_ch2;
391 struct work_struct _irq_work_entry_ch2; 389 struct workqueue_struct *_irq_audio_queues;
392 struct workqueue_struct * _irq_audio_queues; 390 struct work_struct _audio_work_entry;
393 struct work_struct _audio_work_entry; 391 char *input_filename;
394 char *input_filename; 392 char *input_filename_ch2;
395 char *input_filename_ch2; 393 int _frame_index_ch2;
396 int _frame_index_ch2; 394 int _isNTSC_ch2;
397 int _isNTSC_ch2; 395 char *vid_stdname_ch2;
398 char *vid_stdname_ch2; 396 int pixel_format_ch2;
399 int pixel_format_ch2; 397 int channel_select_ch2;
400 int channel_select_ch2; 398 int command_ch2;
401 int command_ch2; 399 char *input_audiofilename;
402 char *input_audiofilename; 400 char *vid_stdname;
403 char *vid_stdname; 401 int pixel_format;
404 int pixel_format; 402 int channel_select;
405 int channel_select; 403 int command;
406 int command; 404 int pixel_formats[VID_CHANNEL_NUM];
407 int pixel_formats[VID_CHANNEL_NUM]; 405 int use_cif_resolution[VID_CHANNEL_NUM];
408 int use_cif_resolution[VID_CHANNEL_NUM]; 406 int cif_width[VID_CHANNEL_NUM];
409 int cif_width[VID_CHANNEL_NUM]; 407 int channel_opened;
410 int channel_opened;
411}; 408};
412 409
413
414struct upstream_user_struct { 410struct upstream_user_struct {
415 char *input_filename; 411 char *input_filename;
416 char *vid_stdname; 412 char *vid_stdname;
417 int pixel_format; 413 int pixel_format;
418 int channel_select; 414 int channel_select;
419 int command; 415 int command;
420}; 416};
421 417
422struct downstream_user_struct { 418struct downstream_user_struct {
423 char *vid_stdname; 419 char *vid_stdname;
424 int pixel_format; 420 int pixel_format;
425 int cif_resolution_enable; 421 int cif_resolution_enable;
426 int cif_width; 422 int cif_width;
427 int decoder_select; 423 int decoder_select;
428 int command; 424 int command;
429 int reg_address; 425 int reg_address;
430 int reg_data; 426 int reg_data;
431}; 427};
432 428
433extern struct upstream_user_struct *up_data; 429extern struct upstream_user_struct *up_data;
434 430
435static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev) 431static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
436{ 432{
437 return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev); 433 return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
438} 434}
439 435
440#define cx25821_call_all(dev, o, f, args...) \ 436#define cx25821_call_all(dev, o, f, args...) \
@@ -444,21 +440,19 @@ extern struct list_head cx25821_devlist;
444extern struct cx25821_board cx25821_boards[]; 440extern struct cx25821_board cx25821_boards[];
445extern struct cx25821_subid cx25821_subids[]; 441extern struct cx25821_subid cx25821_subids[];
446 442
447#define SRAM_CH00 0 /* Video A */ 443#define SRAM_CH00 0 /* Video A */
448#define SRAM_CH01 1 /* Video B */ 444#define SRAM_CH01 1 /* Video B */
449#define SRAM_CH02 2 /* Video C */ 445#define SRAM_CH02 2 /* Video C */
450#define SRAM_CH03 3 /* Video D */ 446#define SRAM_CH03 3 /* Video D */
451#define SRAM_CH04 4 /* Video E */ 447#define SRAM_CH04 4 /* Video E */
452#define SRAM_CH05 5 /* Video F */ 448#define SRAM_CH05 5 /* Video F */
453#define SRAM_CH06 6 /* Video G */ 449#define SRAM_CH06 6 /* Video G */
454#define SRAM_CH07 7 /* Video H */ 450#define SRAM_CH07 7 /* Video H */
455
456#define SRAM_CH08 8 /* Audio A */
457#define SRAM_CH09 9 /* Video Upstream I */
458#define SRAM_CH10 10 /* Video Upstream J */
459#define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
460
461 451
452#define SRAM_CH08 8 /* Audio A */
453#define SRAM_CH09 9 /* Video Upstream I */
454#define SRAM_CH10 10 /* Video Upstream J */
455#define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
462 456
463#define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09 457#define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09
464#define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10 458#define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10
@@ -466,38 +460,38 @@ extern struct cx25821_subid cx25821_subids[];
466#define VIDEO_IOCTL_CH 11 460#define VIDEO_IOCTL_CH 11
467 461
468struct sram_channel { 462struct sram_channel {
469 char *name; 463 char *name;
470 u32 i; 464 u32 i;
471 u32 cmds_start; 465 u32 cmds_start;
472 u32 ctrl_start; 466 u32 ctrl_start;
473 u32 cdt; 467 u32 cdt;
474 u32 fifo_start; 468 u32 fifo_start;
475 u32 fifo_size; 469 u32 fifo_size;
476 u32 ptr1_reg; 470 u32 ptr1_reg;
477 u32 ptr2_reg; 471 u32 ptr2_reg;
478 u32 cnt1_reg; 472 u32 cnt1_reg;
479 u32 cnt2_reg; 473 u32 cnt2_reg;
480 u32 int_msk; 474 u32 int_msk;
481 u32 int_stat; 475 u32 int_stat;
482 u32 int_mstat; 476 u32 int_mstat;
483 u32 dma_ctl; 477 u32 dma_ctl;
484 u32 gpcnt_ctl; 478 u32 gpcnt_ctl;
485 u32 gpcnt; 479 u32 gpcnt;
486 u32 aud_length; 480 u32 aud_length;
487 u32 aud_cfg; 481 u32 aud_cfg;
488 u32 fld_aud_fifo_en; 482 u32 fld_aud_fifo_en;
489 u32 fld_aud_risc_en; 483 u32 fld_aud_risc_en;
490 484
491 //For Upstream Video 485 //For Upstream Video
492 u32 vid_fmt_ctl; 486 u32 vid_fmt_ctl;
493 u32 vid_active_ctl1; 487 u32 vid_active_ctl1;
494 u32 vid_active_ctl2; 488 u32 vid_active_ctl2;
495 u32 vid_cdt_size; 489 u32 vid_cdt_size;
496 490
497 u32 vip_ctl; 491 u32 vip_ctl;
498 u32 pix_frmt; 492 u32 pix_frmt;
499 u32 jumponly; 493 u32 jumponly;
500 u32 irq_bit; 494 u32 irq_bit;
501}; 495};
502extern struct sram_channel cx25821_sram_channels[]; 496extern struct sram_channel cx25821_sram_channels[];
503 497
@@ -521,70 +515,88 @@ extern struct sram_channel cx25821_sram_channels[];
521#define CX25821_WARN(fmt, args...) printk(KERN_WARNING "cx25821(%d): " fmt, dev->board , ## args) 515#define CX25821_WARN(fmt, args...) printk(KERN_WARNING "cx25821(%d): " fmt, dev->board , ## args)
522#define CX25821_INFO(fmt, args...) printk(KERN_INFO "cx25821(%d): " fmt, dev->board , ## args) 516#define CX25821_INFO(fmt, args...) printk(KERN_INFO "cx25821(%d): " fmt, dev->board , ## args)
523 517
524extern int cx25821_i2c_register(struct cx25821_i2c *bus); 518extern int cx25821_i2c_register(struct cx25821_i2c *bus);
525extern void cx25821_card_setup(struct cx25821_dev *dev); 519extern void cx25821_card_setup(struct cx25821_dev *dev);
526extern int cx25821_ir_init(struct cx25821_dev *dev); 520extern int cx25821_ir_init(struct cx25821_dev *dev);
527extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value); 521extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
528extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value); 522extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
529extern int cx25821_i2c_unregister(struct cx25821_i2c *bus); 523extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
530extern void cx25821_gpio_init(struct cx25821_dev *dev); 524extern void cx25821_gpio_init(struct cx25821_dev *dev);
531extern void cx25821_set_gpiopin_direction( struct cx25821_dev *dev, 525extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
532 int pin_number, 526 int pin_number, int pin_logic_value);
533 int pin_logic_value); 527
534 528extern int medusa_video_init(struct cx25821_dev *dev);
535extern int medusa_video_init(struct cx25821_dev *dev); 529extern int medusa_set_videostandard(struct cx25821_dev *dev);
536extern int medusa_set_videostandard(struct cx25821_dev *dev); 530extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
537extern void medusa_set_resolution(struct cx25821_dev *dev, int width, int decoder_select); 531 int decoder_select);
538extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder); 532extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
539extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder); 533 int decoder);
540extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder); 534extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
541extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder); 535 int decoder);
542 536extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
543extern int cx25821_sram_channel_setup(struct cx25821_dev *dev, struct sram_channel *ch, unsigned int bpl, u32 risc); 537extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
538 int decoder);
539
540extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
541 struct sram_channel *ch, unsigned int bpl,
542 u32 risc);
544 543
545extern int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, 544extern int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
546 struct scatterlist *sglist, 545 struct scatterlist *sglist,
547 unsigned int top_offset, 546 unsigned int top_offset,
548 unsigned int bottom_offset, 547 unsigned int bottom_offset,
549 unsigned int bpl, 548 unsigned int bpl,
550 unsigned int padding, 549 unsigned int padding, unsigned int lines);
551 unsigned int lines);
552extern int cx25821_risc_databuffer_audio(struct pci_dev *pci, 550extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
553 struct btcx_riscmem *risc, 551 struct btcx_riscmem *risc,
554 struct scatterlist *sglist, 552 struct scatterlist *sglist,
555 unsigned int bpl, 553 unsigned int bpl,
556 unsigned int lines, 554 unsigned int lines, unsigned int lpi);
557 unsigned int lpi); 555extern void cx25821_free_buffer(struct videobuf_queue *q,
558extern void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf); 556 struct cx25821_buffer *buf);
559extern int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,u32 reg, u32 mask, u32 value); 557extern int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
560extern void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch); 558 u32 reg, u32 mask, u32 value);
561extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, struct sram_channel *ch); 559extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
562 560 struct sram_channel *ch);
563 561extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
564extern struct cx25821_dev* cx25821_dev_get(struct pci_dev *pci); 562 struct sram_channel *ch);
565extern void cx25821_print_irqbits(char *name, char *tag, char **strings, int len, u32 bits, u32 mask); 563
564extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
565extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
566 int len, u32 bits, u32 mask);
566extern void cx25821_dev_unregister(struct cx25821_dev *dev); 567extern void cx25821_dev_unregister(struct cx25821_dev *dev);
567extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, 568extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
568 struct sram_channel *ch, 569 struct sram_channel *ch,
569 unsigned int bpl, u32 risc); 570 unsigned int bpl, u32 risc);
570 571
571extern int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select, int pixel_format); 572extern int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev,
572extern int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select, int pixel_format); 573 int channel_select, int pixel_format);
573extern int cx25821_audio_upstream_init(struct cx25821_dev *dev, int channel_select); 574extern int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev,
575 int channel_select, int pixel_format);
576extern int cx25821_audio_upstream_init(struct cx25821_dev *dev,
577 int channel_select);
574extern void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev); 578extern void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev);
575extern void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev); 579extern void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev);
576extern void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev); 580extern void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev);
577extern void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev, struct upstream_user_struct *up_data); 581extern void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
578extern void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev, struct upstream_user_struct *up_data); 582 struct upstream_user_struct
579extern void cx25821_start_upstream_audio(struct cx25821_dev *dev, struct upstream_user_struct *up_data); 583 *up_data);
584extern void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
585 struct upstream_user_struct
586 *up_data);
587extern void cx25821_start_upstream_audio(struct cx25821_dev *dev,
588 struct upstream_user_struct *up_data);
580extern void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev); 589extern void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev);
581extern void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev); 590extern void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev);
582extern void cx25821_stop_upstream_audio(struct cx25821_dev *dev); 591extern void cx25821_stop_upstream_audio(struct cx25821_dev *dev);
583extern int cx25821_sram_channel_setup_upstream( struct cx25821_dev *dev, struct sram_channel *ch, unsigned int bpl, u32 risc); 592extern int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
584extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel, u32 format); 593 struct sram_channel *ch,
594 unsigned int bpl, u32 risc);
595extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
596 u32 format);
585extern void cx25821_videoioctl_unregister(struct cx25821_dev *dev); 597extern void cx25821_videoioctl_unregister(struct cx25821_dev *dev);
586extern struct video_device *cx25821_vdev_init(struct cx25821_dev *dev, 598extern struct video_device *cx25821_vdev_init(struct cx25821_dev *dev,
587 struct pci_dev *pci, 599 struct pci_dev *pci,
588 struct video_device *template, 600 struct video_device *template,
589 char *type); 601 char *type);
590#endif 602#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 10:04:40 -0500