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authorAndy Gospodarek <andy@greyhouse.net>2007-09-17 21:50:36 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:51:34 -0400
commit1a348ccc1047a00507e554826775a3d81f7f3437 (patch)
treedf2a7cd4ee403dbb60705a5988c97a721f7eb2a0 /drivers
parent1202d6ff356cc66dc8d2b85546eb4f187f9e1f25 (diff)
[NET]: Add Tehuti network driver.
[ Ported to napi_struct changes... -DaveM ] Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/Kconfig6
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/tehuti.c2508
-rw-r--r--drivers/net/tehuti.h564
-rw-r--r--drivers/net/tehuti_fw.h10712
5 files changed, 13791 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 63ab05b5a87a..fd284a93c9dd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2661,6 +2661,12 @@ config MLX4_DEBUG
2661 debug_level module parameter (which can also be set after 2661 debug_level module parameter (which can also be set after
2662 the driver is loaded through sysfs). 2662 the driver is loaded through sysfs).
2663 2663
2664config TEHUTI
2665 tristate "Tehuti Networks 10G Ethernet"
2666 depends on PCI
2667 help
2668 Tehuti Networks 10G Ethernet NIC
2669
2664endif # NETDEV_10000 2670endif # NETDEV_10000
2665 2671
2666source "drivers/net/tokenring/Kconfig" 2672source "drivers/net/tokenring/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2098647080a0..2ab33e8b9159 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_EHEA) += ehea/
14obj-$(CONFIG_BONDING) += bonding/ 14obj-$(CONFIG_BONDING) += bonding/
15obj-$(CONFIG_ATL1) += atl1/ 15obj-$(CONFIG_ATL1) += atl1/
16obj-$(CONFIG_GIANFAR) += gianfar_driver.o 16obj-$(CONFIG_GIANFAR) += gianfar_driver.o
17obj-$(CONFIG_TEHUTI) += tehuti.o
17 18
18gianfar_driver-objs := gianfar.o \ 19gianfar_driver-objs := gianfar.o \
19 gianfar_ethtool.o \ 20 gianfar_ethtool.o \
diff --git a/drivers/net/tehuti.c b/drivers/net/tehuti.c
new file mode 100644
index 000000000000..248343177356
--- /dev/null
+++ b/drivers/net/tehuti.c
@@ -0,0 +1,2508 @@
1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
65#include "tehuti.h"
66#include "tehuti_fw.h"
67
68static struct pci_device_id __devinitdata bdx_pci_tbl[] = {
69 {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
70 {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {0}
73};
74
75MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
76
77/* Definitions needed by ISR or NAPI functions */
78static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
79static void bdx_tx_cleanup(struct bdx_priv *priv);
80static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
81
82/* Definitions needed by FW loading */
83static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
84
85/* Definitions needed by hw_start */
86static int bdx_tx_init(struct bdx_priv *priv);
87static int bdx_rx_init(struct bdx_priv *priv);
88
89/* Definitions needed by bdx_close */
90static void bdx_rx_free(struct bdx_priv *priv);
91static void bdx_tx_free(struct bdx_priv *priv);
92
93/* Definitions needed by bdx_probe */
94static void bdx_ethtool_ops(struct net_device *netdev);
95
96/*************************************************************************
97 * Print Info *
98 *************************************************************************/
99
100static void print_hw_id(struct pci_dev *pdev)
101{
102 struct pci_nic *nic = pci_get_drvdata(pdev);
103 u16 pci_link_status = 0;
104 u16 pci_ctrl = 0;
105
106 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
107 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
108
109 printk(KERN_INFO "tehuti: %s%s\n", BDX_NIC_NAME,
110 nic->port_num == 1 ? "" : ", 2-Port");
111 printk(KERN_INFO
112 "tehuti: srom 0x%x fpga %d build %u lane# %d"
113 " max_pl 0x%x mrrs 0x%x\n",
114 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
115 readl(nic->regs + FPGA_SEED),
116 GET_LINK_STATUS_LANES(pci_link_status),
117 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
118}
119
120static void print_fw_id(struct pci_nic *nic)
121{
122 printk(KERN_INFO "tehuti: fw 0x%x\n", readl(nic->regs + FW_VER));
123}
124
125static void print_eth_id(struct net_device *ndev)
126{
127 printk(KERN_INFO "%s: %s, Port %c\n", ndev->name, BDX_NIC_NAME,
128 (ndev->if_port == 0) ? 'A' : 'B');
129
130}
131
132/*************************************************************************
133 * Code *
134 *************************************************************************/
135
136#define bdx_enable_interrupts(priv) \
137 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
138#define bdx_disable_interrupts(priv) \
139 do { WRITE_REG(priv, regIMR, 0); } while (0)
140
141/* bdx_fifo_init
142 * create TX/RX descriptor fifo for host-NIC communication.
143 * 1K extra space is allocated at the end of the fifo to simplify
144 * processing of descriptors that wraps around fifo's end
145 * @priv - NIC private structure
146 * @f - fifo to initialize
147 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
148 * @reg_XXX - offsets of registers relative to base address
149 *
150 * Returns 0 on success, negative value on failure
151 *
152 */
153static int
154bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
155 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
156{
157 u16 memsz = FIFO_SIZE * (1 << fsz_type);
158
159 memset(f, 0, sizeof(struct fifo));
160 /* pci_alloc_consistent gives us 4k-aligned memory */
161 f->va = pci_alloc_consistent(priv->pdev,
162 memsz + FIFO_EXTRA_SPACE, &f->da);
163 if (!f->va) {
164 ERR("pci_alloc_consistent failed\n");
165 RET(-ENOMEM);
166 }
167 f->reg_CFG0 = reg_CFG0;
168 f->reg_CFG1 = reg_CFG1;
169 f->reg_RPTR = reg_RPTR;
170 f->reg_WPTR = reg_WPTR;
171 f->rptr = 0;
172 f->wptr = 0;
173 f->memsz = memsz;
174 f->size_mask = memsz - 1;
175 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
176 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
177
178 RET(0);
179}
180
181/* bdx_fifo_free - free all resources used by fifo
182 * @priv - NIC private structure
183 * @f - fifo to release
184 */
185static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
186{
187 ENTER;
188 if (f->va) {
189 pci_free_consistent(priv->pdev,
190 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
191 f->va = NULL;
192 }
193 RET();
194}
195
196/*
197 * bdx_link_changed - notifies OS about hw link state.
198 * @bdx_priv - hw adapter structure
199 */
200static void bdx_link_changed(struct bdx_priv *priv)
201{
202 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
203
204 if (!link) {
205 if (netif_carrier_ok(priv->ndev)) {
206 netif_stop_queue(priv->ndev);
207 netif_carrier_off(priv->ndev);
208 ERR("%s: Link Down\n", priv->ndev->name);
209 }
210 } else {
211 if (!netif_carrier_ok(priv->ndev)) {
212 netif_wake_queue(priv->ndev);
213 netif_carrier_on(priv->ndev);
214 ERR("%s: Link Up\n", priv->ndev->name);
215 }
216 }
217}
218
219static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
220{
221 if (isr & IR_RX_FREE_0) {
222 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
223 DBG("RX_FREE_0\n");
224 }
225
226 if (isr & IR_LNKCHG0)
227 bdx_link_changed(priv);
228
229 if (isr & IR_PCIE_LINK)
230 ERR("%s: PCI-E Link Fault\n", priv->ndev->name);
231
232 if (isr & IR_PCIE_TOUT)
233 ERR("%s: PCI-E Time Out\n", priv->ndev->name);
234
235}
236
237/* bdx_isr - Interrupt Service Routine for Bordeaux NIC
238 * @irq - interrupt number
239 * @ndev - network device
240 * @regs - CPU registers
241 *
242 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
243 *
244 * It reads ISR register to know interrupt reasons, and proceed them one by one.
245 * Reasons of interest are:
246 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
247 * RX_FREE - number of free Rx buffers in RXF fifo gets low
248 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
249 */
250
251static irqreturn_t bdx_isr_napi(int irq, void *dev)
252{
253 struct net_device *ndev = dev;
254 struct bdx_priv *priv = ndev->priv;
255 u32 isr;
256
257 ENTER;
258 isr = (READ_REG(priv, regISR) & IR_RUN);
259 if (unlikely(!isr)) {
260 bdx_enable_interrupts(priv);
261 return IRQ_NONE; /* Not our interrupt */
262 }
263
264 if (isr & IR_EXTRA)
265 bdx_isr_extra(priv, isr);
266
267 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
268 if (likely(netif_rx_schedule_prep(ndev, &priv->napi))) {
269 __netif_rx_schedule(ndev, &priv->napi);
270 RET(IRQ_HANDLED);
271 } else {
272 /* NOTE: we get here if intr has slipped into window
273 * between these lines in bdx_poll:
274 * bdx_enable_interrupts(priv);
275 * return 0;
276 * currently intrs are disabled (since we read ISR),
277 * and we have failed to register next poll.
278 * so we read the regs to trigger chip
279 * and allow further interupts. */
280 READ_REG(priv, regTXF_WPTR_0);
281 READ_REG(priv, regRXD_WPTR_0);
282 }
283 }
284
285 bdx_enable_interrupts(priv);
286 RET(IRQ_HANDLED);
287}
288
289static int bdx_poll(struct napi_struct *napi, int budget)
290{
291 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
292 struct net_device *dev = priv->ndev;
293 int work_done;
294
295 ENTER;
296 bdx_tx_cleanup(priv);
297 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
298 if ((work_done < budget) ||
299 (priv->napi_stop++ >= 30)) {
300 DBG("rx poll is done. backing to isr-driven\n");
301
302 /* from time to time we exit to let NAPI layer release
303 * device lock and allow waiting tasks (eg rmmod) to advance) */
304 priv->napi_stop = 0;
305
306 netif_rx_complete(dev, napi);
307 bdx_enable_interrupts(priv);
308 }
309 return work_done;
310}
311
312/* bdx_fw_load - loads firmware to NIC
313 * @priv - NIC private structure
314 * Firmware is loaded via TXD fifo, so it must be initialized first.
315 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
316 * can have few of them). So all drivers use semaphore register to choose one
317 * that will actually load FW to NIC.
318 */
319
320static int bdx_fw_load(struct bdx_priv *priv)
321{
322 int master, i;
323
324 ENTER;
325 master = READ_REG(priv, regINIT_SEMAPHORE);
326 if (!READ_REG(priv, regINIT_STATUS) && master) {
327 bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad));
328 mdelay(100);
329 }
330 for (i = 0; i < 200; i++) {
331 if (READ_REG(priv, regINIT_STATUS))
332 break;
333 mdelay(2);
334 }
335 if (master)
336 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
337
338 if (i == 200) {
339 ERR("%s: firmware loading failed\n", priv->ndev->name);
340 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
341 READ_REG(priv, regVPC),
342 READ_REG(priv, regVIC), READ_REG(priv, regINIT_STATUS), i);
343 RET(-EIO);
344 } else {
345 DBG("%s: firmware loading success\n", priv->ndev->name);
346 RET(0);
347 }
348}
349
350static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
351{
352 u32 val;
353
354 ENTER;
355 DBG("mac0=%x mac1=%x mac2=%x\n",
356 READ_REG(priv, regUNC_MAC0_A),
357 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
358
359 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
360 WRITE_REG(priv, regUNC_MAC2_A, val);
361 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
362 WRITE_REG(priv, regUNC_MAC1_A, val);
363 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
364 WRITE_REG(priv, regUNC_MAC0_A, val);
365
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv, regUNC_MAC0_A),
368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
369 RET();
370}
371
372/* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
373 * @priv - NIC private structure
374 */
375static int bdx_hw_start(struct bdx_priv *priv)
376{
377 int rc = -EIO;
378 struct net_device *ndev = priv->ndev;
379
380 ENTER;
381 bdx_link_changed(priv);
382
383 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
384 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
385 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
386 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
387 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
388 WRITE_REG(priv, regRX_FULLNESS, 0);
389 WRITE_REG(priv, regTX_FULLNESS, 0);
390 WRITE_REG(priv, regCTRLST,
391 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
392
393 WRITE_REG(priv, regVGLB, 0);
394 WRITE_REG(priv, regMAX_FRAME_A,
395 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
396
397 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
398 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
399 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
400
401 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
402 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
403
404 /* Enable timer interrupt once in 2 secs. */
405 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
406 bdx_restore_mac(priv->ndev, priv);
407
408 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
409 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
410
411#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED)
412 if ((rc = request_irq(priv->pdev->irq, &bdx_isr_napi, BDX_IRQ_TYPE,
413 ndev->name, ndev)))
414 goto err_irq;
415 bdx_enable_interrupts(priv);
416
417 RET(0);
418
419err_irq:
420 RET(rc);
421}
422
423static void bdx_hw_stop(struct bdx_priv *priv)
424{
425 ENTER;
426 bdx_disable_interrupts(priv);
427 free_irq(priv->pdev->irq, priv->ndev);
428
429 netif_carrier_off(priv->ndev);
430 netif_stop_queue(priv->ndev);
431
432 RET();
433}
434
435static int bdx_hw_reset_direct(void __iomem *regs)
436{
437 u32 val, i;
438 ENTER;
439
440 /* reset sequences: read, write 1, read, write 0 */
441 val = readl(regs + regCLKPLL);
442 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
443 udelay(50);
444 val = readl(regs + regCLKPLL);
445 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
446
447 /* check that the PLLs are locked and reset ended */
448 for (i = 0; i < 70; i++, mdelay(10))
449 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
450 /* do any PCI-E read transaction */
451 readl(regs + regRXD_CFG0_0);
452 return 0;
453 }
454 ERR("tehuti: HW reset failed\n");
455 return 1; /* failure */
456}
457
458static int bdx_hw_reset(struct bdx_priv *priv)
459{
460 u32 val, i;
461 ENTER;
462
463 if (priv->port == 0) {
464 /* reset sequences: read, write 1, read, write 0 */
465 val = READ_REG(priv, regCLKPLL);
466 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
467 udelay(50);
468 val = READ_REG(priv, regCLKPLL);
469 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
470 }
471 /* check that the PLLs are locked and reset ended */
472 for (i = 0; i < 70; i++, mdelay(10))
473 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
474 /* do any PCI-E read transaction */
475 READ_REG(priv, regRXD_CFG0_0);
476 return 0;
477 }
478 ERR("tehuti: HW reset failed\n");
479 return 1; /* failure */
480}
481
482static int bdx_sw_reset(struct bdx_priv *priv)
483{
484 int i;
485
486 ENTER;
487 /* 1. load MAC (obsolete) */
488 /* 2. disable Rx (and Tx) */
489 WRITE_REG(priv, regGMAC_RXF_A, 0);
490 mdelay(100);
491 /* 3. disable port */
492 WRITE_REG(priv, regDIS_PORT, 1);
493 /* 4. disable queue */
494 WRITE_REG(priv, regDIS_QU, 1);
495 /* 5. wait until hw is disabled */
496 for (i = 0; i < 50; i++) {
497 if (READ_REG(priv, regRST_PORT) & 1)
498 break;
499 mdelay(10);
500 }
501 if (i == 50)
502 ERR("%s: SW reset timeout. continuing anyway\n",
503 priv->ndev->name);
504
505 /* 6. disable intrs */
506 WRITE_REG(priv, regRDINTCM0, 0);
507 WRITE_REG(priv, regTDINTCM0, 0);
508 WRITE_REG(priv, regIMR, 0);
509 READ_REG(priv, regISR);
510
511 /* 7. reset queue */
512 WRITE_REG(priv, regRST_QU, 1);
513 /* 8. reset port */
514 WRITE_REG(priv, regRST_PORT, 1);
515 /* 9. zero all read and write pointers */
516 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
517 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
518 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
519 WRITE_REG(priv, i, 0);
520 /* 10. unseet port disable */
521 WRITE_REG(priv, regDIS_PORT, 0);
522 /* 11. unset queue disable */
523 WRITE_REG(priv, regDIS_QU, 0);
524 /* 12. unset queue reset */
525 WRITE_REG(priv, regRST_QU, 0);
526 /* 13. unset port reset */
527 WRITE_REG(priv, regRST_PORT, 0);
528 /* 14. enable Rx */
529 /* skiped. will be done later */
530 /* 15. save MAC (obsolete) */
531 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
532 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
533
534 RET(0);
535}
536
537/* bdx_reset - performs right type of reset depending on hw type */
538static int bdx_reset(struct bdx_priv *priv)
539{
540 ENTER;
541 RET((priv->pdev->device == 0x3009)
542 ? bdx_hw_reset(priv)
543 : bdx_sw_reset(priv));
544}
545
546/**
547 * bdx_close - Disables a network interface
548 * @netdev: network interface device structure
549 *
550 * Returns 0, this is not allowed to fail
551 *
552 * The close entry point is called when an interface is de-activated
553 * by the OS. The hardware is still under the drivers control, but
554 * needs to be disabled. A global MAC reset is issued to stop the
555 * hardware, and all transmit and receive resources are freed.
556 **/
557static int bdx_close(struct net_device *ndev)
558{
559 struct bdx_priv *priv = NULL;
560
561 ENTER;
562 priv = ndev->priv;
563
564 napi_disable(&priv->napi);
565
566 bdx_reset(priv);
567 bdx_hw_stop(priv);
568 bdx_rx_free(priv);
569 bdx_tx_free(priv);
570 RET(0);
571}
572
573/**
574 * bdx_open - Called when a network interface is made active
575 * @netdev: network interface device structure
576 *
577 * Returns 0 on success, negative value on failure
578 *
579 * The open entry point is called when a network interface is made
580 * active by the system (IFF_UP). At this point all resources needed
581 * for transmit and receive operations are allocated, the interrupt
582 * handler is registered with the OS, the watchdog timer is started,
583 * and the stack is notified that the interface is ready.
584 **/
585static int bdx_open(struct net_device *ndev)
586{
587 struct bdx_priv *priv;
588 int rc;
589
590 ENTER;
591 priv = ndev->priv;
592 bdx_reset(priv);
593 if (netif_running(ndev))
594 netif_stop_queue(priv->ndev);
595
596 if ((rc = bdx_tx_init(priv)))
597 goto err;
598
599 if ((rc = bdx_rx_init(priv)))
600 goto err;
601
602 if ((rc = bdx_fw_load(priv)))
603 goto err;
604
605 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
606
607 if ((rc = bdx_hw_start(priv)))
608 goto err;
609
610 napi_enable(&priv->napi);
611
612 print_fw_id(priv->nic);
613
614 RET(0);
615
616err:
617 bdx_close(ndev);
618 RET(rc);
619}
620
621static void __init bdx_firmware_endianess(void)
622{
623 int i;
624 for (i = 0; i < sizeof(s_firmLoad) / sizeof(u32); i++)
625 s_firmLoad[i] = CPU_CHIP_SWAP32(s_firmLoad[i]);
626}
627
628static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
629{
630 struct bdx_priv *priv = ndev->priv;
631 u32 data[3];
632 int error;
633
634 ENTER;
635
636 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
637 if (cmd != SIOCDEVPRIVATE) {
638 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
639 if (error) {
640 ERR("cant copy from user\n");
641 RET(error);
642 }
643 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
644 }
645
646 switch (data[0]) {
647
648 case BDX_OP_READ:
649 data[2] = READ_REG(priv, data[1]);
650 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
651 data[2]);
652 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
653 if (error)
654 RET(error);
655 break;
656
657 case BDX_OP_WRITE:
658 WRITE_REG(priv, data[1], data[2]);
659 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
660 break;
661
662 default:
663 RET(-EOPNOTSUPP);
664 }
665 return 0;
666}
667
668static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
669{
670 ENTER;
671 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
672 RET(bdx_ioctl_priv(ndev, ifr, cmd));
673 else
674 RET(-EOPNOTSUPP);
675}
676
677/*
678 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
679 * by passing VLAN filter table to hardware
680 * @ndev network device
681 * @vid VLAN vid
682 * @op add or kill operation
683 */
684static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
685{
686 struct bdx_priv *priv = ndev->priv;
687 u32 reg, bit, val;
688
689 ENTER;
690 DBG2("vid=%d value=%d\n", (int)vid, enable);
691 if (unlikely(vid >= 4096)) {
692 ERR("tehuti: invalid VID: %u (> 4096)\n", vid);
693 RET();
694 }
695 reg = regVLAN_0 + (vid / 32) * 4;
696 bit = 1 << vid % 32;
697 val = READ_REG(priv, reg);
698 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
699 if (enable)
700 val |= bit;
701 else
702 val &= ~bit;
703 DBG2("new val %x\n", val);
704 WRITE_REG(priv, reg, val);
705 RET();
706}
707
708/*
709 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
710 * @ndev network device
711 * @vid VLAN vid to add
712 */
713static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
714{
715 __bdx_vlan_rx_vid(ndev, vid, 1);
716}
717
718/*
719 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
720 * @ndev network device
721 * @vid VLAN vid to kill
722 */
723static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
724{
725 __bdx_vlan_rx_vid(ndev, vid, 0);
726}
727
728/*
729 * bdx_vlan_rx_register - kernel hook for adding VLAN group
730 * @ndev network device
731 * @grp VLAN group
732 */
733static void
734bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
735{
736 struct bdx_priv *priv = ndev->priv;
737
738 ENTER;
739 DBG("device='%s', group='%p'\n", ndev->name, grp);
740 priv->vlgrp = grp;
741 RET();
742}
743
744/**
745 * bdx_change_mtu - Change the Maximum Transfer Unit
746 * @netdev: network interface device structure
747 * @new_mtu: new value for maximum frame size
748 *
749 * Returns 0 on success, negative on failure
750 */
751static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
752{
753 BDX_ASSERT(ndev == 0);
754 ENTER;
755
756 if (new_mtu == ndev->mtu)
757 RET(0);
758
759 /* enforce minimum frame size */
760 if (new_mtu < ETH_ZLEN) {
761 ERR("%s: %s mtu %d is less then minimal %d\n",
762 BDX_DRV_NAME, ndev->name, new_mtu, ETH_ZLEN);
763 RET(-EINVAL);
764 }
765
766 ndev->mtu = new_mtu;
767 if (netif_running(ndev)) {
768 bdx_close(ndev);
769 bdx_open(ndev);
770 }
771 RET(0);
772}
773
774static void bdx_setmulti(struct net_device *ndev)
775{
776 struct bdx_priv *priv = ndev->priv;
777
778 u32 rxf_val =
779 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
780 int i;
781
782 ENTER;
783 /* IMF - imperfect (hash) rx multicat filter */
784 /* PMF - perfect rx multicat filter */
785
786 /* FIXME: RXE(OFF) */
787 if (ndev->flags & IFF_PROMISC) {
788 rxf_val |= GMAC_RX_FILTER_PRM;
789 } else if (ndev->flags & IFF_ALLMULTI) {
790 /* set IMF to accept all multicast frmaes */
791 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
792 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
793 } else if (ndev->mc_count) {
794 u8 hash;
795 struct dev_mc_list *mclist;
796 u32 reg, val;
797
798 /* set IMF to deny all multicast frames */
799 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
800 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
801 /* set PMF to deny all multicast frames */
802 for (i = 0; i < MAC_MCST_NUM; i++) {
803 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
804 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
805 }
806
807 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
808 /* TBD: sort addreses and write them in ascending order
809 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
810 * multicast frames throu IMF */
811 mclist = ndev->mc_list;
812
813 /* accept the rest of addresses throu IMF */
814 for (; mclist; mclist = mclist->next) {
815 hash = 0;
816 for (i = 0; i < ETH_ALEN; i++)
817 hash ^= mclist->dmi_addr[i];
818 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
819 val = READ_REG(priv, reg);
820 val |= (1 << (hash % 32));
821 WRITE_REG(priv, reg, val);
822 }
823
824 } else {
825 DBG("only own mac %d\n", ndev->mc_count);
826 rxf_val |= GMAC_RX_FILTER_AB;
827 }
828 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
829 /* enable RX */
830 /* FIXME: RXE(ON) */
831 RET();
832}
833
834static int bdx_set_mac(struct net_device *ndev, void *p)
835{
836 struct bdx_priv *priv = ndev->priv;
837 struct sockaddr *addr = p;
838
839 ENTER;
840 /*
841 if (netif_running(dev))
842 return -EBUSY
843 */
844 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
845 bdx_restore_mac(ndev, priv);
846 RET(0);
847}
848
849static int bdx_read_mac(struct bdx_priv *priv)
850{
851 u16 macAddress[3], i;
852 ENTER;
853
854 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
855 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
856 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
857 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
858 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
859 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
860 for (i = 0; i < 3; i++) {
861 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
862 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
863 }
864 RET(0);
865}
866
867static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
868{
869 u64 val;
870
871 val = READ_REG(priv, reg);
872 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
873 return val;
874}
875
876/*Do the statistics-update work*/
877static void bdx_update_stats(struct bdx_priv *priv)
878{
879 struct bdx_stats *stats = &priv->hw_stats;
880 u64 *stats_vector = (u64 *) stats;
881 int i;
882 int addr;
883
884 /*Fill HW structure */
885 addr = 0x7200;
886 /*First 12 statistics - 0x7200 - 0x72B0 */
887 for (i = 0; i < 12; i++) {
888 stats_vector[i] = bdx_read_l2stat(priv, addr);
889 addr += 0x10;
890 }
891 BDX_ASSERT(addr != 0x72C0);
892 /* 0x72C0-0x72E0 RSRV */
893 addr = 0x72F0;
894 for (; i < 16; i++) {
895 stats_vector[i] = bdx_read_l2stat(priv, addr);
896 addr += 0x10;
897 }
898 BDX_ASSERT(addr != 0x7330);
899 /* 0x7330-0x7360 RSRV */
900 addr = 0x7370;
901 for (; i < 19; i++) {
902 stats_vector[i] = bdx_read_l2stat(priv, addr);
903 addr += 0x10;
904 }
905 BDX_ASSERT(addr != 0x73A0);
906 /* 0x73A0-0x73B0 RSRV */
907 addr = 0x73C0;
908 for (; i < 23; i++) {
909 stats_vector[i] = bdx_read_l2stat(priv, addr);
910 addr += 0x10;
911 }
912 BDX_ASSERT(addr != 0x7400);
913 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
914}
915
916static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
917{
918 struct bdx_priv *priv = ndev->priv;
919 struct net_device_stats *net_stat = &priv->net_stats;
920 return net_stat;
921}
922
923static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
924 u16 rxd_vlan);
925static void print_rxfd(struct rxf_desc *rxfd);
926
927/*************************************************************************
928 * Rx DB *
929 *************************************************************************/
930
931static void bdx_rxdb_destroy(struct rxdb *db)
932{
933 if (db)
934 vfree(db);
935}
936
937static struct rxdb *bdx_rxdb_create(int nelem)
938{
939 struct rxdb *db;
940 int i;
941
942 db = vmalloc(sizeof(struct rxdb)
943 + (nelem * sizeof(int))
944 + (nelem * sizeof(struct rx_map)));
945 if (likely(db != NULL)) {
946 db->stack = (int *)(db + 1);
947 db->elems = (void *)(db->stack + nelem);
948 db->nelem = nelem;
949 db->top = nelem;
950 for (i = 0; i < nelem; i++)
951 db->stack[i] = nelem - i - 1; /* to make first allocs
952 close to db struct*/
953 }
954
955 return db;
956}
957
958static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
959{
960 BDX_ASSERT(db->top <= 0);
961 return db->stack[--(db->top)];
962}
963
964static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
965{
966 BDX_ASSERT((n < 0) || (n >= db->nelem));
967 return db->elems + n;
968}
969
970static inline int bdx_rxdb_available(struct rxdb *db)
971{
972 return db->top;
973}
974
975static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
976{
977 BDX_ASSERT((n >= db->nelem) || (n < 0));
978 db->stack[(db->top)++] = n;
979}
980
981/*************************************************************************
982 * Rx Init *
983 *************************************************************************/
984
985/* bdx_rx_init - initialize RX all related HW and SW resources
986 * @priv - NIC private structure
987 *
988 * Returns 0 on success, negative value on failure
989 *
990 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
991 * skb for rx. It assumes that Rx is desabled in HW
992 * funcs are grouped for better cache usage
993 *
994 * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be
995 * filled and packets will be dropped by nic without getting into host or
996 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
997 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
998 */
999
1000/* TBD: ensure proper packet size */
1001
1002static int bdx_rx_init(struct bdx_priv *priv)
1003{
1004 ENTER;
1005 BDX_ASSERT(priv == 0);
1006 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1007 regRXD_CFG0_0, regRXD_CFG1_0,
1008 regRXD_RPTR_0, regRXD_WPTR_0))
1009 goto err_mem;
1010 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1011 regRXF_CFG0_0, regRXF_CFG1_0,
1012 regRXF_RPTR_0, regRXF_WPTR_0))
1013 goto err_mem;
1014 if (!
1015 (priv->rxdb =
1016 bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1017 sizeof(struct rxf_desc))))
1018 goto err_mem;
1019
1020 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1021 return 0;
1022
1023err_mem:
1024 ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME, priv->ndev->name);
1025 return -ENOMEM;
1026}
1027
1028/* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1029 * @priv - NIC private structure
1030 * @f - RXF fifo
1031 */
1032static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1033{
1034 struct rx_map *dm;
1035 struct rxdb *db = priv->rxdb;
1036 u16 i;
1037
1038 ENTER;
1039 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1040 db->nelem - bdx_rxdb_available(db));
1041 while (bdx_rxdb_available(db) > 0) {
1042 i = bdx_rxdb_alloc_elem(db);
1043 dm = bdx_rxdb_addr_elem(db, i);
1044 dm->dma = 0;
1045 }
1046 for (i = 0; i < db->nelem; i++) {
1047 dm = bdx_rxdb_addr_elem(db, i);
1048 if (dm->dma) {
1049 pci_unmap_single(priv->pdev,
1050 dm->dma, f->m.pktsz,
1051 PCI_DMA_FROMDEVICE);
1052 dev_kfree_skb(dm->skb);
1053 }
1054 }
1055}
1056
1057/* bdx_rx_free - release all Rx resources
1058 * @priv - NIC private structure
1059 * It assumes that Rx is desabled in HW
1060 */
1061static void bdx_rx_free(struct bdx_priv *priv)
1062{
1063 ENTER;
1064 if (priv->rxdb) {
1065 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1066 bdx_rxdb_destroy(priv->rxdb);
1067 priv->rxdb = NULL;
1068 }
1069 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1070 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1071
1072 RET();
1073}
1074
1075/*************************************************************************
1076 * Rx Engine *
1077 *************************************************************************/
1078
1079/* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1080 * @priv - nic's private structure
1081 * @f - RXF fifo that needs skbs
1082 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1083 * skb's virtual and physical addresses are stored in skb db.
1084 * To calculate free space, func uses cached values of RPTR and WPTR
1085 * When needed, it also updates RPTR and WPTR.
1086 */
1087
1088/* TBD: do not update WPTR if no desc were written */
1089
1090static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1091{
1092 struct sk_buff *skb;
1093 struct rxf_desc *rxfd;
1094 struct rx_map *dm;
1095 int dno, delta, idx;
1096 struct rxdb *db = priv->rxdb;
1097
1098 ENTER;
1099 dno = bdx_rxdb_available(db) - 1;
1100 while (dno > 0) {
1101 if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) {
1102 ERR("NO MEM: dev_alloc_skb failed\n");
1103 break;
1104 }
1105 skb->dev = priv->ndev;
1106 skb_reserve(skb, NET_IP_ALIGN);
1107
1108 idx = bdx_rxdb_alloc_elem(db);
1109 dm = bdx_rxdb_addr_elem(db, idx);
1110 dm->dma = pci_map_single(priv->pdev,
1111 skb->data, f->m.pktsz,
1112 PCI_DMA_FROMDEVICE);
1113 dm->skb = skb;
1114 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1115 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1116 rxfd->va_lo = idx;
1117 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1118 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1119 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1120 print_rxfd(rxfd);
1121
1122 f->m.wptr += sizeof(struct rxf_desc);
1123 delta = f->m.wptr - f->m.memsz;
1124 if (unlikely(delta >= 0)) {
1125 f->m.wptr = delta;
1126 if (delta > 0) {
1127 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1128 DBG("wrapped descriptor\n");
1129 }
1130 }
1131 dno--;
1132 }
1133 /*TBD: to do - delayed rxf wptr like in txd */
1134 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1135 RET();
1136}
1137
1138static inline void
1139NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1140 struct sk_buff *skb)
1141{
1142 ENTER;
1143 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
1144 priv->vlgrp);
1145 if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
1146 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1147 priv->ndev->name,
1148 GET_RXD_VLAN_ID(rxd_vlan),
1149 GET_RXD_VTAG(rxd_val1),
1150 vlan_group_get_device(priv->vlgrp,
1151 GET_RXD_VLAN_ID(rxd_vlan))->name);
1152 /* NAPI variant of receive functions */
1153 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1154 GET_RXD_VLAN_ID(rxd_vlan));
1155 } else {
1156 netif_receive_skb(skb);
1157 }
1158}
1159
1160static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1161{
1162 struct rxf_desc *rxfd;
1163 struct rx_map *dm;
1164 struct rxf_fifo *f;
1165 struct rxdb *db;
1166 struct sk_buff *skb;
1167 int delta;
1168
1169 ENTER;
1170 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1171 f = &priv->rxf_fifo0;
1172 db = priv->rxdb;
1173 DBG("db=%p f=%p\n", db, f);
1174 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1175 DBG("dm=%p\n", dm);
1176 skb = dm->skb;
1177 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1178 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1179 rxfd->va_lo = rxdd->va_lo;
1180 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1181 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1182 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1183 print_rxfd(rxfd);
1184
1185 f->m.wptr += sizeof(struct rxf_desc);
1186 delta = f->m.wptr - f->m.memsz;
1187 if (unlikely(delta >= 0)) {
1188 f->m.wptr = delta;
1189 if (delta > 0) {
1190 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1191 DBG("wrapped descriptor\n");
1192 }
1193 }
1194 RET();
1195}
1196
1197/* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1198 * NOTE: a special treatment is given to non-continous descriptors
1199 * that start near the end, wraps around and continue at the beginning. a second
1200 * part is copied right after the first, and then descriptor is interpreted as
1201 * normal. fifo has an extra space to allow such operations
1202 * @priv - nic's private structure
1203 * @f - RXF fifo that needs skbs
1204 */
1205
1206/* TBD: replace memcpy func call by explicite inline asm */
1207
1208static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1209{
1210 struct sk_buff *skb, *skb2;
1211 struct rxd_desc *rxdd;
1212 struct rx_map *dm;
1213 struct rxf_fifo *rxf_fifo;
1214 int tmp_len, size;
1215 int done = 0;
1216 int max_done = BDX_MAX_RX_DONE;
1217 struct rxdb *db = NULL;
1218 /* Unmarshalled descriptor - copy of descriptor in host order */
1219 u32 rxd_val1;
1220 u16 len;
1221 u16 rxd_vlan;
1222
1223 ENTER;
1224 max_done = budget;
1225
1226 priv->ndev->last_rx = jiffies;
1227 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1228
1229 size = f->m.wptr - f->m.rptr;
1230 if (size < 0)
1231 size = f->m.memsz + size; /* size is negative :-) */
1232
1233 while (size > 0) {
1234
1235 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1236 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1237
1238 len = CPU_CHIP_SWAP16(rxdd->len);
1239
1240 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1241
1242 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1243
1244 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1245 BDX_ASSERT(tmp_len <= 0);
1246 size -= tmp_len;
1247 if (size < 0) /* test for partially arrived descriptor */
1248 break;
1249
1250 f->m.rptr += tmp_len;
1251
1252 tmp_len = f->m.rptr - f->m.memsz;
1253 if (unlikely(tmp_len >= 0)) {
1254 f->m.rptr = tmp_len;
1255 if (tmp_len > 0) {
1256 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1257 f->m.rptr, tmp_len);
1258 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1259 }
1260 }
1261
1262 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1263 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1264 priv->net_stats.rx_errors++;
1265 bdx_recycle_skb(priv, rxdd);
1266 continue;
1267 }
1268
1269 rxf_fifo = &priv->rxf_fifo0;
1270 db = priv->rxdb;
1271 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1272 skb = dm->skb;
1273
1274 if (len < BDX_COPYBREAK &&
1275 (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
1276 skb_reserve(skb2, NET_IP_ALIGN);
1277 /*skb_put(skb2, len); */
1278 pci_dma_sync_single_for_cpu(priv->pdev,
1279 dm->dma, rxf_fifo->m.pktsz,
1280 PCI_DMA_FROMDEVICE);
1281 memcpy(skb2->data, skb->data, len);
1282 bdx_recycle_skb(priv, rxdd);
1283 skb = skb2;
1284 } else {
1285 pci_unmap_single(priv->pdev,
1286 dm->dma, rxf_fifo->m.pktsz,
1287 PCI_DMA_FROMDEVICE);
1288 bdx_rxdb_free_elem(db, rxdd->va_lo);
1289 }
1290
1291 priv->net_stats.rx_bytes += len;
1292
1293 skb_put(skb, len);
1294 skb->dev = priv->ndev;
1295 skb->ip_summed = CHECKSUM_UNNECESSARY;
1296 skb->protocol = eth_type_trans(skb, priv->ndev);
1297
1298 /* Non-IP packets aren't checksum-offloaded */
1299 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1300 skb->ip_summed = CHECKSUM_NONE;
1301
1302 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1303
1304 if (++done >= max_done)
1305 break;
1306 }
1307
1308 priv->net_stats.rx_packets += done;
1309
1310 /* FIXME: do smth to minimize pci accesses */
1311 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1312
1313 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1314
1315 RET(done);
1316}
1317
1318/*************************************************************************
1319 * Debug / Temprorary Code *
1320 *************************************************************************/
1321static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1322 u16 rxd_vlan)
1323{
1324 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d "
1325 "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d "
1326 "va_lo %d va_hi %d\n",
1327 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1328 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1329 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1330 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1331 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1332 rxdd->va_hi);
1333}
1334
1335static void print_rxfd(struct rxf_desc *rxfd)
1336{
1337 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1338 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1339 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1340}
1341
1342/*
1343 * TX HW/SW interaction overview
1344 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1345 * There are 2 types of TX communication channels betwean driver and NIC.
1346 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1347 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1348 *
1349 * Currently NIC supports TSO, checksuming and gather DMA
1350 * UFO and IP fragmentation is on the way
1351 *
1352 * RX SW Data Structures
1353 * ~~~~~~~~~~~~~~~~~~~~~
1354 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1355 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1356 * acknowledges sent by TXF descriptors.
1357 * Implemented as cyclic buffer.
1358 * fifo - keeps info about fifo's size and location, relevant HW registers,
1359 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1360 * Implemented as simple struct.
1361 *
1362 * TX SW Execution Flow
1363 * ~~~~~~~~~~~~~~~~~~~~
1364 * OS calls driver's hard_xmit method with packet to sent.
1365 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1366 * by updating TXD WPTR.
1367 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1368 * To prevent TXD fifo overflow without reading HW registers every time,
1369 * SW deploys "tx level" technique.
1370 * Upon strart up, tx level is initialized to TXD fifo length.
1371 * For every sent packet, SW gets its TXD descriptor sizei
1372 * (from precalculated array) and substructs it from tx level.
1373 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1374 * original TXD descriptor from txdb and adds it to tx level.
1375 * When Tx level drops under some predefined treshhold, the driver
1376 * stops the TX queue. When TX level rises above that level,
1377 * the tx queue is enabled again.
1378 *
1379 * This technique avoids eccessive reading of RPTR and WPTR registers.
1380 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1381 */
1382
1383/*************************************************************************
1384 * Tx DB *
1385 *************************************************************************/
1386static inline int bdx_tx_db_size(struct txdb *db)
1387{
1388 int taken = db->wptr - db->rptr;
1389 if (taken < 0)
1390 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1391
1392 return db->size - taken;
1393}
1394
1395/* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1396 * @d - tx data base
1397 * @ptr - read or write pointer
1398 */
1399static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1400{
1401 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1402
1403 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1404 *pptr != db->wptr); /* or write pointer */
1405
1406 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1407 *pptr >= db->end); /* in range */
1408
1409 ++*pptr;
1410 if (unlikely(*pptr == db->end))
1411 *pptr = db->start;
1412}
1413
1414/* bdx_tx_db_inc_rptr - increment read pointer
1415 * @d - tx data base
1416 */
1417static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1418{
1419 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1420 __bdx_tx_db_ptr_next(db, &db->rptr);
1421}
1422
1423/* bdx_tx_db_inc_rptr - increment write pointer
1424 * @d - tx data base
1425 */
1426static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1427{
1428 __bdx_tx_db_ptr_next(db, &db->wptr);
1429 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1430 a result of write */
1431}
1432
1433/* bdx_tx_db_init - creates and initializes tx db
1434 * @d - tx data base
1435 * @sz_type - size of tx fifo
1436 * Returns 0 on success, error code otherwise
1437 */
1438static int bdx_tx_db_init(struct txdb *d, int sz_type)
1439{
1440 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1441
1442 d->start = vmalloc(memsz);
1443 if (!d->start)
1444 return -ENOMEM;
1445
1446 /*
1447 * In order to differentiate between db is empty and db is full
1448 * states at least one element should always be empty in order to
1449 * avoid rptr == wptr which means db is empty
1450 */
1451 d->size = memsz / sizeof(struct tx_map) - 1;
1452 d->end = d->start + d->size + 1; /* just after last element */
1453
1454 /* all dbs are created equally empty */
1455 d->rptr = d->start;
1456 d->wptr = d->start;
1457
1458 return 0;
1459}
1460
1461/* bdx_tx_db_close - closes tx db and frees all memory
1462 * @d - tx data base
1463 */
1464static void bdx_tx_db_close(struct txdb *d)
1465{
1466 BDX_ASSERT(d == NULL);
1467
1468 if (d->start) {
1469 vfree(d->start);
1470 d->start = NULL;
1471 }
1472}
1473
1474/*************************************************************************
1475 * Tx Engine *
1476 *************************************************************************/
1477
1478/* sizes of tx desc (including padding if needed) as function
1479 * of skb's frag number */
1480static struct {
1481 u16 bytes;
1482 u16 qwords; /* qword = 64 bit */
1483} txd_sizes[MAX_SKB_FRAGS + 1];
1484
1485/* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1486 * @priv - NIC private structure
1487 * @skb - socket buffer to map
1488 *
1489 * It makes dma mappings for skb's data blocks and writes them to PBL of
1490 * new tx descriptor. It also stores them in the tx db, so they could be
1491 * unmaped after data was sent. It is reponsibility of a caller to make
1492 * sure that there is enough space in the tx db. Last element holds pointer
1493 * to skb itself and marked with zero length
1494 */
1495static inline void
1496bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1497 struct txd_desc *txdd)
1498{
1499 struct txdb *db = &priv->txdb;
1500 struct pbl *pbl = &txdd->pbl[0];
1501 int nr_frags = skb_shinfo(skb)->nr_frags;
1502 int i;
1503
1504 db->wptr->len = skb->len - skb->data_len;
1505 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1506 db->wptr->len, PCI_DMA_TODEVICE);
1507 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1508 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1509 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1510 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1511 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1512 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1513 bdx_tx_db_inc_wptr(db);
1514
1515 for (i = 0; i < nr_frags; i++) {
1516 struct skb_frag_struct *frag;
1517
1518 frag = &skb_shinfo(skb)->frags[i];
1519 db->wptr->len = frag->size;
1520 db->wptr->addr.dma =
1521 pci_map_page(priv->pdev, frag->page, frag->page_offset,
1522 frag->size, PCI_DMA_TODEVICE);
1523
1524 pbl++;
1525 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1526 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1527 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1528 bdx_tx_db_inc_wptr(db);
1529 }
1530
1531 /* add skb clean up info. */
1532 db->wptr->len = -txd_sizes[nr_frags].bytes;
1533 db->wptr->addr.skb = skb;
1534 bdx_tx_db_inc_wptr(db);
1535}
1536
1537/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1538 * number of frags is used as index to fetch correct descriptors size,
1539 * instead of calculating it each time */
1540static void __init init_txd_sizes(void)
1541{
1542 int i, lwords;
1543
1544 /* 7 - is number of lwords in txd with one phys buffer
1545 * 3 - is number of lwords used for every additional phys buffer */
1546 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1547 lwords = 7 + (i * 3);
1548 if (lwords & 1)
1549 lwords++; /* pad it with 1 lword */
1550 txd_sizes[i].qwords = lwords >> 1;
1551 txd_sizes[i].bytes = lwords << 2;
1552 }
1553}
1554
1555/* bdx_tx_init - initialize all Tx related stuff.
1556 * Namely, TXD and TXF fifos, database etc */
1557static int bdx_tx_init(struct bdx_priv *priv)
1558{
1559 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1560 regTXD_CFG0_0,
1561 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1562 goto err_mem;
1563 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1564 regTXF_CFG0_0,
1565 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1566 goto err_mem;
1567
1568 /* The TX db has to keep mappings for all packets sent (on TxD)
1569 * and not yet reclaimed (on TxF) */
1570 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1571 goto err_mem;
1572
1573 priv->tx_level = BDX_MAX_TX_LEVEL;
1574#ifdef BDX_DELAY_WPTR
1575 priv->tx_update_mark = priv->tx_level - 1024;
1576#endif
1577 return 0;
1578
1579err_mem:
1580 ERR("tehuti: %s: Tx init failed\n", priv->ndev->name);
1581 return -ENOMEM;
1582}
1583
1584/*
1585 * bdx_tx_space - calculates avalable space in TX fifo
1586 * @priv - NIC private structure
1587 * Returns avaliable space in TX fifo in bytes
1588 */
1589static inline int bdx_tx_space(struct bdx_priv *priv)
1590{
1591 struct txd_fifo *f = &priv->txd_fifo0;
1592 int fsize;
1593
1594 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1595 fsize = f->m.rptr - f->m.wptr;
1596 if (fsize <= 0)
1597 fsize = f->m.memsz + fsize;
1598 return (fsize);
1599}
1600
1601/* bdx_tx_transmit - send packet to NIC
1602 * @skb - packet to send
1603 * ndev - network device assigned to NIC
1604 * Return codes:
1605 * o NETDEV_TX_OK everything ok.
1606 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1607 * Usually a bug, means queue start/stop flow control is broken in
1608 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1609 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1610 */
1611static int bdx_tx_transmit(struct sk_buff *skb, struct net_device *ndev)
1612{
1613 struct bdx_priv *priv = ndev->priv;
1614 struct txd_fifo *f = &priv->txd_fifo0;
1615 int txd_checksum = 7; /* full checksum */
1616 int txd_lgsnd = 0;
1617 int txd_vlan_id = 0;
1618 int txd_vtag = 0;
1619 int txd_mss = 0;
1620
1621 int nr_frags = skb_shinfo(skb)->nr_frags;
1622 struct txd_desc *txdd;
1623 int len;
1624 unsigned long flags;
1625
1626 ENTER;
1627 local_irq_save(flags);
1628 if (!spin_trylock(&priv->tx_lock)) {
1629 local_irq_restore(flags);
1630 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1631 BDX_DRV_NAME, ndev->name);
1632 return NETDEV_TX_LOCKED;
1633 }
1634
1635 /* build tx descriptor */
1636 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1637 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1638 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1639 txd_checksum = 0;
1640
1641 if (skb_shinfo(skb)->gso_size) {
1642 txd_mss = skb_shinfo(skb)->gso_size;
1643 txd_lgsnd = 1;
1644 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1645 txd_mss);
1646 }
1647
1648 if (vlan_tx_tag_present(skb)) {
1649 /*Cut VLAN ID to 12 bits */
1650 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
1651 txd_vtag = 1;
1652 }
1653
1654 txdd->length = CPU_CHIP_SWAP16(skb->len);
1655 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1656 txdd->txd_val1 =
1657 CPU_CHIP_SWAP32(TXD_W1_VAL
1658 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1659 txd_lgsnd, txd_vlan_id));
1660 DBG("=== TxD desc =====================\n");
1661 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1662 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1663
1664 bdx_tx_map_skb(priv, skb, txdd);
1665
1666 /* increment TXD write pointer. In case of
1667 fifo wrapping copy reminder of the descriptor
1668 to the beginning */
1669 f->m.wptr += txd_sizes[nr_frags].bytes;
1670 len = f->m.wptr - f->m.memsz;
1671 if (unlikely(len >= 0)) {
1672 f->m.wptr = len;
1673 if (len > 0) {
1674 BDX_ASSERT(len > f->m.memsz);
1675 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1676 }
1677 }
1678 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1679
1680 priv->tx_level -= txd_sizes[nr_frags].bytes;
1681 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1682#ifdef BDX_DELAY_WPTR
1683 if (priv->tx_level > priv->tx_update_mark) {
1684 /* Force memory writes to complete before letting h/w
1685 know there are new descriptors to fetch.
1686 (might be needed on platforms like IA64)
1687 wmb(); */
1688 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1689 } else {
1690 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1691 priv->tx_noupd = 0;
1692 WRITE_REG(priv, f->m.reg_WPTR,
1693 f->m.wptr & TXF_WPTR_WR_PTR);
1694 }
1695 }
1696#else
1697 /* Force memory writes to complete before letting h/w
1698 know there are new descriptors to fetch.
1699 (might be needed on platforms like IA64)
1700 wmb(); */
1701 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1702
1703#endif
1704 ndev->trans_start = jiffies;
1705
1706 priv->net_stats.tx_packets++;
1707 priv->net_stats.tx_bytes += skb->len;
1708
1709 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1710 DBG("%s: %s: TX Q STOP level %d\n",
1711 BDX_DRV_NAME, ndev->name, priv->tx_level);
1712 netif_stop_queue(ndev);
1713 }
1714
1715 spin_unlock_irqrestore(&priv->tx_lock, flags);
1716 return NETDEV_TX_OK;
1717}
1718
1719/* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1720 * @priv - bdx adapter
1721 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1722 * that those packets were sent
1723 */
1724static void bdx_tx_cleanup(struct bdx_priv *priv)
1725{
1726 struct txf_fifo *f = &priv->txf_fifo0;
1727 struct txdb *db = &priv->txdb;
1728 int tx_level = 0;
1729
1730 ENTER;
1731 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1732 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1733
1734 while (f->m.wptr != f->m.rptr) {
1735 f->m.rptr += BDX_TXF_DESC_SZ;
1736 f->m.rptr &= f->m.size_mask;
1737
1738 /* unmap all the fragments */
1739 /* first has to come tx_maps containing dma */
1740 BDX_ASSERT(db->rptr->len == 0);
1741 do {
1742 BDX_ASSERT(db->rptr->addr.dma == 0);
1743 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1744 db->rptr->len, PCI_DMA_TODEVICE);
1745 bdx_tx_db_inc_rptr(db);
1746 } while (db->rptr->len > 0);
1747 tx_level -= db->rptr->len; /* '-' koz len is negative */
1748
1749 /* now should come skb pointer - free it */
1750 BDX_ASSERT(db->rptr->addr.skb == 0);
1751 dev_kfree_skb_irq(db->rptr->addr.skb);
1752 bdx_tx_db_inc_rptr(db);
1753 }
1754
1755 /* let h/w know which TXF descriptors were cleaned */
1756 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1757 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1758
1759 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1760 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1761 spin_lock(&priv->tx_lock);
1762 priv->tx_level += tx_level;
1763 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1764#ifdef BDX_DELAY_WPTR
1765 if (priv->tx_noupd) {
1766 priv->tx_noupd = 0;
1767 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1768 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1769 }
1770#endif
1771
1772 if (unlikely(netif_queue_stopped(priv->ndev)
1773 && netif_carrier_ok(priv->ndev)
1774 && (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1775 DBG("%s: %s: TX Q WAKE level %d\n",
1776 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1777 netif_wake_queue(priv->ndev);
1778 }
1779 spin_unlock(&priv->tx_lock);
1780}
1781
1782/* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1783 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1784 */
1785static void bdx_tx_free_skbs(struct bdx_priv *priv)
1786{
1787 struct txdb *db = &priv->txdb;
1788
1789 ENTER;
1790 while (db->rptr != db->wptr) {
1791 if (likely(db->rptr->len))
1792 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1793 db->rptr->len, PCI_DMA_TODEVICE);
1794 else
1795 dev_kfree_skb(db->rptr->addr.skb);
1796 bdx_tx_db_inc_rptr(db);
1797 }
1798 RET();
1799}
1800
1801/* bdx_tx_free - frees all Tx resources */
1802static void bdx_tx_free(struct bdx_priv *priv)
1803{
1804 ENTER;
1805 bdx_tx_free_skbs(priv);
1806 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1807 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1808 bdx_tx_db_close(&priv->txdb);
1809}
1810
1811/* bdx_tx_push_desc - push descriptor to TxD fifo
1812 * @priv - NIC private structure
1813 * @data - desc's data
1814 * @size - desc's size
1815 *
1816 * Pushes desc to TxD fifo and overlaps it if needed.
1817 * NOTE: this func does not check for available space. this is responsibility
1818 * of the caller. Neither does it check that data size is smaller then
1819 * fifo size.
1820 */
1821static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1822{
1823 struct txd_fifo *f = &priv->txd_fifo0;
1824 int i = f->m.memsz - f->m.wptr;
1825
1826 if (size == 0)
1827 return;
1828
1829 if (i > size) {
1830 memcpy(f->m.va + f->m.wptr, data, size);
1831 f->m.wptr += size;
1832 } else {
1833 memcpy(f->m.va + f->m.wptr, data, i);
1834 f->m.wptr = size - i;
1835 memcpy(f->m.va, data + i, f->m.wptr);
1836 }
1837 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1838}
1839
1840/* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1841 * @priv - NIC private structure
1842 * @data - desc's data
1843 * @size - desc's size
1844 *
1845 * NOTE: this func does check for available space and, if neccessary, waits for
1846 * NIC to read existing data before writing new one.
1847 */
1848static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1849{
1850 int timer = 0;
1851 ENTER;
1852
1853 while (size > 0) {
1854 /* we substruct 8 because when fifo is full rptr == wptr
1855 which also means that fifo is empty, we can understand
1856 the difference, but could hw do the same ??? :) */
1857 int avail = bdx_tx_space(priv) - 8;
1858 if (avail <= 0) {
1859 if (timer++ > 300) { /* prevent endless loop */
1860 DBG("timeout while writing desc to TxD fifo\n");
1861 break;
1862 }
1863 udelay(50); /* give hw a chance to clean fifo */
1864 continue;
1865 }
1866 avail = MIN(avail, size);
1867 DBG("about to push %d bytes starting %p size %d\n", avail,
1868 data, size);
1869 bdx_tx_push_desc(priv, data, avail);
1870 size -= avail;
1871 data += avail;
1872 }
1873 RET();
1874}
1875
1876/**
1877 * bdx_probe - Device Initialization Routine
1878 * @pdev: PCI device information struct
1879 * @ent: entry in bdx_pci_tbl
1880 *
1881 * Returns 0 on success, negative on failure
1882 *
1883 * bdx_probe initializes an adapter identified by a pci_dev structure.
1884 * The OS initialization, configuring of the adapter private structure,
1885 * and a hardware reset occur.
1886 *
1887 * functions and their order used as explained in
1888 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1889 *
1890 */
1891
1892/* TBD: netif_msg should be checked and implemented. I disable it for now */
1893static int __devinit
1894bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1895{
1896 struct net_device *ndev;
1897 struct bdx_priv *priv;
1898 int err, pci_using_dac, port;
1899 unsigned long pciaddr;
1900 u32 regionSize;
1901 struct pci_nic *nic;
1902
1903 ENTER;
1904
1905 nic = vmalloc(sizeof(*nic));
1906 if (!nic)
1907 RET(-ENOMEM);
1908
1909 /************** pci *****************/
1910 if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */
1911 RET(err); /* it's not a problem though */
1912
1913 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
1914 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1915 pci_using_dac = 1;
1916 } else {
1917 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
1918 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1919 printk(KERN_ERR "tehuti: No usable DMA configuration"
1920 ", aborting\n");
1921 goto err_dma;
1922 }
1923 pci_using_dac = 0;
1924 }
1925
1926 if ((err = pci_request_regions(pdev, BDX_DRV_NAME)))
1927 goto err_dma;
1928
1929 pci_set_master(pdev);
1930
1931 pciaddr = pci_resource_start(pdev, 0);
1932 if (!pciaddr) {
1933 err = -EIO;
1934 ERR("tehuti: no MMIO resource\n");
1935 goto err_out_res;
1936 }
1937 if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) {
1938 err = -EIO;
1939 ERR("tehuti: MMIO resource (%x) too small\n", regionSize);
1940 goto err_out_res;
1941 }
1942
1943 nic->regs = ioremap(pciaddr, regionSize);
1944 if (!nic->regs) {
1945 err = -EIO;
1946 ERR("tehuti: ioremap failed\n");
1947 goto err_out_res;
1948 }
1949
1950 if (pdev->irq < 2) {
1951 err = -EIO;
1952 ERR("tehuti: invalid irq (%d)\n", pdev->irq);
1953 goto err_out_iomap;
1954 }
1955 pci_set_drvdata(pdev, nic);
1956
1957 if (pdev->device == 0x3014)
1958 nic->port_num = 2;
1959 else
1960 nic->port_num = 1;
1961
1962 print_hw_id(pdev);
1963
1964 bdx_hw_reset_direct(nic->regs);
1965
1966 nic->irq_type = IRQ_INTX;
1967#ifdef BDX_MSI
1968 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1969 if ((err = pci_enable_msi(pdev)))
1970 ERR("Tehuti: Can't eneble msi. error is %d\n", err);
1971 else
1972 nic->irq_type = IRQ_MSI;
1973 } else
1974 DBG("HW does not support MSI\n");
1975#endif
1976
1977 /************** netdev **************/
1978 for (port = 0; port < nic->port_num; port++) {
1979 if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) {
1980 err = -ENOMEM;
1981 printk(KERN_ERR "tehuti: alloc_etherdev failed\n");
1982 goto err_out_iomap;
1983 }
1984
1985 ndev->open = bdx_open;
1986 ndev->stop = bdx_close;
1987 ndev->hard_start_xmit = bdx_tx_transmit;
1988 ndev->do_ioctl = bdx_ioctl;
1989 ndev->set_multicast_list = bdx_setmulti;
1990 ndev->get_stats = bdx_get_stats;
1991 ndev->change_mtu = bdx_change_mtu;
1992 ndev->set_mac_address = bdx_set_mac;
1993 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1994 ndev->vlan_rx_register = bdx_vlan_rx_register;
1995 ndev->vlan_rx_add_vid = bdx_vlan_rx_add_vid;
1996 ndev->vlan_rx_kill_vid = bdx_vlan_rx_kill_vid;
1997
1998 bdx_ethtool_ops(ndev); /* ethtool interface */
1999
2000 /* these fields are used for info purposes only
2001 * so we can have them same for all ports of the board */
2002 ndev->if_port = port;
2003 ndev->base_addr = pciaddr;
2004 ndev->mem_start = pciaddr;
2005 ndev->mem_end = pciaddr + regionSize;
2006 ndev->irq = pdev->irq;
2007 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2008 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2009 NETIF_F_HW_VLAN_FILTER
2010 /*| NETIF_F_FRAGLIST */
2011 ;
2012
2013 if (pci_using_dac)
2014 ndev->features |= NETIF_F_HIGHDMA;
2015
2016 /************** priv ****************/
2017 priv = nic->priv[port] = ndev->priv;
2018
2019 memset(priv, 0, sizeof(struct bdx_priv));
2020 priv->pBdxRegs = nic->regs + port * 0x8000;
2021 priv->port = port;
2022 priv->pdev = pdev;
2023 priv->ndev = ndev;
2024 priv->nic = nic;
2025 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2026
2027 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2028
2029 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2030 DBG("HW statistics not supported\n");
2031 priv->stats_flag = 0;
2032 } else {
2033 priv->stats_flag = 1;
2034 }
2035
2036 /* Initialize fifo sizes. */
2037 priv->txd_size = 2;
2038 priv->txf_size = 2;
2039 priv->rxd_size = 2;
2040 priv->rxf_size = 3;
2041
2042 /* Initialize the initial coalescing registers. */
2043 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2044 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2045
2046 /* ndev->xmit_lock spinlock is not used.
2047 * Private priv->tx_lock is used for synchronization
2048 * between transmit and TX irq cleanup. In addition
2049 * set multicast list callback has to use priv->tx_lock.
2050 */
2051#ifdef BDX_LLTX
2052 ndev->features |= NETIF_F_LLTX;
2053#endif
2054 spin_lock_init(&priv->tx_lock);
2055
2056 /*bdx_hw_reset(priv); */
2057 if (bdx_read_mac(priv)) {
2058 printk(KERN_ERR "tehuti: load MAC address failed\n");
2059 goto err_out_iomap;
2060 }
2061 SET_NETDEV_DEV(ndev, &pdev->dev);
2062 if ((err = register_netdev(ndev))) {
2063 printk(KERN_ERR "tehuti: register_netdev failed\n");
2064 goto err_out_free;
2065 }
2066 netif_carrier_off(ndev);
2067 netif_stop_queue(ndev);
2068
2069 print_eth_id(ndev);
2070 }
2071 RET(0);
2072
2073err_out_free:
2074 free_netdev(ndev);
2075err_out_iomap:
2076 iounmap(nic->regs);
2077err_out_res:
2078 pci_release_regions(pdev);
2079err_dma:
2080 pci_disable_device(pdev);
2081 vfree(nic);
2082
2083 RET(err);
2084}
2085
2086/****************** Ethtool interface *********************/
2087/* get strings for tests */
2088static const char
2089 bdx_test_names[][ETH_GSTRING_LEN] = {
2090 "No tests defined"
2091};
2092
2093/* get strings for statistics counters */
2094static const char
2095 bdx_stat_names[][ETH_GSTRING_LEN] = {
2096 "InUCast", /* 0x7200 */
2097 "InMCast", /* 0x7210 */
2098 "InBCast", /* 0x7220 */
2099 "InPkts", /* 0x7230 */
2100 "InErrors", /* 0x7240 */
2101 "InDropped", /* 0x7250 */
2102 "FrameTooLong", /* 0x7260 */
2103 "FrameSequenceErrors", /* 0x7270 */
2104 "InVLAN", /* 0x7280 */
2105 "InDroppedDFE", /* 0x7290 */
2106 "InDroppedIntFull", /* 0x72A0 */
2107 "InFrameAlignErrors", /* 0x72B0 */
2108
2109 /* 0x72C0-0x72E0 RSRV */
2110
2111 "OutUCast", /* 0x72F0 */
2112 "OutMCast", /* 0x7300 */
2113 "OutBCast", /* 0x7310 */
2114 "OutPkts", /* 0x7320 */
2115
2116 /* 0x7330-0x7360 RSRV */
2117
2118 "OutVLAN", /* 0x7370 */
2119 "InUCastOctects", /* 0x7380 */
2120 "OutUCastOctects", /* 0x7390 */
2121
2122 /* 0x73A0-0x73B0 RSRV */
2123
2124 "InBCastOctects", /* 0x73C0 */
2125 "OutBCastOctects", /* 0x73D0 */
2126 "InOctects", /* 0x73E0 */
2127 "OutOctects", /* 0x73F0 */
2128};
2129
2130/*
2131 * bdx_get_settings - get device-specific settings
2132 * @netdev
2133 * @ecmd
2134 */
2135static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2136{
2137 u32 rdintcm;
2138 u32 tdintcm;
2139 struct bdx_priv *priv = netdev->priv;
2140
2141 rdintcm = priv->rdintcm;
2142 tdintcm = priv->tdintcm;
2143
2144 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2145 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2146 ecmd->speed = SPEED_10000;
2147 ecmd->duplex = DUPLEX_FULL;
2148 ecmd->port = PORT_FIBRE;
2149 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2150 ecmd->autoneg = AUTONEG_DISABLE;
2151
2152 /* PCK_TH measures in multiples of FIFO bytes
2153 We translate to packets */
2154 ecmd->maxtxpkt =
2155 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2156 ecmd->maxrxpkt =
2157 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2158
2159 return 0;
2160}
2161
2162/*
2163 * bdx_get_drvinfo - report driver information
2164 * @netdev
2165 * @drvinfo
2166 */
2167static void
2168bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2169{
2170 struct bdx_priv *priv = netdev->priv;
2171
2172 strncat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2173 strncat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2174 strncat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2175 strncat(drvinfo->bus_info, pci_name(priv->pdev),
2176 sizeof(drvinfo->bus_info));
2177
2178 drvinfo->n_stats = ((priv->stats_flag) ?
2179 (sizeof(bdx_stat_names) / ETH_GSTRING_LEN) : 0);
2180 drvinfo->testinfo_len = 0;
2181 drvinfo->regdump_len = 0;
2182 drvinfo->eedump_len = 0;
2183}
2184
2185/*
2186 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2187 * @netdev
2188 */
2189static u32 bdx_get_rx_csum(struct net_device *netdev)
2190{
2191 return 1; /* always on */
2192}
2193
2194/*
2195 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2196 * @netdev
2197 */
2198static u32 bdx_get_tx_csum(struct net_device *netdev)
2199{
2200 return (netdev->features & NETIF_F_IP_CSUM) != 0;
2201}
2202
2203/*
2204 * bdx_get_coalesce - get interrupt coalescing parameters
2205 * @netdev
2206 * @ecoal
2207 */
2208static int
2209bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2210{
2211 u32 rdintcm;
2212 u32 tdintcm;
2213 struct bdx_priv *priv = netdev->priv;
2214
2215 rdintcm = priv->rdintcm;
2216 tdintcm = priv->tdintcm;
2217
2218 /* PCK_TH measures in multiples of FIFO bytes
2219 We translate to packets */
2220 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2221 ecoal->rx_max_coalesced_frames =
2222 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2223
2224 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2225 ecoal->tx_max_coalesced_frames =
2226 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2227
2228 /* adaptive parameters ignored */
2229 return 0;
2230}
2231
2232/*
2233 * bdx_set_coalesce - set interrupt coalescing parameters
2234 * @netdev
2235 * @ecoal
2236 */
2237static int
2238bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2239{
2240 u32 rdintcm;
2241 u32 tdintcm;
2242 struct bdx_priv *priv = netdev->priv;
2243 int rx_coal;
2244 int tx_coal;
2245 int rx_max_coal;
2246 int tx_max_coal;
2247
2248 /* Check for valid input */
2249 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2250 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2251 rx_max_coal = ecoal->rx_max_coalesced_frames;
2252 tx_max_coal = ecoal->tx_max_coalesced_frames;
2253
2254 /* Translate from packets to multiples of FIFO bytes */
2255 rx_max_coal =
2256 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2257 / PCK_TH_MULT);
2258 tx_max_coal =
2259 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2260 / PCK_TH_MULT);
2261
2262 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF)
2263 || (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2264 return -EINVAL;
2265
2266 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2267 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2268 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2269 tx_max_coal);
2270
2271 priv->rdintcm = rdintcm;
2272 priv->tdintcm = tdintcm;
2273
2274 WRITE_REG(priv, regRDINTCM0, rdintcm);
2275 WRITE_REG(priv, regTDINTCM0, tdintcm);
2276
2277 return 0;
2278}
2279
2280/* Convert RX fifo size to number of pending packets */
2281static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2282{
2283 return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc));
2284}
2285
2286/* Convert TX fifo size to number of pending packets */
2287static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2288{
2289 return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ);
2290}
2291
2292/*
2293 * bdx_get_ringparam - report ring sizes
2294 * @netdev
2295 * @ring
2296 */
2297static void
2298bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2299{
2300 struct bdx_priv *priv = netdev->priv;
2301
2302 /*max_pending - the maximum-sized FIFO we allow */
2303 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2304 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2305 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2306 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2307}
2308
2309/*
2310 * bdx_set_ringparam - set ring sizes
2311 * @netdev
2312 * @ring
2313 */
2314static int
2315bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2316{
2317 struct bdx_priv *priv = netdev->priv;
2318 int rx_size = 0;
2319 int tx_size = 0;
2320
2321 for (; rx_size < 4; rx_size++) {
2322 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2323 break;
2324 }
2325 if (rx_size == 4)
2326 rx_size = 3;
2327
2328 for (; tx_size < 4; tx_size++) {
2329 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2330 break;
2331 }
2332 if (tx_size == 4)
2333 tx_size = 3;
2334
2335 /*Is there anything to do? */
2336 if ((rx_size == priv->rxf_size)
2337 && (tx_size == priv->txd_size))
2338 return 0;
2339
2340 priv->rxf_size = rx_size;
2341 if (rx_size > 1)
2342 priv->rxd_size = rx_size - 1;
2343 else
2344 priv->rxd_size = rx_size;
2345
2346 priv->txf_size = priv->txd_size = tx_size;
2347
2348 if (netif_running(netdev)) {
2349 bdx_close(netdev);
2350 bdx_open(netdev);
2351 }
2352 return 0;
2353}
2354
2355/*
2356 * bdx_get_strings - return a set of strings that describe the requested objects
2357 * @netdev
2358 * @data
2359 */
2360static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2361{
2362 switch (stringset) {
2363 case ETH_SS_TEST:
2364 memcpy(data, *bdx_test_names, sizeof(bdx_test_names));
2365 break;
2366 case ETH_SS_STATS:
2367 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2368 break;
2369 }
2370}
2371
2372/*
2373 * bdx_get_stats_count - return number of 64bit statistics counters
2374 * @netdev
2375 */
2376static int bdx_get_stats_count(struct net_device *netdev)
2377{
2378 struct bdx_priv *priv = netdev->priv;
2379 BDX_ASSERT(sizeof(bdx_stat_names) / ETH_GSTRING_LEN
2380 != sizeof(struct bdx_stats) / sizeof(u64));
2381 return ((priv->stats_flag) ? (sizeof(bdx_stat_names) / ETH_GSTRING_LEN)
2382 : 0);
2383}
2384
2385/*
2386 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2387 * @netdev
2388 * @stats
2389 * @data
2390 */
2391static void bdx_get_ethtool_stats(struct net_device *netdev,
2392 struct ethtool_stats *stats, u64 *data)
2393{
2394 struct bdx_priv *priv = netdev->priv;
2395
2396 if (priv->stats_flag) {
2397
2398 /* Update stats from HW */
2399 bdx_update_stats(priv);
2400
2401 /* Copy data to user buffer */
2402 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2403 }
2404}
2405
2406/*
2407 * bdx_ethtool_ops - ethtool interface implementation
2408 * @netdev
2409 */
2410static void bdx_ethtool_ops(struct net_device *netdev)
2411{
2412 static struct ethtool_ops bdx_ethtool_ops = {
2413 .get_settings = bdx_get_settings,
2414 .get_drvinfo = bdx_get_drvinfo,
2415 .get_link = ethtool_op_get_link,
2416 .get_coalesce = bdx_get_coalesce,
2417 .set_coalesce = bdx_set_coalesce,
2418 .get_ringparam = bdx_get_ringparam,
2419 .set_ringparam = bdx_set_ringparam,
2420 .get_rx_csum = bdx_get_rx_csum,
2421 .get_tx_csum = bdx_get_tx_csum,
2422 .get_sg = ethtool_op_get_sg,
2423 .get_tso = ethtool_op_get_tso,
2424 .get_strings = bdx_get_strings,
2425 .get_stats_count = bdx_get_stats_count,
2426 .get_ethtool_stats = bdx_get_ethtool_stats,
2427 };
2428
2429 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
2430}
2431
2432/**
2433 * bdx_remove - Device Removal Routine
2434 * @pdev: PCI device information struct
2435 *
2436 * bdx_remove is called by the PCI subsystem to alert the driver
2437 * that it should release a PCI device. The could be caused by a
2438 * Hot-Plug event, or because the driver is going to be removed from
2439 * memory.
2440 **/
2441static void __devexit bdx_remove(struct pci_dev *pdev)
2442{
2443 struct pci_nic *nic = pci_get_drvdata(pdev);
2444 struct net_device *ndev;
2445 int port;
2446
2447 for (port = 0; port < nic->port_num; port++) {
2448 ndev = nic->priv[port]->ndev;
2449 unregister_netdev(ndev);
2450 free_netdev(ndev);
2451 }
2452
2453 /*bdx_hw_reset_direct(nic->regs); */
2454#ifdef BDX_MSI
2455 if (nic->irq_type == IRQ_MSI)
2456 pci_disable_msi(pdev);
2457#endif
2458
2459 iounmap(nic->regs);
2460 pci_release_regions(pdev);
2461 pci_disable_device(pdev);
2462 pci_set_drvdata(pdev, NULL);
2463 vfree(nic);
2464
2465 RET();
2466}
2467
2468static struct pci_driver bdx_pci_driver = {
2469 .name = BDX_DRV_NAME,
2470 .id_table = bdx_pci_tbl,
2471 .probe = bdx_probe,
2472 .remove = __devexit_p(bdx_remove),
2473};
2474
2475/*
2476 * print_driver_id - print parameters of the driver build
2477 */
2478static void __init print_driver_id(void)
2479{
2480 printk(KERN_INFO "%s: %s, %s\n", BDX_DRV_NAME, BDX_DRV_DESC,
2481 BDX_DRV_VERSION);
2482 printk(KERN_INFO "%s: Options: hw_csum %s\n", BDX_DRV_NAME,
2483 BDX_MSI_STRING);
2484}
2485
2486static int __init bdx_module_init(void)
2487{
2488 ENTER;
2489 bdx_firmware_endianess();
2490 init_txd_sizes();
2491 print_driver_id();
2492 RET(pci_register_driver(&bdx_pci_driver));
2493}
2494
2495module_init(bdx_module_init);
2496
2497static void __exit bdx_module_exit(void)
2498{
2499 ENTER;
2500 pci_unregister_driver(&bdx_pci_driver);
2501 RET();
2502}
2503
2504module_exit(bdx_module_exit);
2505
2506MODULE_LICENSE("GPL");
2507MODULE_AUTHOR(DRIVER_AUTHOR);
2508MODULE_DESCRIPTION(BDX_DRV_DESC);
diff --git a/drivers/net/tehuti.h b/drivers/net/tehuti.h
new file mode 100644
index 000000000000..efd170f451b4
--- /dev/null
+++ b/drivers/net/tehuti.h
@@ -0,0 +1,564 @@
1/*
2 * Tehuti Networks(R) Network Driver
3 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef _TEHUTI_H
12#define _TEHUTI_H
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/ethtool.h>
21#include <linux/mii.h>
22#include <linux/crc32.h>
23#include <linux/uaccess.h>
24#include <linux/in.h>
25#include <linux/ip.h>
26#include <linux/tcp.h>
27#include <linux/sched.h>
28#include <linux/tty.h>
29#include <linux/if_vlan.h>
30#include <linux/version.h>
31#include <linux/interrupt.h>
32#include <linux/vmalloc.h>
33#include <asm/byteorder.h>
34
35/* Compile Time Switches */
36/* start */
37#define BDX_TSO
38#define BDX_LLTX
39#define BDX_DELAY_WPTR
40/* #define BDX_MSI */
41/* end */
42
43#if !defined CONFIG_PCI_MSI
44# undef BDX_MSI
45#endif
46
47#define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
48 NETIF_MSG_PROBE | \
49 NETIF_MSG_LINK)
50
51/* ioctl ops */
52#define BDX_OP_READ 1
53#define BDX_OP_WRITE 2
54
55/* RX copy break size */
56#define BDX_COPYBREAK 257
57
58#define DRIVER_AUTHOR "Tehuti Networks(R)"
59#define BDX_DRV_DESC "Tehuti Networks(R) Network Driver"
60#define BDX_DRV_NAME "tehuti"
61#define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC"
62#define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
63#define BDX_DRV_VERSION "7.29.3"
64
65#ifdef BDX_MSI
66# define BDX_MSI_STRING "msi "
67#else
68# define BDX_MSI_STRING ""
69#endif
70
71/* netdev tx queue len for Luxor. default value is, btw, 1000
72 * ifcontig eth1 txqueuelen 3000 - to change it at runtime */
73#define BDX_NDEV_TXQ_LEN 3000
74
75#define FIFO_SIZE 4096
76#define FIFO_EXTRA_SPACE 1024
77
78#define MIN(x, y) ((x) < (y) ? (x) : (y))
79
80#if BITS_PER_LONG == 64
81# define H32_64(x) (u32) ((u64)(x) >> 32)
82# define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
83#elif BITS_PER_LONG == 32
84# define H32_64(x) 0
85# define L32_64(x) ((u32) (x))
86#else /* BITS_PER_LONG == ?? */
87# error BITS_PER_LONG is undefined. Must be 64 or 32
88#endif /* BITS_PER_LONG */
89
90#ifdef __BIG_ENDIAN
91# define CPU_CHIP_SWAP32(x) swab32(x)
92# define CPU_CHIP_SWAP16(x) swab16(x)
93#else
94# define CPU_CHIP_SWAP32(x) (x)
95# define CPU_CHIP_SWAP16(x) (x)
96#endif
97
98#define READ_REG(pp, reg) readl(pp->pBdxRegs + reg)
99#define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg)
100
101#ifndef DMA_64BIT_MASK
102# define DMA_64BIT_MASK 0xffffffffffffffffULL
103#endif
104
105#ifndef DMA_32BIT_MASK
106# define DMA_32BIT_MASK 0x00000000ffffffffULL
107#endif
108
109#ifndef NET_IP_ALIGN
110# define NET_IP_ALIGN 2
111#endif
112
113#ifndef NETDEV_TX_OK
114# define NETDEV_TX_OK 0
115#endif
116
117#define LUXOR_MAX_PORT 2
118#define BDX_MAX_RX_DONE 150
119#define BDX_TXF_DESC_SZ 16
120#define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16)
121#define BDX_MIN_TX_LEVEL 256
122#define BDX_NO_UPD_PACKETS 40
123
124struct pci_nic {
125 int port_num;
126 void __iomem *regs;
127 int irq_type;
128 struct bdx_priv *priv[LUXOR_MAX_PORT];
129};
130
131enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX };
132
133#define PCK_TH_MULT 128
134#define INT_COAL_MULT 2
135
136#define BITS_MASK(nbits) ((1<<nbits)-1)
137#define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits))
138#define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift)
139#define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift)
140#define BITS_SHIFT_CLEAR(x, nbits, nshift) \
141 ((x)&(~BITS_SHIFT_MASK(nbits, nshift)))
142
143#define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
144#define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15)
145#define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16)
146#define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20)
147
148#define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \
149 ((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20))
150
151struct fifo {
152 dma_addr_t da; /* physical address of fifo (used by HW) */
153 char *va; /* virtual address of fifo (used by SW) */
154 u32 rptr, wptr; /* cached values of RPTR and WPTR registers,
155 they're 32 bits on both 32 and 64 archs */
156 u16 reg_CFG0, reg_CFG1;
157 u16 reg_RPTR, reg_WPTR;
158 u16 memsz; /* memory size allocated for fifo */
159 u16 size_mask;
160 u16 pktsz; /* skb packet size to allocate */
161 u16 rcvno; /* number of buffers that come from this RXF */
162};
163
164struct txf_fifo {
165 struct fifo m; /* minimal set of variables used by all fifos */
166};
167
168struct txd_fifo {
169 struct fifo m; /* minimal set of variables used by all fifos */
170};
171
172struct rxf_fifo {
173 struct fifo m; /* minimal set of variables used by all fifos */
174};
175
176struct rxd_fifo {
177 struct fifo m; /* minimal set of variables used by all fifos */
178};
179
180struct rx_map {
181 u64 dma;
182 struct sk_buff *skb;
183};
184
185struct rxdb {
186 int *stack;
187 struct rx_map *elems;
188 int nelem;
189 int top;
190};
191
192union bdx_dma_addr {
193 dma_addr_t dma;
194 struct sk_buff *skb;
195};
196
197/* Entry in the db.
198 * if len == 0 addr is dma
199 * if len != 0 addr is skb */
200struct tx_map {
201 union bdx_dma_addr addr;
202 int len;
203};
204
205/* tx database - implemented as circular fifo buffer*/
206struct txdb {
207 struct tx_map *start; /* points to the first element */
208 struct tx_map *end; /* points just AFTER the last element */
209 struct tx_map *rptr; /* points to the next element to read */
210 struct tx_map *wptr; /* points to the next element to write */
211 int size; /* number of elements in the db */
212};
213
214/*Internal stats structure*/
215struct bdx_stats {
216 u64 InUCast; /* 0x7200 */
217 u64 InMCast; /* 0x7210 */
218 u64 InBCast; /* 0x7220 */
219 u64 InPkts; /* 0x7230 */
220 u64 InErrors; /* 0x7240 */
221 u64 InDropped; /* 0x7250 */
222 u64 FrameTooLong; /* 0x7260 */
223 u64 FrameSequenceErrors; /* 0x7270 */
224 u64 InVLAN; /* 0x7280 */
225 u64 InDroppedDFE; /* 0x7290 */
226 u64 InDroppedIntFull; /* 0x72A0 */
227 u64 InFrameAlignErrors; /* 0x72B0 */
228
229 /* 0x72C0-0x72E0 RSRV */
230
231 u64 OutUCast; /* 0x72F0 */
232 u64 OutMCast; /* 0x7300 */
233 u64 OutBCast; /* 0x7310 */
234 u64 OutPkts; /* 0x7320 */
235
236 /* 0x7330-0x7360 RSRV */
237
238 u64 OutVLAN; /* 0x7370 */
239 u64 InUCastOctects; /* 0x7380 */
240 u64 OutUCastOctects; /* 0x7390 */
241
242 /* 0x73A0-0x73B0 RSRV */
243
244 u64 InBCastOctects; /* 0x73C0 */
245 u64 OutBCastOctects; /* 0x73D0 */
246 u64 InOctects; /* 0x73E0 */
247 u64 OutOctects; /* 0x73F0 */
248};
249
250struct bdx_priv {
251 void __iomem *pBdxRegs;
252 struct net_device *ndev;
253
254 struct napi_struct napi;
255
256 /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
257 struct rxd_fifo rxd_fifo0;
258 struct rxf_fifo rxf_fifo0;
259 struct rxdb *rxdb; /* rx dbs to store skb pointers */
260 int napi_stop;
261 struct vlan_group *vlgrp;
262
263 /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
264 struct txd_fifo txd_fifo0;
265 struct txf_fifo txf_fifo0;
266
267 struct txdb txdb;
268 int tx_level;
269#ifdef BDX_DELAY_WPTR
270 int tx_update_mark;
271 int tx_noupd;
272#endif
273 spinlock_t tx_lock; /* NETIF_F_LLTX mode */
274
275 /* rarely used */
276 u8 port;
277 u32 msg_enable;
278 int stats_flag;
279 struct bdx_stats hw_stats;
280 struct net_device_stats net_stats;
281 struct pci_dev *pdev;
282
283 struct pci_nic *nic;
284
285 u8 txd_size;
286 u8 txf_size;
287 u8 rxd_size;
288 u8 rxf_size;
289 u32 rdintcm;
290 u32 tdintcm;
291};
292
293/* RX FREE descriptor - 64bit*/
294struct rxf_desc {
295 u32 info; /* Buffer Count + Info - described below */
296 u32 va_lo; /* VAdr[31:0] */
297 u32 va_hi; /* VAdr[63:32] */
298 u32 pa_lo; /* PAdr[31:0] */
299 u32 pa_hi; /* PAdr[63:32] */
300 u32 len; /* Buffer Length */
301};
302
303#define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0)
304#define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8)
305#define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15)
306#define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16)
307#define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21)
308#define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27)
309#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28)
310#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31)
311#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0)
312#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12)
313#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13)
314
315struct rxd_desc {
316 u32 rxd_val1;
317 u16 len;
318 u16 rxd_vlan;
319 u32 va_lo;
320 u32 va_hi;
321};
322
323/* PBL describes each virtual buffer to be */
324/* transmitted from the host.*/
325struct pbl {
326 u32 pa_lo;
327 u32 pa_hi;
328 u32 len;
329};
330
331/* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
332 * hw_csum = 7 for ip+udp+tcp hw checksums */
333#define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \
334 ((bc) | ((checksum)<<5) | ((vtag)<<8) | \
335 ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))
336
337struct txd_desc {
338 u32 txd_val1;
339 u16 mss;
340 u16 length;
341 u32 va_lo;
342 u32 va_hi;
343 struct pbl pbl[0]; /* Fragments */
344} __attribute__ ((packed));
345
346/* Register region size */
347#define BDX_REGS_SIZE 0x1000
348
349/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
350#define regTXD_CFG1_0 0x4000
351#define regRXF_CFG1_0 0x4010
352#define regRXD_CFG1_0 0x4020
353#define regTXF_CFG1_0 0x4030
354#define regTXD_CFG0_0 0x4040
355#define regRXF_CFG0_0 0x4050
356#define regRXD_CFG0_0 0x4060
357#define regTXF_CFG0_0 0x4070
358#define regTXD_WPTR_0 0x4080
359#define regRXF_WPTR_0 0x4090
360#define regRXD_WPTR_0 0x40A0
361#define regTXF_WPTR_0 0x40B0
362#define regTXD_RPTR_0 0x40C0
363#define regRXF_RPTR_0 0x40D0
364#define regRXD_RPTR_0 0x40E0
365#define regTXF_RPTR_0 0x40F0
366#define regTXF_RPTR_3 0x40FC
367
368/* hardware versioning */
369#define FW_VER 0x5010
370#define SROM_VER 0x5020
371#define FPGA_VER 0x5030
372#define FPGA_SEED 0x5040
373
374/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
375#define regISR regISR0
376#define regISR0 0x5100
377
378#define regIMR regIMR0
379#define regIMR0 0x5110
380
381#define regRDINTCM0 0x5120
382#define regRDINTCM2 0x5128
383
384#define regTDINTCM0 0x5130
385
386#define regISR_MSK0 0x5140
387
388#define regINIT_SEMAPHORE 0x5170
389#define regINIT_STATUS 0x5180
390
391#define regMAC_LNK_STAT 0x0200
392#define MAC_LINK_STAT 0x4 /* Link state */
393
394#define regGMAC_RXF_A 0x1240
395
396#define regUNC_MAC0_A 0x1250
397#define regUNC_MAC1_A 0x1260
398#define regUNC_MAC2_A 0x1270
399
400#define regVLAN_0 0x1800
401
402#define regMAX_FRAME_A 0x12C0
403
404#define regRX_MAC_MCST0 0x1A80
405#define regRX_MAC_MCST1 0x1A84
406#define MAC_MCST_NUM 15
407#define regRX_MCST_HASH0 0x1A00
408#define MAC_MCST_HASH_NUM 8
409
410#define regVPC 0x2300
411#define regVIC 0x2320
412#define regVGLB 0x2340
413
414#define regCLKPLL 0x5000
415
416/*for 10G only*/
417#define regREVISION 0x6000
418#define regSCRATCH 0x6004
419#define regCTRLST 0x6008
420#define regMAC_ADDR_0 0x600C
421#define regMAC_ADDR_1 0x6010
422#define regFRM_LENGTH 0x6014
423#define regPAUSE_QUANT 0x6018
424#define regRX_FIFO_SECTION 0x601C
425#define regTX_FIFO_SECTION 0x6020
426#define regRX_FULLNESS 0x6024
427#define regTX_FULLNESS 0x6028
428#define regHASHTABLE 0x602C
429#define regMDIO_ST 0x6030
430#define regMDIO_CTL 0x6034
431#define regMDIO_DATA 0x6038
432#define regMDIO_ADDR 0x603C
433
434#define regRST_PORT 0x7000
435#define regDIS_PORT 0x7010
436#define regRST_QU 0x7020
437#define regDIS_QU 0x7030
438
439#define regCTRLST_TX_ENA 0x0001
440#define regCTRLST_RX_ENA 0x0002
441#define regCTRLST_PRM_ENA 0x0010
442#define regCTRLST_PAD_ENA 0x0020
443
444#define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA)
445
446#define regRX_FLT 0x1400
447
448/* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/
449#define TX_RX_CFG1_BASE 0xffffffff /*0-31 */
450#define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */
451#define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */
452#define TX_RX_CFG0_SIZE 0x0003 /*1:0 */
453
454/* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */
455#define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */
456
457/* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */
458#define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */
459
460#define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped
461 * size is rounded to 16 */
462
463/* regISR 0x0100 */
464/* regIMR 0x0110 */
465#define IMR_INPROG 0x80000000 /*31 */
466#define IR_LNKCHG1 0x10000000 /*28 */
467#define IR_LNKCHG0 0x08000000 /*27 */
468#define IR_GPIO 0x04000000 /*26 */
469#define IR_RFRSH 0x02000000 /*25 */
470#define IR_RSVD 0x01000000 /*24 */
471#define IR_SWI 0x00800000 /*23 */
472#define IR_RX_FREE_3 0x00400000 /*22 */
473#define IR_RX_FREE_2 0x00200000 /*21 */
474#define IR_RX_FREE_1 0x00100000 /*20 */
475#define IR_RX_FREE_0 0x00080000 /*19 */
476#define IR_TX_FREE_3 0x00040000 /*18 */
477#define IR_TX_FREE_2 0x00020000 /*17 */
478#define IR_TX_FREE_1 0x00010000 /*16 */
479#define IR_TX_FREE_0 0x00008000 /*15 */
480#define IR_RX_DESC_3 0x00004000 /*14 */
481#define IR_RX_DESC_2 0x00002000 /*13 */
482#define IR_RX_DESC_1 0x00001000 /*12 */
483#define IR_RX_DESC_0 0x00000800 /*11 */
484#define IR_PSE 0x00000400 /*10 */
485#define IR_TMR3 0x00000200 /*9 */
486#define IR_TMR2 0x00000100 /*8 */
487#define IR_TMR1 0x00000080 /*7 */
488#define IR_TMR0 0x00000040 /*6 */
489#define IR_VNT 0x00000020 /*5 */
490#define IR_RxFL 0x00000010 /*4 */
491#define IR_SDPERR 0x00000008 /*3 */
492#define IR_TR 0x00000004 /*2 */
493#define IR_PCIE_LINK 0x00000002 /*1 */
494#define IR_PCIE_TOUT 0x00000001 /*0 */
495
496#define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \
497 IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT)
498#define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0)
499#define IR_ALL 0xfdfffff7
500
501#define IR_LNKCHG0_ofst 27
502
503#define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */
504#define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */
505#define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */
506#define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */
507#define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */
508#define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */
509#define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */
510#define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */
511#define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */
512#define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */
513#define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscous mode */
514
515#define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */
516
517#define CLKPLL_PLLLKD 0x0200 /*9 */
518#define CLKPLL_RSTEND 0x0100 /*8 */
519#define CLKPLL_SFTRST 0x0001 /*0 */
520
521#define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND)
522
523/*
524 * PCI-E Device Control Register (Offset 0x88)
525 * Source: Luxor Data Sheet, 7.1.3.3.3
526 */
527#define PCI_DEV_CTRL_REG 0x88
528#define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5)
529#define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12)
530
531/*
532 * PCI-E Link Status Register (Offset 0x92)
533 * Source: Luxor Data Sheet, 7.1.3.3.7
534 */
535#define PCI_LINK_STATUS_REG 0x92
536#define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4)
537
538/* Debugging Macros */
539
540#define ERR(fmt, args...) printk(KERN_ERR fmt, ## args)
541#define DBG2(fmt, args...) \
542 printk(KERN_ERR "%s:%-5d: " fmt, __FUNCTION__, __LINE__, ## args)
543
544#define BDX_ASSERT(x) BUG_ON(x)
545
546#ifdef DEBUG
547
548#define ENTER do { \
549 printk(KERN_ERR "%s:%-5d: ENTER\n", __FUNCTION__, __LINE__); \
550} while (0)
551
552#define RET(args...) do { \
553 printk(KERN_ERR "%s:%-5d: RETURN\n", __FUNCTION__, __LINE__); \
554return args; } while (0)
555
556#define DBG(fmt, args...) \
557 printk(KERN_ERR "%s:%-5d: " fmt, __FUNCTION__, __LINE__, ## args)
558#else
559#define ENTER do { } while (0)
560#define RET(args...) return args
561#define DBG(fmt, args...) do { } while (0)
562#endif
563
564#endif /* _BDX__H */
diff --git a/drivers/net/tehuti_fw.h b/drivers/net/tehuti_fw.h
new file mode 100644
index 000000000000..2c603a8a4383
--- /dev/null
+++ b/drivers/net/tehuti_fw.h
@@ -0,0 +1,10712 @@
1/*
2 * Tehuti Networks(R) Network Driver
3 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11/* Loading Firmware */
12/* INT_MEM Ver */
13static u32 s_firmLoad[] = {
14 0x000f0002,
15 0x40718000,
16 0x0000002d,
17 0xc0000000,
18 0x000f0002,
19 0x00718001,
20 0x0000002d,
21 0xc0800000,
22 0x000f0002,
23 0x00718002,
24 0x0000002d,
25 0xc1000000,
26 0x000f0002,
27 0x00718003,
28 0x0000002d,
29 0xc1800000,
30 0x000f0002,
31 0x00718004,
32 0x0000002d,
33 0xc2000000,
34 0x000f0002,
35 0x00718005,
36 0x0000002d,
37 0xc2800000,
38 0x000f0002,
39 0x00718006,
40 0x0000002d,
41 0xc3000000,
42 0x000f0002,
43 0x00718007,
44 0x0000002d,
45 0xc3800000,
46 0x000f0002,
47 0x00718008,
48 0x0000002d,
49 0xc4000000,
50 0x000f0002,
51 0x00718009,
52 0x0000002d,
53 0xc4800000,
54 0x000f0002,
55 0x0071800a,
56 0x0000002d,
57 0xc5000000,
58 0x000f0002,
59 0x0071800b,
60 0x0000002d,
61 0xc5800000,
62 0x000f0002,
63 0x0071800c,
64 0x0000002d,
65 0xc6000000,
66 0x000f0002,
67 0x0071800d,
68 0x0000002d,
69 0xc6800000,
70 0x000f0002,
71 0x0071800e,
72 0x0000002d,
73 0xc7000000,
74 0x000f0002,
75 0x0071800f,
76 0x0000002d,
77 0xc7800000,
78 0x000f0002,
79 0x00718010,
80 0x0000002d,
81 0xc8000000,
82 0x000f0002,
83 0x00718011,
84 0x0000002d,
85 0xc8800000,
86 0x000f0002,
87 0x00718012,
88 0x0000002d,
89 0xc9000000,
90 0x000f0002,
91 0x00718013,
92 0x0000002d,
93 0xc9800000,
94 0x000f0002,
95 0x00718014,
96 0x0000002d,
97 0xca000000,
98 0x000f0002,
99 0x00718015,
100 0x0000002d,
101 0xca800000,
102 0x000f0002,
103 0x00718016,
104 0x0000002d,
105 0xcb000000,
106 0x000f0002,
107 0x00718017,
108 0x0000002d,
109 0xcb800000,
110 0x000f0002,
111 0x00718018,
112 0x0000002d,
113 0xcc000000,
114 0x000f0002,
115 0x00718019,
116 0x0000002d,
117 0xcc800000,
118 0x000f0002,
119 0x0071801a,
120 0x0000002d,
121 0xcd000000,
122 0x000f0002,
123 0x0071801b,
124 0x0000002d,
125 0xcd800000,
126 0x000f0002,
127 0x0071801c,
128 0x0000002d,
129 0xce000000,
130 0x000f0002,
131 0x0071801d,
132 0x0000002d,
133 0xce800000,
134 0x000f0002,
135 0x0071801e,
136 0x0000002d,
137 0xcf000000,
138 0x000f0002,
139 0x0071801f,
140 0x0000002d,
141 0xcf800000,
142 0x000f0002,
143 0x00718020,
144 0x0000002d,
145 0xd0000000,
146 0x000f0002,
147 0x00718021,
148 0x0000002d,
149 0xd0800000,
150 0x000f0002,
151 0x00718022,
152 0x0000002d,
153 0xd1000000,
154 0x000f0002,
155 0x00718023,
156 0x0000002d,
157 0xd1800000,
158 0x000f0002,
159 0x00718024,
160 0x0000002d,
161 0xd2000000,
162 0x000f0002,
163 0x00718025,
164 0x0000002d,
165 0xd2800000,
166 0x000f0002,
167 0x00718026,
168 0x0000002d,
169 0xd3000000,
170 0x000f0002,
171 0x00718027,
172 0x0000002d,
173 0xd3800000,
174 0x000f0002,
175 0x00718028,
176 0x0000002d,
177 0xd4000000,
178 0x000f0002,
179 0x00718029,
180 0x0000002d,
181 0xd4800000,
182 0x000f0002,
183 0x0071802a,
184 0x0000002d,
185 0xd5000000,
186 0x000f0002,
187 0x0071802b,
188 0x0000002d,
189 0xd5800000,
190 0x000f0002,
191 0x0071802c,
192 0x0000002d,
193 0xd6000000,
194 0x000f0002,
195 0x0071802d,
196 0x0000002d,
197 0xd6800000,
198 0x000f0002,
199 0x0071802e,
200 0x0000002d,
201 0xd7000000,
202 0x000f0002,
203 0x0071802f,
204 0x0000002d,
205 0xd7800000,
206 0x000f0002,
207 0x00718030,
208 0x0000002d,
209 0xd8000000,
210 0x000f0002,
211 0x00718031,
212 0x0000002d,
213 0xd8800000,
214 0x000f0002,
215 0x00718032,
216 0x0000002d,
217 0xd9000000,
218 0x000f0002,
219 0x00718033,
220 0x0000002d,
221 0xd9800000,
222 0x000f0002,
223 0x00718034,
224 0x0000002d,
225 0xda000000,
226 0x000f0002,
227 0x00718035,
228 0x0000002d,
229 0xda800000,
230 0x000f0002,
231 0x00718036,
232 0x0000002d,
233 0xdb000000,
234 0x000f0002,
235 0x00718037,
236 0x0000002d,
237 0xdb800000,
238 0x000f0002,
239 0x00718038,
240 0x0000007b,
241 0xdd608000,
242 0x000f0002,
243 0x00718039,
244 0x0000002d,
245 0xdd000000,
246 0x000f0002,
247 0x0071803a,
248 0x0000002d,
249 0xdb800000,
250 0x000f0002,
251 0x0071803b,
252 0x0000002d,
253 0xdd000000,
254 0x000f0002,
255 0x0071803c,
256 0x0000002d,
257 0xdd000000,
258 0x000f0002,
259 0x0071803d,
260 0x00000000,
261 0x00000000,
262 0x000f0002,
263 0x0071803e,
264 0x00000000,
265 0x00000000,
266 0x000f0002,
267 0x0071803f,
268 0x00000000,
269 0x00000000,
270 0x000f0002,
271 0x00718040,
272 0x00000000,
273 0x00000000,
274 0x000f0002,
275 0x00718041,
276 0x00000000,
277 0x00000000,
278 0x000f0002,
279 0x00718042,
280 0x00000000,
281 0x00000000,
282 0x000f0002,
283 0x00718043,
284 0x00000000,
285 0x00000000,
286 0x000f0002,
287 0x00718044,
288 0x00000000,
289 0x00000000,
290 0x000f0002,
291 0x00718045,
292 0x00000000,
293 0x00000000,
294 0x000f0002,
295 0x00718046,
296 0x00000000,
297 0x00000000,
298 0x000f0002,
299 0x00718047,
300 0x00000000,
301 0x00000000,
302 0x000f0002,
303 0x00718048,
304 0x00000000,
305 0x00000000,
306 0x000f0002,
307 0x00718049,
308 0x00000000,
309 0x00000000,
310 0x000f0002,
311 0x0071804a,
312 0x00000000,
313 0x00000000,
314 0x000f0002,
315 0x0071804b,
316 0x00000000,
317 0x00000000,
318 0x000f0002,
319 0x0071804c,
320 0x00000000,
321 0x00000000,
322 0x000f0002,
323 0x0071804d,
324 0x00000000,
325 0x00000000,
326 0x000f0002,
327 0x0071804e,
328 0x00000000,
329 0x00000000,
330 0x000f0002,
331 0x0071804f,
332 0x00000000,
333 0x00000000,
334 0x000f0002,
335 0x00718050,
336 0x00000000,
337 0x00000000,
338 0x000f0002,
339 0x00718051,
340 0x00000000,
341 0x00000000,
342 0x000f0002,
343 0x00718052,
344 0x00000000,
345 0x00000000,
346 0x000f0002,
347 0x00718053,
348 0x00000000,
349 0x00000000,
350 0x000f0002,
351 0x00718054,
352 0x00000000,
353 0x00000000,
354 0x000f0002,
355 0x00718055,
356 0x00000000,
357 0x00000000,
358 0x000f0002,
359 0x00718056,
360 0x00000000,
361 0x00000000,
362 0x000f0002,
363 0x00718057,
364 0x00000000,
365 0x00000000,
366 0x000f0002,
367 0x00718058,
368 0x00000000,
369 0x00000000,
370 0x000f0002,
371 0x00718059,
372 0x00000000,
373 0x00000000,
374 0x000f0002,
375 0x0071805a,
376 0x00000000,
377 0x00000000,
378 0x000f0002,
379 0x0071805b,
380 0x00000000,
381 0x00000000,
382 0x000f0002,
383 0x0071805c,
384 0x00000000,
385 0x00000000,
386 0x000f0002,
387 0x0071805d,
388 0x00000000,
389 0x00000000,
390 0x000f0002,
391 0x0071805e,
392 0x00000000,
393 0x00000000,
394 0x000f0002,
395 0x0071805f,
396 0x00000000,
397 0x00000000,
398 0x000f0002,
399 0x00718060,
400 0x00000000,
401 0x00000000,
402 0x000f0002,
403 0x00718061,
404 0x00000000,
405 0x00000000,
406 0x000f0002,
407 0x00718062,
408 0x00000000,
409 0x00000000,
410 0x000f0002,
411 0x00718063,
412 0x00000000,
413 0x00000000,
414 0x000f0002,
415 0x00718064,
416 0x0000002d,
417 0xdb000000,
418 0x000f0002,
419 0x00718065,
420 0x0000003f,
421 0xdd000104,
422 0x000f0002,
423 0x00718066,
424 0x0000003f,
425 0xdd180001,
426 0x000f0002,
427 0x00718067,
428 0x00000069,
429 0xdd003d7a,
430 0x000f0002,
431 0x00718068,
432 0x0000003f,
433 0xdd000804,
434 0x000f0002,
435 0x00718069,
436 0x00000069,
437 0xdd003d7a,
438 0x000f0002,
439 0x0071806a,
440 0x0000003f,
441 0xdd003004,
442 0x000f0002,
443 0x0071806b,
444 0x0000003f,
445 0xdd180001,
446 0x000f0002,
447 0x0071806c,
448 0x00000069,
449 0xdd003d7a,
450 0x000f0002,
451 0x0071806d,
452 0x0000003f,
453 0xdd000004,
454 0x000f0002,
455 0x0071806e,
456 0x00000069,
457 0xdd003d7a,
458 0x000f0002,
459 0x0071806f,
460 0x0000003f,
461 0xdd003d04,
462 0x000f0002,
463 0x00718070,
464 0x0000003f,
465 0xdd180001,
466 0x000f0002,
467 0x00718071,
468 0x00000069,
469 0xdd003d7a,
470 0x000f0002,
471 0x00718072,
472 0x0000003f,
473 0xdd000704,
474 0x000f0002,
475 0x00718073,
476 0x00000069,
477 0xdd003d7a,
478 0x000f0002,
479 0x00718074,
480 0x0000003f,
481 0xdd002884,
482 0x000f0002,
483 0x00718075,
484 0x0000003f,
485 0xdd180001,
486 0x000f0002,
487 0x00718076,
488 0x00000069,
489 0xdd003d7a,
490 0x000f0002,
491 0x00718077,
492 0x0000003f,
493 0xdd003704,
494 0x000f0002,
495 0x00718078,
496 0x00000069,
497 0xdd003d7a,
498 0x000f0002,
499 0x00718079,
500 0x0000003f,
501 0xdd002904,
502 0x000f0002,
503 0x0071807a,
504 0x0000003f,
505 0xdd180001,
506 0x000f0002,
507 0x0071807b,
508 0x00000069,
509 0xdd003d7a,
510 0x000f0002,
511 0x0071807c,
512 0x0000003f,
513 0xdd04aa04,
514 0x000f0002,
515 0x0071807d,
516 0x00000069,
517 0xdd003d7a,
518 0x000f0002,
519 0x0071807e,
520 0x0000003f,
521 0xdd002804,
522 0x000f0002,
523 0x0071807f,
524 0x0000003f,
525 0xdd180001,
526 0x000f0002,
527 0x00718080,
528 0x00000069,
529 0xdd003d7a,
530 0x000f0002,
531 0x00718081,
532 0x0000003f,
533 0xdd003104,
534 0x000f0002,
535 0x00718082,
536 0x00000069,
537 0xdd003d7a,
538 0x000f0002,
539 0x00718083,
540 0x0000003f,
541 0xdd002b84,
542 0x000f0002,
543 0x00718084,
544 0x0000003f,
545 0xdd180001,
546 0x000f0002,
547 0x00718085,
548 0x00000069,
549 0xdd003d7a,
550 0x000f0002,
551 0x00718086,
552 0x0000003f,
553 0xdd01e404,
554 0x000f0002,
555 0x00718087,
556 0x00000069,
557 0xdd003d7a,
558 0x000f0002,
559 0x00718088,
560 0x0000003f,
561 0xd7800084,
562 0x000f0002,
563 0x00718089,
564 0x0000003f,
565 0xd7980001,
566 0x000f0002,
567 0x0071808a,
568 0x00000059,
569 0xd78037ef,
570 0x000f0002,
571 0x0071808b,
572 0x0000003d,
573 0xf780006f,
574 0x000f0002,
575 0x0071808c,
576 0x0000003d,
577 0xf780006f,
578 0x000f0002,
579 0x0071808d,
580 0x0000003d,
581 0xf780006f,
582 0x000f0002,
583 0x0071808e,
584 0x0000002d,
585 0xd7d6027f,
586 0x000f0002,
587 0x0071808f,
588 0x00000018,
589 0x17ff0081,
590 0x000f0002,
591 0x00718090,
592 0x0000003d,
593 0xf780006f,
594 0x000f0002,
595 0x00718091,
596 0x0000003d,
597 0xf780006f,
598 0x000f0002,
599 0x00718092,
600 0x0000002d,
601 0xd7d800b8,
602 0x000f0002,
603 0x00718093,
604 0x00000018,
605 0x17eb0081,
606 0x000f0002,
607 0x00718094,
608 0x0000003f,
609 0xdd002904,
610 0x000f0002,
611 0x00718095,
612 0x0000003f,
613 0xdd180001,
614 0x000f0002,
615 0x00718096,
616 0x00000069,
617 0xdd003d7a,
618 0x000f0002,
619 0x00718097,
620 0x0000003f,
621 0xdd04aa84,
622 0x000f0002,
623 0x00718098,
624 0x00000069,
625 0xdd003d7a,
626 0x000f0002,
627 0x00718099,
628 0x0000003f,
629 0xdd002b04,
630 0x000f0002,
631 0x0071809a,
632 0x0000003f,
633 0xdd180001,
634 0x000f0002,
635 0x0071809b,
636 0x00000069,
637 0xdd003d7a,
638 0x000f0002,
639 0x0071809c,
640 0x0000003f,
641 0xdd000004,
642 0x000f0002,
643 0x0071809d,
644 0x00000069,
645 0xdd003d7a,
646 0x000f0002,
647 0x0071809e,
648 0x0000003f,
649 0xdd002984,
650 0x000f0002,
651 0x0071809f,
652 0x0000003f,
653 0xdd180001,
654 0x000f0002,
655 0x007180a0,
656 0x00000069,
657 0xdd003d7a,
658 0x000f0002,
659 0x007180a1,
660 0x0000003f,
661 0xdd000004,
662 0x000f0002,
663 0x007180a2,
664 0x00000069,
665 0xdd003d7a,
666 0x000f0002,
667 0x007180a3,
668 0x0000003f,
669 0xdd002a04,
670 0x000f0002,
671 0x007180a4,
672 0x0000003f,
673 0xdd180001,
674 0x000f0002,
675 0x007180a5,
676 0x00000069,
677 0xdd003d7a,
678 0x000f0002,
679 0x007180a6,
680 0x0000003f,
681 0xdd009184,
682 0x000f0002,
683 0x007180a7,
684 0x00000069,
685 0xdd003d7a,
686 0x000f0002,
687 0x007180a8,
688 0x0000003f,
689 0xd6801984,
690 0x000f0002,
691 0x007180a9,
692 0x0000003f,
693 0xd6800001,
694 0x000f0002,
695 0x007180aa,
696 0x00000035,
697 0xd68000ed,
698 0x000f0002,
699 0x007180ab,
700 0x00000018,
701 0x37ff0081,
702 0x000f0002,
703 0x007180ac,
704 0x0000003f,
705 0xdd002b04,
706 0x000f0002,
707 0x007180ad,
708 0x0000003f,
709 0xdd180001,
710 0x000f0002,
711 0x007180ae,
712 0x00000069,
713 0xdd003d7a,
714 0x000f0002,
715 0x007180af,
716 0x0000003f,
717 0xdd000004,
718 0x000f0002,
719 0x007180b0,
720 0x00000069,
721 0xdd003d7a,
722 0x000f0002,
723 0x007180b1,
724 0x0000003f,
725 0xdd002a84,
726 0x000f0002,
727 0x007180b2,
728 0x0000003f,
729 0xdd180001,
730 0x000f0002,
731 0x007180b3,
732 0x00000069,
733 0xdd003d7a,
734 0x000f0002,
735 0x007180b4,
736 0x0000003f,
737 0xdd000004,
738 0x000f0002,
739 0x007180b5,
740 0x00000069,
741 0xdd003d7a,
742 0x000f0002,
743 0x007180b6,
744 0x0000003f,
745 0xd6800c84,
746 0x000f0002,
747 0x007180b7,
748 0x0000003f,
749 0xd6800001,
750 0x000f0002,
751 0x007180b8,
752 0x00000035,
753 0xd68000ed,
754 0x000f0002,
755 0x007180b9,
756 0x00000018,
757 0x37ff0081,
758 0x000f0002,
759 0x007180ba,
760 0x0000003f,
761 0xdd002a84,
762 0x000f0002,
763 0x007180bb,
764 0x0000003f,
765 0xdd180001,
766 0x000f0002,
767 0x007180bc,
768 0x00000069,
769 0xdd003d7a,
770 0x000f0002,
771 0x007180bd,
772 0x0000003f,
773 0xdd000004,
774 0x000f0002,
775 0x007180be,
776 0x00000069,
777 0xdd003d7a,
778 0x000f0002,
779 0x007180bf,
780 0x0000003f,
781 0xd6800f84,
782 0x000f0002,
783 0x007180c0,
784 0x0000003f,
785 0xd6800001,
786 0x000f0002,
787 0x007180c1,
788 0x00000035,
789 0xd68000ed,
790 0x000f0002,
791 0x007180c2,
792 0x00000018,
793 0x37ff0081,
794 0x000f0002,
795 0x007180c3,
796 0x0000003f,
797 0xdd002a04,
798 0x000f0002,
799 0x007180c4,
800 0x0000003f,
801 0xdd180001,
802 0x000f0002,
803 0x007180c5,
804 0x00000069,
805 0xdd003d7a,
806 0x000f0002,
807 0x007180c6,
808 0x0000003f,
809 0xdd001184,
810 0x000f0002,
811 0x007180c7,
812 0x00000069,
813 0xdd003d7a,
814 0x000f0002,
815 0x007180c8,
816 0x0000003f,
817 0xdd002884,
818 0x000f0002,
819 0x007180c9,
820 0x0000003f,
821 0xdd180001,
822 0x000f0002,
823 0x007180ca,
824 0x00000069,
825 0xdd003d7a,
826 0x000f0002,
827 0x007180cb,
828 0x0000003f,
829 0xdd003784,
830 0x000f0002,
831 0x007180cc,
832 0x00000069,
833 0xdd003d7a,
834 0x000f0002,
835 0x007180cd,
836 0x0000002d,
837 0xd3800000,
838 0x000f0002,
839 0x007180ce,
840 0x0000003f,
841 0xd2003780,
842 0x000f0002,
843 0x007180cf,
844 0x0000003f,
845 0xd1800404,
846 0x000f0002,
847 0x007180d0,
848 0x0000003f,
849 0xd1840001,
850 0x000f0002,
851 0x007180d1,
852 0x00000069,
853 0xdd003b76,
854 0x000f0002,
855 0x007180d2,
856 0x00000069,
857 0xdd003b76,
858 0x000f0002,
859 0x007180d3,
860 0x00000069,
861 0xdd003b76,
862 0x000f0002,
863 0x007180d4,
864 0x0000003f,
865 0xd17fff84,
866 0x000f0002,
867 0x007180d5,
868 0x0000003f,
869 0xd17fff81,
870 0x000f0002,
871 0x007180d6,
872 0x00000069,
873 0xdd003b76,
874 0x000f0002,
875 0x007180d7,
876 0x00000069,
877 0xdd003b76,
878 0x000f0002,
879 0x007180d8,
880 0x00000069,
881 0xdd003b76,
882 0x000f0002,
883 0x007180d9,
884 0x00000069,
885 0xdd003b76,
886 0x000f0002,
887 0x007180da,
888 0x00000069,
889 0xdd003b76,
890 0x000f0002,
891 0x007180db,
892 0x00000069,
893 0xdd003b76,
894 0x000f0002,
895 0x007180dc,
896 0x0000003f,
897 0xd6800784,
898 0x000f0002,
899 0x007180dd,
900 0x0000003f,
901 0xd6800001,
902 0x000f0002,
903 0x007180de,
904 0x00000035,
905 0xd68000ed,
906 0x000f0002,
907 0x007180df,
908 0x00000018,
909 0x37ff0081,
910 0x000f0002,
911 0x007180e0,
912 0x00000049,
913 0xdd003b63,
914 0x000f0002,
915 0x007180e1,
916 0x00000059,
917 0xdd003b76,
918 0x000f0002,
919 0x007180e2,
920 0x0000003d,
921 0xf780006f,
922 0x000f0002,
923 0x007180e3,
924 0x0000003d,
925 0xf780006f,
926 0x000f0002,
927 0x007180e4,
928 0x0000003d,
929 0xf780006f,
930 0x000f0002,
931 0x007180e5,
932 0x0000002d,
933 0xdd06027f,
934 0x000f0002,
935 0x007180e6,
936 0x00000018,
937 0x1d7f3d7a,
938 0x000f0002,
939 0x007180e7,
940 0x00000045,
941 0xdd003139,
942 0x000f0002,
943 0x007180e8,
944 0x00000094,
945 0x000b313b,
946 0x000f0002,
947 0x007180e9,
948 0x00000094,
949 0x0009313d,
950 0x000f0002,
951 0x007180ea,
952 0x00000094,
953 0x0007313f,
954 0x000f0002,
955 0x007180eb,
956 0x00000094,
957 0x00053b76,
958 0x000f0002,
959 0x007180ec,
960 0x00000009,
961 0xc1ed3d7a,
962 0x000f0002,
963 0x007180ed,
964 0x0000003f,
965 0xd200b780,
966 0x000f0002,
967 0x007180ee,
968 0x0000003f,
969 0xdd002884,
970 0x000f0002,
971 0x007180ef,
972 0x0000003f,
973 0xdd180001,
974 0x000f0002,
975 0x007180f0,
976 0x00000069,
977 0xdd003264,
978 0x000f0002,
979 0x007180f1,
980 0x00000069,
981 0xdd003d7a,
982 0x000f0002,
983 0x007180f2,
984 0x0000003f,
985 0xd6800784,
986 0x000f0002,
987 0x007180f3,
988 0x0000003f,
989 0xd6800001,
990 0x000f0002,
991 0x007180f4,
992 0x00000035,
993 0xd68000ed,
994 0x000f0002,
995 0x007180f5,
996 0x00000018,
997 0x37ff0081,
998 0x000f0002,
999 0x007180f6,
1000 0x00000049,
1001 0xdd003b63,
1002 0x000f0002,
1003 0x007180f7,
1004 0x00000059,
1005 0xdd003b76,
1006 0x000f0002,
1007 0x007180f8,
1008 0x0000003d,
1009 0xf780006f,
1010 0x000f0002,
1011 0x007180f9,
1012 0x0000003d,
1013 0xf780006f,
1014 0x000f0002,
1015 0x007180fa,
1016 0x0000003d,
1017 0xf780006f,
1018 0x000f0002,
1019 0x007180fb,
1020 0x0000002d,
1021 0xdd06027f,
1022 0x000f0002,
1023 0x007180fc,
1024 0x00000018,
1025 0x1d7f3d7a,
1026 0x000f0002,
1027 0x007180fd,
1028 0x00000045,
1029 0xdd00313a,
1030 0x000f0002,
1031 0x007180fe,
1032 0x00000018,
1033 0x1d2d3b76,
1034 0x000f0002,
1035 0x007180ff,
1036 0x00000045,
1037 0xdd00313c,
1038 0x000f0002,
1039 0x00718100,
1040 0x00000018,
1041 0x1d133b76,
1042 0x000f0002,
1043 0x00718101,
1044 0x00000045,
1045 0xdd00313e,
1046 0x000f0002,
1047 0x00718102,
1048 0x00000018,
1049 0x1d1b3b76,
1050 0x000f0002,
1051 0x00718103,
1052 0x0000003f,
1053 0xdd003004,
1054 0x000f0002,
1055 0x00718104,
1056 0x0000003f,
1057 0xdd180001,
1058 0x000f0002,
1059 0x00718105,
1060 0x00000069,
1061 0xdd003d7a,
1062 0x000f0002,
1063 0x00718106,
1064 0x0000003f,
1065 0xdd000104,
1066 0x000f0002,
1067 0x00718107,
1068 0x00000069,
1069 0xdd003d7a,
1070 0x000f0002,
1071 0x00718108,
1072 0x00000009,
1073 0xc52d3d7a,
1074 0x000f0002,
1075 0x00718109,
1076 0x00000029,
1077 0xd2010064,
1078 0x000f0002,
1079 0x0071810a,
1080 0x0000003f,
1081 0xdd002884,
1082 0x000f0002,
1083 0x0071810b,
1084 0x0000003f,
1085 0xdd180001,
1086 0x000f0002,
1087 0x0071810c,
1088 0x00000069,
1089 0xdd003264,
1090 0x000f0002,
1091 0x0071810d,
1092 0x00000069,
1093 0xdd003d7a,
1094 0x000f0002,
1095 0x0071810e,
1096 0x00000009,
1097 0xc2293d7a,
1098 0x000f0002,
1099 0x0071810f,
1100 0x00000029,
1101 0xd2000064,
1102 0x000f0002,
1103 0x00718110,
1104 0x0000003f,
1105 0xdd002884,
1106 0x000f0002,
1107 0x00718111,
1108 0x0000003f,
1109 0xdd180001,
1110 0x000f0002,
1111 0x00718112,
1112 0x00000069,
1113 0xdd003264,
1114 0x000f0002,
1115 0x00718113,
1116 0x00000069,
1117 0xdd003d7a,
1118 0x000f0002,
1119 0x00718114,
1120 0x00000049,
1121 0xdd003b63,
1122 0x000f0002,
1123 0x00718115,
1124 0x00000059,
1125 0xdd003b76,
1126 0x000f0002,
1127 0x00718116,
1128 0x0000003d,
1129 0xf780006f,
1130 0x000f0002,
1131 0x00718117,
1132 0x0000003d,
1133 0xf780006f,
1134 0x000f0002,
1135 0x00718118,
1136 0x0000003d,
1137 0xf780006f,
1138 0x000f0002,
1139 0x00718119,
1140 0x0000002d,
1141 0xdd06027f,
1142 0x000f0002,
1143 0x0071811a,
1144 0x00000018,
1145 0x1d7f3d7a,
1146 0x000f0002,
1147 0x0071811b,
1148 0x00000045,
1149 0xdd00313a,
1150 0x000f0002,
1151 0x0071811c,
1152 0x00000018,
1153 0x1d0f3b76,
1154 0x000f0002,
1155 0x0071811d,
1156 0x0000003f,
1157 0xdd003004,
1158 0x000f0002,
1159 0x0071811e,
1160 0x0000003f,
1161 0xdd180001,
1162 0x000f0002,
1163 0x0071811f,
1164 0x00000069,
1165 0xdd003d7a,
1166 0x000f0002,
1167 0x00718120,
1168 0x0000003f,
1169 0xdd000104,
1170 0x000f0002,
1171 0x00718121,
1172 0x00000069,
1173 0xdd003d7a,
1174 0x000f0002,
1175 0x00718122,
1176 0x00000009,
1177 0xc52d3d7a,
1178 0x000f0002,
1179 0x00718123,
1180 0x0000002d,
1181 0xd1080082,
1182 0x000f0002,
1183 0x00718124,
1184 0x00000008,
1185 0x23c33d7a,
1186 0x000f0002,
1187 0x00718125,
1188 0x00000049,
1189 0xd6003b0a,
1190 0x000f0002,
1191 0x00718126,
1192 0x0000003f,
1193 0xd3000004,
1194 0x000f0002,
1195 0x00718127,
1196 0x0000003f,
1197 0xd3040001,
1198 0x000f0002,
1199 0x00718128,
1200 0x0000002f,
1201 0xd6814085,
1202 0x000f0002,
1203 0x00718129,
1204 0x0000003f,
1205 0xd4ffff84,
1206 0x000f0002,
1207 0x0071812a,
1208 0x0000003f,
1209 0xd4800781,
1210 0x000f0002,
1211 0x0071812b,
1212 0x0000003f,
1213 0xd1ffff84,
1214 0x000f0002,
1215 0x0071812c,
1216 0x0000003f,
1217 0xd1800001,
1218 0x000f0002,
1219 0x0071812d,
1220 0x00000049,
1221 0xdd003666,
1222 0x000f0002,
1223 0x0071812e,
1224 0x00000069,
1225 0xdd003b76,
1226 0x000f0002,
1227 0x0071812f,
1228 0x00000069,
1229 0xdd003b76,
1230 0x000f0002,
1231 0x00718130,
1232 0x00000069,
1233 0xdd003b76,
1234 0x000f0002,
1235 0x00718131,
1236 0x00000069,
1237 0xdd003b69,
1238 0x000f0002,
1239 0x00718132,
1240 0x00000069,
1241 0xdd003b76,
1242 0x000f0002,
1243 0x00718133,
1244 0x00000069,
1245 0xdd003b76,
1246 0x000f0002,
1247 0x00718134,
1248 0x00000069,
1249 0xdd003b76,
1250 0x000f0002,
1251 0x00718135,
1252 0x00000069,
1253 0xdd003b69,
1254 0x000f0002,
1255 0x00718136,
1256 0x00000061,
1257 0xf600046c,
1258 0x000f0002,
1259 0x00718137,
1260 0x00000035,
1261 0xd68000ed,
1262 0x000f0002,
1263 0x00718138,
1264 0x00000018,
1265 0x3d6b0081,
1266 0x000f0002,
1267 0x00718139,
1268 0x00000049,
1269 0xd600058b,
1270 0x000f0002,
1271 0x0071813a,
1272 0x0000002f,
1273 0xd6810106,
1274 0x000f0002,
1275 0x0071813b,
1276 0x0000002d,
1277 0xd2000000,
1278 0x000f0002,
1279 0x0071813c,
1280 0x00000021,
1281 0xd20000e4,
1282 0x000f0002,
1283 0x0071813d,
1284 0x0000003d,
1285 0xf780006f,
1286 0x000f0002,
1287 0x0071813e,
1288 0x0000002d,
1289 0xdd06017f,
1290 0x000f0002,
1291 0x0071813f,
1292 0x00000018,
1293 0x1d7f3d7a,
1294 0x000f0002,
1295 0x00718140,
1296 0x00000049,
1297 0xd800366c,
1298 0x000f0002,
1299 0x00718141,
1300 0x00000069,
1301 0xd80033e7,
1302 0x000f0002,
1303 0x00718142,
1304 0x00000069,
1305 0xd80033e7,
1306 0x000f0002,
1307 0x00718143,
1308 0x00000069,
1309 0xd80037ef,
1310 0x000f0002,
1311 0x00718144,
1312 0x00000031,
1313 0xd600016c,
1314 0x000f0002,
1315 0x00718145,
1316 0x0000002d,
1317 0xd1000000,
1318 0x000f0002,
1319 0x00718146,
1320 0x00000049,
1321 0xd17a33e4,
1322 0x000f0002,
1323 0x00718147,
1324 0x0000002f,
1325 0xd1710162,
1326 0x000f0002,
1327 0x00718148,
1328 0x0000002f,
1329 0xd1610162,
1330 0x000f0002,
1331 0x00718149,
1332 0x00000049,
1333 0xd14033e3,
1334 0x000f0002,
1335 0x0071814a,
1336 0x0000003d,
1337 0xf780006f,
1338 0x000f0002,
1339 0x0071814b,
1340 0x0000002d,
1341 0xdd06017f,
1342 0x000f0002,
1343 0x0071814c,
1344 0x00000018,
1345 0x1d7f3d7a,
1346 0x000f0002,
1347 0x0071814d,
1348 0x00000049,
1349 0xd800366c,
1350 0x000f0002,
1351 0x0071814e,
1352 0x00000069,
1353 0xd80033e7,
1354 0x000f0002,
1355 0x0071814f,
1356 0x00000069,
1357 0xd8003162,
1358 0x000f0002,
1359 0x00718150,
1360 0x00000069,
1361 0xd80037ef,
1362 0x000f0002,
1363 0x00718151,
1364 0x00000031,
1365 0xd600016c,
1366 0x000f0002,
1367 0x00718152,
1368 0x0000003d,
1369 0xf780006f,
1370 0x000f0002,
1371 0x00718153,
1372 0x0000002d,
1373 0xdd06017f,
1374 0x000f0002,
1375 0x00718154,
1376 0x00000018,
1377 0x1d7f3d7a,
1378 0x000f0002,
1379 0x00718155,
1380 0x00000049,
1381 0xd800366c,
1382 0x000f0002,
1383 0x00718156,
1384 0x00000069,
1385 0xd80033e7,
1386 0x000f0002,
1387 0x00718157,
1388 0x00000069,
1389 0xd80033e7,
1390 0x000f0002,
1391 0x00718158,
1392 0x00000069,
1393 0xd80037ef,
1394 0x000f0002,
1395 0x00718159,
1396 0x00000031,
1397 0xd600016c,
1398 0x000f0002,
1399 0x0071815a,
1400 0x0000002d,
1401 0xd1000000,
1402 0x000f0002,
1403 0x0071815b,
1404 0x0000002d,
1405 0xd16c07e4,
1406 0x000f0002,
1407 0x0071815c,
1408 0x00000049,
1409 0xd14033e3,
1410 0x000f0002,
1411 0x0071815d,
1412 0x0000003d,
1413 0xf780006f,
1414 0x000f0002,
1415 0x0071815e,
1416 0x0000002d,
1417 0xdd06017f,
1418 0x000f0002,
1419 0x0071815f,
1420 0x00000018,
1421 0x1d7f3d7a,
1422 0x000f0002,
1423 0x00718160,
1424 0x00000049,
1425 0xd800366c,
1426 0x000f0002,
1427 0x00718161,
1428 0x00000069,
1429 0xd80033e7,
1430 0x000f0002,
1431 0x00718162,
1432 0x00000069,
1433 0xd8003162,
1434 0x000f0002,
1435 0x00718163,
1436 0x00000069,
1437 0xd80037ef,
1438 0x000f0002,
1439 0x00718164,
1440 0x00000031,
1441 0xd600016c,
1442 0x000f0002,
1443 0x00718165,
1444 0x0000003d,
1445 0xf780006f,
1446 0x000f0002,
1447 0x00718166,
1448 0x0000002d,
1449 0xdd06017f,
1450 0x000f0002,
1451 0x00718167,
1452 0x00000018,
1453 0x1d7f3d7a,
1454 0x000f0002,
1455 0x00718168,
1456 0x00000049,
1457 0xd800366c,
1458 0x000f0002,
1459 0x00718169,
1460 0x00000069,
1461 0xd80033e7,
1462 0x000f0002,
1463 0x0071816a,
1464 0x00000069,
1465 0xd80033e7,
1466 0x000f0002,
1467 0x0071816b,
1468 0x00000069,
1469 0xd80037ef,
1470 0x000f0002,
1471 0x0071816c,
1472 0x00000031,
1473 0xd600016c,
1474 0x000f0002,
1475 0x0071816d,
1476 0x0000002d,
1477 0xd1000000,
1478 0x000f0002,
1479 0x0071816e,
1480 0x00000049,
1481 0xd17833e4,
1482 0x000f0002,
1483 0x0071816f,
1484 0x0000002f,
1485 0xd1710162,
1486 0x000f0002,
1487 0x00718170,
1488 0x0000002f,
1489 0xd1610162,
1490 0x000f0002,
1491 0x00718171,
1492 0x00000049,
1493 0xd14033e3,
1494 0x000f0002,
1495 0x00718172,
1496 0x0000003d,
1497 0xf780006f,
1498 0x000f0002,
1499 0x00718173,
1500 0x0000002d,
1501 0xdd06017f,
1502 0x000f0002,
1503 0x00718174,
1504 0x00000018,
1505 0x1d7f3d7a,
1506 0x000f0002,
1507 0x00718175,
1508 0x00000049,
1509 0xd800366c,
1510 0x000f0002,
1511 0x00718176,
1512 0x00000069,
1513 0xd80033e7,
1514 0x000f0002,
1515 0x00718177,
1516 0x00000069,
1517 0xd8003162,
1518 0x000f0002,
1519 0x00718178,
1520 0x00000069,
1521 0xd80037ef,
1522 0x000f0002,
1523 0x00718179,
1524 0x00000031,
1525 0xd600016c,
1526 0x000f0002,
1527 0x0071817a,
1528 0x0000003d,
1529 0xf780006f,
1530 0x000f0002,
1531 0x0071817b,
1532 0x0000002d,
1533 0xdd06017f,
1534 0x000f0002,
1535 0x0071817c,
1536 0x00000018,
1537 0x1d7f3d7a,
1538 0x000f0002,
1539 0x0071817d,
1540 0x00000049,
1541 0xd800366c,
1542 0x000f0002,
1543 0x0071817e,
1544 0x00000069,
1545 0xd80033e7,
1546 0x000f0002,
1547 0x0071817f,
1548 0x00000069,
1549 0xd80033e7,
1550 0x000f0002,
1551 0x00718180,
1552 0x00000069,
1553 0xd80037ef,
1554 0x000f0002,
1555 0x00718181,
1556 0x00000031,
1557 0xd600016c,
1558 0x000f0002,
1559 0x00718182,
1560 0x0000002d,
1561 0xd1000000,
1562 0x000f0002,
1563 0x00718183,
1564 0x0000002d,
1565 0xd16807e4,
1566 0x000f0002,
1567 0x00718184,
1568 0x00000049,
1569 0xd14033e3,
1570 0x000f0002,
1571 0x00718185,
1572 0x0000003d,
1573 0xf780006f,
1574 0x000f0002,
1575 0x00718186,
1576 0x0000002d,
1577 0xdd06017f,
1578 0x000f0002,
1579 0x00718187,
1580 0x00000018,
1581 0x1d7f3d7a,
1582 0x000f0002,
1583 0x00718188,
1584 0x00000049,
1585 0xd800366c,
1586 0x000f0002,
1587 0x00718189,
1588 0x00000069,
1589 0xd80033e7,
1590 0x000f0002,
1591 0x0071818a,
1592 0x00000069,
1593 0xd8003162,
1594 0x000f0002,
1595 0x0071818b,
1596 0x00000069,
1597 0xd80037ef,
1598 0x000f0002,
1599 0x0071818c,
1600 0x00000031,
1601 0xd600016c,
1602 0x000f0002,
1603 0x0071818d,
1604 0x00000035,
1605 0xd68000ed,
1606 0x000f0002,
1607 0x0071818e,
1608 0x00000008,
1609 0x22790081,
1610 0x000f0002,
1611 0x0071818f,
1612 0x00000049,
1613 0xd600060c,
1614 0x000f0002,
1615 0x00718190,
1616 0x0000002f,
1617 0xd6810106,
1618 0x000f0002,
1619 0x00718191,
1620 0x0000003f,
1621 0xd4800002,
1622 0x000f0002,
1623 0x00718192,
1624 0x0000003f,
1625 0xd4800084,
1626 0x000f0002,
1627 0x00718193,
1628 0x0000003f,
1629 0xd5000102,
1630 0x000f0002,
1631 0x00718194,
1632 0x0000003f,
1633 0xd5000184,
1634 0x000f0002,
1635 0x00718195,
1636 0x0000003f,
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1653 0x1d7f3d7a,
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1800 0x00000035,
1801 0xd68000ed,
1802 0x000f0002,
1803 0x007181bf,
1804 0x00000018,
1805 0x37ed0081,
1806 0x000f0002,
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1810 0x000f0002,
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1813 0xd5020004,
1814 0x000f0002,
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1816 0x0000003f,
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1833 0xd50000ea,
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1837 0xdd0e3b6a,
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1845 0x37f50081,
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1856 0x0000003f,
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1861 0xdd003b69,
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1873 0xf50000ea,
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1876 0x0000003d,
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1893 0x37f50081,
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1896 0x0000003f,
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1900 0x0000003f,
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1905 0xd6804000,
1906 0x000f0002,
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1908 0x0000003f,
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1911 0x007181da,
1912 0x00000025,
1913 0xde2000e2,
1914 0x000f0002,
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1937 0x37f50081,
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1940 0x0000003f,
1941 0xdd003004,
1942 0x000f0002,
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1944 0x0000003f,
1945 0xdd180001,
1946 0x000f0002,
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1949 0xdd001d3a,
1950 0x000f0002,
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1953 0xdd003d7a,
1954 0x000f0002,
1955 0x007181e5,
1956 0x0000007d,
1957 0xc760a713,
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1960 0x00000031,
1961 0xc0800041,
1962 0x000f0002,
1963 0x007181e7,
1964 0x00000031,
1965 0xc4000048,
1966 0x000f0002,
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1968 0x00000031,
1969 0xc2800045,
1970 0x000f0002,
1971 0x007181e9,
1972 0x00000000,
1973 0x00000000,
1974 0x000f0002,
1975 0x007181ea,
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1977 0x00000000,
1978 0x000f0002,
1979 0x007181eb,
1980 0x00000000,
1981 0x00000000,
1982 0x000f0002,
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1984 0x00000000,
1985 0x00000000,
1986 0x000f0002,
1987 0x007181ed,
1988 0x00000000,
1989 0x00000000,
1990 0x000f0002,
1991 0x007181ee,
1992 0x00000000,
1993 0x00000000,
1994 0x000f0002,
1995 0x007181ef,
1996 0x00000000,
1997 0x00000000,
1998 0x000f0002,
1999 0x007181f0,
2000 0x00000000,
2001 0x00000000,
2002 0x000f0002,
2003 0x007181f1,
2004 0x00000000,
2005 0x00000000,
2006 0x000f0002,
2007 0x007181f2,
2008 0x00000000,
2009 0x00000000,
2010 0x000f0002,
2011 0x007181f3,
2012 0x00000000,
2013 0x00000000,
2014 0x000f0002,
2015 0x007181f4,
2016 0x0000002d,
2017 0xdb000000,
2018 0x000f0002,
2019 0x007181f5,
2020 0x0000003f,
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2321 0xdd003d7a,
2322 0x000f0002,
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2453 0xdd001804,
2454 0x000f0002,
2455 0x00718262,
2456 0x0000003f,
2457 0xdd180001,
2458 0x000f0002,
2459 0x00718263,
2460 0x00000069,
2461 0xdd000b97,
2462 0x000f0002,
2463 0x00718264,
2464 0x00000069,
2465 0xdd003d7a,
2466 0x000f0002,
2467 0x00718265,
2468 0x00000049,
2469 0xd1043397,
2470 0x000f0002,
2471 0x00718266,
2472 0x0000003f,
2473 0xdd001884,
2474 0x000f0002,
2475 0x00718267,
2476 0x0000003f,
2477 0xdd180001,
2478 0x000f0002,
2479 0x00718268,
2480 0x00000069,
2481 0xdd003162,
2482 0x000f0002,
2483 0x00718269,
2484 0x00000069,
2485 0xdd003d7a,
2486 0x000f0002,
2487 0x0071826a,
2488 0x0000003f,
2489 0xdd001904,
2490 0x000f0002,
2491 0x0071826b,
2492 0x0000003f,
2493 0xdd180001,
2494 0x000f0002,
2495 0x0071826c,
2496 0x00000069,
2497 0xdd000c18,
2498 0x000f0002,
2499 0x0071826d,
2500 0x00000069,
2501 0xdd003d7a,
2502 0x000f0002,
2503 0x0071826e,
2504 0x00000049,
2505 0xd1043398,
2506 0x000f0002,
2507 0x0071826f,
2508 0x0000003f,
2509 0xdd001984,
2510 0x000f0002,
2511 0x00718270,
2512 0x0000003f,
2513 0xdd180001,
2514 0x000f0002,
2515 0x00718271,
2516 0x00000069,
2517 0xdd003162,
2518 0x000f0002,
2519 0x00718272,
2520 0x00000069,
2521 0xdd003d7a,
2522 0x000f0002,
2523 0x00718273,
2524 0x0000003f,
2525 0xdd001a04,
2526 0x000f0002,
2527 0x00718274,
2528 0x0000003f,
2529 0xdd180001,
2530 0x000f0002,
2531 0x00718275,
2532 0x00000069,
2533 0xdd003d7a,
2534 0x000f0002,
2535 0x00718276,
2536 0x0000003f,
2537 0xdd000004,
2538 0x000f0002,
2539 0x00718277,
2540 0x00000069,
2541 0xdd003d7a,
2542 0x000f0002,
2543 0x00718278,
2544 0x0000003f,
2545 0xdd001a84,
2546 0x000f0002,
2547 0x00718279,
2548 0x0000003f,
2549 0xdd180001,
2550 0x000f0002,
2551 0x0071827a,
2552 0x00000069,
2553 0xdd000b16,
2554 0x000f0002,
2555 0x0071827b,
2556 0x00000069,
2557 0xdd003d7a,
2558 0x000f0002,
2559 0x0071827c,
2560 0x0000003f,
2561 0xdd001c04,
2562 0x000f0002,
2563 0x0071827d,
2564 0x0000003f,
2565 0xdd180001,
2566 0x000f0002,
2567 0x0071827e,
2568 0x00000069,
2569 0xdd000c99,
2570 0x000f0002,
2571 0x0071827f,
2572 0x00000069,
2573 0xdd003d7a,
2574 0x000f0002,
2575 0x00718280,
2576 0x0000003f,
2577 0xdd001c84,
2578 0x000f0002,
2579 0x00718281,
2580 0x0000003f,
2581 0xdd180001,
2582 0x000f0002,
2583 0x00718282,
2584 0x00000069,
2585 0xdd000d1a,
2586 0x000f0002,
2587 0x00718283,
2588 0x00000069,
2589 0xdd003d7a,
2590 0x000f0002,
2591 0x00718284,
2592 0x0000003f,
2593 0xdd001d04,
2594 0x000f0002,
2595 0x00718285,
2596 0x0000003f,
2597 0xdd180001,
2598 0x000f0002,
2599 0x00718286,
2600 0x00000069,
2601 0xdd000d9b,
2602 0x000f0002,
2603 0x00718287,
2604 0x00000069,
2605 0xdd003d7a,
2606 0x000f0002,
2607 0x00718288,
2608 0x00000049,
2609 0xd104339b,
2610 0x000f0002,
2611 0x00718289,
2612 0x0000003f,
2613 0xdd001d84,
2614 0x000f0002,
2615 0x0071828a,
2616 0x0000003f,
2617 0xdd180001,
2618 0x000f0002,
2619 0x0071828b,
2620 0x00000069,
2621 0xdd003162,
2622 0x000f0002,
2623 0x0071828c,
2624 0x00000069,
2625 0xdd003d7a,
2626 0x000f0002,
2627 0x0071828d,
2628 0x0000003f,
2629 0xdd001e04,
2630 0x000f0002,
2631 0x0071828e,
2632 0x0000003f,
2633 0xdd180001,
2634 0x000f0002,
2635 0x0071828f,
2636 0x00000069,
2637 0xdd000e1c,
2638 0x000f0002,
2639 0x00718290,
2640 0x00000069,
2641 0xdd003d7a,
2642 0x000f0002,
2643 0x00718291,
2644 0x0000003f,
2645 0xdd000104,
2646 0x000f0002,
2647 0x00718292,
2648 0x0000003f,
2649 0xdd180001,
2650 0x000f0002,
2651 0x00718293,
2652 0x00000069,
2653 0xdd003d7a,
2654 0x000f0002,
2655 0x00718294,
2656 0x0000003f,
2657 0xdd000f04,
2658 0x000f0002,
2659 0x00718295,
2660 0x00000069,
2661 0xdd003d7a,
2662 0x000f0002,
2663 0x00718296,
2664 0x0000007d,
2665 0xc760a713,
2666 0x000f0002,
2667 0x00718297,
2668 0x00000031,
2669 0xc0800041,
2670 0x000f0002,
2671 0x00718298,
2672 0x00000031,
2673 0xc4000048,
2674 0x000f0002,
2675 0x00718299,
2676 0x00000031,
2677 0xc2800045,
2678 0x000f0002,
2679 0x0071829a,
2680 0x00000031,
2681 0xd680006d,
2682/* BRDX_INIT_SDRAM */
2683 0x000f000f,
2684 0x00700064,
2685 0x00000000,
2686 0x00000000,
2687 0x00000000,
2688 0x00000040,
2689 0x00000100,
2690 0x00000400,
2691 0x00000064,
2692 0x00000054,
2693 0x00000000,
2694 0x00002400,
2695 0x00002800,
2696 0x00000400,
2697 0x00002880,
2698 0x00000180,
2699 0x00000003,
2700 0x00000000,
2701 0x00000000,
2702 0x00000000,
2703 0x00000051,
2704 0x0000017d,
2705 0x00000008,
2706 0x00000051,
2707 0x0000005d,
2708 0x00000000,
2709 0x00000009,
2710 0x00005000,
2711 0x00000000,
2712 0x00000000,
2713/* BRDX_INIT */
2714 0x000f000f,
2715 0x007001f4,
2716 0x00000000,
2717 0x00000000,
2718 0x00000000,
2719 0x00000040,
2720 0x00000100,
2721 0x00000400,
2722 0x00000064,
2723 0x00000054,
2724 0x00000000,
2725 0x00002400,
2726 0x00002800,
2727 0x00000400,
2728 0x00002880,
2729 0x00000180,
2730 0x00000003,
2731 0x00000000,
2732 0x00000000,
2733 0x00000000,
2734 0x00000051,
2735 0x0000017d,
2736 0x00000008,
2737 0x00000051,
2738 0x0000005d,
2739 0x00000000,
2740 0x00000009,
2741 0x00005000,
2742 0x00000000,
2743 0x00000000,
2744/* ZERO_INIT */
2745 0x000f0002,
2746 0x00700000,
2747 0x00000001,
2748 0x00000000,
2749/* ZERO_INIT */
2750 0x000f0002,
2751 0x00700000,
2752 0x00000001,
2753 0x00000000,
2754/* Loading operational Firmware */
2755 0x000f0002,
2756 0x00718000,
2757 0x00000025,
2758 0xdd0e0002,
2759 0x000f0002,
2760 0x00718001,
2761 0x00000004,
2762 0x01d13b76,
2763 0x000f0002,
2764 0x00718002,
2765 0x00000025,
2766 0xdd0e0082,
2767 0x000f0002,
2768 0x00718003,
2769 0x00000004,
2770 0x02893b76,
2771 0x000f0002,
2772 0x00718004,
2773 0x00000025,
2774 0xdd0e0102,
2775 0x000f0002,
2776 0x00718005,
2777 0x00000004,
2778 0x02853b76,
2779 0x000f0002,
2780 0x00718006,
2781 0x00000025,
2782 0xdd0e0182,
2783 0x000f0002,
2784 0x00718007,
2785 0x00000004,
2786 0x03fd3b76,
2787 0x000f0002,
2788 0x00718008,
2789 0x00000009,
2790 0xcf813b76,
2791 0x000f0002,
2792 0x00718009,
2793 0x00000000,
2794 0x00000000,
2795 0x000f0002,
2796 0x0071800a,
2797 0x00000000,
2798 0x00000000,
2799 0x000f0002,
2800 0x0071800b,
2801 0x00000000,
2802 0x00000000,
2803 0x000f0002,
2804 0x0071800c,
2805 0x00000000,
2806 0x00000000,
2807 0x000f0002,
2808 0x0071800d,
2809 0x00000000,
2810 0x00000000,
2811 0x000f0002,
2812 0x0071800e,
2813 0x00000000,
2814 0x00000000,
2815 0x000f0002,
2816 0x0071800f,
2817 0x00000000,
2818 0x00000000,
2819 0x000f0002,
2820 0x00718010,
2821 0x00000000,
2822 0x00000000,
2823 0x000f0002,
2824 0x00718011,
2825 0x00000000,
2826 0x00000000,
2827 0x000f0002,
2828 0x00718012,
2829 0x00000000,
2830 0x00000000,
2831 0x000f0002,
2832 0x00718013,
2833 0x00000000,
2834 0x00000000,
2835 0x000f0002,
2836 0x00718014,
2837 0x00000000,
2838 0x00000000,
2839 0x000f0002,
2840 0x00718015,
2841 0x00000000,
2842 0x00000000,
2843 0x000f0002,
2844 0x00718016,
2845 0x00000000,
2846 0x00000000,
2847 0x000f0002,
2848 0x00718017,
2849 0x00000000,
2850 0x00000000,
2851 0x000f0002,
2852 0x00718018,
2853 0x00000000,
2854 0x00000000,
2855 0x000f0002,
2856 0x00718019,
2857 0x00000000,
2858 0x00000000,
2859 0x000f0002,
2860 0x0071801a,
2861 0x00000000,
2862 0x00000000,
2863 0x000f0002,
2864 0x0071801b,
2865 0x00000000,
2866 0x00000000,
2867 0x000f0002,
2868 0x0071801c,
2869 0x00000000,
2870 0x00000000,
2871 0x000f0002,
2872 0x0071801d,
2873 0x00000000,
2874 0x00000000,
2875 0x000f0002,
2876 0x0071801e,
2877 0x00000000,
2878 0x00000000,
2879 0x000f0002,
2880 0x0071801f,
2881 0x00000000,
2882 0x00000000,
2883 0x000f0002,
2884 0x00718020,
2885 0x00000000,
2886 0x00000000,
2887 0x000f0002,
2888 0x00718021,
2889 0x00000000,
2890 0x00000000,
2891 0x000f0002,
2892 0x00718022,
2893 0x00000000,
2894 0x00000000,
2895 0x000f0002,
2896 0x00718023,
2897 0x00000000,
2898 0x00000000,
2899 0x000f0002,
2900 0x00718024,
2901 0x00000000,
2902 0x00000000,
2903 0x000f0002,
2904 0x00718025,
2905 0x00000000,
2906 0x00000000,
2907 0x000f0002,
2908 0x00718026,
2909 0x00000000,
2910 0x00000000,
2911 0x000f0002,
2912 0x00718027,
2913 0x00000000,
2914 0x00000000,
2915 0x000f0002,
2916 0x00718028,
2917 0x00000049,
2918 0xc0003b00,
2919 0x000f0002,
2920 0x00718029,
2921 0x00000049,
2922 0xc0803b02,
2923 0x000f0002,
2924 0x0071802a,
2925 0x00000049,
2926 0xc1003b03,
2927 0x000f0002,
2928 0x0071802b,
2929 0x00000049,
2930 0xc1803b04,
2931 0x000f0002,
2932 0x0071802c,
2933 0x00000029,
2934 0xdf600076,
2935 0x000f0002,
2936 0x0071802d,
2937 0x00000049,
2938 0xdf443b7d,
2939 0x000f0002,
2940 0x0071802e,
2941 0x00000079,
2942 0xfd609076,
2943 0x000f0002,
2944 0x0071802f,
2945 0x0000003d,
2946 0xf780006f,
2947 0x000f0002,
2948 0x00718030,
2949 0x0000003d,
2950 0xf780006f,
2951 0x000f0002,
2952 0x00718031,
2953 0x0000003d,
2954 0xf780006f,
2955 0x000f0002,
2956 0x00718032,
2957 0x0000003d,
2958 0xf780006f,
2959 0x000f0002,
2960 0x00718033,
2961 0x00000000,
2962 0x00000000,
2963 0x000f0002,
2964 0x00718034,
2965 0x00000000,
2966 0x00000000,
2967 0x000f0002,
2968 0x00718035,
2969 0x00000000,
2970 0x00000000,
2971 0x000f0002,
2972 0x00718036,
2973 0x00000000,
2974 0x00000000,
2975 0x000f0002,
2976 0x00718037,
2977 0x00000000,
2978 0x00000000,
2979 0x000f0002,
2980 0x00718038,
2981 0x00000000,
2982 0x00000000,
2983 0x000f0002,
2984 0x00718039,
2985 0x00000000,
2986 0x00000000,
2987 0x000f0002,
2988 0x0071803a,
2989 0x00000000,
2990 0x00000000,
2991 0x000f0002,
2992 0x0071803b,
2993 0x00000000,
2994 0x00000000,
2995 0x000f0002,
2996 0x0071803c,
2997 0x00000000,
2998 0x00000000,
2999 0x000f0002,
3000 0x0071803d,
3001 0x00000000,
3002 0x00000000,
3003 0x000f0002,
3004 0x0071803e,
3005 0x00000000,
3006 0x00000000,
3007 0x000f0002,
3008 0x0071803f,
3009 0x00000000,
3010 0x00000000,
3011 0x000f0002,
3012 0x00718040,
3013 0x00000000,
3014 0x00000000,
3015 0x000f0002,
3016 0x00718041,
3017 0x00000000,
3018 0x00000000,
3019 0x000f0002,
3020 0x00718042,
3021 0x00000000,
3022 0x00000000,
3023 0x000f0002,
3024 0x00718043,
3025 0x00000000,
3026 0x00000000,
3027 0x000f0002,
3028 0x00718044,
3029 0x00000000,
3030 0x00000000,
3031 0x000f0002,
3032 0x00718045,
3033 0x00000000,
3034 0x00000000,
3035 0x000f0002,
3036 0x00718046,
3037 0x00000000,
3038 0x00000000,
3039 0x000f0002,
3040 0x00718047,
3041 0x00000000,
3042 0x00000000,
3043 0x000f0002,
3044 0x00718048,
3045 0x00000000,
3046 0x00000000,
3047 0x000f0002,
3048 0x00718049,
3049 0x00000000,
3050 0x00000000,
3051 0x000f0002,
3052 0x0071804a,
3053 0x00000000,
3054 0x00000000,
3055 0x000f0002,
3056 0x0071804b,
3057 0x00000000,
3058 0x00000000,
3059 0x000f0002,
3060 0x0071804c,
3061 0x00000000,
3062 0x00000000,
3063 0x000f0002,
3064 0x0071804d,
3065 0x00000000,
3066 0x00000000,
3067 0x000f0002,
3068 0x0071804e,
3069 0x00000000,
3070 0x00000000,
3071 0x000f0002,
3072 0x0071804f,
3073 0x00000000,
3074 0x00000000,
3075 0x000f0002,
3076 0x00718050,
3077 0x00000000,
3078 0x00000000,
3079 0x000f0002,
3080 0x00718051,
3081 0x00000000,
3082 0x00000000,
3083 0x000f0002,
3084 0x00718052,
3085 0x00000000,
3086 0x00000000,
3087 0x000f0002,
3088 0x00718053,
3089 0x00000000,
3090 0x00000000,
3091 0x000f0002,
3092 0x00718054,
3093 0x00000000,
3094 0x00000000,
3095 0x000f0002,
3096 0x00718055,
3097 0x00000000,
3098 0x00000000,
3099 0x000f0002,
3100 0x00718056,
3101 0x00000000,
3102 0x00000000,
3103 0x000f0002,
3104 0x00718057,
3105 0x00000000,
3106 0x00000000,
3107 0x000f0002,
3108 0x00718058,
3109 0x00000000,
3110 0x00000000,
3111 0x000f0002,
3112 0x00718059,
3113 0x00000000,
3114 0x00000000,
3115 0x000f0002,
3116 0x0071805a,
3117 0x00000000,
3118 0x00000000,
3119 0x000f0002,
3120 0x0071805b,
3121 0x00000000,
3122 0x00000000,
3123 0x000f0002,
3124 0x0071805c,
3125 0x00000000,
3126 0x00000000,
3127 0x000f0002,
3128 0x0071805d,
3129 0x00000000,
3130 0x00000000,
3131 0x000f0002,
3132 0x0071805e,
3133 0x00000000,
3134 0x00000000,
3135 0x000f0002,
3136 0x0071805f,
3137 0x00000000,
3138 0x00000000,
3139 0x000f0002,
3140 0x00718060,
3141 0x0000003f,
3142 0xdf000003,
3143 0x000f0002,
3144 0x00718061,
3145 0x0000002d,
3146 0xdde00f81,
3147 0x000f0002,
3148 0x00718062,
3149 0x0000003f,
3150 0xdd800283,
3151 0x000f0002,
3152 0x00718063,
3153 0x0000002d,
3154 0xdd040180,
3155 0x000f0002,
3156 0x00718064,
3157 0x0000007d,
3158 0xfd150080,
3159 0x000f0002,
3160 0x00718065,
3161 0x0000007a,
3162 0x10203b76,
3163 0x000f0002,
3164 0x00718066,
3165 0x0000007a,
3166 0x30207b76,
3167 0x000f0002,
3168 0x00718067,
3169 0x00000021,
3170 0xd0240060,
3171 0x000f0002,
3172 0x00718068,
3173 0x0000003f,
3174 0xdd000104,
3175 0x000f0002,
3176 0x00718069,
3177 0x0000003f,
3178 0xdd400281,
3179 0x000f0002,
3180 0x0071806a,
3181 0x00000079,
3182 0xdd31bb03,
3183 0x000f0002,
3184 0x0071806b,
3185 0x00000079,
3186 0xdd31fb04,
3187 0x000f0002,
3188 0x0071806c,
3189 0x00000079,
3190 0xdd31bb76,
3191 0x000f0002,
3192 0x0071806d,
3193 0x00000079,
3194 0xdd31fb76,
3195 0x000f0002,
3196 0x0071806e,
3197 0x00000079,
3198 0xfd210101,
3199 0x000f0002,
3200 0x0071806f,
3201 0x0000007d,
3202 0xfd2b4081,
3203 0x000f0002,
3204 0x00718070,
3205 0x00000040,
3206 0x3d003002,
3207 0x000f0002,
3208 0x00718071,
3209 0x00000048,
3210 0x1d003b02,
3211 0x000f0002,
3212 0x00718072,
3213 0x00000079,
3214 0xdd217b76,
3215 0x000f0002,
3216 0x00718073,
3217 0x0000002d,
3218 0xdd04057f,
3219 0x000f0002,
3220 0x00718074,
3221 0x00000018,
3222 0x3d7f3b76,
3223 0x000f0002,
3224 0x00718075,
3225 0x0000003d,
3226 0xf780006f,
3227 0x000f0002,
3228 0x00718076,
3229 0x0000003d,
3230 0xf780006f,
3231 0x000f0002,
3232 0x00718077,
3233 0x0000003d,
3234 0xf780006f,
3235 0x000f0002,
3236 0x00718078,
3237 0x00000021,
3238 0xe3371f76,
3239 0x000f0002,
3240 0x00718079,
3241 0x00000049,
3242 0xdd003b79,
3243 0x000f0002,
3244 0x0071807a,
3245 0x00000079,
3246 0xdd21bb76,
3247 0x000f0002,
3248 0x0071807b,
3249 0x00000049,
3250 0xdd003b79,
3251 0x000f0002,
3252 0x0071807c,
3253 0x00000079,
3254 0xdd21bb76,
3255 0x000f0002,
3256 0x0071807d,
3257 0x00000049,
3258 0xdd003b79,
3259 0x000f0002,
3260 0x0071807e,
3261 0x00000079,
3262 0xdd21bb76,
3263 0x000f0002,
3264 0x0071807f,
3265 0x00000079,
3266 0xfd609076,
3267 0x000f0002,
3268 0x00718080,
3269 0x00000079,
3270 0xdd21fb76,
3271 0x000f0002,
3272 0x00718081,
3273 0x0000003f,
3274 0xdf000083,
3275 0x000f0002,
3276 0x00718082,
3277 0x0000003d,
3278 0xf780006f,
3279 0x000f0002,
3280 0x00718083,
3281 0x00000000,
3282 0x00000000,
3283 0x000f0002,
3284 0x00718084,
3285 0x00000000,
3286 0x00000000,
3287 0x000f0002,
3288 0x00718085,
3289 0x00000000,
3290 0x00000000,
3291 0x000f0002,
3292 0x00718086,
3293 0x00000000,
3294 0x00000000,
3295 0x000f0002,
3296 0x00718087,
3297 0x00000000,
3298 0x00000000,
3299 0x000f0002,
3300 0x00718088,
3301 0x00000000,
3302 0x00000000,
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10345 0x00000000,
10346 0x00000000,
10347 0x000f0002,
10348 0x0071876a,
10349 0x00000000,
10350 0x00000000,
10351 0x000f0002,
10352 0x0071876b,
10353 0x00000000,
10354 0x00000000,
10355 0x000f0002,
10356 0x0071876c,
10357 0x00000000,
10358 0x00000000,
10359 0x000f0002,
10360 0x0071876d,
10361 0x00000000,
10362 0x00000000,
10363 0x000f0002,
10364 0x0071876e,
10365 0x00000000,
10366 0x00000000,
10367 0x000f0002,
10368 0x0071876f,
10369 0x00000000,
10370 0x00000000,
10371 0x000f0002,
10372 0x00718770,
10373 0x00000000,
10374 0x00000000,
10375 0x000f0002,
10376 0x00718771,
10377 0x00000000,
10378 0x00000000,
10379 0x000f0002,
10380 0x00718772,
10381 0x00000000,
10382 0x00000000,
10383 0x000f0002,
10384 0x00718773,
10385 0x00000000,
10386 0x00000000,
10387 0x000f0002,
10388 0x00718774,
10389 0x00000000,
10390 0x00000000,
10391 0x000f0002,
10392 0x00718775,
10393 0x00000000,
10394 0x00000000,
10395 0x000f0002,
10396 0x00718776,
10397 0x00000000,
10398 0x00000000,
10399 0x000f0002,
10400 0x00718777,
10401 0x00000000,
10402 0x00000000,
10403 0x000f0002,
10404 0x00718778,
10405 0x00000000,
10406 0x00000000,
10407 0x000f0002,
10408 0x00718779,
10409 0x00000000,
10410 0x00000000,
10411 0x000f0002,
10412 0x0071877a,
10413 0x00000000,
10414 0x00000000,
10415 0x000f0002,
10416 0x0071877b,
10417 0x00000000,
10418 0x00000000,
10419 0x000f0002,
10420 0x0071877c,
10421 0x00000000,
10422 0x00000000,
10423 0x000f0002,
10424 0x0071877d,
10425 0x00000000,
10426 0x00000000,
10427 0x000f0002,
10428 0x0071877e,
10429 0x00000000,
10430 0x00000000,
10431 0x000f0002,
10432 0x0071877f,
10433 0x00000000,
10434 0x00000000,
10435 0x000f0002,
10436 0x00718780,
10437 0x00000000,
10438 0x00000000,
10439 0x000f0002,
10440 0x00718781,
10441 0x00000000,
10442 0x00000000,
10443 0x000f0002,
10444 0x00718782,
10445 0x00000000,
10446 0x00000000,
10447 0x000f0002,
10448 0x00718783,
10449 0x00000000,
10450 0x00000000,
10451 0x000f0002,
10452 0x00718784,
10453 0x00000000,
10454 0x00000000,
10455 0x000f0002,
10456 0x00718785,
10457 0x00000000,
10458 0x00000000,
10459 0x000f0002,
10460 0x00718786,
10461 0x00000000,
10462 0x00000000,
10463 0x000f0002,
10464 0x00718787,
10465 0x00000000,
10466 0x00000000,
10467 0x000f0002,
10468 0x00718788,
10469 0x00000000,
10470 0x00000000,
10471 0x000f0002,
10472 0x00718789,
10473 0x00000000,
10474 0x00000000,
10475 0x000f0002,
10476 0x0071878a,
10477 0x00000000,
10478 0x00000000,
10479 0x000f0002,
10480 0x0071878b,
10481 0x00000000,
10482 0x00000000,
10483 0x000f0002,
10484 0x0071878c,
10485 0x00000000,
10486 0x00000000,
10487 0x000f0002,
10488 0x0071878d,
10489 0x00000000,
10490 0x00000000,
10491 0x000f0002,
10492 0x0071878e,
10493 0x00000000,
10494 0x00000000,
10495 0x000f0002,
10496 0x0071878f,
10497 0x00000000,
10498 0x00000000,
10499 0x000f0002,
10500 0x00718790,
10501 0x00000000,
10502 0x00000000,
10503 0x000f0002,
10504 0x00718791,
10505 0x00000000,
10506 0x00000000,
10507 0x000f0002,
10508 0x00718792,
10509 0x00000000,
10510 0x00000000,
10511 0x000f0002,
10512 0x00718793,
10513 0x00000000,
10514 0x00000000,
10515 0x000f0002,
10516 0x00718794,
10517 0x00000000,
10518 0x00000000,
10519 0x000f0002,
10520 0x00718795,
10521 0x00000000,
10522 0x00000000,
10523 0x000f0002,
10524 0x00718796,
10525 0x00000000,
10526 0x00000000,
10527 0x000f0002,
10528 0x00718797,
10529 0x00000000,
10530 0x00000000,
10531 0x000f0002,
10532 0x00718798,
10533 0x00000000,
10534 0x00000000,
10535 0x000f0002,
10536 0x00718799,
10537 0x00000000,
10538 0x00000000,
10539 0x000f0002,
10540 0x0071879a,
10541 0x00000000,
10542 0x00000000,
10543 0x000f0002,
10544 0x0071879b,
10545 0x00000000,
10546 0x00000000,
10547 0x000f0002,
10548 0x0071879c,
10549 0x00000000,
10550 0x00000000,
10551 0x000f0002,
10552 0x0071879d,
10553 0x00000000,
10554 0x00000000,
10555 0x000f0002,
10556 0x0071879e,
10557 0x00000000,
10558 0x00000000,
10559 0x000f0002,
10560 0x0071879f,
10561 0x00000000,
10562 0x00000000,
10563 0x000f0002,
10564 0x007187a0,
10565 0x00000000,
10566 0x00000000,
10567 0x000f0002,
10568 0x007187a1,
10569 0x00000000,
10570 0x00000000,
10571 0x000f0002,
10572 0x007187a2,
10573 0x00000000,
10574 0x00000000,
10575 0x000f0002,
10576 0x007187a3,
10577 0x00000000,
10578 0x00000000,
10579 0x000f0002,
10580 0x007187a4,
10581 0x00000000,
10582 0x00000000,
10583 0x000f0002,
10584 0x007187a5,
10585 0x00000000,
10586 0x00000000,
10587 0x000f0002,
10588 0x007187a6,
10589 0x00000000,
10590 0x00000000,
10591 0x000f0002,
10592 0x007187a7,
10593 0x00000000,
10594 0x00000000,
10595 0x000f0002,
10596 0x007187a8,
10597 0x00000000,
10598 0x00000000,
10599 0x000f0002,
10600 0x007187a9,
10601 0x00000000,
10602 0x00000000,
10603 0x000f0002,
10604 0x007187aa,
10605 0x00000000,
10606 0x00000000,
10607 0x000f0002,
10608 0x007187ab,
10609 0x00000000,
10610 0x00000000,
10611 0x000f0002,
10612 0x007187ac,
10613 0x00000000,
10614 0x00000000,
10615 0x000f0002,
10616 0x007187ad,
10617 0x00000000,
10618 0x00000000,
10619 0x000f0002,
10620 0x007187ae,
10621 0x00000000,
10622 0x00000000,
10623 0x000f0002,
10624 0x007187af,
10625 0x00000000,
10626 0x00000000,
10627 0x000f0002,
10628 0x007187b0,
10629 0x00000000,
10630 0x00000000,
10631 0x000f0002,
10632 0x007187b1,
10633 0x00000000,
10634 0x00000000,
10635 0x000f0002,
10636 0x007187b2,
10637 0x00000000,
10638 0x00000000,
10639 0x000f0002,
10640 0x007187b3,
10641 0x00000000,
10642 0x00000000,
10643 0x000f0002,
10644 0x007187b4,
10645 0x00000000,
10646 0x00000000,
10647 0x000f0002,
10648 0x007187b5,
10649 0x00000000,
10650 0x00000000,
10651 0x000f0002,
10652 0x007187b6,
10653 0x00000000,
10654 0x00000000,
10655 0x000f0002,
10656 0x007187b7,
10657 0x00000000,
10658 0x00000000,
10659 0x000f0002,
10660 0x007187b8,
10661 0x00000000,
10662 0x00000000,
10663 0x000f0002,
10664 0x007187b9,
10665 0x00000000,
10666 0x00000000,
10667 0x000f0002,
10668 0x007187ba,
10669 0x00000000,
10670 0x00000000,
10671 0x000f0002,
10672 0x007187bb,
10673 0x00000000,
10674 0x00000000,
10675 0x000f0002,
10676 0x007187bc,
10677 0x00000000,
10678 0x00000000,
10679 0x000f0002,
10680 0x007187bd,
10681 0x00000000,
10682 0x00000000,
10683 0x000f0002,
10684 0x007187be,
10685 0x00000000,
10686 0x00000000,
10687 0x000f0002,
10688 0x007187bf,
10689 0x00000000,
10690 0x00000000,
10691 0x000f0002,
10692 0x007187c0,
10693 0x00000079,
10694 0xfd609076,
10695 0x000f0002,
10696 0x007187c1,
10697 0x0000003d,
10698 0xf780006f,
10699 0x000f0002,
10700 0x007187c2,
10701 0x0000003d,
10702 0xf780006f,
10703 0x000f0002,
10704 0x007187c3,
10705 0x0000003d,
10706 0xf780006f,
10707/* FINISH INIT Descriptor */
10708 0x000f0002,
10709 0x807187c4,
10710 0x0000003d,
10711 0xf780006f,
10712};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 15:58:58 -0500