RDMA/cxgb4: Zero out ISGL padding

The HW design requires zeroing any pad in SGLs.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 4f5dd66da39d..bdbf54d517d9 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -263,6 +263,9 @@ static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
                         rem -= len;
                 }
         }
+        len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
+        if (len)
+                memset(dstp, 0, len);
         immdp->op = FW_RI_DATA_IMMD;
         immdp->r1 = 0;
         immdp->r2 = 0;
@@ -292,6 +295,7 @@ static int build_isgl(__be64 *queue_start, __be64 *queue_end,
                 if (++flitp == queue_end)
                         flitp = queue_start;
         }
+        *flitp = (__force __be64)0;
         isglp->op = FW_RI_DATA_ISGL;
         isglp->r1 = 0;
         isglp->nsge = cpu_to_be16(num_sge);