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authorLinus Torvalds <torvalds@g5.osdl.org>2005-09-27 16:32:33 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-27 16:32:33 -0400
commit63906e41fe70fe8a376c5887429448272a0ee7d4 (patch)
tree38129b935e279d1e127eed4ad20fcfeb60187602 /drivers
parent59175839783287d3b03f18460bb3539c69300837 (diff)
parentc8a6c2963982c68475f409aeee21aa80b923cb9c (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c94
-rw-r--r--drivers/net/tg3.h1
2 files changed, 80 insertions, 15 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 81f4aedf534c..25f85fb9df46 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -67,8 +67,8 @@
67 67
68#define DRV_MODULE_NAME "tg3" 68#define DRV_MODULE_NAME "tg3"
69#define PFX DRV_MODULE_NAME ": " 69#define PFX DRV_MODULE_NAME ": "
70#define DRV_MODULE_VERSION "3.40" 70#define DRV_MODULE_VERSION "3.41"
71#define DRV_MODULE_RELDATE "September 15, 2005" 71#define DRV_MODULE_RELDATE "September 27, 2005"
72 72
73#define TG3_DEF_MAC_MODE 0 73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0 74#define TG3_DEF_RX_MODE 0
@@ -3389,7 +3389,8 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3389 struct tg3 *tp = netdev_priv(dev); 3389 struct tg3 *tp = netdev_priv(dev);
3390 struct tg3_hw_status *sblk = tp->hw_status; 3390 struct tg3_hw_status *sblk = tp->hw_status;
3391 3391
3392 if (sblk->status & SD_STATUS_UPDATED) { 3392 if ((sblk->status & SD_STATUS_UPDATED) ||
3393 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3393 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 3394 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3394 0x00000001); 3395 0x00000001);
3395 return IRQ_RETVAL(1); 3396 return IRQ_RETVAL(1);
@@ -5395,6 +5396,9 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5395 struct tg3 *tp = netdev_priv(dev); 5396 struct tg3 *tp = netdev_priv(dev);
5396 struct sockaddr *addr = p; 5397 struct sockaddr *addr = p;
5397 5398
5399 if (!is_valid_ether_addr(addr->sa_data))
5400 return -EINVAL;
5401
5398 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 5402 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5399 5403
5400 spin_lock_bh(&tp->lock); 5404 spin_lock_bh(&tp->lock);
@@ -5806,6 +5810,13 @@ static int tg3_reset_hw(struct tg3 *tp)
5806 } 5810 }
5807 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); 5811 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5808 5812
5813 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5814 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5815 /* reset to prevent losing 1st rx packet intermittently */
5816 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5817 udelay(10);
5818 }
5819
5809 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | 5820 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5810 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; 5821 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5811 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); 5822 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
@@ -5937,7 +5948,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5937 tw32(MAC_LED_CTRL, tp->led_ctrl); 5948 tw32(MAC_LED_CTRL, tp->led_ctrl);
5938 5949
5939 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); 5950 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5940 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { 5951 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5941 tw32_f(MAC_RX_MODE, RX_MODE_RESET); 5952 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5942 udelay(10); 5953 udelay(10);
5943 } 5954 }
@@ -7360,12 +7371,17 @@ static int tg3_nway_reset(struct net_device *dev)
7360 if (!netif_running(dev)) 7371 if (!netif_running(dev))
7361 return -EAGAIN; 7372 return -EAGAIN;
7362 7373
7374 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7375 return -EINVAL;
7376
7363 spin_lock_bh(&tp->lock); 7377 spin_lock_bh(&tp->lock);
7364 r = -EINVAL; 7378 r = -EINVAL;
7365 tg3_readphy(tp, MII_BMCR, &bmcr); 7379 tg3_readphy(tp, MII_BMCR, &bmcr);
7366 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && 7380 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7367 (bmcr & BMCR_ANENABLE)) { 7381 ((bmcr & BMCR_ANENABLE) ||
7368 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART); 7382 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7383 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7384 BMCR_ANENABLE);
7369 r = 0; 7385 r = 0;
7370 } 7386 }
7371 spin_unlock_bh(&tp->lock); 7387 spin_unlock_bh(&tp->lock);
@@ -7927,19 +7943,32 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
7927 struct tg3_rx_buffer_desc *desc; 7943 struct tg3_rx_buffer_desc *desc;
7928 7944
7929 if (loopback_mode == TG3_MAC_LOOPBACK) { 7945 if (loopback_mode == TG3_MAC_LOOPBACK) {
7946 /* HW errata - mac loopback fails in some cases on 5780.
7947 * Normal traffic and PHY loopback are not affected by
7948 * errata.
7949 */
7950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
7951 return 0;
7952
7930 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | 7953 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7931 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY | 7954 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7932 MAC_MODE_PORT_MODE_GMII; 7955 MAC_MODE_PORT_MODE_GMII;
7933 tw32(MAC_MODE, mac_mode); 7956 tw32(MAC_MODE, mac_mode);
7934 } else if (loopback_mode == TG3_PHY_LOOPBACK) { 7957 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
7958 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
7959 BMCR_SPEED1000);
7960 udelay(40);
7961 /* reset to prevent losing 1st rx packet intermittently */
7962 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7963 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7964 udelay(10);
7965 tw32_f(MAC_RX_MODE, tp->rx_mode);
7966 }
7935 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | 7967 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7936 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII; 7968 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
7937 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) 7969 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
7938 mac_mode &= ~MAC_MODE_LINK_POLARITY; 7970 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7939 tw32(MAC_MODE, mac_mode); 7971 tw32(MAC_MODE, mac_mode);
7940
7941 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
7942 BMCR_SPEED1000);
7943 } 7972 }
7944 else 7973 else
7945 return -EINVAL; 7974 return -EINVAL;
@@ -10324,6 +10353,44 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
10324 }; 10353 };
10325} 10354}
10326 10355
10356static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10357{
10358 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10359 strcpy(str, "PCI Express");
10360 return str;
10361 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10362 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10363
10364 strcpy(str, "PCIX:");
10365
10366 if ((clock_ctrl == 7) ||
10367 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10368 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10369 strcat(str, "133MHz");
10370 else if (clock_ctrl == 0)
10371 strcat(str, "33MHz");
10372 else if (clock_ctrl == 2)
10373 strcat(str, "50MHz");
10374 else if (clock_ctrl == 4)
10375 strcat(str, "66MHz");
10376 else if (clock_ctrl == 6)
10377 strcat(str, "100MHz");
10378 else if (clock_ctrl == 7)
10379 strcat(str, "133MHz");
10380 } else {
10381 strcpy(str, "PCI:");
10382 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10383 strcat(str, "66MHz");
10384 else
10385 strcat(str, "33MHz");
10386 }
10387 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10388 strcat(str, ":32-bit");
10389 else
10390 strcat(str, ":64-bit");
10391 return str;
10392}
10393
10327static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp) 10394static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10328{ 10395{
10329 struct pci_dev *peer; 10396 struct pci_dev *peer;
@@ -10386,6 +10453,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10386 struct net_device *dev; 10453 struct net_device *dev;
10387 struct tg3 *tp; 10454 struct tg3 *tp;
10388 int i, err, pci_using_dac, pm_cap; 10455 int i, err, pci_using_dac, pm_cap;
10456 char str[40];
10389 10457
10390 if (tg3_version_printed++ == 0) 10458 if (tg3_version_printed++ == 0)
10391 printk(KERN_INFO "%s", version); 10459 printk(KERN_INFO "%s", version);
@@ -10631,16 +10699,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10631 10699
10632 pci_set_drvdata(pdev, dev); 10700 pci_set_drvdata(pdev, dev);
10633 10701
10634 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ", 10702 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
10635 dev->name, 10703 dev->name,
10636 tp->board_part_number, 10704 tp->board_part_number,
10637 tp->pci_chip_rev_id, 10705 tp->pci_chip_rev_id,
10638 tg3_phy_string(tp), 10706 tg3_phy_string(tp),
10639 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""), 10707 tg3_bus_string(tp, str),
10640 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10641 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10642 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10643 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10644 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000"); 10708 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10645 10709
10646 for (i = 0; i < 6; i++) 10710 for (i = 0; i < 6; i++)
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index c184b773e585..2e733c60bfa4 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2246,6 +2246,7 @@ struct tg3 {
2246 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \ 2246 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2247 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \ 2247 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2248 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \ 2248 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2249 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5780 || \
2249 (X) == PHY_ID_BCM8002) 2250 (X) == PHY_ID_BCM8002)
2250 2251
2251 struct tg3_hw_stats *hw_stats; 2252 struct tg3_hw_stats *hw_stats;