diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-03-05 14:50:37 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-03-30 19:53:53 -0400 |
commit | f867c60def7a8dcd86657fd38a8920a4354f305e (patch) | |
tree | 5dde8663e0af76bcb220ec3c3bf0c1111569e787 /drivers | |
parent | 57f50d70e27f99a9a785c760b2123cdf6a68e2de (diff) |
drm/radeon/kms: gfx init fixes for r6xx/r7xx
This fixes some issues with the last gfx init patch.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cp.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 3 |
3 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 5aee7fe4717f..d568262160e1 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -1133,6 +1133,7 @@ void r600_gpu_init(struct radeon_device *rdev) | |||
1133 | /* Setup pipes */ | 1133 | /* Setup pipes */ |
1134 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 1134 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1135 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | 1135 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
1136 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | ||
1136 | 1137 | ||
1137 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); | 1138 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
1138 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); | 1139 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 40416c068d9f..68e6f4349309 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c | |||
@@ -1548,10 +1548,13 @@ static void r700_gfx_init(struct drm_device *dev, | |||
1548 | 1548 | ||
1549 | RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 1549 | RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1550 | RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | 1550 | RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
1551 | RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | ||
1551 | 1552 | ||
1552 | RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 1553 | RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1553 | RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); | 1554 | RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); |
1554 | RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); | 1555 | RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); |
1556 | RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); | ||
1557 | RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); | ||
1555 | 1558 | ||
1556 | num_qd_pipes = | 1559 | num_qd_pipes = |
1557 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); | 1560 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 2f917db49f23..86d39cb35fe2 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -648,10 +648,13 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
648 | 648 | ||
649 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 649 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
650 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | 650 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
651 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | ||
651 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 652 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
652 | 653 | ||
653 | WREG32(CGTS_SYS_TCC_DISABLE, 0); | 654 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
654 | WREG32(CGTS_TCC_DISABLE, 0); | 655 | WREG32(CGTS_TCC_DISABLE, 0); |
656 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); | ||
657 | WREG32(CGTS_USER_TCC_DISABLE, 0); | ||
655 | 658 | ||
656 | num_qd_pipes = | 659 | num_qd_pipes = |
657 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); | 660 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |