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authorMarc St-Jean <stjeanma@pmc-sierra.com>2007-05-06 17:48:45 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:50 -0400
commitbeab697ab4b2962e3d741b476abe443baad0933d (patch)
treef581ce38378f6cacbf0042b4eb9c084a6fc932d9 /drivers
parent6179b5562d5d17c7c09b54cb11dd925ca308d7a9 (diff)
serial driver PMC MSP71xx
Serial driver patch for the PMC-Sierra MSP71xx devices. There are three different fixes: 1 Fix for DesignWare APB THRE errata: In brief, this is a non-standard 16550 in that the THRE interrupt will not re-assert itself simply by disabling and re-enabling the THRI bit in the IER, it is only re-enabled if a character is actually sent out. It appears that the "8250-uart-backup-timer.patch" in the "mm" tree also fixes it so we have dropped our initial workaround. This patch now needs to be applied on top of that "mm" patch. 2 Fix for Busy Detect on LCR write: The DesignWare APB UART has a feature which causes a new Busy Detect interrupt to be generated if it's busy when the LCR is written. This fix saves the value of the LCR and rewrites it after clearing the interrupt. 3 Workaround for interrupt/data concurrency issue: The SoC needs to ensure that writes that can cause interrupts to be cleared reach the UART before returning from the ISR. This fix reads a non-destructive register on the UART so the read transaction completion ensures the previously queued write transaction has also completed. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/serial/8250.c31
-rw-r--r--drivers/serial/serial_core.c2
2 files changed, 33 insertions, 0 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 90621c3312bc..194362d9f5a3 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -308,6 +308,7 @@ static unsigned int serial_in(struct uart_8250_port *up, int offset)
308 return inb(up->port.iobase + 1); 308 return inb(up->port.iobase + 1);
309 309
310 case UPIO_MEM: 310 case UPIO_MEM:
311 case UPIO_DWAPB:
311 return readb(up->port.membase + offset); 312 return readb(up->port.membase + offset);
312 313
313 case UPIO_MEM32: 314 case UPIO_MEM32:
@@ -333,6 +334,8 @@ static unsigned int serial_in(struct uart_8250_port *up, int offset)
333static void 334static void
334serial_out(struct uart_8250_port *up, int offset, int value) 335serial_out(struct uart_8250_port *up, int offset, int value)
335{ 336{
337 /* Save the offset before it's remapped */
338 int save_offset = offset;
336 offset = map_8250_out_reg(up, offset) << up->port.regshift; 339 offset = map_8250_out_reg(up, offset) << up->port.regshift;
337 340
338 switch (up->port.iotype) { 341 switch (up->port.iotype) {
@@ -359,6 +362,18 @@ serial_out(struct uart_8250_port *up, int offset, int value)
359 writeb(value, up->port.membase + offset); 362 writeb(value, up->port.membase + offset);
360 break; 363 break;
361 364
365 case UPIO_DWAPB:
366 /* Save the LCR value so it can be re-written when a
367 * Busy Detect interrupt occurs. */
368 if (save_offset == UART_LCR)
369 up->lcr = value;
370 writeb(value, up->port.membase + offset);
371 /* Read the IER to ensure any interrupt is cleared before
372 * returning from ISR. */
373 if (save_offset == UART_TX || save_offset == UART_IER)
374 value = serial_in(up, UART_IER);
375 break;
376
362 default: 377 default:
363 outb(value, up->port.iobase + offset); 378 outb(value, up->port.iobase + offset);
364 } 379 }
@@ -373,6 +388,7 @@ serial_out_sync(struct uart_8250_port *up, int offset, int value)
373#ifdef CONFIG_SERIAL_8250_AU1X00 388#ifdef CONFIG_SERIAL_8250_AU1X00
374 case UPIO_AU: 389 case UPIO_AU:
375#endif 390#endif
391 case UPIO_DWAPB:
376 serial_out(up, offset, value); 392 serial_out(up, offset, value);
377 serial_in(up, UART_LCR); /* safe, no side-effects */ 393 serial_in(up, UART_LCR); /* safe, no side-effects */
378 break; 394 break;
@@ -1389,6 +1405,19 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1389 handled = 1; 1405 handled = 1;
1390 1406
1391 end = NULL; 1407 end = NULL;
1408 } else if (up->port.iotype == UPIO_DWAPB &&
1409 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1410 /* The DesignWare APB UART has an Busy Detect (0x07)
1411 * interrupt meaning an LCR write attempt occured while the
1412 * UART was busy. The interrupt must be cleared by reading
1413 * the UART status register (USR) and the LCR re-written. */
1414 unsigned int status;
1415 status = *(volatile u32 *)up->port.private_data;
1416 serial_out(up, UART_LCR, up->lcr);
1417
1418 handled = 1;
1419
1420 end = NULL;
1392 } else if (end == NULL) 1421 } else if (end == NULL)
1393 end = l; 1422 end = l;
1394 1423
@@ -2090,6 +2119,7 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
2090 case UPIO_TSI: 2119 case UPIO_TSI:
2091 case UPIO_MEM32: 2120 case UPIO_MEM32:
2092 case UPIO_MEM: 2121 case UPIO_MEM:
2122 case UPIO_DWAPB:
2093 if (!up->port.mapbase) 2123 if (!up->port.mapbase)
2094 break; 2124 break;
2095 2125
@@ -2127,6 +2157,7 @@ static void serial8250_release_std_resource(struct uart_8250_port *up)
2127 case UPIO_TSI: 2157 case UPIO_TSI:
2128 case UPIO_MEM32: 2158 case UPIO_MEM32:
2129 case UPIO_MEM: 2159 case UPIO_MEM:
2160 case UPIO_DWAPB:
2130 if (!up->port.mapbase) 2161 if (!up->port.mapbase)
2131 break; 2162 break;
2132 2163
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index 0422c0f1f852..a677133ab2d4 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -2064,6 +2064,7 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
2064 case UPIO_MEM32: 2064 case UPIO_MEM32:
2065 case UPIO_AU: 2065 case UPIO_AU:
2066 case UPIO_TSI: 2066 case UPIO_TSI:
2067 case UPIO_DWAPB:
2067 snprintf(address, sizeof(address), 2068 snprintf(address, sizeof(address),
2068 "MMIO 0x%lx", port->mapbase); 2069 "MMIO 0x%lx", port->mapbase);
2069 break; 2070 break;
@@ -2409,6 +2410,7 @@ int uart_match_port(struct uart_port *port1, struct uart_port *port2)
2409 case UPIO_MEM32: 2410 case UPIO_MEM32:
2410 case UPIO_AU: 2411 case UPIO_AU:
2411 case UPIO_TSI: 2412 case UPIO_TSI:
2413 case UPIO_DWAPB:
2412 return (port1->mapbase == port2->mapbase); 2414 return (port1->mapbase == port2->mapbase);
2413 } 2415 }
2414 return 0; 2416 return 0;