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authorYoshinori Sato <ysato@users.sourceforge.jp>2008-08-06 19:49:00 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-08-07 02:20:57 -0400
commit71557a37adb5df17631c493b3b7d912938c720b2 (patch)
tree7fdb2548aa5053289f0198d057e3428d43367688 /drivers
parentd91d4bb9db4a7b2a78accff3560bfd42988c56e4 (diff)
[netdrvr] sh_eth: Add SH7619 support
Add support SH7619 Internal ethernet controler. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/Kconfig5
-rw-r--r--drivers/net/sh_eth.c69
-rw-r--r--drivers/net/sh_eth.h22
3 files changed, 71 insertions, 25 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 8a03875ec877..4b4cb2bf4f11 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -510,14 +510,15 @@ config STNIC
510config SH_ETH 510config SH_ETH
511 tristate "Renesas SuperH Ethernet support" 511 tristate "Renesas SuperH Ethernet support"
512 depends on SUPERH && \ 512 depends on SUPERH && \
513 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763) 513 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763 || \
514 CPU_SUBTYPE_SH7619)
514 select CRC32 515 select CRC32
515 select MII 516 select MII
516 select MDIO_BITBANG 517 select MDIO_BITBANG
517 select PHYLIB 518 select PHYLIB
518 help 519 help
519 Renesas SuperH Ethernet device driver. 520 Renesas SuperH Ethernet device driver.
520 This driver support SH7710, SH7712 and SH7763. 521 This driver support SH7710, SH7712, SH7763 and SH7619.
521 522
522config SUNLANCE 523config SUNLANCE
523 tristate "Sun LANCE support" 524 tristate "Sun LANCE support"
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 6a06b9503e4f..25e62cf58d3a 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -34,6 +34,29 @@
34 34
35#include "sh_eth.h" 35#include "sh_eth.h"
36 36
37/* CPU <-> EDMAC endian convert */
38static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
39{
40 switch (mdp->edmac_endian) {
41 case EDMAC_LITTLE_ENDIAN:
42 return cpu_to_le32(x);
43 case EDMAC_BIG_ENDIAN:
44 return cpu_to_be32(x);
45 }
46 return x;
47}
48
49static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
50{
51 switch (mdp->edmac_endian) {
52 case EDMAC_LITTLE_ENDIAN:
53 return le32_to_cpu(x);
54 case EDMAC_BIG_ENDIAN:
55 return be32_to_cpu(x);
56 }
57 return x;
58}
59
37/* 60/*
38 * Program the hardware MAC address from dev->dev_addr. 61 * Program the hardware MAC address from dev->dev_addr.
39 */ 62 */
@@ -240,7 +263,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
240 /* RX descriptor */ 263 /* RX descriptor */
241 rxdesc = &mdp->rx_ring[i]; 264 rxdesc = &mdp->rx_ring[i];
242 rxdesc->addr = (u32)skb->data & ~0x3UL; 265 rxdesc->addr = (u32)skb->data & ~0x3UL;
243 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 266 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
244 267
245 /* The size of the buffer is 16 byte boundary. */ 268 /* The size of the buffer is 16 byte boundary. */
246 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F; 269 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
@@ -262,7 +285,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
262 mdp->dirty_rx = (u32) (i - RX_RING_SIZE); 285 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
263 286
264 /* Mark the last entry as wrapping the ring. */ 287 /* Mark the last entry as wrapping the ring. */
265 rxdesc->status |= cpu_to_le32(RD_RDEL); 288 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
266 289
267 memset(mdp->tx_ring, 0, tx_ringsize); 290 memset(mdp->tx_ring, 0, tx_ringsize);
268 291
@@ -270,10 +293,10 @@ static void sh_eth_ring_format(struct net_device *ndev)
270 for (i = 0; i < TX_RING_SIZE; i++) { 293 for (i = 0; i < TX_RING_SIZE; i++) {
271 mdp->tx_skbuff[i] = NULL; 294 mdp->tx_skbuff[i] = NULL;
272 txdesc = &mdp->tx_ring[i]; 295 txdesc = &mdp->tx_ring[i];
273 txdesc->status = cpu_to_le32(TD_TFP); 296 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
274 txdesc->buffer_length = 0; 297 txdesc->buffer_length = 0;
275 if (i == 0) { 298 if (i == 0) {
276 /* Rx descriptor address set */ 299 /* Tx descriptor address set */
277 ctrl_outl((u32)txdesc, ioaddr + TDLAR); 300 ctrl_outl((u32)txdesc, ioaddr + TDLAR);
278#if defined(CONFIG_CPU_SUBTYPE_SH7763) 301#if defined(CONFIG_CPU_SUBTYPE_SH7763)
279 ctrl_outl((u32)txdesc, ioaddr + TDFAR); 302 ctrl_outl((u32)txdesc, ioaddr + TDFAR);
@@ -281,13 +304,13 @@ static void sh_eth_ring_format(struct net_device *ndev)
281 } 304 }
282 } 305 }
283 306
284 /* Rx descriptor address set */ 307 /* Tx descriptor address set */
285#if defined(CONFIG_CPU_SUBTYPE_SH7763) 308#if defined(CONFIG_CPU_SUBTYPE_SH7763)
286 ctrl_outl((u32)txdesc, ioaddr + TDFXR); 309 ctrl_outl((u32)txdesc, ioaddr + TDFXR);
287 ctrl_outl(0x1, ioaddr + TDFFR); 310 ctrl_outl(0x1, ioaddr + TDFFR);
288#endif 311#endif
289 312
290 txdesc->status |= cpu_to_le32(TD_TDLE); 313 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
291} 314}
292 315
293/* Get skb and descriptor buffer */ 316/* Get skb and descriptor buffer */
@@ -455,7 +478,7 @@ static int sh_eth_txfree(struct net_device *ndev)
455 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 478 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
456 entry = mdp->dirty_tx % TX_RING_SIZE; 479 entry = mdp->dirty_tx % TX_RING_SIZE;
457 txdesc = &mdp->tx_ring[entry]; 480 txdesc = &mdp->tx_ring[entry];
458 if (txdesc->status & cpu_to_le32(TD_TACT)) 481 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
459 break; 482 break;
460 /* Free the original skb. */ 483 /* Free the original skb. */
461 if (mdp->tx_skbuff[entry]) { 484 if (mdp->tx_skbuff[entry]) {
@@ -463,9 +486,9 @@ static int sh_eth_txfree(struct net_device *ndev)
463 mdp->tx_skbuff[entry] = NULL; 486 mdp->tx_skbuff[entry] = NULL;
464 freeNum++; 487 freeNum++;
465 } 488 }
466 txdesc->status = cpu_to_le32(TD_TFP); 489 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
467 if (entry >= TX_RING_SIZE - 1) 490 if (entry >= TX_RING_SIZE - 1)
468 txdesc->status |= cpu_to_le32(TD_TDLE); 491 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
469 492
470 mdp->stats.tx_packets++; 493 mdp->stats.tx_packets++;
471 mdp->stats.tx_bytes += txdesc->buffer_length; 494 mdp->stats.tx_bytes += txdesc->buffer_length;
@@ -486,8 +509,8 @@ static int sh_eth_rx(struct net_device *ndev)
486 u32 desc_status, reserve = 0; 509 u32 desc_status, reserve = 0;
487 510
488 rxdesc = &mdp->rx_ring[entry]; 511 rxdesc = &mdp->rx_ring[entry];
489 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 512 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
490 desc_status = le32_to_cpu(rxdesc->status); 513 desc_status = edmac_to_cpu(mdp, rxdesc->status);
491 pkt_len = rxdesc->frame_length; 514 pkt_len = rxdesc->frame_length;
492 515
493 if (--boguscnt < 0) 516 if (--boguscnt < 0)
@@ -522,7 +545,7 @@ static int sh_eth_rx(struct net_device *ndev)
522 mdp->stats.rx_packets++; 545 mdp->stats.rx_packets++;
523 mdp->stats.rx_bytes += pkt_len; 546 mdp->stats.rx_bytes += pkt_len;
524 } 547 }
525 rxdesc->status |= cpu_to_le32(RD_RACT); 548 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
526 entry = (++mdp->cur_rx) % RX_RING_SIZE; 549 entry = (++mdp->cur_rx) % RX_RING_SIZE;
527 } 550 }
528 551
@@ -552,10 +575,10 @@ static int sh_eth_rx(struct net_device *ndev)
552 } 575 }
553 if (entry >= RX_RING_SIZE - 1) 576 if (entry >= RX_RING_SIZE - 1)
554 rxdesc->status |= 577 rxdesc->status |=
555 cpu_to_le32(RD_RACT | RD_RFP | RD_RDEL); 578 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
556 else 579 else
557 rxdesc->status |= 580 rxdesc->status |=
558 cpu_to_le32(RD_RACT | RD_RFP); 581 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
559 } 582 }
560 583
561 /* Restart Rx engine if stopped. */ 584 /* Restart Rx engine if stopped. */
@@ -931,9 +954,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
931 txdesc->buffer_length = skb->len; 954 txdesc->buffer_length = skb->len;
932 955
933 if (entry >= TX_RING_SIZE - 1) 956 if (entry >= TX_RING_SIZE - 1)
934 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 957 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
935 else 958 else
936 txdesc->status |= cpu_to_le32(TD_TACT); 959 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
937 960
938 mdp->cur_tx++; 961 mdp->cur_tx++;
939 962
@@ -1159,6 +1182,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1159 struct resource *res; 1182 struct resource *res;
1160 struct net_device *ndev = NULL; 1183 struct net_device *ndev = NULL;
1161 struct sh_eth_private *mdp; 1184 struct sh_eth_private *mdp;
1185 struct sh_eth_plat_data *pd;
1162 1186
1163 /* get base addr */ 1187 /* get base addr */
1164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1196,8 +1220,11 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1196 mdp = netdev_priv(ndev); 1220 mdp = netdev_priv(ndev);
1197 spin_lock_init(&mdp->lock); 1221 spin_lock_init(&mdp->lock);
1198 1222
1223 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1199 /* get PHY ID */ 1224 /* get PHY ID */
1200 mdp->phy_id = (int)pdev->dev.platform_data; 1225 mdp->phy_id = pd->phy;
1226 /* EDMAC endian */
1227 mdp->edmac_endian = pd->edmac_endian;
1201 1228
1202 /* set function */ 1229 /* set function */
1203 ndev->open = sh_eth_open; 1230 ndev->open = sh_eth_open;
@@ -1217,12 +1244,16 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1217 1244
1218 /* First device only init */ 1245 /* First device only init */
1219 if (!devno) { 1246 if (!devno) {
1247#if defined(ARSTR)
1220 /* reset device */ 1248 /* reset device */
1221 ctrl_outl(ARSTR_ARSTR, ARSTR); 1249 ctrl_outl(ARSTR_ARSTR, ARSTR);
1222 mdelay(1); 1250 mdelay(1);
1251#endif
1223 1252
1253#if defined(SH_TSU_ADDR)
1224 /* TSU init (Init only)*/ 1254 /* TSU init (Init only)*/
1225 sh_eth_tsu_init(SH_TSU_ADDR); 1255 sh_eth_tsu_init(SH_TSU_ADDR);
1256#endif
1226 } 1257 }
1227 1258
1228 /* network device register */ 1259 /* network device register */
@@ -1240,8 +1271,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1240 ndev->name, CARDNAME, (u32) ndev->base_addr); 1271 ndev->name, CARDNAME, (u32) ndev->base_addr);
1241 1272
1242 for (i = 0; i < 5; i++) 1273 for (i = 0; i < 5; i++)
1243 printk(KERN_INFO "%02X:", ndev->dev_addr[i]); 1274 printk("%02X:", ndev->dev_addr[i]);
1244 printk(KERN_INFO "%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq); 1275 printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1245 1276
1246 platform_set_drvdata(pdev, ndev); 1277 platform_set_drvdata(pdev, ndev);
1247 1278
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 45ad1b09ca5a..73bc7181cc18 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -30,6 +30,8 @@
30#include <linux/netdevice.h> 30#include <linux/netdevice.h>
31#include <linux/phy.h> 31#include <linux/phy.h>
32 32
33#include <asm/sh_eth.h>
34
33#define CARDNAME "sh-eth" 35#define CARDNAME "sh-eth"
34#define TX_TIMEOUT (5*HZ) 36#define TX_TIMEOUT (5*HZ)
35#define TX_RING_SIZE 64 /* Tx ring size */ 37#define TX_RING_SIZE 64 /* Tx ring size */
@@ -143,10 +145,11 @@
143 145
144#else /* CONFIG_CPU_SUBTYPE_SH7763 */ 146#else /* CONFIG_CPU_SUBTYPE_SH7763 */
145# define RX_OFFSET 2 /* skb offset */ 147# define RX_OFFSET 2 /* skb offset */
148#ifndef CONFIG_CPU_SUBTYPE_SH7619
146/* Chip base address */ 149/* Chip base address */
147# define SH_TSU_ADDR 0xA7000804 150# define SH_TSU_ADDR 0xA7000804
148# define ARSTR 0xA7000800 151# define ARSTR 0xA7000800
149 152#endif
150/* Chip Registers */ 153/* Chip Registers */
151/* E-DMAC */ 154/* E-DMAC */
152# define EDMR 0x0000 155# define EDMR 0x0000
@@ -384,7 +387,11 @@ enum FCFTR_BIT {
384 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 387 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
385}; 388};
386#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 389#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
390#ifndef CONFIG_CPU_SUBTYPE_SH7619
387#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 391#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
392#else
393#define FIFO_F_D_RFD (FCFTR_RFD0)
394#endif
388 395
389/* Transfer descriptor bit */ 396/* Transfer descriptor bit */
390enum TD_STS_BIT { 397enum TD_STS_BIT {
@@ -414,8 +421,10 @@ enum FELIC_MODE_BIT {
414#ifdef CONFIG_CPU_SUBTYPE_SH7763 421#ifdef CONFIG_CPU_SUBTYPE_SH7763
415#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\ 422#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
416 ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 423 ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
424#elif CONFIG_CPU_SUBTYPE_SH7619
425#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
417#else 426#else
418#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT) 427#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
419#endif 428#endif
420 429
421/* ECSR */ 430/* ECSR */
@@ -485,7 +494,11 @@ enum RPADIR_BIT {
485 494
486/* FDR */ 495/* FDR */
487enum FIFO_SIZE_BIT { 496enum FIFO_SIZE_BIT {
497#ifndef CONFIG_CPU_SUBTYPE_SH7619
488 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 498 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
499#else
500 FIFO_SIZE_T = 0x00000100, FIFO_SIZE_R = 0x00000001,
501#endif
489}; 502};
490enum phy_offsets { 503enum phy_offsets {
491 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, 504 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
@@ -601,7 +614,7 @@ struct sh_eth_txdesc {
601#endif 614#endif
602 u32 addr; /* TD2 */ 615 u32 addr; /* TD2 */
603 u32 pad1; /* padding data */ 616 u32 pad1; /* padding data */
604}; 617} __attribute__((aligned(2), packed));
605 618
606/* 619/*
607 * The sh ether Rx buffer descriptors. 620 * The sh ether Rx buffer descriptors.
@@ -618,7 +631,7 @@ struct sh_eth_rxdesc {
618#endif 631#endif
619 u32 addr; /* RD2 */ 632 u32 addr; /* RD2 */
620 u32 pad0; /* padding data */ 633 u32 pad0; /* padding data */
621}; 634} __attribute__((aligned(2), packed));
622 635
623struct sh_eth_private { 636struct sh_eth_private {
624 dma_addr_t rx_desc_dma; 637 dma_addr_t rx_desc_dma;
@@ -633,6 +646,7 @@ struct sh_eth_private {
633 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ 646 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
634 u32 cur_tx, dirty_tx; 647 u32 cur_tx, dirty_tx;
635 u32 rx_buf_sz; /* Based on MTU+slack. */ 648 u32 rx_buf_sz; /* Based on MTU+slack. */
649 int edmac_endian;
636 /* MII transceiver section. */ 650 /* MII transceiver section. */
637 u32 phy_id; /* PHY ID */ 651 u32 phy_id; /* PHY ID */
638 struct mii_bus *mii_bus; /* MDIO bus control */ 652 struct mii_bus *mii_bus; /* MDIO bus control */