aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2010-03-26 14:52:32 -0400
committerDave Airlie <airlied@redhat.com>2010-03-30 23:12:17 -0400
commit5f77df368c84d0a4a5913c8c78f0c6fa0b0db674 (patch)
tree193ee0d47ac929e40afbf776a21512b199d7df45 /drivers
parent5898b1f33c881fe1352464efd15faf7d26513b98 (diff)
drm/radeon/r6xx/r7xx: CS parser fixes
- Drop some more safe regs taht userspace shouldn't hit - Constant base regs need relocs. This allows us to use constant buffers rather than the constant register file. Also we don't want userspace to be able to set arbitrary mc base values for the const caches. - Track SQ_CONFIG so we know whether userspace is using the cfile or constant buffers. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c70
-rw-r--r--drivers/gpu/drm/radeon/r600d.h49
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r60053
3 files changed, 112 insertions, 60 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index cd2c63bce501..c39c1bc13016 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -45,6 +45,7 @@ struct r600_cs_track {
45 u32 nbanks; 45 u32 nbanks;
46 u32 npipes; 46 u32 npipes;
47 /* value we track */ 47 /* value we track */
48 u32 sq_config;
48 u32 nsamples; 49 u32 nsamples;
49 u32 cb_color_base_last[8]; 50 u32 cb_color_base_last[8];
50 struct radeon_bo *cb_color_bo[8]; 51 struct radeon_bo *cb_color_bo[8];
@@ -141,6 +142,8 @@ static void r600_cs_track_init(struct r600_cs_track *track)
141{ 142{
142 int i; 143 int i;
143 144
145 /* assume DX9 mode */
146 track->sq_config = DX9_CONSTS;
144 for (i = 0; i < 8; i++) { 147 for (i = 0; i < 8; i++) {
145 track->cb_color_base_last[i] = 0; 148 track->cb_color_base_last[i] = 0;
146 track->cb_color_size[i] = 0; 149 track->cb_color_size[i] = 0;
@@ -715,6 +718,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
715 tmp =radeon_get_ib_value(p, idx); 718 tmp =radeon_get_ib_value(p, idx);
716 ib[idx] = 0; 719 ib[idx] = 0;
717 break; 720 break;
721 case SQ_CONFIG:
722 track->sq_config = radeon_get_ib_value(p, idx);
723 break;
718 case R_028800_DB_DEPTH_CONTROL: 724 case R_028800_DB_DEPTH_CONTROL:
719 track->db_depth_control = radeon_get_ib_value(p, idx); 725 track->db_depth_control = radeon_get_ib_value(p, idx);
720 break; 726 break;
@@ -869,6 +875,54 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
869 case SQ_PGM_START_VS: 875 case SQ_PGM_START_VS:
870 case SQ_PGM_START_GS: 876 case SQ_PGM_START_GS:
871 case SQ_PGM_START_PS: 877 case SQ_PGM_START_PS:
878 case SQ_ALU_CONST_CACHE_GS_0:
879 case SQ_ALU_CONST_CACHE_GS_1:
880 case SQ_ALU_CONST_CACHE_GS_2:
881 case SQ_ALU_CONST_CACHE_GS_3:
882 case SQ_ALU_CONST_CACHE_GS_4:
883 case SQ_ALU_CONST_CACHE_GS_5:
884 case SQ_ALU_CONST_CACHE_GS_6:
885 case SQ_ALU_CONST_CACHE_GS_7:
886 case SQ_ALU_CONST_CACHE_GS_8:
887 case SQ_ALU_CONST_CACHE_GS_9:
888 case SQ_ALU_CONST_CACHE_GS_10:
889 case SQ_ALU_CONST_CACHE_GS_11:
890 case SQ_ALU_CONST_CACHE_GS_12:
891 case SQ_ALU_CONST_CACHE_GS_13:
892 case SQ_ALU_CONST_CACHE_GS_14:
893 case SQ_ALU_CONST_CACHE_GS_15:
894 case SQ_ALU_CONST_CACHE_PS_0:
895 case SQ_ALU_CONST_CACHE_PS_1:
896 case SQ_ALU_CONST_CACHE_PS_2:
897 case SQ_ALU_CONST_CACHE_PS_3:
898 case SQ_ALU_CONST_CACHE_PS_4:
899 case SQ_ALU_CONST_CACHE_PS_5:
900 case SQ_ALU_CONST_CACHE_PS_6:
901 case SQ_ALU_CONST_CACHE_PS_7:
902 case SQ_ALU_CONST_CACHE_PS_8:
903 case SQ_ALU_CONST_CACHE_PS_9:
904 case SQ_ALU_CONST_CACHE_PS_10:
905 case SQ_ALU_CONST_CACHE_PS_11:
906 case SQ_ALU_CONST_CACHE_PS_12:
907 case SQ_ALU_CONST_CACHE_PS_13:
908 case SQ_ALU_CONST_CACHE_PS_14:
909 case SQ_ALU_CONST_CACHE_PS_15:
910 case SQ_ALU_CONST_CACHE_VS_0:
911 case SQ_ALU_CONST_CACHE_VS_1:
912 case SQ_ALU_CONST_CACHE_VS_2:
913 case SQ_ALU_CONST_CACHE_VS_3:
914 case SQ_ALU_CONST_CACHE_VS_4:
915 case SQ_ALU_CONST_CACHE_VS_5:
916 case SQ_ALU_CONST_CACHE_VS_6:
917 case SQ_ALU_CONST_CACHE_VS_7:
918 case SQ_ALU_CONST_CACHE_VS_8:
919 case SQ_ALU_CONST_CACHE_VS_9:
920 case SQ_ALU_CONST_CACHE_VS_10:
921 case SQ_ALU_CONST_CACHE_VS_11:
922 case SQ_ALU_CONST_CACHE_VS_12:
923 case SQ_ALU_CONST_CACHE_VS_13:
924 case SQ_ALU_CONST_CACHE_VS_14:
925 case SQ_ALU_CONST_CACHE_VS_15:
872 r = r600_cs_packet_next_reloc(p, &reloc); 926 r = r600_cs_packet_next_reloc(p, &reloc);
873 if (r) { 927 if (r) {
874 dev_warn(p->dev, "bad SET_CONTEXT_REG " 928 dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -1226,13 +1280,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1226 } 1280 }
1227 break; 1281 break;
1228 case PACKET3_SET_ALU_CONST: 1282 case PACKET3_SET_ALU_CONST:
1229 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; 1283 if (track->sq_config & DX9_CONSTS) {
1230 end_reg = 4 * pkt->count + start_reg - 4; 1284 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1231 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || 1285 end_reg = 4 * pkt->count + start_reg - 4;
1232 (start_reg >= PACKET3_SET_ALU_CONST_END) || 1286 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1233 (end_reg >= PACKET3_SET_ALU_CONST_END)) { 1287 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1234 DRM_ERROR("bad SET_ALU_CONST\n"); 1288 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1235 return -EINVAL; 1289 DRM_ERROR("bad SET_ALU_CONST\n");
1290 return -EINVAL;
1291 }
1236 } 1292 }
1237 break; 1293 break;
1238 case PACKET3_SET_BOOL_CONST: 1294 case PACKET3_SET_BOOL_CONST:
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 5b2e4d442823..59c1f8793e60 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -77,6 +77,55 @@
77#define CB_COLOR0_FRAG 0x280e0 77#define CB_COLOR0_FRAG 0x280e0
78#define CB_COLOR0_MASK 0x28100 78#define CB_COLOR0_MASK 0x28100
79 79
80#define SQ_ALU_CONST_CACHE_PS_0 0x28940
81#define SQ_ALU_CONST_CACHE_PS_1 0x28944
82#define SQ_ALU_CONST_CACHE_PS_2 0x28948
83#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
84#define SQ_ALU_CONST_CACHE_PS_4 0x28950
85#define SQ_ALU_CONST_CACHE_PS_5 0x28954
86#define SQ_ALU_CONST_CACHE_PS_6 0x28958
87#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
88#define SQ_ALU_CONST_CACHE_PS_8 0x28960
89#define SQ_ALU_CONST_CACHE_PS_9 0x28964
90#define SQ_ALU_CONST_CACHE_PS_10 0x28968
91#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
92#define SQ_ALU_CONST_CACHE_PS_12 0x28970
93#define SQ_ALU_CONST_CACHE_PS_13 0x28974
94#define SQ_ALU_CONST_CACHE_PS_14 0x28978
95#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
96#define SQ_ALU_CONST_CACHE_VS_0 0x28980
97#define SQ_ALU_CONST_CACHE_VS_1 0x28984
98#define SQ_ALU_CONST_CACHE_VS_2 0x28988
99#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
100#define SQ_ALU_CONST_CACHE_VS_4 0x28990
101#define SQ_ALU_CONST_CACHE_VS_5 0x28994
102#define SQ_ALU_CONST_CACHE_VS_6 0x28998
103#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
104#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
105#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
106#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
107#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
108#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
109#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
110#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
111#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
112#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
113#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
114#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
115#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
116#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
117#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
118#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
119#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
120#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
121#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
122#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
123#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
124#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
125#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
126#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
127#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
128
80#define CONFIG_MEMSIZE 0x5428 129#define CONFIG_MEMSIZE 0x5428
81#define CONFIG_CNTL 0x5424 130#define CONFIG_CNTL 0x5424
82#define CP_STAT 0x8680 131#define CP_STAT 0x8680
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 1d3340032cad..bc062f9a847f 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -280,7 +280,6 @@ r600 0x9400
2800x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE 2800x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE
2810x00028814 PA_SU_SC_MODE_CNTL 2810x00028814 PA_SU_SC_MODE_CNTL
2820x00028C08 PA_SU_VTX_CNTL 2820x00028C08 PA_SU_VTX_CNTL
2830x00008C00 SQ_CONFIG
2840x00008C04 SQ_GPR_RESOURCE_MGMT_1 2830x00008C04 SQ_GPR_RESOURCE_MGMT_1
2850x00008C08 SQ_GPR_RESOURCE_MGMT_2 2840x00008C08 SQ_GPR_RESOURCE_MGMT_2
2860x00008C10 SQ_STACK_RESOURCE_MGMT_1 2850x00008C10 SQ_STACK_RESOURCE_MGMT_1
@@ -380,54 +379,6 @@ r600 0x9400
3800x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13 3790x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13
3810x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14 3800x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14
3820x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15 3810x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15
3830x000289C0 SQ_ALU_CONST_CACHE_GS_0
3840x000289C4 SQ_ALU_CONST_CACHE_GS_1
3850x000289C8 SQ_ALU_CONST_CACHE_GS_2
3860x000289CC SQ_ALU_CONST_CACHE_GS_3
3870x000289D0 SQ_ALU_CONST_CACHE_GS_4
3880x000289D4 SQ_ALU_CONST_CACHE_GS_5
3890x000289D8 SQ_ALU_CONST_CACHE_GS_6
3900x000289DC SQ_ALU_CONST_CACHE_GS_7
3910x000289E0 SQ_ALU_CONST_CACHE_GS_8
3920x000289E4 SQ_ALU_CONST_CACHE_GS_9
3930x000289E8 SQ_ALU_CONST_CACHE_GS_10
3940x000289EC SQ_ALU_CONST_CACHE_GS_11
3950x000289F0 SQ_ALU_CONST_CACHE_GS_12
3960x000289F4 SQ_ALU_CONST_CACHE_GS_13
3970x000289F8 SQ_ALU_CONST_CACHE_GS_14
3980x000289FC SQ_ALU_CONST_CACHE_GS_15
3990x00028940 SQ_ALU_CONST_CACHE_PS_0
4000x00028944 SQ_ALU_CONST_CACHE_PS_1
4010x00028948 SQ_ALU_CONST_CACHE_PS_2
4020x0002894C SQ_ALU_CONST_CACHE_PS_3
4030x00028950 SQ_ALU_CONST_CACHE_PS_4
4040x00028954 SQ_ALU_CONST_CACHE_PS_5
4050x00028958 SQ_ALU_CONST_CACHE_PS_6
4060x0002895C SQ_ALU_CONST_CACHE_PS_7
4070x00028960 SQ_ALU_CONST_CACHE_PS_8
4080x00028964 SQ_ALU_CONST_CACHE_PS_9
4090x00028968 SQ_ALU_CONST_CACHE_PS_10
4100x0002896C SQ_ALU_CONST_CACHE_PS_11
4110x00028970 SQ_ALU_CONST_CACHE_PS_12
4120x00028974 SQ_ALU_CONST_CACHE_PS_13
4130x00028978 SQ_ALU_CONST_CACHE_PS_14
4140x0002897C SQ_ALU_CONST_CACHE_PS_15
4150x00028980 SQ_ALU_CONST_CACHE_VS_0
4160x00028984 SQ_ALU_CONST_CACHE_VS_1
4170x00028988 SQ_ALU_CONST_CACHE_VS_2
4180x0002898C SQ_ALU_CONST_CACHE_VS_3
4190x00028990 SQ_ALU_CONST_CACHE_VS_4
4200x00028994 SQ_ALU_CONST_CACHE_VS_5
4210x00028998 SQ_ALU_CONST_CACHE_VS_6
4220x0002899C SQ_ALU_CONST_CACHE_VS_7
4230x000289A0 SQ_ALU_CONST_CACHE_VS_8
4240x000289A4 SQ_ALU_CONST_CACHE_VS_9
4250x000289A8 SQ_ALU_CONST_CACHE_VS_10
4260x000289AC SQ_ALU_CONST_CACHE_VS_11
4270x000289B0 SQ_ALU_CONST_CACHE_VS_12
4280x000289B4 SQ_ALU_CONST_CACHE_VS_13
4290x000289B8 SQ_ALU_CONST_CACHE_VS_14
4300x000289BC SQ_ALU_CONST_CACHE_VS_15
4310x000288D8 SQ_PGM_CF_OFFSET_ES 3820x000288D8 SQ_PGM_CF_OFFSET_ES
4320x000288DC SQ_PGM_CF_OFFSET_FS 3830x000288DC SQ_PGM_CF_OFFSET_FS
4330x000288D4 SQ_PGM_CF_OFFSET_GS 3840x000288D4 SQ_PGM_CF_OFFSET_GS
@@ -497,9 +448,7 @@ r600 0x9400
4970x0000A020 SMX_DC_CTL0 4480x0000A020 SMX_DC_CTL0
4980x0000A024 SMX_DC_CTL1 4490x0000A024 SMX_DC_CTL1
4990x0000A028 SMX_DC_CTL2 4500x0000A028 SMX_DC_CTL2
5000x00009608 TC_CNTL
5010x00009604 TC_INVALIDATE 4510x00009604 TC_INVALIDATE
5020x00009490 TD_CNTL
5030x00009400 TD_FILTER4 4520x00009400 TD_FILTER4
5040x00009404 TD_FILTER4_1 4530x00009404 TD_FILTER4_1
5050x00009408 TD_FILTER4_2 4540x00009408 TD_FILTER4_2
@@ -829,6 +778,4 @@ r600 0x9400
8290x00009838 DB_WATERMARKS 7780x00009838 DB_WATERMARKS
8300x00028D28 DB_SRESULTS_COMPARE_STATE0 7790x00028D28 DB_SRESULTS_COMPARE_STATE0
8310x00028D44 DB_ALPHA_TO_MASK 7800x00028D44 DB_ALPHA_TO_MASK
8320x00009504 TA_CNTL
8330x00009700 VC_CNTL 7810x00009700 VC_CNTL
8340x00009718 VC_CONFIG
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 20:08:27 -0500