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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2007-05-10 00:18:19 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2007-07-12 19:29:45 -0400
commit5d3043586db428b5b4b3df89fa0c2db9731e934c (patch)
treee342467f770d8450d4d7e3ab7d81fdccfd5e7a0d /drivers
parent15a1d5c9271219db2f1bc448247fb8ccbcc08418 (diff)
USB: r8a66597-hcd: host controller driver for R8A66597
I would like to submit Renesas R8A66597 USB HCD driver. R8A66597 is Renesas USB 2.0 host and peripheral combined controller device originally designed for embedded products. As a limitation of this device, it does not support externel hub more than 2 tier, and cannot communicate with a USB device more than 10. Then this device is not compatible with EHCI and/or OHCI, I wrote driver support patch based on sl811 code. This driver has the following unique specifications: - Implement transfer timeout to share one pipe with plural endpoint. - Detach detection of a USB device connected to externel hub. The driver has been tested external hub, usb-hdd, usb-cdrom, usb-speaker, mice, keyboard, and usbtest driver. Signed-off-by : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/Makefile1
-rw-r--r--drivers/usb/host/Kconfig12
-rw-r--r--drivers/usb/host/Makefile2
-rw-r--r--drivers/usb/host/r8a66597-hcd.c2241
-rw-r--r--drivers/usb/host/r8a66597.h634
5 files changed, 2890 insertions, 0 deletions
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 72464b586990..b33aae5d669f 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_USB_UHCI_HCD) += host/
16obj-$(CONFIG_USB_SL811_HCD) += host/ 16obj-$(CONFIG_USB_SL811_HCD) += host/
17obj-$(CONFIG_USB_U132_HCD) += host/ 17obj-$(CONFIG_USB_U132_HCD) += host/
18obj-$(CONFIG_USB_OHCI_AT91) += host/ 18obj-$(CONFIG_USB_OHCI_AT91) += host/
19obj-$(CONFIG_USB_R8A66597_HCD) += host/
19 20
20obj-$(CONFIG_USB_ACM) += class/ 21obj-$(CONFIG_USB_ACM) += class/
21obj-$(CONFIG_USB_PRINTER) += class/ 22obj-$(CONFIG_USB_PRINTER) += class/
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a8faff646ac7..f0fbe4a5a7ca 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -229,3 +229,15 @@ config USB_SL811_CS
229 To compile this driver as a module, choose M here: the 229 To compile this driver as a module, choose M here: the
230 module will be called "sl811_cs". 230 module will be called "sl811_cs".
231 231
232config USB_R8A66597_HCD
233 tristate "R8A66597 HCD suppoort"
234 depends on USB
235 help
236 The R8A66597 is a USB 2.0 host and peripheral controller.
237
238 Enable this option if your board has this chip, and you want
239 to use it as a host controller. If unsure, say N.
240
241 To compile this driver as a module, choose M here: the
242 module will be called r8a66597-hcd.
243
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 2ff396bd180f..bb8e9d44f371 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -15,3 +15,5 @@ obj-$(CONFIG_USB_UHCI_HCD) += uhci-hcd.o
15obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o 15obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o
16obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o 16obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
17obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o 17obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
18obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
19
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
new file mode 100644
index 000000000000..af13f1f2296a
--- /dev/null
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -0,0 +1,2241 @@
1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/smp_lock.h>
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/timer.h>
33#include <linux/delay.h>
34#include <linux/list.h>
35#include <linux/interrupt.h>
36#include <linux/usb.h>
37#include <linux/platform_device.h>
38
39#include <asm/io.h>
40#include <asm/irq.h>
41#include <asm/system.h>
42
43#include "../core/hcd.h"
44#include "r8a66597.h"
45
46MODULE_DESCRIPTION("R8A66597 USB Host Controller Driver");
47MODULE_LICENSE("GPL");
48MODULE_AUTHOR("Yoshihiro Shimoda");
49
50#define DRIVER_VERSION "9 May 2007"
51
52static const char hcd_name[] = "r8a66597_hcd";
53
54/* module parameters */
55static unsigned short clock = XTAL12;
56module_param(clock, ushort, 0644);
57MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=0)");
58static unsigned short vif = LDRV;
59module_param(vif, ushort, 0644);
60MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)");
61static unsigned short endian = 0;
62module_param(endian, ushort, 0644);
63MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)");
64static unsigned short irq_sense = INTL;
65module_param(irq_sense, ushort, 0644);
66MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0(default=32)");
67
68static void packet_write(struct r8a66597 *r8a66597, u16 pipenum);
69static int r8a66597_get_frame(struct usb_hcd *hcd);
70
71/* this function must be called with interrupt disabled */
72static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
73 unsigned long reg)
74{
75 u16 tmp;
76
77 tmp = r8a66597_read(r8a66597, INTENB0);
78 r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE, INTENB0);
79 r8a66597_bset(r8a66597, 1 << pipenum, reg);
80 r8a66597_write(r8a66597, tmp, INTENB0);
81}
82
83/* this function must be called with interrupt disabled */
84static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
85 unsigned long reg)
86{
87 u16 tmp;
88
89 tmp = r8a66597_read(r8a66597, INTENB0);
90 r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE, INTENB0);
91 r8a66597_bclr(r8a66597, 1 << pipenum, reg);
92 r8a66597_write(r8a66597, tmp, INTENB0);
93}
94
95static void set_devadd_reg(struct r8a66597 *r8a66597, u8 r8a66597_address,
96 u16 usbspd, u8 upphub, u8 hubport, int port)
97{
98 u16 val;
99 unsigned long devadd_reg = get_devadd_addr(r8a66597_address);
100
101 val = (upphub << 11) | (hubport << 8) | (usbspd << 6) | (port & 0x0001);
102 r8a66597_write(r8a66597, val, devadd_reg);
103}
104
105static int enable_controller(struct r8a66597 *r8a66597)
106{
107 u16 tmp;
108 int i = 0;
109
110 do {
111 r8a66597_write(r8a66597, USBE, SYSCFG0);
112 tmp = r8a66597_read(r8a66597, SYSCFG0);
113 if (i++ > 1000) {
114 err("register access fail.");
115 return -ENXIO;
116 }
117 } while ((tmp & USBE) != USBE);
118 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
119 r8a66597_mdfy(r8a66597, clock, XTAL, SYSCFG0);
120
121 i = 0;
122 r8a66597_bset(r8a66597, XCKE, SYSCFG0);
123 do {
124 msleep(1);
125 tmp = r8a66597_read(r8a66597, SYSCFG0);
126 if (i++ > 500) {
127 err("register access fail.");
128 return -ENXIO;
129 }
130 } while ((tmp & SCKE) != SCKE);
131
132 r8a66597_bset(r8a66597, DCFM | DRPD, SYSCFG0);
133 r8a66597_bset(r8a66597, DRPD, SYSCFG1);
134
135 r8a66597_bset(r8a66597, vif & LDRV, PINCFG);
136 r8a66597_bset(r8a66597, HSE, SYSCFG0);
137 r8a66597_bset(r8a66597, HSE, SYSCFG1);
138 r8a66597_bset(r8a66597, USBE, SYSCFG0);
139
140 r8a66597_bset(r8a66597, BEMPE | NRDYE | BRDYE, INTENB0);
141 r8a66597_bset(r8a66597, irq_sense & INTL, SOFCFG);
142 r8a66597_bset(r8a66597, BRDY0, BRDYENB);
143 r8a66597_bset(r8a66597, BEMP0, BEMPENB);
144
145 r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, DMA0CFG);
146 r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, DMA1CFG);
147
148 r8a66597_bset(r8a66597, endian & BIGEND, CFIFOSEL);
149 r8a66597_bset(r8a66597, endian & BIGEND, D0FIFOSEL);
150 r8a66597_bset(r8a66597, endian & BIGEND, D1FIFOSEL);
151
152 r8a66597_bset(r8a66597, TRNENSEL, SOFCFG);
153
154 r8a66597_bset(r8a66597, SIGNE | SACKE, INTENB1);
155 r8a66597_bclr(r8a66597, DTCHE, INTENB1);
156 r8a66597_bset(r8a66597, ATTCHE, INTENB1);
157 r8a66597_bclr(r8a66597, DTCHE, INTENB2);
158 r8a66597_bset(r8a66597, ATTCHE, INTENB2);
159
160 return 0;
161}
162
163static void disable_controller(struct r8a66597 *r8a66597)
164{
165 u16 tmp;
166
167 r8a66597_write(r8a66597, 0, INTENB0);
168 r8a66597_write(r8a66597, 0, INTENB1);
169 r8a66597_write(r8a66597, 0, INTENB2);
170 r8a66597_write(r8a66597, 0, INTSTS0);
171 r8a66597_write(r8a66597, 0, INTSTS1);
172 r8a66597_write(r8a66597, 0, INTSTS2);
173
174 r8a66597_port_power(r8a66597, 0, 0);
175 r8a66597_port_power(r8a66597, 1, 0);
176
177 do {
178 tmp = r8a66597_read(r8a66597, SOFCFG) & EDGESTS;
179 udelay(640);
180 } while (tmp == EDGESTS);
181
182 r8a66597_bclr(r8a66597, DCFM | DRPD, SYSCFG0);
183 r8a66597_bclr(r8a66597, DRPD, SYSCFG1);
184 r8a66597_bclr(r8a66597, HSE, SYSCFG0);
185 r8a66597_bclr(r8a66597, HSE, SYSCFG1);
186
187 r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
188 udelay(1);
189 r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
190 r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
191 r8a66597_bclr(r8a66597, USBE, SYSCFG0);
192}
193
194static int get_parent_r8a66597_address(struct r8a66597 *r8a66597,
195 struct usb_device *udev)
196{
197 struct r8a66597_device *dev;
198
199 if (udev->parent && udev->parent->devnum != 1)
200 udev = udev->parent;
201
202 dev = dev_get_drvdata(&udev->dev);
203 if (dev)
204 return dev->address;
205 else
206 return 0;
207}
208
209static int is_child_device(char *devpath)
210{
211 return (devpath[2] ? 1 : 0);
212}
213
214static int is_hub_limit(char *devpath)
215{
216 return ((strlen(devpath) >= 4) ? 1 : 0);
217}
218
219static void get_port_number(char *devpath, u16 *root_port, u16 *hub_port)
220{
221 if (root_port) {
222 *root_port = (devpath[0] & 0x0F) - 1;
223 if (*root_port >= R8A66597_MAX_ROOT_HUB)
224 err("illegal root port number");
225 }
226 if (hub_port)
227 *hub_port = devpath[2] & 0x0F;
228}
229
230static u16 get_r8a66597_usb_speed(enum usb_device_speed speed)
231{
232 u16 usbspd = 0;
233
234 switch (speed) {
235 case USB_SPEED_LOW:
236 usbspd = LSMODE;
237 break;
238 case USB_SPEED_FULL:
239 usbspd = FSMODE;
240 break;
241 case USB_SPEED_HIGH:
242 usbspd = HSMODE;
243 break;
244 default:
245 err("unknown speed");
246 break;
247 }
248
249 return usbspd;
250}
251
252static void set_child_connect_map(struct r8a66597 *r8a66597, int address)
253{
254 int idx;
255
256 idx = address / 32;
257 r8a66597->child_connect_map[idx] |= 1 << (address % 32);
258}
259
260static void put_child_connect_map(struct r8a66597 *r8a66597, int address)
261{
262 int idx;
263
264 idx = address / 32;
265 r8a66597->child_connect_map[idx] &= ~(1 << (address % 32));
266}
267
268static void set_pipe_reg_addr(struct r8a66597_pipe *pipe, u8 dma_ch)
269{
270 u16 pipenum = pipe->info.pipenum;
271 unsigned long fifoaddr[] = {D0FIFO, D1FIFO, CFIFO};
272 unsigned long fifosel[] = {D0FIFOSEL, D1FIFOSEL, CFIFOSEL};
273 unsigned long fifoctr[] = {D0FIFOCTR, D1FIFOCTR, CFIFOCTR};
274
275 if (dma_ch > R8A66597_PIPE_NO_DMA) /* dma fifo not use? */
276 dma_ch = R8A66597_PIPE_NO_DMA;
277
278 pipe->fifoaddr = fifoaddr[dma_ch];
279 pipe->fifosel = fifosel[dma_ch];
280 pipe->fifoctr = fifoctr[dma_ch];
281
282 if (pipenum == 0)
283 pipe->pipectr = DCPCTR;
284 else
285 pipe->pipectr = get_pipectr_addr(pipenum);
286
287 if (check_bulk_or_isoc(pipenum)) {
288 pipe->pipetre = get_pipetre_addr(pipenum);
289 pipe->pipetrn = get_pipetrn_addr(pipenum);
290 } else {
291 pipe->pipetre = 0;
292 pipe->pipetrn = 0;
293 }
294}
295
296static struct r8a66597_device *
297get_urb_to_r8a66597_dev(struct r8a66597 *r8a66597, struct urb *urb)
298{
299 if (usb_pipedevice(urb->pipe) == 0)
300 return &r8a66597->device0;
301
302 return dev_get_drvdata(&urb->dev->dev);
303}
304
305static int make_r8a66597_device(struct r8a66597 *r8a66597,
306 struct urb *urb, u8 addr)
307{
308 struct r8a66597_device *dev;
309 int usb_address = urb->setup_packet[2]; /* urb->pipe is address 0 */
310
311 dev = kzalloc(sizeof(struct r8a66597_device), GFP_KERNEL);
312 if (dev == NULL)
313 return -ENOMEM;
314
315 dev_set_drvdata(&urb->dev->dev, dev);
316 dev->udev = urb->dev;
317 dev->address = addr;
318 dev->usb_address = usb_address;
319 dev->state = USB_STATE_ADDRESS;
320 dev->ep_in_toggle = 0;
321 dev->ep_out_toggle = 0;
322 INIT_LIST_HEAD(&dev->device_list);
323 list_add_tail(&dev->device_list, &r8a66597->child_device);
324
325 get_port_number(urb->dev->devpath, &dev->root_port, &dev->hub_port);
326 if (!is_child_device(urb->dev->devpath))
327 r8a66597->root_hub[dev->root_port].dev = dev;
328
329 set_devadd_reg(r8a66597, dev->address,
330 get_r8a66597_usb_speed(urb->dev->speed),
331 get_parent_r8a66597_address(r8a66597, urb->dev),
332 dev->hub_port, dev->root_port);
333
334 return 0;
335}
336
337/* this function must be called with interrupt disabled */
338static u8 alloc_usb_address(struct r8a66597 *r8a66597, struct urb *urb)
339{
340 u8 addr; /* R8A66597's address */
341 struct r8a66597_device *dev;
342
343 if (is_hub_limit(urb->dev->devpath)) {
344 err("Externel hub limit reached.");
345 return 0;
346 }
347
348 dev = get_urb_to_r8a66597_dev(r8a66597, urb);
349 if (dev && dev->state >= USB_STATE_ADDRESS)
350 return dev->address;
351
352 for (addr = 1; addr <= R8A66597_MAX_DEVICE; addr++) {
353 if (r8a66597->address_map & (1 << addr))
354 continue;
355
356 dbg("alloc_address: r8a66597_addr=%d", addr);
357 r8a66597->address_map |= 1 << addr;
358
359 if (make_r8a66597_device(r8a66597, urb, addr) < 0)
360 return 0;
361
362 return addr;
363 }
364
365 err("cannot communicate with a USB device more than 10.(%x)",
366 r8a66597->address_map);
367
368 return 0;
369}
370
371/* this function must be called with interrupt disabled */
372static void free_usb_address(struct r8a66597 *r8a66597,
373 struct r8a66597_device *dev)
374{
375 int port;
376
377 if (!dev)
378 return;
379
380 dbg("free_addr: addr=%d", dev->address);
381
382 dev->state = USB_STATE_DEFAULT;
383 r8a66597->address_map &= ~(1 << dev->address);
384 dev->address = 0;
385 dev_set_drvdata(&dev->udev->dev, NULL);
386 list_del(&dev->device_list);
387 kfree(dev);
388
389 for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) {
390 if (r8a66597->root_hub[port].dev == dev) {
391 r8a66597->root_hub[port].dev = NULL;
392 break;
393 }
394 }
395}
396
397static void r8a66597_reg_wait(struct r8a66597 *r8a66597, unsigned long reg,
398 u16 mask, u16 loop)
399{
400 u16 tmp;
401 int i = 0;
402
403 do {
404 tmp = r8a66597_read(r8a66597, reg);
405 if (i++ > 1000000) {
406 err("register%lx, loop %x is timeout", reg, loop);
407 break;
408 }
409 ndelay(1);
410 } while ((tmp & mask) != loop);
411}
412
413/* this function must be called with interrupt disabled */
414static void pipe_start(struct r8a66597 *r8a66597, struct r8a66597_pipe *pipe)
415{
416 u16 tmp;
417
418 tmp = r8a66597_read(r8a66597, pipe->pipectr) & PID;
419 if ((pipe->info.pipenum != 0) & ((tmp & PID_STALL) != 0)) /* stall? */
420 r8a66597_mdfy(r8a66597, PID_NAK, PID, pipe->pipectr);
421 r8a66597_mdfy(r8a66597, PID_BUF, PID, pipe->pipectr);
422}
423
424/* this function must be called with interrupt disabled */
425static void pipe_stop(struct r8a66597 *r8a66597, struct r8a66597_pipe *pipe)
426{
427 u16 tmp;
428
429 tmp = r8a66597_read(r8a66597, pipe->pipectr) & PID;
430 if ((tmp & PID_STALL11) != PID_STALL11) /* force stall? */
431 r8a66597_mdfy(r8a66597, PID_STALL, PID, pipe->pipectr);
432 r8a66597_mdfy(r8a66597, PID_NAK, PID, pipe->pipectr);
433 r8a66597_reg_wait(r8a66597, pipe->pipectr, PBUSY, 0);
434}
435
436/* this function must be called with interrupt disabled */
437static void clear_all_buffer(struct r8a66597 *r8a66597,
438 struct r8a66597_pipe *pipe)
439{
440 u16 tmp;
441
442 if (!pipe || pipe->info.pipenum == 0)
443 return;
444
445 pipe_stop(r8a66597, pipe);
446 r8a66597_bset(r8a66597, ACLRM, pipe->pipectr);
447 tmp = r8a66597_read(r8a66597, pipe->pipectr);
448 tmp = r8a66597_read(r8a66597, pipe->pipectr);
449 tmp = r8a66597_read(r8a66597, pipe->pipectr);
450 r8a66597_bclr(r8a66597, ACLRM, pipe->pipectr);
451}
452
453/* this function must be called with interrupt disabled */
454static void r8a66597_pipe_toggle(struct r8a66597 *r8a66597,
455 struct r8a66597_pipe *pipe, int toggle)
456{
457 if (toggle)
458 r8a66597_bset(r8a66597, SQSET, pipe->pipectr);
459 else
460 r8a66597_bset(r8a66597, SQCLR, pipe->pipectr);
461}
462
463/* this function must be called with interrupt disabled */
464static inline void cfifo_change(struct r8a66597 *r8a66597, u16 pipenum)
465{
466 r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL);
467 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, pipenum);
468}
469
470/* this function must be called with interrupt disabled */
471static inline void fifo_change_from_pipe(struct r8a66597 *r8a66597,
472 struct r8a66597_pipe *pipe)
473{
474 cfifo_change(r8a66597, 0);
475 r8a66597_mdfy(r8a66597, MBW | 0, MBW | CURPIPE, D0FIFOSEL);
476 r8a66597_mdfy(r8a66597, MBW | 0, MBW | CURPIPE, D1FIFOSEL);
477
478 r8a66597_mdfy(r8a66597, MBW | pipe->info.pipenum, MBW | CURPIPE,
479 pipe->fifosel);
480 r8a66597_reg_wait(r8a66597, pipe->fifosel, CURPIPE, pipe->info.pipenum);
481}
482
483static u16 r8a66597_get_pipenum(struct urb *urb, struct usb_host_endpoint *hep)
484{
485 struct r8a66597_pipe *pipe = hep->hcpriv;
486
487 if (usb_pipeendpoint(urb->pipe) == 0)
488 return 0;
489 else
490 return pipe->info.pipenum;
491}
492
493static u16 get_urb_to_r8a66597_addr(struct r8a66597 *r8a66597, struct urb *urb)
494{
495 struct r8a66597_device *dev = get_urb_to_r8a66597_dev(r8a66597, urb);
496
497 return (usb_pipedevice(urb->pipe) == 0) ? 0 : dev->address;
498}
499
500static unsigned short *get_toggle_pointer(struct r8a66597_device *dev,
501 int urb_pipe)
502{
503 if (!dev)
504 return NULL;
505
506 return usb_pipein(urb_pipe) ? &dev->ep_in_toggle : &dev->ep_out_toggle;
507}
508
509/* this function must be called with interrupt disabled */
510static void pipe_toggle_set(struct r8a66597 *r8a66597,
511 struct r8a66597_pipe *pipe,
512 struct urb *urb, int set)
513{
514 struct r8a66597_device *dev = get_urb_to_r8a66597_dev(r8a66597, urb);
515 unsigned char endpoint = usb_pipeendpoint(urb->pipe);
516 unsigned short *toggle = get_toggle_pointer(dev, urb->pipe);
517
518 if (!toggle)
519 return;
520
521 if (set)
522 *toggle |= 1 << endpoint;
523 else
524 *toggle &= ~(1 << endpoint);
525}
526
527/* this function must be called with interrupt disabled */
528static void pipe_toggle_save(struct r8a66597 *r8a66597,
529 struct r8a66597_pipe *pipe,
530 struct urb *urb)
531{
532 if (r8a66597_read(r8a66597, pipe->pipectr) & SQMON)
533 pipe_toggle_set(r8a66597, pipe, urb, 1);
534 else
535 pipe_toggle_set(r8a66597, pipe, urb, 0);
536}
537
538/* this function must be called with interrupt disabled */
539static void pipe_toggle_restore(struct r8a66597 *r8a66597,
540 struct r8a66597_pipe *pipe,
541 struct urb *urb)
542{
543 struct r8a66597_device *dev = get_urb_to_r8a66597_dev(r8a66597, urb);
544 unsigned char endpoint = usb_pipeendpoint(urb->pipe);
545 unsigned short *toggle = get_toggle_pointer(dev, urb->pipe);
546
547 r8a66597_pipe_toggle(r8a66597, pipe, *toggle & (1 << endpoint));
548}
549
550/* this function must be called with interrupt disabled */
551static void pipe_buffer_setting(struct r8a66597 *r8a66597,
552 struct r8a66597_pipe_info *info)
553{
554 u16 val = 0;
555
556 if (info->pipenum == 0)
557 return;
558
559 r8a66597_bset(r8a66597, ACLRM, get_pipectr_addr(info->pipenum));
560 r8a66597_bclr(r8a66597, ACLRM, get_pipectr_addr(info->pipenum));
561 r8a66597_write(r8a66597, info->pipenum, PIPESEL);
562 if (!info->dir_in)
563 val |= R8A66597_DIR;
564 if (info->type == R8A66597_BULK && info->dir_in)
565 val |= R8A66597_DBLB | R8A66597_SHTNAK;
566 val |= info->type | info->epnum;
567 r8a66597_write(r8a66597, val, PIPECFG);
568
569 r8a66597_write(r8a66597, (info->buf_bsize << 10) | (info->bufnum),
570 PIPEBUF);
571 r8a66597_write(r8a66597, make_devsel(info->address) | info->maxpacket,
572 PIPEMAXP);
573 if (info->interval)
574 info->interval--;
575 r8a66597_write(r8a66597, info->interval, PIPEPERI);
576}
577
578
579
580/* this function must be called with interrupt disabled */
581static void pipe_setting(struct r8a66597 *r8a66597, struct r8a66597_td *td)
582{
583 struct r8a66597_pipe_info *info;
584 struct urb *urb = td->urb;
585
586 if (td->pipenum > 0) {
587 info = &td->pipe->info;
588 cfifo_change(r8a66597, 0);
589 pipe_buffer_setting(r8a66597, info);
590
591 if (!usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
592 usb_pipeout(urb->pipe)) &&
593 !usb_pipecontrol(urb->pipe)) {
594 r8a66597_pipe_toggle(r8a66597, td->pipe, 0);
595 pipe_toggle_set(r8a66597, td->pipe, urb, 0);
596 clear_all_buffer(r8a66597, td->pipe);
597 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
598 usb_pipeout(urb->pipe), 1);
599 }
600 pipe_toggle_restore(r8a66597, td->pipe, urb);
601 }
602}
603
604/* this function must be called with interrupt disabled */
605static u16 get_empty_pipenum(struct r8a66597 *r8a66597,
606 struct usb_endpoint_descriptor *ep)
607{
608 u16 array[R8A66597_MAX_NUM_PIPE], i = 0, min;
609
610 memset(array, 0, sizeof(array));
611 switch(ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
612 case USB_ENDPOINT_XFER_BULK:
613 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
614 array[i++] = 4;
615 else {
616 array[i++] = 3;
617 array[i++] = 5;
618 }
619 break;
620 case USB_ENDPOINT_XFER_INT:
621 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) {
622 array[i++] = 6;
623 array[i++] = 7;
624 array[i++] = 8;
625 } else
626 array[i++] = 9;
627 break;
628 case USB_ENDPOINT_XFER_ISOC:
629 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
630 array[i++] = 2;
631 else
632 array[i++] = 1;
633 break;
634 default:
635 err("Illegal type");
636 return 0;
637 }
638
639 i = 1;
640 min = array[0];
641 while (array[i] != 0) {
642 if (r8a66597->pipe_cnt[min] > r8a66597->pipe_cnt[array[i]])
643 min = array[i];
644 i++;
645 }
646
647 return min;
648}
649
650static u16 get_r8a66597_type(__u8 type)
651{
652 u16 r8a66597_type;
653
654 switch(type) {
655 case USB_ENDPOINT_XFER_BULK:
656 r8a66597_type = R8A66597_BULK;
657 break;
658 case USB_ENDPOINT_XFER_INT:
659 r8a66597_type = R8A66597_INT;
660 break;
661 case USB_ENDPOINT_XFER_ISOC:
662 r8a66597_type = R8A66597_ISO;
663 break;
664 default:
665 err("Illegal type");
666 r8a66597_type = 0x0000;
667 break;
668 }
669
670 return r8a66597_type;
671}
672
673static u16 get_bufnum(u16 pipenum)
674{
675 u16 bufnum = 0;
676
677 if (pipenum == 0)
678 bufnum = 0;
679 else if (check_bulk_or_isoc(pipenum))
680 bufnum = 8 + (pipenum - 1) * R8A66597_BUF_BSIZE*2;
681 else if (check_interrupt(pipenum))
682 bufnum = 4 + (pipenum - 6);
683 else
684 err("Illegal pipenum (%d)", pipenum);
685
686 return bufnum;
687}
688
689static u16 get_buf_bsize(u16 pipenum)
690{
691 u16 buf_bsize = 0;
692
693 if (pipenum == 0)
694 buf_bsize = 3;
695 else if (check_bulk_or_isoc(pipenum))
696 buf_bsize = R8A66597_BUF_BSIZE - 1;
697 else if (check_interrupt(pipenum))
698 buf_bsize = 0;
699 else
700 err("Illegal pipenum (%d)", pipenum);
701
702 return buf_bsize;
703}
704
705/* this function must be called with interrupt disabled */
706static void enable_r8a66597_pipe_dma(struct r8a66597 *r8a66597,
707 struct r8a66597_device *dev,
708 struct r8a66597_pipe *pipe,
709 struct urb *urb)
710{
711 int i;
712 struct r8a66597_pipe_info *info = &pipe->info;
713
714 if ((pipe->info.pipenum != 0) && (info->type != R8A66597_INT)) {
715 for (i = 0; i < R8A66597_MAX_DMA_CHANNEL; i++) {
716 if ((r8a66597->dma_map & (1 << i)) != 0)
717 continue;
718
719 info("address %d, EndpointAddress 0x%02x use DMA FIFO",
720 usb_pipedevice(urb->pipe),
721 info->dir_in ? USB_ENDPOINT_DIR_MASK + info->epnum
722 : info->epnum);
723
724 r8a66597->dma_map |= 1 << i;
725 dev->dma_map |= 1 << i;
726 set_pipe_reg_addr(pipe, i);
727
728 cfifo_change(r8a66597, 0);
729 r8a66597_mdfy(r8a66597, MBW | pipe->info.pipenum,
730 MBW | CURPIPE, pipe->fifosel);
731
732 r8a66597_reg_wait(r8a66597, pipe->fifosel, CURPIPE,
733 pipe->info.pipenum);
734 r8a66597_bset(r8a66597, BCLR, pipe->fifoctr);
735 break;
736 }
737 }
738}
739
740/* this function must be called with interrupt disabled */
741static void enable_r8a66597_pipe(struct r8a66597 *r8a66597, struct urb *urb,
742 struct usb_host_endpoint *hep,
743 struct r8a66597_pipe_info *info)
744{
745 struct r8a66597_device *dev = get_urb_to_r8a66597_dev(r8a66597, urb);
746 struct r8a66597_pipe *pipe = hep->hcpriv;
747
748 dbg("enable_pipe:");
749
750 pipe->info = *info;
751 set_pipe_reg_addr(pipe, R8A66597_PIPE_NO_DMA);
752 r8a66597->pipe_cnt[pipe->info.pipenum]++;
753 dev->pipe_cnt[pipe->info.pipenum]++;
754
755 enable_r8a66597_pipe_dma(r8a66597, dev, pipe, urb);
756}
757
758/* this function must be called with interrupt disabled */
759static void force_dequeue(struct r8a66597 *r8a66597, u16 pipenum, u16 address)
760{
761 struct r8a66597_td *td, *next;
762 struct urb *urb;
763 struct list_head *list = &r8a66597->pipe_queue[pipenum];
764
765 if (list_empty(list))
766 return;
767
768 list_for_each_entry_safe(td, next, list, queue) {
769 if (!td)
770 continue;
771 if (td->address != address)
772 continue;
773
774 urb = td->urb;
775 list_del(&td->queue);
776 kfree(td);
777
778 if (urb) {
779 urb->status = -ENODEV;
780 urb->hcpriv = NULL;
781 spin_unlock(&r8a66597->lock);
782 usb_hcd_giveback_urb(r8a66597_to_hcd(r8a66597), urb);
783 spin_lock(&r8a66597->lock);
784 }
785 break;
786 }
787}
788
789/* this function must be called with interrupt disabled */
790static void disable_r8a66597_pipe_all(struct r8a66597 *r8a66597,
791 struct r8a66597_device *dev)
792{
793 int check_ep0 = 0;
794 u16 pipenum;
795
796 if (!dev)
797 return;
798
799 for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
800 if (!dev->pipe_cnt[pipenum])
801 continue;
802
803 if (!check_ep0) {
804 check_ep0 = 1;
805 force_dequeue(r8a66597, 0, dev->address);
806 }
807
808 r8a66597->pipe_cnt[pipenum] -= dev->pipe_cnt[pipenum];
809 dev->pipe_cnt[pipenum] = 0;
810 force_dequeue(r8a66597, pipenum, dev->address);
811 }
812
813 dbg("disable_pipe");
814
815 r8a66597->dma_map &= ~(dev->dma_map);
816 dev->dma_map = 0;
817}
818
819/* this function must be called with interrupt disabled */
820static void init_pipe_info(struct r8a66597 *r8a66597, struct urb *urb,
821 struct usb_host_endpoint *hep,
822 struct usb_endpoint_descriptor *ep)
823{
824 struct r8a66597_pipe_info info;
825
826 info.pipenum = get_empty_pipenum(r8a66597, ep);
827 info.address = get_urb_to_r8a66597_addr(r8a66597, urb);
828 info.epnum = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
829 info.maxpacket = ep->wMaxPacketSize;
830 info.type = get_r8a66597_type(ep->bmAttributes
831 & USB_ENDPOINT_XFERTYPE_MASK);
832 info.bufnum = get_bufnum(info.pipenum);
833 info.buf_bsize = get_buf_bsize(info.pipenum);
834 info.interval = ep->bInterval;
835 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
836 info.dir_in = 1;
837 else
838 info.dir_in = 0;
839
840 enable_r8a66597_pipe(r8a66597, urb, hep, &info);
841}
842
843static void init_pipe_config(struct r8a66597 *r8a66597, struct urb *urb)
844{
845 struct r8a66597_device *dev;
846
847 dev = get_urb_to_r8a66597_dev(r8a66597, urb);
848 dev->state = USB_STATE_CONFIGURED;
849}
850
851static void pipe_irq_enable(struct r8a66597 *r8a66597, struct urb *urb,
852 u16 pipenum)
853{
854 if (pipenum == 0 && usb_pipeout(urb->pipe))
855 enable_irq_empty(r8a66597, pipenum);
856 else
857 enable_irq_ready(r8a66597, pipenum);
858
859 if (!usb_pipeisoc(urb->pipe))
860 enable_irq_nrdy(r8a66597, pipenum);
861}
862
863static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
864{
865 disable_irq_ready(r8a66597, pipenum);
866 disable_irq_nrdy(r8a66597, pipenum);
867}
868
869/* this function must be called with interrupt disabled */
870static void r8a66597_usb_preconnect(struct r8a66597 *r8a66597, int port)
871{
872 r8a66597->root_hub[port].port |= (1 << USB_PORT_FEAT_CONNECTION)
873 | (1 << USB_PORT_FEAT_C_CONNECTION);
874 r8a66597_write(r8a66597, (u16)~DTCH, get_intsts_reg(port));
875 r8a66597_bset(r8a66597, DTCHE, get_intenb_reg(port));
876}
877
878/* this function must be called with interrupt disabled */
879static void r8a66597_usb_connect(struct r8a66597 *r8a66597, int port)
880{
881 u16 speed = get_rh_usb_speed(r8a66597, port);
882 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
883
884 if (speed == HSMODE)
885 rh->port |= (1 << USB_PORT_FEAT_HIGHSPEED);
886 else if (speed == LSMODE)
887 rh->port |= (1 << USB_PORT_FEAT_LOWSPEED);
888
889 rh->port &= ~(1 << USB_PORT_FEAT_RESET);
890 rh->port |= 1 << USB_PORT_FEAT_ENABLE;
891}
892
893/* this function must be called with interrupt disabled */
894static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597, int port)
895{
896 struct r8a66597_device *dev = r8a66597->root_hub[port].dev;
897
898 r8a66597->root_hub[port].port &= ~(1 << USB_PORT_FEAT_CONNECTION);
899 r8a66597->root_hub[port].port |= (1 << USB_PORT_FEAT_C_CONNECTION);
900
901 disable_r8a66597_pipe_all(r8a66597, dev);
902 free_usb_address(r8a66597, dev);
903
904 r8a66597_bset(r8a66597, ATTCHE, get_intenb_reg(port));
905}
906
907/* this function must be called with interrupt disabled */
908static void prepare_setup_packet(struct r8a66597 *r8a66597,
909 struct r8a66597_td *td)
910{
911 int i;
912 u16 *p = (u16 *)td->urb->setup_packet;
913 unsigned long setup_addr = USBREQ;
914
915 r8a66597_write(r8a66597, make_devsel(td->address) | td->maxpacket,
916 DCPMAXP);
917 r8a66597_write(r8a66597, (u16)~(SIGN | SACK), INTSTS1);
918
919 for (i = 0; i < 4; i++) {
920 r8a66597_write(r8a66597, p[i], setup_addr);
921 setup_addr += 2;
922 }
923 r8a66597_write(r8a66597, SUREQ, DCPCTR);
924}
925
926/* this function must be called with interrupt disabled */
927static void prepare_packet_read(struct r8a66597 *r8a66597,
928 struct r8a66597_td *td)
929{
930 struct urb *urb = td->urb;
931
932 if (usb_pipecontrol(urb->pipe)) {
933 r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
934 r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
935 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
936 if (urb->actual_length == 0) {
937 r8a66597_pipe_toggle(r8a66597, td->pipe, 1);
938 r8a66597_write(r8a66597, BCLR, CFIFOCTR);
939 }
940 pipe_irq_disable(r8a66597, td->pipenum);
941 pipe_start(r8a66597, td->pipe);
942 pipe_irq_enable(r8a66597, urb, td->pipenum);
943 } else {
944 if (urb->actual_length == 0) {
945 pipe_irq_disable(r8a66597, td->pipenum);
946 pipe_setting(r8a66597, td);
947 pipe_stop(r8a66597, td->pipe);
948 r8a66597_write(r8a66597, (u16)~(1 << td->pipenum),
949 BRDYSTS);
950
951 if (td->pipe->pipetre) {
952 r8a66597_write(r8a66597, TRCLR,
953 td->pipe->pipetre);
954 r8a66597_write(r8a66597,
955 (urb->transfer_buffer_length
956 + td->maxpacket - 1)
957 / td->maxpacket,
958 td->pipe->pipetrn);
959 r8a66597_bset(r8a66597, TRENB,
960 td->pipe->pipetre);
961 }
962
963 pipe_start(r8a66597, td->pipe);
964 pipe_irq_enable(r8a66597, urb, td->pipenum);
965 }
966 }
967}
968
969/* this function must be called with interrupt disabled */
970static void prepare_packet_write(struct r8a66597 *r8a66597,
971 struct r8a66597_td *td)
972{
973 u16 tmp;
974 struct urb *urb = td->urb;
975
976 if (usb_pipecontrol(urb->pipe)) {
977 pipe_stop(r8a66597, td->pipe);
978 r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG);
979 r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL);
980 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
981 if (urb->actual_length == 0) {
982 r8a66597_pipe_toggle(r8a66597, td->pipe, 1);
983 r8a66597_write(r8a66597, BCLR, CFIFOCTR);
984 }
985 } else {
986 if (urb->actual_length == 0)
987 pipe_setting(r8a66597, td);
988 if (td->pipe->pipetre)
989 r8a66597_bclr(r8a66597, TRENB, td->pipe->pipetre);
990 }
991 r8a66597_write(r8a66597, (u16)~(1 << td->pipenum), BRDYSTS);
992
993 fifo_change_from_pipe(r8a66597, td->pipe);
994 tmp = r8a66597_read(r8a66597, td->pipe->fifoctr);
995 if (unlikely((tmp & FRDY) == 0))
996 pipe_irq_enable(r8a66597, urb, td->pipenum);
997 else
998 packet_write(r8a66597, td->pipenum);
999 pipe_start(r8a66597, td->pipe);
1000}
1001
1002/* this function must be called with interrupt disabled */
1003static void prepare_status_packet(struct r8a66597 *r8a66597,
1004 struct r8a66597_td *td)
1005{
1006 struct urb *urb = td->urb;
1007
1008 r8a66597_pipe_toggle(r8a66597, td->pipe, 1);
1009
1010 if (urb->setup_packet[0] & USB_ENDPOINT_DIR_MASK) {
1011 r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG);
1012 r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL);
1013 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
1014 r8a66597_write(r8a66597, BVAL | BCLR, CFIFOCTR);
1015 r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS);
1016 enable_irq_empty(r8a66597, 0);
1017 } else {
1018 r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
1019 r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
1020 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
1021 r8a66597_write(r8a66597, BCLR, CFIFOCTR);
1022 r8a66597_write(r8a66597, (u16)~BRDY0, BRDYSTS);
1023 r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS);
1024 enable_irq_ready(r8a66597, 0);
1025 }
1026 enable_irq_nrdy(r8a66597, 0);
1027 pipe_start(r8a66597, td->pipe);
1028}
1029
1030/* this function must be called with interrupt disabled */
1031static int start_transfer(struct r8a66597 *r8a66597, struct r8a66597_td *td)
1032{
1033 BUG_ON(!td);
1034
1035 switch (td->type) {
1036 case USB_PID_SETUP:
1037 if (td->urb->setup_packet[1] == USB_REQ_SET_ADDRESS) {
1038 td->set_address = 1;
1039 td->urb->setup_packet[2] = alloc_usb_address(r8a66597,
1040 td->urb);
1041 if (td->urb->setup_packet[2] == 0)
1042 return -EPIPE;
1043 }
1044 prepare_setup_packet(r8a66597, td);
1045 break;
1046 case USB_PID_IN:
1047 prepare_packet_read(r8a66597, td);
1048 break;
1049 case USB_PID_OUT:
1050 prepare_packet_write(r8a66597, td);
1051 break;
1052 case USB_PID_ACK:
1053 prepare_status_packet(r8a66597, td);
1054 break;
1055 default:
1056 err("invalid type.");
1057 break;
1058 }
1059
1060 return 0;
1061}
1062
1063static int check_transfer_finish(struct r8a66597_td *td, struct urb *urb)
1064{
1065 if (usb_pipeisoc(urb->pipe)) {
1066 if (urb->number_of_packets == td->iso_cnt)
1067 return 1;
1068 }
1069
1070 /* control or bulk or interrupt */
1071 if ((urb->transfer_buffer_length <= urb->actual_length) ||
1072 (td->short_packet) || (td->zero_packet))
1073 return 1;
1074
1075 return 0;
1076}
1077
1078/* this function must be called with interrupt disabled */
1079static void set_td_timer(struct r8a66597 *r8a66597, struct r8a66597_td *td)
1080{
1081 unsigned long time;
1082
1083 BUG_ON(!td);
1084
1085 if (!list_empty(&r8a66597->pipe_queue[td->pipenum]) &&
1086 !usb_pipecontrol(td->urb->pipe) && usb_pipein(td->urb->pipe)) {
1087 r8a66597->timeout_map |= 1 << td->pipenum;
1088 switch (usb_pipetype(td->urb->pipe)) {
1089 case PIPE_INTERRUPT:
1090 case PIPE_ISOCHRONOUS:
1091 time = 30;
1092 break;
1093 default:
1094 time = 300;
1095 break;
1096 }
1097
1098 mod_timer(&r8a66597->td_timer[td->pipenum],
1099 jiffies + msecs_to_jiffies(time));
1100 }
1101}
1102
1103/* this function must be called with interrupt disabled */
1104static void done(struct r8a66597 *r8a66597, struct r8a66597_td *td,
1105 u16 pipenum, struct urb *urb)
1106{
1107 int restart = 0;
1108 struct usb_hcd *hcd = r8a66597_to_hcd(r8a66597);
1109
1110 r8a66597->timeout_map &= ~(1 << pipenum);
1111
1112 if (likely(td)) {
1113 if (td->set_address && urb->status != 0)
1114 r8a66597->address_map &= ~(1 << urb->setup_packet[2]);
1115
1116 pipe_toggle_save(r8a66597, td->pipe, urb);
1117 list_del(&td->queue);
1118 kfree(td);
1119 }
1120
1121 if (!list_empty(&r8a66597->pipe_queue[pipenum]))
1122 restart = 1;
1123
1124 if (likely(urb)) {
1125 if (usb_pipeisoc(urb->pipe))
1126 urb->start_frame = r8a66597_get_frame(hcd);
1127
1128 urb->hcpriv = NULL;
1129 spin_unlock(&r8a66597->lock);
1130 usb_hcd_giveback_urb(hcd, urb);
1131 spin_lock(&r8a66597->lock);
1132 }
1133
1134 if (restart) {
1135 td = r8a66597_get_td(r8a66597, pipenum);
1136 if (unlikely(!td))
1137 return;
1138
1139 start_transfer(r8a66597, td);
1140 set_td_timer(r8a66597, td);
1141 }
1142}
1143
1144/* this function must be called with interrupt disabled */
1145static void finish_request(struct r8a66597 *r8a66597, struct r8a66597_td *td,
1146 u16 pipenum, struct urb *urb)
1147__releases(r8a66597->lock) __acquires(r8a66597->lock)
1148{
1149 done(r8a66597, td, pipenum, urb);
1150}
1151
1152static void packet_read(struct r8a66597 *r8a66597, u16 pipenum)
1153{
1154 u16 tmp;
1155 int rcv_len, bufsize, urb_len, size;
1156 u16 *buf;
1157 struct r8a66597_td *td = r8a66597_get_td(r8a66597, pipenum);
1158 struct urb *urb;
1159 int finish = 0;
1160
1161 if (unlikely(!td))
1162 return;
1163 urb = td->urb;
1164
1165 fifo_change_from_pipe(r8a66597, td->pipe);
1166 tmp = r8a66597_read(r8a66597, td->pipe->fifoctr);
1167 if (unlikely((tmp & FRDY) == 0)) {
1168 urb->status = -EPIPE;
1169 pipe_stop(r8a66597, td->pipe);
1170 pipe_irq_disable(r8a66597, pipenum);
1171 err("in fifo not ready (%d)", pipenum);
1172 finish_request(r8a66597, td, pipenum, td->urb);
1173 return;
1174 }
1175
1176 /* prepare parameters */
1177 rcv_len = tmp & DTLN;
1178 bufsize = td->maxpacket;
1179 if (usb_pipeisoc(urb->pipe)) {
1180 buf = (u16 *)(urb->transfer_buffer +
1181 urb->iso_frame_desc[td->iso_cnt].offset);
1182 urb_len = urb->iso_frame_desc[td->iso_cnt].length;
1183 } else {
1184 buf = (void *)urb->transfer_buffer + urb->actual_length;
1185 urb_len = urb->transfer_buffer_length - urb->actual_length;
1186 }
1187 if (rcv_len < bufsize)
1188 size = min(rcv_len, urb_len);
1189 else
1190 size = min(bufsize, urb_len);
1191
1192 /* update parameters */
1193 urb->actual_length += size;
1194 if (rcv_len == 0)
1195 td->zero_packet = 1;
1196 if ((size % td->maxpacket) > 0) {
1197 td->short_packet = 1;
1198 if (urb->transfer_buffer_length != urb->actual_length &&
1199 urb->transfer_flags & URB_SHORT_NOT_OK)
1200 td->urb->status = -EREMOTEIO;
1201 }
1202 if (usb_pipeisoc(urb->pipe)) {
1203 urb->iso_frame_desc[td->iso_cnt].actual_length = size;
1204 urb->iso_frame_desc[td->iso_cnt].status = 0;
1205 td->iso_cnt++;
1206 }
1207
1208 /* check transfer finish */
1209 if (check_transfer_finish(td, urb)) {
1210 pipe_stop(r8a66597, td->pipe);
1211 pipe_irq_disable(r8a66597, pipenum);
1212 finish = 1;
1213 }
1214
1215 /* read fifo */
1216 if (urb->transfer_buffer) {
1217 if (size == 0)
1218 r8a66597_write(r8a66597, BCLR, td->pipe->fifoctr);
1219 else
1220 r8a66597_read_fifo(r8a66597, td->pipe->fifoaddr,
1221 buf, size);
1222 }
1223
1224 if (finish && pipenum != 0) {
1225 if (td->urb->status == -EINPROGRESS)
1226 td->urb->status = 0;
1227 finish_request(r8a66597, td, pipenum, urb);
1228 }
1229}
1230
1231static void packet_write(struct r8a66597 *r8a66597, u16 pipenum)
1232{
1233 u16 tmp;
1234 int bufsize, size;
1235 u16 *buf;
1236 struct r8a66597_td *td = r8a66597_get_td(r8a66597, pipenum);
1237 struct urb *urb;
1238
1239 if (unlikely(!td))
1240 return;
1241 urb = td->urb;
1242
1243 fifo_change_from_pipe(r8a66597, td->pipe);
1244 tmp = r8a66597_read(r8a66597, td->pipe->fifoctr);
1245 if (unlikely((tmp & FRDY) == 0)) {
1246 urb->status = -EPIPE;
1247 pipe_stop(r8a66597, td->pipe);
1248 pipe_irq_disable(r8a66597, pipenum);
1249 err("out write fifo not ready. (%d)", pipenum);
1250 finish_request(r8a66597, td, pipenum, td->urb);
1251 return;
1252 }
1253
1254 /* prepare parameters */
1255 bufsize = td->maxpacket;
1256 if (usb_pipeisoc(urb->pipe)) {
1257 buf = (u16 *)(urb->transfer_buffer +
1258 urb->iso_frame_desc[td->iso_cnt].offset);
1259 size = min(bufsize,
1260 (int)urb->iso_frame_desc[td->iso_cnt].length);
1261 } else {
1262 buf = (u16 *)(urb->transfer_buffer + urb->actual_length);
1263 size = min((int)bufsize,
1264 urb->transfer_buffer_length - urb->actual_length);
1265 }
1266
1267 /* write fifo */
1268 if (pipenum > 0)
1269 r8a66597_write(r8a66597, (u16)~(1 << pipenum), BEMPSTS);
1270 if (urb->transfer_buffer) {
1271 r8a66597_write_fifo(r8a66597, td->pipe->fifoaddr, buf, size);
1272 if (!usb_pipebulk(urb->pipe) || td->maxpacket != size)
1273 r8a66597_write(r8a66597, BVAL, td->pipe->fifoctr);
1274 }
1275
1276 /* update parameters */
1277 urb->actual_length += size;
1278 if (usb_pipeisoc(urb->pipe)) {
1279 urb->iso_frame_desc[td->iso_cnt].actual_length = size;
1280 urb->iso_frame_desc[td->iso_cnt].status = 0;
1281 td->iso_cnt++;
1282 }
1283
1284 /* check transfer finish */
1285 if (check_transfer_finish(td, urb)) {
1286 disable_irq_ready(r8a66597, pipenum);
1287 enable_irq_empty(r8a66597, pipenum);
1288 if (!usb_pipeisoc(urb->pipe))
1289 enable_irq_nrdy(r8a66597, pipenum);
1290 } else
1291 pipe_irq_enable(r8a66597, urb, pipenum);
1292}
1293
1294
1295static void check_next_phase(struct r8a66597 *r8a66597)
1296{
1297 struct r8a66597_td *td = r8a66597_get_td(r8a66597, 0);
1298 struct urb *urb;
1299 u8 finish = 0;
1300
1301 if (unlikely(!td))
1302 return;
1303 urb = td->urb;
1304
1305 switch (td->type) {
1306 case USB_PID_IN:
1307 case USB_PID_OUT:
1308 if (urb->status != -EINPROGRESS) {
1309 finish = 1;
1310 break;
1311 }
1312 if (check_transfer_finish(td, urb))
1313 td->type = USB_PID_ACK;
1314 break;
1315 case USB_PID_SETUP:
1316 if (urb->status != -EINPROGRESS)
1317 finish = 1;
1318 else if (urb->transfer_buffer_length == urb->actual_length) {
1319 td->type = USB_PID_ACK;
1320 urb->status = 0;
1321 } else if (usb_pipeout(urb->pipe))
1322 td->type = USB_PID_OUT;
1323 else
1324 td->type = USB_PID_IN;
1325 break;
1326 case USB_PID_ACK:
1327 finish = 1;
1328 if (urb->status == -EINPROGRESS)
1329 urb->status = 0;
1330 break;
1331 }
1332
1333 if (finish)
1334 finish_request(r8a66597, td, 0, urb);
1335 else
1336 start_transfer(r8a66597, td);
1337}
1338
1339static void set_urb_error(struct r8a66597 *r8a66597, u16 pipenum)
1340{
1341 struct r8a66597_td *td = r8a66597_get_td(r8a66597, pipenum);
1342
1343 if (td && td->urb) {
1344 u16 pid = r8a66597_read(r8a66597, td->pipe->pipectr) & PID;
1345
1346 if (pid == PID_NAK)
1347 td->urb->status = -ECONNRESET;
1348 else
1349 td->urb->status = -EPIPE;
1350 }
1351}
1352
1353static void irq_pipe_ready(struct r8a66597 *r8a66597)
1354{
1355 u16 check;
1356 u16 pipenum;
1357 u16 mask;
1358 struct r8a66597_td *td;
1359
1360 mask = r8a66597_read(r8a66597, BRDYSTS)
1361 & r8a66597_read(r8a66597, BRDYENB);
1362 r8a66597_write(r8a66597, (u16)~mask, BRDYSTS);
1363 if (mask & BRDY0) {
1364 td = r8a66597_get_td(r8a66597, 0);
1365 if (td && td->type == USB_PID_IN)
1366 packet_read(r8a66597, 0);
1367 else
1368 pipe_irq_disable(r8a66597, 0);
1369 check_next_phase(r8a66597);
1370 }
1371
1372 for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
1373 check = 1 << pipenum;
1374 if (mask & check) {
1375 td = r8a66597_get_td(r8a66597, pipenum);
1376 if (unlikely(!td))
1377 continue;
1378
1379 if (td->type == USB_PID_IN)
1380 packet_read(r8a66597, pipenum);
1381 else if (td->type == USB_PID_OUT)
1382 packet_write(r8a66597, pipenum);
1383 }
1384 }
1385}
1386
1387static void irq_pipe_empty(struct r8a66597 *r8a66597)
1388{
1389 u16 tmp;
1390 u16 check;
1391 u16 pipenum;
1392 u16 mask;
1393 struct r8a66597_td *td;
1394
1395 mask = r8a66597_read(r8a66597, BEMPSTS)
1396 & r8a66597_read(r8a66597, BEMPENB);
1397 r8a66597_write(r8a66597, (u16)~mask, BEMPSTS);
1398 if (mask & BEMP0) {
1399 cfifo_change(r8a66597, 0);
1400 td = r8a66597_get_td(r8a66597, 0);
1401 if (td && td->type != USB_PID_OUT)
1402 disable_irq_empty(r8a66597, 0);
1403 check_next_phase(r8a66597);
1404 }
1405
1406 for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
1407 check = 1 << pipenum;
1408 if (mask & check) {
1409 struct r8a66597_td *td;
1410 td = r8a66597_get_td(r8a66597, pipenum);
1411 if (unlikely(!td))
1412 continue;
1413
1414 tmp = r8a66597_read(r8a66597, td->pipe->pipectr);
1415 if ((tmp & INBUFM) == 0) {
1416 disable_irq_empty(r8a66597, pipenum);
1417 pipe_irq_disable(r8a66597, pipenum);
1418 if (td->urb->status == -EINPROGRESS)
1419 td->urb->status = 0;
1420 finish_request(r8a66597, td, pipenum, td->urb);
1421 }
1422 }
1423 }
1424}
1425
1426static void irq_pipe_nrdy(struct r8a66597 *r8a66597)
1427{
1428 u16 check;
1429 u16 pipenum;
1430 u16 mask;
1431
1432 mask = r8a66597_read(r8a66597, NRDYSTS)
1433 & r8a66597_read(r8a66597, NRDYENB);
1434 r8a66597_write(r8a66597, (u16)~mask, NRDYSTS);
1435 if (mask & NRDY0) {
1436 cfifo_change(r8a66597, 0);
1437 set_urb_error(r8a66597, 0);
1438 pipe_irq_disable(r8a66597, 0);
1439 check_next_phase(r8a66597);
1440 }
1441
1442 for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
1443 check = 1 << pipenum;
1444 if (mask & check) {
1445 struct r8a66597_td *td;
1446 td = r8a66597_get_td(r8a66597, pipenum);
1447 if (unlikely(!td))
1448 continue;
1449
1450 set_urb_error(r8a66597, pipenum);
1451 pipe_irq_disable(r8a66597, pipenum);
1452 pipe_stop(r8a66597, td->pipe);
1453 finish_request(r8a66597, td, pipenum, td->urb);
1454 }
1455 }
1456}
1457
1458static void start_root_hub_sampling(struct r8a66597 *r8a66597, int port)
1459{
1460 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
1461
1462 rh->old_syssts = r8a66597_read(r8a66597, get_syssts_reg(port)) & LNST;
1463 rh->scount = R8A66597_MAX_SAMPLING;
1464 mod_timer(&r8a66597->rh_timer, jiffies + msecs_to_jiffies(50));
1465}
1466
1467static irqreturn_t r8a66597_irq(struct usb_hcd *hcd)
1468{
1469 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1470 u16 intsts0, intsts1, intsts2;
1471 u16 intenb0, intenb1, intenb2;
1472 u16 mask0, mask1, mask2;
1473
1474 spin_lock(&r8a66597->lock);
1475
1476 intsts0 = r8a66597_read(r8a66597, INTSTS0);
1477 intsts1 = r8a66597_read(r8a66597, INTSTS1);
1478 intsts2 = r8a66597_read(r8a66597, INTSTS2);
1479 intenb0 = r8a66597_read(r8a66597, INTENB0);
1480 intenb1 = r8a66597_read(r8a66597, INTENB1);
1481 intenb2 = r8a66597_read(r8a66597, INTENB2);
1482
1483 mask2 = intsts2 & intenb2;
1484 mask1 = intsts1 & intenb1;
1485 mask0 = intsts0 & intenb0 & (BEMP | NRDY | BRDY);
1486 if (mask2) {
1487 if (mask2 & ATTCH) {
1488 r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS2);
1489 r8a66597_bclr(r8a66597, ATTCHE, INTENB2);
1490
1491 /* start usb bus sampling */
1492 start_root_hub_sampling(r8a66597, 1);
1493 }
1494 if (mask2 & DTCH) {
1495 r8a66597_write(r8a66597, (u16)~DTCH, INTSTS2);
1496 r8a66597_bclr(r8a66597, DTCHE, INTENB2);
1497 r8a66597_usb_disconnect(r8a66597, 1);
1498 }
1499 }
1500
1501 if (mask1) {
1502 if (mask1 & ATTCH) {
1503 r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS1);
1504 r8a66597_bclr(r8a66597, ATTCHE, INTENB1);
1505
1506 /* start usb bus sampling */
1507 start_root_hub_sampling(r8a66597, 0);
1508 }
1509 if (mask1 & DTCH) {
1510 r8a66597_write(r8a66597, (u16)~DTCH, INTSTS1);
1511 r8a66597_bclr(r8a66597, DTCHE, INTENB1);
1512 r8a66597_usb_disconnect(r8a66597, 0);
1513 }
1514 if (mask1 & SIGN) {
1515 r8a66597_write(r8a66597, (u16)~SIGN, INTSTS1);
1516 set_urb_error(r8a66597, 0);
1517 check_next_phase(r8a66597);
1518 }
1519 if (mask1 & SACK) {
1520 r8a66597_write(r8a66597, (u16)~SACK, INTSTS1);
1521 check_next_phase(r8a66597);
1522 }
1523 }
1524 if (mask0) {
1525 if (mask0 & BRDY)
1526 irq_pipe_ready(r8a66597);
1527 if (mask0 & BEMP)
1528 irq_pipe_empty(r8a66597);
1529 if (mask0 & NRDY)
1530 irq_pipe_nrdy(r8a66597);
1531 }
1532
1533 spin_unlock(&r8a66597->lock);
1534 return IRQ_HANDLED;
1535}
1536
1537/* this function must be called with interrupt disabled */
1538static void r8a66597_root_hub_control(struct r8a66597 *r8a66597, int port)
1539{
1540 u16 tmp;
1541 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
1542
1543 if (rh->port & (1 << USB_PORT_FEAT_RESET)) {
1544 unsigned long dvstctr_reg = get_dvstctr_reg(port);
1545
1546 tmp = r8a66597_read(r8a66597, dvstctr_reg);
1547 if ((tmp & USBRST) == USBRST) {
1548 r8a66597_mdfy(r8a66597, UACT, USBRST | UACT,
1549 dvstctr_reg);
1550 mod_timer(&r8a66597->rh_timer,
1551 jiffies + msecs_to_jiffies(50));
1552 } else
1553 r8a66597_usb_connect(r8a66597, port);
1554 }
1555
1556 if (rh->scount > 0) {
1557 tmp = r8a66597_read(r8a66597, get_syssts_reg(port)) & LNST;
1558 if (tmp == rh->old_syssts) {
1559 rh->scount--;
1560 if (rh->scount == 0) {
1561 if (tmp == FS_JSTS) {
1562 r8a66597_bset(r8a66597, HSE,
1563 get_syscfg_reg(port));
1564 r8a66597_usb_preconnect(r8a66597, port);
1565 } else if (tmp == LS_JSTS) {
1566 r8a66597_bclr(r8a66597, HSE,
1567 get_syscfg_reg(port));
1568 r8a66597_usb_preconnect(r8a66597, port);
1569 } else if (tmp == SE0)
1570 r8a66597_bset(r8a66597, ATTCHE,
1571 get_intenb_reg(port));
1572 } else {
1573 mod_timer(&r8a66597->rh_timer,
1574 jiffies + msecs_to_jiffies(50));
1575 }
1576 } else {
1577 rh->scount = R8A66597_MAX_SAMPLING;
1578 rh->old_syssts = tmp;
1579 mod_timer(&r8a66597->rh_timer,
1580 jiffies + msecs_to_jiffies(50));
1581 }
1582 }
1583}
1584
1585static void r8a66597_td_timer(unsigned long _r8a66597)
1586{
1587 struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
1588 unsigned long flags;
1589 u16 pipenum;
1590 struct r8a66597_td *td, *new_td = NULL;
1591 struct r8a66597_pipe *pipe;
1592
1593 spin_lock_irqsave(&r8a66597->lock, flags);
1594 for (pipenum = 0; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
1595 if (!(r8a66597->timeout_map & (1 << pipenum)))
1596 continue;
1597 if (timer_pending(&r8a66597->td_timer[pipenum]))
1598 continue;
1599
1600 td = r8a66597_get_td(r8a66597, pipenum);
1601 if (!td) {
1602 r8a66597->timeout_map &= ~(1 << pipenum);
1603 continue;
1604 }
1605
1606 if (td->urb->actual_length) {
1607 set_td_timer(r8a66597, td);
1608 break;
1609 }
1610
1611 pipe = td->pipe;
1612 pipe_stop(r8a66597, pipe);
1613
1614 new_td = td;
1615 do {
1616 list_move_tail(&new_td->queue,
1617 &r8a66597->pipe_queue[pipenum]);
1618 new_td = r8a66597_get_td(r8a66597, pipenum);
1619 if (!new_td) {
1620 new_td = td;
1621 break;
1622 }
1623 } while (td != new_td && td->address == new_td->address);
1624
1625 start_transfer(r8a66597, new_td);
1626
1627 if (td == new_td)
1628 r8a66597->timeout_map &= ~(1 << pipenum);
1629 else
1630 set_td_timer(r8a66597, new_td);
1631 break;
1632 }
1633 spin_unlock_irqrestore(&r8a66597->lock, flags);
1634}
1635
1636static void r8a66597_timer(unsigned long _r8a66597)
1637{
1638 struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
1639 unsigned long flags;
1640
1641 spin_lock_irqsave(&r8a66597->lock, flags);
1642
1643 r8a66597_root_hub_control(r8a66597, 0);
1644 r8a66597_root_hub_control(r8a66597, 1);
1645
1646 spin_unlock_irqrestore(&r8a66597->lock, flags);
1647}
1648
1649static int check_pipe_config(struct r8a66597 *r8a66597, struct urb *urb)
1650{
1651 struct r8a66597_device *dev = get_urb_to_r8a66597_dev(r8a66597, urb);
1652
1653 if (dev && dev->address && dev->state != USB_STATE_CONFIGURED &&
1654 (urb->dev->state == USB_STATE_CONFIGURED))
1655 return 1;
1656 else
1657 return 0;
1658}
1659
1660static int r8a66597_start(struct usb_hcd *hcd)
1661{
1662 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1663 int ret;
1664
1665 hcd->state = HC_STATE_RUNNING;
1666 if ((ret = enable_controller(r8a66597)) < 0)
1667 return ret;
1668
1669 return 0;
1670}
1671
1672static void r8a66597_stop(struct usb_hcd *hcd)
1673{
1674 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1675
1676 disable_controller(r8a66597);
1677}
1678
1679static void set_address_zero(struct r8a66597 *r8a66597, struct urb *urb)
1680{
1681 unsigned int usb_address = usb_pipedevice(urb->pipe);
1682 u16 root_port, hub_port;
1683
1684 if (usb_address == 0) {
1685 get_port_number(urb->dev->devpath,
1686 &root_port, &hub_port);
1687 set_devadd_reg(r8a66597, 0,
1688 get_r8a66597_usb_speed(urb->dev->speed),
1689 get_parent_r8a66597_address(r8a66597, urb->dev),
1690 hub_port, root_port);
1691 }
1692}
1693
1694static struct r8a66597_td *r8a66597_make_td(struct r8a66597 *r8a66597,
1695 struct urb *urb,
1696 struct usb_host_endpoint *hep,
1697 gfp_t mem_flags)
1698{
1699 struct r8a66597_td *td;
1700 u16 pipenum;
1701
1702 td = kzalloc(sizeof(struct r8a66597_td), mem_flags);
1703 if (td == NULL)
1704 return NULL;
1705
1706 pipenum = r8a66597_get_pipenum(urb, hep);
1707 td->pipenum = pipenum;
1708 td->pipe = hep->hcpriv;
1709 td->urb = urb;
1710 td->address = get_urb_to_r8a66597_addr(r8a66597, urb);
1711 td->maxpacket = usb_maxpacket(urb->dev, urb->pipe,
1712 !usb_pipein(urb->pipe));
1713 if (usb_pipecontrol(urb->pipe))
1714 td->type = USB_PID_SETUP;
1715 else if (usb_pipein(urb->pipe))
1716 td->type = USB_PID_IN;
1717 else
1718 td->type = USB_PID_OUT;
1719 INIT_LIST_HEAD(&td->queue);
1720
1721 return td;
1722}
1723
1724static int r8a66597_urb_enqueue(struct usb_hcd *hcd,
1725 struct usb_host_endpoint *hep,
1726 struct urb *urb,
1727 gfp_t mem_flags)
1728{
1729 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1730 struct r8a66597_td *td = NULL;
1731 int ret = 0, request = 0;
1732 unsigned long flags;
1733
1734 spin_lock_irqsave(&r8a66597->lock, flags);
1735 if (!get_urb_to_r8a66597_dev(r8a66597, urb)) {
1736 ret = -ENODEV;
1737 goto error;
1738 }
1739
1740 if (!hep->hcpriv) {
1741 hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe), mem_flags);
1742 if (!hep->hcpriv) {
1743 ret = -ENOMEM;
1744 goto error;
1745 }
1746 set_pipe_reg_addr(hep->hcpriv, R8A66597_PIPE_NO_DMA);
1747 if (usb_pipeendpoint(urb->pipe))
1748 init_pipe_info(r8a66597, urb, hep, &hep->desc);
1749 }
1750
1751 if (unlikely(check_pipe_config(r8a66597, urb)))
1752 init_pipe_config(r8a66597, urb);
1753
1754 set_address_zero(r8a66597, urb);
1755 td = r8a66597_make_td(r8a66597, urb, hep, mem_flags);
1756 if (td == NULL) {
1757 ret = -ENOMEM;
1758 goto error;
1759 }
1760 if (list_empty(&r8a66597->pipe_queue[td->pipenum]))
1761 request = 1;
1762 list_add_tail(&td->queue, &r8a66597->pipe_queue[td->pipenum]);
1763
1764 spin_lock(&urb->lock);
1765 if (urb->status != -EINPROGRESS) {
1766 spin_unlock(&urb->lock);
1767 ret = -EPIPE;
1768 goto error;
1769 }
1770 urb->hcpriv = td;
1771 spin_unlock(&urb->lock);
1772
1773 if (request) {
1774 ret = start_transfer(r8a66597, td);
1775 if (ret < 0) {
1776 list_del(&td->queue);
1777 kfree(td);
1778 }
1779 } else
1780 set_td_timer(r8a66597, td);
1781
1782error:
1783 spin_unlock_irqrestore(&r8a66597->lock, flags);
1784 return ret;
1785}
1786
1787static int r8a66597_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
1788{
1789 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1790 struct r8a66597_td *td;
1791 unsigned long flags;
1792
1793 spin_lock_irqsave(&r8a66597->lock, flags);
1794 if (urb->hcpriv) {
1795 td = urb->hcpriv;
1796 pipe_stop(r8a66597, td->pipe);
1797 pipe_irq_disable(r8a66597, td->pipenum);
1798 disable_irq_empty(r8a66597, td->pipenum);
1799 done(r8a66597, td, td->pipenum, urb);
1800 }
1801 spin_unlock_irqrestore(&r8a66597->lock, flags);
1802 return 0;
1803}
1804
1805static void r8a66597_endpoint_disable(struct usb_hcd *hcd,
1806 struct usb_host_endpoint *hep)
1807{
1808 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1809 struct r8a66597_pipe *pipe = (struct r8a66597_pipe *)hep->hcpriv;
1810 struct r8a66597_td *td;
1811 struct urb *urb = NULL;
1812 u16 pipenum;
1813 unsigned long flags;
1814
1815 if (pipe == NULL)
1816 return;
1817 pipenum = pipe->info.pipenum;
1818
1819 if (pipenum == 0) {
1820 kfree(hep->hcpriv);
1821 hep->hcpriv = NULL;
1822 return;
1823 }
1824
1825 spin_lock_irqsave(&r8a66597->lock, flags);
1826 pipe_stop(r8a66597, pipe);
1827 pipe_irq_disable(r8a66597, pipenum);
1828 disable_irq_empty(r8a66597, pipenum);
1829 td = r8a66597_get_td(r8a66597, pipenum);
1830 if (td)
1831 urb = td->urb;
1832 done(r8a66597, td, pipenum, urb);
1833 kfree(hep->hcpriv);
1834 hep->hcpriv = NULL;
1835 spin_unlock_irqrestore(&r8a66597->lock, flags);
1836}
1837
1838static int r8a66597_get_frame(struct usb_hcd *hcd)
1839{
1840 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1841 return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
1842}
1843
1844static void collect_usb_address_map(struct usb_device *udev, unsigned long *map)
1845{
1846 int chix;
1847
1848 if (udev->state == USB_STATE_CONFIGURED &&
1849 udev->parent && udev->parent->devnum > 1 &&
1850 udev->parent->descriptor.bDeviceClass == USB_CLASS_HUB)
1851 map[udev->devnum/32] |= (1 << (udev->devnum % 32));
1852
1853 for (chix = 0; chix < udev->maxchild; chix++) {
1854 struct usb_device *childdev = udev->children[chix];
1855
1856 if (childdev)
1857 collect_usb_address_map(childdev, map);
1858 }
1859}
1860
1861/* this function must be called with interrupt disabled */
1862static struct r8a66597_device *get_r8a66597_device(struct r8a66597 *r8a66597,
1863 int addr)
1864{
1865 struct r8a66597_device *dev;
1866 struct list_head *list = &r8a66597->child_device;
1867
1868 list_for_each_entry(dev, list, device_list) {
1869 if (!dev)
1870 continue;
1871 if (dev->usb_address != addr)
1872 continue;
1873
1874 return dev;
1875 }
1876
1877 err("get_r8a66597_device fail.(%d)\n", addr);
1878 return NULL;
1879}
1880
1881static void update_usb_address_map(struct r8a66597 *r8a66597,
1882 struct usb_device *root_hub,
1883 unsigned long *map)
1884{
1885 int i, j, addr;
1886 unsigned long diff;
1887 unsigned long flags;
1888
1889 for (i = 0; i < 4; i++) {
1890 diff = r8a66597->child_connect_map[i] ^ map[i];
1891 if (!diff)
1892 continue;
1893
1894 for (j = 0; j < 32; j++) {
1895 if (!(diff & (1 << j)))
1896 continue;
1897
1898 addr = i * 32 + j;
1899 if (map[i] & (1 << j))
1900 set_child_connect_map(r8a66597, addr);
1901 else {
1902 struct r8a66597_device *dev;
1903
1904 spin_lock_irqsave(&r8a66597->lock, flags);
1905 dev = get_r8a66597_device(r8a66597, addr);
1906 disable_r8a66597_pipe_all(r8a66597, dev);
1907 free_usb_address(r8a66597, dev);
1908 put_child_connect_map(r8a66597, addr);
1909 spin_unlock_irqrestore(&r8a66597->lock, flags);
1910 }
1911 }
1912 }
1913}
1914
1915static void r8a66597_check_detect_child(struct r8a66597 *r8a66597,
1916 struct usb_hcd *hcd)
1917{
1918 struct usb_bus *bus;
1919 unsigned long now_map[4];
1920
1921 memset(now_map, 0, sizeof(now_map));
1922
1923 list_for_each_entry(bus, &usb_bus_list, bus_list) {
1924 if (!bus->root_hub)
1925 continue;
1926
1927 if (bus->busnum != hcd->self.busnum)
1928 continue;
1929
1930 collect_usb_address_map(bus->root_hub, now_map);
1931 update_usb_address_map(r8a66597, bus->root_hub, now_map);
1932 }
1933}
1934
1935static int r8a66597_hub_status_data(struct usb_hcd *hcd, char *buf)
1936{
1937 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1938 unsigned long flags;
1939 int i;
1940
1941 r8a66597_check_detect_child(r8a66597, hcd);
1942
1943 spin_lock_irqsave(&r8a66597->lock, flags);
1944
1945 *buf = 0; /* initialize (no change) */
1946
1947 for (i = 0; i < R8A66597_MAX_ROOT_HUB; i++) {
1948 if (r8a66597->root_hub[i].port & 0xffff0000)
1949 *buf |= 1 << (i + 1);
1950 }
1951
1952 spin_unlock_irqrestore(&r8a66597->lock, flags);
1953
1954 return (*buf != 0);
1955}
1956
1957static void r8a66597_hub_descriptor(struct r8a66597 *r8a66597,
1958 struct usb_hub_descriptor *desc)
1959{
1960 desc->bDescriptorType = 0x29;
1961 desc->bHubContrCurrent = 0;
1962 desc->bNbrPorts = R8A66597_MAX_ROOT_HUB;
1963 desc->bDescLength = 9;
1964 desc->bPwrOn2PwrGood = 0;
1965 desc->wHubCharacteristics = cpu_to_le16(0x0011);
1966 desc->bitmap[0] = ((1 << R8A66597_MAX_ROOT_HUB) - 1) << 1;
1967 desc->bitmap[1] = ~0;
1968}
1969
1970static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1971 u16 wIndex, char *buf, u16 wLength)
1972{
1973 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
1974 int ret;
1975 int port = (wIndex & 0x00FF) - 1;
1976 struct r8a66597_root_hub *rh = &r8a66597->root_hub[port];
1977 unsigned long flags;
1978
1979 ret = 0;
1980
1981 spin_lock_irqsave(&r8a66597->lock, flags);
1982 switch (typeReq) {
1983 case ClearHubFeature:
1984 case SetHubFeature:
1985 switch (wValue) {
1986 case C_HUB_OVER_CURRENT:
1987 case C_HUB_LOCAL_POWER:
1988 break;
1989 default:
1990 goto error;
1991 }
1992 break;
1993 case ClearPortFeature:
1994 if (wIndex > R8A66597_MAX_ROOT_HUB)
1995 goto error;
1996 if (wLength != 0)
1997 goto error;
1998
1999 switch (wValue) {
2000 case USB_PORT_FEAT_ENABLE:
2001 rh->port &= (1 << USB_PORT_FEAT_POWER);
2002 break;
2003 case USB_PORT_FEAT_SUSPEND:
2004 break;
2005 case USB_PORT_FEAT_POWER:
2006 r8a66597_port_power(r8a66597, port, 0);
2007 break;
2008 case USB_PORT_FEAT_C_ENABLE:
2009 case USB_PORT_FEAT_C_SUSPEND:
2010 case USB_PORT_FEAT_C_CONNECTION:
2011 case USB_PORT_FEAT_C_OVER_CURRENT:
2012 case USB_PORT_FEAT_C_RESET:
2013 break;
2014 default:
2015 goto error;
2016 }
2017 rh->port &= ~(1 << wValue);
2018 break;
2019 case GetHubDescriptor:
2020 r8a66597_hub_descriptor(r8a66597,
2021 (struct usb_hub_descriptor *)buf);
2022 break;
2023 case GetHubStatus:
2024 *buf = 0x00;
2025 break;
2026 case GetPortStatus:
2027 if (wIndex > R8A66597_MAX_ROOT_HUB)
2028 goto error;
2029 *(u32 *)buf = rh->port;
2030 break;
2031 case SetPortFeature:
2032 if (wIndex > R8A66597_MAX_ROOT_HUB)
2033 goto error;
2034 if (wLength != 0)
2035 goto error;
2036
2037 switch (wValue) {
2038 case USB_PORT_FEAT_SUSPEND:
2039 break;
2040 case USB_PORT_FEAT_POWER:
2041 r8a66597_port_power(r8a66597, port, 1);
2042 rh->port |= (1 << USB_PORT_FEAT_POWER);
2043 break;
2044 case USB_PORT_FEAT_RESET: {
2045 struct r8a66597_device *dev = rh->dev;
2046
2047 rh->port |= (1 << USB_PORT_FEAT_RESET);
2048
2049 disable_r8a66597_pipe_all(r8a66597, dev);
2050 free_usb_address(r8a66597, dev);
2051
2052 r8a66597_mdfy(r8a66597, USBRST, USBRST | UACT,
2053 get_dvstctr_reg(port));
2054 mod_timer(&r8a66597->rh_timer,
2055 jiffies + msecs_to_jiffies(50));
2056 }
2057 break;
2058 default:
2059 goto error;
2060 }
2061 rh->port |= 1 << wValue;
2062 break;
2063 default:
2064error:
2065 ret = -EPIPE;
2066 break;
2067 }
2068
2069 spin_unlock_irqrestore(&r8a66597->lock, flags);
2070 return ret;
2071}
2072
2073static struct hc_driver r8a66597_hc_driver = {
2074 .description = hcd_name,
2075 .hcd_priv_size = sizeof(struct r8a66597),
2076 .irq = r8a66597_irq,
2077
2078 /*
2079 * generic hardware linkage
2080 */
2081 .flags = HCD_USB2,
2082
2083 .start = r8a66597_start,
2084 .stop = r8a66597_stop,
2085
2086 /*
2087 * managing i/o requests and associated device resources
2088 */
2089 .urb_enqueue = r8a66597_urb_enqueue,
2090 .urb_dequeue = r8a66597_urb_dequeue,
2091 .endpoint_disable = r8a66597_endpoint_disable,
2092
2093 /*
2094 * periodic schedule support
2095 */
2096 .get_frame_number = r8a66597_get_frame,
2097
2098 /*
2099 * root hub support
2100 */
2101 .hub_status_data = r8a66597_hub_status_data,
2102 .hub_control = r8a66597_hub_control,
2103};
2104
2105#if defined(CONFIG_PM)
2106static int r8a66597_suspend(struct platform_device *pdev, pm_message_t state)
2107{
2108 pdev->dev.power.power_state = state;
2109 return 0;
2110}
2111
2112static int r8a66597_resume(struct platform_device *pdev)
2113{
2114 pdev->dev.power.power_state = PMSG_ON;
2115 return 0;
2116}
2117#else /* if defined(CONFIG_PM) */
2118#define r8a66597_suspend NULL
2119#define r8a66597_resume NULL
2120#endif
2121
2122static int __init_or_module r8a66597_remove(struct platform_device *pdev)
2123{
2124 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
2125 struct usb_hcd *hcd = r8a66597_to_hcd(r8a66597);
2126
2127 del_timer_sync(&r8a66597->rh_timer);
2128 iounmap((void *)r8a66597->reg);
2129 usb_remove_hcd(hcd);
2130 usb_put_hcd(hcd);
2131 return 0;
2132}
2133
2134#define resource_len(r) (((r)->end - (r)->start) + 1)
2135static int __init r8a66597_probe(struct platform_device *pdev)
2136{
2137 struct resource *res = NULL;
2138 int irq = -1;
2139 void __iomem *reg = NULL;
2140 struct usb_hcd *hcd = NULL;
2141 struct r8a66597 *r8a66597;
2142 int ret = 0;
2143 int i;
2144
2145 if (pdev->dev.dma_mask) {
2146 ret = -EINVAL;
2147 err("dma not support");
2148 goto clean_up;
2149 }
2150
2151 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2152 (char *)hcd_name);
2153 if (!res) {
2154 ret = -ENODEV;
2155 err("platform_get_resource_byname error.");
2156 goto clean_up;
2157 }
2158
2159 irq = platform_get_irq(pdev, 0);
2160 if (irq < 0) {
2161 ret = -ENODEV;
2162 err("platform_get_irq error.");
2163 goto clean_up;
2164 }
2165
2166 reg = ioremap(res->start, resource_len(res));
2167 if (reg == NULL) {
2168 ret = -ENOMEM;
2169 err("ioremap error.");
2170 goto clean_up;
2171 }
2172
2173 /* initialize hcd */
2174 hcd = usb_create_hcd(&r8a66597_hc_driver, &pdev->dev, (char *)hcd_name);
2175 if (!hcd) {
2176 ret = -ENOMEM;
2177 err("Failed to create hcd");
2178 goto clean_up;
2179 }
2180 r8a66597 = hcd_to_r8a66597(hcd);
2181 memset(r8a66597, 0, sizeof(struct r8a66597));
2182 dev_set_drvdata(&pdev->dev, r8a66597);
2183
2184 spin_lock_init(&r8a66597->lock);
2185 init_timer(&r8a66597->rh_timer);
2186 r8a66597->rh_timer.function = r8a66597_timer;
2187 r8a66597->rh_timer.data = (unsigned long)r8a66597;
2188 r8a66597->reg = (unsigned long)reg;
2189
2190 for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
2191 INIT_LIST_HEAD(&r8a66597->pipe_queue[i]);
2192 init_timer(&r8a66597->td_timer[i]);
2193 r8a66597->td_timer[i].function = r8a66597_td_timer;
2194 r8a66597->td_timer[i].data = (unsigned long)r8a66597;
2195 }
2196 INIT_LIST_HEAD(&r8a66597->child_device);
2197
2198 hcd->rsrc_start = res->start;
2199 ret = usb_add_hcd(hcd, irq, 0);
2200 if (ret != 0) {
2201 err("Failed to add hcd");
2202 goto clean_up;
2203 }
2204
2205 return 0;
2206
2207clean_up:
2208 if (reg)
2209 iounmap(reg);
2210 if (res)
2211 release_mem_region(res->start, 1);
2212
2213 return ret;
2214}
2215
2216static struct platform_driver r8a66597_driver = {
2217 .probe = r8a66597_probe,
2218 .remove = r8a66597_remove,
2219 .suspend = r8a66597_suspend,
2220 .resume = r8a66597_resume,
2221 .driver = {
2222 .name = (char *) hcd_name,
2223 },
2224};
2225
2226static int __init r8a66597_init(void)
2227{
2228 if (usb_disabled())
2229 return -ENODEV;
2230
2231 info("driver %s, %s", hcd_name, DRIVER_VERSION);
2232 return platform_driver_register(&r8a66597_driver);
2233}
2234module_init(r8a66597_init);
2235
2236static void __exit r8a66597_cleanup(void)
2237{
2238 platform_driver_unregister(&r8a66597_driver);
2239}
2240module_exit(r8a66597_cleanup);
2241
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
new file mode 100644
index 000000000000..97c2a71ac7a1
--- /dev/null
+++ b/drivers/usb/host/r8a66597.h
@@ -0,0 +1,634 @@
1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26#ifndef __R8A66597_H__
27#define __R8A66597_H__
28
29#define SYSCFG0 0x00
30#define SYSCFG1 0x02
31#define SYSSTS0 0x04
32#define SYSSTS1 0x06
33#define DVSTCTR0 0x08
34#define DVSTCTR1 0x0A
35#define TESTMODE 0x0C
36#define PINCFG 0x0E
37#define DMA0CFG 0x10
38#define DMA1CFG 0x12
39#define CFIFO 0x14
40#define D0FIFO 0x18
41#define D1FIFO 0x1C
42#define CFIFOSEL 0x20
43#define CFIFOCTR 0x22
44#define CFIFOSIE 0x24
45#define D0FIFOSEL 0x28
46#define D0FIFOCTR 0x2A
47#define D1FIFOSEL 0x2C
48#define D1FIFOCTR 0x2E
49#define INTENB0 0x30
50#define INTENB1 0x32
51#define INTENB2 0x34
52#define BRDYENB 0x36
53#define NRDYENB 0x38
54#define BEMPENB 0x3A
55#define SOFCFG 0x3C
56#define INTSTS0 0x40
57#define INTSTS1 0x42
58#define INTSTS2 0x44
59#define BRDYSTS 0x46
60#define NRDYSTS 0x48
61#define BEMPSTS 0x4A
62#define FRMNUM 0x4C
63#define UFRMNUM 0x4E
64#define USBADDR 0x50
65#define USBREQ 0x54
66#define USBVAL 0x56
67#define USBINDX 0x58
68#define USBLENG 0x5A
69#define DCPCFG 0x5C
70#define DCPMAXP 0x5E
71#define DCPCTR 0x60
72#define PIPESEL 0x64
73#define PIPECFG 0x68
74#define PIPEBUF 0x6A
75#define PIPEMAXP 0x6C
76#define PIPEPERI 0x6E
77#define PIPE1CTR 0x70
78#define PIPE2CTR 0x72
79#define PIPE3CTR 0x74
80#define PIPE4CTR 0x76
81#define PIPE5CTR 0x78
82#define PIPE6CTR 0x7A
83#define PIPE7CTR 0x7C
84#define PIPE8CTR 0x7E
85#define PIPE9CTR 0x80
86#define PIPE1TRE 0x90
87#define PIPE1TRN 0x92
88#define PIPE2TRE 0x94
89#define PIPE2TRN 0x96
90#define PIPE3TRE 0x98
91#define PIPE3TRN 0x9A
92#define PIPE4TRE 0x9C
93#define PIPE4TRN 0x9E
94#define PIPE5TRE 0xA0
95#define PIPE5TRN 0xA2
96#define DEVADD0 0xD0
97#define DEVADD1 0xD2
98#define DEVADD2 0xD4
99#define DEVADD3 0xD6
100#define DEVADD4 0xD8
101#define DEVADD5 0xDA
102#define DEVADD6 0xDC
103#define DEVADD7 0xDE
104#define DEVADD8 0xE0
105#define DEVADD9 0xE2
106#define DEVADDA 0xE4
107
108/* System Configuration Control Register */
109#define XTAL 0xC000 /* b15-14: Crystal selection */
110#define XTAL48 0x8000 /* 48MHz */
111#define XTAL24 0x4000 /* 24MHz */
112#define XTAL12 0x0000 /* 12MHz */
113#define XCKE 0x2000 /* b13: External clock enable */
114#define PLLC 0x0800 /* b11: PLL control */
115#define SCKE 0x0400 /* b10: USB clock enable */
116#define PCSDIS 0x0200 /* b9: not CS wakeup */
117#define LPSME 0x0100 /* b8: Low power sleep mode */
118#define HSE 0x0080 /* b7: Hi-speed enable */
119#define DCFM 0x0040 /* b6: Controller function select */
120#define DRPD 0x0020 /* b5: D+/- pull down control */
121#define DPRPU 0x0010 /* b4: D+ pull up control */
122#define USBE 0x0001 /* b0: USB module operation enable */
123
124/* System Configuration Status Register */
125#define OVCBIT 0x8000 /* b15-14: Over-current bit */
126#define OVCMON 0xC000 /* b15-14: Over-current monitor */
127#define SOFEA 0x0020 /* b5: SOF monitor */
128#define IDMON 0x0004 /* b3: ID-pin monitor */
129#define LNST 0x0003 /* b1-0: D+, D- line status */
130#define SE1 0x0003 /* SE1 */
131#define FS_KSTS 0x0002 /* Full-Speed K State */
132#define FS_JSTS 0x0001 /* Full-Speed J State */
133#define LS_JSTS 0x0002 /* Low-Speed J State */
134#define LS_KSTS 0x0001 /* Low-Speed K State */
135#define SE0 0x0000 /* SE0 */
136
137/* Device State Control Register */
138#define EXTLP0 0x0400 /* b10: External port */
139#define VBOUT 0x0200 /* b9: VBUS output */
140#define WKUP 0x0100 /* b8: Remote wakeup */
141#define RWUPE 0x0080 /* b7: Remote wakeup sense */
142#define USBRST 0x0040 /* b6: USB reset enable */
143#define RESUME 0x0020 /* b5: Resume enable */
144#define UACT 0x0010 /* b4: USB bus enable */
145#define RHST 0x0007 /* b1-0: Reset handshake status */
146#define HSPROC 0x0004 /* HS handshake is processing */
147#define HSMODE 0x0003 /* Hi-Speed mode */
148#define FSMODE 0x0002 /* Full-Speed mode */
149#define LSMODE 0x0001 /* Low-Speed mode */
150#define UNDECID 0x0000 /* Undecided */
151
152/* Test Mode Register */
153#define UTST 0x000F /* b3-0: Test select */
154#define H_TST_PACKET 0x000C /* HOST TEST Packet */
155#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
156#define H_TST_K 0x000A /* HOST TEST K */
157#define H_TST_J 0x0009 /* HOST TEST J */
158#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
159#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
160#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
161#define P_TST_K 0x0002 /* PERI TEST K */
162#define P_TST_J 0x0001 /* PERI TEST J */
163#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
164
165/* Data Pin Configuration Register */
166#define LDRV 0x8000 /* b15: Drive Current Adjust */
167#define VIF1 0x0000 /* VIF = 1.8V */
168#define VIF3 0x8000 /* VIF = 3.3V */
169#define INTA 0x0001 /* b1: USB INT-pin active */
170
171/* DMAx Pin Configuration Register */
172#define DREQA 0x4000 /* b14: Dreq active select */
173#define BURST 0x2000 /* b13: Burst mode */
174#define DACKA 0x0400 /* b10: Dack active select */
175#define DFORM 0x0380 /* b9-7: DMA mode select */
176#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
177#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
178#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
179#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
180#define DENDA 0x0040 /* b6: Dend active select */
181#define PKTM 0x0020 /* b5: Packet mode */
182#define DENDE 0x0010 /* b4: Dend enable */
183#define OBUS 0x0004 /* b2: OUTbus mode */
184
185/* CFIFO/DxFIFO Port Select Register */
186#define RCNT 0x8000 /* b15: Read count mode */
187#define REW 0x4000 /* b14: Buffer rewind */
188#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
189#define DREQE 0x1000 /* b12: DREQ output enable */
190#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
191#define MBW_8 0x0000 /* 8bit */
192#define MBW_16 0x0400 /* 16bit */
193#define BIGEND 0x0100 /* b8: Big endian mode */
194#define BYTE_LITTLE 0x0000 /* little dendian */
195#define BYTE_BIG 0x0100 /* big endifan */
196#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
197#define CURPIPE 0x000F /* b2-0: PIPE select */
198
199/* CFIFO/DxFIFO Port Control Register */
200#define BVAL 0x8000 /* b15: Buffer valid flag */
201#define BCLR 0x4000 /* b14: Buffer clear */
202#define FRDY 0x2000 /* b13: FIFO ready */
203#define DTLN 0x0FFF /* b11-0: FIFO received data length */
204
205/* Interrupt Enable Register 0 */
206#define VBSE 0x8000 /* b15: VBUS interrupt */
207#define RSME 0x4000 /* b14: Resume interrupt */
208#define SOFE 0x2000 /* b13: Frame update interrupt */
209#define DVSE 0x1000 /* b12: Device state transition interrupt */
210#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
211#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
212#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
213#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
214
215/* Interrupt Enable Register 1 */
216#define OVRCRE 0x8000 /* b15: Over-current interrupt */
217#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
218#define DTCHE 0x1000 /* b12: Detach sense interrupt */
219#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
220#define EOFERRE 0x0040 /* b6: EOF error interrupt */
221#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
222#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
223
224/* BRDY Interrupt Enable/Status Register */
225#define BRDY9 0x0200 /* b9: PIPE9 */
226#define BRDY8 0x0100 /* b8: PIPE8 */
227#define BRDY7 0x0080 /* b7: PIPE7 */
228#define BRDY6 0x0040 /* b6: PIPE6 */
229#define BRDY5 0x0020 /* b5: PIPE5 */
230#define BRDY4 0x0010 /* b4: PIPE4 */
231#define BRDY3 0x0008 /* b3: PIPE3 */
232#define BRDY2 0x0004 /* b2: PIPE2 */
233#define BRDY1 0x0002 /* b1: PIPE1 */
234#define BRDY0 0x0001 /* b1: PIPE0 */
235
236/* NRDY Interrupt Enable/Status Register */
237#define NRDY9 0x0200 /* b9: PIPE9 */
238#define NRDY8 0x0100 /* b8: PIPE8 */
239#define NRDY7 0x0080 /* b7: PIPE7 */
240#define NRDY6 0x0040 /* b6: PIPE6 */
241#define NRDY5 0x0020 /* b5: PIPE5 */
242#define NRDY4 0x0010 /* b4: PIPE4 */
243#define NRDY3 0x0008 /* b3: PIPE3 */
244#define NRDY2 0x0004 /* b2: PIPE2 */
245#define NRDY1 0x0002 /* b1: PIPE1 */
246#define NRDY0 0x0001 /* b1: PIPE0 */
247
248/* BEMP Interrupt Enable/Status Register */
249#define BEMP9 0x0200 /* b9: PIPE9 */
250#define BEMP8 0x0100 /* b8: PIPE8 */
251#define BEMP7 0x0080 /* b7: PIPE7 */
252#define BEMP6 0x0040 /* b6: PIPE6 */
253#define BEMP5 0x0020 /* b5: PIPE5 */
254#define BEMP4 0x0010 /* b4: PIPE4 */
255#define BEMP3 0x0008 /* b3: PIPE3 */
256#define BEMP2 0x0004 /* b2: PIPE2 */
257#define BEMP1 0x0002 /* b1: PIPE1 */
258#define BEMP0 0x0001 /* b0: PIPE0 */
259
260/* SOF Pin Configuration Register */
261#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
262#define BRDYM 0x0040 /* b6: BRDY clear timing */
263#define INTL 0x0020 /* b5: Interrupt sense select */
264#define EDGESTS 0x0010 /* b4: */
265#define SOFMODE 0x000C /* b3-2: SOF pin select */
266#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
267#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
268#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
269
270/* Interrupt Status Register 0 */
271#define VBINT 0x8000 /* b15: VBUS interrupt */
272#define RESM 0x4000 /* b14: Resume interrupt */
273#define SOFR 0x2000 /* b13: SOF frame update interrupt */
274#define DVST 0x1000 /* b12: Device state transition interrupt */
275#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
276#define BEMP 0x0400 /* b10: Buffer empty interrupt */
277#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
278#define BRDY 0x0100 /* b8: Buffer ready interrupt */
279#define VBSTS 0x0080 /* b7: VBUS input port */
280#define DVSQ 0x0070 /* b6-4: Device state */
281#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
282#define DS_SPD_ADDR 0x0060 /* Suspend Address */
283#define DS_SPD_DFLT 0x0050 /* Suspend Default */
284#define DS_SPD_POWR 0x0040 /* Suspend Powered */
285#define DS_SUSP 0x0040 /* Suspend */
286#define DS_CNFG 0x0030 /* Configured */
287#define DS_ADDS 0x0020 /* Address */
288#define DS_DFLT 0x0010 /* Default */
289#define DS_POWR 0x0000 /* Powered */
290#define DVSQS 0x0030 /* b5-4: Device state */
291#define VALID 0x0008 /* b3: Setup packet detected flag */
292#define CTSQ 0x0007 /* b2-0: Control transfer stage */
293#define CS_SQER 0x0006 /* Sequence error */
294#define CS_WRND 0x0005 /* Control write nodata status stage */
295#define CS_WRSS 0x0004 /* Control write status stage */
296#define CS_WRDS 0x0003 /* Control write data stage */
297#define CS_RDSS 0x0002 /* Control read status stage */
298#define CS_RDDS 0x0001 /* Control read data stage */
299#define CS_IDST 0x0000 /* Idle or setup stage */
300
301/* Interrupt Status Register 1 */
302#define OVRCR 0x8000 /* b15: Over-current interrupt */
303#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
304#define DTCH 0x1000 /* b12: Detach sense interrupt */
305#define ATTCH 0x0800 /* b11: Attach sense interrupt */
306#define EOFERR 0x0040 /* b6: EOF-error interrupt */
307#define SIGN 0x0020 /* b5: Setup ignore interrupt */
308#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
309
310/* Frame Number Register */
311#define OVRN 0x8000 /* b15: Overrun error */
312#define CRCE 0x4000 /* b14: Received data error */
313#define FRNM 0x07FF /* b10-0: Frame number */
314
315/* Micro Frame Number Register */
316#define UFRNM 0x0007 /* b2-0: Micro frame number */
317
318/* USB Address / Low Power Status Recovery Register */
319//#define USBADDR 0x007F /* b6-0: USB address */
320
321/* Default Control Pipe Maxpacket Size Register */
322/* Pipe Maxpacket Size Register */
323#define DEVSEL 0xF000 /* b15-14: Device address select */
324#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
325
326/* Default Control Pipe Control Register */
327#define BSTS 0x8000 /* b15: Buffer status */
328#define SUREQ 0x4000 /* b14: Send USB request */
329#define CSCLR 0x2000 /* b13: complete-split status clear */
330#define CSSTS 0x1000 /* b12: complete-split status */
331#define SUREQCLR 0x0800 /* b11: stop setup request */
332#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
333#define SQSET 0x0080 /* b7: Sequence toggle bit set */
334#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
335#define PBUSY 0x0020 /* b5: pipe busy */
336#define PINGE 0x0010 /* b4: ping enable */
337#define CCPL 0x0004 /* b2: Enable control transfer complete */
338#define PID 0x0003 /* b1-0: Response PID */
339#define PID_STALL11 0x0003 /* STALL */
340#define PID_STALL 0x0002 /* STALL */
341#define PID_BUF 0x0001 /* BUF */
342#define PID_NAK 0x0000 /* NAK */
343
344/* Pipe Window Select Register */
345#define PIPENM 0x0007 /* b2-0: Pipe select */
346
347/* Pipe Configuration Register */
348#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
349#define R8A66597_ISO 0xC000 /* Isochronous */
350#define R8A66597_INT 0x8000 /* Interrupt */
351#define R8A66597_BULK 0x4000 /* Bulk */
352#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
353#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
354#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
355#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
356#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
357#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
358
359/* Pipe Buffer Configuration Register */
360#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
361#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
362#define PIPE0BUF 256
363#define PIPExBUF 64
364
365/* Pipe Maxpacket Size Register */
366#define MXPS 0x07FF /* b10-0: Maxpacket size */
367
368/* Pipe Cycle Configuration Register */
369#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
370#define IITV 0x0007 /* b2-0: Isochronous interval */
371
372/* Pipex Control Register */
373#define BSTS 0x8000 /* b15: Buffer status */
374#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
375#define CSCLR 0x2000 /* b13: complete-split status clear */
376#define CSSTS 0x1000 /* b12: complete-split status */
377#define ATREPM 0x0400 /* b10: Auto repeat mode */
378#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
379#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
380#define SQSET 0x0080 /* b7: Sequence toggle bit set */
381#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
382#define PBUSY 0x0020 /* b5: pipe busy */
383#define PID 0x0003 /* b1-0: Response PID */
384
385/* PIPExTRE */
386#define TRENB 0x0200 /* b9: Transaction counter enable */
387#define TRCLR 0x0100 /* b8: Transaction counter clear */
388
389/* PIPExTRN */
390#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
391
392/* DEVADDx */
393#define UPPHUB 0x7800
394#define HUBPORT 0x0700
395#define USBSPD 0x00C0
396#define RTPORT 0x0001
397
398#define R8A66597_MAX_NUM_PIPE 10
399#define R8A66597_BUF_BSIZE 8
400#define R8A66597_MAX_DEVICE 10
401#define R8A66597_MAX_ROOT_HUB 2
402#define R8A66597_MAX_SAMPLING 10
403#define R8A66597_MAX_DMA_CHANNEL 2
404#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
405#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
406#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
407#define make_devsel(addr) (addr << 12)
408
409struct r8a66597_pipe_info {
410 u16 pipenum;
411 u16 address; /* R8A66597 HCD usb addres */
412 u16 epnum;
413 u16 maxpacket;
414 u16 type;
415 u16 bufnum;
416 u16 buf_bsize;
417 u16 interval;
418 u16 dir_in;
419};
420
421struct r8a66597_pipe {
422 struct r8a66597_pipe_info info;
423
424 unsigned long fifoaddr;
425 unsigned long fifosel;
426 unsigned long fifoctr;
427 unsigned long pipectr;
428 unsigned long pipetre;
429 unsigned long pipetrn;
430};
431
432struct r8a66597_td {
433 struct r8a66597_pipe *pipe;
434 struct urb *urb;
435 struct list_head queue;
436
437 u16 type;
438 u16 pipenum;
439 int iso_cnt;
440
441 u16 address; /* R8A66597's USB address */
442 u16 maxpacket;
443
444 unsigned zero_packet:1;
445 unsigned short_packet:1;
446 unsigned set_address:1;
447};
448
449struct r8a66597_device {
450 u16 address; /* R8A66597's USB address */
451 u16 hub_port;
452 u16 root_port;
453
454 unsigned short ep_in_toggle;
455 unsigned short ep_out_toggle;
456 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
457 unsigned char dma_map;
458
459 enum usb_device_state state;
460
461 struct usb_device *udev;
462 int usb_address;
463 struct list_head device_list;
464};
465
466struct r8a66597_root_hub {
467 u32 port;
468 u16 old_syssts;
469 int scount;
470
471 struct r8a66597_device *dev;
472};
473
474struct r8a66597 {
475 spinlock_t lock;
476 unsigned long reg;
477
478 struct r8a66597_device device0;
479 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
480 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
481
482 struct timer_list rh_timer;
483 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
484
485 unsigned short address_map;
486 unsigned short timeout_map;
487 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
488 unsigned char dma_map;
489
490 struct list_head child_device;
491 unsigned long child_connect_map[4];
492};
493
494static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
495{
496 return (struct r8a66597 *)(hcd->hcd_priv);
497}
498
499static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
500{
501 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
502}
503
504static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
505 u16 pipenum)
506{
507 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
508 return NULL;
509
510 return list_entry(r8a66597->pipe_queue[pipenum].next,
511 struct r8a66597_td, queue);
512}
513
514static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
515 u16 pipenum)
516{
517 struct r8a66597_td *td;
518
519 td = r8a66597_get_td(r8a66597, pipenum);
520 return (td ? td->urb : NULL);
521}
522
523static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
524{
525 return inw(r8a66597->reg + offset);
526}
527
528static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
529 unsigned long offset, u16 *buf,
530 int len)
531{
532 len = (len + 1) / 2;
533 insw(r8a66597->reg + offset, buf, len);
534}
535
536static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
537 unsigned long offset)
538{
539 outw(val, r8a66597->reg + offset);
540}
541
542static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
543 unsigned long offset, u16 *buf,
544 int len)
545{
546 unsigned long fifoaddr = r8a66597->reg + offset;
547 int odd = len & 0x0001;
548
549 len = len / 2;
550 outsw(fifoaddr, buf, len);
551 if (unlikely(odd)) {
552 buf = &buf[len];
553 outb((unsigned char)*buf, fifoaddr);
554 }
555}
556
557static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
558 u16 val, u16 pat, unsigned long offset)
559{
560 u16 tmp;
561 tmp = r8a66597_read(r8a66597, offset);
562 tmp = tmp & (~pat);
563 tmp = tmp | val;
564 r8a66597_write(r8a66597, tmp, offset);
565}
566
567#define r8a66597_bclr(r8a66597, val, offset) \
568 r8a66597_mdfy(r8a66597, 0, val, offset)
569#define r8a66597_bset(r8a66597, val, offset) \
570 r8a66597_mdfy(r8a66597, val, 0, offset)
571
572static inline unsigned long get_syscfg_reg(int port)
573{
574 return port == 0 ? SYSCFG0 : SYSCFG1;
575}
576
577static inline unsigned long get_syssts_reg(int port)
578{
579 return port == 0 ? SYSSTS0 : SYSSTS1;
580}
581
582static inline unsigned long get_dvstctr_reg(int port)
583{
584 return port == 0 ? DVSTCTR0 : DVSTCTR1;
585}
586
587static inline unsigned long get_intenb_reg(int port)
588{
589 return port == 0 ? INTENB1 : INTENB2;
590}
591
592static inline unsigned long get_intsts_reg(int port)
593{
594 return port == 0 ? INTSTS1 : INTSTS2;
595}
596
597static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
598{
599 unsigned long dvstctr_reg = get_dvstctr_reg(port);
600
601 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
602}
603
604static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
605 int power)
606{
607 unsigned long dvstctr_reg = get_dvstctr_reg(port);
608
609 if (power)
610 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
611 else
612 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
613}
614
615#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
616#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
617#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
618#define get_devadd_addr(address) (DEVADD0 + address * 2)
619
620#define enable_irq_ready(r8a66597, pipenum) \
621 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
622#define disable_irq_ready(r8a66597, pipenum) \
623 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
624#define enable_irq_empty(r8a66597, pipenum) \
625 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
626#define disable_irq_empty(r8a66597, pipenum) \
627 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
628#define enable_irq_nrdy(r8a66597, pipenum) \
629 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
630#define disable_irq_nrdy(r8a66597, pipenum) \
631 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
632
633#endif /* __R8A66597_H__ */
634
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