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authorDavid Howells <dhowells@redhat.com>2006-12-05 09:37:56 -0500
committerDavid Howells <dhowells@warthog.cambridge.redhat.com>2006-12-05 09:37:56 -0500
commit4c1ac1b49122b805adfa4efc620592f68dccf5db (patch)
tree87557f4bc2fd4fe65b7570489c2f610c45c0adcd /drivers
parentc4028958b6ecad064b1a6303a6a5906d4fe48d73 (diff)
parentd916faace3efc0bf19fe9a615a1ab8fa1a24cd93 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/infiniband/core/iwcm.c drivers/net/chelsio/cxgb2.c drivers/net/wireless/bcm43xx/bcm43xx_main.c drivers/net/wireless/prism54/islpci_eth.c drivers/usb/core/hub.h drivers/usb/input/hid-core.c net/core/netpoll.c Fix up merge failures with Linus's head and fix new compilation failures. Signed-Off-By: David Howells <dhowells@redhat.com>
Diffstat (limited to 'drivers')
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-rw-r--r--drivers/net/skge.c8
-rw-r--r--drivers/net/sky2.c41
-rw-r--r--drivers/net/sky2.h11
-rw-r--r--drivers/net/spider_net.c20
-rw-r--r--drivers/net/spider_net.h8
-rw-r--r--drivers/net/sundance.c58
-rw-r--r--drivers/net/sungem.c2
-rw-r--r--drivers/net/sunhme.c2
-rw-r--r--drivers/net/tokenring/olympic.c2
-rw-r--r--drivers/net/tsi108_eth.c1708
-rw-r--r--drivers/net/tsi108_eth.h365
-rw-r--r--drivers/net/tulip/de2104x.c4
-rw-r--r--drivers/net/tulip/dmfe.c9
-rw-r--r--drivers/net/typhoon.c1
-rw-r--r--drivers/net/ucc_geth.c6
-rw-r--r--drivers/net/wan/Kconfig76
-rw-r--r--drivers/net/wireless/atmel.c36
-rw-r--r--drivers/net/wireless/atmel_cs.c74
-rw-r--r--drivers/net/wireless/atmel_pci.c10
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx.h32
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_main.c207
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_power.c28
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_wx.c4
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_xmit.c18
-rw-r--r--drivers/net/wireless/hostap/hostap_pci.c8
-rw-r--r--drivers/net/wireless/ipw2100.c25
-rw-r--r--drivers/net/wireless/ipw2200.c12
-rw-r--r--drivers/net/wireless/orinoco_pci.h7
-rw-r--r--drivers/net/wireless/prism54/isl_38xx.c17
-rw-r--r--drivers/net/wireless/prism54/isl_38xx.h7
-rw-r--r--drivers/net/wireless/prism54/isl_ioctl.c61
-rw-r--r--drivers/net/wireless/prism54/isl_ioctl.h1
-rw-r--r--drivers/net/wireless/prism54/isl_oid.h48
-rw-r--r--drivers/net/wireless/prism54/islpci_dev.c13
-rw-r--r--drivers/net/wireless/prism54/islpci_dev.h11
-rw-r--r--drivers/net/wireless/prism54/islpci_eth.c28
-rw-r--r--drivers/net/wireless/prism54/islpci_eth.h1
-rw-r--r--drivers/net/wireless/prism54/islpci_hotplug.c43
-rw-r--r--drivers/net/wireless/prism54/islpci_mgt.c3
-rw-r--r--drivers/net/wireless/prism54/islpci_mgt.h5
-rw-r--r--drivers/net/wireless/prism54/oid_mgt.c6
-rw-r--r--drivers/net/wireless/prism54/prismcompat.h4
-rw-r--r--drivers/net/wireless/zd1201.c6
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.c38
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.h104
-rw-r--r--drivers/net/wireless/zd1211rw/zd_def.h1
-rw-r--r--drivers/net/wireless/zd1211rw/zd_ieee80211.c10
-rw-r--r--drivers/net/wireless/zd1211rw/zd_ieee80211.h3
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.c404
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.h38
-rw-r--r--drivers/net/wireless/zd1211rw/zd_netdev.c13
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.c45
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.h14
-rw-r--r--drivers/net/zorro8390.c24
-rw-r--r--drivers/parisc/ccio-dma.c2
-rw-r--r--drivers/parisc/iosapic.c6
-rw-r--r--drivers/pci/Kconfig6
-rw-r--r--drivers/pci/access.c75
-rw-r--r--drivers/pci/hotplug/acpiphp.h4
-rw-r--r--drivers/pci/hotplug/acpiphp_core.c39
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c8
-rw-r--r--drivers/pci/hotplug/ibmphp_hpc.c2
-rw-r--r--drivers/pci/hotplug/ibmphp_pci.c4
-rw-r--r--drivers/pci/hotplug/pciehp_core.c7
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c2
-rw-r--r--drivers/pci/hotplug/rpadlpar_core.c2
-rw-r--r--drivers/pci/hotplug/rpaphp_core.c2
-rw-r--r--drivers/pci/hotplug/sgi_hotplug.c35
-rw-r--r--drivers/pci/msi.h8
-rw-r--r--drivers/pci/pci-acpi.c10
-rw-r--r--drivers/pci/pci-driver.c11
-rw-r--r--drivers/pci/pci-sysfs.c33
-rw-r--r--drivers/pci/pci.c123
-rw-r--r--drivers/pci/pci.h1
-rw-r--r--drivers/pci/probe.c27
-rw-r--r--drivers/pci/quirks.c59
-rw-r--r--drivers/pci/rom.c9
-rw-r--r--drivers/pcmcia/ds.c2
-rw-r--r--drivers/rtc/interface.c16
-rw-r--r--drivers/rtc/rtc-at91.c3
-rw-r--r--drivers/rtc/rtc-dev.c25
-rw-r--r--drivers/rtc/rtc-ds1553.c3
-rw-r--r--drivers/rtc/rtc-rs5c372.c6
-rw-r--r--drivers/rtc/rtc-test.c2
-rw-r--r--drivers/s390/net/claw.h2
-rw-r--r--drivers/s390/net/lcs.c2
-rw-r--r--drivers/s390/net/lcs.h4
-rw-r--r--drivers/s390/net/qeth_eddp.c40
-rw-r--r--drivers/s390/net/qeth_eddp.h2
-rw-r--r--drivers/scsi/aic94xx/aic94xx_reg_def.h2
-rw-r--r--drivers/scsi/aic94xx/aic94xx_sds.c4
-rw-r--r--drivers/scsi/ncr53c8xx.c14
-rw-r--r--drivers/scsi/ncr53c8xx.h6
-rw-r--r--drivers/spi/Kconfig2
-rw-r--r--drivers/usb/atm/speedtch.c4
-rw-r--r--drivers/usb/atm/ueagle-atm.c10
-rw-r--r--drivers/usb/class/cdc-acm.c2
-rw-r--r--drivers/usb/core/Kconfig15
-rw-r--r--drivers/usb/core/devices.c9
-rw-r--r--drivers/usb/core/devio.c4
-rw-r--r--drivers/usb/core/driver.c304
-rw-r--r--drivers/usb/core/endpoint.c98
-rw-r--r--drivers/usb/core/hcd.c4
-rw-r--r--drivers/usb/core/hub.c234
-rw-r--r--drivers/usb/core/hub.h41
-rw-r--r--drivers/usb/core/message.c8
-rw-r--r--drivers/usb/core/usb.c160
-rw-r--r--drivers/usb/core/usb.h9
-rw-r--r--drivers/usb/gadget/ether.c4
-rw-r--r--drivers/usb/gadget/lh7a40x_udc.c1
-rw-r--r--drivers/usb/gadget/net2280.c8
-rw-r--r--drivers/usb/gadget/net2280.h3
-rw-r--r--drivers/usb/gadget/pxa2xx_udc.c2
-rw-r--r--drivers/usb/host/Kconfig2
-rw-r--r--drivers/usb/host/ehci-hcd.c16
-rw-r--r--drivers/usb/host/ehci-hub.c104
-rw-r--r--drivers/usb/host/ehci-pci.c40
-rw-r--r--drivers/usb/host/ehci.h1
-rw-r--r--drivers/usb/host/ohci-hcd.c10
-rw-r--r--drivers/usb/host/ohci-hub.c172
-rw-r--r--drivers/usb/host/u132-hcd.c14
-rw-r--r--drivers/usb/image/microtek.c8
-rw-r--r--drivers/usb/input/Kconfig6
-rw-r--r--drivers/usb/input/ati_remote.c17
-rw-r--r--drivers/usb/input/ati_remote2.c3
-rw-r--r--drivers/usb/input/hid-core.c91
-rw-r--r--drivers/usb/input/hid.h1
-rw-r--r--drivers/usb/input/usbkbd.c10
-rw-r--r--drivers/usb/input/usbmouse.c4
-rw-r--r--drivers/usb/input/usbtouchscreen.c96
-rw-r--r--drivers/usb/input/wacom.h1
-rw-r--r--drivers/usb/input/wacom_sys.c2
-rw-r--r--drivers/usb/input/yealink.c6
-rw-r--r--drivers/usb/misc/Makefile1
-rw-r--r--drivers/usb/misc/appledisplay.c5
-rw-r--r--drivers/usb/misc/auerswald.c7
-rw-r--r--drivers/usb/misc/emi26.c3
-rw-r--r--drivers/usb/misc/emi62.c3
-rw-r--r--drivers/usb/misc/ftdi-elan.c20
-rw-r--r--drivers/usb/misc/idmouse.c22
-rw-r--r--drivers/usb/misc/legousbtower.c31
-rw-r--r--drivers/usb/misc/phidgetkit.c5
-rw-r--r--drivers/usb/misc/phidgetmotorcontrol.c5
-rw-r--r--drivers/usb/misc/usb_u132.h6
-rw-r--r--drivers/usb/misc/usbtest.c4
-rw-r--r--drivers/usb/net/asix.c6
-rw-r--r--drivers/usb/net/catc.c12
-rw-r--r--drivers/usb/net/cdc_ether.c3
-rw-r--r--drivers/usb/net/net1080.c4
-rw-r--r--drivers/usb/net/pegasus.c1
-rw-r--r--drivers/usb/net/usbnet.c4
-rw-r--r--drivers/usb/serial/Kconfig11
-rw-r--r--drivers/usb/serial/Makefile1
-rw-r--r--drivers/usb/serial/aircable.c9
-rw-r--r--drivers/usb/serial/airprime.c1
-rw-r--r--drivers/usb/serial/ark3116.c3
-rw-r--r--drivers/usb/serial/console.c6
-rw-r--r--drivers/usb/serial/cypress_m8.c9
-rw-r--r--drivers/usb/serial/digi_acceleport.c2
-rw-r--r--drivers/usb/serial/ezusb.c3
-rw-r--r--drivers/usb/serial/ftdi_sio.c3
-rw-r--r--drivers/usb/serial/garmin_gps.c3
-rw-r--r--drivers/usb/serial/io_edgeport.c4
-rw-r--r--drivers/usb/serial/ipw.c3
-rw-r--r--drivers/usb/serial/keyspan.c18
-rw-r--r--drivers/usb/serial/kobil_sct.c9
-rw-r--r--drivers/usb/serial/mct_u232.c6
-rw-r--r--drivers/usb/serial/mos7840.c3
-rw-r--r--drivers/usb/serial/navman.c3
-rw-r--r--drivers/usb/serial/ti_usb_3410_5052.c5
-rw-r--r--drivers/usb/serial/ti_usb_3410_5052.h1
-rw-r--r--drivers/usb/serial/usb-serial.c12
-rw-r--r--drivers/usb/serial/usb_debug.c65
-rw-r--r--drivers/usb/serial/visor.c3
-rw-r--r--drivers/usb/storage/onetouch.c5
-rw-r--r--drivers/usb/storage/unusual_devs.h10
-rw-r--r--drivers/usb/storage/usb.c8
-rw-r--r--drivers/video/fbmem.c16
-rw-r--r--drivers/video/fbsysfs.c163
500 files changed, 36894 insertions, 25427 deletions
diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c
index 10f160dc75b1..a2f46d587d55 100644
--- a/drivers/acpi/glue.c
+++ b/drivers/acpi/glue.c
@@ -267,9 +267,9 @@ static int acpi_bind_one(struct device *dev, acpi_handle handle)
267{ 267{
268 acpi_status status; 268 acpi_status status;
269 269
270 if (dev->firmware_data) { 270 if (dev->archdata.acpi_handle) {
271 printk(KERN_WARNING PREFIX 271 printk(KERN_WARNING PREFIX
272 "Drivers changed 'firmware_data' for %s\n", dev->bus_id); 272 "Drivers changed 'acpi_handle' for %s\n", dev->bus_id);
273 return -EINVAL; 273 return -EINVAL;
274 } 274 }
275 get_device(dev); 275 get_device(dev);
@@ -278,25 +278,26 @@ static int acpi_bind_one(struct device *dev, acpi_handle handle)
278 put_device(dev); 278 put_device(dev);
279 return -EINVAL; 279 return -EINVAL;
280 } 280 }
281 dev->firmware_data = handle; 281 dev->archdata.acpi_handle = handle;
282 282
283 return 0; 283 return 0;
284} 284}
285 285
286static int acpi_unbind_one(struct device *dev) 286static int acpi_unbind_one(struct device *dev)
287{ 287{
288 if (!dev->firmware_data) 288 if (!dev->archdata.acpi_handle)
289 return 0; 289 return 0;
290 if (dev == acpi_get_physical_device(dev->firmware_data)) { 290 if (dev == acpi_get_physical_device(dev->archdata.acpi_handle)) {
291 /* acpi_get_physical_device increase refcnt by one */ 291 /* acpi_get_physical_device increase refcnt by one */
292 put_device(dev); 292 put_device(dev);
293 acpi_detach_data(dev->firmware_data, acpi_glue_data_handler); 293 acpi_detach_data(dev->archdata.acpi_handle,
294 dev->firmware_data = NULL; 294 acpi_glue_data_handler);
295 dev->archdata.acpi_handle = NULL;
295 /* acpi_bind_one increase refcnt by one */ 296 /* acpi_bind_one increase refcnt by one */
296 put_device(dev); 297 put_device(dev);
297 } else { 298 } else {
298 printk(KERN_ERR PREFIX 299 printk(KERN_ERR PREFIX
299 "Oops, 'firmware_data' corrupt for %s\n", dev->bus_id); 300 "Oops, 'acpi_handle' corrupt for %s\n", dev->bus_id);
300 } 301 }
301 return 0; 302 return 0;
302} 303}
@@ -328,7 +329,8 @@ static int acpi_platform_notify(struct device *dev)
328 if (!ret) { 329 if (!ret) {
329 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 330 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
330 331
331 acpi_get_name(dev->firmware_data, ACPI_FULL_PATHNAME, &buffer); 332 acpi_get_name(dev->archdata.acpi_handle,
333 ACPI_FULL_PATHNAME, &buffer);
332 DBG("Device %s -> %s\n", dev->bus_id, (char *)buffer.pointer); 334 DBG("Device %s -> %s\n", dev->bus_id, (char *)buffer.pointer);
333 kfree(buffer.pointer); 335 kfree(buffer.pointer);
334 } else 336 } else
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
index 7ba5e49ab302..6fd174a37149 100644
--- a/drivers/acpi/processor_perflib.c
+++ b/drivers/acpi/processor_perflib.c
@@ -83,10 +83,8 @@ static int acpi_processor_ppc_notifier(struct notifier_block *nb,
83 goto out; 83 goto out;
84 84
85 ppc = (unsigned int)pr->performance_platform_limit; 85 ppc = (unsigned int)pr->performance_platform_limit;
86 if (!ppc)
87 goto out;
88 86
89 if (ppc > pr->performance->state_count) 87 if (ppc >= pr->performance->state_count)
90 goto out; 88 goto out;
91 89
92 cpufreq_verify_within_limits(policy, 0, 90 cpufreq_verify_within_limits(policy, 0,
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 234197e57e9e..bddb14e91d3c 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -78,6 +78,7 @@ enum {
78 78
79 board_ahci = 0, 79 board_ahci = 0,
80 board_ahci_vt8251 = 1, 80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
81 82
82 /* global controller registers */ 83 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */ 84 HOST_CAP = 0x00, /* host capabilities */
@@ -168,6 +169,7 @@ enum {
168 /* ap->flags bits */ 169 /* ap->flags bits */
169 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24), 170 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
170 AHCI_FLAG_NO_NCQ = (1 << 25), 171 AHCI_FLAG_NO_NCQ = (1 << 25),
172 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 26), /* ignore IRQ_IF_ERR */
171}; 173};
172 174
173struct ahci_cmd_hdr { 175struct ahci_cmd_hdr {
@@ -295,6 +297,17 @@ static const struct ata_port_info ahci_port_info[] = {
295 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 297 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
296 .port_ops = &ahci_ops, 298 .port_ops = &ahci_ops,
297 }, 299 },
300 /* board_ahci_ign_iferr */
301 {
302 .sht = &ahci_sht,
303 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
304 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
305 ATA_FLAG_SKIP_D2H_BSY |
306 AHCI_FLAG_IGN_IRQ_IF_ERR,
307 .pio_mask = 0x1f, /* pio0-4 */
308 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
309 .port_ops = &ahci_ops,
310 },
298}; 311};
299 312
300static const struct pci_device_id ahci_pci_tbl[] = { 313static const struct pci_device_id ahci_pci_tbl[] = {
@@ -314,13 +327,24 @@ static const struct pci_device_id ahci_pci_tbl[] = {
314 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 327 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
315 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 328 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
316 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 329 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
330 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
331 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
332 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
333 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
334 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
335 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
336 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
337 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
338 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
339 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
340 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
317 341
318 /* JMicron */ 342 /* JMicron */
319 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci }, /* JMicron JMB360 */ 343 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
320 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci }, /* JMicron JMB361 */ 344 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
321 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci }, /* JMicron JMB363 */ 345 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
322 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci }, /* JMicron JMB365 */ 346 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
323 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci }, /* JMicron JMB366 */ 347 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
324 348
325 /* ATI */ 349 /* ATI */
326 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */ 350 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
@@ -969,6 +993,10 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
969 /* analyze @irq_stat */ 993 /* analyze @irq_stat */
970 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 994 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
971 995
996 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
997 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
998 irq_stat &= ~PORT_IRQ_IF_ERR;
999
972 if (irq_stat & PORT_IRQ_TF_ERR) 1000 if (irq_stat & PORT_IRQ_TF_ERR)
973 err_mask |= AC_ERR_DEV; 1001 err_mask |= AC_ERR_DEV;
974 1002
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c
index 377425e71391..4a80ff9312b8 100644
--- a/drivers/ata/ata_generic.c
+++ b/drivers/ata/ata_generic.c
@@ -116,6 +116,7 @@ static struct scsi_host_template generic_sht = {
116 .proc_name = DRV_NAME, 116 .proc_name = DRV_NAME,
117 .dma_boundary = ATA_DMA_BOUNDARY, 117 .dma_boundary = ATA_DMA_BOUNDARY,
118 .slave_configure = ata_scsi_slave_config, 118 .slave_configure = ata_scsi_slave_config,
119 .slave_destroy = ata_scsi_slave_destroy,
119 .bios_param = ata_std_bios_param, 120 .bios_param = ata_std_bios_param,
120}; 121};
121 122
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index c872b324dbd3..4c32d93d44b1 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -1451,6 +1451,7 @@ nothing_to_do:
1451 1451
1452static void ata_scsi_qc_complete(struct ata_queued_cmd *qc) 1452static void ata_scsi_qc_complete(struct ata_queued_cmd *qc)
1453{ 1453{
1454 struct ata_port *ap = qc->ap;
1454 struct scsi_cmnd *cmd = qc->scsicmd; 1455 struct scsi_cmnd *cmd = qc->scsicmd;
1455 u8 *cdb = cmd->cmnd; 1456 u8 *cdb = cmd->cmnd;
1456 int need_sense = (qc->err_mask != 0); 1457 int need_sense = (qc->err_mask != 0);
@@ -1459,11 +1460,12 @@ static void ata_scsi_qc_complete(struct ata_queued_cmd *qc)
1459 * schedule EH_REVALIDATE operation to update the IDENTIFY DEVICE 1460 * schedule EH_REVALIDATE operation to update the IDENTIFY DEVICE
1460 * cache 1461 * cache
1461 */ 1462 */
1462 if (!need_sense && (qc->tf.command == ATA_CMD_SET_FEATURES) && 1463 if (ap->ops->error_handler &&
1464 !need_sense && (qc->tf.command == ATA_CMD_SET_FEATURES) &&
1463 ((qc->tf.feature == SETFEATURES_WC_ON) || 1465 ((qc->tf.feature == SETFEATURES_WC_ON) ||
1464 (qc->tf.feature == SETFEATURES_WC_OFF))) { 1466 (qc->tf.feature == SETFEATURES_WC_OFF))) {
1465 qc->ap->eh_info.action |= ATA_EH_REVALIDATE; 1467 ap->eh_info.action |= ATA_EH_REVALIDATE;
1466 ata_port_schedule_eh(qc->ap); 1468 ata_port_schedule_eh(ap);
1467 } 1469 }
1468 1470
1469 /* For ATA pass thru (SAT) commands, generate a sense block if 1471 /* For ATA pass thru (SAT) commands, generate a sense block if
@@ -1490,8 +1492,8 @@ static void ata_scsi_qc_complete(struct ata_queued_cmd *qc)
1490 } 1492 }
1491 } 1493 }
1492 1494
1493 if (need_sense && !qc->ap->ops->error_handler) 1495 if (need_sense && !ap->ops->error_handler)
1494 ata_dump_status(qc->ap->id, &qc->result_tf); 1496 ata_dump_status(ap->id, &qc->result_tf);
1495 1497
1496 qc->scsidone(cmd); 1498 qc->scsidone(cmd);
1497 1499
@@ -3347,20 +3349,23 @@ EXPORT_SYMBOL_GPL(ata_sas_slave_configure);
3347 * @ap: ATA port to which the command is being sent 3349 * @ap: ATA port to which the command is being sent
3348 * 3350 *
3349 * RETURNS: 3351 * RETURNS:
3350 * Zero. 3352 * Return value from __ata_scsi_queuecmd() if @cmd can be queued,
3353 * 0 otherwise.
3351 */ 3354 */
3352 3355
3353int ata_sas_queuecmd(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *), 3356int ata_sas_queuecmd(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *),
3354 struct ata_port *ap) 3357 struct ata_port *ap)
3355{ 3358{
3359 int rc = 0;
3360
3356 ata_scsi_dump_cdb(ap, cmd); 3361 ata_scsi_dump_cdb(ap, cmd);
3357 3362
3358 if (likely(ata_scsi_dev_enabled(ap->device))) 3363 if (likely(ata_scsi_dev_enabled(ap->device)))
3359 __ata_scsi_queuecmd(cmd, done, ap->device); 3364 rc = __ata_scsi_queuecmd(cmd, done, ap->device);
3360 else { 3365 else {
3361 cmd->result = (DID_BAD_TARGET << 16); 3366 cmd->result = (DID_BAD_TARGET << 16);
3362 done(cmd); 3367 done(cmd);
3363 } 3368 }
3364 return 0; 3369 return rc;
3365} 3370}
3366EXPORT_SYMBOL_GPL(ata_sas_queuecmd); 3371EXPORT_SYMBOL_GPL(ata_sas_queuecmd);
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index 1d695df5860a..64eed99f6814 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -346,6 +346,7 @@ static struct scsi_host_template ali_sht = {
346 .proc_name = DRV_NAME, 346 .proc_name = DRV_NAME,
347 .dma_boundary = ATA_DMA_BOUNDARY, 347 .dma_boundary = ATA_DMA_BOUNDARY,
348 .slave_configure = ata_scsi_slave_config, 348 .slave_configure = ata_scsi_slave_config,
349 .slave_destroy = ata_scsi_slave_destroy,
349 .bios_param = ata_std_bios_param, 350 .bios_param = ata_std_bios_param,
350}; 351};
351 352
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 5c47a9e0e0ca..8be46a63af74 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -333,6 +333,7 @@ static struct scsi_host_template amd_sht = {
333 .proc_name = DRV_NAME, 333 .proc_name = DRV_NAME,
334 .dma_boundary = ATA_DMA_BOUNDARY, 334 .dma_boundary = ATA_DMA_BOUNDARY,
335 .slave_configure = ata_scsi_slave_config, 335 .slave_configure = ata_scsi_slave_config,
336 .slave_destroy = ata_scsi_slave_destroy,
336 .bios_param = ata_std_bios_param, 337 .bios_param = ata_std_bios_param,
337}; 338};
338 339
diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c
index 96a098020a8f..2cd30761ca1f 100644
--- a/drivers/ata/pata_artop.c
+++ b/drivers/ata/pata_artop.c
@@ -314,6 +314,7 @@ static struct scsi_host_template artop_sht = {
314 .proc_name = DRV_NAME, 314 .proc_name = DRV_NAME,
315 .dma_boundary = ATA_DMA_BOUNDARY, 315 .dma_boundary = ATA_DMA_BOUNDARY,
316 .slave_configure = ata_scsi_slave_config, 316 .slave_configure = ata_scsi_slave_config,
317 .slave_destroy = ata_scsi_slave_destroy,
317 .bios_param = ata_std_bios_param, 318 .bios_param = ata_std_bios_param,
318}; 319};
319 320
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c
index 1ce28d2125f4..4e1d3b59adbb 100644
--- a/drivers/ata/pata_atiixp.c
+++ b/drivers/ata/pata_atiixp.c
@@ -216,6 +216,7 @@ static struct scsi_host_template atiixp_sht = {
216 .proc_name = DRV_NAME, 216 .proc_name = DRV_NAME,
217 .dma_boundary = ATA_DMA_BOUNDARY, 217 .dma_boundary = ATA_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config, 218 .slave_configure = ata_scsi_slave_config,
219 .slave_destroy = ata_scsi_slave_destroy,
219 .bios_param = ata_std_bios_param, 220 .bios_param = ata_std_bios_param,
220}; 221};
221 222
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c
index b9bbd1d454bf..29a60df465da 100644
--- a/drivers/ata/pata_cmd64x.c
+++ b/drivers/ata/pata_cmd64x.c
@@ -275,6 +275,7 @@ static struct scsi_host_template cmd64x_sht = {
275 .proc_name = DRV_NAME, 275 .proc_name = DRV_NAME,
276 .dma_boundary = ATA_DMA_BOUNDARY, 276 .dma_boundary = ATA_DMA_BOUNDARY,
277 .slave_configure = ata_scsi_slave_config, 277 .slave_configure = ata_scsi_slave_config,
278 .slave_destroy = ata_scsi_slave_destroy,
278 .bios_param = ata_std_bios_param, 279 .bios_param = ata_std_bios_param,
279}; 280};
280 281
diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c
index 2cd3c0ff76df..33d2b88f9c79 100644
--- a/drivers/ata/pata_cs5520.c
+++ b/drivers/ata/pata_cs5520.c
@@ -166,6 +166,7 @@ static struct scsi_host_template cs5520_sht = {
166 .proc_name = DRV_NAME, 166 .proc_name = DRV_NAME,
167 .dma_boundary = ATA_DMA_BOUNDARY, 167 .dma_boundary = ATA_DMA_BOUNDARY,
168 .slave_configure = ata_scsi_slave_config, 168 .slave_configure = ata_scsi_slave_config,
169 .slave_destroy = ata_scsi_slave_destroy,
169 .bios_param = ata_std_bios_param, 170 .bios_param = ata_std_bios_param,
170}; 171};
171 172
diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c
index a07cc81ef791..981f49223469 100644
--- a/drivers/ata/pata_cs5530.c
+++ b/drivers/ata/pata_cs5530.c
@@ -180,6 +180,7 @@ static struct scsi_host_template cs5530_sht = {
180 .proc_name = DRV_NAME, 180 .proc_name = DRV_NAME,
181 .dma_boundary = ATA_DMA_BOUNDARY, 181 .dma_boundary = ATA_DMA_BOUNDARY,
182 .slave_configure = ata_scsi_slave_config, 182 .slave_configure = ata_scsi_slave_config,
183 .slave_destroy = ata_scsi_slave_destroy,
183 .bios_param = ata_std_bios_param, 184 .bios_param = ata_std_bios_param,
184}; 185};
185 186
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index f8def3f9c618..8dafa4a49fdc 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -184,6 +184,7 @@ static struct scsi_host_template cs5535_sht = {
184 .proc_name = DRV_NAME, 184 .proc_name = DRV_NAME,
185 .dma_boundary = ATA_DMA_BOUNDARY, 185 .dma_boundary = ATA_DMA_BOUNDARY,
186 .slave_configure = ata_scsi_slave_config, 186 .slave_configure = ata_scsi_slave_config,
187 .slave_destroy = ata_scsi_slave_destroy,
187 .bios_param = ata_std_bios_param, 188 .bios_param = ata_std_bios_param,
188}; 189};
189 190
diff --git a/drivers/ata/pata_cypress.c b/drivers/ata/pata_cypress.c
index 247b43608b14..5a0b811907ee 100644
--- a/drivers/ata/pata_cypress.c
+++ b/drivers/ata/pata_cypress.c
@@ -135,6 +135,7 @@ static struct scsi_host_template cy82c693_sht = {
135 .proc_name = DRV_NAME, 135 .proc_name = DRV_NAME,
136 .dma_boundary = ATA_DMA_BOUNDARY, 136 .dma_boundary = ATA_DMA_BOUNDARY,
137 .slave_configure = ata_scsi_slave_config, 137 .slave_configure = ata_scsi_slave_config,
138 .slave_destroy = ata_scsi_slave_destroy,
138 .bios_param = ata_std_bios_param, 139 .bios_param = ata_std_bios_param,
139}; 140};
140 141
diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c
index ef18c60fe140..755f79279de3 100644
--- a/drivers/ata/pata_efar.c
+++ b/drivers/ata/pata_efar.c
@@ -233,6 +233,7 @@ static struct scsi_host_template efar_sht = {
233 .proc_name = DRV_NAME, 233 .proc_name = DRV_NAME,
234 .dma_boundary = ATA_DMA_BOUNDARY, 234 .dma_boundary = ATA_DMA_BOUNDARY,
235 .slave_configure = ata_scsi_slave_config, 235 .slave_configure = ata_scsi_slave_config,
236 .slave_destroy = ata_scsi_slave_destroy,
236 .bios_param = ata_std_bios_param, 237 .bios_param = ata_std_bios_param,
237}; 238};
238 239
diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
index 6d3e4c0f15fe..c0e150a9586b 100644
--- a/drivers/ata/pata_hpt366.c
+++ b/drivers/ata/pata_hpt366.c
@@ -329,6 +329,7 @@ static struct scsi_host_template hpt36x_sht = {
329 .proc_name = DRV_NAME, 329 .proc_name = DRV_NAME,
330 .dma_boundary = ATA_DMA_BOUNDARY, 330 .dma_boundary = ATA_DMA_BOUNDARY,
331 .slave_configure = ata_scsi_slave_config, 331 .slave_configure = ata_scsi_slave_config,
332 .slave_destroy = ata_scsi_slave_destroy,
332 .bios_param = ata_std_bios_param, 333 .bios_param = ata_std_bios_param,
333}; 334};
334 335
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index fce3fcdc7e79..1eeb16f0fb02 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -775,6 +775,7 @@ static struct scsi_host_template hpt37x_sht = {
775 .proc_name = DRV_NAME, 775 .proc_name = DRV_NAME,
776 .dma_boundary = ATA_DMA_BOUNDARY, 776 .dma_boundary = ATA_DMA_BOUNDARY,
777 .slave_configure = ata_scsi_slave_config, 777 .slave_configure = ata_scsi_slave_config,
778 .slave_destroy = ata_scsi_slave_destroy,
778 .bios_param = ata_std_bios_param, 779 .bios_param = ata_std_bios_param,
779}; 780};
780 781
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index 58cfb2bc8098..47d7664e9eee 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -341,6 +341,7 @@ static struct scsi_host_template hpt3x2n_sht = {
341 .proc_name = DRV_NAME, 341 .proc_name = DRV_NAME,
342 .dma_boundary = ATA_DMA_BOUNDARY, 342 .dma_boundary = ATA_DMA_BOUNDARY,
343 .slave_configure = ata_scsi_slave_config, 343 .slave_configure = ata_scsi_slave_config,
344 .slave_destroy = ata_scsi_slave_destroy,
344 .bios_param = ata_std_bios_param, 345 .bios_param = ata_std_bios_param,
345}; 346};
346 347
diff --git a/drivers/ata/pata_hpt3x3.c b/drivers/ata/pata_hpt3x3.c
index 3334d72e251b..d216cc564b56 100644
--- a/drivers/ata/pata_hpt3x3.c
+++ b/drivers/ata/pata_hpt3x3.c
@@ -118,6 +118,7 @@ static struct scsi_host_template hpt3x3_sht = {
118 .proc_name = DRV_NAME, 118 .proc_name = DRV_NAME,
119 .dma_boundary = ATA_DMA_BOUNDARY, 119 .dma_boundary = ATA_DMA_BOUNDARY,
120 .slave_configure = ata_scsi_slave_config, 120 .slave_configure = ata_scsi_slave_config,
121 .slave_destroy = ata_scsi_slave_destroy,
121 .bios_param = ata_std_bios_param, 122 .bios_param = ata_std_bios_param,
122}; 123};
123 124
diff --git a/drivers/ata/pata_isapnp.c b/drivers/ata/pata_isapnp.c
index 640b8b0954f5..40ca2b82b7fc 100644
--- a/drivers/ata/pata_isapnp.c
+++ b/drivers/ata/pata_isapnp.c
@@ -34,6 +34,7 @@ static struct scsi_host_template isapnp_sht = {
34 .proc_name = DRV_NAME, 34 .proc_name = DRV_NAME,
35 .dma_boundary = ATA_DMA_BOUNDARY, 35 .dma_boundary = ATA_DMA_BOUNDARY,
36 .slave_configure = ata_scsi_slave_config, 36 .slave_configure = ata_scsi_slave_config,
37 .slave_destroy = ata_scsi_slave_destroy,
37 .bios_param = ata_std_bios_param, 38 .bios_param = ata_std_bios_param,
38}; 39};
39 40
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c
index 18ff3e59a89b..7f68f14be6fd 100644
--- a/drivers/ata/pata_it821x.c
+++ b/drivers/ata/pata_it821x.c
@@ -675,6 +675,7 @@ static struct scsi_host_template it821x_sht = {
675 .proc_name = DRV_NAME, 675 .proc_name = DRV_NAME,
676 .dma_boundary = ATA_DMA_BOUNDARY, 676 .dma_boundary = ATA_DMA_BOUNDARY,
677 .slave_configure = ata_scsi_slave_config, 677 .slave_configure = ata_scsi_slave_config,
678 .slave_destroy = ata_scsi_slave_destroy,
678 .bios_param = ata_std_bios_param, 679 .bios_param = ata_std_bios_param,
679}; 680};
680 681
diff --git a/drivers/ata/pata_jmicron.c b/drivers/ata/pata_jmicron.c
index 52a2bdf3c38d..0210b10d49cd 100644
--- a/drivers/ata/pata_jmicron.c
+++ b/drivers/ata/pata_jmicron.c
@@ -136,6 +136,7 @@ static struct scsi_host_template jmicron_sht = {
136 .proc_name = DRV_NAME, 136 .proc_name = DRV_NAME,
137 .dma_boundary = ATA_DMA_BOUNDARY, 137 .dma_boundary = ATA_DMA_BOUNDARY,
138 .slave_configure = ata_scsi_slave_config, 138 .slave_configure = ata_scsi_slave_config,
139 .slave_destroy = ata_scsi_slave_destroy,
139 /* Use standard CHS mapping rules */ 140 /* Use standard CHS mapping rules */
140 .bios_param = ata_std_bios_param, 141 .bios_param = ata_std_bios_param,
141}; 142};
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c
index 10231ef731d1..b39078b2a47b 100644
--- a/drivers/ata/pata_legacy.c
+++ b/drivers/ata/pata_legacy.c
@@ -135,6 +135,7 @@ static struct scsi_host_template legacy_sht = {
135 .proc_name = DRV_NAME, 135 .proc_name = DRV_NAME,
136 .dma_boundary = ATA_DMA_BOUNDARY, 136 .dma_boundary = ATA_DMA_BOUNDARY,
137 .slave_configure = ata_scsi_slave_config, 137 .slave_configure = ata_scsi_slave_config,
138 .slave_destroy = ata_scsi_slave_destroy,
138 .bios_param = ata_std_bios_param, 139 .bios_param = ata_std_bios_param,
139}; 140};
140 141
diff --git a/drivers/ata/pata_mpiix.c b/drivers/ata/pata_mpiix.c
index 9dfe3e9abea3..e00d406bfdf5 100644
--- a/drivers/ata/pata_mpiix.c
+++ b/drivers/ata/pata_mpiix.c
@@ -166,6 +166,7 @@ static struct scsi_host_template mpiix_sht = {
166 .proc_name = DRV_NAME, 166 .proc_name = DRV_NAME,
167 .dma_boundary = ATA_DMA_BOUNDARY, 167 .dma_boundary = ATA_DMA_BOUNDARY,
168 .slave_configure = ata_scsi_slave_config, 168 .slave_configure = ata_scsi_slave_config,
169 .slave_destroy = ata_scsi_slave_destroy,
169 .bios_param = ata_std_bios_param, 170 .bios_param = ata_std_bios_param,
170}; 171};
171 172
diff --git a/drivers/ata/pata_netcell.c b/drivers/ata/pata_netcell.c
index f5672de99c22..1963a4d35873 100644
--- a/drivers/ata/pata_netcell.c
+++ b/drivers/ata/pata_netcell.c
@@ -62,6 +62,7 @@ static struct scsi_host_template netcell_sht = {
62 .proc_name = DRV_NAME, 62 .proc_name = DRV_NAME,
63 .dma_boundary = ATA_DMA_BOUNDARY, 63 .dma_boundary = ATA_DMA_BOUNDARY,
64 .slave_configure = ata_scsi_slave_config, 64 .slave_configure = ata_scsi_slave_config,
65 .slave_destroy = ata_scsi_slave_destroy,
65 /* Use standard CHS mapping rules */ 66 /* Use standard CHS mapping rules */
66 .bios_param = ata_std_bios_param, 67 .bios_param = ata_std_bios_param,
67}; 68};
diff --git a/drivers/ata/pata_ns87410.c b/drivers/ata/pata_ns87410.c
index 2a3dbeed89b4..7ec800f00ec8 100644
--- a/drivers/ata/pata_ns87410.c
+++ b/drivers/ata/pata_ns87410.c
@@ -156,6 +156,7 @@ static struct scsi_host_template ns87410_sht = {
156 .proc_name = DRV_NAME, 156 .proc_name = DRV_NAME,
157 .dma_boundary = ATA_DMA_BOUNDARY, 157 .dma_boundary = ATA_DMA_BOUNDARY,
158 .slave_configure = ata_scsi_slave_config, 158 .slave_configure = ata_scsi_slave_config,
159 .slave_destroy = ata_scsi_slave_destroy,
159 .bios_param = ata_std_bios_param, 160 .bios_param = ata_std_bios_param,
160}; 161};
161 162
diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c
index fc947dfecd73..8837256632e9 100644
--- a/drivers/ata/pata_oldpiix.c
+++ b/drivers/ata/pata_oldpiix.c
@@ -231,6 +231,7 @@ static struct scsi_host_template oldpiix_sht = {
231 .proc_name = DRV_NAME, 231 .proc_name = DRV_NAME,
232 .dma_boundary = ATA_DMA_BOUNDARY, 232 .dma_boundary = ATA_DMA_BOUNDARY,
233 .slave_configure = ata_scsi_slave_config, 233 .slave_configure = ata_scsi_slave_config,
234 .slave_destroy = ata_scsi_slave_destroy,
234 .bios_param = ata_std_bios_param, 235 .bios_param = ata_std_bios_param,
235}; 236};
236 237
diff --git a/drivers/ata/pata_opti.c b/drivers/ata/pata_opti.c
index a7320ba15575..c6319cf50de4 100644
--- a/drivers/ata/pata_opti.c
+++ b/drivers/ata/pata_opti.c
@@ -202,6 +202,7 @@ static struct scsi_host_template opti_sht = {
202 .proc_name = DRV_NAME, 202 .proc_name = DRV_NAME,
203 .dma_boundary = ATA_DMA_BOUNDARY, 203 .dma_boundary = ATA_DMA_BOUNDARY,
204 .slave_configure = ata_scsi_slave_config, 204 .slave_configure = ata_scsi_slave_config,
205 .slave_destroy = ata_scsi_slave_destroy,
205 .bios_param = ata_std_bios_param, 206 .bios_param = ata_std_bios_param,
206}; 207};
207 208
diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c
index c6906b4215de..2f4770cce04e 100644
--- a/drivers/ata/pata_optidma.c
+++ b/drivers/ata/pata_optidma.c
@@ -359,6 +359,7 @@ static struct scsi_host_template optidma_sht = {
359 .proc_name = DRV_NAME, 359 .proc_name = DRV_NAME,
360 .dma_boundary = ATA_DMA_BOUNDARY, 360 .dma_boundary = ATA_DMA_BOUNDARY,
361 .slave_configure = ata_scsi_slave_config, 361 .slave_configure = ata_scsi_slave_config,
362 .slave_destroy = ata_scsi_slave_destroy,
362 .bios_param = ata_std_bios_param, 363 .bios_param = ata_std_bios_param,
363}; 364};
364 365
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index e93ea2702c73..999922de476e 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -69,6 +69,7 @@ static struct scsi_host_template pcmcia_sht = {
69 .proc_name = DRV_NAME, 69 .proc_name = DRV_NAME,
70 .dma_boundary = ATA_DMA_BOUNDARY, 70 .dma_boundary = ATA_DMA_BOUNDARY,
71 .slave_configure = ata_scsi_slave_config, 71 .slave_configure = ata_scsi_slave_config,
72 .slave_destroy = ata_scsi_slave_destroy,
72 .bios_param = ata_std_bios_param, 73 .bios_param = ata_std_bios_param,
73}; 74};
74 75
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index d894d9918b1d..beb6d10a234b 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -141,6 +141,7 @@ static struct scsi_host_template pdc2027x_sht = {
141 .proc_name = DRV_NAME, 141 .proc_name = DRV_NAME,
142 .dma_boundary = ATA_DMA_BOUNDARY, 142 .dma_boundary = ATA_DMA_BOUNDARY,
143 .slave_configure = ata_scsi_slave_config, 143 .slave_configure = ata_scsi_slave_config,
144 .slave_destroy = ata_scsi_slave_destroy,
144 .bios_param = ata_std_bios_param, 145 .bios_param = ata_std_bios_param,
145}; 146};
146 147
diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c
index 5ba9eb20a6c2..6baf51b2fda1 100644
--- a/drivers/ata/pata_pdc202xx_old.c
+++ b/drivers/ata/pata_pdc202xx_old.c
@@ -269,6 +269,7 @@ static struct scsi_host_template pdc_sht = {
269 .proc_name = DRV_NAME, 269 .proc_name = DRV_NAME,
270 .dma_boundary = ATA_DMA_BOUNDARY, 270 .dma_boundary = ATA_DMA_BOUNDARY,
271 .slave_configure = ata_scsi_slave_config, 271 .slave_configure = ata_scsi_slave_config,
272 .slave_destroy = ata_scsi_slave_destroy,
272 .bios_param = ata_std_bios_param, 273 .bios_param = ata_std_bios_param,
273}; 274};
274 275
diff --git a/drivers/ata/pata_qdi.c b/drivers/ata/pata_qdi.c
index 2c3cc0ccc606..314938dea1fc 100644
--- a/drivers/ata/pata_qdi.c
+++ b/drivers/ata/pata_qdi.c
@@ -164,6 +164,7 @@ static struct scsi_host_template qdi_sht = {
164 .proc_name = DRV_NAME, 164 .proc_name = DRV_NAME,
165 .dma_boundary = ATA_DMA_BOUNDARY, 165 .dma_boundary = ATA_DMA_BOUNDARY,
166 .slave_configure = ata_scsi_slave_config, 166 .slave_configure = ata_scsi_slave_config,
167 .slave_destroy = ata_scsi_slave_destroy,
167 .bios_param = ata_std_bios_param, 168 .bios_param = ata_std_bios_param,
168}; 169};
169 170
diff --git a/drivers/ata/pata_radisys.c b/drivers/ata/pata_radisys.c
index 1af83d7694d5..048c2bb21ef1 100644
--- a/drivers/ata/pata_radisys.c
+++ b/drivers/ata/pata_radisys.c
@@ -227,6 +227,7 @@ static struct scsi_host_template radisys_sht = {
227 .proc_name = DRV_NAME, 227 .proc_name = DRV_NAME,
228 .dma_boundary = ATA_DMA_BOUNDARY, 228 .dma_boundary = ATA_DMA_BOUNDARY,
229 .slave_configure = ata_scsi_slave_config, 229 .slave_configure = ata_scsi_slave_config,
230 .slave_destroy = ata_scsi_slave_destroy,
230 .bios_param = ata_std_bios_param, 231 .bios_param = ata_std_bios_param,
231}; 232};
232 233
diff --git a/drivers/ata/pata_rz1000.c b/drivers/ata/pata_rz1000.c
index 4533b6357d99..e4e5ea423fef 100644
--- a/drivers/ata/pata_rz1000.c
+++ b/drivers/ata/pata_rz1000.c
@@ -90,6 +90,7 @@ static struct scsi_host_template rz1000_sht = {
90 .proc_name = DRV_NAME, 90 .proc_name = DRV_NAME,
91 .dma_boundary = ATA_DMA_BOUNDARY, 91 .dma_boundary = ATA_DMA_BOUNDARY,
92 .slave_configure = ata_scsi_slave_config, 92 .slave_configure = ata_scsi_slave_config,
93 .slave_destroy = ata_scsi_slave_destroy,
93 .bios_param = ata_std_bios_param, 94 .bios_param = ata_std_bios_param,
94}; 95};
95 96
diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c
index 067d9d223e35..0c75dae74764 100644
--- a/drivers/ata/pata_sc1200.c
+++ b/drivers/ata/pata_sc1200.c
@@ -193,6 +193,7 @@ static struct scsi_host_template sc1200_sht = {
193 .proc_name = DRV_NAME, 193 .proc_name = DRV_NAME,
194 .dma_boundary = ATA_DMA_BOUNDARY, 194 .dma_boundary = ATA_DMA_BOUNDARY,
195 .slave_configure = ata_scsi_slave_config, 195 .slave_configure = ata_scsi_slave_config,
196 .slave_destroy = ata_scsi_slave_destroy,
196 .bios_param = ata_std_bios_param, 197 .bios_param = ata_std_bios_param,
197}; 198};
198 199
diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c
index 5bbf76ec14a4..be7f60efcb61 100644
--- a/drivers/ata/pata_serverworks.c
+++ b/drivers/ata/pata_serverworks.c
@@ -325,6 +325,7 @@ static struct scsi_host_template serverworks_sht = {
325 .proc_name = DRV_NAME, 325 .proc_name = DRV_NAME,
326 .dma_boundary = ATA_DMA_BOUNDARY, 326 .dma_boundary = ATA_DMA_BOUNDARY,
327 .slave_configure = ata_scsi_slave_config, 327 .slave_configure = ata_scsi_slave_config,
328 .slave_destroy = ata_scsi_slave_destroy,
328 .bios_param = ata_std_bios_param, 329 .bios_param = ata_std_bios_param,
329}; 330};
330 331
diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c
index 4a2b72b4be8a..11942fd03b55 100644
--- a/drivers/ata/pata_sil680.c
+++ b/drivers/ata/pata_sil680.c
@@ -225,6 +225,7 @@ static struct scsi_host_template sil680_sht = {
225 .proc_name = DRV_NAME, 225 .proc_name = DRV_NAME,
226 .dma_boundary = ATA_DMA_BOUNDARY, 226 .dma_boundary = ATA_DMA_BOUNDARY,
227 .slave_configure = ata_scsi_slave_config, 227 .slave_configure = ata_scsi_slave_config,
228 .slave_destroy = ata_scsi_slave_destroy,
228 .bios_param = ata_std_bios_param, 229 .bios_param = ata_std_bios_param,
229}; 230};
230 231
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
index b9ffafb4198c..91e85f90941d 100644
--- a/drivers/ata/pata_sis.c
+++ b/drivers/ata/pata_sis.c
@@ -545,6 +545,7 @@ static struct scsi_host_template sis_sht = {
545 .proc_name = DRV_NAME, 545 .proc_name = DRV_NAME,
546 .dma_boundary = ATA_DMA_BOUNDARY, 546 .dma_boundary = ATA_DMA_BOUNDARY,
547 .slave_configure = ata_scsi_slave_config, 547 .slave_configure = ata_scsi_slave_config,
548 .slave_destroy = ata_scsi_slave_destroy,
548 .bios_param = ata_std_bios_param, 549 .bios_param = ata_std_bios_param,
549}; 550};
550 551
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index 08a6dc88676f..dc1cfc6d805b 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -237,6 +237,7 @@ static struct scsi_host_template sl82c105_sht = {
237 .proc_name = DRV_NAME, 237 .proc_name = DRV_NAME,
238 .dma_boundary = ATA_DMA_BOUNDARY, 238 .dma_boundary = ATA_DMA_BOUNDARY,
239 .slave_configure = ata_scsi_slave_config, 239 .slave_configure = ata_scsi_slave_config,
240 .slave_destroy = ata_scsi_slave_destroy,
240 .bios_param = ata_std_bios_param, 241 .bios_param = ata_std_bios_param,
241}; 242};
242 243
diff --git a/drivers/ata/pata_triflex.c b/drivers/ata/pata_triflex.c
index 9640f80e8b0d..bfda1f7e760a 100644
--- a/drivers/ata/pata_triflex.c
+++ b/drivers/ata/pata_triflex.c
@@ -192,6 +192,7 @@ static struct scsi_host_template triflex_sht = {
192 .proc_name = DRV_NAME, 192 .proc_name = DRV_NAME,
193 .dma_boundary = ATA_DMA_BOUNDARY, 193 .dma_boundary = ATA_DMA_BOUNDARY,
194 .slave_configure = ata_scsi_slave_config, 194 .slave_configure = ata_scsi_slave_config,
195 .slave_destroy = ata_scsi_slave_destroy,
195 .bios_param = ata_std_bios_param, 196 .bios_param = ata_std_bios_param,
196}; 197};
197 198
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 1e7be9eee9c3..c5f1616d224d 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -295,6 +295,7 @@ static struct scsi_host_template via_sht = {
295 .proc_name = DRV_NAME, 295 .proc_name = DRV_NAME,
296 .dma_boundary = ATA_DMA_BOUNDARY, 296 .dma_boundary = ATA_DMA_BOUNDARY,
297 .slave_configure = ata_scsi_slave_config, 297 .slave_configure = ata_scsi_slave_config,
298 .slave_destroy = ata_scsi_slave_destroy,
298 .bios_param = ata_std_bios_param, 299 .bios_param = ata_std_bios_param,
299}; 300};
300 301
diff --git a/drivers/atm/ambassador.c b/drivers/atm/ambassador.c
index 9fffa7af6db1..afa7d750a593 100644
--- a/drivers/atm/ambassador.c
+++ b/drivers/atm/ambassador.c
@@ -972,7 +972,7 @@ static int make_rate (unsigned int rate, rounding r,
972 } 972 }
973 case round_up: { 973 case round_up: {
974 // check all bits that we are discarding 974 // check all bits that we are discarding
975 if (man & (-1>>9)) { 975 if (man & (~0U>>9)) {
976 man = (man>>(32-9)) + 1; 976 man = (man>>(32-9)) + 1;
977 if (man == (1<<9)) { 977 if (man == (1<<9)) {
978 // no need to check for round up outside of range 978 // no need to check for round up outside of range
diff --git a/drivers/atm/firestream.c b/drivers/atm/firestream.c
index 697ad82f6634..9c67df5ccfa4 100644
--- a/drivers/atm/firestream.c
+++ b/drivers/atm/firestream.c
@@ -512,7 +512,7 @@ static unsigned int make_rate (unsigned int rate, int r,
512 } 512 }
513 case ROUND_UP: { 513 case ROUND_UP: {
514 /* check all bits that we are discarding */ 514 /* check all bits that we are discarding */
515 if (man & (-1>>9)) { 515 if (man & (~0U>>9)) {
516 man = (man>>(32-9)) + 1; 516 man = (man>>(32-9)) + 1;
517 if (man == (1<<9)) { 517 if (man == (1<<9)) {
518 /* no need to check for round up outside of range */ 518 /* no need to check for round up outside of range */
diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c
index 9ed1c60048f0..bb7ef570514c 100644
--- a/drivers/atm/iphase.c
+++ b/drivers/atm/iphase.c
@@ -305,7 +305,7 @@ static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) {
305** | R | NZ | 5-bit exponent | 9-bit mantissa | 305** | R | NZ | 5-bit exponent | 9-bit mantissa |
306** +----+----+------------------+-------------------------------+ 306** +----+----+------------------+-------------------------------+
307** 307**
308** R = reserverd (written as 0) 308** R = reserved (written as 0)
309** NZ = 0 if 0 cells/sec; 1 otherwise 309** NZ = 0 if 0 cells/sec; 1 otherwise
310** 310**
311** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec 311** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec
diff --git a/drivers/base/bus.c b/drivers/base/bus.c
index 7d8a7ce73fb3..472810f8e6e7 100644
--- a/drivers/base/bus.c
+++ b/drivers/base/bus.c
@@ -355,6 +355,21 @@ static void device_remove_attrs(struct bus_type * bus, struct device * dev)
355 } 355 }
356} 356}
357 357
358#ifdef CONFIG_SYSFS_DEPRECATED
359static int make_deprecated_bus_links(struct device *dev)
360{
361 return sysfs_create_link(&dev->kobj,
362 &dev->bus->subsys.kset.kobj, "bus");
363}
364
365static void remove_deprecated_bus_links(struct device *dev)
366{
367 sysfs_remove_link(&dev->kobj, "bus");
368}
369#else
370static inline int make_deprecated_bus_links(struct device *dev) { return 0; }
371static inline void remove_deprecated_bus_links(struct device *dev) { }
372#endif
358 373
359/** 374/**
360 * bus_add_device - add device to bus 375 * bus_add_device - add device to bus
@@ -381,8 +396,7 @@ int bus_add_device(struct device * dev)
381 &dev->bus->subsys.kset.kobj, "subsystem"); 396 &dev->bus->subsys.kset.kobj, "subsystem");
382 if (error) 397 if (error)
383 goto out_subsys; 398 goto out_subsys;
384 error = sysfs_create_link(&dev->kobj, 399 error = make_deprecated_bus_links(dev);
385 &dev->bus->subsys.kset.kobj, "bus");
386 if (error) 400 if (error)
387 goto out_deprecated; 401 goto out_deprecated;
388 } 402 }
@@ -436,7 +450,7 @@ void bus_remove_device(struct device * dev)
436{ 450{
437 if (dev->bus) { 451 if (dev->bus) {
438 sysfs_remove_link(&dev->kobj, "subsystem"); 452 sysfs_remove_link(&dev->kobj, "subsystem");
439 sysfs_remove_link(&dev->kobj, "bus"); 453 remove_deprecated_bus_links(dev);
440 sysfs_remove_link(&dev->bus->devices.kobj, dev->bus_id); 454 sysfs_remove_link(&dev->bus->devices.kobj, dev->bus_id);
441 device_remove_attrs(dev->bus, dev); 455 device_remove_attrs(dev->bus, dev);
442 if (dev->is_registered) { 456 if (dev->is_registered) {
@@ -724,6 +738,8 @@ int bus_register(struct bus_type * bus)
724{ 738{
725 int retval; 739 int retval;
726 740
741 BLOCKING_INIT_NOTIFIER_HEAD(&bus->bus_notifier);
742
727 retval = kobject_set_name(&bus->subsys.kset.kobj, "%s", bus->name); 743 retval = kobject_set_name(&bus->subsys.kset.kobj, "%s", bus->name);
728 if (retval) 744 if (retval)
729 goto out; 745 goto out;
@@ -782,6 +798,18 @@ void bus_unregister(struct bus_type * bus)
782 subsystem_unregister(&bus->subsys); 798 subsystem_unregister(&bus->subsys);
783} 799}
784 800
801int bus_register_notifier(struct bus_type *bus, struct notifier_block *nb)
802{
803 return blocking_notifier_chain_register(&bus->bus_notifier, nb);
804}
805EXPORT_SYMBOL_GPL(bus_register_notifier);
806
807int bus_unregister_notifier(struct bus_type *bus, struct notifier_block *nb)
808{
809 return blocking_notifier_chain_unregister(&bus->bus_notifier, nb);
810}
811EXPORT_SYMBOL_GPL(bus_unregister_notifier);
812
785int __init buses_init(void) 813int __init buses_init(void)
786{ 814{
787 return subsystem_register(&bus_subsys); 815 return subsystem_register(&bus_subsys);
diff --git a/drivers/base/class.c b/drivers/base/class.c
index 0ff267a248db..f098881f45b2 100644
--- a/drivers/base/class.c
+++ b/drivers/base/class.c
@@ -352,6 +352,92 @@ static const char *class_uevent_name(struct kset *kset, struct kobject *kobj)
352 return class_dev->class->name; 352 return class_dev->class->name;
353} 353}
354 354
355#ifdef CONFIG_SYSFS_DEPRECATED
356char *make_class_name(const char *name, struct kobject *kobj)
357{
358 char *class_name;
359 int size;
360
361 size = strlen(name) + strlen(kobject_name(kobj)) + 2;
362
363 class_name = kmalloc(size, GFP_KERNEL);
364 if (!class_name)
365 return ERR_PTR(-ENOMEM);
366
367 strcpy(class_name, name);
368 strcat(class_name, ":");
369 strcat(class_name, kobject_name(kobj));
370 return class_name;
371}
372
373static int deprecated_class_uevent(char **envp, int num_envp, int *cur_index,
374 char *buffer, int buffer_size,
375 int *cur_len,
376 struct class_device *class_dev)
377{
378 struct device *dev = class_dev->dev;
379 char *path;
380
381 if (!dev)
382 return 0;
383
384 /* add device, backing this class device (deprecated) */
385 path = kobject_get_path(&dev->kobj, GFP_KERNEL);
386
387 add_uevent_var(envp, num_envp, cur_index, buffer, buffer_size,
388 cur_len, "PHYSDEVPATH=%s", path);
389 kfree(path);
390
391 if (dev->bus)
392 add_uevent_var(envp, num_envp, cur_index,
393 buffer, buffer_size, cur_len,
394 "PHYSDEVBUS=%s", dev->bus->name);
395
396 if (dev->driver)
397 add_uevent_var(envp, num_envp, cur_index,
398 buffer, buffer_size, cur_len,
399 "PHYSDEVDRIVER=%s", dev->driver->name);
400 return 0;
401}
402
403static int make_deprecated_class_device_links(struct class_device *class_dev)
404{
405 char *class_name;
406 int error;
407
408 if (!class_dev->dev)
409 return 0;
410
411 class_name = make_class_name(class_dev->class->name, &class_dev->kobj);
412 error = sysfs_create_link(&class_dev->dev->kobj, &class_dev->kobj,
413 class_name);
414 kfree(class_name);
415 return error;
416}
417
418static void remove_deprecated_class_device_links(struct class_device *class_dev)
419{
420 char *class_name;
421
422 if (!class_dev->dev)
423 return;
424
425 class_name = make_class_name(class_dev->class->name, &class_dev->kobj);
426 sysfs_remove_link(&class_dev->dev->kobj, class_name);
427 kfree(class_name);
428}
429#else
430static inline int deprecated_class_uevent(char **envp, int num_envp,
431 int *cur_index, char *buffer,
432 int buffer_size, int *cur_len,
433 struct class_device *class_dev)
434{ return 0; }
435static inline int make_deprecated_class_device_links(struct class_device *cd)
436{ return 0; }
437static void remove_deprecated_class_device_links(struct class_device *cd)
438{ }
439#endif
440
355static int class_uevent(struct kset *kset, struct kobject *kobj, char **envp, 441static int class_uevent(struct kset *kset, struct kobject *kobj, char **envp,
356 int num_envp, char *buffer, int buffer_size) 442 int num_envp, char *buffer, int buffer_size)
357{ 443{
@@ -362,25 +448,8 @@ static int class_uevent(struct kset *kset, struct kobject *kobj, char **envp,
362 448
363 pr_debug("%s - name = %s\n", __FUNCTION__, class_dev->class_id); 449 pr_debug("%s - name = %s\n", __FUNCTION__, class_dev->class_id);
364 450
365 if (class_dev->dev) { 451 deprecated_class_uevent(envp, num_envp, &i, buffer, buffer_size,
366 /* add device, backing this class device (deprecated) */ 452 &length, class_dev);
367 struct device *dev = class_dev->dev;
368 char *path = kobject_get_path(&dev->kobj, GFP_KERNEL);
369
370 add_uevent_var(envp, num_envp, &i, buffer, buffer_size,
371 &length, "PHYSDEVPATH=%s", path);
372 kfree(path);
373
374 if (dev->bus)
375 add_uevent_var(envp, num_envp, &i,
376 buffer, buffer_size, &length,
377 "PHYSDEVBUS=%s", dev->bus->name);
378
379 if (dev->driver)
380 add_uevent_var(envp, num_envp, &i,
381 buffer, buffer_size, &length,
382 "PHYSDEVDRIVER=%s", dev->driver->name);
383 }
384 453
385 if (MAJOR(class_dev->devt)) { 454 if (MAJOR(class_dev->devt)) {
386 add_uevent_var(envp, num_envp, &i, 455 add_uevent_var(envp, num_envp, &i,
@@ -506,29 +575,11 @@ void class_device_initialize(struct class_device *class_dev)
506 INIT_LIST_HEAD(&class_dev->node); 575 INIT_LIST_HEAD(&class_dev->node);
507} 576}
508 577
509char *make_class_name(const char *name, struct kobject *kobj)
510{
511 char *class_name;
512 int size;
513
514 size = strlen(name) + strlen(kobject_name(kobj)) + 2;
515
516 class_name = kmalloc(size, GFP_KERNEL);
517 if (!class_name)
518 return ERR_PTR(-ENOMEM);
519
520 strcpy(class_name, name);
521 strcat(class_name, ":");
522 strcat(class_name, kobject_name(kobj));
523 return class_name;
524}
525
526int class_device_add(struct class_device *class_dev) 578int class_device_add(struct class_device *class_dev)
527{ 579{
528 struct class *parent_class = NULL; 580 struct class *parent_class = NULL;
529 struct class_device *parent_class_dev = NULL; 581 struct class_device *parent_class_dev = NULL;
530 struct class_interface *class_intf; 582 struct class_interface *class_intf;
531 char *class_name = NULL;
532 int error = -EINVAL; 583 int error = -EINVAL;
533 584
534 class_dev = class_device_get(class_dev); 585 class_dev = class_device_get(class_dev);
@@ -599,20 +650,18 @@ int class_device_add(struct class_device *class_dev)
599 goto out5; 650 goto out5;
600 651
601 if (class_dev->dev) { 652 if (class_dev->dev) {
602 class_name = make_class_name(class_dev->class->name,
603 &class_dev->kobj);
604 error = sysfs_create_link(&class_dev->kobj, 653 error = sysfs_create_link(&class_dev->kobj,
605 &class_dev->dev->kobj, "device"); 654 &class_dev->dev->kobj, "device");
606 if (error) 655 if (error)
607 goto out6; 656 goto out6;
608 error = sysfs_create_link(&class_dev->dev->kobj, &class_dev->kobj,
609 class_name);
610 if (error)
611 goto out7;
612 } 657 }
613 658
614 error = class_device_add_groups(class_dev); 659 error = class_device_add_groups(class_dev);
615 if (error) 660 if (error)
661 goto out7;
662
663 error = make_deprecated_class_device_links(class_dev);
664 if (error)
616 goto out8; 665 goto out8;
617 666
618 kobject_uevent(&class_dev->kobj, KOBJ_ADD); 667 kobject_uevent(&class_dev->kobj, KOBJ_ADD);
@@ -629,8 +678,7 @@ int class_device_add(struct class_device *class_dev)
629 goto out1; 678 goto out1;
630 679
631 out8: 680 out8:
632 if (class_dev->dev) 681 class_device_remove_groups(class_dev);
633 sysfs_remove_link(&class_dev->kobj, class_name);
634 out7: 682 out7:
635 if (class_dev->dev) 683 if (class_dev->dev)
636 sysfs_remove_link(&class_dev->kobj, "device"); 684 sysfs_remove_link(&class_dev->kobj, "device");
@@ -649,7 +697,6 @@ int class_device_add(struct class_device *class_dev)
649 class_put(parent_class); 697 class_put(parent_class);
650 out1: 698 out1:
651 class_device_put(class_dev); 699 class_device_put(class_dev);
652 kfree(class_name);
653 return error; 700 return error;
654} 701}
655 702
@@ -726,7 +773,6 @@ void class_device_del(struct class_device *class_dev)
726 struct class *parent_class = class_dev->class; 773 struct class *parent_class = class_dev->class;
727 struct class_device *parent_device = class_dev->parent; 774 struct class_device *parent_device = class_dev->parent;
728 struct class_interface *class_intf; 775 struct class_interface *class_intf;
729 char *class_name = NULL;
730 776
731 if (parent_class) { 777 if (parent_class) {
732 down(&parent_class->sem); 778 down(&parent_class->sem);
@@ -738,10 +784,8 @@ void class_device_del(struct class_device *class_dev)
738 } 784 }
739 785
740 if (class_dev->dev) { 786 if (class_dev->dev) {
741 class_name = make_class_name(class_dev->class->name, 787 remove_deprecated_class_device_links(class_dev);
742 &class_dev->kobj);
743 sysfs_remove_link(&class_dev->kobj, "device"); 788 sysfs_remove_link(&class_dev->kobj, "device");
744 sysfs_remove_link(&class_dev->dev->kobj, class_name);
745 } 789 }
746 sysfs_remove_link(&class_dev->kobj, "subsystem"); 790 sysfs_remove_link(&class_dev->kobj, "subsystem");
747 class_device_remove_file(class_dev, &class_dev->uevent_attr); 791 class_device_remove_file(class_dev, &class_dev->uevent_attr);
@@ -755,7 +799,6 @@ void class_device_del(struct class_device *class_dev)
755 799
756 class_device_put(parent_device); 800 class_device_put(parent_device);
757 class_put(parent_class); 801 class_put(parent_class);
758 kfree(class_name);
759} 802}
760 803
761void class_device_unregister(struct class_device *class_dev) 804void class_device_unregister(struct class_device *class_dev)
@@ -804,14 +847,17 @@ int class_device_rename(struct class_device *class_dev, char *new_name)
804 pr_debug("CLASS: renaming '%s' to '%s'\n", class_dev->class_id, 847 pr_debug("CLASS: renaming '%s' to '%s'\n", class_dev->class_id,
805 new_name); 848 new_name);
806 849
850#ifdef CONFIG_SYSFS_DEPRECATED
807 if (class_dev->dev) 851 if (class_dev->dev)
808 old_class_name = make_class_name(class_dev->class->name, 852 old_class_name = make_class_name(class_dev->class->name,
809 &class_dev->kobj); 853 &class_dev->kobj);
854#endif
810 855
811 strlcpy(class_dev->class_id, new_name, KOBJ_NAME_LEN); 856 strlcpy(class_dev->class_id, new_name, KOBJ_NAME_LEN);
812 857
813 error = kobject_rename(&class_dev->kobj, new_name); 858 error = kobject_rename(&class_dev->kobj, new_name);
814 859
860#ifdef CONFIG_SYSFS_DEPRECATED
815 if (class_dev->dev) { 861 if (class_dev->dev) {
816 new_class_name = make_class_name(class_dev->class->name, 862 new_class_name = make_class_name(class_dev->class->name,
817 &class_dev->kobj); 863 &class_dev->kobj);
@@ -819,6 +865,7 @@ int class_device_rename(struct class_device *class_dev, char *new_name)
819 new_class_name); 865 new_class_name);
820 sysfs_remove_link(&class_dev->dev->kobj, old_class_name); 866 sysfs_remove_link(&class_dev->dev->kobj, old_class_name);
821 } 867 }
868#endif
822 class_device_put(class_dev); 869 class_device_put(class_dev);
823 870
824 kfree(old_class_name); 871 kfree(old_class_name);
@@ -893,23 +940,6 @@ void class_interface_unregister(struct class_interface *class_intf)
893 class_put(parent); 940 class_put(parent);
894} 941}
895 942
896int virtual_device_parent(struct device *dev)
897{
898 if (!dev->class)
899 return -ENODEV;
900
901 if (!dev->class->virtual_dir) {
902 static struct kobject *virtual_dir = NULL;
903
904 if (!virtual_dir)
905 virtual_dir = kobject_add_dir(&devices_subsys.kset.kobj, "virtual");
906 dev->class->virtual_dir = kobject_add_dir(virtual_dir, dev->class->name);
907 }
908
909 dev->kobj.parent = dev->class->virtual_dir;
910 return 0;
911}
912
913int __init classes_init(void) 943int __init classes_init(void)
914{ 944{
915 int retval; 945 int retval;
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 68ad11af22b4..e4b530ef757d 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -17,6 +17,7 @@
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/string.h> 18#include <linux/string.h>
19#include <linux/kdev_t.h> 19#include <linux/kdev_t.h>
20#include <linux/notifier.h>
20 21
21#include <asm/semaphore.h> 22#include <asm/semaphore.h>
22 23
@@ -153,20 +154,24 @@ static int dev_uevent(struct kset *kset, struct kobject *kobj, char **envp,
153 "MINOR=%u", MINOR(dev->devt)); 154 "MINOR=%u", MINOR(dev->devt));
154 } 155 }
155 156
157#ifdef CONFIG_SYSFS_DEPRECATED
156 /* add bus name (same as SUBSYSTEM, deprecated) */ 158 /* add bus name (same as SUBSYSTEM, deprecated) */
157 if (dev->bus) 159 if (dev->bus)
158 add_uevent_var(envp, num_envp, &i, 160 add_uevent_var(envp, num_envp, &i,
159 buffer, buffer_size, &length, 161 buffer, buffer_size, &length,
160 "PHYSDEVBUS=%s", dev->bus->name); 162 "PHYSDEVBUS=%s", dev->bus->name);
163#endif
161 164
162 /* add driver name (PHYSDEV* values are deprecated)*/ 165 /* add driver name (PHYSDEV* values are deprecated)*/
163 if (dev->driver) { 166 if (dev->driver) {
164 add_uevent_var(envp, num_envp, &i, 167 add_uevent_var(envp, num_envp, &i,
165 buffer, buffer_size, &length, 168 buffer, buffer_size, &length,
166 "DRIVER=%s", dev->driver->name); 169 "DRIVER=%s", dev->driver->name);
170#ifdef CONFIG_SYSFS_DEPRECATED
167 add_uevent_var(envp, num_envp, &i, 171 add_uevent_var(envp, num_envp, &i,
168 buffer, buffer_size, &length, 172 buffer, buffer_size, &length,
169 "PHYSDEVDRIVER=%s", dev->driver->name); 173 "PHYSDEVDRIVER=%s", dev->driver->name);
174#endif
170 } 175 }
171 176
172 /* terminate, set to next free slot, shrink available space */ 177 /* terminate, set to next free slot, shrink available space */
@@ -383,6 +388,52 @@ void device_initialize(struct device *dev)
383 device_init_wakeup(dev, 0); 388 device_init_wakeup(dev, 0);
384} 389}
385 390
391#ifdef CONFIG_SYSFS_DEPRECATED
392static int setup_parent(struct device *dev, struct device *parent)
393{
394 /* Set the parent to the class, not the parent device */
395 /* this keeps sysfs from having a symlink to make old udevs happy */
396 if (dev->class)
397 dev->kobj.parent = &dev->class->subsys.kset.kobj;
398 else if (parent)
399 dev->kobj.parent = &parent->kobj;
400
401 return 0;
402}
403#else
404static int virtual_device_parent(struct device *dev)
405{
406 if (!dev->class)
407 return -ENODEV;
408
409 if (!dev->class->virtual_dir) {
410 static struct kobject *virtual_dir = NULL;
411
412 if (!virtual_dir)
413 virtual_dir = kobject_add_dir(&devices_subsys.kset.kobj, "virtual");
414 dev->class->virtual_dir = kobject_add_dir(virtual_dir, dev->class->name);
415 }
416
417 dev->kobj.parent = dev->class->virtual_dir;
418 return 0;
419}
420
421static int setup_parent(struct device *dev, struct device *parent)
422{
423 int error;
424
425 /* if this is a class device, and has no parent, create one */
426 if ((dev->class) && (parent == NULL)) {
427 error = virtual_device_parent(dev);
428 if (error)
429 return error;
430 } else if (parent)
431 dev->kobj.parent = &parent->kobj;
432
433 return 0;
434}
435#endif
436
386/** 437/**
387 * device_add - add device to device hierarchy. 438 * device_add - add device to device hierarchy.
388 * @dev: device. 439 * @dev: device.
@@ -405,29 +456,29 @@ int device_add(struct device *dev)
405 if (!dev || !strlen(dev->bus_id)) 456 if (!dev || !strlen(dev->bus_id))
406 goto Error; 457 goto Error;
407 458
408 /* if this is a class device, and has no parent, create one */ 459 pr_debug("DEV: registering device: ID = '%s'\n", dev->bus_id);
409 if ((dev->class) && (dev->parent == NULL)) {
410 error = virtual_device_parent(dev);
411 if (error)
412 goto Error;
413 }
414 460
415 parent = get_device(dev->parent); 461 parent = get_device(dev->parent);
416 462
417 pr_debug("DEV: registering device: ID = '%s'\n", dev->bus_id); 463 error = setup_parent(dev, parent);
464 if (error)
465 goto Error;
418 466
419 /* first, register with generic layer. */ 467 /* first, register with generic layer. */
420 kobject_set_name(&dev->kobj, "%s", dev->bus_id); 468 kobject_set_name(&dev->kobj, "%s", dev->bus_id);
421 if (parent) 469 error = kobject_add(&dev->kobj);
422 dev->kobj.parent = &parent->kobj; 470 if (error)
423
424 if ((error = kobject_add(&dev->kobj)))
425 goto Error; 471 goto Error;
426 472
427 /* notify platform of device entry */ 473 /* notify platform of device entry */
428 if (platform_notify) 474 if (platform_notify)
429 platform_notify(dev); 475 platform_notify(dev);
430 476
477 /* notify clients of device entry (new way) */
478 if (dev->bus)
479 blocking_notifier_call_chain(&dev->bus->bus_notifier,
480 BUS_NOTIFY_ADD_DEVICE, dev);
481
431 dev->uevent_attr.attr.name = "uevent"; 482 dev->uevent_attr.attr.name = "uevent";
432 dev->uevent_attr.attr.mode = S_IWUSR; 483 dev->uevent_attr.attr.mode = S_IWUSR;
433 if (dev->driver) 484 if (dev->driver)
@@ -461,13 +512,18 @@ int device_add(struct device *dev)
461 if (dev->class) { 512 if (dev->class) {
462 sysfs_create_link(&dev->kobj, &dev->class->subsys.kset.kobj, 513 sysfs_create_link(&dev->kobj, &dev->class->subsys.kset.kobj,
463 "subsystem"); 514 "subsystem");
464 sysfs_create_link(&dev->class->subsys.kset.kobj, &dev->kobj, 515 /* If this is not a "fake" compatible device, then create the
465 dev->bus_id); 516 * symlink from the class to the device. */
517 if (dev->kobj.parent != &dev->class->subsys.kset.kobj)
518 sysfs_create_link(&dev->class->subsys.kset.kobj,
519 &dev->kobj, dev->bus_id);
520#ifdef CONFIG_SYSFS_DEPRECATED
466 if (parent) { 521 if (parent) {
467 sysfs_create_link(&dev->kobj, &dev->parent->kobj, "device"); 522 sysfs_create_link(&dev->kobj, &dev->parent->kobj, "device");
468 class_name = make_class_name(dev->class->name, &dev->kobj); 523 class_name = make_class_name(dev->class->name, &dev->kobj);
469 sysfs_create_link(&dev->parent->kobj, &dev->kobj, class_name); 524 sysfs_create_link(&dev->parent->kobj, &dev->kobj, class_name);
470 } 525 }
526#endif
471 } 527 }
472 528
473 if ((error = device_add_attrs(dev))) 529 if ((error = device_add_attrs(dev)))
@@ -504,6 +560,9 @@ int device_add(struct device *dev)
504 BusError: 560 BusError:
505 device_pm_remove(dev); 561 device_pm_remove(dev);
506 PMError: 562 PMError:
563 if (dev->bus)
564 blocking_notifier_call_chain(&dev->bus->bus_notifier,
565 BUS_NOTIFY_DEL_DEVICE, dev);
507 device_remove_groups(dev); 566 device_remove_groups(dev);
508 GroupError: 567 GroupError:
509 device_remove_attrs(dev); 568 device_remove_attrs(dev);
@@ -586,22 +645,31 @@ void put_device(struct device * dev)
586void device_del(struct device * dev) 645void device_del(struct device * dev)
587{ 646{
588 struct device * parent = dev->parent; 647 struct device * parent = dev->parent;
589 char *class_name = NULL;
590 struct class_interface *class_intf; 648 struct class_interface *class_intf;
591 649
592 if (parent) 650 if (parent)
593 klist_del(&dev->knode_parent); 651 klist_del(&dev->knode_parent);
594 if (dev->devt_attr) 652 if (dev->devt_attr) {
595 device_remove_file(dev, dev->devt_attr); 653 device_remove_file(dev, dev->devt_attr);
654 kfree(dev->devt_attr);
655 }
596 if (dev->class) { 656 if (dev->class) {
597 sysfs_remove_link(&dev->kobj, "subsystem"); 657 sysfs_remove_link(&dev->kobj, "subsystem");
598 sysfs_remove_link(&dev->class->subsys.kset.kobj, dev->bus_id); 658 /* If this is not a "fake" compatible device, remove the
599 class_name = make_class_name(dev->class->name, &dev->kobj); 659 * symlink from the class to the device. */
660 if (dev->kobj.parent != &dev->class->subsys.kset.kobj)
661 sysfs_remove_link(&dev->class->subsys.kset.kobj,
662 dev->bus_id);
663#ifdef CONFIG_SYSFS_DEPRECATED
600 if (parent) { 664 if (parent) {
601 sysfs_remove_link(&dev->kobj, "device"); 665 char *class_name = make_class_name(dev->class->name,
666 &dev->kobj);
602 sysfs_remove_link(&dev->parent->kobj, class_name); 667 sysfs_remove_link(&dev->parent->kobj, class_name);
668 kfree(class_name);
669 sysfs_remove_link(&dev->kobj, "device");
603 } 670 }
604 kfree(class_name); 671#endif
672
605 down(&dev->class->sem); 673 down(&dev->class->sem);
606 /* notify any interfaces that the device is now gone */ 674 /* notify any interfaces that the device is now gone */
607 list_for_each_entry(class_intf, &dev->class->interfaces, node) 675 list_for_each_entry(class_intf, &dev->class->interfaces, node)
@@ -614,13 +682,16 @@ void device_del(struct device * dev)
614 device_remove_file(dev, &dev->uevent_attr); 682 device_remove_file(dev, &dev->uevent_attr);
615 device_remove_groups(dev); 683 device_remove_groups(dev);
616 device_remove_attrs(dev); 684 device_remove_attrs(dev);
685 bus_remove_device(dev);
617 686
618 /* Notify the platform of the removal, in case they 687 /* Notify the platform of the removal, in case they
619 * need to do anything... 688 * need to do anything...
620 */ 689 */
621 if (platform_notify_remove) 690 if (platform_notify_remove)
622 platform_notify_remove(dev); 691 platform_notify_remove(dev);
623 bus_remove_device(dev); 692 if (dev->bus)
693 blocking_notifier_call_chain(&dev->bus->bus_notifier,
694 BUS_NOTIFY_DEL_DEVICE, dev);
624 device_pm_remove(dev); 695 device_pm_remove(dev);
625 kobject_uevent(&dev->kobj, KOBJ_REMOVE); 696 kobject_uevent(&dev->kobj, KOBJ_REMOVE);
626 kobject_del(&dev->kobj); 697 kobject_del(&dev->kobj);
@@ -679,12 +750,45 @@ int device_for_each_child(struct device * parent, void * data,
679 return error; 750 return error;
680} 751}
681 752
753/**
754 * device_find_child - device iterator for locating a particular device.
755 * @parent: parent struct device
756 * @data: Data to pass to match function
757 * @match: Callback function to check device
758 *
759 * This is similar to the device_for_each_child() function above, but it
760 * returns a reference to a device that is 'found' for later use, as
761 * determined by the @match callback.
762 *
763 * The callback should return 0 if the device doesn't match and non-zero
764 * if it does. If the callback returns non-zero and a reference to the
765 * current device can be obtained, this function will return to the caller
766 * and not iterate over any more devices.
767 */
768struct device * device_find_child(struct device *parent, void *data,
769 int (*match)(struct device *, void *))
770{
771 struct klist_iter i;
772 struct device *child;
773
774 if (!parent)
775 return NULL;
776
777 klist_iter_init(&parent->klist_children, &i);
778 while ((child = next_device(&i)))
779 if (match(child, data) && get_device(child))
780 break;
781 klist_iter_exit(&i);
782 return child;
783}
784
682int __init devices_init(void) 785int __init devices_init(void)
683{ 786{
684 return subsystem_register(&devices_subsys); 787 return subsystem_register(&devices_subsys);
685} 788}
686 789
687EXPORT_SYMBOL_GPL(device_for_each_child); 790EXPORT_SYMBOL_GPL(device_for_each_child);
791EXPORT_SYMBOL_GPL(device_find_child);
688 792
689EXPORT_SYMBOL_GPL(device_initialize); 793EXPORT_SYMBOL_GPL(device_initialize);
690EXPORT_SYMBOL_GPL(device_add); 794EXPORT_SYMBOL_GPL(device_add);
@@ -807,8 +911,10 @@ int device_rename(struct device *dev, char *new_name)
807 911
808 pr_debug("DEVICE: renaming '%s' to '%s'\n", dev->bus_id, new_name); 912 pr_debug("DEVICE: renaming '%s' to '%s'\n", dev->bus_id, new_name);
809 913
914#ifdef CONFIG_SYSFS_DEPRECATED
810 if ((dev->class) && (dev->parent)) 915 if ((dev->class) && (dev->parent))
811 old_class_name = make_class_name(dev->class->name, &dev->kobj); 916 old_class_name = make_class_name(dev->class->name, &dev->kobj);
917#endif
812 918
813 if (dev->class) { 919 if (dev->class) {
814 old_symlink_name = kmalloc(BUS_ID_SIZE, GFP_KERNEL); 920 old_symlink_name = kmalloc(BUS_ID_SIZE, GFP_KERNEL);
@@ -823,6 +929,7 @@ int device_rename(struct device *dev, char *new_name)
823 929
824 error = kobject_rename(&dev->kobj, new_name); 930 error = kobject_rename(&dev->kobj, new_name);
825 931
932#ifdef CONFIG_SYSFS_DEPRECATED
826 if (old_class_name) { 933 if (old_class_name) {
827 new_class_name = make_class_name(dev->class->name, &dev->kobj); 934 new_class_name = make_class_name(dev->class->name, &dev->kobj);
828 if (new_class_name) { 935 if (new_class_name) {
@@ -831,6 +938,8 @@ int device_rename(struct device *dev, char *new_name)
831 sysfs_remove_link(&dev->parent->kobj, old_class_name); 938 sysfs_remove_link(&dev->parent->kobj, old_class_name);
832 } 939 }
833 } 940 }
941#endif
942
834 if (dev->class) { 943 if (dev->class) {
835 sysfs_remove_link(&dev->class->subsys.kset.kobj, 944 sysfs_remove_link(&dev->class->subsys.kset.kobj,
836 old_symlink_name); 945 old_symlink_name);
@@ -846,3 +955,95 @@ int device_rename(struct device *dev, char *new_name)
846 955
847 return error; 956 return error;
848} 957}
958
959
960static int device_move_class_links(struct device *dev,
961 struct device *old_parent,
962 struct device *new_parent)
963{
964#ifdef CONFIG_SYSFS_DEPRECATED
965 int error;
966 char *class_name;
967
968 class_name = make_class_name(dev->class->name, &dev->kobj);
969 if (!class_name) {
970 error = PTR_ERR(class_name);
971 class_name = NULL;
972 goto out;
973 }
974 if (old_parent) {
975 sysfs_remove_link(&dev->kobj, "device");
976 sysfs_remove_link(&old_parent->kobj, class_name);
977 }
978 error = sysfs_create_link(&dev->kobj, &new_parent->kobj, "device");
979 if (error)
980 goto out;
981 error = sysfs_create_link(&new_parent->kobj, &dev->kobj, class_name);
982 if (error)
983 sysfs_remove_link(&dev->kobj, "device");
984out:
985 kfree(class_name);
986 return error;
987#else
988 return 0;
989#endif
990}
991
992/**
993 * device_move - moves a device to a new parent
994 * @dev: the pointer to the struct device to be moved
995 * @new_parent: the new parent of the device
996 */
997int device_move(struct device *dev, struct device *new_parent)
998{
999 int error;
1000 struct device *old_parent;
1001
1002 dev = get_device(dev);
1003 if (!dev)
1004 return -EINVAL;
1005
1006 if (!device_is_registered(dev)) {
1007 error = -EINVAL;
1008 goto out;
1009 }
1010 new_parent = get_device(new_parent);
1011 if (!new_parent) {
1012 error = -EINVAL;
1013 goto out;
1014 }
1015 pr_debug("DEVICE: moving '%s' to '%s'\n", dev->bus_id,
1016 new_parent->bus_id);
1017 error = kobject_move(&dev->kobj, &new_parent->kobj);
1018 if (error) {
1019 put_device(new_parent);
1020 goto out;
1021 }
1022 old_parent = dev->parent;
1023 dev->parent = new_parent;
1024 if (old_parent)
1025 klist_remove(&dev->knode_parent);
1026 klist_add_tail(&dev->knode_parent, &new_parent->klist_children);
1027 if (!dev->class)
1028 goto out_put;
1029 error = device_move_class_links(dev, old_parent, new_parent);
1030 if (error) {
1031 /* We ignore errors on cleanup since we're hosed anyway... */
1032 device_move_class_links(dev, new_parent, old_parent);
1033 if (!kobject_move(&dev->kobj, &old_parent->kobj)) {
1034 klist_remove(&dev->knode_parent);
1035 if (old_parent)
1036 klist_add_tail(&dev->knode_parent,
1037 &old_parent->klist_children);
1038 }
1039 put_device(new_parent);
1040 goto out;
1041 }
1042out_put:
1043 put_device(old_parent);
1044out:
1045 put_device(dev);
1046 return error;
1047}
1048
1049EXPORT_SYMBOL_GPL(device_move);
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index c5d6bb4290ad..510e7884975f 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -26,33 +26,28 @@
26#define to_drv(node) container_of(node, struct device_driver, kobj.entry) 26#define to_drv(node) container_of(node, struct device_driver, kobj.entry)
27 27
28 28
29/** 29static void driver_bound(struct device *dev)
30 * device_bind_driver - bind a driver to one device.
31 * @dev: device.
32 *
33 * Allow manual attachment of a driver to a device.
34 * Caller must have already set @dev->driver.
35 *
36 * Note that this does not modify the bus reference count
37 * nor take the bus's rwsem. Please verify those are accounted
38 * for before calling this. (It is ok to call with no other effort
39 * from a driver's probe() method.)
40 *
41 * This function must be called with @dev->sem held.
42 */
43int device_bind_driver(struct device *dev)
44{ 30{
45 int ret;
46
47 if (klist_node_attached(&dev->knode_driver)) { 31 if (klist_node_attached(&dev->knode_driver)) {
48 printk(KERN_WARNING "%s: device %s already bound\n", 32 printk(KERN_WARNING "%s: device %s already bound\n",
49 __FUNCTION__, kobject_name(&dev->kobj)); 33 __FUNCTION__, kobject_name(&dev->kobj));
50 return 0; 34 return;
51 } 35 }
52 36
53 pr_debug("bound device '%s' to driver '%s'\n", 37 pr_debug("bound device '%s' to driver '%s'\n",
54 dev->bus_id, dev->driver->name); 38 dev->bus_id, dev->driver->name);
39
40 if (dev->bus)
41 blocking_notifier_call_chain(&dev->bus->bus_notifier,
42 BUS_NOTIFY_BOUND_DRIVER, dev);
43
55 klist_add_tail(&dev->knode_driver, &dev->driver->klist_devices); 44 klist_add_tail(&dev->knode_driver, &dev->driver->klist_devices);
45}
46
47static int driver_sysfs_add(struct device *dev)
48{
49 int ret;
50
56 ret = sysfs_create_link(&dev->driver->kobj, &dev->kobj, 51 ret = sysfs_create_link(&dev->driver->kobj, &dev->kobj,
57 kobject_name(&dev->kobj)); 52 kobject_name(&dev->kobj));
58 if (ret == 0) { 53 if (ret == 0) {
@@ -65,6 +60,36 @@ int device_bind_driver(struct device *dev)
65 return ret; 60 return ret;
66} 61}
67 62
63static void driver_sysfs_remove(struct device *dev)
64{
65 struct device_driver *drv = dev->driver;
66
67 if (drv) {
68 sysfs_remove_link(&drv->kobj, kobject_name(&dev->kobj));
69 sysfs_remove_link(&dev->kobj, "driver");
70 }
71}
72
73/**
74 * device_bind_driver - bind a driver to one device.
75 * @dev: device.
76 *
77 * Allow manual attachment of a driver to a device.
78 * Caller must have already set @dev->driver.
79 *
80 * Note that this does not modify the bus reference count
81 * nor take the bus's rwsem. Please verify those are accounted
82 * for before calling this. (It is ok to call with no other effort
83 * from a driver's probe() method.)
84 *
85 * This function must be called with @dev->sem held.
86 */
87int device_bind_driver(struct device *dev)
88{
89 driver_bound(dev);
90 return driver_sysfs_add(dev);
91}
92
68struct stupid_thread_structure { 93struct stupid_thread_structure {
69 struct device_driver *drv; 94 struct device_driver *drv;
70 struct device *dev; 95 struct device *dev;
@@ -85,30 +110,32 @@ static int really_probe(void *void_data)
85 drv->bus->name, drv->name, dev->bus_id); 110 drv->bus->name, drv->name, dev->bus_id);
86 111
87 dev->driver = drv; 112 dev->driver = drv;
113 if (driver_sysfs_add(dev)) {
114 printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n",
115 __FUNCTION__, dev->bus_id);
116 goto probe_failed;
117 }
118
88 if (dev->bus->probe) { 119 if (dev->bus->probe) {
89 ret = dev->bus->probe(dev); 120 ret = dev->bus->probe(dev);
90 if (ret) { 121 if (ret)
91 dev->driver = NULL;
92 goto probe_failed; 122 goto probe_failed;
93 }
94 } else if (drv->probe) { 123 } else if (drv->probe) {
95 ret = drv->probe(dev); 124 ret = drv->probe(dev);
96 if (ret) { 125 if (ret)
97 dev->driver = NULL;
98 goto probe_failed; 126 goto probe_failed;
99 }
100 }
101 if (device_bind_driver(dev)) {
102 printk(KERN_ERR "%s: device_bind_driver(%s) failed\n",
103 __FUNCTION__, dev->bus_id);
104 /* How does undo a ->probe? We're screwed. */
105 } 127 }
128
129 driver_bound(dev);
106 ret = 1; 130 ret = 1;
107 pr_debug("%s: Bound Device %s to Driver %s\n", 131 pr_debug("%s: Bound Device %s to Driver %s\n",
108 drv->bus->name, dev->bus_id, drv->name); 132 drv->bus->name, dev->bus_id, drv->name);
109 goto done; 133 goto done;
110 134
111probe_failed: 135probe_failed:
136 driver_sysfs_remove(dev);
137 dev->driver = NULL;
138
112 if (ret == -ENODEV || ret == -ENXIO) { 139 if (ret == -ENODEV || ret == -ENXIO) {
113 /* Driver matched, but didn't support device 140 /* Driver matched, but didn't support device
114 * or device not found. 141 * or device not found.
@@ -284,10 +311,15 @@ static void __device_release_driver(struct device * dev)
284 drv = dev->driver; 311 drv = dev->driver;
285 if (drv) { 312 if (drv) {
286 get_driver(drv); 313 get_driver(drv);
287 sysfs_remove_link(&drv->kobj, kobject_name(&dev->kobj)); 314 driver_sysfs_remove(dev);
288 sysfs_remove_link(&dev->kobj, "driver"); 315 sysfs_remove_link(&dev->kobj, "driver");
289 klist_remove(&dev->knode_driver); 316 klist_remove(&dev->knode_driver);
290 317
318 if (dev->bus)
319 blocking_notifier_call_chain(&dev->bus->bus_notifier,
320 BUS_NOTIFY_UNBIND_DRIVER,
321 dev);
322
291 if (dev->bus && dev->bus->remove) 323 if (dev->bus && dev->bus->remove)
292 dev->bus->remove(dev); 324 dev->bus->remove(dev);
293 else if (drv->remove) 325 else if (drv->remove)
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c
index 14615694ae9a..4bad2870c485 100644
--- a/drivers/base/firmware_class.c
+++ b/drivers/base/firmware_class.c
@@ -21,6 +21,8 @@
21#include <linux/firmware.h> 21#include <linux/firmware.h>
22#include "base.h" 22#include "base.h"
23 23
24#define to_dev(obj) container_of(obj, struct device, kobj)
25
24MODULE_AUTHOR("Manuel Estrada Sainz <ranty@debian.org>"); 26MODULE_AUTHOR("Manuel Estrada Sainz <ranty@debian.org>");
25MODULE_DESCRIPTION("Multi purpose firmware loading support"); 27MODULE_DESCRIPTION("Multi purpose firmware loading support");
26MODULE_LICENSE("GPL"); 28MODULE_LICENSE("GPL");
@@ -86,12 +88,12 @@ firmware_timeout_store(struct class *class, const char *buf, size_t count)
86 88
87static CLASS_ATTR(timeout, 0644, firmware_timeout_show, firmware_timeout_store); 89static CLASS_ATTR(timeout, 0644, firmware_timeout_show, firmware_timeout_store);
88 90
89static void fw_class_dev_release(struct class_device *class_dev); 91static void fw_dev_release(struct device *dev);
90 92
91static int firmware_class_uevent(struct class_device *class_dev, char **envp, 93static int firmware_uevent(struct device *dev, char **envp, int num_envp,
92 int num_envp, char *buffer, int buffer_size) 94 char *buffer, int buffer_size)
93{ 95{
94 struct firmware_priv *fw_priv = class_get_devdata(class_dev); 96 struct firmware_priv *fw_priv = dev_get_drvdata(dev);
95 int i = 0, len = 0; 97 int i = 0, len = 0;
96 98
97 if (!test_bit(FW_STATUS_READY, &fw_priv->status)) 99 if (!test_bit(FW_STATUS_READY, &fw_priv->status))
@@ -110,21 +112,21 @@ static int firmware_class_uevent(struct class_device *class_dev, char **envp,
110 112
111static struct class firmware_class = { 113static struct class firmware_class = {
112 .name = "firmware", 114 .name = "firmware",
113 .uevent = firmware_class_uevent, 115 .dev_uevent = firmware_uevent,
114 .release = fw_class_dev_release, 116 .dev_release = fw_dev_release,
115}; 117};
116 118
117static ssize_t 119static ssize_t firmware_loading_show(struct device *dev,
118firmware_loading_show(struct class_device *class_dev, char *buf) 120 struct device_attribute *attr, char *buf)
119{ 121{
120 struct firmware_priv *fw_priv = class_get_devdata(class_dev); 122 struct firmware_priv *fw_priv = dev_get_drvdata(dev);
121 int loading = test_bit(FW_STATUS_LOADING, &fw_priv->status); 123 int loading = test_bit(FW_STATUS_LOADING, &fw_priv->status);
122 return sprintf(buf, "%d\n", loading); 124 return sprintf(buf, "%d\n", loading);
123} 125}
124 126
125/** 127/**
126 * firmware_loading_store - set value in the 'loading' control file 128 * firmware_loading_store - set value in the 'loading' control file
127 * @class_dev: class_device pointer 129 * @dev: device pointer
128 * @buf: buffer to scan for loading control value 130 * @buf: buffer to scan for loading control value
129 * @count: number of bytes in @buf 131 * @count: number of bytes in @buf
130 * 132 *
@@ -134,11 +136,11 @@ firmware_loading_show(struct class_device *class_dev, char *buf)
134 * 0: Conclude the load and hand the data to the driver code. 136 * 0: Conclude the load and hand the data to the driver code.
135 * -1: Conclude the load with an error and discard any written data. 137 * -1: Conclude the load with an error and discard any written data.
136 **/ 138 **/
137static ssize_t 139static ssize_t firmware_loading_store(struct device *dev,
138firmware_loading_store(struct class_device *class_dev, 140 struct device_attribute *attr,
139 const char *buf, size_t count) 141 const char *buf, size_t count)
140{ 142{
141 struct firmware_priv *fw_priv = class_get_devdata(class_dev); 143 struct firmware_priv *fw_priv = dev_get_drvdata(dev);
142 int loading = simple_strtol(buf, NULL, 10); 144 int loading = simple_strtol(buf, NULL, 10);
143 145
144 switch (loading) { 146 switch (loading) {
@@ -174,15 +176,14 @@ firmware_loading_store(struct class_device *class_dev,
174 return count; 176 return count;
175} 177}
176 178
177static CLASS_DEVICE_ATTR(loading, 0644, 179static DEVICE_ATTR(loading, 0644, firmware_loading_show, firmware_loading_store);
178 firmware_loading_show, firmware_loading_store);
179 180
180static ssize_t 181static ssize_t
181firmware_data_read(struct kobject *kobj, 182firmware_data_read(struct kobject *kobj,
182 char *buffer, loff_t offset, size_t count) 183 char *buffer, loff_t offset, size_t count)
183{ 184{
184 struct class_device *class_dev = to_class_dev(kobj); 185 struct device *dev = to_dev(kobj);
185 struct firmware_priv *fw_priv = class_get_devdata(class_dev); 186 struct firmware_priv *fw_priv = dev_get_drvdata(dev);
186 struct firmware *fw; 187 struct firmware *fw;
187 ssize_t ret_count = count; 188 ssize_t ret_count = count;
188 189
@@ -234,7 +235,7 @@ fw_realloc_buffer(struct firmware_priv *fw_priv, int min_size)
234 235
235/** 236/**
236 * firmware_data_write - write method for firmware 237 * firmware_data_write - write method for firmware
237 * @kobj: kobject for the class_device 238 * @kobj: kobject for the device
238 * @buffer: buffer being written 239 * @buffer: buffer being written
239 * @offset: buffer offset for write in total data store area 240 * @offset: buffer offset for write in total data store area
240 * @count: buffer size 241 * @count: buffer size
@@ -246,8 +247,8 @@ static ssize_t
246firmware_data_write(struct kobject *kobj, 247firmware_data_write(struct kobject *kobj,
247 char *buffer, loff_t offset, size_t count) 248 char *buffer, loff_t offset, size_t count)
248{ 249{
249 struct class_device *class_dev = to_class_dev(kobj); 250 struct device *dev = to_dev(kobj);
250 struct firmware_priv *fw_priv = class_get_devdata(class_dev); 251 struct firmware_priv *fw_priv = dev_get_drvdata(dev);
251 struct firmware *fw; 252 struct firmware *fw;
252 ssize_t retval; 253 ssize_t retval;
253 254
@@ -280,13 +281,12 @@ static struct bin_attribute firmware_attr_data_tmpl = {
280 .write = firmware_data_write, 281 .write = firmware_data_write,
281}; 282};
282 283
283static void 284static void fw_dev_release(struct device *dev)
284fw_class_dev_release(struct class_device *class_dev)
285{ 285{
286 struct firmware_priv *fw_priv = class_get_devdata(class_dev); 286 struct firmware_priv *fw_priv = dev_get_drvdata(dev);
287 287
288 kfree(fw_priv); 288 kfree(fw_priv);
289 kfree(class_dev); 289 kfree(dev);
290 290
291 module_put(THIS_MODULE); 291 module_put(THIS_MODULE);
292} 292}
@@ -298,26 +298,23 @@ firmware_class_timeout(u_long data)
298 fw_load_abort(fw_priv); 298 fw_load_abort(fw_priv);
299} 299}
300 300
301static inline void 301static inline void fw_setup_device_id(struct device *f_dev, struct device *dev)
302fw_setup_class_device_id(struct class_device *class_dev, struct device *dev)
303{ 302{
304 /* XXX warning we should watch out for name collisions */ 303 /* XXX warning we should watch out for name collisions */
305 strlcpy(class_dev->class_id, dev->bus_id, BUS_ID_SIZE); 304 strlcpy(f_dev->bus_id, dev->bus_id, BUS_ID_SIZE);
306} 305}
307 306
308static int 307static int fw_register_device(struct device **dev_p, const char *fw_name,
309fw_register_class_device(struct class_device **class_dev_p, 308 struct device *device)
310 const char *fw_name, struct device *device)
311{ 309{
312 int retval; 310 int retval;
313 struct firmware_priv *fw_priv = kzalloc(sizeof(*fw_priv), 311 struct firmware_priv *fw_priv = kzalloc(sizeof(*fw_priv),
314 GFP_KERNEL); 312 GFP_KERNEL);
315 struct class_device *class_dev = kzalloc(sizeof(*class_dev), 313 struct device *f_dev = kzalloc(sizeof(*f_dev), GFP_KERNEL);
316 GFP_KERNEL);
317 314
318 *class_dev_p = NULL; 315 *dev_p = NULL;
319 316
320 if (!fw_priv || !class_dev) { 317 if (!fw_priv || !f_dev) {
321 printk(KERN_ERR "%s: kmalloc failed\n", __FUNCTION__); 318 printk(KERN_ERR "%s: kmalloc failed\n", __FUNCTION__);
322 retval = -ENOMEM; 319 retval = -ENOMEM;
323 goto error_kfree; 320 goto error_kfree;
@@ -331,55 +328,54 @@ fw_register_class_device(struct class_device **class_dev_p,
331 fw_priv->timeout.data = (u_long) fw_priv; 328 fw_priv->timeout.data = (u_long) fw_priv;
332 init_timer(&fw_priv->timeout); 329 init_timer(&fw_priv->timeout);
333 330
334 fw_setup_class_device_id(class_dev, device); 331 fw_setup_device_id(f_dev, device);
335 class_dev->dev = device; 332 f_dev->parent = device;
336 class_dev->class = &firmware_class; 333 f_dev->class = &firmware_class;
337 class_set_devdata(class_dev, fw_priv); 334 dev_set_drvdata(f_dev, fw_priv);
338 retval = class_device_register(class_dev); 335 retval = device_register(f_dev);
339 if (retval) { 336 if (retval) {
340 printk(KERN_ERR "%s: class_device_register failed\n", 337 printk(KERN_ERR "%s: device_register failed\n",
341 __FUNCTION__); 338 __FUNCTION__);
342 goto error_kfree; 339 goto error_kfree;
343 } 340 }
344 *class_dev_p = class_dev; 341 *dev_p = f_dev;
345 return 0; 342 return 0;
346 343
347error_kfree: 344error_kfree:
348 kfree(fw_priv); 345 kfree(fw_priv);
349 kfree(class_dev); 346 kfree(f_dev);
350 return retval; 347 return retval;
351} 348}
352 349
353static int 350static int fw_setup_device(struct firmware *fw, struct device **dev_p,
354fw_setup_class_device(struct firmware *fw, struct class_device **class_dev_p, 351 const char *fw_name, struct device *device,
355 const char *fw_name, struct device *device, int uevent) 352 int uevent)
356{ 353{
357 struct class_device *class_dev; 354 struct device *f_dev;
358 struct firmware_priv *fw_priv; 355 struct firmware_priv *fw_priv;
359 int retval; 356 int retval;
360 357
361 *class_dev_p = NULL; 358 *dev_p = NULL;
362 retval = fw_register_class_device(&class_dev, fw_name, device); 359 retval = fw_register_device(&f_dev, fw_name, device);
363 if (retval) 360 if (retval)
364 goto out; 361 goto out;
365 362
366 /* Need to pin this module until class device is destroyed */ 363 /* Need to pin this module until class device is destroyed */
367 __module_get(THIS_MODULE); 364 __module_get(THIS_MODULE);
368 365
369 fw_priv = class_get_devdata(class_dev); 366 fw_priv = dev_get_drvdata(f_dev);
370 367
371 fw_priv->fw = fw; 368 fw_priv->fw = fw;
372 retval = sysfs_create_bin_file(&class_dev->kobj, &fw_priv->attr_data); 369 retval = sysfs_create_bin_file(&f_dev->kobj, &fw_priv->attr_data);
373 if (retval) { 370 if (retval) {
374 printk(KERN_ERR "%s: sysfs_create_bin_file failed\n", 371 printk(KERN_ERR "%s: sysfs_create_bin_file failed\n",
375 __FUNCTION__); 372 __FUNCTION__);
376 goto error_unreg; 373 goto error_unreg;
377 } 374 }
378 375
379 retval = class_device_create_file(class_dev, 376 retval = device_create_file(f_dev, &dev_attr_loading);
380 &class_device_attr_loading);
381 if (retval) { 377 if (retval) {
382 printk(KERN_ERR "%s: class_device_create_file failed\n", 378 printk(KERN_ERR "%s: device_create_file failed\n",
383 __FUNCTION__); 379 __FUNCTION__);
384 goto error_unreg; 380 goto error_unreg;
385 } 381 }
@@ -388,11 +384,11 @@ fw_setup_class_device(struct firmware *fw, struct class_device **class_dev_p,
388 set_bit(FW_STATUS_READY, &fw_priv->status); 384 set_bit(FW_STATUS_READY, &fw_priv->status);
389 else 385 else
390 set_bit(FW_STATUS_READY_NOHOTPLUG, &fw_priv->status); 386 set_bit(FW_STATUS_READY_NOHOTPLUG, &fw_priv->status);
391 *class_dev_p = class_dev; 387 *dev_p = f_dev;
392 goto out; 388 goto out;
393 389
394error_unreg: 390error_unreg:
395 class_device_unregister(class_dev); 391 device_unregister(f_dev);
396out: 392out:
397 return retval; 393 return retval;
398} 394}
@@ -401,7 +397,7 @@ static int
401_request_firmware(const struct firmware **firmware_p, const char *name, 397_request_firmware(const struct firmware **firmware_p, const char *name,
402 struct device *device, int uevent) 398 struct device *device, int uevent)
403{ 399{
404 struct class_device *class_dev; 400 struct device *f_dev;
405 struct firmware_priv *fw_priv; 401 struct firmware_priv *fw_priv;
406 struct firmware *firmware; 402 struct firmware *firmware;
407 int retval; 403 int retval;
@@ -417,12 +413,11 @@ _request_firmware(const struct firmware **firmware_p, const char *name,
417 goto out; 413 goto out;
418 } 414 }
419 415
420 retval = fw_setup_class_device(firmware, &class_dev, name, device, 416 retval = fw_setup_device(firmware, &f_dev, name, device, uevent);
421 uevent);
422 if (retval) 417 if (retval)
423 goto error_kfree_fw; 418 goto error_kfree_fw;
424 419
425 fw_priv = class_get_devdata(class_dev); 420 fw_priv = dev_get_drvdata(f_dev);
426 421
427 if (uevent) { 422 if (uevent) {
428 if (loading_timeout > 0) { 423 if (loading_timeout > 0) {
@@ -430,7 +425,7 @@ _request_firmware(const struct firmware **firmware_p, const char *name,
430 add_timer(&fw_priv->timeout); 425 add_timer(&fw_priv->timeout);
431 } 426 }
432 427
433 kobject_uevent(&class_dev->kobj, KOBJ_ADD); 428 kobject_uevent(&f_dev->kobj, KOBJ_ADD);
434 wait_for_completion(&fw_priv->completion); 429 wait_for_completion(&fw_priv->completion);
435 set_bit(FW_STATUS_DONE, &fw_priv->status); 430 set_bit(FW_STATUS_DONE, &fw_priv->status);
436 del_timer_sync(&fw_priv->timeout); 431 del_timer_sync(&fw_priv->timeout);
@@ -445,7 +440,7 @@ _request_firmware(const struct firmware **firmware_p, const char *name,
445 } 440 }
446 fw_priv->fw = NULL; 441 fw_priv->fw = NULL;
447 mutex_unlock(&fw_lock); 442 mutex_unlock(&fw_lock);
448 class_device_unregister(class_dev); 443 device_unregister(f_dev);
449 goto out; 444 goto out;
450 445
451error_kfree_fw: 446error_kfree_fw:
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 940ce41f1887..d1df4a087924 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -388,6 +388,11 @@ static int platform_drv_probe(struct device *_dev)
388 return drv->probe(dev); 388 return drv->probe(dev);
389} 389}
390 390
391static int platform_drv_probe_fail(struct device *_dev)
392{
393 return -ENXIO;
394}
395
391static int platform_drv_remove(struct device *_dev) 396static int platform_drv_remove(struct device *_dev)
392{ 397{
393 struct platform_driver *drv = to_platform_driver(_dev->driver); 398 struct platform_driver *drv = to_platform_driver(_dev->driver);
@@ -451,6 +456,49 @@ void platform_driver_unregister(struct platform_driver *drv)
451} 456}
452EXPORT_SYMBOL_GPL(platform_driver_unregister); 457EXPORT_SYMBOL_GPL(platform_driver_unregister);
453 458
459/**
460 * platform_driver_probe - register driver for non-hotpluggable device
461 * @drv: platform driver structure
462 * @probe: the driver probe routine, probably from an __init section
463 *
464 * Use this instead of platform_driver_register() when you know the device
465 * is not hotpluggable and has already been registered, and you want to
466 * remove its run-once probe() infrastructure from memory after the driver
467 * has bound to the device.
468 *
469 * One typical use for this would be with drivers for controllers integrated
470 * into system-on-chip processors, where the controller devices have been
471 * configured as part of board setup.
472 *
473 * Returns zero if the driver registered and bound to a device, else returns
474 * a negative error code and with the driver not registered.
475 */
476int platform_driver_probe(struct platform_driver *drv,
477 int (*probe)(struct platform_device *))
478{
479 int retval, code;
480
481 /* temporary section violation during probe() */
482 drv->probe = probe;
483 retval = code = platform_driver_register(drv);
484
485 /* Fixup that section violation, being paranoid about code scanning
486 * the list of drivers in order to probe new devices. Check to see
487 * if the probe was successful, and make sure any forced probes of
488 * new devices fail.
489 */
490 spin_lock(&platform_bus_type.klist_drivers.k_lock);
491 drv->probe = NULL;
492 if (code == 0 && list_empty(&drv->driver.klist_devices.k_list))
493 retval = -ENODEV;
494 drv->driver.probe = platform_drv_probe_fail;
495 spin_unlock(&platform_bus_type.klist_drivers.k_lock);
496
497 if (code != retval)
498 platform_driver_unregister(drv);
499 return retval;
500}
501EXPORT_SYMBOL_GPL(platform_driver_probe);
454 502
455/* modalias support enables more hands-off userspace setup: 503/* modalias support enables more hands-off userspace setup:
456 * (a) environment variable lets new-style hotplug events work once system is 504 * (a) environment variable lets new-style hotplug events work once system is
diff --git a/drivers/base/topology.c b/drivers/base/topology.c
index 28dccb730af9..3d12b85b0962 100644
--- a/drivers/base/topology.c
+++ b/drivers/base/topology.c
@@ -94,54 +94,63 @@ static struct attribute_group topology_attr_group = {
94 .name = "topology" 94 .name = "topology"
95}; 95};
96 96
97static cpumask_t topology_dev_map = CPU_MASK_NONE;
98
97/* Add/Remove cpu_topology interface for CPU device */ 99/* Add/Remove cpu_topology interface for CPU device */
98static int __cpuinit topology_add_dev(struct sys_device * sys_dev) 100static int __cpuinit topology_add_dev(unsigned int cpu)
99{ 101{
100 return sysfs_create_group(&sys_dev->kobj, &topology_attr_group); 102 int rc;
103 struct sys_device *sys_dev = get_cpu_sysdev(cpu);
104
105 rc = sysfs_create_group(&sys_dev->kobj, &topology_attr_group);
106 if (!rc)
107 cpu_set(cpu, topology_dev_map);
108 return rc;
101} 109}
102 110
103static int __cpuinit topology_remove_dev(struct sys_device * sys_dev) 111#ifdef CONFIG_HOTPLUG_CPU
112static void __cpuinit topology_remove_dev(unsigned int cpu)
104{ 113{
114 struct sys_device *sys_dev = get_cpu_sysdev(cpu);
115
116 if (!cpu_isset(cpu, topology_dev_map))
117 return;
118 cpu_clear(cpu, topology_dev_map);
105 sysfs_remove_group(&sys_dev->kobj, &topology_attr_group); 119 sysfs_remove_group(&sys_dev->kobj, &topology_attr_group);
106 return 0;
107} 120}
108 121
109static int __cpuinit topology_cpu_callback(struct notifier_block *nfb, 122static int __cpuinit topology_cpu_callback(struct notifier_block *nfb,
110 unsigned long action, void *hcpu) 123 unsigned long action, void *hcpu)
111{ 124{
112 unsigned int cpu = (unsigned long)hcpu; 125 unsigned int cpu = (unsigned long)hcpu;
113 struct sys_device *sys_dev; 126 int rc = 0;
114 127
115 sys_dev = get_cpu_sysdev(cpu);
116 switch (action) { 128 switch (action) {
117 case CPU_ONLINE: 129 case CPU_UP_PREPARE:
118 topology_add_dev(sys_dev); 130 rc = topology_add_dev(cpu);
119 break; 131 break;
132 case CPU_UP_CANCELED:
120 case CPU_DEAD: 133 case CPU_DEAD:
121 topology_remove_dev(sys_dev); 134 topology_remove_dev(cpu);
122 break; 135 break;
123 } 136 }
124 return NOTIFY_OK; 137 return rc ? NOTIFY_BAD : NOTIFY_OK;
125} 138}
126 139#endif
127static struct notifier_block __cpuinitdata topology_cpu_notifier =
128{
129 .notifier_call = topology_cpu_callback,
130};
131 140
132static int __cpuinit topology_sysfs_init(void) 141static int __cpuinit topology_sysfs_init(void)
133{ 142{
134 int i; 143 int cpu;
144 int rc;
135 145
136 for_each_online_cpu(i) { 146 for_each_online_cpu(cpu) {
137 topology_cpu_callback(&topology_cpu_notifier, CPU_ONLINE, 147 rc = topology_add_dev(cpu);
138 (void *)(long)i); 148 if (rc)
149 return rc;
139 } 150 }
140 151 hotcpu_notifier(topology_cpu_callback, 0);
141 register_hotcpu_notifier(&topology_cpu_notifier);
142 152
143 return 0; 153 return 0;
144} 154}
145 155
146device_initcall(topology_sysfs_init); 156device_initcall(topology_sysfs_init);
147
diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c
index 7ea0f48f8fa6..2df5cf4ec743 100644
--- a/drivers/cdrom/cdrom.c
+++ b/drivers/cdrom/cdrom.c
@@ -2133,16 +2133,14 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
2133 rq->timeout = 60 * HZ; 2133 rq->timeout = 60 * HZ;
2134 bio = rq->bio; 2134 bio = rq->bio;
2135 2135
2136 if (rq->bio)
2137 blk_queue_bounce(q, &rq->bio);
2138
2139 if (blk_execute_rq(q, cdi->disk, rq, 0)) { 2136 if (blk_execute_rq(q, cdi->disk, rq, 0)) {
2140 struct request_sense *s = rq->sense; 2137 struct request_sense *s = rq->sense;
2141 ret = -EIO; 2138 ret = -EIO;
2142 cdi->last_sense = s->sense_key; 2139 cdi->last_sense = s->sense_key;
2143 } 2140 }
2144 2141
2145 if (blk_rq_unmap_user(bio, len)) 2142 rq->bio = bio;
2143 if (blk_rq_unmap_user(rq))
2146 ret = -EFAULT; 2144 ret = -EFAULT;
2147 2145
2148 if (ret) 2146 if (ret)
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 2af12fc45115..24f922f12783 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -855,39 +855,6 @@ config TANBAC_TB0219
855 depends TANBAC_TB022X 855 depends TANBAC_TB022X
856 select GPIO_VR41XX 856 select GPIO_VR41XX
857 857
858menu "Ftape, the floppy tape device driver"
859
860config FTAPE
861 tristate "Ftape (QIC-80/Travan) support"
862 depends on BROKEN_ON_SMP && (ALPHA || X86)
863 ---help---
864 If you have a tape drive that is connected to your floppy
865 controller, say Y here.
866
867 Some tape drives (like the Seagate "Tape Store 3200" or the Iomega
868 "Ditto 3200" or the Exabyte "Eagle TR-3") come with a "high speed"
869 controller of their own. These drives (and their companion
870 controllers) are also supported if you say Y here.
871
872 If you have a special controller (such as the CMS FC-10, FC-20,
873 Mountain Mach-II, or any controller that is based on the Intel 82078
874 FDC like the high speed controllers by Seagate and Exabyte and
875 Iomega's "Ditto Dash") you must configure it by selecting the
876 appropriate entries from the "Floppy tape controllers" sub-menu
877 below and possibly modify the default values for the IRQ and DMA
878 channel and the IO base in ftape's configuration menu.
879
880 If you want to use your floppy tape drive on a PCI-bus based system,
881 please read the file <file:drivers/char/ftape/README.PCI>.
882
883 The ftape kernel driver is also available as a runtime loadable
884 module. To compile this driver as a module, choose M here: the
885 module will be called ftape.
886
887source "drivers/char/ftape/Kconfig"
888
889endmenu
890
891source "drivers/char/agp/Kconfig" 858source "drivers/char/agp/Kconfig"
892 859
893source "drivers/char/drm/Kconfig" 860source "drivers/char/drm/Kconfig"
@@ -994,7 +961,7 @@ config HPET
994 help 961 help
995 If you say Y here, you will have a miscdevice named "/dev/hpet/". Each 962 If you say Y here, you will have a miscdevice named "/dev/hpet/". Each
996 open selects one of the timers supported by the HPET. The timers are 963 open selects one of the timers supported by the HPET. The timers are
997 non-periodioc and/or periodic. 964 non-periodic and/or periodic.
998 965
999config HPET_RTC_IRQ 966config HPET_RTC_IRQ
1000 bool "HPET Control RTC IRQ" if !HPET_EMULATE_RTC 967 bool "HPET Control RTC IRQ" if !HPET_EMULATE_RTC
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 777cad045094..b1fcdab90947 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -78,7 +78,6 @@ obj-$(CONFIG_TOSHIBA) += toshiba.o
78obj-$(CONFIG_I8K) += i8k.o 78obj-$(CONFIG_I8K) += i8k.o
79obj-$(CONFIG_DS1620) += ds1620.o 79obj-$(CONFIG_DS1620) += ds1620.o
80obj-$(CONFIG_HW_RANDOM) += hw_random/ 80obj-$(CONFIG_HW_RANDOM) += hw_random/
81obj-$(CONFIG_FTAPE) += ftape/
82obj-$(CONFIG_COBALT_LCD) += lcd.o 81obj-$(CONFIG_COBALT_LCD) += lcd.o
83obj-$(CONFIG_PPDEV) += ppdev.o 82obj-$(CONFIG_PPDEV) += ppdev.o
84obj-$(CONFIG_NWBUTTON) += nwbutton.o 83obj-$(CONFIG_NWBUTTON) += nwbutton.o
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index c39200161688..5ff457b41efb 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -1054,7 +1054,7 @@ void *agp_generic_alloc_page(struct agp_bridge_data *bridge)
1054{ 1054{
1055 struct page * page; 1055 struct page * page;
1056 1056
1057 page = alloc_page(GFP_KERNEL); 1057 page = alloc_page(GFP_KERNEL | GFP_DMA32);
1058 if (page == NULL) 1058 if (page == NULL)
1059 return NULL; 1059 return NULL;
1060 1060
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index d1ede7db5a12..555b3a8ab49c 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -169,7 +169,7 @@ static void *i8xx_alloc_pages(void)
169{ 169{
170 struct page * page; 170 struct page * page;
171 171
172 page = alloc_pages(GFP_KERNEL, 2); 172 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
173 if (page == NULL) 173 if (page == NULL)
174 return NULL; 174 return NULL;
175 175
@@ -387,11 +387,7 @@ static void intel_i830_init_gtt_entries(void)
387 /* We obtain the size of the GTT, which is also stored (for some 387 /* We obtain the size of the GTT, which is also stored (for some
388 * reason) at the top of stolen memory. Then we add 4KB to that 388 * reason) at the top of stolen memory. Then we add 4KB to that
389 * for the video BIOS popup, which is also stored in there. */ 389 * for the video BIOS popup, which is also stored in there. */
390 390 size = agp_bridge->driver->fetch_size() + 4;
391 if (IS_I965)
392 size = 512 + 4;
393 else
394 size = agp_bridge->driver->fetch_size() + 4;
395 391
396 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 392 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
397 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 393 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
@@ -805,6 +801,26 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
805 801
806 return 0; 802 return 0;
807} 803}
804
805/*
806 * The i965 supports 36-bit physical addresses, but to keep
807 * the format of the GTT the same, the bits that don't fit
808 * in a 32-bit word are shifted down to bits 4..7.
809 *
810 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
811 * is always zero on 32-bit architectures, so no need to make
812 * this conditional.
813 */
814static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
815 unsigned long addr, int type)
816{
817 /* Shift high bits down */
818 addr |= (addr >> 28) & 0xf0;
819
820 /* Type checking must be done elsewhere */
821 return addr | bridge->driver->masks[type].mask;
822}
823
808static int intel_i965_fetch_size(void) 824static int intel_i965_fetch_size(void)
809{ 825{
810 struct aper_size_info_fixed *values; 826 struct aper_size_info_fixed *values;
@@ -832,7 +848,8 @@ static int intel_i965_fetch_size(void)
832 848
833 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset); 849 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
834 850
835 return values[offset].size; 851 /* The i965 GTT is always sized as if it had a 512kB aperture size */
852 return 512;
836} 853}
837 854
838/* The intel i965 automatically initializes the agp aperture during POST. 855/* The intel i965 automatically initializes the agp aperture during POST.
@@ -1584,7 +1601,7 @@ static struct agp_bridge_driver intel_i965_driver = {
1584 .fetch_size = intel_i965_fetch_size, 1601 .fetch_size = intel_i965_fetch_size,
1585 .cleanup = intel_i915_cleanup, 1602 .cleanup = intel_i915_cleanup,
1586 .tlb_flush = intel_i810_tlbflush, 1603 .tlb_flush = intel_i810_tlbflush,
1587 .mask_memory = intel_i810_mask_memory, 1604 .mask_memory = intel_i965_mask_memory,
1588 .masks = intel_i810_masks, 1605 .masks = intel_i810_masks,
1589 .agp_enable = intel_i810_agp_enable, 1606 .agp_enable = intel_i810_agp_enable,
1590 .cache_flush = global_cache_flush, 1607 .cache_flush = global_cache_flush,
diff --git a/drivers/char/ftape/Kconfig b/drivers/char/ftape/Kconfig
deleted file mode 100644
index 0d65189a7ae8..000000000000
--- a/drivers/char/ftape/Kconfig
+++ /dev/null
@@ -1,330 +0,0 @@
1#
2# Ftape configuration
3#
4config ZFTAPE
5 tristate "Zftape, the VFS interface"
6 depends on FTAPE
7 ---help---
8 Normally, you want to say Y or M. DON'T say N here or you
9 WON'T BE ABLE TO USE YOUR FLOPPY TAPE DRIVE.
10
11 The ftape module itself no longer contains the routines necessary
12 to interface with the kernel VFS layer (i.e. to actually write data
13 to and read data from the tape drive). Instead the file system
14 interface (i.e. the hardware independent part of the driver) has
15 been moved to a separate module.
16
17 To compile this driver as a module, choose M here: the
18 module will be called zftape.
19
20 Regardless of whether you say Y or M here, an additional runtime
21 loadable module called `zft-compressor' which contains code to
22 support user transparent on-the-fly compression based on Ross
23 William's lzrw3 algorithm will be produced. If you have enabled the
24 kernel module loader (i.e. have said Y to "Kernel module loader
25 support", above) then `zft-compressor' will be loaded
26 automatically by zftape when needed.
27
28 Despite its name, zftape does NOT use compression by default.
29
30config ZFT_DFLT_BLK_SZ
31 int "Default block size"
32 depends on ZFTAPE
33 default "10240"
34 ---help---
35 If unsure leave this at its default value, i.e. 10240. Note that
36 you specify only the default block size here. The block size can be
37 changed at run time using the MTSETBLK tape operation with the
38 MTIOCTOP ioctl (i.e. with "mt -f /dev/qft0 setblk #BLKSZ" from the
39 shell command line).
40
41 The probably most striking difference between zftape and previous
42 versions of ftape is the fact that all data must be written or read
43 in multiples of a fixed block size. The block size defaults to
44 10240 which is what GNU tar uses. The values for the block size
45 should be either 1 or multiples of 1024 up to a maximum value of
46 63488 (i.e. 62 K). If you specify `1' then zftape's builtin
47 compression will be disabled.
48
49 Reasonable values are `10240' (GNU tar's default block size),
50 `5120' (afio's default block size), `32768' (default block size some
51 backup programs assume for SCSI tape drives) or `1' (no restriction
52 on block size, but disables builtin compression).
53
54comment "The compressor will be built as a module only!"
55 depends on FTAPE && ZFTAPE
56
57config ZFT_COMPRESSOR
58 tristate
59 depends on FTAPE!=n && ZFTAPE!=n
60 default m
61
62config FT_NR_BUFFERS
63 int "Number of ftape buffers (EXPERIMENTAL)"
64 depends on FTAPE && EXPERIMENTAL
65 default "3"
66 help
67 Please leave this at `3' unless you REALLY know what you are doing.
68 It is not necessary to change this value. Values below 3 make the
69 proper use of ftape impossible, values greater than 3 are a waste of
70 memory. You can change the amount of DMA memory used by ftape at
71 runtime with "mt -f /dev/qft0 setdrvbuffer #NUMBUFFERS". Each buffer
72 wastes 32 KB of memory. Please note that this memory cannot be
73 swapped out.
74
75config FT_PROC_FS
76 bool "Enable procfs status report (+2kb)"
77 depends on FTAPE && PROC_FS
78 ---help---
79 Optional. Saying Y will result in creation of a directory
80 `/proc/ftape' under the /proc file system. The files can be viewed
81 with your favorite pager (i.e. use "more /proc/ftape/history" or
82 "less /proc/ftape/history" or simply "cat /proc/ftape/history"). The
83 file will contain some status information about the inserted
84 cartridge, the kernel driver, your tape drive, the floppy disk
85 controller and the error history for the most recent use of the
86 kernel driver. Saying Y will enlarge the size of the ftape driver
87 by approximately 2 KB.
88
89 WARNING: When compiling ftape as a module (i.e. saying M to "Floppy
90 tape drive") it is dangerous to use ftape's /proc file system
91 interface. Accessing `/proc/ftape' while the module is unloaded will
92 result in a kernel Oops. This cannot be fixed from inside ftape.
93
94choice
95 prompt "Debugging output"
96 depends on FTAPE
97 default FT_NORMAL_DEBUG
98
99config FT_NORMAL_DEBUG
100 bool "Normal"
101 ---help---
102 This option controls the amount of debugging output the ftape driver
103 is ABLE to produce; it does not increase or diminish the debugging
104 level itself. If unsure, leave this at its default setting,
105 i.e. choose "Normal".
106
107 Ftape can print lots of debugging messages to the system console
108 resp. kernel log files. Reducing the amount of possible debugging
109 output reduces the size of the kernel module by some KB, so it might
110 be a good idea to use "None" for emergency boot floppies.
111
112 If you want to save memory then the following strategy is
113 recommended: leave this option at its default setting "Normal" until
114 you know that the driver works as expected, afterwards reconfigure
115 the kernel, this time specifying "Reduced" or "None" and recompile
116 and install the kernel as usual. Note that choosing "Excessive"
117 debugging output does not increase the amount of debugging output
118 printed to the console but only makes it possible to produce
119 "Excessive" debugging output.
120
121 Please read <file:Documentation/ftape.txt> for a short description
122 how to control the amount of debugging output.
123
124config FT_FULL_DEBUG
125 bool "Excessive"
126 help
127 Extremely verbose output for driver debugging purposes.
128
129config FT_NO_TRACE
130 bool "Reduced"
131 help
132 Reduced tape driver debugging output.
133
134config FT_NO_TRACE_AT_ALL
135 bool "None"
136 help
137 Suppress all debugging output from the tape drive.
138
139endchoice
140
141comment "Hardware configuration"
142 depends on FTAPE
143
144choice
145 prompt "Floppy tape controllers"
146 depends on FTAPE
147 default FT_STD_FDC
148
149config FT_STD_FDC
150 bool "Standard"
151 ---help---
152 Only change this setting if you have a special controller. If you
153 didn't plug any add-on card into your computer system but just
154 plugged the floppy tape cable into the already existing floppy drive
155 controller then you don't want to change the default setting,
156 i.e. choose "Standard".
157
158 Choose "MACH-2" if you have a Mountain Mach-2 controller.
159 Choose "FC-10/FC-20" if you have a Colorado FC-10 or FC-20
160 controller.
161 Choose "Alt/82078" if you have another controller that is located at
162 an IO base address different from the standard floppy drive
163 controller's base address of `0x3f0', or uses an IRQ (interrupt)
164 channel different from `6', or a DMA channel different from
165 `2'. This is necessary for any controller card that is based on
166 Intel's 82078 FDC such as Seagate's, Exabyte's and Iomega's "high
167 speed" controllers.
168
169 If you choose something other than "Standard" then please make
170 sure that the settings for the IO base address and the IRQ and DMA
171 channel in the configuration menus below are correct. Use the manual
172 of your tape drive to determine the correct settings!
173
174 If you are already successfully using your tape drive with another
175 operating system then you definitely should use the same settings
176 for the IO base, the IRQ and DMA channel that have proven to work
177 with that other OS.
178
179 Note that this menu lets you specify only the default setting for
180 the hardware setup. The hardware configuration can be changed at
181 boot time (when ftape is compiled into the kernel, i.e. if you
182 have said Y to "Floppy tape drive") or module load time (i.e. if you
183 have said M to "Floppy tape drive").
184
185 Please read also the file <file:Documentation/ftape.txt> which
186 contains a short description of the parameters that can be set at
187 boot or load time. If you want to use your floppy tape drive on a
188 PCI-bus based system, please read the file
189 <file:drivers/char/ftape/README.PCI>.
190
191config FT_MACH2
192 bool "MACH-2"
193
194config FT_PROBE_FC10
195 bool "FC-10/FC-20"
196
197config FT_ALT_FDC
198 bool "Alt/82078"
199
200endchoice
201
202comment "Consult the manuals of your tape drive for the correct settings!"
203 depends on FTAPE && !FT_STD_FDC
204
205config FT_FDC_BASE
206 hex "IO base of the floppy disk controller"
207 depends on FTAPE && !FT_STD_FDC
208 default "0"
209 ---help---
210 You don't need to specify a value if the following default
211 settings for the base IO address are correct:
212 <<< MACH-2 : 0x1E0 >>>
213 <<< FC-10/FC-20: 0x180 >>>
214 <<< Secondary : 0x370 >>>
215 Secondary refers to a secondary FDC controller like the "high speed"
216 controllers delivered by Seagate or Exabyte or Iomega's Ditto Dash.
217 Please make sure that the setting for the IO base address
218 specified here is correct. USE THE MANUAL OF YOUR TAPE DRIVE OR
219 CONTROLLER CARD TO DETERMINE THE CORRECT SETTING. If you are already
220 successfully using the tape drive with another operating system then
221 you definitely should use the same settings for the IO base that has
222 proven to work with that other OS.
223
224 Note that this menu lets you specify only the default setting for
225 the IO base. The hardware configuration can be changed at boot time
226 (when ftape is compiled into the kernel, i.e. if you specified Y to
227 "Floppy tape drive") or module load time (i.e. if you have said M to
228 "Floppy tape drive").
229
230 Please read also the file <file:Documentation/ftape.txt> which
231 contains a short description of the parameters that can be set at
232 boot or load time.
233
234config FT_FDC_IRQ
235 int "IRQ channel of the floppy disk controller"
236 depends on FTAPE && !FT_STD_FDC
237 default "0"
238 ---help---
239 You don't need to specify a value if the following default
240 settings for the interrupt channel are correct:
241 <<< MACH-2 : 6 >>>
242 <<< FC-10/FC-20: 9 >>>
243 <<< Secondary : 6 >>>
244 Secondary refers to secondary a FDC controller like the "high speed"
245 controllers delivered by Seagate or Exabyte or Iomega's Ditto Dash.
246 Please make sure that the setting for the IO base address
247 specified here is correct. USE THE MANUAL OF YOUR TAPE DRIVE OR
248 CONTROLLER CARD TO DETERMINE THE CORRECT SETTING. If you are already
249 successfully using the tape drive with another operating system then
250 you definitely should use the same settings for the IO base that has
251 proven to work with that other OS.
252
253 Note that this menu lets you specify only the default setting for
254 the IRQ channel. The hardware configuration can be changed at boot
255 time (when ftape is compiled into the kernel, i.e. if you said Y to
256 "Floppy tape drive") or module load time (i.e. if you said M to
257 "Floppy tape drive").
258
259 Please read also the file <file:Documentation/ftape.txt> which
260 contains a short description of the parameters that can be set at
261 boot or load time.
262
263config FT_FDC_DMA
264 int "DMA channel of the floppy disk controller"
265 depends on FTAPE && !FT_STD_FDC
266 default "0"
267 ---help---
268 You don't need to specify a value if the following default
269 settings for the DMA channel are correct:
270 <<< MACH-2 : 2 >>>
271 <<< FC-10/FC-20: 3 >>>
272 <<< Secondary : 2 >>>
273 Secondary refers to a secondary FDC controller like the "high speed"
274 controllers delivered by Seagate or Exabyte or Iomega's Ditto Dash.
275 Please make sure that the setting for the IO base address
276 specified here is correct. USE THE MANUAL OF YOUR TAPE DRIVE OR
277 CONTROLLER CARD TO DETERMINE THE CORRECT SETTING. If you are already
278 successfully using the tape drive with another operating system then
279 you definitely should use the same settings for the IO base that has
280 proven to work with that other OS.
281
282 Note that this menu lets you specify only the default setting for
283 the DMA channel. The hardware configuration can be changed at boot
284 time (when ftape is compiled into the kernel, i.e. if you said Y to
285 "Floppy tape drive") or module load time (i.e. if you said M to
286 "Floppy tape drive").
287
288 Please read also the file <file:Documentation/ftape.txt> which
289 contains a short description of the parameters that can be set at
290 boot or load time.
291
292config FT_FDC_THR
293 int "Default FIFO threshold (EXPERIMENTAL)"
294 depends on FTAPE && EXPERIMENTAL
295 default "8"
296 help
297 Set the FIFO threshold of the FDC. If this is higher the DMA
298 controller may serve the FDC after a higher latency time. If this is
299 lower, fewer DMA transfers occur leading to less bus contention.
300 You may try to tune this if ftape annoys you with "reduced data
301 rate because of excessive overrun errors" messages. However, this
302 doesn't seem to have too much effect.
303
304 If unsure, don't touch the initial value, i.e. leave it at "8".
305
306config FT_FDC_MAX_RATE
307 int "Maximal data rate to use (EXPERIMENTAL)"
308 depends on FTAPE && EXPERIMENTAL
309 default "2000"
310 ---help---
311 With some motherboard/FDC combinations ftape will not be able to
312 run your FDC/tape drive combination at the highest available
313 speed. If this is the case you'll encounter "reduced data rate
314 because of excessive overrun errors" messages and lots of retries
315 before ftape finally decides to reduce the data rate.
316
317 In this case it might be desirable to tell ftape beforehand that
318 it need not try to run the tape drive at the highest available
319 speed. If unsure, leave this disabled, i.e. leave it at 2000
320 bits/sec.
321
322config FT_ALPHA_CLOCK
323 int "CPU clock frequency of your DEC Alpha" if ALPHA
324 depends on FTAPE
325 default "0"
326 help
327 On some DEC Alpha machines the CPU clock frequency cannot be
328 determined automatically, so you need to specify it here ONLY if
329 running a DEC Alpha, otherwise this setting has no effect.
330
diff --git a/drivers/char/ftape/Makefile b/drivers/char/ftape/Makefile
deleted file mode 100644
index 0e67d2f8b7ec..000000000000
--- a/drivers/char/ftape/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
1#
2# Copyright (C) 1997 Claus Heine.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2, or (at your option)
7# any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; see the file COPYING. If not, write to
16# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17#
18# $Source: /homes/cvs/ftape-stacked/ftape/Makefile,v $
19# $Revision: 1.4 $
20# $Date: 1997/10/05 19:17:56 $
21#
22# Makefile for the QIC-40/80/3010/3020 floppy-tape driver for
23# Linux.
24#
25
26obj-$(CONFIG_FTAPE) += lowlevel/
27obj-$(CONFIG_ZFTAPE) += zftape/
28obj-$(CONFIG_ZFT_COMPRESSOR) += compressor/
diff --git a/drivers/char/ftape/README.PCI b/drivers/char/ftape/README.PCI
deleted file mode 100644
index 18de159d36e0..000000000000
--- a/drivers/char/ftape/README.PCI
+++ /dev/null
@@ -1,81 +0,0 @@
1Some notes for ftape users with PCI motherboards:
2=================================================
3
4The problem:
5------------
6
7There have been some problem reports from people using PCI-bus based
8systems getting overrun errors.
9I wasn't able to reproduce these until I ran ftape on a Intel Plato
10(Premiere PCI II) motherboard with bios version 1.00.08AX1.
11It turned out that if GAT (Guaranteed Access Timing) is enabled (?)
12ftape gets a lot of overrun errors.
13The problem disappears when disabling GAT in the bios.
14Note that Intel removed this setting (permanently disabled) from the
151.00.10AX1 bios !
16
17It looks like that if GAT is enabled there are often large periods
18(greater than 120 us !??) on the ISA bus that the DMA controller cannot
19service the floppy disk controller.
20I cannot imagine this being acceptable in a decent PCI implementation.
21Maybe this is a `feature' of the chipset. I can only speculate why
22Intel choose to remove the option from the latest Bios...
23
24The lesson of this all is that there may be other motherboard
25implementations having the same of similar problems.
26If you experience a lot of overrun errors during a backup to tape,
27see if there is some setting in the Bios that may influence the
28bus timing.
29
30I judge this a hardware problem and not a limitation of ftape ;-)
31My DOS backup software seems to be suffering from the same problems
32and even refuses to run at 1 Mbps !
33Ftape will reduce the data-rate from 1 Mbps to 500 Kbps if the number
34of overrun errors on a track exceeds a threshold.
35
36
37Possible solutions:
38-------------------
39
40Some of the problems were solved by upgrading the (flash) bios.
41Other suggest that it has to do with the FDC being on the PCI
42bus, but that is not the case with the Intel Premiere II boards.
43[If upgrading the bios doesn't solve the problem you could try
44a floppy disk controller on the isa-bus].
45
46Here is a list of systems and recommended BIOS settings:
47
48
49 Intel Premiere PCI (Revenge):
50
51Bios version 1.00.09.AF2 is reported to work.
52
53
54
55 Intel Premiere PCI II (Plato):
56
57Bios version 1.00.10.AX1 and version 11 beta are ok.
58If using version 1.00.08.AX1, GAT must be disabled !
59
60
61
62 ASUS PCI/I-SP3G:
63
64Preferred settings: ISA-GAT-mode : disabled
65 DMA-linebuffer-mode : standard
66 ISA-masterbuffer-mode : standard
67
68
69 DELL Dimension XPS P90
70
71Bios version A2 is reported to be broken, while bios version A5 works.
72You can get a flash bios upgrade from http://www.dell.com
73
74
75To see if you're having the GAT problem, try making a backup
76under DOS. If it's very slow and often repositions you're
77probably having this problem.
78
79 --//--
80 LocalWords: ftape PCI bios GAT ISA DMA chipset Mbps Kbps FDC isa AF ok ASUS
81 LocalWords: SP linebuffer masterbuffer XPS http www com
diff --git a/drivers/char/ftape/RELEASE-NOTES b/drivers/char/ftape/RELEASE-NOTES
deleted file mode 100644
index 03799dbc05a4..000000000000
--- a/drivers/char/ftape/RELEASE-NOTES
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@@ -1,966 +0,0 @@
1Hey, Emacs, we're -*-Text-*- mode!
2
3===== Release notes for ftape-3.04d 25/11/97 =====
4- The correct pre-processor statement for "else if" is "#elif" not
5 "elsif".
6- Need to call zft_reset_position() when overwriting cartridges
7 previously written with ftape-2.x, sftape, or ancient
8 (pre-ftape-3.x) versions of zftape.
9
10===== Release notes for ftape-3.04c 16/11/97 =====
11- fdc_probe() was calling DUMPREGS with a result length of "1" which
12 was just fine. Undo previous change.
13
14===== Release notes for ftape-3.04b 14/11/97 =====
15
16- patches/2.x.x/floppy.c.diff was somewhat broken, releasing i/o
17 regions it never had allocated.
18- fdc_probe() was calling DUMPREGS with a result length of "1" instead
19 of "10"
20- Writing deleted data marks if the first segents on track zero are
21 should work now.
22- ftformat should now be able to handle those cases where the tape
23 drive sets the read only status bit (QIC-40/80 cartridges with
24 QIC-3010/3020 tape drives) because the header segment is damaged.
25- the MTIOCFTCMD ioctl may now be issued by the superuser ONLY.
26
27===== Release notes for ftape-3.04a 12/11/97 =====
28- Fix an "infinite loop can't be killed by signal" bug in
29 ftape_get_drive_status(). Only relevant when trying to access
30 buggy/misconfigured hardware
31- Try to compensate a bug in the HP Colorado T3000's firmware: it
32 doesn't set the write protect bit for QIC80/QIC40 cartridges.
33
34===== Release notes for ftape-3.04 06/11/97 =====
35- If positioning with fast seeking fails fall back to a slow seek
36 before giving up.
37- (nearly) no retries on "no data errors" when verifying after
38 formatting. Improved tuning of the bad sector map after formatting.
39- the directory layout has changed again to allow for easier kernel
40 integration
41- Module parameter "ftape_tracing" now is called "ft_tracing" because
42 the "ftape_tracing" variable has the version checksum attached to it.
43- `/proc/ftape' interface for 2.0.* kernels. `/proc/ftape' no longer
44 is a directory but a file that contains all the information formerly
45 provided in separate files under the `/proc/ftape/' directory.
46- Most of the configuration options have been prefixed by "CONFIG_FT_"
47 in preparation of the kernel inclusion. The Makefiles under
48 "./ftape/" should be directly usable by the kernel.
49- The MODVERSIONS stuff is now auto-detected.
50- Broke backslashed multi line options in MCONFIG into separate lines
51 using GNU-make's "+=" feature.
52- The html and dvi version of the manual is now installed under
53 '/usr/doc/ftape` with 'make install`
54- New SMP define in MCONFIG. ftape works with SMP if this is defined.
55- attempt to cope with "excessive overrun errors" by gradually
56 increasing FDC FIFO threshold. But this doesn't seem to have too
57 much an effect.
58- New load time configuration parameter "ft_fdc_rate_limit". If you
59 encounter too many overrun errors with a 2Mb controller then you
60 might want to set this to 1000.
61- overrun errors on the last sector in a segment sometimes result in
62 a zero DMA residue. Dunno why, but compensate for it.
63- there were still fdc_read() timeout errors. I think I have fixed it
64 now, please FIXME.
65- Sometimes ftape_write() failed to re-start the tape drive when a
66 segment without a good sector was reached ("wait for empty segment
67 failed"). This is fixed. Especially important for > QIC-3010.
68- sftape (aka ftape-2.x) has vanished. I didn't work on it for
69 ages. It is probably still possible to use the old code with
70 ftape-3.04, if one really needs it (BUT RECOMPILE IT)
71- zftape no longer alters the contents of already existing volume
72 table entries, which makes it possible to fill in missing fields,
73 like time stamps using some user space program.
74- ./contrib/vtblc/ contains such a program.
75- new perl script ./contrib/scripts/listtape that list the contents of a
76 floppy tape cartridge parsing the output of "mt volinfo" + "mt fsf"
77- the MTWEOF implementation has changed a little bit (after I had a
78 look at amanda). Calling MTWEOF while the tape is still held open
79 after writing something to the tape now will terminate the current
80 volume, and start a new one at the current position.
81- the volume table maintained by zftape now is a doubly linked list
82 that grows dynamically as needed.
83
84 formatting floppy tape cartridges
85 ---------------------------------
86 * there is a new user space formatting program that does most of the
87 dirty work in user space (auto-detect, computing the sector
88 coordinates, adjusting time stamps and statistics). It has a
89 simple command line interface.
90 * ftape-format.o has vanished, it has been folded into the low level
91 ftape.o module, and the ioctl interface into zftape.o. Most of the
92 complicated stuff has been moved to user space, so there was no
93 need for a separate module anymore.
94 * there is a new ioctl MTIOCFTCMD that sends a bare QIC-117 command
95 to the tape drive.
96 * there is a new mmap() feature to map the dma buffers into user
97 space to be used by the user level formatting program.
98 * Formatting of yet unformatted or totally degaussed cartridges
99 should be possible now. FIXME.
100
101===== Release notes for ftape-3.03b, <forgot the exact date> ====
102
103ftape-3.03b was released as a beta release only. Its main new feature
104was support of the DITTO-2GB drive. This was made possible by reverse
105engineering done by <fill in his name> after Iomega failed to support
106ftape. Although they had promised to do so (this makes me feel a bit
107sad and uncomfortable about Iomega).
108
109===== Release notes for ftape-3.03a, 22/05/97 ====
110
111- Finally fixed auto-un-loading of modules for kernels > 2.1.18
112- Add an "uninstall" target to the Makefile
113- removed the kdtime hack
114- texi2www didn't properly set the back-reference from a footnote back
115 to the regular text.
116
117 zftape specific
118 ---------------
119 * hide the old compression map volume. Taper doesn't accept the
120 presence of non-Taper volumes and Taper-written volume on the same
121 tape.
122 * EOD (End Of Data) handling was still broken: the expected behavior
123 is to return a zero byte count at the first attempt to read past
124 EOD, return a zero byte count at the second attempt to read past
125 EOD and THEN return -EIO.
126
127 ftape-format specific
128 ---------------------
129 * Detection of QIC-40 cartridges in select_tape_format() was broken
130 and made it impossible to format QIC-3010/3020 cartridges.
131 * There are strange "TR-1 Extra" cartridges out there which weren't
132 detected properly because the don't strictly conform to the
133 QIC-80, Rev. N, spec.
134
135===== Release notes for ftape-3.03, 30/04/97 =====
136
137- Removed kernel integration code from the package. I plan to provide
138 a package that can be integrated into the stock kernel separately
139 (hopefully soon).
140 As a result, a simple `make' command now will build everything.
141- ALL compile time configuration options have been moved to the file
142 `MCONFIG'.
143- Quite a few `low level' changes to allow formatting of cartridges.
144- formatting is implemented as a separate module `ftape-format.o'. The
145 modified `mt' program contains sample code that shows how to use it.
146- The VFS interface has been moved from the `ftape.o' module to the
147 high level modules `zftape.o' resp. `sftape.o'. `ftape.o' contains
148 the hardware support only.
149- A bit of /proc support for kernels > 2.1.28
150- Moved documentation to Doc subdir. INSTALL now contains some real
151 installation notes.
152- `install' target in Makefile.
153
154zftape specific:
155----------------
156
157- zftape works for large cartridges now ( > 2^31 bytes)
158- MTIOCVOLINFO and MTIOCGETSIZE now return the size in KILOBYTES,
159 NO LONGER in bytes.
160
161- permissions for write access to a cartridge have changed:
162 * zftape now also takes the file access mode into account
163 * zftape no longer allows writing in the middle of the recorded
164 media. The tape has to be positioned at BOT or EOD for write
165 access.
166
167- MTBSF has changed. It used to position at the beginning of the
168 previous file when called with count 1. This was different from the
169 expected behavior for other Un*x tape drivers (i.e. SCSI). MTBSF
170 with count 1 should merely position at the beginning of the current
171 volume. Fixed. As a result, `tar --verify' now produces the desired
172 result: it verifies the last written volume, not the pre-last
173 written volume.
174
175- The compression map has vanished --> no need for `mt erase' any
176 more. Fast seeking in a compressed volume is still be possible, but
177 takes slightly longer. As a side effect, you may experience an
178 additional volume showing up in front of all others for old
179 cartridges. This is the tape volume that holds the compression map.
180
181- The compression support for zftape has been moved to a separate
182 module `zft-compressor'. DON'T forget to load it before trying to
183 read back compressed volumes. The stock `zftape.o' module probes for
184 the module `zft-compressor' using the kerneld message channel; you
185 have to install `zft-compressor.o' in a place where modprobe can
186 find it if you want to use this.
187
188- New experimental feature that tries to get the broken down GMT time
189 from user space via a kernel daemon message channel. You need to
190 compile and start the `kdtime' daemon contained in the contrib
191 directory to use it. Needed (?) for time stamps in the header
192 segments and the volume table.
193
194- variable block size mode via MTSETBLK 0
195
196- keep modules locked in memory after the block size has been changed
197
198sftape specific:
199----------------
200
201- end of tape handling should be fixed, i.e. multi volume archives
202 written with `afio' can be read back now.
203
204
205===== Release notes for ftape-3.02a, 09/01/97 =====
206
207No big news:
208- call zft_init() resp. sft_init() when compiling the entire stuff
209 into the kernel image.
210- fix bug in ftape-setup.c when NO_TRACE_AT_ALL was defined.
211- fix bug in sftape-eof.c/zftape-eof.c for old kernels (1.2.*)
212- add support for new module interface for recent kernels
213
214===== Release notes for ftape-3.02, 16/12/96 =====
215- Fixed the `FDC unlock command failed' bug in fdc-io.c. When the FIFO
216 was already locked when ftape was loaded, ftape failed to unlock it.
217- Fixed compilation of `contrib/gnumt'. It now finds `mtio.h' even if
218 ftape is NOT included into the kernel source tree.
219- fc-10.c: include <asm/io.h> for inb() and outb().
220- ftape/sftape/zftape: all global variable now have either a `ftape_',
221 a `ft_', `sft_', `zft_' or `qic_' prefix to prevent name clashes
222 with other parts of the kernel when including ftape into the kernel
223 source tree.
224- Kerneld support has changed. `ftape' now searches for a module
225 `ftape-frontend' when none of the frontend (`sftape' or `zftape') is
226 loaded. Please refer to the `Installation/Loading ftape' section of
227 the TeXinfo manual.
228- Add load resp. boot-time configuration of ftape. There are now
229 variables ft_fdc_base, ft_fdc_dma and ft_fdc_irq corresponding to
230 the former FDC_BASE etc. compile time definitions. One can also use
231 the kernel command line parameters to configure the driver if it is
232 compiled into the kernel. Also, the FC-10/FC-20 support is load-time
233 configurable now as well as the MACH-II hack (ft_probe_fc10,
234 resp. ft_mach2). Please refer to the section `Installation/Configure
235 ftape' of the TeXinfo manual.
236- I removed the MODVERSIONS option from `Makefile.module'. Let me alone
237 with ftape and MODVERSIONS unless you include the ftape sources into
238 the kernel source tree.
239- new vendors in `vendors.h':
240 * HP Colorado T3000
241 * ComByte DoublePlay (including a bug fix for their broken
242 formatting software, thanks to whraven@njackn.com)
243 * Iomega DITTO 2GIG. NOTE: this drive cannot work with ftape because
244 the logical data layout of the cartridges used by this drive does
245 NOT conform to the QIC standards, it is a special Iomega specific
246 format. I've sent mail to Iomega but didn't receive an answer
247 yet. If you want this drive to be supported by ftape, ask Iomega
248 to give me information about it.
249- zftape:
250 * re-introduced the MTIOC_ZFTAPE_GETBLKSZ ioctl for compatibility
251 with zftape 1.06a and earlier. Please don't use it when writing
252 new software, use the MTIOCVOLINFO ioctl instead.
253 * Major overhaul of the code that updates the header segments. Never
254 change the tape label unless erasing the tape. Thus we almost
255 never need to write the header segments, unless we would modify
256 the bad sector map which isn't done yet. Updating of volume table
257 and compression map more secure now although it takes a bit
258 longer.
259 * Fixed bug when aborting a write operation with a signal: zftape
260 now finishes the current volume (i.e. writes an eof marker) at the
261 current position. It didn't before which led to somehow *strange*
262 behavior in this cases.
263 * Keep module locked in memory when using it with the non-rewinding
264 devices and the tape is not logical at BOT. Needed for kerneld
265 support.
266- sftape:
267 * Keep module locked in memory when using it with the non-rewinding
268 devices and the tape is not logical at BOT. Needed for kerneld
269 support.
270
271===== Release notes for ftape-3.01, 14/11/96 =====
272
273- Fixed silly bugs in ftape-3.00:
274 * MAKEDEV.ftape: major device number must be 27, not 23
275 * sftape/sftape-read.c: sftape_read_header_segments() called
276 itself recursively instead of calling ftape_read_header_segment()
277 * zftape/qic-vtbl.h: conversion of ftape's file marks to zftape's
278 internal volume table was broken.
279 * patches/2.x.x/linux-2.0.21.dif: my RCS (resp. CVS) system replaced
280 the `$Revison:' etc. macros in the `ftape.h' concerning part of the
281 patch :-( Fixed.
282 * info/ftape.info: Fixed misspellings (`cp' <-> `cp -r' etc.)
283 * when ftape/sftape or ftape/zftape was compiled into the kernel the
284 variable ftape_status was declared twice. Fixed.
285 * removed reference to undeclared variable kernel_version when not
286 compiling as module
287 * fixed a bug introduced by the use of bit-fields for some flags
288 (i.e. write_protected, no_cartridge, formatted)
289 * flag `header_read' is now reset correctly to zero when tape is
290 removed.
291- fixed a bug in sftape/sftape-eof.c that was already in the original
292 ftape code. MTFSF/BSF was not handled correctly when positioned
293 right before the file mark (think of tar)
294- Changed TRACE macros (following a suggestion of Marcin Dalecki) to use
295 the predefined __FUNCTION__ macro of GCC. Spares about 4k of code.
296- added new vendor id for Iomega DITTO 2GIG
297- fixed a bug already present in zftape-1.06 when aborting a write
298 with a signal: we now finish the current volume at that
299 position. Header segments remain NOT up to date until an explicit call
300 to MTREW or MTOFFL is done.
301
302===== Release notes for ftape-3.00, 14/10/96 =====
303
304- Merged ftape with zftape. There are three modules now:
305 ftape for the hardware support, sftape for the implementation of the
306 original ftape eof mark stuff and zftape that implements zftape's way
307 of handling things (compression, volume table, tape blocks of
308 constant length)
309- Documentation in TeXinfo format in the `info' subdirectory.
310- New ioctls for zftape. See zftape/zftape.h
311- Dummy formatting ioctl for ftape. See ftape.h
312- Kernel patch files for the 2.*.* series to include ftape-3.00 in the
313 kernel source tree. These includes a kernel compatible Config.in
314 script and fairly large online information for the kernel configure
315 script.
316- Support for compiling with Linux-1.2.13.
317- Modified GNU mt from their cpio package that can handle the new
318 ioctls.
319- ftape/sftape/zftape is kerneld save now!
320
321Notes on sftape:
322- sftape implements the eof handling code of the original ftape. If
323 you like to stick with the original ftape stuff, you have to use
324 this module, not zftape.
325- sftape is kerneld save, unlike the original ftape.
326- we keep the entire header segment now in memory, so no need to read
327 it before updating the header segments. Additional memory
328 consumption: 256 bytes.
329
330Notes for zftape:
331- zftape has support for tapes with format code 6 now, which use a
332 slightly different volume table format compared with other floppy
333 tapes.
334- new ioctls for zftape. Have a look at zftape/zftape.h
335- The internal volume table representation has changed for zftape. Old
336 cartridges are converted automatically.
337- zftape no longer uses compression map segments, which have vanished
338 from the QIC specs, but creates volume table entry that reserves
339 enough space for the compression map.
340- zftape is kerneld save now.
341- we keep the entire header segment now in memory, so no need to read
342 it before updating the header segments. Additional memory
343 consumption: 256 bytes.
344
345Notes for contrib/gnumt:
346- modified mt from the GNU cpio package that supports all the new
347 ioctls of zftape.
348Notes for contrib/swapout:
349- This contains the swapout.c program that was written by Kai
350 Harrekilde-Pederson. I simply added a Makefile.
351
352===== Release notes for ftape-2.10, 14/10/96 =====
353
354The ftape maintainer has changed.
355Kai Harrekilde-Petersen <khp@dolphinics.no>
356has resigned from maintaining ftape, and I,
357Claus-Justus Heine <claus@momo.math.rwth-aachen.de>,
358have taken over.
359
360- Added support for tapes with `format code 6', i.e. QIC-3020 tapes
361 with more than 2^16 segments.
362- merged changes made by Bas Laarhoven with ftape-2.09. Refer
363 to his release notes below. I've included them into this
364 file unchanged for your reference.
365- disabled call stack back trace for now. This new feature
366 introduced by the interim release 2.0.x still seems to
367 be buggy.
368- Tried to minimize differences between the ftape version
369 to be included into the kernel source tree and the standalone
370 module version.
371- Reintroduced support for Linux-1.2.13. Please refer to the
372 Install-guide.
373
374===== Release notes for ftape-2.09, 16/06/96 =====
375
376There aren't any really big news in this release, mostly just that I
377(the maintainer) have changed my email address (due to a new job). My
378new address is <khp@dolphinics.no>
379
380- The CLK_48MHZ and FDC_82078SL options has gone (all 2Mbps cards seem
381 to use a 48MHz oscillator anyway and I haven't heard of an 'SL
382 chip out there).
383- The S82078B has been `downgraded' to i82077AA compability.
384- TESTING option revived. Right now, it'll enable the (seriously broken)
385 2Mbps code. If you enable it, you'll experience a tape drive that's
386 *really* out to lunch!
387- Some (bold) changes in the init code. Please notify me if they
388 break things for you.
389
390===== Release notes for ftape-2.08, 14/03/96 =====
391
392If you correct a problem with ftape, please send your patch to
393khp@dolphinics.no too.
394
395- Updated to reflect that NR_MEM_LISTS is gone in 1.3.74
396- Teac 700 added to list of known drives.
397- The registered device name is now "ft" rather than "ftape".
398
399===== Release notes for ftape-2.07a, 14/03/96 =====
400
401Bugfixes by Marcin Dalecki <dalecki@namu03.gwdg.de>:
402- In the last release it just compiled against 1.3.70;
403 now the params to request_irq() and free_irq are() are fixed, so it also
404 works in 1.3.73 :-)
405- Support for modules is now correct for newer kernels.
406
407===== Release notes for ftape-2.07, 04/03/96 =====
408
409
410- ftape updated to compile against 1.3.70.
411- Iomega 700 and Wangtek 3200 recognised.
412
413
414===== Release notes for ftape-2.06b, 13/02/96 =====
415
416Another simple bugfix version.
417
418- Jumbo 700 recognised.
419- Typo in vendors.h fixed.
420
421
422===== Release notes for ftape-2.06a, 10/02/96 =====
423
424This release is a simple bugfix version.
425
426- Linux/SMP: ftape *should* work.
427- FC-10/20: Only accepts IRQs 3-7, or 9. If IRQ 9, properly tell the card
428 to use IRQ 2. Thanks to Greg Crider (gcrider@iclnet.org) for finding and
429 locating this bug and testing the patch.
430- Insight drive recognised correctly again.
431- Motor-on wakeup version of the Iomega 250 drive added
432
433
434===== Release notes for ftape-2.06, 28/01/96 =====
435
436Special thanks go to Neal Friedman and Steven Sorbom for their
437help in producing and testing this release.
438
439I have continued to clean up the code, with an eye towards inclusion
440of ftape in Linus' official kernel (In fact, as I type this, I am
441running on a kernel with ftape support statically linked). I have
442test-compiled ftape against my 1.2.13 tree without problems.
443Hopefully, everything should be OK for the v1.2.x people.
444
445WARNING! Alan Cox has mailed me that ftape does *NOT* work with
446Linux/SMP. If you try to run ftape under Linux/SMP, it will cause a
447kernel deadlock (which is worse than a panic).
448
449- QIC-3020/TR-3: 1Mbps support works. Neal is capable of reading and
450 writing data to a tape. ftape will automatically detect the type of
451 tape (e.g. TR-3 vs QIC-80) and move the fdc in and out of
452 "perpendicular mode" as necessary.
453- 2Mbps support is disabled by default, since it is not fully
454 debugged. If you are adventurous, remove -DFDC_82078SL in the
455 Makefile and see what happens :-)
456- fdc detection: silly bugs removed (Only 2Mbps fdcs were affected)
457 and added detection of the National Semiconductors PC8744 fdc chip
458 (used in the PC873xx "super-IO" chips).
459- Removed warning about incompatible types when compiling with Linux
460 1.2.x.
461- README.PCI updated with info about the DELL Dimension XPS P90.
462- Connor TST3200R added to detected drives.
463- `swapout' utility added to distribution. It will dirty 5Meg of
464 memory, trying to swap out other programs. Just say `make swapout'
465 to build it. ftape will do this automatically Real Soon Now (ie:
466 when I have found out which kernel memory alloc function to call).
467
468
469===== Release notes for ftape-2.05, 08/01/96 =====
470
471- For v1.2.x Kernels, you must apply the patch linux-1.2/ksyms.patch to
472 the kernel and rebuild it (it adds the __get_dma_pages symbol to
473 ksyms.c).
474- Included new asm-i386/io.h file from v1.3.x kernel series, to enable
475 gcc v.2.7.[12] to compile v1.2.x kernels (linux-1.2/io.h).
476- Module versions: If you wish to compile ftape as a versioned module,
477 you must first compile your kernel with CONFIG_MODVERSIONS=y.
478 Otherwise, you will get complaints that <linux/modversions.h> does not
479 exist (if that happens, a `touch modversions.h' will help you out).
480- CLK_48MHZ: new define in the Makefile (default: non-zero). If you have
481 a tape controller card that uses the i82078(-1) chip, but cannot get
482 it to work with ftape, try set it to 0 (and please report this).
483- QIC-3010/3020: Complete support is still missing, but will hopefully
484 come soon. Steven Sorbom has kindly provided me with hints about
485 this. Writing of QIC-3020 tapes definitely does NOT work (do not try
486 it! - the drive will not be in "perpendicular mode" and this will ruin
487 the formatting info on the tape).
488- ftape_num_buffers is out of fashion: use NR_BUFFERS instead (and
489 recompile if you want to change it :-).
490
491
492===== Release notes for ftape-2.04, 01/01/96 =====
493
494This version by Kai Harrekilde-Petersen <khp@dolphinics.no>
495
496- ALERT! Support for Kernels earlier then v1.1.85 is about to go away.
497 I intend to clean up some of the code (getting rid of an annoyingly
498 large numbers of #ifdef mostly), which means that support for
499 pre-1.1.85 kernels must go as well.
500- NR_FTAPE_BUFFERS is gone; You can instead select the number of dma
501 buffers by saying `insmod ftape.o ftape_num_buffer=<n>' instead.
502- Configure script gone. ftape will now automagically determine your
503 kernel version by /usr/include/linux/version.h instead.
504- CONFIG_MODVERSIONS now work. All combinations of versioned /
505 unversioned kernel and ftape module works (at least with my 1.3.52
506 kernel).
507- If you have problems with inserting ftape into an old (1.2.x)
508 kernel (e.g. insmod says "1.2.8 does not match 1.2.8), recompile
509 your modules utilities with your new compiler.
510- Reveal TB1400 drive added to vendors.h
511- Support for the i82078-1 (2Mbps) chip is coming along. The
512 biggest problem is that I don't have such a card, which makes
513 testing / debugging somewhat problematic. The second biggest
514 problem is that I do not have the QIC-3010/3020 standards either.
515 Status right now is that the chip is detected, and it should be
516 possible to put it into 2Mbps mode. However, I do not know what
517 "extras" are needed to complete the support. Although putting the
518 i82078 into 1Mbps mode ought to work out of the box, it doesn't
519 (right now, ftape complains about id am errors).
520
521
522===== Release notes for ftape-2.04beta5, 29/12/95 =====
523
524Bas offline linux-tape
525----------------------
526For reasons only known to the majordomo mail list processor, Bas was
527kicked off the linux-tape list sometime during the summer. Being
528overworked at his for-pay job, he didn't notice it much. Instead I
529(Kai, khp@dolphinics.no) has worked on ftape to produce the 2.04(beta)
530version.
531
532zftape
533------
534Note that there exists a much improved version of ftape, written by
535Claus-Justus Heine <claus@willi.math.rwth-aachen.de> which is named
536zftape, which conforms to the QIC-80 specs on how to mark backups, and
537is capable of doing automatic compression. However, zftape makes
538substantial changes to ftape, and I (Kai) have therefore declined to
539integrate zftape into ftape. Hopefully, this will happen soon.
540
541CONFIG_QIC117 removed from the kernel
542-------------------------------------
543The biggest change of all is that ftape now will allocate its dma
544buffers when it is inserted. The means that the CONFIG_QIC117 option
545has disappeared from the Linux kernel as of v1.3.34. If you have an
546earlier kernel, simply answer 'no' to the question will do the trick
547(if you get complains about __get_free_pages() missing, contact the
548linux-tape mailing list).
549
550Note that ftape-2.04beta will work equally well on kernels with and
551without `ftape support'. The only catch is, that you will waste
552around 96-128Kb of precious DMA'able memory on a box that has ftape
553support compiled in.
554
555Now for the real changes:
556
557- FC-20 can now use DMA channels 1, 2, and 3. Thanks to Daniel
558 Cohen, catman@wpi.edu.
559- ftape no longer requires a (gigantic) 96Kb buffer to be statically
560 allocated by the kernel.
561- Added new Iomega drive (8882) to vendors.h
562- -fno-strength-reduce added to Makefile, since GCC is broken.
563- i82078-1 (2Mbps) FDC support started.
564
565
566===== Release notes for ftape-2.03b, 27/05/95 =====
567
568- Prevented verify_area to return error if called with zero length.
569- Fixed a bug in flush_buffers that caused too much padding to be
570 written when a final segment had bad sectors.
571- Increased maximum fast-seek overshoot value from 5 to 10 segments.
572- Breaking loop after 5 retries when positioning fails.
573- Fixed wrong calculation of tape length for QIC-3010 and QIC-3020
574 tapes (densities were swapped).
575- Fixed wrong calculation of overshoot on seek_forward: Wrong sign
576 of error.
577- Suppress (false) error message due to new tape loaded.
578- Added two new CMS drives (11c3 and 11c5) to vendors.h.
579
580
581===== Release notes for ftape-2.03a, 09/05/95 =====
582
583- Fixed display of old error (even if already cleared) in ftape_open.
584- Improved tape length detection, ioctls would fail for 425 ft tapes.
585 Until the tape length is calculated with data from the header
586 segment, we'll use worst-case values.
587- Clear eof_mark after rewinding ioctls.
588- Fixed wrong version message (2.03 had 2.02g id).
589- Fixed bug that caused the fdc to be reset very frequently.
590 This shouldn't affect normal operation but the timing of the
591 report routines has changed again and that may cause problems.
592 We'll just have to find out....
593- Implemented correct write precompensation setting for QIC-3010/3020.
594- Cleaned up fdc_interrupt_wait routine. Hope it still works :-)
595- Finally removed (already disabled) special eof mark handling for
596 gnu tar.
597- Changed order of get_dma_residue and disable_dma in fdc-isr.c
598 because the current order would fail on at least one system.
599 We're back to the original order again, hope (and expect) this
600 doesn't break any other system.
601
602
603===== Release notes for ftape-2.03, 07/05/95 =====
604
605(Changes refer to the first ftape-2.02 release)
606
607Support for wide and extended length tapes
608------------------------------------------
609The Conner TSM 420 and 850 drives are reported to be working.
610I haven't received any reports about other brands; the TSM 420
611and 850 seem to be the most widely used wide drives.
612Extended length tapes (425 ft) with normal QIC-80 drives
613are operating too (At least I've had no reports stating otherwise).
614_Not_ yet completely supported (although they may work) are
615QIC-3020 drives and 2 Mbps floppy disk controllers won't work at
616the highest speed.
617If someone is kind enough to send me one of these, I'll include
618support for it too ;-)
619
620Easier configuration
621--------------------
622Problems due to wrong settings in the Makefile are prevented
623by using a configuration script that sets the necessary (kernel
624version dependent) compile time options.
625This kernel version is now determined from the sources found
626at /usr/src/linux, or if not found, the old way using
627/proc/version.
628Versioned modules will be used automatically when supported
629by- and configured in- the kernel.
630Note that the current modules code (1.1.87) is still broken
631and _needs_ the fix included in the insmod directory.
632Please don't send me any more Oops reports caused by insmod :-(
633
634Reduced module size
635-------------------
636The standard module size is much reduced and some compile time
637options can even reduce it further. (I don't recommend this
638for normal use but it can be handy for rescue diskettes)
639
640Option: Approx. module size:
641
642<standard> 150 Kb
643NO_TRACE 125 Kb
644NO_TRACE_AT_ALL 67 Kb
645
646
647Much improved driver interruption
648---------------------------------
649Most possible loops have been broken and signal detection
650has been improved.
651In most cases the driver can be aborted by ^C (SIGINT) and
652SIGKILL (kill -9) will generate be a sure kill.
653(Note that aborting a tape operation may damage the last
654data written to tape)
655
656Improved error recovery
657-----------------------
658Ftape now returns an error (ENODATA) to the application if
659a segment proves to be unrecoverable and then skips the
660bad segment.
661This causes most applications to continue to work (tar
662and afio) loosing only a small amount (up to 29 Kb) of data.
663Retried read operations will now be done slightly off-track
664to improve the chance of success. Serious head off-track
665errors will be detected.
666
667FC-10 and FC-20 controllers
668---------------------------
669Ftape now supports both the old CMS FC-10 and the newer FC-20
670controllers.
671Because the operation of these cards is still undocumented,
672thus far they will only work with the default settings (See
673Makefile). Any feed-back on how to use them with other settings
674will be welcome !
675Compilation will fail if one changes the settings to illegal
676values.
677
678Kernels and compilers
679---------------------
680Ftape is currently being developed using the 2.5.8 compiler.
681The older 2.4.5 probably works too (Set option in Makefile!).
682I have no experience with any later compilers nor Elf support.
683Any information on this is welcome.
684The latest kernel I have tested ftape with is 1.2.6.
685
686Compression
687-----------
688An impressive collection of changes for ftape including
689on-the-fly compression is still lying on my desk.
690If 2.03 proves to be reliable I might start integrating these
691but as usual, I'm short in time :-(
692
693Formatting
694----------
695There is still no way to format tapes under Linux. As far as
696I know all attempts to write such a program have died now.
697Since formatted tapes are rather common now, I think all we
698need is a utility that writes a worst case pattern and verifies
699that with the drive put in verify mode, reducing margins.
700Any takers ?
701
702Furthermore
703-----------
704Cleaned up messages.
705Prepared to support multiple tape drives on one fdc.
706Thanks to all the people who sent bug reports and helped me
707improve the driver. Without trying to be complete I'll mention
708Gary Anderson (without his accurate reports and unreliable
709hardware there wouldn't be a 2.03), Stefan Kneifel (FC-20),
710Robert Broughton (FC-20, you were almost there ;-), Bjorn
711Ekwall (for the versioned modules and buggy insmod ;-), Peter
712Fox, Christopher Oliver, Ralph Whittaker and not the least
713Linus Torvalds (for Linux and keeping me busy because of
714changes to the kernel ;-)
715Thanks to anyone I forgot, for the bug reports, the ftape
716bashing and the mental support...
717
718
719That's it for now. Have Fun,
720
721Bas.
722
723
724===== Release notes for ftape-2.02g, 06/05/95 =====
725
726- Added extra test to break read-id loop with signal.
727- Changed rewind code to handle negative overshoot for drives
728 that take very long to start or stop.
729- Let use of get/set i/o-regions depend on kernel version.
730- Changed code to use a more general test for conditional
731 compilations depending on kernel version.
732- Improved micro-step functionality to go off-track only
733 while reading (id & data).
734- Added failure on tape-not-referenced bit in ftape_command.
735- Added FOREVER option to read-wait routine.
736- Changed read-id to use shorter timeout causing smaller
737 rewinds on timeout.
738- Made kernel-interface functions static.
739
740
741===== Release notes for ftape-2.02f, 03/05/95 =====
742
743- Added support for dual tape drives on my system, extended Configure
744 script to detect host 'dodo'.
745- Log media defect in history if ecc failed and no data was returned.
746- Fixed Configure script that was failing for kernel versions with
747 double digit version or revision numbers.
748
749
750===== Release notes for ftape-2.02e, 01/05/95 =====
751
752- Fixed reposition loop at logical eot (failing read_id).
753- Fixed 34 segment offset when rewinding.
754- Added fast seek capability for more than 255 segments.
755- Fixed wrong busy result from ftape_command causing reverse
756 seek to fail.
757- Added breakout from infinite rewind loop (if something fails).
758
759
760===== Release notes for ftape-2.02d, 30/04/95 =====
761
762- Improved abortion on signals: Interrupt will make a graceful
763 exit, Kill will be less nice and should be used if everything
764 else fails.
765- Included check for tape-head off track.
766- Implemented exit from tape-start loop.
767- Added kernel io-port registration.
768- Implemented skip of failing segment (ENODATA) on ecc failure.
769 This allows afio and tar to continue when the tape is damaged.
770- Made distinction between drive names with different codes.
771
772
773===== Release notes for ftape-2.02c, 22/04/95 =====
774
775- Fixed too tight command queueing after tape stop/pause command
776 issued from within interrupt service routine (Showed as timeout
777 on Acknowledge errors during retries on some systems)
778- Tried to fix timeouts when using 425 ft tape because the extended
779 length doesn't seem to be detected by the hardware.
780 We now use the format code from the header segment so adjust the
781 timing after reading the header segment.
782- Fixed some messages stating 'unexpected something...' being not
783 unexpected anymore.
784- Started preparations for merge of dynamic buffer allocation and
785 compression code.
786- Changed some debug messages to include relevant segment information
787 at level 4.
788- Included early bail-out when drive offline, preventing a lot of
789 false messages.
790- Moved ftape_parameter_xxx() offsets into function instead of in calls.
791- Removed 'weird, drive busy but no data' error when caused by
792 an error during a read-id.
793- Improved 'timeout on acknowledge' diagnostics.
794- Moved MODULE option into Configure.
795- Reduced code size when no tracing at all was set (Claus Heine).
796- No longer log error code 0 (no error) as an error.
797
798
799===== Release notes for ftape-2.02b, 09/04/95 =====
800
801- Relaxed timing for status operation and displaying
802 abnormal results. Hopefully this shows what's going
803 wrong with the Conner TSM850R drives.
804- Created script for configuration, using version number
805 of kernel source if available, otherwise /proc/version.
806- Fixed conditionals in kernel-interface.c.
807- Removed unavoidable TRACE output.
808
809
810===== Release notes for ftape-2.02a, 01/04/95 =====
811
812- Implemented `new-style' (versioned) modules support for new
813 kernels.
814- Reduced size of module by moving static data to bss.
815- Now using version number of kernel source instead of running
816 kernel for kernel versions >= 1.1.82
817- Added feedback on drive speeds to vendor information.
818- Included fixed insmod sources to distribution (Let's hope
819 the modules distribution get fixed soon :-/).
820
821Note that I haven't yet implemented any of the code extension I
822received. I hope to find some time to do this soon.
823
824
825===== Release notes for ftape-2.02, 15/01/95 =====
826
827
828- Fixed failing repositioning when overshoot was incremented.
829- Fixed rate selection: Because of a deficiency in the QIC-117
830 specification one cannot distinguish between a not implemented
831 and a failing command. Therefor we now try to find out if the
832 drive does support this command before usage.
833- Fixed error retry using wrong offset in fdc-isr.
834- Improved retry code to retry only once on a single no-data
835 error in a segment.
836- Validate sector number extracted from eof mark because an
837 invalid file mark (due to ???) could cause kernel panic.
838- Split ftape-io.c into ftape-io.c and ftape-ctl.c files.
839- Corrected too high media error count after writing to
840 a bad tape.
841- Added #include <asm/segment.h> again because old kernel versions
842 need it.
843- Fixed fdc not being disabled when open failed because no tape
844 drive was found.
845- Fixed problem with soft error in sector 32 (shift operator with
846 shiftcount 32 is not defined).
847
848
849===== Release notes for ftape-2.01, 08/01/95 =====
850
851
852- Removed TESTING setting from distributed Makefile.
853- Fixed `mt asf' failure: Rewind was deferred to close which
854 overruled the fsf ioctl.
855- Prevented non-interruptible commands being interrupted.
856- Added missing timeout.pause setting.
857- Maximum tape speed read from drive type information table.
858 If the information is not in the table (0) the drive will
859 determine the speed itself and put a message in the logfile.
860 This information should then be added to the table in the
861 vendors.h file (and reported to me).
862- Added call to ftape_init_drive after soft reset for those
863 (antique) drives that don't do an implicit seek_load_point
864 after a reset or power up.
865- Don't try to set data rate if reset failed.
866- Prevent update of seek variables when starting from the
867 beginning or the end of the tape.
868- Fixed wrong adjustment of overshoot in seek_forward().
869- Added sync to Makefile (again).
870- Added code to diagnose timer problems (calibr.c).
871- Replaced time differences by timediff calls.
872- Removed reference to do_floppy from object for recent kernels.
873- Fixed wrong display of 'failing dma controller' message.
874- Removed various no longer used #include statements.
875- Added max. tape speed value to vendor-struct.
876- Changed ftape-command to check pre-conditions and wait
877 if needed.
878- Further updated qic117.h to rev G.
879- Combined command name table and restrictions table to one.
880 Extended this table with some new fields.
881- Increased timeout on Ack timer value and included code to
882 report out of spec behaviour.
883- Increased rewind timeout margin to calculated + 20%.
884- Improved data rate selection so it won't fail on some
885 older (pre standard) drives.
886- Changed initialisation code so drive will be rewound if the
887 driver is reloaded and the tape is not at bot.
888- Moved some of the flush operations from close to the ioctls.
889- Added exit code value to failing verify area message.
890- Loop until tape halted in smart-stop.
891- Fast seek handled specially if located at bot or eot.
892- Being more conservative on overshoot value.
893
894
895===== Release notes for ftape-2.00, 31/12/94 =====
896
897 The Install-guide is completely rewritten and now also includes
898some information on how to use the driver. If you're either new
899to ftape or new to Unix tape devices make sure to read it !
900
901 If you own a pci system and experience problems with the
902ftape driver make sure to read the README.PCI file. It contains
903some hints on how to fix your hardware.
904
905 For anybody who hasn't noticed: The version number of the
906driver has been incremented (The latest released version has
907been version 1.14d).
908 This has been done for two major reasons:
909
910 o A new (better) error recovery scheme is implemented.
911 o Support for new drive types has been added.
912
913 All these improvements/changes will probably include a couple
914of new (and old?) bugs. If you encounter any problems that you think
915I'm not yet aware of, feel free to send a report to <bas@vimec.nl>.
916 I recommend keeping a version of ftape-1.14d available, just
917in case ;-)
918
919 This version should work with all kernel versions from 1.0.9 up
920to 1.1.72 (and probably earlier and later versions too).
921
922
923Major new features:
924
925- Better handling of tapes with defects: When a sector repeatedly
926 (SOFT_RETRIES in ftape.h) cannot be written to or read from it is
927 marked as an hard error and gets skipped.
928 The error correction code can handle up to three of these hard
929 errors provided there are no other errors in that segment (32 Kb).
930
931- Allows writing to tapes with defects (although the risk of loosing
932 data increases !)
933 Look for the media-defects entry printed with the statistics when
934 the tape is closed. A non-zero value here shows a bad tape.
935 [the actual count is wrong (too high), this is a known bug].
936
937- Use of backup header segment if first one is failing.
938
939- Support for extended length tapes with QIC-80: both 425 and 1100 ft.
940 0.25 inch tapes are now recognized and handled.
941
942- Support for new QIC-80 drives with 8 mm `wide' tapes (e.g. Conner
943 TSM 420).
944
945- Support for new QIC-3010 and QIC-3020 drives (experimental) with
946 both 0.25 inch and 8 mm tapes.
947
948Some minor features were added, a couple of small bugs were fixed and
949probably some new ones introduced ;-).
950
951[lseek() didn't make it into this version]
952
953Have fun,
954
955Bas.
956----
957 LocalWords: ftape MCONFIG mt VFS zftape resp sftape proc subdir MTIOCVOLINFO
958 LocalWords: MTIOCGETSIZE BOT EOD MTBSF zft kerneld modprobe kdtime contrib TR
959 LocalWords: MTSETBLK afio uninstall texi www EIO QIC init sft eof aka dma GB
960 LocalWords: SIGKILL MTIOCFTCMD mmap Iomega FDC fdc io gnumt mtio fc asm inb
961 LocalWords: outb ft qic frontend TeXinfo irq mach MODVERSIONS CONFIG html dvi
962 LocalWords: usr doc SMP Mb Dunno FIXME vtblc perl listtape volinfo fsf MTWEOF
963 LocalWords: amanda degaussed ComByte DoublePlay whraven njackn com MTIOC vtbl
964 LocalWords: GETBLKSZ MAKEDEV zftape's linux dif CVS Revison cp MTREW MTOFFL
965 LocalWords: MTFSF BSF Marcin Dalecki GCC Config cpio swapout Kai Harrekilde
966 LocalWords: Pederson khp dolphinics Justus claus momo rwth aachen Laarhoven
diff --git a/drivers/char/ftape/compressor/Makefile b/drivers/char/ftape/compressor/Makefile
deleted file mode 100644
index 1fbd6c4019db..000000000000
--- a/drivers/char/ftape/compressor/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
1#
2# Copyright (C) 1997 Claus-Justus Heine.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2, or (at your option)
7# any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; see the file COPYING. If not, write to
16# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17#
18# $Source: /homes/cvs/ftape-stacked/ftape/compressor/Makefile,v $
19# $Revision: 1.1 $
20# $Date: 1997/10/05 19:12:28 $
21#
22# Makefile for the optional compressor for th zftape VFS
23# interface to the QIC-40/80/3010/3020 floppy-tape driver for
24# Linux.
25#
26
27obj-$(CONFIG_ZFT_COMPRESSOR) += zft-compressor.o
28
29zft-compressor-objs := zftape-compress.o lzrw3.o
30
31CFLAGS_lzrw3.o := -O6 -funroll-all-loops
diff --git a/drivers/char/ftape/compressor/lzrw3.c b/drivers/char/ftape/compressor/lzrw3.c
deleted file mode 100644
index a032a0ee2a99..000000000000
--- a/drivers/char/ftape/compressor/lzrw3.c
+++ /dev/null
@@ -1,743 +0,0 @@
1/*
2 * $Source: /homes/cvs/ftape-stacked/ftape/compressor/lzrw3.c,v $
3 * $Revision: 1.1 $
4 * $Date: 1997/10/05 19:12:29 $
5 *
6 * Implementation of Ross Williams lzrw3 algorithm. Adaption for zftape.
7 *
8 */
9
10#include "../compressor/lzrw3.h" /* Defines single exported function "compress". */
11
12/******************************************************************************/
13/* */
14/* LZRW3.C */
15/* */
16/******************************************************************************/
17/* */
18/* Author : Ross Williams. */
19/* Date : 30-Jun-1991. */
20/* Release : 1. */
21/* */
22/******************************************************************************/
23/* */
24/* This file contains an implementation of the LZRW3 data compression */
25/* algorithm in C. */
26/* */
27/* The algorithm is a general purpose compression algorithm that runs fast */
28/* and gives reasonable compression. The algorithm is a member of the Lempel */
29/* Ziv family of algorithms and bases its compression on the presence in the */
30/* data of repeated substrings. */
31/* */
32/* This algorithm is unpatented and the code is public domain. As the */
33/* algorithm is based on the LZ77 class of algorithms, it is unlikely to be */
34/* the subject of a patent challenge. */
35/* */
36/* Unlike the LZRW1 and LZRW1-A algorithms, the LZRW3 algorithm is */
37/* deterministic and is guaranteed to yield the same compressed */
38/* representation for a given file each time it is run. */
39/* */
40/* The LZRW3 algorithm was originally designed and implemented */
41/* by Ross Williams on 31-Dec-1990. */
42/* */
43/* Here are the results of applying this code, compiled under THINK C 4.0 */
44/* and running on a Mac-SE (8MHz 68000), to the standard calgary corpus. */
45/* */
46/* +----------------------------------------------------------------+ */
47/* | DATA COMPRESSION TEST | */
48/* | ===================== | */
49/* | Time of run : Sun 30-Jun-1991 09:31PM | */
50/* | Timing accuracy : One part in 100 | */
51/* | Context length : 262144 bytes (= 256.0000K) | */
52/* | Test suite : Calgary Corpus Suite | */
53/* | Files in suite : 14 | */
54/* | Algorithm : LZRW3 | */
55/* | Note: All averages are calculated from the un-rounded values. | */
56/* +----------------------------------------------------------------+ */
57/* | File Name Length CxB ComLen %Remn Bits Com K/s Dec K/s | */
58/* | ---------- ------ --- ------ ----- ---- ------- ------- | */
59/* | rpus:Bib.D 111261 1 55033 49.5 3.96 19.46 32.27 | */
60/* | us:Book1.D 768771 3 467962 60.9 4.87 17.03 31.07 | */
61/* | us:Book2.D 610856 3 317102 51.9 4.15 19.39 34.15 | */
62/* | rpus:Geo.D 102400 1 82424 80.5 6.44 11.65 18.18 | */
63/* | pus:News.D 377109 2 205670 54.5 4.36 17.14 27.47 | */
64/* | pus:Obj1.D 21504 1 13027 60.6 4.85 13.40 18.95 | */
65/* | pus:Obj2.D 246814 1 116286 47.1 3.77 19.31 30.10 | */
66/* | s:Paper1.D 53161 1 27522 51.8 4.14 18.60 31.15 | */
67/* | s:Paper2.D 82199 1 45160 54.9 4.40 18.45 32.84 | */
68/* | rpus:Pic.D 513216 2 122388 23.8 1.91 35.29 51.05 | */
69/* | us:Progc.D 39611 1 19669 49.7 3.97 18.87 30.64 | */
70/* | us:Progl.D 71646 1 28247 39.4 3.15 24.34 40.66 | */
71/* | us:Progp.D 49379 1 19377 39.2 3.14 23.91 39.23 | */
72/* | us:Trans.D 93695 1 33481 35.7 2.86 25.48 40.37 | */
73/* +----------------------------------------------------------------+ */
74/* | Average 224401 1 110953 50.0 4.00 20.17 32.72 | */
75/* +----------------------------------------------------------------+ */
76/* */
77/******************************************************************************/
78
79/******************************************************************************/
80
81/* The following structure is returned by the "compress" function below when */
82/* the user asks the function to return identifying information. */
83/* The most important field in the record is the working memory field which */
84/* tells the calling program how much working memory should be passed to */
85/* "compress" when it is called to perform a compression or decompression. */
86/* LZRW3 uses the same amount of memory during compression and decompression. */
87/* For more information on this structure see "compress.h". */
88
89#define U(X) ((ULONG) X)
90#define SIZE_P_BYTE (U(sizeof(UBYTE *)))
91#define SIZE_WORD (U(sizeof(UWORD )))
92#define ALIGNMENT_FUDGE (U(16))
93#define MEM_REQ ( U(4096)*(SIZE_P_BYTE) + ALIGNMENT_FUDGE )
94
95static struct compress_identity identity =
96{
97 U(0x032DDEA8), /* Algorithm identification number. */
98 MEM_REQ, /* Working memory (bytes) required. */
99 "LZRW3", /* Name of algorithm. */
100 "1.0", /* Version number of algorithm. */
101 "31-Dec-1990", /* Date of algorithm. */
102 "Public Domain", /* Copyright notice. */
103 "Ross N. Williams", /* Author of algorithm. */
104 "Renaissance Software", /* Affiliation of author. */
105 "Public Domain" /* Vendor of algorithm. */
106};
107
108LOCAL void compress_compress (UBYTE *,UBYTE *,ULONG,UBYTE *, LONG *);
109LOCAL void compress_decompress(UBYTE *,UBYTE *,LONG, UBYTE *, ULONG *);
110
111/******************************************************************************/
112
113/* This function is the only function exported by this module. */
114/* Depending on its first parameter, the function can be requested to */
115/* compress a block of memory, decompress a block of memory, or to identify */
116/* itself. For more information, see the specification file "compress.h". */
117
118EXPORT void lzrw3_compress(
119 UWORD action, /* Action to be performed. */
120 UBYTE *wrk_mem, /* Address of working memory we can use.*/
121 UBYTE *src_adr, /* Address of input data. */
122 LONG src_len, /* Length of input data. */
123 UBYTE *dst_adr, /* Address to put output data. */
124 void *p_dst_len /* Address of longword for length of output data.*/
125)
126{
127 switch (action)
128 {
129 case COMPRESS_ACTION_IDENTITY:
130 *((struct compress_identity **)p_dst_len)= &identity;
131 break;
132 case COMPRESS_ACTION_COMPRESS:
133 compress_compress(wrk_mem,src_adr,src_len,dst_adr,(LONG *)p_dst_len);
134 break;
135 case COMPRESS_ACTION_DECOMPRESS:
136 compress_decompress(wrk_mem,src_adr,src_len,dst_adr,(LONG *)p_dst_len);
137 break;
138 }
139}
140
141/******************************************************************************/
142/* */
143/* BRIEF DESCRIPTION OF THE LZRW3 ALGORITHM */
144/* ======================================== */
145/* The LZRW3 algorithm is identical to the LZRW1-A algorithm except that */
146/* instead of transmitting history offsets, it transmits hash table indexes. */
147/* In order to decode the indexes, the decompressor must maintain an */
148/* identical hash table. Copy items are straightforward:when the decompressor */
149/* receives a copy item, it simply looks up the hash table to translate the */
150/* index into a pointer into the data already decompressed. To update the */
151/* hash table, it replaces the same table entry with a pointer to the start */
152/* of the newly decoded phrase. The tricky part is with literal items, for at */
153/* the time that the decompressor receives a literal item the decompressor */
154/* does not have the three bytes in the Ziv (that the compressor has) to */
155/* perform the three-byte hash. To solve this problem, in LZRW3, both the */
156/* compressor and decompressor are wired up so that they "buffer" these */
157/* literals and update their hash tables only when three bytes are available. */
158/* This makes the maximum buffering 2 bytes. */
159/* */
160/* Replacement of offsets by hash table indexes yields a few percent extra */
161/* compression at the cost of some speed. LZRW3 is slower than LZRW1, LZRW1-A */
162/* and LZRW2, but yields better compression. */
163/* */
164/* Extra compression could be obtained by using a hash table of depth two. */
165/* However, increasing the depth above one incurs a significant decrease in */
166/* compression speed which was not considered worthwhile. Another reason for */
167/* keeping the depth down to one was to allow easy comparison with the */
168/* LZRW1-A and LZRW2 algorithms so as to demonstrate the exact effect of the */
169/* use of direct hash indexes. */
170/* */
171/* +---+ */
172/* |___|4095 */
173/* |___| */
174/* +---------------------*_|<---+ /----+---\ */
175/* | |___| +---|Hash | */
176/* | |___| |Function| */
177/* | |___| \--------/ */
178/* | |___|0 ^ */
179/* | +---+ | */
180/* | Hash +-----+ */
181/* | Table | */
182/* | --- */
183/* v ^^^ */
184/* +-------------------------------------|----------------+ */
185/* |||||||||||||||||||||||||||||||||||||||||||||||||||||||| */
186/* +-------------------------------------|----------------+ */
187/* | |1......18| | */
188/* |<------- Lempel=History ------------>|<--Ziv-->| | */
189/* | (=bytes already processed) |<-Still to go-->| */
190/* |<-------------------- INPUT BLOCK ------------------->| */
191/* */
192/* The diagram above for LZRW3 looks almost identical to the diagram for */
193/* LZRW1. The difference is that in LZRW3, the compressor transmits hash */
194/* table indices instead of Lempel offsets. For this to work, the */
195/* decompressor must maintain a hash table as well as the compressor and both */
196/* compressor and decompressor must "buffer" literals, as the decompressor */
197/* cannot hash phrases commencing with a literal until another two bytes have */
198/* arrived. */
199/* */
200/* LZRW3 Algorithm Execution Summary */
201/* --------------------------------- */
202/* 1. Hash the first three bytes of the Ziv to yield a hash table index h. */
203/* 2. Look up the hash table yielding history pointer p. */
204/* 3. Match where p points with the Ziv. If there is a match of three or */
205/* more bytes, code those bytes (in the Ziv) as a copy item, otherwise */
206/* code the next byte in the Ziv as a literal item. */
207/* 4. Update the hash table as possible subject to the constraint that only */
208/* phrases commencing three bytes back from the Ziv can be hashed and */
209/* entered into the hash table. (This enables the decompressor to keep */
210/* pace). See the description and code for more details. */
211/* */
212/******************************************************************************/
213/* */
214/* DEFINITION OF COMPRESSED FILE FORMAT */
215/* ==================================== */
216/* * A compressed file consists of a COPY FLAG followed by a REMAINDER. */
217/* * The copy flag CF uses up four bytes with the first byte being the */
218/* least significant. */
219/* * If CF=1, then the compressed file represents the remainder of the file */
220/* exactly. Otherwise CF=0 and the remainder of the file consists of zero */
221/* or more GROUPS, each of which represents one or more bytes. */
222/* * Each group consists of two bytes of CONTROL information followed by */
223/* sixteen ITEMs except for the last group which can contain from one */
224/* to sixteen items. */
225/* * An item can be either a LITERAL item or a COPY item. */
226/* * Each item corresponds to a bit in the control bytes. */
227/* * The first control byte corresponds to the first 8 items in the group */
228/* with bit 0 corresponding to the first item in the group and bit 7 to */
229/* the eighth item in the group. */
230/* * The second control byte corresponds to the second 8 items in the group */
231/* with bit 0 corresponding to the ninth item in the group and bit 7 to */
232/* the sixteenth item in the group. */
233/* * A zero bit in a control word means that the corresponding item is a */
234/* literal item. A one bit corresponds to a copy item. */
235/* * A literal item consists of a single byte which represents itself. */
236/* * A copy item consists of two bytes that represent from 3 to 18 bytes. */
237/* * The first byte in a copy item will be denoted C1. */
238/* * The second byte in a copy item will be denoted C2. */
239/* * Bits will be selected using square brackets. */
240/* For example: C1[0..3] is the low nibble of the first control byte. */
241/* of copy item C1. */
242/* * The LENGTH of a copy item is defined to be C1[0..3]+3 which is a number */
243/* in the range [3,18]. */
244/* * The INDEX of a copy item is defined to be C1[4..7]*256+C2[0..8] which */
245/* is a number in the range [0,4095]. */
246/* * A copy item represents the sequence of bytes */
247/* text[POS-OFFSET..POS-OFFSET+LENGTH-1] where */
248/* text is the entire text of the uncompressed string. */
249/* POS is the index in the text of the character following the */
250/* string represented by all the items preceeding the item */
251/* being defined. */
252/* OFFSET is obtained from INDEX by looking up the hash table. */
253/* */
254/******************************************************************************/
255
256/* The following #define defines the length of the copy flag that appears at */
257/* the start of the compressed file. The value of four bytes was chosen */
258/* because the fast_copy routine on my Macintosh runs faster if the source */
259/* and destination blocks are relatively longword aligned. */
260/* The actual flag data appears in the first byte. The rest are zeroed so as */
261/* to normalize the compressed representation (i.e. not non-deterministic). */
262#define FLAG_BYTES 4
263
264/* The following #defines define the meaning of the values of the copy */
265/* flag at the start of the compressed file. */
266#define FLAG_COMPRESS 0 /* Signals that output was result of compression. */
267#define FLAG_COPY 1 /* Signals that output was simply copied over. */
268
269/* The 68000 microprocessor (on which this algorithm was originally developed */
270/* is fussy about non-aligned arrays of words. To avoid these problems the */
271/* following macro can be used to "waste" from 0 to 3 bytes so as to align */
272/* the argument pointer. */
273#define ULONG_ALIGN_UP(X) ((((ULONG)X)+sizeof(ULONG)-1)&~(sizeof(ULONG)-1))
274
275
276/* The following constant defines the maximum length of an uncompressed item. */
277/* This definition must not be changed; its value is hardwired into the code. */
278/* The longest number of bytes that can be spanned by a single item is 18 */
279/* for the longest copy item. */
280#define MAX_RAW_ITEM (18)
281
282/* The following constant defines the maximum length of an uncompressed group.*/
283/* This definition must not be changed; its value is hardwired into the code. */
284/* A group contains at most 16 items which explains this definition. */
285#define MAX_RAW_GROUP (16*MAX_RAW_ITEM)
286
287/* The following constant defines the maximum length of a compressed group. */
288/* This definition must not be changed; its value is hardwired into the code. */
289/* A compressed group consists of two control bytes followed by up to 16 */
290/* compressed items each of which can have a maximum length of two bytes. */
291#define MAX_CMP_GROUP (2+16*2)
292
293/* The following constant defines the number of entries in the hash table. */
294/* This definition must not be changed; its value is hardwired into the code. */
295#define HASH_TABLE_LENGTH (4096)
296
297/* LZRW3, unlike LZRW1(-A), must initialize its hash table so as to enable */
298/* the compressor and decompressor to stay in step maintaining identical hash */
299/* tables. In an early version of the algorithm, the tables were simply */
300/* initialized to zero and a check for zero was included just before the */
301/* matching code. However, this test costs time. A better solution is to */
302/* initialize all the entries in the hash table to point to a constant */
303/* string. The decompressor does the same. This solution requires no extra */
304/* test. The contents of the string do not matter so long as the string is */
305/* the same for the compressor and decompressor and contains at least */
306/* MAX_RAW_ITEM bytes. I chose consecutive decimal digits because they do not */
307/* have white space problems (e.g. there is no chance that the compiler will */
308/* replace more than one space by a TAB) and because they make the length of */
309/* the string obvious by inspection. */
310#define START_STRING_18 ((UBYTE *) "123456789012345678")
311
312/* In this algorithm, hash values have to be calculated at more than one */
313/* point. The following macro neatens the code up for this. */
314#define HASH(PTR) \
315 (((40543*(((*(PTR))<<8)^((*((PTR)+1))<<4)^(*((PTR)+2))))>>4) & 0xFFF)
316
317/******************************************************************************/
318
319/* Input : Hand over the required amount of working memory in p_wrk_mem. */
320/* Input : Specify input block using p_src_first and src_len. */
321/* Input : Point p_dst_first to the start of the output zone (OZ). */
322/* Input : Point p_dst_len to a ULONG to receive the output length. */
323/* Input : Input block and output zone must not overlap. */
324/* Output : Length of output block written to *p_dst_len. */
325/* Output : Output block in Mem[p_dst_first..p_dst_first+*p_dst_len-1]. May */
326/* Output : write in OZ=Mem[p_dst_first..p_dst_first+src_len+MAX_CMP_GROUP-1].*/
327/* Output : Upon completion guaranteed *p_dst_len<=src_len+FLAG_BYTES. */
328LOCAL void compress_compress(UBYTE *p_wrk_mem,
329 UBYTE *p_src_first, ULONG src_len,
330 UBYTE *p_dst_first, LONG *p_dst_len)
331{
332 /* p_src and p_dst step through the source and destination blocks. */
333 register UBYTE *p_src = p_src_first;
334 register UBYTE *p_dst = p_dst_first;
335
336 /* The following variables are never modified and are used in the */
337 /* calculations that determine when the main loop terminates. */
338 UBYTE *p_src_post = p_src_first+src_len;
339 UBYTE *p_dst_post = p_dst_first+src_len;
340 UBYTE *p_src_max1 = p_src_first+src_len-MAX_RAW_ITEM;
341 UBYTE *p_src_max16 = p_src_first+src_len-MAX_RAW_ITEM*16;
342
343 /* The variables 'p_control' and 'control' are used to buffer control bits. */
344 /* Before each group is processed, the next two bytes of the output block */
345 /* are set aside for the control word for the group about to be processed. */
346 /* 'p_control' is set to point to the first byte of that word. Meanwhile, */
347 /* 'control' buffers the control bits being generated during the processing */
348 /* of the group. Instead of having a counter to keep track of how many items */
349 /* have been processed (=the number of bits in the control word), at the */
350 /* start of each group, the top word of 'control' is filled with 1 bits. */
351 /* As 'control' is shifted for each item, the 1 bits in the top word are */
352 /* absorbed or destroyed. When they all run out (i.e. when the top word is */
353 /* all zero bits, we know that we are at the end of a group. */
354# define TOPWORD 0xFFFF0000
355 UBYTE *p_control;
356 register ULONG control=TOPWORD;
357
358 /* THe variable 'hash' always points to the first element of the hash table. */
359 UBYTE **hash= (UBYTE **) ULONG_ALIGN_UP(p_wrk_mem);
360
361 /* The following two variables represent the literal buffer. p_h1 points to */
362 /* the hash table entry corresponding to the youngest literal. p_h2 points */
363 /* to the hash table entry corresponding to the second youngest literal. */
364 /* Note: p_h1=0=>p_h2=0 because zero values denote absence of a pending */
365 /* literal. The variables are initialized to zero meaning an empty "buffer". */
366 UBYTE **p_h1=NULL;
367 UBYTE **p_h2=NULL;
368
369 /* To start, we write the flag bytes. Being optimistic, we set the flag to */
370 /* FLAG_COMPRESS. The remaining flag bytes are zeroed so as to keep the */
371 /* algorithm deterministic. */
372 *p_dst++=FLAG_COMPRESS;
373 {UWORD i; for (i=2;i<=FLAG_BYTES;i++) *p_dst++=0;}
374
375 /* Reserve the first word of output as the control word for the first group. */
376 /* Note: This is undone at the end if the input block is empty. */
377 p_control=p_dst; p_dst+=2;
378
379 /* Initialize all elements of the hash table to point to a constant string. */
380 /* Use of an unrolled loop speeds this up considerably. */
381 {UWORD i; UBYTE **p_h=hash;
382# define ZH *p_h++=START_STRING_18
383 for (i=0;i<256;i++) /* 256=HASH_TABLE_LENGTH/16. */
384 {ZH;ZH;ZH;ZH;
385 ZH;ZH;ZH;ZH;
386 ZH;ZH;ZH;ZH;
387 ZH;ZH;ZH;ZH;}
388 }
389
390 /* The main loop processes either 1 or 16 items per iteration. As its */
391 /* termination logic is complicated, I have opted for an infinite loop */
392 /* structure containing 'break' and 'goto' statements. */
393 while (TRUE)
394 {/* Begin main processing loop. */
395
396 /* Note: All the variables here except unroll should be defined within */
397 /* the inner loop. Unfortunately the loop hasn't got a block. */
398 register UBYTE *p; /* Scans through targ phrase during matching. */
399 register UBYTE *p_ziv= NULL ; /* Points to first byte of current Ziv. */
400 register UWORD unroll; /* Loop counter for unrolled inner loop. */
401 register UWORD index; /* Index of current hash table entry. */
402 register UBYTE **p_h0 = NULL ; /* Pointer to current hash table entry. */
403
404 /* Test for overrun and jump to overrun code if necessary. */
405 if (p_dst>p_dst_post)
406 goto overrun;
407
408 /* The following cascade of if statements efficiently catches and deals */
409 /* with varying degrees of closeness to the end of the input block. */
410 /* When we get very close to the end, we stop updating the table and */
411 /* code the remaining bytes as literals. This makes the code simpler. */
412 unroll=16;
413 if (p_src>p_src_max16)
414 {
415 unroll=1;
416 if (p_src>p_src_max1)
417 {
418 if (p_src==p_src_post)
419 break;
420 else
421 goto literal;
422 }
423 }
424
425 /* This inner unrolled loop processes 'unroll' (whose value is either 1 */
426 /* or 16) items. I have chosen to implement this loop with labels and */
427 /* gotos to heighten the ease with which the loop may be implemented with */
428 /* a single decrement and branch instruction in assembly language and */
429 /* also because the labels act as highly readable place markers. */
430 /* (Also because we jump into the loop for endgame literals (see above)). */
431
432 begin_unrolled_loop:
433
434 /* To process the next phrase, we hash the next three bytes and use */
435 /* the resultant hash table index to look up the hash table. A pointer */
436 /* to the entry is stored in p_h0 so as to avoid an array lookup. The */
437 /* hash table entry *p_h0 is looked up yielding a pointer p to a */
438 /* potential match of the Ziv in the history. */
439 index=HASH(p_src);
440 p_h0=&hash[index];
441 p=*p_h0;
442
443 /* Having looked up the candidate position, we are in a position to */
444 /* attempt a match. The match loop has been unrolled using the PS */
445 /* macro so that failure within the first three bytes automatically */
446 /* results in the literal branch being taken. The coding is simple. */
447 /* p_ziv saves p_src so we can let p_src wander. */
448# define PS *p++!=*p_src++
449 p_ziv=p_src;
450 if (PS || PS || PS)
451 {
452 /* Literal. */
453
454 /* Code the literal byte as itself and a zero control bit. */
455 p_src=p_ziv; literal: *p_dst++=*p_src++; control&=0xFFFEFFFF;
456
457 /* We have just coded a literal. If we had two pending ones, that */
458 /* makes three and we can update the hash table. */
459 if (p_h2!=0)
460 {*p_h2=p_ziv-2;}
461
462 /* In any case, rotate the hash table pointers for next time. */
463 p_h2=p_h1; p_h1=p_h0;
464
465 }
466 else
467 {
468 /* Copy */
469
470 /* Match up to 15 remaining bytes using an unrolled loop and code. */
471#if 0
472 PS || PS || PS || PS || PS || PS || PS || PS ||
473 PS || PS || PS || PS || PS || PS || PS || p_src++;
474#else
475 if (
476 !( PS || PS || PS || PS || PS || PS || PS || PS ||
477 PS || PS || PS || PS || PS || PS || PS )
478 ) p_src++;
479#endif
480 *p_dst++=((index&0xF00)>>4)|(--p_src-p_ziv-3);
481 *p_dst++=index&0xFF;
482
483 /* As we have just coded three bytes, we are now in a position to */
484 /* update the hash table with the literal bytes that were pending */
485 /* upon the arrival of extra context bytes. */
486 if (p_h1!=0)
487 {
488 if (p_h2)
489 {*p_h2=p_ziv-2; p_h2=NULL;}
490 *p_h1=p_ziv-1; p_h1=NULL;
491 }
492
493 /* In any case, we can update the hash table based on the current */
494 /* position as we just coded at least three bytes in a copy items. */
495 *p_h0=p_ziv;
496
497 }
498 control>>=1;
499
500 /* This loop is all set up for a decrement and jump instruction! */
501#ifndef linux
502` end_unrolled_loop: if (--unroll) goto begin_unrolled_loop;
503#else
504 /* end_unrolled_loop: */ if (--unroll) goto begin_unrolled_loop;
505#endif
506
507 /* At this point it will nearly always be the end of a group in which */
508 /* case, we have to do some control-word processing. However, near the */
509 /* end of the input block, the inner unrolled loop is only executed once. */
510 /* This necessitates the 'if' test. */
511 if ((control&TOPWORD)==0)
512 {
513 /* Write the control word to the place we saved for it in the output. */
514 *p_control++= control &0xFF;
515 *p_control = (control>>8) &0xFF;
516
517 /* Reserve the next word in the output block for the control word */
518 /* for the group about to be processed. */
519 p_control=p_dst; p_dst+=2;
520
521 /* Reset the control bits buffer. */
522 control=TOPWORD;
523 }
524
525 } /* End main processing loop. */
526
527 /* After the main processing loop has executed, all the input bytes have */
528 /* been processed. However, the control word has still to be written to the */
529 /* word reserved for it in the output at the start of the most recent group. */
530 /* Before writing, the control word has to be shifted so that all the bits */
531 /* are in the right place. The "empty" bit positions are filled with 1s */
532 /* which partially fill the top word. */
533 while(control&TOPWORD) control>>=1;
534 *p_control++= control &0xFF;
535 *p_control++=(control>>8) &0xFF;
536
537 /* If the last group contained no items, delete the control word too. */
538 if (p_control==p_dst) p_dst-=2;
539
540 /* Write the length of the output block to the dst_len parameter and return. */
541 *p_dst_len=p_dst-p_dst_first;
542 return;
543
544 /* Jump here as soon as an overrun is detected. An overrun is defined to */
545 /* have occurred if p_dst>p_dst_first+src_len. That is, the moment the */
546 /* length of the output written so far exceeds the length of the input block.*/
547 /* The algorithm checks for overruns at least at the end of each group */
548 /* which means that the maximum overrun is MAX_CMP_GROUP bytes. */
549 /* Once an overrun occurs, the only thing to do is to set the copy flag and */
550 /* copy the input over. */
551 overrun:
552#if 0
553 *p_dst_first=FLAG_COPY;
554 fast_copy(p_src_first,p_dst_first+FLAG_BYTES,src_len);
555 *p_dst_len=src_len+FLAG_BYTES;
556#else
557 fast_copy(p_src_first,p_dst_first,src_len);
558 *p_dst_len= -src_len; /* return a negative number to indicate uncompressed data */
559#endif
560}
561
562/******************************************************************************/
563
564/* Input : Hand over the required amount of working memory in p_wrk_mem. */
565/* Input : Specify input block using p_src_first and src_len. */
566/* Input : Point p_dst_first to the start of the output zone. */
567/* Input : Point p_dst_len to a ULONG to receive the output length. */
568/* Input : Input block and output zone must not overlap. User knows */
569/* Input : upperbound on output block length from earlier compression. */
570/* Input : In any case, maximum expansion possible is nine times. */
571/* Output : Length of output block written to *p_dst_len. */
572/* Output : Output block in Mem[p_dst_first..p_dst_first+*p_dst_len-1]. */
573/* Output : Writes only in Mem[p_dst_first..p_dst_first+*p_dst_len-1]. */
574LOCAL void compress_decompress( UBYTE *p_wrk_mem,
575 UBYTE *p_src_first, LONG src_len,
576 UBYTE *p_dst_first, ULONG *p_dst_len)
577{
578 /* Byte pointers p_src and p_dst scan through the input and output blocks. */
579 register UBYTE *p_src = p_src_first+FLAG_BYTES;
580 register UBYTE *p_dst = p_dst_first;
581 /* we need to avoid a SEGV when trying to uncompress corrupt data */
582 register UBYTE *p_dst_post = p_dst_first + *p_dst_len;
583
584 /* The following two variables are never modified and are used to control */
585 /* the main loop. */
586 UBYTE *p_src_post = p_src_first+src_len;
587 UBYTE *p_src_max16 = p_src_first+src_len-(MAX_CMP_GROUP-2);
588
589 /* The hash table is the only resident of the working memory. The hash table */
590 /* contains HASH_TABLE_LENGTH=4096 pointers to positions in the history. To */
591 /* keep Macintoshes happy, it is longword aligned. */
592 UBYTE **hash = (UBYTE **) ULONG_ALIGN_UP(p_wrk_mem);
593
594 /* The variable 'control' is used to buffer the control bits which appear in */
595 /* groups of 16 bits (control words) at the start of each compressed group. */
596 /* When each group is read, bit 16 of the register is set to one. Whenever */
597 /* a new bit is needed, the register is shifted right. When the value of the */
598 /* register becomes 1, we know that we have reached the end of a group. */
599 /* Initializing the register to 1 thus instructs the code to follow that it */
600 /* should read a new control word immediately. */
601 register ULONG control=1;
602
603 /* The value of 'literals' is always in the range 0..3. It is the number of */
604 /* consecutive literal items just seen. We have to record this number so as */
605 /* to know when to update the hash table. When literals gets to 3, there */
606 /* have been three consecutive literals and we can update at the position of */
607 /* the oldest of the three. */
608 register UWORD literals=0;
609
610 /* Check the leading copy flag to see if the compressor chose to use a copy */
611 /* operation instead of a compression operation. If a copy operation was */
612 /* used, then all we need to do is copy the data over, set the output length */
613 /* and return. */
614#if 0
615 if (*p_src_first==FLAG_COPY)
616 {
617 fast_copy(p_src_first+FLAG_BYTES,p_dst_first,src_len-FLAG_BYTES);
618 *p_dst_len=src_len-FLAG_BYTES;
619 return;
620 }
621#else
622 if ( src_len < 0 )
623 {
624 fast_copy(p_src_first,p_dst_first,-src_len );
625 *p_dst_len = (ULONG)-src_len;
626 return;
627 }
628#endif
629
630 /* Initialize all elements of the hash table to point to a constant string. */
631 /* Use of an unrolled loop speeds this up considerably. */
632 {UWORD i; UBYTE **p_h=hash;
633# define ZJ *p_h++=START_STRING_18
634 for (i=0;i<256;i++) /* 256=HASH_TABLE_LENGTH/16. */
635 {ZJ;ZJ;ZJ;ZJ;
636 ZJ;ZJ;ZJ;ZJ;
637 ZJ;ZJ;ZJ;ZJ;
638 ZJ;ZJ;ZJ;ZJ;}
639 }
640
641 /* The outer loop processes either 1 or 16 items per iteration depending on */
642 /* how close p_src is to the end of the input block. */
643 while (p_src!=p_src_post)
644 {/* Start of outer loop */
645
646 register UWORD unroll; /* Counts unrolled loop executions. */
647
648 /* When 'control' has the value 1, it means that the 16 buffered control */
649 /* bits that were read in at the start of the current group have all been */
650 /* shifted out and that all that is left is the 1 bit that was injected */
651 /* into bit 16 at the start of the current group. When we reach the end */
652 /* of a group, we have to load a new control word and inject a new 1 bit. */
653 if (control==1)
654 {
655 control=0x10000|*p_src++;
656 control|=(*p_src++)<<8;
657 }
658
659 /* If it is possible that we are within 16 groups from the end of the */
660 /* input, execute the unrolled loop only once, else process a whole group */
661 /* of 16 items by looping 16 times. */
662 unroll= p_src<=p_src_max16 ? 16 : 1;
663
664 /* This inner loop processes one phrase (item) per iteration. */
665 while (unroll--)
666 { /* Begin unrolled inner loop. */
667
668 /* Process a literal or copy item depending on the next control bit. */
669 if (control&1)
670 {
671 /* Copy item. */
672
673 register UBYTE *p; /* Points to place from which to copy. */
674 register UWORD lenmt; /* Length of copy item minus three. */
675 register UBYTE **p_hte; /* Pointer to current hash table entry.*/
676 register UBYTE *p_ziv=p_dst; /* Pointer to start of current Ziv. */
677
678 /* Read and dismantle the copy word. Work out from where to copy. */
679 lenmt=*p_src++;
680 p_hte=&hash[((lenmt&0xF0)<<4)|*p_src++];
681 p=*p_hte;
682 lenmt&=0xF;
683
684 /* Now perform the copy using a half unrolled loop. */
685 *p_dst++=*p++;
686 *p_dst++=*p++;
687 *p_dst++=*p++;
688 while (lenmt--)
689 *p_dst++=*p++;
690
691 /* Because we have just received 3 or more bytes in a copy item */
692 /* (whose bytes we have just installed in the output), we are now */
693 /* in a position to flush all the pending literal hashings that had */
694 /* been postponed for lack of bytes. */
695 if (literals>0)
696 {
697 register UBYTE *r=p_ziv-literals;
698 hash[HASH(r)]=r;
699 if (literals==2)
700 {r++; hash[HASH(r)]=r;}
701 literals=0;
702 }
703
704 /* In any case, we can immediately update the hash table with the */
705 /* current position. We don't need to do a HASH(...) to work out */
706 /* where to put the pointer, as the compressor just told us!!! */
707 *p_hte=p_ziv;
708
709 }
710 else
711 {
712 /* Literal item. */
713
714 /* Copy over the literal byte. */
715 *p_dst++=*p_src++;
716
717 /* If we now have three literals waiting to be hashed into the hash */
718 /* table, we can do one of them now (because there are three). */
719 if (++literals == 3)
720 {register UBYTE *p=p_dst-3; hash[HASH(p)]=p; literals=2;}
721 }
722
723 /* Shift the control buffer so the next control bit is in bit 0. */
724 control>>=1;
725#if 1
726 if (p_dst > p_dst_post)
727 {
728 /* Shit: we tried to decompress corrupt data */
729 *p_dst_len = 0;
730 return;
731 }
732#endif
733 } /* End unrolled inner loop. */
734
735 } /* End of outer loop */
736
737 /* Write the length of the decompressed data before returning. */
738 *p_dst_len=p_dst-p_dst_first;
739}
740
741/******************************************************************************/
742/* End of LZRW3.C */
743/******************************************************************************/
diff --git a/drivers/char/ftape/compressor/lzrw3.h b/drivers/char/ftape/compressor/lzrw3.h
deleted file mode 100644
index 533feba47526..000000000000
--- a/drivers/char/ftape/compressor/lzrw3.h
+++ /dev/null
@@ -1,253 +0,0 @@
1#ifndef _LZRW3_H
2#define _LZRW3_H
3/*
4 * $Source: /homes/cvs/ftape-stacked/ftape/compressor/lzrw3.h,v $
5 * $Revision: 1.1 $
6 * $Date: 1997/10/05 19:12:30 $
7 *
8 * include files for lzrw3. Only slighty modified from the original
9 * version. Assembles the three include files compress.h, port.h and
10 * fastcopy.h from the original lzrw3 package.
11 *
12 */
13
14#include <linux/types.h>
15#include <linux/string.h>
16
17/******************************************************************************/
18/* */
19/* COMPRESS.H */
20/* */
21/******************************************************************************/
22/* */
23/* Author : Ross Williams. */
24/* Date : December 1989. */
25/* */
26/* This header file defines the interface to a set of functions called */
27/* 'compress', each member of which implements a particular data compression */
28/* algorithm. */
29/* */
30/* Normally in C programming, for each .H file, there is a corresponding .C */
31/* file that implements the functions promised in the .H file. */
32/* Here, there are many .C files corresponding to this header file. */
33/* Each comforming implementation file contains a single function */
34/* called 'compress' that implements a single data compression */
35/* algorithm that conforms with the interface specified in this header file. */
36/* Only one algorithm can be linked in at a time in this organization. */
37/* */
38/******************************************************************************/
39/* */
40/* DEFINITION OF FUNCTION COMPRESS */
41/* =============================== */
42/* */
43/* Summary of Function Compress */
44/* ---------------------------- */
45/* The action that 'compress' takes depends on its first argument called */
46/* 'action'. The function provides three actions: */
47/* */
48/* - Return information about the algorithm. */
49/* - Compress a block of memory. */
50/* - Decompress a block of memory. */
51/* */
52/* Parameters */
53/* ---------- */
54/* See the formal C definition later for a description of the parameters. */
55/* */
56/* Constants */
57/* --------- */
58/* COMPRESS_OVERRUN: The constant COMPRESS_OVERRUN defines by how many bytes */
59/* an algorithm is allowed to expand a block during a compression operation. */
60/* */
61/* Although compression algorithms usually compress data, there will always */
62/* be data that a given compressor will expand (this can be proven). */
63/* Fortunately, the degree of expansion can be limited to a single bit, by */
64/* copying over the input data if the data gets bigger during compression. */
65/* To allow for this possibility, the first bit of a compressed */
66/* representation can be used as a flag indicating whether the */
67/* input data was copied over, or truly compressed. In practice, the first */
68/* byte would be used to store this bit so as to maintain byte alignment. */
69/* */
70/* Unfortunately, in general, the only way to tell if an algorithm will */
71/* expand a particular block of data is to run the algorithm on the data. */
72/* If the algorithm does not continuously monitor how many output bytes it */
73/* has written, it might write an output block far larger than the input */
74/* block before realizing that it has done so. */
75/* On the other hand, continuous checks on output length are inefficient. */
76/* */
77/* To cater for all these problems, this interface definition: */
78/* > Allows a compression algorithm to return an output block that is up to */
79/* COMPRESS_OVERRUN bytes longer than the input block. */
80/* > Allows a compression algorithm to write up to COMPRESS_OVERRUN bytes */
81/* more than the length of the input block to the memory of the output */
82/* block regardless of the length of the output block eventually returned. */
83/* This allows an algorithm to overrun the length of the input block in the */
84/* output block by up to COMPRESS_OVERRUN bytes between expansion checks. */
85/* */
86/* The problem does not arise for decompression. */
87/* */
88/* Identity Action */
89/* --------------- */
90/* > action must be COMPRESS_ACTION_IDENTITY. */
91/* > p_dst_len must point to a longword to receive a longword address. */
92/* > The value of the other parameters does not matter. */
93/* > After execution, the longword that p_dst_len points to will be a pointer */
94/* to a structure of type compress_identity. */
95/* Thus, for example, after the call, (*p_dst_len)->memory will return the */
96/* number of bytes of working memory that the algorithm requires to run. */
97/* > The values of the identity structure returned are fixed constant */
98/* attributes of the algorithm and must not vary from call to call. */
99/* */
100/* Common Requirements for Compression and Decompression Actions */
101/* ------------------------------------------------------------- */
102/* > wrk_mem must point to an unused block of memory of a length specified in */
103/* the algorithm's identity block. The identity block can be obtained by */
104/* making a separate call to compress, specifying the identity action. */
105/* > The INPUT BLOCK is defined to be Memory[src_addr,src_addr+src_len-1]. */
106/* > dst_len will be used to denote *p_dst_len. */
107/* > dst_len is not read by compress, only written. */
108/* > The value of dst_len is defined only upon termination. */
109/* > The OUTPUT BLOCK is defined to be Memory[dst_addr,dst_addr+dst_len-1]. */
110/* */
111/* Compression Action */
112/* ------------------ */
113/* > action must be COMPRESS_ACTION_COMPRESS. */
114/* > src_len must be in the range [0,COMPRESS_MAX_ORG]. */
115/* > The OUTPUT ZONE is defined to be */
116/* Memory[dst_addr,dst_addr+src_len-1+COMPRESS_OVERRUN]. */
117/* > The function can modify any part of the output zone regardless of the */
118/* final length of the output block. */
119/* > The input block and the output zone must not overlap. */
120/* > dst_len will be in the range [0,src_len+COMPRESS_OVERRUN]. */
121/* > dst_len will be in the range [0,COMPRESS_MAX_COM] (from prev fact). */
122/* > The output block will consist of a representation of the input block. */
123/* */
124/* Decompression Action */
125/* -------------------- */
126/* > action must be COMPRESS_ACTION_DECOMPRESS. */
127/* > The input block must be the result of an earlier compression operation. */
128/* > If the previous fact is true, the following facts must also be true: */
129/* > src_len will be in the range [0,COMPRESS_MAX_COM]. */
130/* > dst_len will be in the range [0,COMPRESS_MAX_ORG]. */
131/* > The input and output blocks must not overlap. */
132/* > Only the output block is modified. */
133/* > Upon termination, the output block will consist of the bytes contained */
134/* in the input block passed to the earlier compression operation. */
135/* */
136/******************************************************************************/
137
138/******************************************************************************/
139/* */
140/* PORT.H */
141/* */
142/******************************************************************************/
143/* */
144/* This module contains macro definitions and types that are likely to */
145/* change between computers. */
146/* */
147/******************************************************************************/
148
149#ifndef DONE_PORT /* Only do this if not previously done. */
150
151 #ifdef THINK_C
152 #define UBYTE unsigned char /* Unsigned byte */
153 #define UWORD unsigned int /* Unsigned word (2 bytes) */
154 #define ULONG unsigned long /* Unsigned word (4 bytes) */
155 #define BOOL unsigned char /* Boolean */
156 #define FOPEN_BINARY_READ "rb" /* Mode string for binary reading. */
157 #define FOPEN_BINARY_WRITE "wb" /* Mode string for binary writing. */
158 #define FOPEN_TEXT_APPEND "a" /* Mode string for text appending. */
159 #define REAL double /* USed for floating point stuff. */
160 #endif
161 #if defined(LINUX) || defined(linux)
162 #define UBYTE __u8 /* Unsigned byte */
163 #define UWORD __u16 /* Unsigned word (2 bytes) */
164 #define ULONG __u32 /* Unsigned word (4 bytes) */
165 #define LONG __s32 /* Signed word (4 bytes) */
166 #define BOOL is not used here /* Boolean */
167 #define FOPEN_BINARY_READ not used /* Mode string for binary reading. */
168 #define FOPEN_BINARY_WRITE not used /* Mode string for binary writing. */
169 #define FOPEN_TEXT_APPEND not used /* Mode string for text appending. */
170 #define REAL not used /* USed for floating point stuff. */
171 #ifndef TRUE
172 #define TRUE 1
173 #endif
174 #endif
175
176 #define DONE_PORT /* Don't do all this again. */
177 #define MALLOC_FAIL NULL /* Failure status from malloc() */
178 #define LOCAL static /* For non-exported routines. */
179 #define EXPORT /* Signals exported function. */
180 #define then /* Useful for aligning ifs. */
181
182#endif
183
184/******************************************************************************/
185/* End of PORT.H */
186/******************************************************************************/
187
188#define COMPRESS_ACTION_IDENTITY 0
189#define COMPRESS_ACTION_COMPRESS 1
190#define COMPRESS_ACTION_DECOMPRESS 2
191
192#define COMPRESS_OVERRUN 1024
193#define COMPRESS_MAX_COM 0x70000000
194#define COMPRESS_MAX_ORG (COMPRESS_MAX_COM-COMPRESS_OVERRUN)
195
196#define COMPRESS_MAX_STRLEN 255
197
198/* The following structure provides information about the algorithm. */
199/* > The top bit of id must be zero. The remaining bits must be chosen by */
200/* the author of the algorithm by tossing a coin 31 times. */
201/* > The amount of memory requested by the algorithm is specified in bytes */
202/* and must be in the range [0,0x70000000]. */
203/* > All strings s must be such that strlen(s)<=COMPRESS_MAX_STRLEN. */
204struct compress_identity
205 {
206 ULONG id; /* Identifying number of algorithm. */
207 ULONG memory; /* Number of bytes of working memory required. */
208
209 char *name; /* Name of algorithm. */
210 char *version; /* Version number. */
211 char *date; /* Date of release of this version. */
212 char *copyright; /* Copyright message. */
213
214 char *author; /* Author of algorithm. */
215 char *affiliation; /* Affiliation of author. */
216 char *vendor; /* Where the algorithm can be obtained. */
217 };
218
219void lzrw3_compress( /* Single function interface to compression algorithm. */
220UWORD action, /* Action to be performed. */
221UBYTE *wrk_mem, /* Working memory temporarily given to routine to use. */
222UBYTE *src_adr, /* Address of input data. */
223LONG src_len, /* Length of input data. */
224UBYTE *dst_adr, /* Address of output data. */
225void *p_dst_len /* Pointer to a longword where routine will write: */
226 /* If action=..IDENTITY => Adr of id structure. */
227 /* If action=..COMPRESS => Length of output data. */
228 /* If action=..DECOMPRESS => Length of output data. */
229);
230
231/******************************************************************************/
232/* End of COMPRESS.H */
233/******************************************************************************/
234
235
236/******************************************************************************/
237/* fast_copy.h */
238/******************************************************************************/
239
240/* This function copies a block of memory very quickly. */
241/* The exact speed depends on the relative alignment of the blocks of memory. */
242/* PRE : 0<=src_len<=(2^32)-1 . */
243/* PRE : Source and destination blocks must not overlap. */
244/* POST : MEM[dst_adr,dst_adr+src_len-1]=MEM[src_adr,src_adr+src_len-1]. */
245/* POST : MEM[dst_adr,dst_adr+src_len-1] is the only memory changed. */
246
247#define fast_copy(src,dst,len) memcpy(dst,src,len)
248
249/******************************************************************************/
250/* End of fast_copy.h */
251/******************************************************************************/
252
253#endif
diff --git a/drivers/char/ftape/compressor/zftape-compress.c b/drivers/char/ftape/compressor/zftape-compress.c
deleted file mode 100644
index 65ffc0be3df9..000000000000
--- a/drivers/char/ftape/compressor/zftape-compress.c
+++ /dev/null
@@ -1,1203 +0,0 @@
1/*
2 * Copyright (C) 1994-1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or
5 modify it under the terms of the GNU General Public License as
6 published by the Free Software Foundation; either version 2, or (at
7 your option) any later version.
8
9 This program is distributed in the hope that it will be useful, but
10 WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
17 USA.
18
19 *
20 * This file implements a "generic" interface between the *
21 * zftape-driver and a compression-algorithm. The *
22 * compression-algorithm currently used is a LZ77. I use the *
23 * implementation lzrw3 by Ross N. Williams (Renaissance *
24 * Software). The compression program itself is in the file
25 * lzrw3.c * and lzrw3.h. To adopt another compression algorithm
26 * the functions * zft_compress() and zft_uncompress() must be
27 * changed * appropriately. See below.
28 */
29
30#include <linux/errno.h>
31#include <linux/mm.h>
32#include <linux/module.h>
33
34#include <linux/zftape.h>
35
36#include <asm/uaccess.h>
37
38#include "../zftape/zftape-init.h"
39#include "../zftape/zftape-eof.h"
40#include "../zftape/zftape-ctl.h"
41#include "../zftape/zftape-write.h"
42#include "../zftape/zftape-read.h"
43#include "../zftape/zftape-rw.h"
44#include "../compressor/zftape-compress.h"
45#include "../zftape/zftape-vtbl.h"
46#include "../compressor/lzrw3.h"
47
48/*
49 * global variables
50 */
51
52/* I handle the allocation of this buffer as a special case, because
53 * it's size varies depending on the tape length inserted.
54 */
55
56/* local variables
57 */
58static void *zftc_wrk_mem = NULL;
59static __u8 *zftc_buf = NULL;
60static void *zftc_scratch_buf = NULL;
61
62/* compression statistics
63 */
64static unsigned int zftc_wr_uncompressed = 0;
65static unsigned int zftc_wr_compressed = 0;
66static unsigned int zftc_rd_uncompressed = 0;
67static unsigned int zftc_rd_compressed = 0;
68
69/* forward */
70static int zftc_write(int *write_cnt,
71 __u8 *dst_buf, const int seg_sz,
72 const __u8 __user *src_buf, const int req_len,
73 const zft_position *pos, const zft_volinfo *volume);
74static int zftc_read(int *read_cnt,
75 __u8 __user *dst_buf, const int to_do,
76 const __u8 *src_buf, const int seg_sz,
77 const zft_position *pos, const zft_volinfo *volume);
78static int zftc_seek(unsigned int new_block_pos,
79 zft_position *pos, const zft_volinfo *volume,
80 __u8 *buffer);
81static void zftc_lock (void);
82static void zftc_reset (void);
83static void zftc_cleanup(void);
84static void zftc_stats (void);
85
86/* compressed segment. This conforms to QIC-80-MC, Revision K.
87 *
88 * Rev. K applies to tapes with `fixed length format' which is
89 * indicated by format code 2,3 and 5. See below for format code 4 and 6
90 *
91 * 2 bytes: offset of compression segment structure
92 * 29k > offset >= 29k-18: data from previous segment ens in this
93 * segment and no compressed block starts
94 * in this segment
95 * offset == 0: data from previous segment occupies entire
96 * segment and continues in next segment
97 * n bytes: remainder from previous segment
98 *
99 * Rev. K:
100 * 4 bytes: 4 bytes: files set byte offset
101 * Post Rev. K and QIC-3020/3020:
102 * 8 bytes: 8 bytes: files set byte offset
103 * 2 bytes: byte count N (amount of data following)
104 * bit 15 is set if data is compressed, bit 15 is not
105 * set if data is uncompressed
106 * N bytes: data (as much as specified in the byte count)
107 * 2 bytes: byte count N_1 of next cluster
108 * N_1 bytes: data of next cluset
109 * 2 bytes: byte count N_2 of next cluster
110 * N_2 bytes: ...
111 *
112 * Note that the `N' byte count accounts only for the bytes that in the
113 * current segment if the cluster spans to the next segment.
114 */
115
116typedef struct
117{
118 int cmpr_pos; /* actual position in compression buffer */
119 int cmpr_sz; /* what is left in the compression buffer
120 * when copying the compressed data to the
121 * deblock buffer
122 */
123 unsigned int first_block; /* location of header information in
124 * this segment
125 */
126 unsigned int count; /* amount of data of current block
127 * contained in current segment
128 */
129 unsigned int offset; /* offset in current segment */
130 unsigned int spans:1; /* might continue in next segment */
131 unsigned int uncmpr; /* 0x8000 if this block contains
132 * uncompressed data
133 */
134 __s64 foffs; /* file set byte offset, same as in
135 * compression map segment
136 */
137} cmpr_info;
138
139static cmpr_info cseg; /* static data. Must be kept uptodate and shared by
140 * read, write and seek functions
141 */
142
143#define DUMP_CMPR_INFO(level, msg, info) \
144 TRACE(level, msg "\n" \
145 KERN_INFO "cmpr_pos : %d\n" \
146 KERN_INFO "cmpr_sz : %d\n" \
147 KERN_INFO "first_block: %d\n" \
148 KERN_INFO "count : %d\n" \
149 KERN_INFO "offset : %d\n" \
150 KERN_INFO "spans : %d\n" \
151 KERN_INFO "uncmpr : 0x%04x\n" \
152 KERN_INFO "foffs : " LL_X, \
153 (info)->cmpr_pos, (info)->cmpr_sz, (info)->first_block, \
154 (info)->count, (info)->offset, (info)->spans == 1, \
155 (info)->uncmpr, LL((info)->foffs))
156
157/* dispatch compression segment info, return error code
158 *
159 * afterwards, cseg->offset points to start of data of the NEXT
160 * compressed block, and cseg->count contains the amount of data
161 * left in the actual compressed block. cseg->spans is set to 1 if
162 * the block is continued in the following segment. Otherwise it is
163 * set to 0.
164 */
165static int get_cseg (cmpr_info *cinfo, const __u8 *buff,
166 const unsigned int seg_sz,
167 const zft_volinfo *volume)
168{
169 TRACE_FUN(ft_t_flow);
170
171 cinfo->first_block = GET2(buff, 0);
172 if (cinfo->first_block == 0) { /* data spans to next segment */
173 cinfo->count = seg_sz - sizeof(__u16);
174 cinfo->offset = seg_sz;
175 cinfo->spans = 1;
176 } else { /* cluster definetely ends in this segment */
177 if (cinfo->first_block > seg_sz) {
178 /* data corrupted */
179 TRACE_ABORT(-EIO, ft_t_err, "corrupted data:\n"
180 KERN_INFO "segment size: %d\n"
181 KERN_INFO "first block : %d",
182 seg_sz, cinfo->first_block);
183 }
184 cinfo->count = cinfo->first_block - sizeof(__u16);
185 cinfo->offset = cinfo->first_block;
186 cinfo->spans = 0;
187 }
188 /* now get the offset the first block should have in the
189 * uncompressed data stream.
190 *
191 * For this magic `18' refer to CRF-3 standard or QIC-80MC,
192 * Rev. K.
193 */
194 if ((seg_sz - cinfo->offset) > 18) {
195 if (volume->qic113) { /* > revision K */
196 TRACE(ft_t_data_flow, "New QIC-113 compliance");
197 cinfo->foffs = GET8(buff, cinfo->offset);
198 cinfo->offset += sizeof(__s64);
199 } else {
200 TRACE(/* ft_t_data_flow */ ft_t_noise, "pre QIC-113 version");
201 cinfo->foffs = (__s64)GET4(buff, cinfo->offset);
202 cinfo->offset += sizeof(__u32);
203 }
204 }
205 if (cinfo->foffs > volume->size) {
206 TRACE_ABORT(-EIO, ft_t_err, "Inconsistency:\n"
207 KERN_INFO "offset in current volume: %d\n"
208 KERN_INFO "size of current volume : %d",
209 (int)(cinfo->foffs>>10), (int)(volume->size>>10));
210 }
211 if (cinfo->cmpr_pos + cinfo->count > volume->blk_sz) {
212 TRACE_ABORT(-EIO, ft_t_err, "Inconsistency:\n"
213 KERN_INFO "block size : %d\n"
214 KERN_INFO "data record: %d",
215 volume->blk_sz, cinfo->cmpr_pos + cinfo->count);
216 }
217 DUMP_CMPR_INFO(ft_t_noise /* ft_t_any */, "", cinfo);
218 TRACE_EXIT 0;
219}
220
221/* This one is called, when a new cluster starts in same segment.
222 *
223 * Note: if this is the first cluster in the current segment, we must
224 * not check whether there are more than 18 bytes available because
225 * this have already been done in get_cseg() and there may be less
226 * than 18 bytes available due to header information.
227 *
228 */
229static void get_next_cluster(cmpr_info *cluster, const __u8 *buff,
230 const int seg_sz, const int finish)
231{
232 TRACE_FUN(ft_t_flow);
233
234 if (seg_sz - cluster->offset > 18 || cluster->foffs != 0) {
235 cluster->count = GET2(buff, cluster->offset);
236 cluster->uncmpr = cluster->count & 0x8000;
237 cluster->count -= cluster->uncmpr;
238 cluster->offset += sizeof(__u16);
239 cluster->foffs = 0;
240 if ((cluster->offset + cluster->count) < seg_sz) {
241 cluster->spans = 0;
242 } else if (cluster->offset + cluster->count == seg_sz) {
243 cluster->spans = !finish;
244 } else {
245 /* either an error or a volume written by an
246 * old version. If this is a data error, then we'll
247 * catch it later.
248 */
249 TRACE(ft_t_data_flow, "Either error or old volume");
250 cluster->spans = 1;
251 cluster->count = seg_sz - cluster->offset;
252 }
253 } else {
254 cluster->count = 0;
255 cluster->spans = 0;
256 cluster->foffs = 0;
257 }
258 DUMP_CMPR_INFO(ft_t_noise /* ft_t_any */ , "", cluster);
259 TRACE_EXIT;
260}
261
262static void zftc_lock(void)
263{
264}
265
266/* this function is needed for zftape_reset_position in zftape-io.c
267 */
268static void zftc_reset(void)
269{
270 TRACE_FUN(ft_t_flow);
271
272 memset((void *)&cseg, '\0', sizeof(cseg));
273 zftc_stats();
274 TRACE_EXIT;
275}
276
277static int cmpr_mem_initialized = 0;
278static unsigned int alloc_blksz = 0;
279
280static int zft_allocate_cmpr_mem(unsigned int blksz)
281{
282 TRACE_FUN(ft_t_flow);
283
284 if (cmpr_mem_initialized && blksz == alloc_blksz) {
285 TRACE_EXIT 0;
286 }
287 TRACE_CATCH(zft_vmalloc_once(&zftc_wrk_mem, CMPR_WRK_MEM_SIZE),
288 zftc_cleanup());
289 TRACE_CATCH(zft_vmalloc_always(&zftc_buf, blksz + CMPR_OVERRUN),
290 zftc_cleanup());
291 alloc_blksz = blksz;
292 TRACE_CATCH(zft_vmalloc_always(&zftc_scratch_buf, blksz+CMPR_OVERRUN),
293 zftc_cleanup());
294 cmpr_mem_initialized = 1;
295 TRACE_EXIT 0;
296}
297
298static void zftc_cleanup(void)
299{
300 TRACE_FUN(ft_t_flow);
301
302 zft_vfree(&zftc_wrk_mem, CMPR_WRK_MEM_SIZE);
303 zft_vfree(&zftc_buf, alloc_blksz + CMPR_OVERRUN);
304 zft_vfree(&zftc_scratch_buf, alloc_blksz + CMPR_OVERRUN);
305 cmpr_mem_initialized = alloc_blksz = 0;
306 TRACE_EXIT;
307}
308
309/*****************************************************************************
310 * *
311 * The following two functions "ftape_compress()" and *
312 * "ftape_uncompress()" are the interface to the actual compression *
313 * algorithm (i.e. they are calling the "compress()" function from *
314 * the lzrw3 package for now). These routines could quite easily be *
315 * changed to adopt another compression algorithm instead of lzrw3, *
316 * which currently is used. *
317 * *
318 *****************************************************************************/
319
320/* called by zft_compress_write() to perform the compression. Must
321 * return the size of the compressed data.
322 *
323 * NOTE: The size of the compressed data should not exceed the size of
324 * the uncompressed data. Most compression algorithms have means
325 * to store data unchanged if the "compressed" data amount would
326 * exceed the original one. Mostly this is done by storing some
327 * flag-bytes in front of the compressed data to indicate if it
328 * is compressed or not. Thus the worst compression result
329 * length is the original length plus those flag-bytes.
330 *
331 * We don't want that, as the QIC-80 standard provides a means
332 * of marking uncompressed blocks by simply setting bit 15 of
333 * the compressed block's length. Thus a compessed block can
334 * have at most a length of 2^15-1 bytes. The QIC-80 standard
335 * restricts the block-length even further, allowing only 29k -
336 * 6 bytes.
337 *
338 * Currently, the maximum blocksize used by zftape is 28k.
339 *
340 * In short: don't exceed the length of the input-package, set
341 * bit 15 of the compressed size to 1 if you have copied data
342 * instead of compressing it.
343 */
344static int zft_compress(__u8 *in_buffer, unsigned int in_sz, __u8 *out_buffer)
345{
346 __s32 compressed_sz;
347 TRACE_FUN(ft_t_flow);
348
349
350 lzrw3_compress(COMPRESS_ACTION_COMPRESS, zftc_wrk_mem,
351 in_buffer, in_sz, out_buffer, &compressed_sz);
352 if (TRACE_LEVEL >= ft_t_info) {
353 /* the compiler will optimize this away when
354 * compiled with NO_TRACE_AT_ALL option
355 */
356 TRACE(ft_t_data_flow, "\n"
357 KERN_INFO "before compression: %d bytes\n"
358 KERN_INFO "after compresison : %d bytes",
359 in_sz,
360 (int)(compressed_sz < 0
361 ? -compressed_sz : compressed_sz));
362 /* for statistical purposes
363 */
364 zftc_wr_compressed += (compressed_sz < 0
365 ? -compressed_sz : compressed_sz);
366 zftc_wr_uncompressed += in_sz;
367 }
368 TRACE_EXIT (int)compressed_sz;
369}
370
371/* called by zft_compress_read() to decompress the data. Must
372 * return the size of the decompressed data for sanity checks
373 * (compared with zft_blk_sz)
374 *
375 * NOTE: Read the note for zft_compress() above! If bit 15 of the
376 * parameter in_sz is set, then the data in in_buffer isn't
377 * compressed, which must be handled by the un-compression
378 * algorithm. (I changed lzrw3 to handle this.)
379 *
380 * The parameter max_out_sz is needed to prevent buffer overruns when
381 * uncompressing corrupt data.
382 */
383static unsigned int zft_uncompress(__u8 *in_buffer,
384 int in_sz,
385 __u8 *out_buffer,
386 unsigned int max_out_sz)
387{
388 TRACE_FUN(ft_t_flow);
389
390 lzrw3_compress(COMPRESS_ACTION_DECOMPRESS, zftc_wrk_mem,
391 in_buffer, (__s32)in_sz,
392 out_buffer, (__u32 *)&max_out_sz);
393
394 if (TRACE_LEVEL >= ft_t_info) {
395 TRACE(ft_t_data_flow, "\n"
396 KERN_INFO "before decompression: %d bytes\n"
397 KERN_INFO "after decompression : %d bytes",
398 in_sz < 0 ? -in_sz : in_sz,(int)max_out_sz);
399 /* for statistical purposes
400 */
401 zftc_rd_compressed += in_sz < 0 ? -in_sz : in_sz;
402 zftc_rd_uncompressed += max_out_sz;
403 }
404 TRACE_EXIT (unsigned int)max_out_sz;
405}
406
407/* print some statistics about the efficiency of the compression to
408 * the kernel log
409 */
410static void zftc_stats(void)
411{
412 TRACE_FUN(ft_t_flow);
413
414 if (TRACE_LEVEL < ft_t_info) {
415 TRACE_EXIT;
416 }
417 if (zftc_wr_uncompressed != 0) {
418 if (zftc_wr_compressed > (1<<14)) {
419 TRACE(ft_t_info, "compression statistics (writing):\n"
420 KERN_INFO " compr./uncmpr. : %3d %%",
421 (((zftc_wr_compressed>>10) * 100)
422 / (zftc_wr_uncompressed>>10)));
423 } else {
424 TRACE(ft_t_info, "compression statistics (writing):\n"
425 KERN_INFO " compr./uncmpr. : %3d %%",
426 ((zftc_wr_compressed * 100)
427 / zftc_wr_uncompressed));
428 }
429 }
430 if (zftc_rd_uncompressed != 0) {
431 if (zftc_rd_compressed > (1<<14)) {
432 TRACE(ft_t_info, "compression statistics (reading):\n"
433 KERN_INFO " compr./uncmpr. : %3d %%",
434 (((zftc_rd_compressed>>10) * 100)
435 / (zftc_rd_uncompressed>>10)));
436 } else {
437 TRACE(ft_t_info, "compression statistics (reading):\n"
438 KERN_INFO " compr./uncmpr. : %3d %%",
439 ((zftc_rd_compressed * 100)
440 / zftc_rd_uncompressed));
441 }
442 }
443 /* only print it once: */
444 zftc_wr_uncompressed =
445 zftc_wr_compressed =
446 zftc_rd_uncompressed =
447 zftc_rd_compressed = 0;
448 TRACE_EXIT;
449}
450
451/* start new compressed block
452 */
453static int start_new_cseg(cmpr_info *cluster,
454 char *dst_buf,
455 const zft_position *pos,
456 const unsigned int blk_sz,
457 const char *src_buf,
458 const int this_segs_sz,
459 const int qic113)
460{
461 int size_left;
462 int cp_cnt;
463 int buf_pos;
464 TRACE_FUN(ft_t_flow);
465
466 size_left = this_segs_sz - sizeof(__u16) - cluster->cmpr_sz;
467 TRACE(ft_t_data_flow,"\n"
468 KERN_INFO "segment size : %d\n"
469 KERN_INFO "compressed_sz: %d\n"
470 KERN_INFO "size_left : %d",
471 this_segs_sz, cluster->cmpr_sz, size_left);
472 if (size_left > 18) { /* start a new cluseter */
473 cp_cnt = cluster->cmpr_sz;
474 cluster->cmpr_sz = 0;
475 buf_pos = cp_cnt + sizeof(__u16);
476 PUT2(dst_buf, 0, buf_pos);
477
478 if (qic113) {
479 __s64 foffs = pos->volume_pos;
480 if (cp_cnt) foffs += (__s64)blk_sz;
481
482 TRACE(ft_t_data_flow, "new style QIC-113 header");
483 PUT8(dst_buf, buf_pos, foffs);
484 buf_pos += sizeof(__s64);
485 } else {
486 __u32 foffs = (__u32)pos->volume_pos;
487 if (cp_cnt) foffs += (__u32)blk_sz;
488
489 TRACE(ft_t_data_flow, "old style QIC-80MC header");
490 PUT4(dst_buf, buf_pos, foffs);
491 buf_pos += sizeof(__u32);
492 }
493 } else if (size_left >= 0) {
494 cp_cnt = cluster->cmpr_sz;
495 cluster->cmpr_sz = 0;
496 buf_pos = cp_cnt + sizeof(__u16);
497 PUT2(dst_buf, 0, buf_pos);
498 /* zero unused part of segment. */
499 memset(dst_buf + buf_pos, '\0', size_left);
500 buf_pos = this_segs_sz;
501 } else { /* need entire segment and more space */
502 PUT2(dst_buf, 0, 0);
503 cp_cnt = this_segs_sz - sizeof(__u16);
504 cluster->cmpr_sz -= cp_cnt;
505 buf_pos = this_segs_sz;
506 }
507 memcpy(dst_buf + sizeof(__u16), src_buf + cluster->cmpr_pos, cp_cnt);
508 cluster->cmpr_pos += cp_cnt;
509 TRACE_EXIT buf_pos;
510}
511
512/* return-value: the number of bytes removed from the user-buffer
513 * `src_buf' or error code
514 *
515 * int *write_cnt : how much actually has been moved to the
516 * dst_buf. Need not be initialized when
517 * function returns with an error code
518 * (negativ return value)
519 * __u8 *dst_buf : kernel space buffer where the has to be
520 * copied to. The contents of this buffers
521 * goes to a specific segment.
522 * const int seg_sz : the size of the segment dst_buf will be
523 * copied to.
524 * const zft_position *pos : struct containing the coordinates in
525 * the current volume (byte position,
526 * segment id of current segment etc)
527 * const zft_volinfo *volume: information about the current volume,
528 * size etc.
529 * const __u8 *src_buf : user space buffer that contains the
530 * data the user wants to be written to
531 * tape.
532 * const int req_len : the amount of data the user wants to be
533 * written to tape.
534 */
535static int zftc_write(int *write_cnt,
536 __u8 *dst_buf, const int seg_sz,
537 const __u8 __user *src_buf, const int req_len,
538 const zft_position *pos, const zft_volinfo *volume)
539{
540 int req_len_left = req_len;
541 int result;
542 int len_left;
543 int buf_pos_write = pos->seg_byte_pos;
544 TRACE_FUN(ft_t_flow);
545
546 /* Note: we do not unlock the module because
547 * there are some values cached in that `cseg' variable. We
548 * don't don't want to use this information when being
549 * unloaded by kerneld even when the tape is full or when we
550 * cannot allocate enough memory.
551 */
552 if (pos->tape_pos > (volume->size-volume->blk_sz-ZFT_CMPR_OVERHEAD)) {
553 TRACE_EXIT -ENOSPC;
554 }
555 if (zft_allocate_cmpr_mem(volume->blk_sz) < 0) {
556 /* should we unlock the module? But it shouldn't
557 * be locked anyway ...
558 */
559 TRACE_EXIT -ENOMEM;
560 }
561 if (buf_pos_write == 0) { /* fill a new segment */
562 *write_cnt = buf_pos_write = start_new_cseg(&cseg,
563 dst_buf,
564 pos,
565 volume->blk_sz,
566 zftc_buf,
567 seg_sz,
568 volume->qic113);
569 if (cseg.cmpr_sz == 0 && cseg.cmpr_pos != 0) {
570 req_len_left -= result = volume->blk_sz;
571 cseg.cmpr_pos = 0;
572 } else {
573 result = 0;
574 }
575 } else {
576 *write_cnt = result = 0;
577 }
578
579 len_left = seg_sz - buf_pos_write;
580 while ((req_len_left > 0) && (len_left > 18)) {
581 /* now we have some size left for a new compressed
582 * block. We know, that the compression buffer is
583 * empty (else there wouldn't be any space left).
584 */
585 if (copy_from_user(zftc_scratch_buf, src_buf + result,
586 volume->blk_sz) != 0) {
587 TRACE_EXIT -EFAULT;
588 }
589 req_len_left -= volume->blk_sz;
590 cseg.cmpr_sz = zft_compress(zftc_scratch_buf, volume->blk_sz,
591 zftc_buf);
592 if (cseg.cmpr_sz < 0) {
593 cseg.uncmpr = 0x8000;
594 cseg.cmpr_sz = -cseg.cmpr_sz;
595 } else {
596 cseg.uncmpr = 0;
597 }
598 /* increment "result" iff we copied the entire
599 * compressed block to the zft_deblock_buf
600 */
601 len_left -= sizeof(__u16);
602 if (len_left >= cseg.cmpr_sz) {
603 len_left -= cseg.count = cseg.cmpr_sz;
604 cseg.cmpr_pos = cseg.cmpr_sz = 0;
605 result += volume->blk_sz;
606 } else {
607 cseg.cmpr_sz -=
608 cseg.cmpr_pos =
609 cseg.count = len_left;
610 len_left = 0;
611 }
612 PUT2(dst_buf, buf_pos_write, cseg.uncmpr | cseg.count);
613 buf_pos_write += sizeof(__u16);
614 memcpy(dst_buf + buf_pos_write, zftc_buf, cseg.count);
615 buf_pos_write += cseg.count;
616 *write_cnt += cseg.count + sizeof(__u16);
617 FT_SIGNAL_EXIT(_DONT_BLOCK);
618 }
619 /* erase the remainder of the segment if less than 18 bytes
620 * left (18 bytes is due to the QIC-80 standard)
621 */
622 if (len_left <= 18) {
623 memset(dst_buf + buf_pos_write, '\0', len_left);
624 (*write_cnt) += len_left;
625 }
626 TRACE(ft_t_data_flow, "returning %d", result);
627 TRACE_EXIT result;
628}
629
630/* out:
631 *
632 * int *read_cnt: the number of bytes we removed from the zft_deblock_buf
633 * (result)
634 * int *to_do : the remaining size of the read-request.
635 *
636 * in:
637 *
638 * char *buff : buff is the address of the upper part of the user
639 * buffer, that hasn't been filled with data yet.
640
641 * int buf_pos_read : copy of from _ftape_read()
642 * int buf_len_read : copy of buf_len_rd from _ftape_read()
643 * char *zft_deblock_buf: zft_deblock_buf
644 * unsigned short blk_sz: the block size valid for this volume, may differ
645 * from zft_blk_sz.
646 * int finish: if != 0 means that this is the last segment belonging
647 * to this volume
648 * returns the amount of data actually copied to the user-buffer
649 *
650 * to_do MUST NOT SHRINK except to indicate an EOF. In this case *to_do has to
651 * be set to 0
652 */
653static int zftc_read (int *read_cnt,
654 __u8 __user *dst_buf, const int to_do,
655 const __u8 *src_buf, const int seg_sz,
656 const zft_position *pos, const zft_volinfo *volume)
657{
658 int uncompressed_sz;
659 int result = 0;
660 int remaining = to_do;
661 TRACE_FUN(ft_t_flow);
662
663 TRACE_CATCH(zft_allocate_cmpr_mem(volume->blk_sz),);
664 if (pos->seg_byte_pos == 0) {
665 /* new segment just read
666 */
667 TRACE_CATCH(get_cseg(&cseg, src_buf, seg_sz, volume),
668 *read_cnt = 0);
669 memcpy(zftc_buf + cseg.cmpr_pos, src_buf + sizeof(__u16),
670 cseg.count);
671 cseg.cmpr_pos += cseg.count;
672 *read_cnt = cseg.offset;
673 DUMP_CMPR_INFO(ft_t_noise /* ft_t_any */, "", &cseg);
674 } else {
675 *read_cnt = 0;
676 }
677 /* loop and uncompress until user buffer full or
678 * deblock-buffer empty
679 */
680 TRACE(ft_t_data_flow, "compressed_sz: %d, compos : %d, *read_cnt: %d",
681 cseg.cmpr_sz, cseg.cmpr_pos, *read_cnt);
682 while ((cseg.spans == 0) && (remaining > 0)) {
683 if (cseg.cmpr_pos != 0) { /* cmpr buf is not empty */
684 uncompressed_sz =
685 zft_uncompress(zftc_buf,
686 cseg.uncmpr == 0x8000 ?
687 -cseg.cmpr_pos : cseg.cmpr_pos,
688 zftc_scratch_buf,
689 volume->blk_sz);
690 if (uncompressed_sz != volume->blk_sz) {
691 *read_cnt = 0;
692 TRACE_ABORT(-EIO, ft_t_warn,
693 "Uncompressed blk (%d) != blk size (%d)",
694 uncompressed_sz, volume->blk_sz);
695 }
696 if (copy_to_user(dst_buf + result,
697 zftc_scratch_buf,
698 uncompressed_sz) != 0 ) {
699 TRACE_EXIT -EFAULT;
700 }
701 remaining -= uncompressed_sz;
702 result += uncompressed_sz;
703 cseg.cmpr_pos = 0;
704 }
705 if (remaining > 0) {
706 get_next_cluster(&cseg, src_buf, seg_sz,
707 volume->end_seg == pos->seg_pos);
708 if (cseg.count != 0) {
709 memcpy(zftc_buf, src_buf + cseg.offset,
710 cseg.count);
711 cseg.cmpr_pos = cseg.count;
712 cseg.offset += cseg.count;
713 *read_cnt += cseg.count + sizeof(__u16);
714 } else {
715 remaining = 0;
716 }
717 }
718 TRACE(ft_t_data_flow, "\n"
719 KERN_INFO "compressed_sz: %d\n"
720 KERN_INFO "compos : %d\n"
721 KERN_INFO "*read_cnt : %d",
722 cseg.cmpr_sz, cseg.cmpr_pos, *read_cnt);
723 }
724 if (seg_sz - cseg.offset <= 18) {
725 *read_cnt += seg_sz - cseg.offset;
726 TRACE(ft_t_data_flow, "expanding read cnt to: %d", *read_cnt);
727 }
728 TRACE(ft_t_data_flow, "\n"
729 KERN_INFO "segment size : %d\n"
730 KERN_INFO "read count : %d\n"
731 KERN_INFO "buf_pos_read : %d\n"
732 KERN_INFO "remaining : %d",
733 seg_sz, *read_cnt, pos->seg_byte_pos,
734 seg_sz - *read_cnt - pos->seg_byte_pos);
735 TRACE(ft_t_data_flow, "returning: %d", result);
736 TRACE_EXIT result;
737}
738
739/* seeks to the new data-position. Reads sometimes a segment.
740 *
741 * start_seg and end_seg give the boundaries of the current volume
742 * blk_sz is the blk_sz of the current volume as stored in the
743 * volume label
744 *
745 * We don't allow blocksizes less than 1024 bytes, therefore we don't need
746 * a 64 bit argument for new_block_pos.
747 */
748
749static int seek_in_segment(const unsigned int to_do, cmpr_info *c_info,
750 const char *src_buf, const int seg_sz,
751 const int seg_pos, const zft_volinfo *volume);
752static int slow_seek_forward_until_error(const unsigned int distance,
753 cmpr_info *c_info, zft_position *pos,
754 const zft_volinfo *volume, __u8 *buf);
755static int search_valid_segment(unsigned int segment,
756 const unsigned int end_seg,
757 const unsigned int max_foffs,
758 zft_position *pos, cmpr_info *c_info,
759 const zft_volinfo *volume, __u8 *buf);
760static int slow_seek_forward(unsigned int dest, cmpr_info *c_info,
761 zft_position *pos, const zft_volinfo *volume,
762 __u8 *buf);
763static int compute_seg_pos(unsigned int dest, zft_position *pos,
764 const zft_volinfo *volume);
765
766#define ZFT_SLOW_SEEK_THRESHOLD 10 /* segments */
767#define ZFT_FAST_SEEK_MAX_TRIALS 10 /* times */
768#define ZFT_FAST_SEEK_BACKUP 10 /* segments */
769
770static int zftc_seek(unsigned int new_block_pos,
771 zft_position *pos, const zft_volinfo *volume, __u8 *buf)
772{
773 unsigned int dest;
774 int limit;
775 int distance;
776 int result = 0;
777 int seg_dist;
778 int new_seg;
779 int old_seg = 0;
780 int fast_seek_trials = 0;
781 TRACE_FUN(ft_t_flow);
782
783 if (new_block_pos == 0) {
784 pos->seg_pos = volume->start_seg;
785 pos->seg_byte_pos = 0;
786 pos->volume_pos = 0;
787 zftc_reset();
788 TRACE_EXIT 0;
789 }
790 dest = new_block_pos * (volume->blk_sz >> 10);
791 distance = dest - (pos->volume_pos >> 10);
792 while (distance != 0) {
793 seg_dist = compute_seg_pos(dest, pos, volume);
794 TRACE(ft_t_noise, "\n"
795 KERN_INFO "seg_dist: %d\n"
796 KERN_INFO "distance: %d\n"
797 KERN_INFO "dest : %d\n"
798 KERN_INFO "vpos : %d\n"
799 KERN_INFO "seg_pos : %d\n"
800 KERN_INFO "trials : %d",
801 seg_dist, distance, dest,
802 (unsigned int)(pos->volume_pos>>10), pos->seg_pos,
803 fast_seek_trials);
804 if (distance > 0) {
805 if (seg_dist < 0) {
806 TRACE(ft_t_bug, "BUG: distance %d > 0, "
807 "segment difference %d < 0",
808 distance, seg_dist);
809 result = -EIO;
810 break;
811 }
812 new_seg = pos->seg_pos + seg_dist;
813 if (new_seg > volume->end_seg) {
814 new_seg = volume->end_seg;
815 }
816 if (old_seg == new_seg || /* loop */
817 seg_dist <= ZFT_SLOW_SEEK_THRESHOLD ||
818 fast_seek_trials >= ZFT_FAST_SEEK_MAX_TRIALS) {
819 TRACE(ft_t_noise, "starting slow seek:\n"
820 KERN_INFO "fast seek failed too often: %s\n"
821 KERN_INFO "near target position : %s\n"
822 KERN_INFO "looping between two segs : %s",
823 (fast_seek_trials >=
824 ZFT_FAST_SEEK_MAX_TRIALS)
825 ? "yes" : "no",
826 (seg_dist <= ZFT_SLOW_SEEK_THRESHOLD)
827 ? "yes" : "no",
828 (old_seg == new_seg)
829 ? "yes" : "no");
830 result = slow_seek_forward(dest, &cseg,
831 pos, volume, buf);
832 break;
833 }
834 old_seg = new_seg;
835 limit = volume->end_seg;
836 fast_seek_trials ++;
837 for (;;) {
838 result = search_valid_segment(new_seg, limit,
839 volume->size,
840 pos, &cseg,
841 volume, buf);
842 if (result == 0 || result == -EINTR) {
843 break;
844 }
845 if (new_seg == volume->start_seg) {
846 result = -EIO; /* set errror
847 * condition
848 */
849 break;
850 }
851 limit = new_seg;
852 new_seg -= ZFT_FAST_SEEK_BACKUP;
853 if (new_seg < volume->start_seg) {
854 new_seg = volume->start_seg;
855 }
856 }
857 if (result < 0) {
858 TRACE(ft_t_warn,
859 "Couldn't find a readable segment");
860 break;
861 }
862 } else /* if (distance < 0) */ {
863 if (seg_dist > 0) {
864 TRACE(ft_t_bug, "BUG: distance %d < 0, "
865 "segment difference %d >0",
866 distance, seg_dist);
867 result = -EIO;
868 break;
869 }
870 new_seg = pos->seg_pos + seg_dist;
871 if (fast_seek_trials > 0 && seg_dist == 0) {
872 /* this avoids sticking to the same
873 * segment all the time. On the other hand:
874 * if we got here for the first time, and the
875 * deblock_buffer still contains a valid
876 * segment, then there is no need to skip to
877 * the previous segment if the desired position
878 * is inside this segment.
879 */
880 new_seg --;
881 }
882 if (new_seg < volume->start_seg) {
883 new_seg = volume->start_seg;
884 }
885 limit = pos->seg_pos;
886 fast_seek_trials ++;
887 for (;;) {
888 result = search_valid_segment(new_seg, limit,
889 pos->volume_pos,
890 pos, &cseg,
891 volume, buf);
892 if (result == 0 || result == -EINTR) {
893 break;
894 }
895 if (new_seg == volume->start_seg) {
896 result = -EIO; /* set errror
897 * condition
898 */
899 break;
900 }
901 limit = new_seg;
902 new_seg -= ZFT_FAST_SEEK_BACKUP;
903 if (new_seg < volume->start_seg) {
904 new_seg = volume->start_seg;
905 }
906 }
907 if (result < 0) {
908 TRACE(ft_t_warn,
909 "Couldn't find a readable segment");
910 break;
911 }
912 }
913 distance = dest - (pos->volume_pos >> 10);
914 }
915 TRACE_EXIT result;
916}
917
918
919/* advance inside the given segment at most to_do bytes.
920 * of kilobytes moved
921 */
922
923static int seek_in_segment(const unsigned int to_do,
924 cmpr_info *c_info,
925 const char *src_buf,
926 const int seg_sz,
927 const int seg_pos,
928 const zft_volinfo *volume)
929{
930 int result = 0;
931 int blk_sz = volume->blk_sz >> 10;
932 int remaining = to_do;
933 TRACE_FUN(ft_t_flow);
934
935 if (c_info->offset == 0) {
936 /* new segment just read
937 */
938 TRACE_CATCH(get_cseg(c_info, src_buf, seg_sz, volume),);
939 c_info->cmpr_pos += c_info->count;
940 DUMP_CMPR_INFO(ft_t_noise, "", c_info);
941 }
942 /* loop and uncompress until user buffer full or
943 * deblock-buffer empty
944 */
945 TRACE(ft_t_noise, "compressed_sz: %d, compos : %d",
946 c_info->cmpr_sz, c_info->cmpr_pos);
947 while (c_info->spans == 0 && remaining > 0) {
948 if (c_info->cmpr_pos != 0) { /* cmpr buf is not empty */
949 result += blk_sz;
950 remaining -= blk_sz;
951 c_info->cmpr_pos = 0;
952 }
953 if (remaining > 0) {
954 get_next_cluster(c_info, src_buf, seg_sz,
955 volume->end_seg == seg_pos);
956 if (c_info->count != 0) {
957 c_info->cmpr_pos = c_info->count;
958 c_info->offset += c_info->count;
959 } else {
960 break;
961 }
962 }
963 /* Allow escape from this loop on signal!
964 */
965 FT_SIGNAL_EXIT(_DONT_BLOCK);
966 DUMP_CMPR_INFO(ft_t_noise, "", c_info);
967 TRACE(ft_t_noise, "to_do: %d", remaining);
968 }
969 if (seg_sz - c_info->offset <= 18) {
970 c_info->offset = seg_sz;
971 }
972 TRACE(ft_t_noise, "\n"
973 KERN_INFO "segment size : %d\n"
974 KERN_INFO "buf_pos_read : %d\n"
975 KERN_INFO "remaining : %d",
976 seg_sz, c_info->offset,
977 seg_sz - c_info->offset);
978 TRACE_EXIT result;
979}
980
981static int slow_seek_forward_until_error(const unsigned int distance,
982 cmpr_info *c_info,
983 zft_position *pos,
984 const zft_volinfo *volume,
985 __u8 *buf)
986{
987 unsigned int remaining = distance;
988 int seg_sz;
989 int seg_pos;
990 int result;
991 TRACE_FUN(ft_t_flow);
992
993 seg_pos = pos->seg_pos;
994 do {
995 TRACE_CATCH(seg_sz = zft_fetch_segment(seg_pos, buf,
996 FT_RD_AHEAD),);
997 /* now we have the contents of the actual segment in
998 * the deblock buffer
999 */
1000 TRACE_CATCH(result = seek_in_segment(remaining, c_info, buf,
1001 seg_sz, seg_pos,volume),);
1002 remaining -= result;
1003 pos->volume_pos += result<<10;
1004 pos->seg_pos = seg_pos;
1005 pos->seg_byte_pos = c_info->offset;
1006 seg_pos ++;
1007 if (seg_pos <= volume->end_seg && c_info->offset == seg_sz) {
1008 pos->seg_pos ++;
1009 pos->seg_byte_pos = 0;
1010 c_info->offset = 0;
1011 }
1012 /* Allow escape from this loop on signal!
1013 */
1014 FT_SIGNAL_EXIT(_DONT_BLOCK);
1015 TRACE(ft_t_noise, "\n"
1016 KERN_INFO "remaining: %d\n"
1017 KERN_INFO "seg_pos: %d\n"
1018 KERN_INFO "end_seg: %d\n"
1019 KERN_INFO "result: %d",
1020 remaining, seg_pos, volume->end_seg, result);
1021 } while (remaining > 0 && seg_pos <= volume->end_seg);
1022 TRACE_EXIT 0;
1023}
1024
1025/* return segment id of next segment containing valid data, -EIO otherwise
1026 */
1027static int search_valid_segment(unsigned int segment,
1028 const unsigned int end_seg,
1029 const unsigned int max_foffs,
1030 zft_position *pos,
1031 cmpr_info *c_info,
1032 const zft_volinfo *volume,
1033 __u8 *buf)
1034{
1035 cmpr_info tmp_info;
1036 int seg_sz;
1037 TRACE_FUN(ft_t_flow);
1038
1039 memset(&tmp_info, 0, sizeof(cmpr_info));
1040 while (segment <= end_seg) {
1041 FT_SIGNAL_EXIT(_DONT_BLOCK);
1042 TRACE(ft_t_noise,
1043 "Searching readable segment between %d and %d",
1044 segment, end_seg);
1045 seg_sz = zft_fetch_segment(segment, buf, FT_RD_AHEAD);
1046 if ((seg_sz > 0) &&
1047 (get_cseg (&tmp_info, buf, seg_sz, volume) >= 0) &&
1048 (tmp_info.foffs != 0 || segment == volume->start_seg)) {
1049 if ((tmp_info.foffs>>10) > max_foffs) {
1050 TRACE_ABORT(-EIO, ft_t_noise, "\n"
1051 KERN_INFO "cseg.foff: %d\n"
1052 KERN_INFO "dest : %d",
1053 (int)(tmp_info.foffs >> 10),
1054 max_foffs);
1055 }
1056 DUMP_CMPR_INFO(ft_t_noise, "", &tmp_info);
1057 *c_info = tmp_info;
1058 pos->seg_pos = segment;
1059 pos->volume_pos = c_info->foffs;
1060 pos->seg_byte_pos = c_info->offset;
1061 TRACE(ft_t_noise, "found segment at %d", segment);
1062 TRACE_EXIT 0;
1063 }
1064 segment++;
1065 }
1066 TRACE_EXIT -EIO;
1067}
1068
1069static int slow_seek_forward(unsigned int dest,
1070 cmpr_info *c_info,
1071 zft_position *pos,
1072 const zft_volinfo *volume,
1073 __u8 *buf)
1074{
1075 unsigned int distance;
1076 int result = 0;
1077 TRACE_FUN(ft_t_flow);
1078
1079 distance = dest - (pos->volume_pos >> 10);
1080 while ((distance > 0) &&
1081 (result = slow_seek_forward_until_error(distance,
1082 c_info,
1083 pos,
1084 volume,
1085 buf)) < 0) {
1086 if (result == -EINTR) {
1087 break;
1088 }
1089 TRACE(ft_t_noise, "seg_pos: %d", pos->seg_pos);
1090 /* the failing segment is either pos->seg_pos or
1091 * pos->seg_pos + 1. There is no need to further try
1092 * that segment, because ftape_read_segment() already
1093 * has tried very much to read it. So we start with
1094 * following segment, which is pos->seg_pos + 1
1095 */
1096 if(search_valid_segment(pos->seg_pos+1, volume->end_seg, dest,
1097 pos, c_info,
1098 volume, buf) < 0) {
1099 TRACE(ft_t_noise, "search_valid_segment() failed");
1100 result = -EIO;
1101 break;
1102 }
1103 distance = dest - (pos->volume_pos >> 10);
1104 result = 0;
1105 TRACE(ft_t_noise, "segment: %d", pos->seg_pos);
1106 /* found valid segment, retry the seek */
1107 }
1108 TRACE_EXIT result;
1109}
1110
1111static int compute_seg_pos(const unsigned int dest,
1112 zft_position *pos,
1113 const zft_volinfo *volume)
1114{
1115 int segment;
1116 int distance = dest - (pos->volume_pos >> 10);
1117 unsigned int raw_size;
1118 unsigned int virt_size;
1119 unsigned int factor;
1120 TRACE_FUN(ft_t_flow);
1121
1122 if (distance >= 0) {
1123 raw_size = volume->end_seg - pos->seg_pos + 1;
1124 virt_size = ((unsigned int)(volume->size>>10)
1125 - (unsigned int)(pos->volume_pos>>10)
1126 + FT_SECTORS_PER_SEGMENT - FT_ECC_SECTORS - 1);
1127 virt_size /= FT_SECTORS_PER_SEGMENT - FT_ECC_SECTORS;
1128 if (virt_size == 0 || raw_size == 0) {
1129 TRACE_EXIT 0;
1130 }
1131 if (raw_size >= (1<<25)) {
1132 factor = raw_size/(virt_size>>7);
1133 } else {
1134 factor = (raw_size<<7)/virt_size;
1135 }
1136 segment = distance/(FT_SECTORS_PER_SEGMENT-FT_ECC_SECTORS);
1137 segment = (segment * factor)>>7;
1138 } else {
1139 raw_size = pos->seg_pos - volume->start_seg + 1;
1140 virt_size = ((unsigned int)(pos->volume_pos>>10)
1141 + FT_SECTORS_PER_SEGMENT - FT_ECC_SECTORS - 1);
1142 virt_size /= FT_SECTORS_PER_SEGMENT - FT_ECC_SECTORS;
1143 if (virt_size == 0 || raw_size == 0) {
1144 TRACE_EXIT 0;
1145 }
1146 if (raw_size >= (1<<25)) {
1147 factor = raw_size/(virt_size>>7);
1148 } else {
1149 factor = (raw_size<<7)/virt_size;
1150 }
1151 segment = distance/(FT_SECTORS_PER_SEGMENT-FT_ECC_SECTORS);
1152 }
1153 TRACE(ft_t_noise, "factor: %d/%d", factor, 1<<7);
1154 TRACE_EXIT segment;
1155}
1156
1157static struct zft_cmpr_ops cmpr_ops = {
1158 zftc_write,
1159 zftc_read,
1160 zftc_seek,
1161 zftc_lock,
1162 zftc_reset,
1163 zftc_cleanup
1164};
1165
1166int zft_compressor_init(void)
1167{
1168 TRACE_FUN(ft_t_flow);
1169
1170#ifdef MODULE
1171 printk(KERN_INFO "zftape compressor v1.00a 970514 for " FTAPE_VERSION "\n");
1172 if (TRACE_LEVEL >= ft_t_info) {
1173 printk(
1174KERN_INFO "(c) 1997 Claus-Justus Heine (claus@momo.math.rwth-aachen.de)\n"
1175KERN_INFO "Compressor for zftape (lzrw3 algorithm)\n");
1176 }
1177#else /* !MODULE */
1178 /* print a short no-nonsense boot message */
1179 printk(KERN_INFO "zftape compressor v1.00a 970514\n");
1180 printk(KERN_INFO "For use with " FTAPE_VERSION "\n");
1181#endif /* MODULE */
1182 TRACE(ft_t_info, "zft_compressor_init @ 0x%p", zft_compressor_init);
1183 TRACE(ft_t_info, "installing compressor for zftape ...");
1184 TRACE_CATCH(zft_cmpr_register(&cmpr_ops),);
1185 TRACE_EXIT 0;
1186}
1187
1188#ifdef MODULE
1189
1190MODULE_AUTHOR(
1191 "(c) 1996, 1997 Claus-Justus Heine (claus@momo.math.rwth-aachen.de");
1192MODULE_DESCRIPTION(
1193"Compression routines for zftape. Uses the lzrw3 algorithm by Ross Williams");
1194MODULE_LICENSE("GPL");
1195
1196/* Called by modules package when installing the driver
1197 */
1198int init_module(void)
1199{
1200 return zft_compressor_init();
1201}
1202
1203#endif /* MODULE */
diff --git a/drivers/char/ftape/compressor/zftape-compress.h b/drivers/char/ftape/compressor/zftape-compress.h
deleted file mode 100644
index f200741e33bf..000000000000
--- a/drivers/char/ftape/compressor/zftape-compress.h
+++ /dev/null
@@ -1,83 +0,0 @@
1#ifndef _ZFTAPE_COMPRESS_H
2#define _ZFTAPE_COMPRESS_H
3/*
4 * Copyright (c) 1994-1997 Claus-Justus Heine
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 2, or (at
9 your option) any later version.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
19 USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/compressor/zftape-compress.h,v $
23 * $Revision: 1.1 $
24 * $Date: 1997/10/05 19:12:32 $
25 *
26 * This file contains macros and definitions for zftape's
27 * builtin compression code.
28 *
29 */
30
31#include "../zftape/zftape-buffers.h"
32#include "../zftape/zftape-vtbl.h"
33#include "../compressor/lzrw3.h"
34
35/* CMPR_WRK_MEM_SIZE gives the size of the compression wrk_mem */
36/* I got these out of lzrw3.c */
37#define U(X) ((__u32) X)
38#define SIZE_P_BYTE (U(sizeof(__u8 *)))
39#define ALIGNMENT_FUDGE (U(16))
40
41#define CMPR_WRK_MEM_SIZE (U(4096)*(SIZE_P_BYTE) + ALIGNMENT_FUDGE)
42
43/* the maximum number of bytes the size of the "compressed" data can
44 * exceed the uncompressed data. As it is quite useless to compress
45 * data twice it is sometimes the case that it is more efficient to
46 * copy a block of data but to feed it to the "compression"
47 * algorithm. In this case there are some flag bytes or the like
48 * proceding the "compressed" data. THAT MUST NOT BE THE CASE for the
49 * algorithm we use for this driver. Instead, the high bit 15 of
50 * compressed_size:
51 *
52 * compressed_size = ftape_compress()
53 *
54 * must be set in such a case.
55 *
56 * Nevertheless, it might also be as for lzrw3 that there is an
57 * "intermediate" overrun that exceeds the amount of the compressed
58 * data that is actually produced. During the algorithm we need in the
59 * worst case MAX_CMP_GROUP bytes more than the input-size.
60 */
61#define MAX_CMP_GROUP (2+16*2) /* from lzrw3.c */
62
63#define CMPR_OVERRUN MAX_CMP_GROUP /* during compression */
64
65/****************************************************/
66
67#define CMPR_BUFFER_SIZE (MAX_BLOCK_SIZE + CMPR_OVERRUN)
68
69/* the compression map stores the byte offset compressed blocks within
70 * the current volume for catridges with format code 2,3 and 5
71 * (and old versions of zftape) and the offset measured in kilobytes for
72 * format code 4 and 6. This gives us a possible max. size of a
73 * compressed volume of 1024*4GIG which should be enough.
74 */
75typedef __u32 CmprMap;
76
77/* globals
78 */
79
80/* exported functions
81 */
82
83#endif /* _ZFTAPE_COMPRESS_H */
diff --git a/drivers/char/ftape/lowlevel/Makefile b/drivers/char/ftape/lowlevel/Makefile
deleted file mode 100644
index febab07ba427..000000000000
--- a/drivers/char/ftape/lowlevel/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
1#
2# Copyright (C) 1996, 1997 Clau-Justus Heine.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2, or (at your option)
7# any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; see the file COPYING. If not, write to
16# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17#
18# $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/Makefile,v $
19# $Revision: 1.4 $
20# $Date: 1997/10/07 09:26:02 $
21#
22# Makefile for the lowlevel part QIC-40/80/3010/3020 floppy-tape
23# driver for Linux.
24#
25
26obj-$(CONFIG_FTAPE) += ftape.o
27
28ftape-objs := ftape-init.o fdc-io.o fdc-isr.o \
29 ftape-bsm.o ftape-ctl.o ftape-read.o ftape-rw.o \
30 ftape-write.o ftape-io.o ftape-calibr.o ftape-ecc.o fc-10.o \
31 ftape-buffer.o ftape-format.o ftape_syms.o
32
33ifeq ($(CONFIG_FTAPE),y)
34ftape-objs += ftape-setup.o
35endif
36
37ifndef CONFIG_FT_NO_TRACE_AT_ALL
38ftape-objs += ftape-tracing.o
39endif
40
41ifeq ($(CONFIG_FT_PROC_FS),y)
42ftape-objs += ftape-proc.o
43endif
diff --git a/drivers/char/ftape/lowlevel/fc-10.c b/drivers/char/ftape/lowlevel/fc-10.c
deleted file mode 100644
index 9bc1cddade76..000000000000
--- a/drivers/char/ftape/lowlevel/fc-10.c
+++ /dev/null
@@ -1,175 +0,0 @@
1/*
2 *
3
4 Copyright (C) 1993,1994 Jon Tombs.
5
6 This program is distributed in the hope that it will be useful,
7 but WITHOUT ANY WARRANTY; without even the implied warranty of
8 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 GNU General Public License for more details.
10
11 The entire guts of this program was written by dosemu, modified to
12 record reads and writes to the ports in the 0x180-0x188 address space,
13 while running the CMS program TAPE.EXE V2.0.5 supplied with the drive.
14
15 Modified to use an array of addresses and generally cleaned up (made
16 much shorter) 4 June 94, dosemu isn't that good at writing short code it
17 would seem :-). Made independent of 0x180, but I doubt it will work
18 at any other address.
19
20 Modified for distribution with ftape source. 21 June 94, SJL.
21
22 Modifications on 20 October 95, by Daniel Cohen (catman@wpi.edu):
23 Modified to support different DMA, IRQ, and IO Ports. Borland's
24 Turbo Debugger in virtual 8086 mode (TD386.EXE with hardware breakpoints
25 provided by the TDH386.SYS Device Driver) was used on the CMS program
26 TAPE V4.0.5. I set breakpoints on I/O to ports 0x180-0x187. Note that
27 CMS's program will not successfully configure the tape drive if you set
28 breakpoints on IO Reads, but you can set them on IO Writes without problems.
29 Known problems:
30 - You can not use DMA Channels 5 or 7.
31
32 Modification on 29 January 96, by Daniel Cohen (catman@wpi.edu):
33 Modified to only accept IRQs 3 - 7, or 9. Since we can only send a 3 bit
34 number representing the IRQ to the card, special handling is required when
35 IRQ 9 is selected. IRQ 2 and 9 are the same, and we should request IRQ 9
36 from the kernel while telling the card to use IRQ 2. Thanks to Greg
37 Crider (gcrider@iclnet.org) for finding and locating this bug, as well as
38 testing the patch.
39
40 Modification on 11 December 96, by Claus Heine (claus@momo.math.rwth-aachen.de):
41 Modified a little to use variahle ft_fdc_base, ft_fdc_irq, ft_fdc_dma
42 instead of preprocessor symbols. Thus we can compile this into the module
43 or kernel and let the user specify the options as command line arguments.
44
45 *
46 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fc-10.c,v $
47 * $Revision: 1.2 $
48 * $Date: 1997/10/05 19:18:04 $
49 *
50 * This file contains code for the CMS FC-10/FC-20 card.
51 */
52
53#include <asm/io.h>
54#include <linux/ftape.h>
55#include "../lowlevel/ftape-tracing.h"
56#include "../lowlevel/fdc-io.h"
57#include "../lowlevel/fc-10.h"
58
59static __u16 inbs_magic[] = {
60 0x3, 0x3, 0x0, 0x4, 0x7, 0x2, 0x5, 0x3, 0x1, 0x4,
61 0x3, 0x5, 0x2, 0x0, 0x3, 0x7, 0x4, 0x2,
62 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
63};
64
65static __u16 fc10_ports[] = {
66 0x180, 0x210, 0x2A0, 0x300, 0x330, 0x340, 0x370
67};
68
69int fc10_enable(void)
70{
71 int i;
72 __u8 cardConfig = 0x00;
73 __u8 x;
74 TRACE_FUN(ft_t_flow);
75
76/* This code will only work if the FC-10 (or FC-20) is set to
77 * use DMA channels 1, 2, or 3. DMA channels 5 and 7 seem to be
78 * initialized by the same command as channels 1 and 3, respectively.
79 */
80 if (ft_fdc_dma > 3) {
81 TRACE_ABORT(0, ft_t_err,
82"Error: The FC-10/20 must be set to use DMA channels 1, 2, or 3!");
83 }
84/* Only allow the FC-10/20 to use IRQ 3-7, or 9. Note that CMS's program
85 * only accepts IRQ's 2-7, but in linux, IRQ 2 is the same as IRQ 9.
86 */
87 if (ft_fdc_irq < 3 || ft_fdc_irq == 8 || ft_fdc_irq > 9) {
88 TRACE_ABORT(0, ft_t_err,
89"Error: The FC-10/20 must be set to use IRQ levels 3 - 7, or 9!\n"
90KERN_INFO "Note: IRQ 9 is the same as IRQ 2");
91 }
92 /* Clear state machine ???
93 */
94 for (i = 0; i < NR_ITEMS(inbs_magic); i++) {
95 inb(ft_fdc_base + inbs_magic[i]);
96 }
97 outb(0x0, ft_fdc_base);
98
99 x = inb(ft_fdc_base);
100 if (x == 0x13 || x == 0x93) {
101 for (i = 1; i < 8; i++) {
102 if (inb(ft_fdc_base + i) != x) {
103 TRACE_EXIT 0;
104 }
105 }
106 } else {
107 TRACE_EXIT 0;
108 }
109
110 outb(0x8, ft_fdc_base);
111
112 for (i = 0; i < 8; i++) {
113 if (inb(ft_fdc_base + i) != 0x0) {
114 TRACE_EXIT 0;
115 }
116 }
117 outb(0x10, ft_fdc_base);
118
119 for (i = 0; i < 8; i++) {
120 if (inb(ft_fdc_base + i) != 0xff) {
121 TRACE_EXIT 0;
122 }
123 }
124
125 /* Okay, we found a FC-10 card ! ???
126 */
127 outb(0x0, fdc.ccr);
128
129 /* Clear state machine again ???
130 */
131 for (i = 0; i < NR_ITEMS(inbs_magic); i++) {
132 inb(ft_fdc_base + inbs_magic[i]);
133 }
134 /* Send io port */
135 for (i = 0; i < NR_ITEMS(fc10_ports); i++)
136 if (ft_fdc_base == fc10_ports[i])
137 cardConfig = i + 1;
138 if (cardConfig == 0) {
139 TRACE_EXIT 0; /* Invalid I/O Port */
140 }
141 /* and IRQ - If using IRQ 9, tell the FC card it is actually IRQ 2 */
142 if (ft_fdc_irq != 9)
143 cardConfig |= ft_fdc_irq << 3;
144 else
145 cardConfig |= 2 << 3;
146
147 /* and finally DMA Channel */
148 cardConfig |= ft_fdc_dma << 6;
149 outb(cardConfig, ft_fdc_base); /* DMA [2 bits]/IRQ [3 bits]/BASE [3 bits] */
150
151 /* Enable FC-10 ???
152 */
153 outb(0, fdc.ccr);
154 outb(0, fdc.dor2);
155 outb(FDC_DMA_MODE /* 8 */, fdc.dor);
156 outb(FDC_DMA_MODE /* 8 */, fdc.dor);
157 outb(1, fdc.dor2);
158
159 /*************************************
160 *
161 * cH: why the hell should this be necessary? This is done
162 * by fdc_reset()!!!
163 *
164 *************************************/
165 /* Initialize fdc, select drive B:
166 */
167 outb(FDC_DMA_MODE, fdc.dor); /* assert reset, dma & irq enabled */
168 /* 0x08 */
169 outb(FDC_DMA_MODE|FDC_RESET_NOT, fdc.dor); /* release reset */
170 /* 0x08 | 0x04 = 0x0c */
171 outb(FDC_DMA_MODE|FDC_RESET_NOT|FDC_MOTOR_1|FTAPE_SEL_B, fdc.dor);
172 /* 0x08 | 0x04 | 0x20 | 0x01 = 0x2d */
173 /* select drive 1 */ /* why not drive 0 ???? */
174 TRACE_EXIT (x == 0x93) ? 2 : 1;
175}
diff --git a/drivers/char/ftape/lowlevel/fc-10.h b/drivers/char/ftape/lowlevel/fc-10.h
deleted file mode 100644
index da7b88bca889..000000000000
--- a/drivers/char/ftape/lowlevel/fc-10.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef _FC_10_H
2#define _FC_10_H
3
4/*
5 * Copyright (C) 1994-1996 Bas Laarhoven.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fc-10.h,v $
23 * $Revision: 1.1 $
24 * $Date: 1997/09/19 09:05:22 $
25 *
26 * This file contains definitions for the FC-10 code
27 * of the QIC-40/80 floppy-tape driver for Linux.
28 */
29
30/*
31 * fc-10.c defined global vars.
32 */
33
34/*
35 * fc-10.c defined global functions.
36 */
37extern int fc10_enable(void);
38
39#endif
diff --git a/drivers/char/ftape/lowlevel/fdc-io.c b/drivers/char/ftape/lowlevel/fdc-io.c
deleted file mode 100644
index bbcf918f056f..000000000000
--- a/drivers/char/ftape/lowlevel/fdc-io.c
+++ /dev/null
@@ -1,1349 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fdc-io.c,v $
21 * $Revision: 1.7.4.2 $
22 * $Date: 1997/11/16 14:48:17 $
23 *
24 * This file contains the low-level floppy disk interface code
25 * for the QIC-40/80/3010/3020 floppy-tape driver "ftape" for
26 * Linux.
27 */
28
29#include <linux/errno.h>
30#include <linux/sched.h>
31#include <linux/ioport.h>
32#include <linux/interrupt.h>
33#include <linux/kernel.h>
34#include <asm/system.h>
35#include <asm/io.h>
36#include <asm/dma.h>
37#include <asm/irq.h>
38
39#include <linux/ftape.h>
40#include <linux/qic117.h>
41#include "../lowlevel/ftape-tracing.h"
42#include "../lowlevel/fdc-io.h"
43#include "../lowlevel/fdc-isr.h"
44#include "../lowlevel/ftape-io.h"
45#include "../lowlevel/ftape-rw.h"
46#include "../lowlevel/ftape-ctl.h"
47#include "../lowlevel/ftape-calibr.h"
48#include "../lowlevel/fc-10.h"
49
50/* Global vars.
51 */
52static int ftape_motor;
53volatile int ftape_current_cylinder = -1;
54volatile fdc_mode_enum fdc_mode = fdc_idle;
55fdc_config_info fdc;
56DECLARE_WAIT_QUEUE_HEAD(ftape_wait_intr);
57
58unsigned int ft_fdc_base = CONFIG_FT_FDC_BASE;
59unsigned int ft_fdc_irq = CONFIG_FT_FDC_IRQ;
60unsigned int ft_fdc_dma = CONFIG_FT_FDC_DMA;
61unsigned int ft_fdc_threshold = CONFIG_FT_FDC_THR; /* bytes */
62unsigned int ft_fdc_rate_limit = CONFIG_FT_FDC_MAX_RATE; /* bits/sec */
63int ft_probe_fc10 = CONFIG_FT_PROBE_FC10;
64int ft_mach2 = CONFIG_FT_MACH2;
65
66/* Local vars.
67 */
68static spinlock_t fdc_io_lock;
69static unsigned int fdc_calibr_count;
70static unsigned int fdc_calibr_time;
71static int fdc_status;
72volatile __u8 fdc_head; /* FDC head from sector id */
73volatile __u8 fdc_cyl; /* FDC track from sector id */
74volatile __u8 fdc_sect; /* FDC sector from sector id */
75static int fdc_data_rate = 500; /* data rate (Kbps) */
76static int fdc_rate_code; /* data rate code (0 == 500 Kbps) */
77static int fdc_seek_rate = 2; /* step rate (msec) */
78static void (*do_ftape) (void);
79static int fdc_fifo_state; /* original fifo setting - fifo enabled */
80static int fdc_fifo_thr; /* original fifo setting - threshold */
81static int fdc_lock_state; /* original lock setting - locked */
82static int fdc_fifo_locked; /* has fifo && lock set ? */
83static __u8 fdc_precomp; /* default precomp. value (nsec) */
84static __u8 fdc_prec_code; /* fdc precomp. select code */
85
86static char ftape_id[] = "ftape"; /* used by request irq and free irq */
87
88static int fdc_set_seek_rate(int seek_rate);
89
90void fdc_catch_stray_interrupts(int count)
91{
92 unsigned long flags;
93
94 spin_lock_irqsave(&fdc_io_lock, flags);
95 if (count == 0) {
96 ft_expected_stray_interrupts = 0;
97 } else {
98 ft_expected_stray_interrupts += count;
99 }
100 spin_unlock_irqrestore(&fdc_io_lock, flags);
101}
102
103/* Wait during a timeout period for a given FDC status.
104 * If usecs == 0 then just test status, else wait at least for usecs.
105 * Returns -ETIME on timeout. Function must be calibrated first !
106 */
107static int fdc_wait(unsigned int usecs, __u8 mask, __u8 state)
108{
109 int count_1 = (fdc_calibr_count * usecs +
110 fdc_calibr_count - 1) / fdc_calibr_time;
111
112 do {
113 fdc_status = inb_p(fdc.msr);
114 if ((fdc_status & mask) == state) {
115 return 0;
116 }
117 } while (count_1-- >= 0);
118 return -ETIME;
119}
120
121int fdc_ready_wait(unsigned int usecs)
122{
123 return fdc_wait(usecs, FDC_DATA_READY | FDC_BUSY, FDC_DATA_READY);
124}
125
126/* Why can't we just use udelay()?
127 */
128static void fdc_usec_wait(unsigned int usecs)
129{
130 fdc_wait(usecs, 0, 1); /* will always timeout ! */
131}
132
133static int fdc_ready_out_wait(unsigned int usecs)
134{
135 fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
136 return fdc_wait(usecs, FDC_DATA_OUT_READY, FDC_DATA_OUT_READY);
137}
138
139void fdc_wait_calibrate(void)
140{
141 ftape_calibrate("fdc_wait",
142 fdc_usec_wait, &fdc_calibr_count, &fdc_calibr_time);
143}
144
145/* Wait for a (short) while for the FDC to become ready
146 * and transfer the next command byte.
147 * Return -ETIME on timeout on getting ready (depends on hardware!).
148 */
149static int fdc_write(const __u8 data)
150{
151 fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
152 if (fdc_wait(150, FDC_DATA_READY_MASK, FDC_DATA_IN_READY) < 0) {
153 return -ETIME;
154 } else {
155 outb(data, fdc.fifo);
156 return 0;
157 }
158}
159
160/* Wait for a (short) while for the FDC to become ready
161 * and transfer the next result byte.
162 * Return -ETIME if timeout on getting ready (depends on hardware!).
163 */
164static int fdc_read(__u8 * data)
165{
166 fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
167 if (fdc_wait(150, FDC_DATA_READY_MASK, FDC_DATA_OUT_READY) < 0) {
168 return -ETIME;
169 } else {
170 *data = inb(fdc.fifo);
171 return 0;
172 }
173}
174
175/* Output a cmd_len long command string to the FDC.
176 * The FDC should be ready to receive a new command or
177 * an error (EBUSY or ETIME) will occur.
178 */
179int fdc_command(const __u8 * cmd_data, int cmd_len)
180{
181 int result = 0;
182 unsigned long flags;
183 int count = cmd_len;
184 int retry = 0;
185#ifdef TESTING
186 static unsigned int last_time;
187 unsigned int time;
188#endif
189 TRACE_FUN(ft_t_any);
190
191 fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
192 spin_lock_irqsave(&fdc_io_lock, flags);
193 if (!in_interrupt())
194 /* Yes, I know, too much comments inside this function
195 * ...
196 *
197 * Yet another bug in the original driver. All that
198 * havoc is caused by the fact that the isr() sends
199 * itself a command to the floppy tape driver (pause,
200 * micro step pause). Now, the problem is that
201 * commands are transmitted via the fdc_seek
202 * command. But: the fdc performs seeks in the
203 * background i.e. it doesn't signal busy while
204 * sending the step pulses to the drive. Therefore the
205 * non-interrupt level driver has no chance to tell
206 * whether the isr() just has issued a seek. Therefore
207 * we HAVE TO have a look at the ft_hide_interrupt
208 * flag: it signals the non-interrupt level part of
209 * the driver that it has to wait for the fdc until it
210 * has completet seeking.
211 *
212 * THIS WAS PRESUMABLY THE REASON FOR ALL THAT
213 * "fdc_read timeout" errors, I HOPE :-)
214 */
215 if (ft_hide_interrupt) {
216 restore_flags(flags);
217 TRACE(ft_t_info,
218 "Waiting for the isr() completing fdc_seek()");
219 if (fdc_interrupt_wait(2 * FT_SECOND) < 0) {
220 TRACE(ft_t_warn,
221 "Warning: timeout waiting for isr() seek to complete");
222 }
223 if (ft_hide_interrupt || !ft_seek_completed) {
224 /* There cannot be another
225 * interrupt. The isr() only stops
226 * the tape and the next interrupt
227 * won't come until we have send our
228 * command to the drive.
229 */
230 TRACE_ABORT(-EIO, ft_t_bug,
231 "BUG? isr() is still seeking?\n"
232 KERN_INFO "hide: %d\n"
233 KERN_INFO "seek: %d",
234 ft_hide_interrupt,
235 ft_seek_completed);
236
237 }
238 fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
239 spin_lock_irqsave(&fdc_io_lock, flags);
240 }
241 fdc_status = inb(fdc.msr);
242 if ((fdc_status & FDC_DATA_READY_MASK) != FDC_DATA_IN_READY) {
243 spin_unlock_irqrestore(&fdc_io_lock, flags);
244 TRACE_ABORT(-EBUSY, ft_t_err, "fdc not ready");
245 }
246 fdc_mode = *cmd_data; /* used by isr */
247#ifdef TESTING
248 if (fdc_mode == FDC_SEEK) {
249 time = ftape_timediff(last_time, ftape_timestamp());
250 if (time < 6000) {
251 TRACE(ft_t_bug,"Warning: short timeout between seek commands: %d",
252 time);
253 }
254 }
255#endif
256 if (!in_interrupt()) {
257 /* shouldn't be cleared if called from isr
258 */
259 ft_interrupt_seen = 0;
260 }
261 while (count) {
262 result = fdc_write(*cmd_data);
263 if (result < 0) {
264 TRACE(ft_t_fdc_dma,
265 "fdc_mode = %02x, status = %02x at index %d",
266 (int) fdc_mode, (int) fdc_status,
267 cmd_len - count);
268 if (++retry <= 3) {
269 TRACE(ft_t_warn, "fdc_write timeout, retry");
270 } else {
271 TRACE(ft_t_err, "fdc_write timeout, fatal");
272 /* recover ??? */
273 break;
274 }
275 } else {
276 --count;
277 ++cmd_data;
278 }
279 }
280#ifdef TESTING
281 if (fdc_mode == FDC_SEEK) {
282 last_time = ftape_timestamp();
283 }
284#endif
285 spin_unlock_irqrestore(&fdc_io_lock, flags);
286 TRACE_EXIT result;
287}
288
289/* Input a res_len long result string from the FDC.
290 * The FDC should be ready to send the result or an error
291 * (EBUSY or ETIME) will occur.
292 */
293int fdc_result(__u8 * res_data, int res_len)
294{
295 int result = 0;
296 unsigned long flags;
297 int count = res_len;
298 int retry = 0;
299 TRACE_FUN(ft_t_any);
300
301 spin_lock_irqsave(&fdc_io_lock, flags);
302 fdc_status = inb(fdc.msr);
303 if ((fdc_status & FDC_DATA_READY_MASK) != FDC_DATA_OUT_READY) {
304 TRACE(ft_t_err, "fdc not ready");
305 result = -EBUSY;
306 } else while (count) {
307 if (!(fdc_status & FDC_BUSY)) {
308 spin_unlock_irqrestore(&fdc_io_lock, flags);
309 TRACE_ABORT(-EIO, ft_t_err, "premature end of result phase");
310 }
311 result = fdc_read(res_data);
312 if (result < 0) {
313 TRACE(ft_t_fdc_dma,
314 "fdc_mode = %02x, status = %02x at index %d",
315 (int) fdc_mode,
316 (int) fdc_status,
317 res_len - count);
318 if (++retry <= 3) {
319 TRACE(ft_t_warn, "fdc_read timeout, retry");
320 } else {
321 TRACE(ft_t_err, "fdc_read timeout, fatal");
322 /* recover ??? */
323 break;
324 ++retry;
325 }
326 } else {
327 --count;
328 ++res_data;
329 }
330 }
331 spin_unlock_irqrestore(&fdc_io_lock, flags);
332 fdc_usec_wait(FT_RQM_DELAY); /* allow FDC to negate BSY */
333 TRACE_EXIT result;
334}
335
336/* Handle command and result phases for
337 * commands without data phase.
338 */
339static int fdc_issue_command(const __u8 * out_data, int out_count,
340 __u8 * in_data, int in_count)
341{
342 TRACE_FUN(ft_t_any);
343
344 if (out_count > 0) {
345 TRACE_CATCH(fdc_command(out_data, out_count),);
346 }
347 /* will take 24 - 30 usec for fdc_sense_drive_status and
348 * fdc_sense_interrupt_status commands.
349 * 35 fails sometimes (5/9/93 SJL)
350 * On a loaded system it incidentally takes longer than
351 * this for the fdc to get ready ! ?????? WHY ??????
352 * So until we know what's going on use a very long timeout.
353 */
354 TRACE_CATCH(fdc_ready_out_wait(500 /* usec */),);
355 if (in_count > 0) {
356 TRACE_CATCH(fdc_result(in_data, in_count),
357 TRACE(ft_t_err, "result phase aborted"));
358 }
359 TRACE_EXIT 0;
360}
361
362/* Wait for FDC interrupt with timeout (in milliseconds).
363 * Signals are blocked so the wait will not be aborted.
364 * Note: interrupts must be enabled ! (23/05/93 SJL)
365 */
366int fdc_interrupt_wait(unsigned int time)
367{
368 DECLARE_WAITQUEUE(wait,current);
369 sigset_t old_sigmask;
370 static int resetting;
371 long timeout;
372
373 TRACE_FUN(ft_t_fdc_dma);
374
375 if (waitqueue_active(&ftape_wait_intr)) {
376 TRACE_ABORT(-EIO, ft_t_err, "error: nested call");
377 }
378 /* timeout time will be up to USPT microseconds too long ! */
379 timeout = (1000 * time + FT_USPT - 1) / FT_USPT;
380
381 spin_lock_irq(&current->sighand->siglock);
382 old_sigmask = current->blocked;
383 sigfillset(&current->blocked);
384 recalc_sigpending();
385 spin_unlock_irq(&current->sighand->siglock);
386
387 set_current_state(TASK_INTERRUPTIBLE);
388 add_wait_queue(&ftape_wait_intr, &wait);
389 while (!ft_interrupt_seen && timeout)
390 timeout = schedule_timeout_interruptible(timeout);
391
392 spin_lock_irq(&current->sighand->siglock);
393 current->blocked = old_sigmask;
394 recalc_sigpending();
395 spin_unlock_irq(&current->sighand->siglock);
396
397 remove_wait_queue(&ftape_wait_intr, &wait);
398 /* the following IS necessary. True: as well
399 * wake_up_interruptible() as the schedule() set TASK_RUNNING
400 * when they wakeup a task, BUT: it may very well be that
401 * ft_interrupt_seen is already set to 1 when we enter here
402 * in which case schedule() gets never called, and
403 * TASK_RUNNING never set. This has the funny effect that we
404 * execute all the code until we leave kernel space, but then
405 * the task is stopped (a task CANNOT be preempted while in
406 * kernel mode. Sending a pair of SIGSTOP/SIGCONT to the
407 * tasks wakes it up again. Funny! :-)
408 */
409 current->state = TASK_RUNNING;
410 if (ft_interrupt_seen) { /* woken up by interrupt */
411 ft_interrupt_seen = 0;
412 TRACE_EXIT 0;
413 }
414 /* Original comment:
415 * In first instance, next statement seems unnecessary since
416 * it will be cleared in fdc_command. However, a small part of
417 * the software seems to rely on this being cleared here
418 * (ftape_close might fail) so stick to it until things get fixed !
419 */
420 /* My deeply sought of knowledge:
421 * Behold NO! It is obvious. fdc_reset() doesn't call fdc_command()
422 * but nevertheless uses fdc_interrupt_wait(). OF COURSE this needs to
423 * be reset here.
424 */
425 ft_interrupt_seen = 0; /* clear for next call */
426 if (!resetting) {
427 resetting = 1; /* break infinite recursion if reset fails */
428 TRACE(ft_t_any, "cleanup reset");
429 fdc_reset();
430 resetting = 0;
431 }
432 TRACE_EXIT (signal_pending(current)) ? -EINTR : -ETIME;
433}
434
435/* Start/stop drive motor. Enable DMA mode.
436 */
437void fdc_motor(int motor)
438{
439 int unit = ft_drive_sel;
440 int data = unit | FDC_RESET_NOT | FDC_DMA_MODE;
441 TRACE_FUN(ft_t_any);
442
443 ftape_motor = motor;
444 if (ftape_motor) {
445 data |= FDC_MOTOR_0 << unit;
446 TRACE(ft_t_noise, "turning motor %d on", unit);
447 } else {
448 TRACE(ft_t_noise, "turning motor %d off", unit);
449 }
450 if (ft_mach2) {
451 outb_p(data, fdc.dor2);
452 } else {
453 outb_p(data, fdc.dor);
454 }
455 ftape_sleep(10 * FT_MILLISECOND);
456 TRACE_EXIT;
457}
458
459static void fdc_update_dsr(void)
460{
461 TRACE_FUN(ft_t_any);
462
463 TRACE(ft_t_flow, "rate = %d Kbps, precomp = %d ns",
464 fdc_data_rate, fdc_precomp);
465 if (fdc.type >= i82077) {
466 outb_p((fdc_rate_code & 0x03) | fdc_prec_code, fdc.dsr);
467 } else {
468 outb_p(fdc_rate_code & 0x03, fdc.ccr);
469 }
470 TRACE_EXIT;
471}
472
473void fdc_set_write_precomp(int precomp)
474{
475 TRACE_FUN(ft_t_any);
476
477 TRACE(ft_t_noise, "New precomp: %d nsec", precomp);
478 fdc_precomp = precomp;
479 /* write precompensation can be set in multiples of 41.67 nsec.
480 * round the parameter to the nearest multiple and convert it
481 * into a fdc setting. Note that 0 means default to the fdc,
482 * 7 is used instead of that.
483 */
484 fdc_prec_code = ((fdc_precomp + 21) / 42) << 2;
485 if (fdc_prec_code == 0 || fdc_prec_code > (6 << 2)) {
486 fdc_prec_code = 7 << 2;
487 }
488 fdc_update_dsr();
489 TRACE_EXIT;
490}
491
492/* Reprogram the 82078 registers to use Data Rate Table 1 on all drives.
493 */
494static void fdc_set_drive_specs(void)
495{
496 __u8 cmd[] = { FDC_DRIVE_SPEC, 0x00, 0x00, 0x00, 0x00, 0xc0};
497 int result;
498 TRACE_FUN(ft_t_any);
499
500 TRACE(ft_t_flow, "Setting of drive specs called");
501 if (fdc.type >= i82078_1) {
502 cmd[1] = (0 << 5) | (2 << 2);
503 cmd[2] = (1 << 5) | (2 << 2);
504 cmd[3] = (2 << 5) | (2 << 2);
505 cmd[4] = (3 << 5) | (2 << 2);
506 result = fdc_command(cmd, NR_ITEMS(cmd));
507 if (result < 0) {
508 TRACE(ft_t_err, "Setting of drive specs failed");
509 }
510 }
511 TRACE_EXIT;
512}
513
514/* Select clock for fdc, must correspond with tape drive setting !
515 * This also influences the fdc timing so we must adjust some values.
516 */
517int fdc_set_data_rate(int rate)
518{
519 int bad_rate = 0;
520 TRACE_FUN(ft_t_any);
521
522 /* Select clock for fdc, must correspond with tape drive setting !
523 * This also influences the fdc timing so we must adjust some values.
524 */
525 TRACE(ft_t_fdc_dma, "new rate = %d", rate);
526 switch (rate) {
527 case 250:
528 fdc_rate_code = fdc_data_rate_250;
529 break;
530 case 500:
531 fdc_rate_code = fdc_data_rate_500;
532 break;
533 case 1000:
534 if (fdc.type < i82077) {
535 bad_rate = 1;
536 } else {
537 fdc_rate_code = fdc_data_rate_1000;
538 }
539 break;
540 case 2000:
541 if (fdc.type < i82078_1) {
542 bad_rate = 1;
543 } else {
544 fdc_rate_code = fdc_data_rate_2000;
545 }
546 break;
547 default:
548 bad_rate = 1;
549 }
550 if (bad_rate) {
551 TRACE_ABORT(-EIO,
552 ft_t_fdc_dma, "%d is not a valid data rate", rate);
553 }
554 fdc_data_rate = rate;
555 fdc_update_dsr();
556 fdc_set_seek_rate(fdc_seek_rate); /* clock changed! */
557 ftape_udelay(1000);
558 TRACE_EXIT 0;
559}
560
561/* keep the unit select if keep_select is != 0,
562 */
563static void fdc_dor_reset(int keep_select)
564{
565 __u8 fdc_ctl = ft_drive_sel;
566
567 if (keep_select != 0) {
568 fdc_ctl |= FDC_DMA_MODE;
569 if (ftape_motor) {
570 fdc_ctl |= FDC_MOTOR_0 << ft_drive_sel;
571 }
572 }
573 ftape_udelay(10); /* ??? but seems to be necessary */
574 if (ft_mach2) {
575 outb_p(fdc_ctl & 0x0f, fdc.dor);
576 outb_p(fdc_ctl, fdc.dor2);
577 } else {
578 outb_p(fdc_ctl, fdc.dor);
579 }
580 fdc_usec_wait(10); /* delay >= 14 fdc clocks */
581 if (keep_select == 0) {
582 fdc_ctl = 0;
583 }
584 fdc_ctl |= FDC_RESET_NOT;
585 if (ft_mach2) {
586 outb_p(fdc_ctl & 0x0f, fdc.dor);
587 outb_p(fdc_ctl, fdc.dor2);
588 } else {
589 outb_p(fdc_ctl, fdc.dor);
590 }
591}
592
593/* Reset the floppy disk controller. Leave the ftape_unit selected.
594 */
595void fdc_reset(void)
596{
597 int st0;
598 int i;
599 int dummy;
600 unsigned long flags;
601 TRACE_FUN(ft_t_any);
602
603 spin_lock_irqsave(&fdc_io_lock, flags);
604
605 fdc_dor_reset(1); /* keep unit selected */
606
607 fdc_mode = fdc_idle;
608
609 /* maybe the spin_lock_irq* pair is not necessary, BUT:
610 * the following line MUST be here. Otherwise fdc_interrupt_wait()
611 * won't wait. Note that fdc_reset() is called from
612 * ftape_dumb_stop() when the fdc is busy transferring data. In this
613 * case fdc_isr() MOST PROBABLY sets ft_interrupt_seen, and tries
614 * to get the result bytes from the fdc etc. CLASH.
615 */
616 ft_interrupt_seen = 0;
617
618 /* Program data rate
619 */
620 fdc_update_dsr(); /* restore data rate and precomp */
621
622 spin_unlock_irqrestore(&fdc_io_lock, flags);
623
624 /*
625 * Wait for first polling cycle to complete
626 */
627 if (fdc_interrupt_wait(1 * FT_SECOND) < 0) {
628 TRACE(ft_t_err, "no drive polling interrupt!");
629 } else { /* clear all disk-changed statuses */
630 for (i = 0; i < 4; ++i) {
631 if(fdc_sense_interrupt_status(&st0, &dummy) != 0) {
632 TRACE(ft_t_err, "sense failed for %d", i);
633 }
634 if (i == ft_drive_sel) {
635 ftape_current_cylinder = dummy;
636 }
637 }
638 TRACE(ft_t_noise, "drive polling completed");
639 }
640 /*
641 * SPECIFY COMMAND
642 */
643 fdc_set_seek_rate(fdc_seek_rate);
644 /*
645 * DRIVE SPECIFICATION COMMAND (if fdc type known)
646 */
647 if (fdc.type >= i82078_1) {
648 fdc_set_drive_specs();
649 }
650 TRACE_EXIT;
651}
652
653#if !defined(CLK_48MHZ)
654# define CLK_48MHZ 1
655#endif
656
657/* When we're done, put the fdc into reset mode so that the regular
658 * floppy disk driver will figure out that something is wrong and
659 * initialize the controller the way it wants.
660 */
661void fdc_disable(void)
662{
663 __u8 cmd1[] = {FDC_CONFIGURE, 0x00, 0x00, 0x00};
664 __u8 cmd2[] = {FDC_LOCK};
665 __u8 cmd3[] = {FDC_UNLOCK};
666 __u8 stat[1];
667 TRACE_FUN(ft_t_flow);
668
669 if (!fdc_fifo_locked) {
670 fdc_reset();
671 TRACE_EXIT;
672 }
673 if (fdc_issue_command(cmd3, 1, stat, 1) < 0 || stat[0] != 0x00) {
674 fdc_dor_reset(0);
675 TRACE_ABORT(/**/, ft_t_bug,
676 "couldn't unlock fifo, configuration remains changed");
677 }
678 fdc_fifo_locked = 0;
679 if (CLK_48MHZ && fdc.type >= i82078) {
680 cmd1[0] |= FDC_CLK48_BIT;
681 }
682 cmd1[2] = ((fdc_fifo_state) ? 0 : 0x20) + (fdc_fifo_thr - 1);
683 if (fdc_command(cmd1, NR_ITEMS(cmd1)) < 0) {
684 fdc_dor_reset(0);
685 TRACE_ABORT(/**/, ft_t_bug,
686 "couldn't reconfigure fifo to old state");
687 }
688 if (fdc_lock_state &&
689 fdc_issue_command(cmd2, 1, stat, 1) < 0) {
690 fdc_dor_reset(0);
691 TRACE_ABORT(/**/, ft_t_bug, "couldn't lock old state again");
692 }
693 TRACE(ft_t_noise, "fifo restored: %sabled, thr. %d, %slocked",
694 fdc_fifo_state ? "en" : "dis",
695 fdc_fifo_thr, (fdc_lock_state) ? "" : "not ");
696 fdc_dor_reset(0);
697 TRACE_EXIT;
698}
699
700/* Specify FDC seek-rate (milliseconds)
701 */
702static int fdc_set_seek_rate(int seek_rate)
703{
704 /* set step rate, dma mode, and minimal head load and unload times
705 */
706 __u8 in[3] = { FDC_SPECIFY, 1, (1 << 1)};
707
708 fdc_seek_rate = seek_rate;
709 in[1] |= (16 - (fdc_data_rate * fdc_seek_rate) / 500) << 4;
710
711 return fdc_command(in, 3);
712}
713
714/* Sense drive status: get unit's drive status (ST3)
715 */
716int fdc_sense_drive_status(int *st3)
717{
718 __u8 out[2];
719 __u8 in[1];
720 TRACE_FUN(ft_t_any);
721
722 out[0] = FDC_SENSED;
723 out[1] = ft_drive_sel;
724 TRACE_CATCH(fdc_issue_command(out, 2, in, 1),);
725 *st3 = in[0];
726 TRACE_EXIT 0;
727}
728
729/* Sense Interrupt Status command:
730 * should be issued at the end of each seek.
731 * get ST0 and current cylinder.
732 */
733int fdc_sense_interrupt_status(int *st0, int *current_cylinder)
734{
735 __u8 out[1];
736 __u8 in[2];
737 TRACE_FUN(ft_t_any);
738
739 out[0] = FDC_SENSEI;
740 TRACE_CATCH(fdc_issue_command(out, 1, in, 2),);
741 *st0 = in[0];
742 *current_cylinder = in[1];
743 TRACE_EXIT 0;
744}
745
746/* step to track
747 */
748int fdc_seek(int track)
749{
750 __u8 out[3];
751 int st0, pcn;
752#ifdef TESTING
753 unsigned int time;
754#endif
755 TRACE_FUN(ft_t_any);
756
757 out[0] = FDC_SEEK;
758 out[1] = ft_drive_sel;
759 out[2] = track;
760#ifdef TESTING
761 time = ftape_timestamp();
762#endif
763 /* We really need this command to work !
764 */
765 ft_seek_completed = 0;
766 TRACE_CATCH(fdc_command(out, 3),
767 fdc_reset();
768 TRACE(ft_t_noise, "destination was: %d, resetting FDC...",
769 track));
770 /* Handle interrupts until ft_seek_completed or timeout.
771 */
772 for (;;) {
773 TRACE_CATCH(fdc_interrupt_wait(2 * FT_SECOND),);
774 if (ft_seek_completed) {
775 TRACE_CATCH(fdc_sense_interrupt_status(&st0, &pcn),);
776 if ((st0 & ST0_SEEK_END) == 0) {
777 TRACE_ABORT(-EIO, ft_t_err,
778 "no seek-end after seek completion !??");
779 }
780 break;
781 }
782 }
783#ifdef TESTING
784 time = ftape_timediff(time, ftape_timestamp()) / abs(track - ftape_current_cylinder);
785 if ((time < 900 || time > 3100) && abs(track - ftape_current_cylinder) > 5) {
786 TRACE(ft_t_warn, "Wrong FDC STEP interval: %d usecs (%d)",
787 time, track - ftape_current_cylinder);
788 }
789#endif
790 /* Verify whether we issued the right tape command.
791 */
792 /* Verify that we seek to the proper track. */
793 if (pcn != track) {
794 TRACE_ABORT(-EIO, ft_t_err, "bad seek..");
795 }
796 ftape_current_cylinder = track;
797 TRACE_EXIT 0;
798}
799
800static int perpend_mode; /* set if fdc is in perpendicular mode */
801
802static int perpend_off(void)
803{
804 __u8 perpend[] = {FDC_PERPEND, 0x00};
805 TRACE_FUN(ft_t_any);
806
807 if (perpend_mode) {
808 /* Turn off perpendicular mode */
809 perpend[1] = 0x80;
810 TRACE_CATCH(fdc_command(perpend, 2),
811 TRACE(ft_t_err,"Perpendicular mode exit failed!"));
812 perpend_mode = 0;
813 }
814 TRACE_EXIT 0;
815}
816
817static int handle_perpend(int segment_id)
818{
819 __u8 perpend[] = {FDC_PERPEND, 0x00};
820 TRACE_FUN(ft_t_any);
821
822 /* When writing QIC-3020 tapes, turn on perpendicular mode
823 * if tape is moving in forward direction (even tracks).
824 */
825 if (ft_qic_std == QIC_TAPE_QIC3020 &&
826 ((segment_id / ft_segments_per_track) & 1) == 0) {
827/* FIXME: some i82077 seem to support perpendicular mode as
828 * well.
829 */
830#if 0
831 if (fdc.type < i82077AA) {}
832#else
833 if (fdc.type < i82077 && ft_data_rate < 1000) {
834#endif
835 /* fdc does not support perpendicular mode: complain
836 */
837 TRACE_ABORT(-EIO, ft_t_err,
838 "Your FDC does not support QIC-3020.");
839 }
840 perpend[1] = 0x03 /* 0x83 + (0x4 << ft_drive_sel) */ ;
841 TRACE_CATCH(fdc_command(perpend, 2),
842 TRACE(ft_t_err,"Perpendicular mode entry failed!"));
843 TRACE(ft_t_flow, "Perpendicular mode set");
844 perpend_mode = 1;
845 TRACE_EXIT 0;
846 }
847 TRACE_EXIT perpend_off();
848}
849
850static inline void fdc_setup_dma(char mode,
851 volatile void *addr, unsigned int count)
852{
853 /* Program the DMA controller.
854 */
855 disable_dma(fdc.dma);
856 clear_dma_ff(fdc.dma);
857 set_dma_mode(fdc.dma, mode);
858 set_dma_addr(fdc.dma, virt_to_bus((void*)addr));
859 set_dma_count(fdc.dma, count);
860 enable_dma(fdc.dma);
861}
862
863/* Setup fdc and dma for formatting the next segment
864 */
865int fdc_setup_formatting(buffer_struct * buff)
866{
867 unsigned long flags;
868 __u8 out[6] = {
869 FDC_FORMAT, 0x00, 3, 4 * FT_SECTORS_PER_SEGMENT, 0x00, 0x6b
870 };
871 TRACE_FUN(ft_t_any);
872
873 TRACE_CATCH(handle_perpend(buff->segment_id),);
874 /* Program the DMA controller.
875 */
876 TRACE(ft_t_fdc_dma,
877 "phys. addr. = %lx", virt_to_bus((void*) buff->ptr));
878 spin_lock_irqsave(&fdc_io_lock, flags);
879 fdc_setup_dma(DMA_MODE_WRITE, buff->ptr, FT_SECTORS_PER_SEGMENT * 4);
880 /* Issue FDC command to start reading/writing.
881 */
882 out[1] = ft_drive_sel;
883 out[4] = buff->gap3;
884 TRACE_CATCH(fdc_setup_error = fdc_command(out, sizeof(out)),
885 restore_flags(flags); fdc_mode = fdc_idle);
886 spin_unlock_irqrestore(&fdc_io_lock, flags);
887 TRACE_EXIT 0;
888}
889
890
891/* Setup Floppy Disk Controller and DMA to read or write the next cluster
892 * of good sectors from or to the current segment.
893 */
894int fdc_setup_read_write(buffer_struct * buff, __u8 operation)
895{
896 unsigned long flags;
897 __u8 out[9];
898 int dma_mode;
899 TRACE_FUN(ft_t_any);
900
901 switch(operation) {
902 case FDC_VERIFY:
903 if (fdc.type < i82077) {
904 operation = FDC_READ;
905 }
906 case FDC_READ:
907 case FDC_READ_DELETED:
908 dma_mode = DMA_MODE_READ;
909 TRACE(ft_t_fdc_dma, "xfer %d sectors to 0x%p",
910 buff->sector_count, buff->ptr);
911 TRACE_CATCH(perpend_off(),);
912 break;
913 case FDC_WRITE_DELETED:
914 TRACE(ft_t_noise, "deleting segment %d", buff->segment_id);
915 case FDC_WRITE:
916 dma_mode = DMA_MODE_WRITE;
917 /* When writing QIC-3020 tapes, turn on perpendicular mode
918 * if tape is moving in forward direction (even tracks).
919 */
920 TRACE_CATCH(handle_perpend(buff->segment_id),);
921 TRACE(ft_t_fdc_dma, "xfer %d sectors from 0x%p",
922 buff->sector_count, buff->ptr);
923 break;
924 default:
925 TRACE_ABORT(-EIO,
926 ft_t_bug, "bug: invalid operation parameter");
927 }
928 TRACE(ft_t_fdc_dma, "phys. addr. = %lx",virt_to_bus((void*)buff->ptr));
929 spin_lock_irqsave(&fdc_io_lock, flags);
930 if (operation != FDC_VERIFY) {
931 fdc_setup_dma(dma_mode, buff->ptr,
932 FT_SECTOR_SIZE * buff->sector_count);
933 }
934 /* Issue FDC command to start reading/writing.
935 */
936 out[0] = operation;
937 out[1] = ft_drive_sel;
938 out[2] = buff->cyl;
939 out[3] = buff->head;
940 out[4] = buff->sect + buff->sector_offset;
941 out[5] = 3; /* Sector size of 1K. */
942 out[6] = out[4] + buff->sector_count - 1; /* last sector */
943 out[7] = 109; /* Gap length. */
944 out[8] = 0xff; /* No limit to transfer size. */
945 TRACE(ft_t_fdc_dma, "C: 0x%02x, H: 0x%02x, R: 0x%02x, cnt: 0x%02x",
946 out[2], out[3], out[4], out[6] - out[4] + 1);
947 spin_unlock_irqrestore(&fdc_io_lock, flags);
948 TRACE_CATCH(fdc_setup_error = fdc_command(out, 9),fdc_mode = fdc_idle);
949 TRACE_EXIT 0;
950}
951
952int fdc_fifo_threshold(__u8 threshold,
953 int *fifo_state, int *lock_state, int *fifo_thr)
954{
955 const __u8 cmd0[] = {FDC_DUMPREGS};
956 __u8 cmd1[] = {FDC_CONFIGURE, 0, (0x0f & (threshold - 1)), 0};
957 const __u8 cmd2[] = {FDC_LOCK};
958 const __u8 cmd3[] = {FDC_UNLOCK};
959 __u8 reg[10];
960 __u8 stat;
961 int i;
962 int result;
963 TRACE_FUN(ft_t_any);
964
965 if (CLK_48MHZ && fdc.type >= i82078) {
966 cmd1[0] |= FDC_CLK48_BIT;
967 }
968 /* Dump fdc internal registers for examination
969 */
970 TRACE_CATCH(fdc_command(cmd0, NR_ITEMS(cmd0)),
971 TRACE(ft_t_warn, "dumpreg cmd failed, fifo unchanged"));
972 /* Now read fdc internal registers from fifo
973 */
974 for (i = 0; i < (int)NR_ITEMS(reg); ++i) {
975 fdc_read(&reg[i]);
976 TRACE(ft_t_fdc_dma, "Register %d = 0x%02x", i, reg[i]);
977 }
978 if (fifo_state && lock_state && fifo_thr) {
979 *fifo_state = (reg[8] & 0x20) == 0;
980 *lock_state = reg[7] & 0x80;
981 *fifo_thr = 1 + (reg[8] & 0x0f);
982 }
983 TRACE(ft_t_noise,
984 "original fifo state: %sabled, threshold %d, %slocked",
985 ((reg[8] & 0x20) == 0) ? "en" : "dis",
986 1 + (reg[8] & 0x0f), (reg[7] & 0x80) ? "" : "not ");
987 /* If fdc is already locked, unlock it first ! */
988 if (reg[7] & 0x80) {
989 fdc_ready_wait(100);
990 TRACE_CATCH(fdc_issue_command(cmd3, NR_ITEMS(cmd3), &stat, 1),
991 TRACE(ft_t_bug, "FDC unlock command failed, "
992 "configuration unchanged"));
993 }
994 fdc_fifo_locked = 0;
995 /* Enable fifo and set threshold at xx bytes to allow a
996 * reasonably large latency and reduce number of dma bursts.
997 */
998 fdc_ready_wait(100);
999 if ((result = fdc_command(cmd1, NR_ITEMS(cmd1))) < 0) {
1000 TRACE(ft_t_bug, "configure cmd failed, fifo unchanged");
1001 }
1002 /* Now lock configuration so reset will not change it
1003 */
1004 if(fdc_issue_command(cmd2, NR_ITEMS(cmd2), &stat, 1) < 0 ||
1005 stat != 0x10) {
1006 TRACE_ABORT(-EIO, ft_t_bug,
1007 "FDC lock command failed, stat = 0x%02x", stat);
1008 }
1009 fdc_fifo_locked = 1;
1010 TRACE_EXIT result;
1011}
1012
1013static int fdc_fifo_enable(void)
1014{
1015 TRACE_FUN(ft_t_any);
1016
1017 if (fdc_fifo_locked) {
1018 TRACE_ABORT(0, ft_t_warn, "Fifo not enabled because locked");
1019 }
1020 TRACE_CATCH(fdc_fifo_threshold(ft_fdc_threshold /* bytes */,
1021 &fdc_fifo_state,
1022 &fdc_lock_state,
1023 &fdc_fifo_thr),);
1024 TRACE_CATCH(fdc_fifo_threshold(ft_fdc_threshold /* bytes */,
1025 NULL, NULL, NULL),);
1026 TRACE_EXIT 0;
1027}
1028
1029/* Determine fd controller type
1030 */
1031static __u8 fdc_save_state[2];
1032
1033static int fdc_probe(void)
1034{
1035 __u8 cmd[1];
1036 __u8 stat[16]; /* must be able to hold dumpregs & save results */
1037 int i;
1038 TRACE_FUN(ft_t_any);
1039
1040 /* Try to find out what kind of fd controller we have to deal with
1041 * Scheme borrowed from floppy driver:
1042 * first try if FDC_DUMPREGS command works
1043 * (this indicates that we have a 82072 or better)
1044 * then try the FDC_VERSION command (82072 doesn't support this)
1045 * then try the FDC_UNLOCK command (some older 82077's don't support this)
1046 * then try the FDC_PARTID command (82078's support this)
1047 */
1048 cmd[0] = FDC_DUMPREGS;
1049 if (fdc_issue_command(cmd, 1, stat, 1) != 0) {
1050 TRACE_ABORT(no_fdc, ft_t_bug, "No FDC found");
1051 }
1052 if (stat[0] == 0x80) {
1053 /* invalid command: must be pre 82072 */
1054 TRACE_ABORT(i8272,
1055 ft_t_warn, "Type 8272A/765A compatible FDC found");
1056 }
1057 fdc_result(&stat[1], 9);
1058 fdc_save_state[0] = stat[7];
1059 fdc_save_state[1] = stat[8];
1060 cmd[0] = FDC_VERSION;
1061 if (fdc_issue_command(cmd, 1, stat, 1) < 0 || stat[0] == 0x80) {
1062 TRACE_ABORT(i8272, ft_t_warn, "Type 82072 FDC found");
1063 }
1064 if (*stat != 0x90) {
1065 TRACE_ABORT(i8272, ft_t_warn, "Unknown FDC found");
1066 }
1067 cmd[0] = FDC_UNLOCK;
1068 if(fdc_issue_command(cmd, 1, stat, 1) < 0 || stat[0] != 0x00) {
1069 TRACE_ABORT(i8272, ft_t_warn,
1070 "Type pre-1991 82077 FDC found, "
1071 "treating it like a 82072");
1072 }
1073 if (fdc_save_state[0] & 0x80) { /* was locked */
1074 cmd[0] = FDC_LOCK; /* restore lock */
1075 (void)fdc_issue_command(cmd, 1, stat, 1);
1076 TRACE(ft_t_warn, "FDC is already locked");
1077 }
1078 /* Test for a i82078 FDC */
1079 cmd[0] = FDC_PARTID;
1080 if (fdc_issue_command(cmd, 1, stat, 1) < 0 || stat[0] == 0x80) {
1081 /* invalid command: not a i82078xx type FDC */
1082 for (i = 0; i < 4; ++i) {
1083 outb_p(i, fdc.tdr);
1084 if ((inb_p(fdc.tdr) & 0x03) != i) {
1085 TRACE_ABORT(i82077,
1086 ft_t_warn, "Type 82077 FDC found");
1087 }
1088 }
1089 TRACE_ABORT(i82077AA, ft_t_warn, "Type 82077AA FDC found");
1090 }
1091 /* FDC_PARTID cmd succeeded */
1092 switch (stat[0] >> 5) {
1093 case 0x0:
1094 /* i82078SL or i82078-1. The SL part cannot run at
1095 * 2Mbps (the SL and -1 dies are identical; they are
1096 * speed graded after production, according to Intel).
1097 * Some SL's can be detected by doing a SAVE cmd and
1098 * look at bit 7 of the first byte (the SEL3V# bit).
1099 * If it is 0, the part runs off 3Volts, and hence it
1100 * is a SL.
1101 */
1102 cmd[0] = FDC_SAVE;
1103 if(fdc_issue_command(cmd, 1, stat, 16) < 0) {
1104 TRACE(ft_t_err, "FDC_SAVE failed. Dunno why");
1105 /* guess we better claim the fdc to be a i82078 */
1106 TRACE_ABORT(i82078,
1107 ft_t_warn,
1108 "Type i82078 FDC (i suppose) found");
1109 }
1110 if ((stat[0] & FDC_SEL3V_BIT)) {
1111 /* fdc running off 5Volts; Pray that it's a i82078-1
1112 */
1113 TRACE_ABORT(i82078_1, ft_t_warn,
1114 "Type i82078-1 or 5Volt i82078SL FDC found");
1115 }
1116 TRACE_ABORT(i82078, ft_t_warn,
1117 "Type 3Volt i82078SL FDC (1Mbps) found");
1118 case 0x1:
1119 case 0x2: /* S82078B */
1120 /* The '78B isn't '78 compatible. Detect it as a '77AA */
1121 TRACE_ABORT(i82077AA, ft_t_warn, "Type i82077AA FDC found");
1122 case 0x3: /* NSC PC8744 core; used in several super-IO chips */
1123 TRACE_ABORT(i82077AA,
1124 ft_t_warn, "Type 82077AA compatible FDC found");
1125 default:
1126 TRACE(ft_t_warn, "A previously undetected FDC found");
1127 TRACE_ABORT(i82077AA, ft_t_warn,
1128 "Treating it as a 82077AA. Please report partid= %d",
1129 stat[0]);
1130 } /* switch(stat[ 0] >> 5) */
1131 TRACE_EXIT no_fdc;
1132}
1133
1134static int fdc_request_regions(void)
1135{
1136 TRACE_FUN(ft_t_flow);
1137
1138 if (ft_mach2 || ft_probe_fc10) {
1139 if (!request_region(fdc.sra, 8, "fdc (ft)")) {
1140#ifndef BROKEN_FLOPPY_DRIVER
1141 TRACE_EXIT -EBUSY;
1142#else
1143 TRACE(ft_t_warn,
1144"address 0x%03x occupied (by floppy driver?), using it anyway", fdc.sra);
1145#endif
1146 }
1147 } else {
1148 if (!request_region(fdc.sra, 6, "fdc (ft)")) {
1149#ifndef BROKEN_FLOPPY_DRIVER
1150 TRACE_EXIT -EBUSY;
1151#else
1152 TRACE(ft_t_warn,
1153"address 0x%03x occupied (by floppy driver?), using it anyway", fdc.sra);
1154#endif
1155 }
1156 if (!request_region(fdc.sra + 7, 1, "fdc (ft)")) {
1157#ifndef BROKEN_FLOPPY_DRIVER
1158 release_region(fdc.sra, 6);
1159 TRACE_EXIT -EBUSY;
1160#else
1161 TRACE(ft_t_warn,
1162"address 0x%03x occupied (by floppy driver?), using it anyway", fdc.sra + 7);
1163#endif
1164 }
1165 }
1166 TRACE_EXIT 0;
1167}
1168
1169void fdc_release_regions(void)
1170{
1171 TRACE_FUN(ft_t_flow);
1172
1173 if (fdc.sra != 0) {
1174 if (fdc.dor2 != 0) {
1175 release_region(fdc.sra, 8);
1176 } else {
1177 release_region(fdc.sra, 6);
1178 release_region(fdc.dir, 1);
1179 }
1180 }
1181 TRACE_EXIT;
1182}
1183
1184static int fdc_config_regs(unsigned int fdc_base,
1185 unsigned int fdc_irq,
1186 unsigned int fdc_dma)
1187{
1188 TRACE_FUN(ft_t_flow);
1189
1190 fdc.irq = fdc_irq;
1191 fdc.dma = fdc_dma;
1192 fdc.sra = fdc_base;
1193 fdc.srb = fdc_base + 1;
1194 fdc.dor = fdc_base + 2;
1195 fdc.tdr = fdc_base + 3;
1196 fdc.msr = fdc.dsr = fdc_base + 4;
1197 fdc.fifo = fdc_base + 5;
1198 fdc.dir = fdc.ccr = fdc_base + 7;
1199 fdc.dor2 = (ft_mach2 || ft_probe_fc10) ? fdc_base + 6 : 0;
1200 TRACE_CATCH(fdc_request_regions(), fdc.sra = 0);
1201 TRACE_EXIT 0;
1202}
1203
1204static int fdc_config(void)
1205{
1206 static int already_done;
1207 TRACE_FUN(ft_t_any);
1208
1209 if (already_done) {
1210 TRACE_CATCH(fdc_request_regions(),);
1211 *(fdc.hook) = fdc_isr; /* hook our handler in */
1212 TRACE_EXIT 0;
1213 }
1214 if (ft_probe_fc10) {
1215 int fc_type;
1216
1217 TRACE_CATCH(fdc_config_regs(ft_fdc_base,
1218 ft_fdc_irq, ft_fdc_dma),);
1219 fc_type = fc10_enable();
1220 if (fc_type != 0) {
1221 TRACE(ft_t_warn, "FC-%c0 controller found", '0' + fc_type);
1222 fdc.type = fc10;
1223 fdc.hook = &do_ftape;
1224 *(fdc.hook) = fdc_isr; /* hook our handler in */
1225 already_done = 1;
1226 TRACE_EXIT 0;
1227 } else {
1228 TRACE(ft_t_warn, "FC-10/20 controller not found");
1229 fdc_release_regions();
1230 fdc.type = no_fdc;
1231 ft_probe_fc10 = 0;
1232 ft_fdc_base = 0x3f0;
1233 ft_fdc_irq = 6;
1234 ft_fdc_dma = 2;
1235 }
1236 }
1237 TRACE(ft_t_warn, "fdc base: 0x%x, irq: %d, dma: %d",
1238 ft_fdc_base, ft_fdc_irq, ft_fdc_dma);
1239 TRACE_CATCH(fdc_config_regs(ft_fdc_base, ft_fdc_irq, ft_fdc_dma),);
1240 fdc.hook = &do_ftape;
1241 *(fdc.hook) = fdc_isr; /* hook our handler in */
1242 already_done = 1;
1243 TRACE_EXIT 0;
1244}
1245
1246static irqreturn_t ftape_interrupt(int irq, void *dev_id)
1247{
1248 void (*handler) (void) = *fdc.hook;
1249 int handled = 0;
1250 TRACE_FUN(ft_t_any);
1251
1252 *fdc.hook = NULL;
1253 if (handler) {
1254 handled = 1;
1255 handler();
1256 } else {
1257 TRACE(ft_t_bug, "Unexpected ftape interrupt");
1258 }
1259 TRACE_EXIT IRQ_RETVAL(handled);
1260}
1261
1262static int fdc_grab_irq_and_dma(void)
1263{
1264 TRACE_FUN(ft_t_any);
1265
1266 if (fdc.hook == &do_ftape) {
1267 /* Get fast interrupt handler.
1268 */
1269 if (request_irq(fdc.irq, ftape_interrupt,
1270 IRQF_DISABLED, "ft", ftape_id)) {
1271 TRACE_ABORT(-EIO, ft_t_bug,
1272 "Unable to grab IRQ%d for ftape driver",
1273 fdc.irq);
1274 }
1275 if (request_dma(fdc.dma, ftape_id)) {
1276 free_irq(fdc.irq, ftape_id);
1277 TRACE_ABORT(-EIO, ft_t_bug,
1278 "Unable to grab DMA%d for ftape driver",
1279 fdc.dma);
1280 }
1281 }
1282 if (ft_fdc_base != 0x3f0 && (ft_fdc_dma == 2 || ft_fdc_irq == 6)) {
1283 /* Using same dma channel or irq as standard fdc, need
1284 * to disable the dma-gate on the std fdc. This
1285 * couldn't be done in the floppy driver as some
1286 * laptops are using the dma-gate to enter a low power
1287 * or even suspended state :-(
1288 */
1289 outb_p(FDC_RESET_NOT, 0x3f2);
1290 TRACE(ft_t_noise, "DMA-gate on standard fdc disabled");
1291 }
1292 TRACE_EXIT 0;
1293}
1294
1295int fdc_release_irq_and_dma(void)
1296{
1297 TRACE_FUN(ft_t_any);
1298
1299 if (fdc.hook == &do_ftape) {
1300 disable_dma(fdc.dma); /* just in case... */
1301 free_dma(fdc.dma);
1302 free_irq(fdc.irq, ftape_id);
1303 }
1304 if (ft_fdc_base != 0x3f0 && (ft_fdc_dma == 2 || ft_fdc_irq == 6)) {
1305 /* Using same dma channel as standard fdc, need to
1306 * disable the dma-gate on the std fdc. This couldn't
1307 * be done in the floppy driver as some laptops are
1308 * using the dma-gate to enter a low power or even
1309 * suspended state :-(
1310 */
1311 outb_p(FDC_RESET_NOT | FDC_DMA_MODE, 0x3f2);
1312 TRACE(ft_t_noise, "DMA-gate on standard fdc enabled again");
1313 }
1314 TRACE_EXIT 0;
1315}
1316
1317int fdc_init(void)
1318{
1319 TRACE_FUN(ft_t_any);
1320
1321 /* find a FDC to use */
1322 TRACE_CATCH(fdc_config(),);
1323 TRACE_CATCH(fdc_grab_irq_and_dma(), fdc_release_regions());
1324 ftape_motor = 0;
1325 fdc_catch_stray_interrupts(0); /* clear number of awainted
1326 * stray interrupte
1327 */
1328 fdc_catch_stray_interrupts(1); /* one always comes (?) */
1329 TRACE(ft_t_flow, "resetting fdc");
1330 fdc_set_seek_rate(2); /* use nominal QIC step rate */
1331 fdc_reset(); /* init fdc & clear track counters */
1332 if (fdc.type == no_fdc) { /* no FC-10 or FC-20 found */
1333 fdc.type = fdc_probe();
1334 fdc_reset(); /* update with new knowledge */
1335 }
1336 if (fdc.type == no_fdc) {
1337 fdc_release_irq_and_dma();
1338 fdc_release_regions();
1339 TRACE_EXIT -ENXIO;
1340 }
1341 if (fdc.type >= i82077) {
1342 if (fdc_fifo_enable() < 0) {
1343 TRACE(ft_t_warn, "couldn't enable fdc fifo !");
1344 } else {
1345 TRACE(ft_t_flow, "fdc fifo enabled and locked");
1346 }
1347 }
1348 TRACE_EXIT 0;
1349}
diff --git a/drivers/char/ftape/lowlevel/fdc-io.h b/drivers/char/ftape/lowlevel/fdc-io.h
deleted file mode 100644
index 7ec3c72178bb..000000000000
--- a/drivers/char/ftape/lowlevel/fdc-io.h
+++ /dev/null
@@ -1,252 +0,0 @@
1#ifndef _FDC_IO_H
2#define _FDC_IO_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fdc-io.h,v $
24 * $Revision: 1.3 $
25 * $Date: 1997/10/05 19:18:06 $
26 *
27 * This file contains the declarations for the low level
28 * functions that communicate with the floppy disk controller,
29 * for the QIC-40/80/3010/3020 floppy-tape driver "ftape" for
30 * Linux.
31 */
32
33#include <linux/fdreg.h>
34
35#include "../lowlevel/ftape-bsm.h"
36
37#define FDC_SK_BIT (0x20)
38#define FDC_MT_BIT (0x80)
39
40#define FDC_READ (FD_READ & ~(FDC_SK_BIT | FDC_MT_BIT))
41#define FDC_WRITE (FD_WRITE & ~FDC_MT_BIT)
42#define FDC_READ_DELETED (0x4c)
43#define FDC_WRITE_DELETED (0x49)
44#define FDC_VERIFY (0x56)
45#define FDC_READID (0x4a)
46#define FDC_SENSED (0x04)
47#define FDC_SENSEI (FD_SENSEI)
48#define FDC_FORMAT (FD_FORMAT)
49#define FDC_RECAL (FD_RECALIBRATE)
50#define FDC_SEEK (FD_SEEK)
51#define FDC_SPECIFY (FD_SPECIFY)
52#define FDC_RECALIBR (FD_RECALIBRATE)
53#define FDC_VERSION (FD_VERSION)
54#define FDC_PERPEND (FD_PERPENDICULAR)
55#define FDC_DUMPREGS (FD_DUMPREGS)
56#define FDC_LOCK (FD_LOCK)
57#define FDC_UNLOCK (FD_UNLOCK)
58#define FDC_CONFIGURE (FD_CONFIGURE)
59#define FDC_DRIVE_SPEC (0x8e) /* i82078 has this (any others?) */
60#define FDC_PARTID (0x18) /* i82078 has this */
61#define FDC_SAVE (0x2e) /* i82078 has this (any others?) */
62#define FDC_RESTORE (0x4e) /* i82078 has this (any others?) */
63
64#define FDC_STATUS_MASK (STATUS_BUSY | STATUS_DMA | STATUS_DIR | STATUS_READY)
65#define FDC_DATA_READY (STATUS_READY)
66#define FDC_DATA_OUTPUT (STATUS_DIR)
67#define FDC_DATA_READY_MASK (STATUS_READY | STATUS_DIR)
68#define FDC_DATA_OUT_READY (STATUS_READY | STATUS_DIR)
69#define FDC_DATA_IN_READY (STATUS_READY)
70#define FDC_BUSY (STATUS_BUSY)
71#define FDC_CLK48_BIT (0x80)
72#define FDC_SEL3V_BIT (0x40)
73
74#define ST0_INT_MASK (ST0_INTR)
75#define FDC_INT_NORMAL (ST0_INTR & 0x00)
76#define FDC_INT_ABNORMAL (ST0_INTR & 0x40)
77#define FDC_INT_INVALID (ST0_INTR & 0x80)
78#define FDC_INT_READYCH (ST0_INTR & 0xC0)
79#define ST0_SEEK_END (ST0_SE)
80#define ST3_TRACK_0 (ST3_TZ)
81
82#define FDC_RESET_NOT (0x04)
83#define FDC_DMA_MODE (0x08)
84#define FDC_MOTOR_0 (0x10)
85#define FDC_MOTOR_1 (0x20)
86
87typedef struct {
88 void (**hook) (void); /* our wedge into the isr */
89 enum {
90 no_fdc, i8272, i82077, i82077AA, fc10,
91 i82078, i82078_1
92 } type; /* FDC type */
93 unsigned int irq; /* FDC irq nr */
94 unsigned int dma; /* FDC dma channel nr */
95 __u16 sra; /* Status register A (PS/2 only) */
96 __u16 srb; /* Status register B (PS/2 only) */
97 __u16 dor; /* Digital output register */
98 __u16 tdr; /* Tape Drive Register (82077SL-1 &
99 82078 only) */
100 __u16 msr; /* Main Status Register */
101 __u16 dsr; /* Datarate Select Register (8207x only) */
102 __u16 fifo; /* Data register / Fifo on 8207x */
103 __u16 dir; /* Digital Input Register */
104 __u16 ccr; /* Configuration Control Register */
105 __u16 dor2; /* Alternate dor on MACH-2 controller,
106 also used with FC-10, meaning unknown */
107} fdc_config_info;
108
109typedef enum {
110 fdc_data_rate_250 = 2,
111 fdc_data_rate_300 = 1, /* any fdc in default configuration */
112 fdc_data_rate_500 = 0,
113 fdc_data_rate_1000 = 3,
114 fdc_data_rate_2000 = 1, /* i82078-1: when using Data Rate Table #2 */
115} fdc_data_rate_type;
116
117typedef enum {
118 fdc_idle = 0,
119 fdc_reading_data = FDC_READ,
120 fdc_seeking = FDC_SEEK,
121 fdc_writing_data = FDC_WRITE,
122 fdc_deleting = FDC_WRITE_DELETED,
123 fdc_reading_id = FDC_READID,
124 fdc_recalibrating = FDC_RECAL,
125 fdc_formatting = FDC_FORMAT,
126 fdc_verifying = FDC_VERIFY
127} fdc_mode_enum;
128
129typedef enum {
130 waiting = 0,
131 reading,
132 writing,
133 formatting,
134 verifying,
135 deleting,
136 done,
137 error,
138 mmapped,
139} buffer_state_enum;
140
141typedef struct {
142 __u8 *address;
143 volatile buffer_state_enum status;
144 volatile __u8 *ptr;
145 volatile unsigned int bytes;
146 volatile unsigned int segment_id;
147
148 /* bitmap for remainder of segment not yet handled.
149 * one bit set for each bad sector that must be skipped.
150 */
151 volatile SectorMap bad_sector_map;
152
153 /* bitmap with bad data blocks in data buffer.
154 * the errors in this map may be retried.
155 */
156 volatile SectorMap soft_error_map;
157
158 /* bitmap with bad data blocks in data buffer
159 * the errors in this map may not be retried.
160 */
161 volatile SectorMap hard_error_map;
162
163 /* retry counter for soft errors.
164 */
165 volatile int retry;
166
167 /* sectors to skip on retry ???
168 */
169 volatile unsigned int skip;
170
171 /* nr of data blocks in data buffer
172 */
173 volatile unsigned int data_offset;
174
175 /* offset in segment for first sector to be handled.
176 */
177 volatile unsigned int sector_offset;
178
179 /* size of cluster of good sectors to be handled.
180 */
181 volatile unsigned int sector_count;
182
183 /* size of remaining part of segment to be handled.
184 */
185 volatile unsigned int remaining;
186
187 /* points to next segment (contiguous) to be handled,
188 * or is zero if no read-ahead is allowed.
189 */
190 volatile unsigned int next_segment;
191
192 /* flag being set if deleted data was read.
193 */
194 volatile int deleted;
195
196 /* floppy coordinates of first sector in segment */
197 volatile __u8 head;
198 volatile __u8 cyl;
199 volatile __u8 sect;
200
201 /* gap to use when formatting */
202 __u8 gap3;
203 /* flag set when buffer is mmaped */
204 int mmapped;
205} buffer_struct;
206
207/*
208 * fdc-io.c defined public variables
209 */
210extern volatile fdc_mode_enum fdc_mode;
211extern int fdc_setup_error; /* outdated ??? */
212extern wait_queue_head_t ftape_wait_intr;
213extern volatile int ftape_current_cylinder; /* track nr FDC thinks we're on */
214extern volatile __u8 fdc_head; /* FDC head */
215extern volatile __u8 fdc_cyl; /* FDC track */
216extern volatile __u8 fdc_sect; /* FDC sector */
217extern fdc_config_info fdc; /* FDC hardware configuration */
218
219extern unsigned int ft_fdc_base;
220extern unsigned int ft_fdc_irq;
221extern unsigned int ft_fdc_dma;
222extern unsigned int ft_fdc_threshold;
223extern unsigned int ft_fdc_rate_limit;
224extern int ft_probe_fc10;
225extern int ft_mach2;
226/*
227 * fdc-io.c defined public functions
228 */
229extern void fdc_catch_stray_interrupts(int count);
230extern int fdc_ready_wait(unsigned int timeout);
231extern int fdc_command(const __u8 * cmd_data, int cmd_len);
232extern int fdc_result(__u8 * res_data, int res_len);
233extern int fdc_interrupt_wait(unsigned int time);
234extern int fdc_seek(int track);
235extern int fdc_sense_drive_status(int *st3);
236extern void fdc_motor(int motor);
237extern void fdc_reset(void);
238extern void fdc_disable(void);
239extern int fdc_fifo_threshold(__u8 threshold,
240 int *fifo_state, int *lock_state, int *fifo_thr);
241extern void fdc_wait_calibrate(void);
242extern int fdc_sense_interrupt_status(int *st0, int *current_cylinder);
243extern void fdc_save_drive_specs(void);
244extern void fdc_restore_drive_specs(void);
245extern int fdc_set_data_rate(int rate);
246extern void fdc_set_write_precomp(int precomp);
247extern int fdc_release_irq_and_dma(void);
248extern void fdc_release_regions(void);
249extern int fdc_init(void);
250extern int fdc_setup_read_write(buffer_struct * buff, __u8 operation);
251extern int fdc_setup_formatting(buffer_struct * buff);
252#endif
diff --git a/drivers/char/ftape/lowlevel/fdc-isr.c b/drivers/char/ftape/lowlevel/fdc-isr.c
deleted file mode 100644
index ad2bc733ae1b..000000000000
--- a/drivers/char/ftape/lowlevel/fdc-isr.c
+++ /dev/null
@@ -1,1170 +0,0 @@
1/*
2 * Copyright (C) 1994-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fdc-isr.c,v $
21 * $Revision: 1.9 $
22 * $Date: 1997/10/17 23:01:53 $
23 *
24 * This file contains the interrupt service routine and
25 * associated code for the QIC-40/80/3010/3020 floppy-tape driver
26 * "ftape" for Linux.
27 */
28
29#include <asm/io.h>
30#include <asm/dma.h>
31
32#define volatile /* */
33
34#include <linux/ftape.h>
35#include <linux/qic117.h>
36#include "../lowlevel/ftape-tracing.h"
37#include "../lowlevel/fdc-isr.h"
38#include "../lowlevel/fdc-io.h"
39#include "../lowlevel/ftape-ctl.h"
40#include "../lowlevel/ftape-rw.h"
41#include "../lowlevel/ftape-io.h"
42#include "../lowlevel/ftape-calibr.h"
43#include "../lowlevel/ftape-bsm.h"
44
45/* Global vars.
46 */
47volatile int ft_expected_stray_interrupts;
48volatile int ft_interrupt_seen;
49volatile int ft_seek_completed;
50volatile int ft_hide_interrupt;
51/* Local vars.
52 */
53typedef enum {
54 no_error = 0, id_am_error = 0x01, id_crc_error = 0x02,
55 data_am_error = 0x04, data_crc_error = 0x08,
56 no_data_error = 0x10, overrun_error = 0x20,
57} error_cause;
58static int stop_read_ahead;
59
60
61static void print_error_cause(int cause)
62{
63 TRACE_FUN(ft_t_any);
64
65 switch (cause) {
66 case no_data_error:
67 TRACE(ft_t_noise, "no data error");
68 break;
69 case id_am_error:
70 TRACE(ft_t_noise, "id am error");
71 break;
72 case id_crc_error:
73 TRACE(ft_t_noise, "id crc error");
74 break;
75 case data_am_error:
76 TRACE(ft_t_noise, "data am error");
77 break;
78 case data_crc_error:
79 TRACE(ft_t_noise, "data crc error");
80 break;
81 case overrun_error:
82 TRACE(ft_t_noise, "overrun error");
83 break;
84 default:;
85 }
86 TRACE_EXIT;
87}
88
89static char *fdc_mode_txt(fdc_mode_enum mode)
90{
91 switch (mode) {
92 case fdc_idle:
93 return "fdc_idle";
94 case fdc_reading_data:
95 return "fdc_reading_data";
96 case fdc_seeking:
97 return "fdc_seeking";
98 case fdc_writing_data:
99 return "fdc_writing_data";
100 case fdc_reading_id:
101 return "fdc_reading_id";
102 case fdc_recalibrating:
103 return "fdc_recalibrating";
104 case fdc_formatting:
105 return "fdc_formatting";
106 case fdc_verifying:
107 return "fdc_verifying";
108 default:
109 return "unknown";
110 }
111}
112
113static inline error_cause decode_irq_cause(fdc_mode_enum mode, __u8 st[])
114{
115 error_cause cause = no_error;
116 TRACE_FUN(ft_t_any);
117
118 /* Valid st[], decode cause of interrupt.
119 */
120 switch (st[0] & ST0_INT_MASK) {
121 case FDC_INT_NORMAL:
122 TRACE(ft_t_fdc_dma,"normal completion: %s",fdc_mode_txt(mode));
123 break;
124 case FDC_INT_ABNORMAL:
125 TRACE(ft_t_flow, "abnormal completion %s", fdc_mode_txt(mode));
126 TRACE(ft_t_fdc_dma, "ST0: 0x%02x, ST1: 0x%02x, ST2: 0x%02x",
127 st[0], st[1], st[2]);
128 TRACE(ft_t_fdc_dma,
129 "C: 0x%02x, H: 0x%02x, R: 0x%02x, N: 0x%02x",
130 st[3], st[4], st[5], st[6]);
131 if (st[1] & 0x01) {
132 if (st[2] & 0x01) {
133 cause = data_am_error;
134 } else {
135 cause = id_am_error;
136 }
137 } else if (st[1] & 0x20) {
138 if (st[2] & 0x20) {
139 cause = data_crc_error;
140 } else {
141 cause = id_crc_error;
142 }
143 } else if (st[1] & 0x04) {
144 cause = no_data_error;
145 } else if (st[1] & 0x10) {
146 cause = overrun_error;
147 }
148 print_error_cause(cause);
149 break;
150 case FDC_INT_INVALID:
151 TRACE(ft_t_flow, "invalid completion %s", fdc_mode_txt(mode));
152 break;
153 case FDC_INT_READYCH:
154 if (st[0] & ST0_SEEK_END) {
155 TRACE(ft_t_flow, "drive poll completed");
156 } else {
157 TRACE(ft_t_flow, "ready change %s",fdc_mode_txt(mode));
158 }
159 break;
160 default:
161 break;
162 }
163 TRACE_EXIT cause;
164}
165
166static void update_history(error_cause cause)
167{
168 switch (cause) {
169 case id_am_error:
170 ft_history.id_am_errors++;
171 break;
172 case id_crc_error:
173 ft_history.id_crc_errors++;
174 break;
175 case data_am_error:
176 ft_history.data_am_errors++;
177 break;
178 case data_crc_error:
179 ft_history.data_crc_errors++;
180 break;
181 case overrun_error:
182 ft_history.overrun_errors++;
183 break;
184 case no_data_error:
185 ft_history.no_data_errors++;
186 break;
187 default:;
188 }
189}
190
191static void skip_bad_sector(buffer_struct * buff)
192{
193 TRACE_FUN(ft_t_any);
194
195 /* Mark sector as soft error and skip it
196 */
197 if (buff->remaining > 0) {
198 ++buff->sector_offset;
199 ++buff->data_offset;
200 --buff->remaining;
201 buff->ptr += FT_SECTOR_SIZE;
202 buff->bad_sector_map >>= 1;
203 } else {
204 /* Hey, what is this????????????? C code: if we shift
205 * more than 31 bits, we get no shift. That's bad!!!!!!
206 */
207 ++buff->sector_offset; /* hack for error maps */
208 TRACE(ft_t_warn, "skipping last sector in segment");
209 }
210 TRACE_EXIT;
211}
212
213static void update_error_maps(buffer_struct * buff, unsigned int error_offset)
214{
215 int hard = 0;
216 TRACE_FUN(ft_t_any);
217
218 if (buff->retry < FT_SOFT_RETRIES) {
219 buff->soft_error_map |= (1 << error_offset);
220 } else {
221 buff->hard_error_map |= (1 << error_offset);
222 buff->soft_error_map &= ~buff->hard_error_map;
223 buff->retry = -1; /* will be set to 0 in setup_segment */
224 hard = 1;
225 }
226 TRACE(ft_t_noise, "sector %d : %s error\n"
227 KERN_INFO "hard map: 0x%08lx\n"
228 KERN_INFO "soft map: 0x%08lx",
229 FT_SECTOR(error_offset), hard ? "hard" : "soft",
230 (long) buff->hard_error_map, (long) buff->soft_error_map);
231 TRACE_EXIT;
232}
233
234static void print_progress(buffer_struct *buff, error_cause cause)
235{
236 TRACE_FUN(ft_t_any);
237
238 switch (cause) {
239 case no_error:
240 TRACE(ft_t_flow,"%d Sector(s) transferred", buff->sector_count);
241 break;
242 case no_data_error:
243 TRACE(ft_t_flow, "Sector %d not found",
244 FT_SECTOR(buff->sector_offset));
245 break;
246 case overrun_error:
247 /* got an overrun error on the first byte, must be a
248 * hardware problem
249 */
250 TRACE(ft_t_bug,
251 "Unexpected error: failing DMA or FDC controller ?");
252 break;
253 case data_crc_error:
254 TRACE(ft_t_flow, "Error in sector %d",
255 FT_SECTOR(buff->sector_offset - 1));
256 break;
257 case id_crc_error:
258 case id_am_error:
259 case data_am_error:
260 TRACE(ft_t_flow, "Error in sector %d",
261 FT_SECTOR(buff->sector_offset));
262 break;
263 default:
264 TRACE(ft_t_flow, "Unexpected error at sector %d",
265 FT_SECTOR(buff->sector_offset));
266 break;
267 }
268 TRACE_EXIT;
269}
270
271/*
272 * Error cause: Amount xferred: Action:
273 *
274 * id_am_error 0 mark bad and skip
275 * id_crc_error 0 mark bad and skip
276 * data_am_error 0 mark bad and skip
277 * data_crc_error % 1024 mark bad and skip
278 * no_data_error 0 retry on write
279 * mark bad and skip on read
280 * overrun_error [ 0..all-1 ] mark bad and skip
281 * no_error all continue
282 */
283
284/* the arg `sector' is returned by the fdc and tells us at which sector we
285 * are positioned at (relative to starting sector of segment)
286 */
287static void determine_verify_progress(buffer_struct *buff,
288 error_cause cause,
289 __u8 sector)
290{
291 TRACE_FUN(ft_t_any);
292
293 if (cause == no_error && sector == 1) {
294 buff->sector_offset = FT_SECTORS_PER_SEGMENT;
295 buff->remaining = 0;
296 if (TRACE_LEVEL >= ft_t_flow) {
297 print_progress(buff, cause);
298 }
299 } else {
300 buff->sector_offset = sector - buff->sect;
301 buff->remaining = FT_SECTORS_PER_SEGMENT - buff->sector_offset;
302 TRACE(ft_t_noise, "%ssector offset: 0x%04x",
303 (cause == no_error) ? "unexpected " : "",
304 buff->sector_offset);
305 switch (cause) {
306 case overrun_error:
307 break;
308#if 0
309 case no_data_error:
310 buff->retry = FT_SOFT_RETRIES;
311 if (buff->hard_error_map &&
312 buff->sector_offset > 1 &&
313 (buff->hard_error_map &
314 (1 << (buff->sector_offset-2)))) {
315 buff->retry --;
316 }
317 break;
318#endif
319 default:
320 buff->retry = FT_SOFT_RETRIES;
321 break;
322 }
323 if (TRACE_LEVEL >= ft_t_flow) {
324 print_progress(buff, cause);
325 }
326 /* Sector_offset points to the problem area Now adjust
327 * sector_offset so it always points one past he failing
328 * sector. I.e. skip the bad sector.
329 */
330 ++buff->sector_offset;
331 --buff->remaining;
332 update_error_maps(buff, buff->sector_offset - 1);
333 }
334 TRACE_EXIT;
335}
336
337static void determine_progress(buffer_struct *buff,
338 error_cause cause,
339 __u8 sector)
340{
341 unsigned int dma_residue;
342 TRACE_FUN(ft_t_any);
343
344 /* Using less preferred order of disable_dma and
345 * get_dma_residue because this seems to fail on at least one
346 * system if reversed!
347 */
348 dma_residue = get_dma_residue(fdc.dma);
349 disable_dma(fdc.dma);
350 if (cause != no_error || dma_residue != 0) {
351 TRACE(ft_t_noise, "%sDMA residue: 0x%04x",
352 (cause == no_error) ? "unexpected " : "",
353 dma_residue);
354 /* adjust to actual value: */
355 if (dma_residue == 0) {
356 /* this happens sometimes with overrun errors.
357 * I don't know whether we could ignore the
358 * overrun error. Play save.
359 */
360 buff->sector_count --;
361 } else {
362 buff->sector_count -= ((dma_residue +
363 (FT_SECTOR_SIZE - 1)) /
364 FT_SECTOR_SIZE);
365 }
366 }
367 /* Update var's influenced by the DMA operation.
368 */
369 if (buff->sector_count > 0) {
370 buff->sector_offset += buff->sector_count;
371 buff->data_offset += buff->sector_count;
372 buff->ptr += (buff->sector_count *
373 FT_SECTOR_SIZE);
374 buff->remaining -= buff->sector_count;
375 buff->bad_sector_map >>= buff->sector_count;
376 }
377 if (TRACE_LEVEL >= ft_t_flow) {
378 print_progress(buff, cause);
379 }
380 if (cause != no_error) {
381 if (buff->remaining == 0) {
382 TRACE(ft_t_warn, "foo?\n"
383 KERN_INFO "count : %d\n"
384 KERN_INFO "offset: %d\n"
385 KERN_INFO "soft : %08x\n"
386 KERN_INFO "hard : %08x",
387 buff->sector_count,
388 buff->sector_offset,
389 buff->soft_error_map,
390 buff->hard_error_map);
391 }
392 /* Sector_offset points to the problem area, except if we got
393 * a data_crc_error. In that case it points one past the
394 * failing sector.
395 *
396 * Now adjust sector_offset so it always points one past he
397 * failing sector. I.e. skip the bad sector.
398 */
399 if (cause != data_crc_error) {
400 skip_bad_sector(buff);
401 }
402 update_error_maps(buff, buff->sector_offset - 1);
403 }
404 TRACE_EXIT;
405}
406
407static int calc_steps(int cmd)
408{
409 if (ftape_current_cylinder > cmd) {
410 return ftape_current_cylinder - cmd;
411 } else {
412 return ftape_current_cylinder + cmd;
413 }
414}
415
416static void pause_tape(int retry, int mode)
417{
418 int result;
419 __u8 out[3] = {FDC_SEEK, ft_drive_sel, 0};
420 TRACE_FUN(ft_t_any);
421
422 /* We'll use a raw seek command to get the tape to rewind and
423 * stop for a retry.
424 */
425 ++ft_history.rewinds;
426 if (qic117_cmds[ftape_current_command].non_intr) {
427 TRACE(ft_t_warn, "motion command may be issued too soon");
428 }
429 if (retry && (mode == fdc_reading_data ||
430 mode == fdc_reading_id ||
431 mode == fdc_verifying)) {
432 ftape_current_command = QIC_MICRO_STEP_PAUSE;
433 ftape_might_be_off_track = 1;
434 } else {
435 ftape_current_command = QIC_PAUSE;
436 }
437 out[2] = calc_steps(ftape_current_command);
438 result = fdc_command(out, 3); /* issue QIC_117 command */
439 ftape_current_cylinder = out[ 2];
440 if (result < 0) {
441 TRACE(ft_t_noise, "qic-pause failed, status = %d", result);
442 } else {
443 ft_location.known = 0;
444 ft_runner_status = idle;
445 ft_hide_interrupt = 1;
446 ftape_tape_running = 0;
447 }
448 TRACE_EXIT;
449}
450
451static void continue_xfer(buffer_struct *buff,
452 fdc_mode_enum mode,
453 unsigned int skip)
454{
455 int write = 0;
456 TRACE_FUN(ft_t_any);
457
458 if (mode == fdc_writing_data || mode == fdc_deleting) {
459 write = 1;
460 }
461 /* This part can be removed if it never happens
462 */
463 if (skip > 0 &&
464 (ft_runner_status != running ||
465 (write && (buff->status != writing)) ||
466 (!write && (buff->status != reading &&
467 buff->status != verifying)))) {
468 TRACE(ft_t_err, "unexpected runner/buffer state %d/%d",
469 ft_runner_status, buff->status);
470 buff->status = error;
471 /* finish this buffer: */
472 (void)ftape_next_buffer(ft_queue_head);
473 ft_runner_status = aborting;
474 fdc_mode = fdc_idle;
475 } else if (buff->remaining > 0 && ftape_calc_next_cluster(buff) > 0) {
476 /* still sectors left in current segment, continue
477 * with this segment
478 */
479 if (fdc_setup_read_write(buff, mode) < 0) {
480 /* failed, abort operation
481 */
482 buff->bytes = buff->ptr - buff->address;
483 buff->status = error;
484 /* finish this buffer: */
485 (void)ftape_next_buffer(ft_queue_head);
486 ft_runner_status = aborting;
487 fdc_mode = fdc_idle;
488 }
489 } else {
490 /* current segment completed
491 */
492 unsigned int last_segment = buff->segment_id;
493 int eot = ((last_segment + 1) % ft_segments_per_track) == 0;
494 unsigned int next = buff->next_segment; /* 0 means stop ! */
495
496 buff->bytes = buff->ptr - buff->address;
497 buff->status = done;
498 buff = ftape_next_buffer(ft_queue_head);
499 if (eot) {
500 /* finished last segment on current track,
501 * can't continue
502 */
503 ft_runner_status = logical_eot;
504 fdc_mode = fdc_idle;
505 TRACE_EXIT;
506 }
507 if (next <= 0) {
508 /* don't continue with next segment
509 */
510 TRACE(ft_t_noise, "no %s allowed, stopping tape",
511 (write) ? "write next" : "read ahead");
512 pause_tape(0, mode);
513 ft_runner_status = idle; /* not quite true until
514 * next irq
515 */
516 TRACE_EXIT;
517 }
518 /* continue with next segment
519 */
520 if (buff->status != waiting) {
521 TRACE(ft_t_noise, "all input buffers %s, pausing tape",
522 (write) ? "empty" : "full");
523 pause_tape(0, mode);
524 ft_runner_status = idle; /* not quite true until
525 * next irq
526 */
527 TRACE_EXIT;
528 }
529 if (write && next != buff->segment_id) {
530 TRACE(ft_t_noise,
531 "segments out of order, aborting write");
532 ft_runner_status = do_abort;
533 fdc_mode = fdc_idle;
534 TRACE_EXIT;
535 }
536 ftape_setup_new_segment(buff, next, 0);
537 if (stop_read_ahead) {
538 buff->next_segment = 0;
539 stop_read_ahead = 0;
540 }
541 if (ftape_calc_next_cluster(buff) == 0 ||
542 fdc_setup_read_write(buff, mode) != 0) {
543 TRACE(ft_t_err, "couldn't start %s-ahead",
544 write ? "write" : "read");
545 ft_runner_status = do_abort;
546 fdc_mode = fdc_idle;
547 } else {
548 /* keep on going */
549 switch (ft_driver_state) {
550 case reading: buff->status = reading; break;
551 case verifying: buff->status = verifying; break;
552 case writing: buff->status = writing; break;
553 case deleting: buff->status = deleting; break;
554 default:
555 TRACE(ft_t_err,
556 "BUG: ft_driver_state %d should be one out of "
557 "{reading, writing, verifying, deleting}",
558 ft_driver_state);
559 buff->status = write ? writing : reading;
560 break;
561 }
562 }
563 }
564 TRACE_EXIT;
565}
566
567static void retry_sector(buffer_struct *buff,
568 int mode,
569 unsigned int skip)
570{
571 TRACE_FUN(ft_t_any);
572
573 TRACE(ft_t_noise, "%s error, will retry",
574 (mode == fdc_writing_data || mode == fdc_deleting) ? "write" : "read");
575 pause_tape(1, mode);
576 ft_runner_status = aborting;
577 buff->status = error;
578 buff->skip = skip;
579 TRACE_EXIT;
580}
581
582static unsigned int find_resume_point(buffer_struct *buff)
583{
584 int i = 0;
585 SectorMap mask;
586 SectorMap map;
587 TRACE_FUN(ft_t_any);
588
589 /* This function is to be called after all variables have been
590 * updated to point past the failing sector.
591 * If there are any soft errors before the failing sector,
592 * find the first soft error and return the sector offset.
593 * Otherwise find the last hard error.
594 * Note: there should always be at least one hard or soft error !
595 */
596 if (buff->sector_offset < 1 || buff->sector_offset > 32) {
597 TRACE(ft_t_bug, "BUG: sector_offset = %d",
598 buff->sector_offset);
599 TRACE_EXIT 0;
600 }
601 if (buff->sector_offset >= 32) { /* C-limitation on shift ! */
602 mask = 0xffffffff;
603 } else {
604 mask = (1 << buff->sector_offset) - 1;
605 }
606 map = buff->soft_error_map & mask;
607 if (map) {
608 while ((map & (1 << i)) == 0) {
609 ++i;
610 }
611 TRACE(ft_t_noise, "at sector %d", FT_SECTOR(i));
612 } else {
613 map = buff->hard_error_map & mask;
614 i = buff->sector_offset - 1;
615 if (map) {
616 while ((map & (1 << i)) == 0) {
617 --i;
618 }
619 TRACE(ft_t_noise, "after sector %d", FT_SECTOR(i));
620 ++i; /* first sector after last hard error */
621 } else {
622 TRACE(ft_t_bug, "BUG: no soft or hard errors");
623 }
624 }
625 TRACE_EXIT i;
626}
627
628/* check possible dma residue when formatting, update position record in
629 * buffer struct. This is, of course, modelled after determine_progress(), but
630 * we don't need to set up for retries because the format process cannot be
631 * interrupted (except at the end of the tape track).
632 */
633static int determine_fmt_progress(buffer_struct *buff, error_cause cause)
634{
635 unsigned int dma_residue;
636 TRACE_FUN(ft_t_any);
637
638 /* Using less preferred order of disable_dma and
639 * get_dma_residue because this seems to fail on at least one
640 * system if reversed!
641 */
642 dma_residue = get_dma_residue(fdc.dma);
643 disable_dma(fdc.dma);
644 if (cause != no_error || dma_residue != 0) {
645 TRACE(ft_t_info, "DMA residue = 0x%04x", dma_residue);
646 fdc_mode = fdc_idle;
647 switch(cause) {
648 case no_error:
649 ft_runner_status = aborting;
650 buff->status = idle;
651 break;
652 case overrun_error:
653 /* got an overrun error on the first byte, must be a
654 * hardware problem
655 */
656 TRACE(ft_t_bug,
657 "Unexpected error: failing DMA controller ?");
658 ft_runner_status = do_abort;
659 buff->status = error;
660 break;
661 default:
662 TRACE(ft_t_noise, "Unexpected error at segment %d",
663 buff->segment_id);
664 ft_runner_status = do_abort;
665 buff->status = error;
666 break;
667 }
668 TRACE_EXIT -EIO; /* can only retry entire track in format mode
669 */
670 }
671 /* Update var's influenced by the DMA operation.
672 */
673 buff->ptr += FT_SECTORS_PER_SEGMENT * 4;
674 buff->bytes -= FT_SECTORS_PER_SEGMENT * 4;
675 buff->remaining -= FT_SECTORS_PER_SEGMENT;
676 buff->segment_id ++; /* done with segment */
677 TRACE_EXIT 0;
678}
679
680/*
681 * Continue formatting, switch buffers if there is no data left in
682 * current buffer. This is, of course, modelled after
683 * continue_xfer(), but we don't need to set up for retries because
684 * the format process cannot be interrupted (except at the end of the
685 * tape track).
686 */
687static void continue_formatting(buffer_struct *buff)
688{
689 TRACE_FUN(ft_t_any);
690
691 if (buff->remaining <= 0) { /* no space left in dma buffer */
692 unsigned int next = buff->next_segment;
693
694 if (next == 0) { /* end of tape track */
695 buff->status = done;
696 ft_runner_status = logical_eot;
697 fdc_mode = fdc_idle;
698 TRACE(ft_t_noise, "Done formatting track %d",
699 ft_location.track);
700 TRACE_EXIT;
701 }
702 /*
703 * switch to next buffer!
704 */
705 buff->status = done;
706 buff = ftape_next_buffer(ft_queue_head);
707
708 if (buff->status != waiting || next != buff->segment_id) {
709 goto format_setup_error;
710 }
711 }
712 if (fdc_setup_formatting(buff) < 0) {
713 goto format_setup_error;
714 }
715 buff->status = formatting;
716 TRACE(ft_t_fdc_dma, "Formatting segment %d on track %d",
717 buff->segment_id, ft_location.track);
718 TRACE_EXIT;
719 format_setup_error:
720 ft_runner_status = do_abort;
721 fdc_mode = fdc_idle;
722 buff->status = error;
723 TRACE(ft_t_err, "Error setting up for segment %d on track %d",
724 buff->segment_id, ft_location.track);
725 TRACE_EXIT;
726
727}
728
729/* this handles writing, read id, reading and formatting
730 */
731static void handle_fdc_busy(buffer_struct *buff)
732{
733 static int no_data_error_count;
734 int retry = 0;
735 error_cause cause;
736 __u8 in[7];
737 int skip;
738 fdc_mode_enum fmode = fdc_mode;
739 TRACE_FUN(ft_t_any);
740
741 if (fdc_result(in, 7) < 0) { /* better get it fast ! */
742 TRACE(ft_t_err,
743 "Probably fatal error during FDC Result Phase\n"
744 KERN_INFO
745 "drive may hang until (power on) reset :-(");
746 /* what to do next ????
747 */
748 TRACE_EXIT;
749 }
750 cause = decode_irq_cause(fdc_mode, in);
751#ifdef TESTING
752 { int i;
753 for (i = 0; i < (int)ft_nr_buffers; ++i)
754 TRACE(ft_t_any, "buffer[%d] status: %d, segment_id: %d",
755 i, ft_buffer[i]->status, ft_buffer[i]->segment_id);
756 }
757#endif
758 if (fmode == fdc_reading_data && ft_driver_state == verifying) {
759 fmode = fdc_verifying;
760 }
761 switch (fmode) {
762 case fdc_verifying:
763 if (ft_runner_status == aborting ||
764 ft_runner_status == do_abort) {
765 TRACE(ft_t_noise,"aborting %s",fdc_mode_txt(fdc_mode));
766 break;
767 }
768 if (buff->retry > 0) {
769 TRACE(ft_t_flow, "this is retry nr %d", buff->retry);
770 }
771 switch (cause) {
772 case no_error:
773 no_data_error_count = 0;
774 determine_verify_progress(buff, cause, in[5]);
775 if (in[2] & 0x40) {
776 /* This should not happen when verifying
777 */
778 TRACE(ft_t_warn,
779 "deleted data in segment %d/%d",
780 buff->segment_id,
781 FT_SECTOR(buff->sector_offset - 1));
782 buff->remaining = 0; /* abort transfer */
783 buff->hard_error_map = EMPTY_SEGMENT;
784 skip = 1;
785 } else {
786 skip = 0;
787 }
788 continue_xfer(buff, fdc_mode, skip);
789 break;
790 case no_data_error:
791 no_data_error_count ++;
792 case overrun_error:
793 retry ++;
794 case id_am_error:
795 case id_crc_error:
796 case data_am_error:
797 case data_crc_error:
798 determine_verify_progress(buff, cause, in[5]);
799 if (cause == no_data_error) {
800 if (no_data_error_count >= 2) {
801 TRACE(ft_t_warn,
802 "retrying because of successive "
803 "no data errors");
804 no_data_error_count = 0;
805 } else {
806 retry --;
807 }
808 } else {
809 no_data_error_count = 0;
810 }
811 if (retry) {
812 skip = find_resume_point(buff);
813 } else {
814 skip = buff->sector_offset;
815 }
816 if (retry && skip < 32) {
817 retry_sector(buff, fdc_mode, skip);
818 } else {
819 continue_xfer(buff, fdc_mode, skip);
820 }
821 update_history(cause);
822 break;
823 default:
824 /* Don't know why this could happen
825 * but find out.
826 */
827 determine_verify_progress(buff, cause, in[5]);
828 retry_sector(buff, fdc_mode, 0);
829 TRACE(ft_t_err, "Error: unexpected error");
830 break;
831 }
832 break;
833 case fdc_reading_data:
834#ifdef TESTING
835 /* I'm sorry, but: NOBODY ever used this trace
836 * messages for ages. I guess that Bas was the last person
837 * that ever really used this (thank you, between the lines)
838 */
839 if (cause == no_error) {
840 TRACE(ft_t_flow,"reading segment %d",buff->segment_id);
841 } else {
842 TRACE(ft_t_noise, "error reading segment %d",
843 buff->segment_id);
844 TRACE(ft_t_noise, "\n"
845 KERN_INFO
846 "IRQ:C: 0x%02x, H: 0x%02x, R: 0x%02x, N: 0x%02x\n"
847 KERN_INFO
848 "BUF:C: 0x%02x, H: 0x%02x, R: 0x%02x",
849 in[3], in[4], in[5], in[6],
850 buff->cyl, buff->head, buff->sect);
851 }
852#endif
853 if (ft_runner_status == aborting ||
854 ft_runner_status == do_abort) {
855 TRACE(ft_t_noise,"aborting %s",fdc_mode_txt(fdc_mode));
856 break;
857 }
858 if (buff->bad_sector_map == FAKE_SEGMENT) {
859 /* This condition occurs when reading a `fake'
860 * sector that's not accessible. Doesn't
861 * really matter as we would have ignored it
862 * anyway !
863 *
864 * Chance is that we're past the next segment
865 * now, so the next operation may fail and
866 * result in a retry.
867 */
868 buff->remaining = 0; /* skip failing sector */
869 /* buff->ptr = buff->address; */
870 /* fake success: */
871 continue_xfer(buff, fdc_mode, 1);
872 /* trace calls are expensive: place them AFTER
873 * the real stuff has been done.
874 *
875 */
876 TRACE(ft_t_noise, "skipping empty segment %d (read), size? %d",
877 buff->segment_id, buff->ptr - buff->address);
878 TRACE_EXIT;
879 }
880 if (buff->retry > 0) {
881 TRACE(ft_t_flow, "this is retry nr %d", buff->retry);
882 }
883 switch (cause) {
884 case no_error:
885 determine_progress(buff, cause, in[5]);
886 if (in[2] & 0x40) {
887 /* Handle deleted data in header segments.
888 * Skip segment and force read-ahead.
889 */
890 TRACE(ft_t_warn,
891 "deleted data in segment %d/%d",
892 buff->segment_id,
893 FT_SECTOR(buff->sector_offset - 1));
894 buff->deleted = 1;
895 buff->remaining = 0;/*abort transfer */
896 buff->soft_error_map |=
897 (-1L << buff->sector_offset);
898 if (buff->segment_id == 0) {
899 /* stop on next segment */
900 stop_read_ahead = 1;
901 }
902 /* force read-ahead: */
903 buff->next_segment =
904 buff->segment_id + 1;
905 skip = (FT_SECTORS_PER_SEGMENT -
906 buff->sector_offset);
907 } else {
908 skip = 0;
909 }
910 continue_xfer(buff, fdc_mode, skip);
911 break;
912 case no_data_error:
913 /* Tape started too far ahead of or behind the
914 * right sector. This may also happen in the
915 * middle of a segment !
916 *
917 * Handle no-data as soft error. If next
918 * sector fails too, a retry (with needed
919 * reposition) will follow.
920 */
921 retry ++;
922 case id_am_error:
923 case id_crc_error:
924 case data_am_error:
925 case data_crc_error:
926 case overrun_error:
927 retry += (buff->soft_error_map != 0 ||
928 buff->hard_error_map != 0);
929 determine_progress(buff, cause, in[5]);
930#if 1 || defined(TESTING)
931 if (cause == overrun_error) retry ++;
932#endif
933 if (retry) {
934 skip = find_resume_point(buff);
935 } else {
936 skip = buff->sector_offset;
937 }
938 /* Try to resume with next sector on single
939 * errors (let ecc correct it), but retry on
940 * no_data (we'll be past the target when we
941 * get here so we cannot retry) or on
942 * multiple errors (reduce chance on ecc
943 * failure).
944 */
945 /* cH: 23/02/97: if the last sector in the
946 * segment was a hard error, then there is
947 * no sense in a retry. This occasion seldom
948 * occurs but ... @:³²¸`@%&§$
949 */
950 if (retry && skip < 32) {
951 retry_sector(buff, fdc_mode, skip);
952 } else {
953 continue_xfer(buff, fdc_mode, skip);
954 }
955 update_history(cause);
956 break;
957 default:
958 /* Don't know why this could happen
959 * but find out.
960 */
961 determine_progress(buff, cause, in[5]);
962 retry_sector(buff, fdc_mode, 0);
963 TRACE(ft_t_err, "Error: unexpected error");
964 break;
965 }
966 break;
967 case fdc_reading_id:
968 if (cause == no_error) {
969 fdc_cyl = in[3];
970 fdc_head = in[4];
971 fdc_sect = in[5];
972 TRACE(ft_t_fdc_dma,
973 "id read: C: 0x%02x, H: 0x%02x, R: 0x%02x",
974 fdc_cyl, fdc_head, fdc_sect);
975 } else { /* no valid information, use invalid sector */
976 fdc_cyl = fdc_head = fdc_sect = 0;
977 TRACE(ft_t_flow, "Didn't find valid sector Id");
978 }
979 fdc_mode = fdc_idle;
980 break;
981 case fdc_deleting:
982 case fdc_writing_data:
983#ifdef TESTING
984 if (cause == no_error) {
985 TRACE(ft_t_flow, "writing segment %d", buff->segment_id);
986 } else {
987 TRACE(ft_t_noise, "error writing segment %d",
988 buff->segment_id);
989 }
990#endif
991 if (ft_runner_status == aborting ||
992 ft_runner_status == do_abort) {
993 TRACE(ft_t_flow, "aborting %s",fdc_mode_txt(fdc_mode));
994 break;
995 }
996 if (buff->retry > 0) {
997 TRACE(ft_t_flow, "this is retry nr %d", buff->retry);
998 }
999 if (buff->bad_sector_map == FAKE_SEGMENT) {
1000 /* This condition occurs when trying to write to a
1001 * `fake' sector that's not accessible. Doesn't really
1002 * matter as it isn't used anyway ! Might be located
1003 * at wrong segment, then we'll fail on the next
1004 * segment.
1005 */
1006 TRACE(ft_t_noise, "skipping empty segment (write)");
1007 buff->remaining = 0; /* skip failing sector */
1008 /* fake success: */
1009 continue_xfer(buff, fdc_mode, 1);
1010 break;
1011 }
1012 switch (cause) {
1013 case no_error:
1014 determine_progress(buff, cause, in[5]);
1015 continue_xfer(buff, fdc_mode, 0);
1016 break;
1017 case no_data_error:
1018 case id_am_error:
1019 case id_crc_error:
1020 case data_am_error:
1021 case overrun_error:
1022 update_history(cause);
1023 determine_progress(buff, cause, in[5]);
1024 skip = find_resume_point(buff);
1025 retry_sector(buff, fdc_mode, skip);
1026 break;
1027 default:
1028 if (in[1] & 0x02) {
1029 TRACE(ft_t_err, "media not writable");
1030 } else {
1031 TRACE(ft_t_bug, "unforeseen write error");
1032 }
1033 fdc_mode = fdc_idle;
1034 break;
1035 }
1036 break; /* fdc_deleting || fdc_writing_data */
1037 case fdc_formatting:
1038 /* The interrupt comes after formatting a segment. We then
1039 * have to set up QUICKLY for the next segment. But
1040 * afterwards, there is plenty of time.
1041 */
1042 switch (cause) {
1043 case no_error:
1044 /* would like to keep most of the formatting stuff
1045 * outside the isr code, but timing is too critical
1046 */
1047 if (determine_fmt_progress(buff, cause) >= 0) {
1048 continue_formatting(buff);
1049 }
1050 break;
1051 case no_data_error:
1052 case id_am_error:
1053 case id_crc_error:
1054 case data_am_error:
1055 case overrun_error:
1056 default:
1057 determine_fmt_progress(buff, cause);
1058 update_history(cause);
1059 if (in[1] & 0x02) {
1060 TRACE(ft_t_err, "media not writable");
1061 } else {
1062 TRACE(ft_t_bug, "unforeseen write error");
1063 }
1064 break;
1065 } /* cause */
1066 break;
1067 default:
1068 TRACE(ft_t_warn, "Warning: unexpected irq during: %s",
1069 fdc_mode_txt(fdc_mode));
1070 fdc_mode = fdc_idle;
1071 break;
1072 }
1073 TRACE_EXIT;
1074}
1075
1076/* FDC interrupt service routine.
1077 */
1078void fdc_isr(void)
1079{
1080 static int isr_active;
1081#ifdef TESTING
1082 unsigned int t0 = ftape_timestamp();
1083#endif
1084 TRACE_FUN(ft_t_any);
1085
1086 if (isr_active++) {
1087 --isr_active;
1088 TRACE(ft_t_bug, "BUG: nested interrupt, not good !");
1089 *fdc.hook = fdc_isr; /* hook our handler into the fdc
1090 * code again
1091 */
1092 TRACE_EXIT;
1093 }
1094 sti();
1095 if (inb_p(fdc.msr) & FDC_BUSY) { /* Entering Result Phase */
1096 ft_hide_interrupt = 0;
1097 handle_fdc_busy(ftape_get_buffer(ft_queue_head));
1098 if (ft_runner_status == do_abort) {
1099 /* cease operation, remember tape position
1100 */
1101 TRACE(ft_t_flow, "runner aborting");
1102 ft_runner_status = aborting;
1103 ++ft_expected_stray_interrupts;
1104 }
1105 } else { /* !FDC_BUSY */
1106 /* clear interrupt, cause should be gotten by issuing
1107 * a Sense Interrupt Status command.
1108 */
1109 if (fdc_mode == fdc_recalibrating || fdc_mode == fdc_seeking) {
1110 if (ft_hide_interrupt) {
1111 int st0;
1112 int pcn;
1113
1114 if (fdc_sense_interrupt_status(&st0, &pcn) < 0)
1115 TRACE(ft_t_err,
1116 "sense interrupt status failed");
1117 ftape_current_cylinder = pcn;
1118 TRACE(ft_t_flow, "handled hidden interrupt");
1119 }
1120 ft_seek_completed = 1;
1121 fdc_mode = fdc_idle;
1122 } else if (!waitqueue_active(&ftape_wait_intr)) {
1123 if (ft_expected_stray_interrupts == 0) {
1124 TRACE(ft_t_warn, "unexpected stray interrupt");
1125 } else {
1126 TRACE(ft_t_flow, "expected stray interrupt");
1127 --ft_expected_stray_interrupts;
1128 }
1129 } else {
1130 if (fdc_mode == fdc_reading_data ||
1131 fdc_mode == fdc_verifying ||
1132 fdc_mode == fdc_writing_data ||
1133 fdc_mode == fdc_deleting ||
1134 fdc_mode == fdc_formatting ||
1135 fdc_mode == fdc_reading_id) {
1136 if (inb_p(fdc.msr) & FDC_BUSY) {
1137 TRACE(ft_t_bug,
1138 "***** FDC failure, busy too late");
1139 } else {
1140 TRACE(ft_t_bug,
1141 "***** FDC failure, no busy");
1142 }
1143 } else {
1144 TRACE(ft_t_fdc_dma, "awaited stray interrupt");
1145 }
1146 }
1147 ft_hide_interrupt = 0;
1148 }
1149 /* Handle sleep code.
1150 */
1151 if (!ft_hide_interrupt) {
1152 ft_interrupt_seen ++;
1153 if (waitqueue_active(&ftape_wait_intr)) {
1154 wake_up_interruptible(&ftape_wait_intr);
1155 }
1156 } else {
1157 TRACE(ft_t_flow, "hiding interrupt while %s",
1158 waitqueue_active(&ftape_wait_intr) ? "waiting":"active");
1159 }
1160#ifdef TESTING
1161 t0 = ftape_timediff(t0, ftape_timestamp());
1162 if (t0 >= 1000) {
1163 /* only tell us about long calls */
1164 TRACE(ft_t_noise, "isr() duration: %5d usec", t0);
1165 }
1166#endif
1167 *fdc.hook = fdc_isr; /* hook our handler into the fdc code again */
1168 --isr_active;
1169 TRACE_EXIT;
1170}
diff --git a/drivers/char/ftape/lowlevel/fdc-isr.h b/drivers/char/ftape/lowlevel/fdc-isr.h
deleted file mode 100644
index 065aa978942d..000000000000
--- a/drivers/char/ftape/lowlevel/fdc-isr.h
+++ /dev/null
@@ -1,55 +0,0 @@
1#ifndef _FDC_ISR_H
2#define _FDC_ISR_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fdc-isr.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:07 $
26 *
27 * This file declares the global variables necessary to
28 * synchronize the interrupt service routine (isr) with the
29 * remainder of the QIC-40/80/3010/3020 floppy-tape driver
30 * "ftape" for Linux.
31 */
32
33/*
34 * fdc-isr.c defined public variables
35 */
36extern volatile int ft_expected_stray_interrupts; /* masks stray interrupts */
37extern volatile int ft_seek_completed; /* flag set by isr */
38extern volatile int ft_interrupt_seen; /* flag set by isr */
39extern volatile int ft_hide_interrupt; /* flag set by isr */
40
41/*
42 * fdc-io.c defined public functions
43 */
44extern void fdc_isr(void);
45
46/*
47 * A kernel hook that steals one interrupt from the floppy
48 * driver (Should be fixed when the new fdc driver gets ready)
49 * See the linux kernel source files:
50 * drivers/block/floppy.c & drivers/block/blk.h
51 * for the details.
52 */
53extern void (*do_floppy) (void);
54
55#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-bsm.c b/drivers/char/ftape/lowlevel/ftape-bsm.c
deleted file mode 100644
index d1a301cc344f..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-bsm.c
+++ /dev/null
@@ -1,491 +0,0 @@
1/*
2 * Copyright (C) 1994-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-bsm.c,v $
21 * $Revision: 1.3 $
22 * $Date: 1997/10/05 19:15:15 $
23 *
24 * This file contains the bad-sector map handling code for
25 * the QIC-117 floppy tape driver for Linux.
26 * QIC-40, QIC-80, QIC-3010 and QIC-3020 maps are implemented.
27 */
28
29#include <linux/string.h>
30
31#include <linux/ftape.h>
32#include "../lowlevel/ftape-tracing.h"
33#include "../lowlevel/ftape-bsm.h"
34#include "../lowlevel/ftape-ctl.h"
35#include "../lowlevel/ftape-rw.h"
36
37/* Global vars.
38 */
39
40/* Local vars.
41 */
42static __u8 *bad_sector_map;
43static SectorCount *bsm_hash_ptr;
44
45typedef enum {
46 forward, backward
47} mode_type;
48
49#if 0
50static void ftape_put_bad_sector_entry(int segment_id, SectorMap new_map);
51#endif
52
53#if 0
54/* fix_tape converts a normal QIC-80 tape into a 'wide' tape.
55 * For testing purposes only !
56 */
57void fix_tape(__u8 * buffer, ft_format_type new_code)
58{
59 static __u8 list[BAD_SECTOR_MAP_SIZE];
60 SectorMap *src_ptr = (SectorMap *) list;
61 __u8 *dst_ptr = bad_sector_map;
62 SectorMap map;
63 unsigned int sector = 1;
64 int i;
65
66 if (format_code != fmt_var && format_code != fmt_big) {
67 memcpy(list, bad_sector_map, sizeof(list));
68 memset(bad_sector_map, 0, sizeof(bad_sector_map));
69 while ((__u8 *) src_ptr - list < sizeof(list)) {
70 map = *src_ptr++;
71 if (map == EMPTY_SEGMENT) {
72 *(SectorMap *) dst_ptr = 0x800000 + sector;
73 dst_ptr += 3;
74 sector += SECTORS_PER_SEGMENT;
75 } else {
76 for (i = 0; i < SECTORS_PER_SEGMENT; ++i) {
77 if (map & 1) {
78 *(SewctorMap *) dst_ptr = sector;
79 dst_ptr += 3;
80 }
81 map >>= 1;
82 ++sector;
83 }
84 }
85 }
86 }
87 bad_sector_map_changed = 1;
88 *(buffer + 4) = new_code; /* put new format code */
89 if (format_code != fmt_var && new_code == fmt_big) {
90 PUT4(buffer, FT_6_HSEG_1, (__u32)GET2(buffer, 6));
91 PUT4(buffer, FT_6_HSEG_2, (__u32)GET2(buffer, 8));
92 PUT4(buffer, FT_6_FRST_SEG, (__u32)GET2(buffer, 10));
93 PUT4(buffer, FT_6_LAST_SEG, (__u32)GET2(buffer, 12));
94 memset(buffer+6, '\0', 8);
95 }
96 format_code = new_code;
97}
98
99#endif
100
101/* given buffer that contains a header segment, find the end of
102 * of the bsm list
103 */
104__u8 * ftape_find_end_of_bsm_list(__u8 * address)
105{
106 __u8 *ptr = address + FT_HEADER_END; /* start of bsm list */
107 __u8 *limit = address + FT_SEGMENT_SIZE;
108 while (ptr + 2 < limit) {
109 if (ptr[0] || ptr[1] || ptr[2]) {
110 ptr += 3;
111 } else {
112 return ptr;
113 }
114 }
115 return NULL;
116}
117
118static inline void put_sector(SectorCount *ptr, unsigned int sector)
119{
120 ptr->bytes[0] = sector & 0xff;
121 sector >>= 8;
122 ptr->bytes[1] = sector & 0xff;
123 sector >>= 8;
124 ptr->bytes[2] = sector & 0xff;
125}
126
127static inline unsigned int get_sector(SectorCount *ptr)
128{
129#if 1
130 unsigned int sector;
131
132 sector = ptr->bytes[0];
133 sector += ptr->bytes[1] << 8;
134 sector += ptr->bytes[2] << 16;
135
136 return sector;
137#else
138 /* GET4 gets the next four bytes in Intel little endian order
139 * and converts them to host byte order and handles unaligned
140 * access.
141 */
142 return (GET4(ptr, 0) & 0x00ffffff); /* back to host byte order */
143#endif
144}
145
146static void bsm_debug_fake(void)
147{
148 /* for testing of bad sector handling at end of tape
149 */
150#if 0
151 ftape_put_bad_sector_entry(segments_per_track * tracks_per_tape - 3,
152 0x000003e0;
153 ftape_put_bad_sector_entry(segments_per_track * tracks_per_tape - 2,
154 0xff3fffff;
155 ftape_put_bad_sector_entry(segments_per_track * tracks_per_tape - 1,
156 0xffffe000;
157#endif
158 /* Enable to test bad sector handling
159 */
160#if 0
161 ftape_put_bad_sector_entry(30, 0xfffffffe)
162 ftape_put_bad_sector_entry(32, 0x7fffffff);
163 ftape_put_bad_sector_entry(34, 0xfffeffff);
164 ftape_put_bad_sector_entry(36, 0x55555555);
165 ftape_put_bad_sector_entry(38, 0xffffffff);
166 ftape_put_bad_sector_entry(50, 0xffff0000);
167 ftape_put_bad_sector_entry(51, 0xffffffff);
168 ftape_put_bad_sector_entry(52, 0xffffffff);
169 ftape_put_bad_sector_entry(53, 0x0000ffff);
170#endif
171 /* Enable when testing multiple volume tar dumps.
172 */
173#if 0
174 {
175 int i;
176
177 for (i = ft_first_data_segment;
178 i <= ft_last_data_segment - 7; ++i) {
179 ftape_put_bad_sector_entry(i, EMPTY_SEGMENT);
180 }
181 }
182#endif
183 /* Enable when testing bit positions in *_error_map
184 */
185#if 0
186 {
187 int i;
188
189 for (i = first_data_segment; i <= last_data_segment; ++i) {
190 ftape_put_bad_sector_entry(i,
191 ftape_get_bad_sector_entry(i)
192 | 0x00ff00ff);
193 }
194 }
195#endif
196}
197
198static void print_bad_sector_map(void)
199{
200 unsigned int good_sectors;
201 unsigned int total_bad = 0;
202 int i;
203 TRACE_FUN(ft_t_flow);
204
205 if (ft_format_code == fmt_big ||
206 ft_format_code == fmt_var ||
207 ft_format_code == fmt_1100ft) {
208 SectorCount *ptr = (SectorCount *)bad_sector_map;
209 unsigned int sector;
210 __u16 *ptr16;
211
212 while((sector = get_sector(ptr++)) != 0) {
213 if ((ft_format_code == fmt_big ||
214 ft_format_code == fmt_var) &&
215 sector & 0x800000) {
216 total_bad += FT_SECTORS_PER_SEGMENT - 3;
217 TRACE(ft_t_noise, "bad segment at sector: %6d",
218 sector & 0x7fffff);
219 } else {
220 ++total_bad;
221 TRACE(ft_t_noise, "bad sector: %6d", sector);
222 }
223 }
224 /* Display old ftape's end-of-file marks
225 */
226 ptr16 = (__u16*)ptr;
227 while ((sector = get_unaligned(ptr16++)) != 0) {
228 TRACE(ft_t_noise, "Old ftape eof mark: %4d/%2d",
229 sector, get_unaligned(ptr16++));
230 }
231 } else { /* fixed size format */
232 for (i = ft_first_data_segment;
233 i < (int)(ft_segments_per_track * ft_tracks_per_tape); ++i) {
234 SectorMap map = ((SectorMap *) bad_sector_map)[i];
235
236 if (map) {
237 TRACE(ft_t_noise,
238 "bsm for segment %4d: 0x%08x", i, (unsigned int)map);
239 total_bad += ((map == EMPTY_SEGMENT)
240 ? FT_SECTORS_PER_SEGMENT - 3
241 : count_ones(map));
242 }
243 }
244 }
245 good_sectors =
246 ((ft_segments_per_track * ft_tracks_per_tape - ft_first_data_segment)
247 * (FT_SECTORS_PER_SEGMENT - 3)) - total_bad;
248 TRACE(ft_t_info, "%d Kb usable on this tape", good_sectors);
249 if (total_bad == 0) {
250 TRACE(ft_t_info,
251 "WARNING: this tape has no bad blocks registered !");
252 } else {
253 TRACE(ft_t_info, "%d bad sectors", total_bad);
254 }
255 TRACE_EXIT;
256}
257
258
259void ftape_extract_bad_sector_map(__u8 * buffer)
260{
261 TRACE_FUN(ft_t_any);
262
263 /* Fill the bad sector map with the contents of buffer.
264 */
265 if (ft_format_code == fmt_var || ft_format_code == fmt_big) {
266 /* QIC-3010/3020 and wide QIC-80 tapes no longer have a failed
267 * sector log but use this area to extend the bad sector map.
268 */
269 bad_sector_map = &buffer[FT_HEADER_END];
270 } else {
271 /* non-wide QIC-80 tapes have a failed sector log area that
272 * mustn't be included in the bad sector map.
273 */
274 bad_sector_map = &buffer[FT_FSL + FT_FSL_SIZE];
275 }
276 if (ft_format_code == fmt_1100ft ||
277 ft_format_code == fmt_var ||
278 ft_format_code == fmt_big) {
279 bsm_hash_ptr = (SectorCount *)bad_sector_map;
280 } else {
281 bsm_hash_ptr = NULL;
282 }
283 bsm_debug_fake();
284 if (TRACE_LEVEL >= ft_t_info) {
285 print_bad_sector_map();
286 }
287 TRACE_EXIT;
288}
289
290static inline SectorMap cvt2map(unsigned int sector)
291{
292 return 1 << (((sector & 0x7fffff) - 1) % FT_SECTORS_PER_SEGMENT);
293}
294
295static inline int cvt2segment(unsigned int sector)
296{
297 return ((sector & 0x7fffff) - 1) / FT_SECTORS_PER_SEGMENT;
298}
299
300static int forward_seek_entry(int segment_id,
301 SectorCount **ptr,
302 SectorMap *map)
303{
304 unsigned int sector;
305 int segment;
306
307 do {
308 sector = get_sector((*ptr)++);
309 segment = cvt2segment(sector);
310 } while (sector != 0 && segment < segment_id);
311 (*ptr) --; /* point to first sector >= segment_id */
312 /* Get all sectors in segment_id
313 */
314 if (sector == 0 || segment != segment_id) {
315 *map = 0;
316 return 0;
317 } else if ((sector & 0x800000) &&
318 (ft_format_code == fmt_var || ft_format_code == fmt_big)) {
319 *map = EMPTY_SEGMENT;
320 return FT_SECTORS_PER_SEGMENT;
321 } else {
322 int count = 1;
323 SectorCount *tmp_ptr = (*ptr) + 1;
324
325 *map = cvt2map(sector);
326 while ((sector = get_sector(tmp_ptr++)) != 0 &&
327 (segment = cvt2segment(sector)) == segment_id) {
328 *map |= cvt2map(sector);
329 ++count;
330 }
331 return count;
332 }
333}
334
335static int backwards_seek_entry(int segment_id,
336 SectorCount **ptr,
337 SectorMap *map)
338{
339 unsigned int sector;
340 int segment; /* max unsigned int */
341
342 if (*ptr <= (SectorCount *)bad_sector_map) {
343 *map = 0;
344 return 0;
345 }
346 do {
347 sector = get_sector(--(*ptr));
348 segment = cvt2segment(sector);
349 } while (*ptr > (SectorCount *)bad_sector_map && segment > segment_id);
350 if (segment > segment_id) { /* at start of list, no entry found */
351 *map = 0;
352 return 0;
353 } else if (segment < segment_id) {
354 /* before smaller entry, adjust for overshoot */
355 (*ptr) ++;
356 *map = 0;
357 return 0;
358 } else if ((sector & 0x800000) &&
359 (ft_format_code == fmt_big || ft_format_code == fmt_var)) {
360 *map = EMPTY_SEGMENT;
361 return FT_SECTORS_PER_SEGMENT;
362 } else { /* get all sectors in segment_id */
363 int count = 1;
364
365 *map = cvt2map(sector);
366 while(*ptr > (SectorCount *)bad_sector_map) {
367 sector = get_sector(--(*ptr));
368 segment = cvt2segment(sector);
369 if (segment != segment_id) {
370 break;
371 }
372 *map |= cvt2map(sector);
373 ++count;
374 }
375 if (segment < segment_id) {
376 (*ptr) ++;
377 }
378 return count;
379 }
380}
381
382#if 0
383static void ftape_put_bad_sector_entry(int segment_id, SectorMap new_map)
384{
385 SectorCount *ptr = (SectorCount *)bad_sector_map;
386 int count;
387 int new_count;
388 SectorMap map;
389 TRACE_FUN(ft_t_any);
390
391 if (ft_format_code == fmt_1100ft ||
392 ft_format_code == fmt_var ||
393 ft_format_code == fmt_big) {
394 count = forward_seek_entry(segment_id, &ptr, &map);
395 new_count = count_ones(new_map);
396 /* If format code == 4 put empty segment instead of 32
397 * bad sectors.
398 */
399 if (ft_format_code == fmt_var || ft_format_code == fmt_big) {
400 if (new_count == FT_SECTORS_PER_SEGMENT) {
401 new_count = 1;
402 }
403 if (count == FT_SECTORS_PER_SEGMENT) {
404 count = 1;
405 }
406 }
407 if (count != new_count) {
408 /* insert (or delete if < 0) new_count - count
409 * entries. Move trailing part of list
410 * including terminating 0.
411 */
412 SectorCount *hi_ptr = ptr;
413
414 do {
415 } while (get_sector(hi_ptr++) != 0);
416 /* Note: ptr is of type byte *, and each bad sector
417 * consumes 3 bytes.
418 */
419 memmove(ptr + new_count, ptr + count,
420 (size_t)(hi_ptr - (ptr + count))*sizeof(SectorCount));
421 }
422 TRACE(ft_t_noise, "putting map 0x%08x at %p, segment %d",
423 (unsigned int)new_map, ptr, segment_id);
424 if (new_count == 1 && new_map == EMPTY_SEGMENT) {
425 put_sector(ptr++, (0x800001 +
426 segment_id *
427 FT_SECTORS_PER_SEGMENT));
428 } else {
429 int i = 0;
430
431 while (new_map) {
432 if (new_map & 1) {
433 put_sector(ptr++,
434 1 + segment_id *
435 FT_SECTORS_PER_SEGMENT + i);
436 }
437 ++i;
438 new_map >>= 1;
439 }
440 }
441 } else {
442 ((SectorMap *) bad_sector_map)[segment_id] = new_map;
443 }
444 TRACE_EXIT;
445}
446#endif /* 0 */
447
448SectorMap ftape_get_bad_sector_entry(int segment_id)
449{
450 if (ft_used_header_segment == -1) {
451 /* When reading header segment we'll need a blank map.
452 */
453 return 0;
454 } else if (bsm_hash_ptr != NULL) {
455 /* Invariants:
456 * map - mask value returned on last call.
457 * bsm_hash_ptr - points to first sector greater or equal to
458 * first sector in last_referenced segment.
459 * last_referenced - segment id used in the last call,
460 * sector and map belong to this id.
461 * This code is designed for sequential access and retries.
462 * For true random access it may have to be redesigned.
463 */
464 static int last_reference = -1;
465 static SectorMap map;
466
467 if (segment_id > last_reference) {
468 /* Skip all sectors before segment_id
469 */
470 forward_seek_entry(segment_id, &bsm_hash_ptr, &map);
471 } else if (segment_id < last_reference) {
472 /* Skip backwards until begin of buffer or
473 * first sector in segment_id
474 */
475 backwards_seek_entry(segment_id, &bsm_hash_ptr, &map);
476 } /* segment_id == last_reference : keep map */
477 last_reference = segment_id;
478 return map;
479 } else {
480 return ((SectorMap *) bad_sector_map)[segment_id];
481 }
482}
483
484/* This is simply here to prevent us from overwriting other kernel
485 * data. Writes will result in NULL Pointer dereference.
486 */
487void ftape_init_bsm(void)
488{
489 bad_sector_map = NULL;
490 bsm_hash_ptr = NULL;
491}
diff --git a/drivers/char/ftape/lowlevel/ftape-bsm.h b/drivers/char/ftape/lowlevel/ftape-bsm.h
deleted file mode 100644
index ed45465af4d4..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-bsm.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef _FTAPE_BSM_H
2#define _FTAPE_BSM_H
3
4/*
5 * Copyright (C) 1994-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-bsm.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:07 $
26 *
27 * This file contains definitions for the bad sector map handling
28 * routines for the QIC-117 floppy-tape driver for Linux.
29 */
30
31#include <linux/ftape.h>
32#include <linux/ftape-header-segment.h>
33
34#define EMPTY_SEGMENT (0xffffffff)
35#define FAKE_SEGMENT (0xfffffffe)
36
37/* maximum (format code 4) bad sector map size (bytes).
38 */
39#define BAD_SECTOR_MAP_SIZE (29 * SECTOR_SIZE - 256)
40
41/* format code 4 bad sector entry, ftape uses this
42 * internally for all format codes
43 */
44typedef __u32 SectorMap;
45/* variable and 1100 ft bad sector map entry. These three bytes represent
46 * a single sector address measured from BOT.
47 */
48typedef struct NewSectorMap {
49 __u8 bytes[3];
50} SectorCount;
51
52
53/*
54 * ftape-bsm.c defined global vars.
55 */
56
57/*
58 * ftape-bsm.c defined global functions.
59 */
60extern void update_bad_sector_map(__u8 * buffer);
61extern void ftape_extract_bad_sector_map(__u8 * buffer);
62extern SectorMap ftape_get_bad_sector_entry(int segment_id);
63extern __u8 *ftape_find_end_of_bsm_list(__u8 * address);
64extern void ftape_init_bsm(void);
65
66#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-buffer.c b/drivers/char/ftape/lowlevel/ftape-buffer.c
deleted file mode 100644
index c706ff162771..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-buffer.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * Copyright (C) 1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-buffer.c,v $
20 * $Revision: 1.3 $
21 * $Date: 1997/10/16 23:33:11 $
22 *
23 * This file contains the allocator/dealloctor for ftape's dynamic dma
24 * buffer.
25 */
26
27#include <linux/slab.h>
28#include <linux/mm.h>
29#include <linux/mman.h>
30#include <asm/dma.h>
31
32#include <linux/ftape.h>
33#include "../lowlevel/ftape-rw.h"
34#include "../lowlevel/ftape-read.h"
35#include "../lowlevel/ftape-tracing.h"
36#include "../lowlevel/ftape-buffer.h"
37
38/* DMA'able memory allocation stuff.
39 */
40
41static inline void *dmaalloc(size_t size)
42{
43 unsigned long addr;
44
45 if (size == 0) {
46 return NULL;
47 }
48 addr = __get_dma_pages(GFP_KERNEL, get_order(size));
49 if (addr) {
50 struct page *page;
51
52 for (page = virt_to_page(addr); page < virt_to_page(addr+size); page++)
53 SetPageReserved(page);
54 }
55 return (void *)addr;
56}
57
58static inline void dmafree(void *addr, size_t size)
59{
60 if (size > 0) {
61 struct page *page;
62
63 for (page = virt_to_page((unsigned long)addr);
64 page < virt_to_page((unsigned long)addr+size); page++)
65 ClearPageReserved(page);
66 free_pages((unsigned long) addr, get_order(size));
67 }
68}
69
70static int add_one_buffer(void)
71{
72 TRACE_FUN(ft_t_flow);
73
74 if (ft_nr_buffers >= FT_MAX_NR_BUFFERS) {
75 TRACE_EXIT -ENOMEM;
76 }
77 ft_buffer[ft_nr_buffers] = kmalloc(sizeof(buffer_struct), GFP_KERNEL);
78 if (ft_buffer[ft_nr_buffers] == NULL) {
79 TRACE_EXIT -ENOMEM;
80 }
81 memset(ft_buffer[ft_nr_buffers], 0, sizeof(buffer_struct));
82 ft_buffer[ft_nr_buffers]->address = dmaalloc(FT_BUFF_SIZE);
83 if (ft_buffer[ft_nr_buffers]->address == NULL) {
84 kfree(ft_buffer[ft_nr_buffers]);
85 ft_buffer[ft_nr_buffers] = NULL;
86 TRACE_EXIT -ENOMEM;
87 }
88 ft_nr_buffers ++;
89 TRACE(ft_t_info, "buffer nr #%d @ %p, dma area @ %p",
90 ft_nr_buffers,
91 ft_buffer[ft_nr_buffers-1],
92 ft_buffer[ft_nr_buffers-1]->address);
93 TRACE_EXIT 0;
94}
95
96static void del_one_buffer(void)
97{
98 TRACE_FUN(ft_t_flow);
99 if (ft_nr_buffers > 0) {
100 TRACE(ft_t_info, "releasing buffer nr #%d @ %p, dma area @ %p",
101 ft_nr_buffers,
102 ft_buffer[ft_nr_buffers-1],
103 ft_buffer[ft_nr_buffers-1]->address);
104 ft_nr_buffers --;
105 dmafree(ft_buffer[ft_nr_buffers]->address, FT_BUFF_SIZE);
106 kfree(ft_buffer[ft_nr_buffers]);
107 ft_buffer[ft_nr_buffers] = NULL;
108 }
109 TRACE_EXIT;
110}
111
112int ftape_set_nr_buffers(int cnt)
113{
114 int delta = cnt - ft_nr_buffers;
115 TRACE_FUN(ft_t_flow);
116
117 if (delta > 0) {
118 while (delta--) {
119 if (add_one_buffer() < 0) {
120 TRACE_EXIT -ENOMEM;
121 }
122 }
123 } else if (delta < 0) {
124 while (delta++) {
125 del_one_buffer();
126 }
127 }
128 ftape_zap_read_buffers();
129 TRACE_EXIT 0;
130}
diff --git a/drivers/char/ftape/lowlevel/ftape-buffer.h b/drivers/char/ftape/lowlevel/ftape-buffer.h
deleted file mode 100644
index eec99cee8f82..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-buffer.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef _FTAPE_BUFFER_H
2#define _FTAPE_BUFFER_H
3
4/*
5 * Copyright (C) 1997 Claus-Justus Heine.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-buffer.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:18:08 $
25 *
26 * This file contains the allocator/dealloctor for ftape's dynamic dma
27 * buffer.
28 */
29
30extern int ftape_set_nr_buffers(int cnt);
31
32#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-calibr.c b/drivers/char/ftape/lowlevel/ftape-calibr.c
deleted file mode 100644
index 8e50bfd35a52..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-calibr.c
+++ /dev/null
@@ -1,275 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-calibr.c,v $
20 * $Revision: 1.2 $
21 * $Date: 1997/10/05 19:18:08 $
22 *
23 * GP calibration routine for processor speed dependent
24 * functions.
25 */
26
27#include <linux/errno.h>
28#include <linux/jiffies.h>
29#include <asm/system.h>
30#include <asm/io.h>
31#if defined(__alpha__)
32# include <asm/hwrpb.h>
33#elif defined(__x86_64__)
34# include <asm/msr.h>
35# include <asm/timex.h>
36#elif defined(__i386__)
37# include <linux/timex.h>
38#endif
39#include <linux/ftape.h>
40#include "../lowlevel/ftape-tracing.h"
41#include "../lowlevel/ftape-calibr.h"
42#include "../lowlevel/fdc-io.h"
43
44#undef DEBUG
45
46#if !defined(__alpha__) && !defined(__i386__) && !defined(__x86_64__)
47# error Ftape is not implemented for this architecture!
48#endif
49
50#if defined(__alpha__) || defined(__x86_64__)
51static unsigned long ps_per_cycle = 0;
52#endif
53
54static spinlock_t calibr_lock;
55
56/*
57 * Note: On Intel PCs, the clock ticks at 100 Hz (HZ==100) which is
58 * too slow for certain timeouts (and that clock doesn't even tick
59 * when interrupts are disabled). For that reason, the 8254 timer is
60 * used directly to implement fine-grained timeouts. However, on
61 * Alpha PCs, the 8254 is *not* used to implement the clock tick
62 * (which is 1024 Hz, normally) and the 8254 timer runs at some
63 * "random" frequency (it seems to run at 18Hz, but it's not safe to
64 * rely on this value). Instead, we use the Alpha's "rpcc"
65 * instruction to read cycle counts. As this is a 32 bit counter,
66 * it will overflow only once per 30 seconds (on a 200MHz machine),
67 * which is plenty.
68 */
69
70unsigned int ftape_timestamp(void)
71{
72#if defined(__alpha__)
73 unsigned long r;
74
75 asm volatile ("rpcc %0" : "=r" (r));
76 return r;
77#elif defined(__x86_64__)
78 unsigned long r;
79 rdtscl(r);
80 return r;
81#elif defined(__i386__)
82
83/*
84 * Note that there is some time between counter underflowing and jiffies
85 * increasing, so the code below won't always give correct output.
86 * -Vojtech
87 */
88
89 unsigned long flags;
90 __u16 lo;
91 __u16 hi;
92
93 spin_lock_irqsave(&calibr_lock, flags);
94 outb_p(0x00, 0x43); /* latch the count ASAP */
95 lo = inb_p(0x40); /* read the latched count */
96 lo |= inb(0x40) << 8;
97 hi = jiffies;
98 spin_unlock_irqrestore(&calibr_lock, flags);
99 return ((hi + 1) * (unsigned int) LATCH) - lo; /* downcounter ! */
100#endif
101}
102
103static unsigned int short_ftape_timestamp(void)
104{
105#if defined(__alpha__) || defined(__x86_64__)
106 return ftape_timestamp();
107#elif defined(__i386__)
108 unsigned int count;
109 unsigned long flags;
110
111 spin_lock_irqsave(&calibr_lock, flags);
112 outb_p(0x00, 0x43); /* latch the count ASAP */
113 count = inb_p(0x40); /* read the latched count */
114 count |= inb(0x40) << 8;
115 spin_unlock_irqrestore(&calibr_lock, flags);
116 return (LATCH - count); /* normal: downcounter */
117#endif
118}
119
120static unsigned int diff(unsigned int t0, unsigned int t1)
121{
122#if defined(__alpha__) || defined(__x86_64__)
123 return (t1 - t0);
124#elif defined(__i386__)
125 /*
126 * This is tricky: to work for both short and full ftape_timestamps
127 * we'll have to discriminate between these.
128 * If it _looks_ like short stamps with wrapping around we'll
129 * asume it are. This will generate a small error if it really
130 * was a (very large) delta from full ftape_timestamps.
131 */
132 return (t1 <= t0 && t0 <= LATCH) ? t1 + LATCH - t0 : t1 - t0;
133#endif
134}
135
136static unsigned int usecs(unsigned int count)
137{
138#if defined(__alpha__) || defined(__x86_64__)
139 return (ps_per_cycle * count) / 1000000UL;
140#elif defined(__i386__)
141 return (10000 * count) / ((CLOCK_TICK_RATE + 50) / 100);
142#endif
143}
144
145unsigned int ftape_timediff(unsigned int t0, unsigned int t1)
146{
147 /*
148 * Calculate difference in usec for ftape_timestamp results t0 & t1.
149 * Note that on the i386 platform with short time-stamps, the
150 * maximum allowed timespan is 1/HZ or we'll lose ticks!
151 */
152 return usecs(diff(t0, t1));
153}
154
155/* To get an indication of the I/O performance,
156 * measure the duration of the inb() function.
157 */
158static void time_inb(void)
159{
160 int i;
161 int t0, t1;
162 unsigned long flags;
163 int status;
164 TRACE_FUN(ft_t_any);
165
166 spin_lock_irqsave(&calibr_lock, flags);
167 t0 = short_ftape_timestamp();
168 for (i = 0; i < 1000; ++i) {
169 status = inb(fdc.msr);
170 }
171 t1 = short_ftape_timestamp();
172 spin_unlock_irqrestore(&calibr_lock, flags);
173 TRACE(ft_t_info, "inb() duration: %d nsec", ftape_timediff(t0, t1));
174 TRACE_EXIT;
175}
176
177static void init_clock(void)
178{
179 TRACE_FUN(ft_t_any);
180
181#if defined(__x86_64__)
182 ps_per_cycle = 1000000000UL / cpu_khz;
183#elif defined(__alpha__)
184 extern struct hwrpb_struct *hwrpb;
185 ps_per_cycle = (1000*1000*1000*1000UL) / hwrpb->cycle_freq;
186#endif
187 TRACE_EXIT;
188}
189
190/*
191 * Input: function taking int count as parameter.
192 * pointers to calculated calibration variables.
193 */
194void ftape_calibrate(char *name,
195 void (*fun) (unsigned int),
196 unsigned int *calibr_count,
197 unsigned int *calibr_time)
198{
199 static int first_time = 1;
200 int i;
201 unsigned int tc = 0;
202 unsigned int count;
203 unsigned int time;
204#if defined(__i386__)
205 unsigned int old_tc = 0;
206 unsigned int old_count = 1;
207 unsigned int old_time = 1;
208#endif
209 TRACE_FUN(ft_t_flow);
210
211 if (first_time) { /* get idea of I/O performance */
212 init_clock();
213 time_inb();
214 first_time = 0;
215 }
216 /* value of timeout must be set so that on very slow systems
217 * it will give a time less than one jiffy, and on
218 * very fast systems it'll give reasonable precision.
219 */
220
221 count = 40;
222 for (i = 0; i < 15; ++i) {
223 unsigned int t0;
224 unsigned int t1;
225 unsigned int once;
226 unsigned int multiple;
227 unsigned long flags;
228
229 *calibr_count =
230 *calibr_time = count; /* set TC to 1 */
231 spin_lock_irqsave(&calibr_lock, flags);
232 fun(0); /* dummy, get code into cache */
233 t0 = short_ftape_timestamp();
234 fun(0); /* overhead + one test */
235 t1 = short_ftape_timestamp();
236 once = diff(t0, t1);
237 t0 = short_ftape_timestamp();
238 fun(count); /* overhead + count tests */
239 t1 = short_ftape_timestamp();
240 multiple = diff(t0, t1);
241 spin_unlock_irqrestore(&calibr_lock, flags);
242 time = ftape_timediff(0, multiple - once);
243 tc = (1000 * time) / (count - 1);
244 TRACE(ft_t_any, "once:%3d us,%6d times:%6d us, TC:%5d ns",
245 usecs(once), count - 1, usecs(multiple), tc);
246#if defined(__alpha__) || defined(__x86_64__)
247 /*
248 * Increase the calibration count exponentially until the
249 * calibration time exceeds 100 ms.
250 */
251 if (time >= 100*1000) {
252 break;
253 }
254#elif defined(__i386__)
255 /*
256 * increase the count until the resulting time nears 2/HZ,
257 * then the tc will drop sharply because we lose LATCH counts.
258 */
259 if (tc <= old_tc / 2) {
260 time = old_time;
261 count = old_count;
262 break;
263 }
264 old_tc = tc;
265 old_count = count;
266 old_time = time;
267#endif
268 count *= 2;
269 }
270 *calibr_count = count - 1;
271 *calibr_time = time;
272 TRACE(ft_t_info, "TC for `%s()' = %d nsec (at %d counts)",
273 name, (1000 * *calibr_time) / *calibr_count, *calibr_count);
274 TRACE_EXIT;
275}
diff --git a/drivers/char/ftape/lowlevel/ftape-calibr.h b/drivers/char/ftape/lowlevel/ftape-calibr.h
deleted file mode 100644
index 0c7e75246c7d..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-calibr.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef _FTAPE_CALIBR_H
2#define _FTAPE_CALIBR_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-calibr.h,v $
23 * $Revision: 1.1 $
24 * $Date: 1997/09/19 09:05:26 $
25 *
26 * This file contains a gp calibration routine for
27 * hardware dependent timeout functions.
28 */
29
30extern void ftape_calibrate(char *name,
31 void (*fun) (unsigned int),
32 unsigned int *calibr_count,
33 unsigned int *calibr_time);
34extern unsigned int ftape_timestamp(void);
35extern unsigned int ftape_timediff(unsigned int t0, unsigned int t1);
36
37#endif /* _FTAPE_CALIBR_H */
diff --git a/drivers/char/ftape/lowlevel/ftape-ctl.c b/drivers/char/ftape/lowlevel/ftape-ctl.c
deleted file mode 100644
index 5d7c1ce92d59..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-ctl.c
+++ /dev/null
@@ -1,896 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-ctl.c,v $
21 * $Revision: 1.4 $
22 * $Date: 1997/11/11 14:37:44 $
23 *
24 * This file contains the non-read/write ftape functions for the
25 * QIC-40/80/3010/3020 floppy-tape driver "ftape" for Linux.
26 */
27
28#include <linux/errno.h>
29#include <linux/mm.h>
30#include <linux/mman.h>
31
32#include <linux/ftape.h>
33#include <linux/qic117.h>
34#include <asm/uaccess.h>
35#include <asm/io.h>
36
37/* ease porting between pre-2.4.x and later kernels */
38#define vma_get_pgoff(v) ((v)->vm_pgoff)
39
40#include "../lowlevel/ftape-tracing.h"
41#include "../lowlevel/ftape-io.h"
42#include "../lowlevel/ftape-ctl.h"
43#include "../lowlevel/ftape-write.h"
44#include "../lowlevel/ftape-read.h"
45#include "../lowlevel/ftape-rw.h"
46#include "../lowlevel/ftape-bsm.h"
47
48/* Global vars.
49 */
50ftape_info ftape_status = {
51/* vendor information */
52 { 0, }, /* drive type */
53/* data rates */
54 500, /* used data rate */
55 500, /* drive max rate */
56 500, /* fdc max rate */
57/* drive selection, either FTAPE_SEL_A/B/C/D */
58 -1, /* drive selection */
59/* flags set after decode the drive and tape status */
60 0, /* formatted */
61 1, /* no tape */
62 1, /* write protected */
63 1, /* new tape */
64/* values of last queried drive/tape status and error */
65 {{0,}}, /* last error code */
66 {{0,}}, /* drive status, configuration, tape status */
67/* cartridge geometry */
68 20, /* tracks_per_tape */
69 102, /* segments_per_track */
70/* location of header segments, etc. */
71 -1, /* used_header_segment */
72 -1, /* header_segment_1 */
73 -1, /* header_segment_2 */
74 -1, /* first_data_segment */
75 -1, /* last_data_segment */
76/* the format code as stored in the header segment */
77 fmt_normal, /* format code */
78/* the default for the qic std: unknown */
79 -1,
80/* is tape running? */
81 idle, /* runner_state */
82/* is tape reading/writing/verifying/formatting/deleting */
83 idle, /* driver state */
84/* flags fatal hardware error */
85 1, /* failure */
86/* history record */
87 { 0, } /* history record */
88};
89
90int ftape_segments_per_head = 1020;
91int ftape_segments_per_cylinder = 4;
92int ftape_init_drive_needed = 1; /* need to be global for ftape_reset_drive()
93 * in ftape-io.c
94 */
95
96/* Local vars.
97 */
98static const vendor_struct vendors[] = QIC117_VENDORS;
99static const wakeup_method methods[] = WAKEUP_METHODS;
100
101const ftape_info *ftape_get_status(void)
102{
103#if defined(STATUS_PARANOYA)
104 static ftape_info get_status;
105
106 get_status = ftape_status;
107 return &get_status;
108#else
109 return &ftape_status; /* maybe return only a copy of it to assure
110 * read only access
111 */
112#endif
113}
114
115static int ftape_not_operational(int status)
116{
117 /* return true if status indicates tape can not be used.
118 */
119 return ((status ^ QIC_STATUS_CARTRIDGE_PRESENT) &
120 (QIC_STATUS_ERROR |
121 QIC_STATUS_CARTRIDGE_PRESENT |
122 QIC_STATUS_NEW_CARTRIDGE));
123}
124
125int ftape_seek_to_eot(void)
126{
127 int status;
128 TRACE_FUN(ft_t_any);
129
130 TRACE_CATCH(ftape_ready_wait(ftape_timeout.pause, &status),);
131 while ((status & QIC_STATUS_AT_EOT) == 0) {
132 if (ftape_not_operational(status)) {
133 TRACE_EXIT -EIO;
134 }
135 TRACE_CATCH(ftape_command_wait(QIC_PHYSICAL_FORWARD,
136 ftape_timeout.rewind,&status),);
137 }
138 TRACE_EXIT 0;
139}
140
141int ftape_seek_to_bot(void)
142{
143 int status;
144 TRACE_FUN(ft_t_any);
145
146 TRACE_CATCH(ftape_ready_wait(ftape_timeout.pause, &status),);
147 while ((status & QIC_STATUS_AT_BOT) == 0) {
148 if (ftape_not_operational(status)) {
149 TRACE_EXIT -EIO;
150 }
151 TRACE_CATCH(ftape_command_wait(QIC_PHYSICAL_REVERSE,
152 ftape_timeout.rewind,&status),);
153 }
154 TRACE_EXIT 0;
155}
156
157static int ftape_new_cartridge(void)
158{
159 ft_location.track = -1; /* force seek on first access */
160 ftape_zap_read_buffers();
161 ftape_zap_write_buffers();
162 return 0;
163}
164
165int ftape_abort_operation(void)
166{
167 int result = 0;
168 int status;
169 TRACE_FUN(ft_t_flow);
170
171 if (ft_runner_status == running) {
172 TRACE(ft_t_noise, "aborting runner, waiting");
173
174 ft_runner_status = do_abort;
175 /* set timeout so that the tape will run to logical EOT
176 * if we missed the last sector and there are no queue pulses.
177 */
178 result = ftape_dumb_stop();
179 }
180 if (ft_runner_status != idle) {
181 if (ft_runner_status == do_abort) {
182 TRACE(ft_t_noise, "forcing runner abort");
183 }
184 TRACE(ft_t_noise, "stopping tape");
185 result = ftape_stop_tape(&status);
186 ft_location.known = 0;
187 ft_runner_status = idle;
188 }
189 ftape_reset_buffer();
190 ftape_zap_read_buffers();
191 ftape_set_state(idle);
192 TRACE_EXIT result;
193}
194
195static int lookup_vendor_id(unsigned int vendor_id)
196{
197 int i = 0;
198
199 while (vendors[i].vendor_id != vendor_id) {
200 if (++i >= NR_ITEMS(vendors)) {
201 return -1;
202 }
203 }
204 return i;
205}
206
207static void ftape_detach_drive(void)
208{
209 TRACE_FUN(ft_t_any);
210
211 TRACE(ft_t_flow, "disabling tape drive and fdc");
212 ftape_put_drive_to_sleep(ft_drive_type.wake_up);
213 fdc_catch_stray_interrupts(1); /* one always comes */
214 fdc_disable();
215 fdc_release_irq_and_dma();
216 fdc_release_regions();
217 TRACE_EXIT;
218}
219
220static void clear_history(void)
221{
222 ft_history.used = 0;
223 ft_history.id_am_errors =
224 ft_history.id_crc_errors =
225 ft_history.data_am_errors =
226 ft_history.data_crc_errors =
227 ft_history.overrun_errors =
228 ft_history.no_data_errors =
229 ft_history.retries =
230 ft_history.crc_errors =
231 ft_history.crc_failures =
232 ft_history.ecc_failures =
233 ft_history.corrected =
234 ft_history.defects =
235 ft_history.rewinds = 0;
236}
237
238static int ftape_activate_drive(vendor_struct * drive_type)
239{
240 int result = 0;
241 TRACE_FUN(ft_t_flow);
242
243 /* If we already know the drive type, wake it up.
244 * Else try to find out what kind of drive is attached.
245 */
246 if (drive_type->wake_up != unknown_wake_up) {
247 TRACE(ft_t_flow, "enabling tape drive and fdc");
248 result = ftape_wakeup_drive(drive_type->wake_up);
249 if (result < 0) {
250 TRACE(ft_t_err, "known wakeup method failed");
251 }
252 } else {
253 wake_up_types method;
254 const ft_trace_t old_tracing = TRACE_LEVEL;
255 if (TRACE_LEVEL < ft_t_flow) {
256 SET_TRACE_LEVEL(ft_t_bug);
257 }
258
259 /* Try to awaken the drive using all known methods.
260 * Lower tracing for a while.
261 */
262 for (method=no_wake_up; method < NR_ITEMS(methods); ++method) {
263 drive_type->wake_up = method;
264#ifdef CONFIG_FT_TWO_DRIVES
265 /* Test setup for dual drive configuration.
266 * /dev/rft2 uses mountain wakeup
267 * /dev/rft3 uses colorado wakeup
268 * Other systems will use the normal scheme.
269 */
270 if ((ft_drive_sel < 2) ||
271 (ft_drive_sel == 2 && method == FT_WAKE_UP_1) ||
272 (ft_drive_sel == 3 && method == FT_WAKE_UP_2)) {
273 result=ftape_wakeup_drive(drive_type->wake_up);
274 } else {
275 result = -EIO;
276 }
277#else
278 result = ftape_wakeup_drive(drive_type->wake_up);
279#endif
280 if (result >= 0) {
281 TRACE(ft_t_warn, "drive wakeup method: %s",
282 methods[drive_type->wake_up].name);
283 break;
284 }
285 }
286 SET_TRACE_LEVEL(old_tracing);
287
288 if (method >= NR_ITEMS(methods)) {
289 /* no response at all, cannot open this drive */
290 drive_type->wake_up = unknown_wake_up;
291 TRACE(ft_t_err, "no tape drive found !");
292 result = -ENODEV;
293 }
294 }
295 TRACE_EXIT result;
296}
297
298static int ftape_get_drive_status(void)
299{
300 int result;
301 int status;
302 TRACE_FUN(ft_t_flow);
303
304 ft_no_tape = ft_write_protected = 0;
305 /* Tape drive is activated now.
306 * First clear error status if present.
307 */
308 do {
309 result = ftape_ready_wait(ftape_timeout.reset, &status);
310 if (result < 0) {
311 if (result == -ETIME) {
312 TRACE(ft_t_err, "ftape_ready_wait timeout");
313 } else if (result == -EINTR) {
314 TRACE(ft_t_err, "ftape_ready_wait aborted");
315 } else {
316 TRACE(ft_t_err, "ftape_ready_wait failed");
317 }
318 TRACE_EXIT -EIO;
319 }
320 /* Clear error condition (drive is ready !)
321 */
322 if (status & QIC_STATUS_ERROR) {
323 unsigned int error;
324 qic117_cmd_t command;
325
326 TRACE(ft_t_err, "error status set");
327 result = ftape_report_error(&error, &command, 1);
328 if (result < 0) {
329 TRACE(ft_t_err,
330 "report_error_code failed: %d", result);
331 /* hope it's working next time */
332 ftape_reset_drive();
333 TRACE_EXIT -EIO;
334 } else if (error != 0) {
335 TRACE(ft_t_noise, "error code : %d", error);
336 TRACE(ft_t_noise, "error command: %d", command);
337 }
338 }
339 if (status & QIC_STATUS_NEW_CARTRIDGE) {
340 unsigned int error;
341 qic117_cmd_t command;
342 const ft_trace_t old_tracing = TRACE_LEVEL;
343 SET_TRACE_LEVEL(ft_t_bug);
344
345 /* Undocumented feature: Must clear (not present!)
346 * error here or we'll fail later.
347 */
348 ftape_report_error(&error, &command, 1);
349
350 SET_TRACE_LEVEL(old_tracing);
351 TRACE(ft_t_info, "status: new cartridge");
352 ft_new_tape = 1;
353 } else {
354 ft_new_tape = 0;
355 }
356 FT_SIGNAL_EXIT(_DONT_BLOCK);
357 } while (status & QIC_STATUS_ERROR);
358
359 ft_no_tape = !(status & QIC_STATUS_CARTRIDGE_PRESENT);
360 ft_write_protected = (status & QIC_STATUS_WRITE_PROTECT) != 0;
361 if (ft_no_tape) {
362 TRACE(ft_t_warn, "no cartridge present");
363 } else {
364 if (ft_write_protected) {
365 TRACE(ft_t_noise, "Write protected cartridge");
366 }
367 }
368 TRACE_EXIT 0;
369}
370
371static void ftape_log_vendor_id(void)
372{
373 int vendor_index;
374 TRACE_FUN(ft_t_flow);
375
376 ftape_report_vendor_id(&ft_drive_type.vendor_id);
377 vendor_index = lookup_vendor_id(ft_drive_type.vendor_id);
378 if (ft_drive_type.vendor_id == UNKNOWN_VENDOR &&
379 ft_drive_type.wake_up == wake_up_colorado) {
380 vendor_index = 0;
381 /* hack to get rid of all this mail */
382 ft_drive_type.vendor_id = 0;
383 }
384 if (vendor_index < 0) {
385 /* Unknown vendor id, first time opening device. The
386 * drive_type remains set to type found at wakeup
387 * time, this will probably keep the driver operating
388 * for this new vendor.
389 */
390 TRACE(ft_t_warn, "\n"
391 KERN_INFO "============ unknown vendor id ===========\n"
392 KERN_INFO "A new, yet unsupported tape drive is found\n"
393 KERN_INFO "Please report the following values:\n"
394 KERN_INFO " Vendor id : 0x%04x\n"
395 KERN_INFO " Wakeup method : %s\n"
396 KERN_INFO "And a description of your tape drive\n"
397 KERN_INFO "to "THE_FTAPE_MAINTAINER"\n"
398 KERN_INFO "==========================================",
399 ft_drive_type.vendor_id,
400 methods[ft_drive_type.wake_up].name);
401 ft_drive_type.speed = 0; /* unknown */
402 } else {
403 ft_drive_type.name = vendors[vendor_index].name;
404 ft_drive_type.speed = vendors[vendor_index].speed;
405 TRACE(ft_t_info, "tape drive type: %s", ft_drive_type.name);
406 /* scan all methods for this vendor_id in table */
407 while(ft_drive_type.wake_up != vendors[vendor_index].wake_up) {
408 if (vendor_index < NR_ITEMS(vendors) - 1 &&
409 vendors[vendor_index + 1].vendor_id
410 ==
411 ft_drive_type.vendor_id) {
412 ++vendor_index;
413 } else {
414 break;
415 }
416 }
417 if (ft_drive_type.wake_up != vendors[vendor_index].wake_up) {
418 TRACE(ft_t_warn, "\n"
419 KERN_INFO "==========================================\n"
420 KERN_INFO "wakeup type mismatch:\n"
421 KERN_INFO "found: %s, expected: %s\n"
422 KERN_INFO "please report this to "THE_FTAPE_MAINTAINER"\n"
423 KERN_INFO "==========================================",
424 methods[ft_drive_type.wake_up].name,
425 methods[vendors[vendor_index].wake_up].name);
426 }
427 }
428 TRACE_EXIT;
429}
430
431void ftape_calc_timeouts(unsigned int qic_std,
432 unsigned int data_rate,
433 unsigned int tape_len)
434{
435 int speed; /* deci-ips ! */
436 int ff_speed;
437 int length;
438 TRACE_FUN(ft_t_any);
439
440 /* tape transport speed
441 * data rate: QIC-40 QIC-80 QIC-3010 QIC-3020
442 *
443 * 250 Kbps 25 ips n/a n/a n/a
444 * 500 Kbps 50 ips 34 ips 22.6 ips n/a
445 * 1 Mbps n/a 68 ips 45.2 ips 22.6 ips
446 * 2 Mbps n/a n/a n/a 45.2 ips
447 *
448 * fast tape transport speed is at least 68 ips.
449 */
450 switch (qic_std) {
451 case QIC_TAPE_QIC40:
452 speed = (data_rate == 250) ? 250 : 500;
453 break;
454 case QIC_TAPE_QIC80:
455 speed = (data_rate == 500) ? 340 : 680;
456 break;
457 case QIC_TAPE_QIC3010:
458 speed = (data_rate == 500) ? 226 : 452;
459 break;
460 case QIC_TAPE_QIC3020:
461 speed = (data_rate == 1000) ? 226 : 452;
462 break;
463 default:
464 TRACE(ft_t_bug, "Unknown qic_std (bug) ?");
465 speed = 500;
466 break;
467 }
468 if (ft_drive_type.speed == 0) {
469 unsigned long t0;
470 static int dt = 0; /* keep gcc from complaining */
471 static int first_time = 1;
472
473 /* Measure the time it takes to wind to EOT and back to BOT.
474 * If the tape length is known, calculate the rewind speed.
475 * Else keep the time value for calculation of the rewind
476 * speed later on, when the length _is_ known.
477 * Ask for a report only when length and speed are both known.
478 */
479 if (first_time) {
480 ftape_seek_to_bot();
481 t0 = jiffies;
482 ftape_seek_to_eot();
483 ftape_seek_to_bot();
484 dt = (int) (((jiffies - t0) * FT_USPT) / 1000);
485 if (dt < 1) {
486 dt = 1; /* prevent div by zero on failures */
487 }
488 first_time = 0;
489 TRACE(ft_t_info,
490 "trying to determine seek timeout, got %d msec",
491 dt);
492 }
493 if (tape_len != 0) {
494 ft_drive_type.speed =
495 (2 * 12 * tape_len * 1000) / dt;
496 TRACE(ft_t_warn, "\n"
497 KERN_INFO "==========================================\n"
498 KERN_INFO "drive type: %s\n"
499 KERN_INFO "delta time = %d ms, length = %d ft\n"
500 KERN_INFO "has a maximum tape speed of %d ips\n"
501 KERN_INFO "please report this to "THE_FTAPE_MAINTAINER"\n"
502 KERN_INFO "==========================================",
503 ft_drive_type.name, dt, tape_len,
504 ft_drive_type.speed);
505 }
506 }
507 /* Handle unknown length tapes as very long ones. We'll
508 * determine the actual length from a header segment later.
509 * This is normal for all modern (Wide,TR1/2/3) formats.
510 */
511 if (tape_len <= 0) {
512 TRACE(ft_t_noise,
513 "Unknown tape length, using maximal timeouts");
514 length = QIC_TOP_TAPE_LEN; /* use worst case values */
515 } else {
516 length = tape_len; /* use actual values */
517 }
518 if (ft_drive_type.speed == 0) {
519 ff_speed = speed;
520 } else {
521 ff_speed = ft_drive_type.speed;
522 }
523 /* time to go from bot to eot at normal speed (data rate):
524 * time = (1+delta) * length (ft) * 12 (inch/ft) / speed (ips)
525 * delta = 10 % for seek speed, 20 % for rewind speed.
526 */
527 ftape_timeout.seek = (length * 132 * FT_SECOND) / speed;
528 ftape_timeout.rewind = (length * 144 * FT_SECOND) / (10 * ff_speed);
529 ftape_timeout.reset = 20 * FT_SECOND + ftape_timeout.rewind;
530 TRACE(ft_t_noise, "timeouts for speed = %d, length = %d\n"
531 KERN_INFO "seek timeout : %d sec\n"
532 KERN_INFO "rewind timeout: %d sec\n"
533 KERN_INFO "reset timeout : %d sec",
534 speed, length,
535 (ftape_timeout.seek + 500) / 1000,
536 (ftape_timeout.rewind + 500) / 1000,
537 (ftape_timeout.reset + 500) / 1000);
538 TRACE_EXIT;
539}
540
541/* This function calibrates the datarate (i.e. determines the maximal
542 * usable data rate) and sets the global variable ft_qic_std to qic_std
543 *
544 */
545int ftape_calibrate_data_rate(unsigned int qic_std)
546{
547 int rate = ft_fdc_rate_limit;
548 int result;
549 TRACE_FUN(ft_t_flow);
550
551 ft_qic_std = qic_std;
552
553 if (ft_qic_std == -1) {
554 TRACE_ABORT(-EIO, ft_t_err,
555 "Unable to determine data rate if QIC standard is unknown");
556 }
557
558 /* Select highest rate supported by both fdc and drive.
559 * Start with highest rate supported by the fdc.
560 */
561 while (fdc_set_data_rate(rate) < 0 && rate > 250) {
562 rate /= 2;
563 }
564 TRACE(ft_t_info,
565 "Highest FDC supported data rate: %d Kbps", rate);
566 ft_fdc_max_rate = rate;
567 do {
568 result = ftape_set_data_rate(rate, ft_qic_std);
569 } while (result == -EINVAL && (rate /= 2) > 250);
570 if (result < 0) {
571 TRACE_ABORT(-EIO, ft_t_err, "set datarate failed");
572 }
573 ft_data_rate = rate;
574 TRACE_EXIT 0;
575}
576
577static int ftape_init_drive(void)
578{
579 int status;
580 qic_model model;
581 unsigned int qic_std;
582 unsigned int data_rate;
583 TRACE_FUN(ft_t_flow);
584
585 ftape_init_drive_needed = 0; /* don't retry if this fails ? */
586 TRACE_CATCH(ftape_report_raw_drive_status(&status),);
587 if (status & QIC_STATUS_CARTRIDGE_PRESENT) {
588 if (!(status & QIC_STATUS_AT_BOT)) {
589 /* Antique drives will get here after a soft reset,
590 * modern ones only if the driver is loaded when the
591 * tape wasn't rewound properly.
592 */
593 /* Tape should be at bot if new cartridge ! */
594 ftape_seek_to_bot();
595 }
596 if (!(status & QIC_STATUS_REFERENCED)) {
597 TRACE(ft_t_flow, "starting seek_load_point");
598 TRACE_CATCH(ftape_command_wait(QIC_SEEK_LOAD_POINT,
599 ftape_timeout.reset,
600 &status),);
601 }
602 }
603 ft_formatted = (status & QIC_STATUS_REFERENCED) != 0;
604 if (!ft_formatted) {
605 TRACE(ft_t_warn, "Warning: tape is not formatted !");
606 }
607
608 /* report configuration aborts when ftape_tape_len == -1
609 * unknown qic_std is okay if not formatted.
610 */
611 TRACE_CATCH(ftape_report_configuration(&model,
612 &data_rate,
613 &qic_std,
614 &ftape_tape_len),);
615
616 /* Maybe add the following to the /proc entry
617 */
618 TRACE(ft_t_info, "%s drive @ %d Kbps",
619 (model == prehistoric) ? "prehistoric" :
620 ((model == pre_qic117c) ? "pre QIC-117C" :
621 ((model == post_qic117b) ? "post QIC-117B" :
622 "post QIC-117D")), data_rate);
623
624 if (ft_formatted) {
625 /* initialize ft_used_data_rate to maximum value
626 * and set ft_qic_std
627 */
628 TRACE_CATCH(ftape_calibrate_data_rate(qic_std),);
629 if (ftape_tape_len == 0) {
630 TRACE(ft_t_info, "unknown length QIC-%s tape",
631 (ft_qic_std == QIC_TAPE_QIC40) ? "40" :
632 ((ft_qic_std == QIC_TAPE_QIC80) ? "80" :
633 ((ft_qic_std == QIC_TAPE_QIC3010)
634 ? "3010" : "3020")));
635 } else {
636 TRACE(ft_t_info, "%d ft. QIC-%s tape", ftape_tape_len,
637 (ft_qic_std == QIC_TAPE_QIC40) ? "40" :
638 ((ft_qic_std == QIC_TAPE_QIC80) ? "80" :
639 ((ft_qic_std == QIC_TAPE_QIC3010)
640 ? "3010" : "3020")));
641 }
642 ftape_calc_timeouts(ft_qic_std, ft_data_rate, ftape_tape_len);
643 /* soft write-protect QIC-40/QIC-80 cartridges used with a
644 * Colorado T3000 drive. Buggy hardware!
645 */
646 if ((ft_drive_type.vendor_id == 0x011c6) &&
647 ((ft_qic_std == QIC_TAPE_QIC40 ||
648 ft_qic_std == QIC_TAPE_QIC80) &&
649 !ft_write_protected)) {
650 TRACE(ft_t_warn, "\n"
651 KERN_INFO "The famous Colorado T3000 bug:\n"
652 KERN_INFO "%s drives can't write QIC40 and QIC80\n"
653 KERN_INFO "cartridges but don't set the write-protect flag!",
654 ft_drive_type.name);
655 ft_write_protected = 1;
656 }
657 } else {
658 /* Doesn't make too much sense to set the data rate
659 * because we don't know what to use for the write
660 * precompensation.
661 * Need to do this again when formatting the cartridge.
662 */
663 ft_data_rate = data_rate;
664 ftape_calc_timeouts(QIC_TAPE_QIC40,
665 data_rate,
666 ftape_tape_len);
667 }
668 ftape_new_cartridge();
669 TRACE_EXIT 0;
670}
671
672static void ftape_munmap(void)
673{
674 int i;
675 TRACE_FUN(ft_t_flow);
676
677 for (i = 0; i < ft_nr_buffers; i++) {
678 ft_buffer[i]->mmapped = 0;
679 }
680 TRACE_EXIT;
681}
682
683/* Map the dma buffers into the virtual address range given by vma.
684 * We only check the caller doesn't map non-existent buffers. We
685 * don't check for multiple mappings.
686 */
687int ftape_mmap(struct vm_area_struct *vma)
688{
689 int num_buffers;
690 int i;
691 TRACE_FUN(ft_t_flow);
692
693 if (ft_failure) {
694 TRACE_EXIT -ENODEV;
695 }
696 if (!(vma->vm_flags & (VM_READ|VM_WRITE))) {
697 TRACE_ABORT(-EINVAL, ft_t_err, "Undefined mmap() access");
698 }
699 if (vma_get_pgoff(vma) != 0) {
700 TRACE_ABORT(-EINVAL, ft_t_err, "page offset must be 0");
701 }
702 if ((vma->vm_end - vma->vm_start) % FT_BUFF_SIZE != 0) {
703 TRACE_ABORT(-EINVAL, ft_t_err,
704 "size = %ld, should be a multiple of %d",
705 vma->vm_end - vma->vm_start,
706 FT_BUFF_SIZE);
707 }
708 num_buffers = (vma->vm_end - vma->vm_start) / FT_BUFF_SIZE;
709 if (num_buffers > ft_nr_buffers) {
710 TRACE_ABORT(-EINVAL,
711 ft_t_err, "size = %ld, should be less than %d",
712 vma->vm_end - vma->vm_start,
713 ft_nr_buffers * FT_BUFF_SIZE);
714 }
715 if (ft_driver_state != idle) {
716 /* this also clears the buffer states
717 */
718 ftape_abort_operation();
719 } else {
720 ftape_reset_buffer();
721 }
722 for (i = 0; i < num_buffers; i++) {
723 unsigned long pfn;
724
725 pfn = virt_to_phys(ft_buffer[i]->address) >> PAGE_SHIFT;
726 TRACE_CATCH(remap_pfn_range(vma, vma->vm_start +
727 i * FT_BUFF_SIZE,
728 pfn,
729 FT_BUFF_SIZE,
730 vma->vm_page_prot),
731 _res = -EAGAIN);
732 TRACE(ft_t_noise, "remapped dma buffer @ %p to location @ %p",
733 ft_buffer[i]->address,
734 (void *)(vma->vm_start + i * FT_BUFF_SIZE));
735 }
736 for (i = 0; i < num_buffers; i++) {
737 memset(ft_buffer[i]->address, 0xAA, FT_BUFF_SIZE);
738 ft_buffer[i]->mmapped++;
739 }
740 TRACE_EXIT 0;
741}
742
743static void ftape_init_driver(void); /* forward declaration */
744
745/* OPEN routine called by kernel-interface code
746 */
747int ftape_enable(int drive_selection)
748{
749 TRACE_FUN(ft_t_any);
750
751 if (ft_drive_sel == -1 || ft_drive_sel != drive_selection) {
752 /* Other selection than last time
753 */
754 ftape_init_driver();
755 }
756 ft_drive_sel = FTAPE_SEL(drive_selection);
757 ft_failure = 0;
758 TRACE_CATCH(fdc_init(),); /* init & detect fdc */
759 TRACE_CATCH(ftape_activate_drive(&ft_drive_type),
760 fdc_disable();
761 fdc_release_irq_and_dma();
762 fdc_release_regions());
763 TRACE_CATCH(ftape_get_drive_status(), ftape_detach_drive());
764 if (ft_drive_type.vendor_id == UNKNOWN_VENDOR) {
765 ftape_log_vendor_id();
766 }
767 if (ft_new_tape) {
768 ftape_init_drive_needed = 1;
769 }
770 if (!ft_no_tape && ftape_init_drive_needed) {
771 TRACE_CATCH(ftape_init_drive(), ftape_detach_drive());
772 }
773 ftape_munmap(); /* clear the mmap flag */
774 clear_history();
775 TRACE_EXIT 0;
776}
777
778/* release routine called by the high level interface modules
779 * zftape or sftape.
780 */
781void ftape_disable(void)
782{
783 int i;
784 TRACE_FUN(ft_t_any);
785
786 for (i = 0; i < ft_nr_buffers; i++) {
787 if (ft_buffer[i]->mmapped) {
788 TRACE(ft_t_noise, "first byte of buffer %d: 0x%02x",
789 i, *ft_buffer[i]->address);
790 }
791 }
792 if (sigtestsetmask(&current->pending.signal, _DONT_BLOCK) &&
793 !(sigtestsetmask(&current->pending.signal, _NEVER_BLOCK)) &&
794 ftape_tape_running) {
795 TRACE(ft_t_warn,
796 "Interrupted by fatal signal and tape still running");
797 ftape_dumb_stop();
798 ftape_abort_operation(); /* it's annoying */
799 } else {
800 ftape_set_state(idle);
801 }
802 ftape_detach_drive();
803 if (ft_history.used) {
804 TRACE(ft_t_info, "== Non-fatal errors this run: ==");
805 TRACE(ft_t_info, "fdc isr statistics:\n"
806 KERN_INFO " id_am_errors : %3d\n"
807 KERN_INFO " id_crc_errors : %3d\n"
808 KERN_INFO " data_am_errors : %3d\n"
809 KERN_INFO " data_crc_errors : %3d\n"
810 KERN_INFO " overrun_errors : %3d\n"
811 KERN_INFO " no_data_errors : %3d\n"
812 KERN_INFO " retries : %3d",
813 ft_history.id_am_errors, ft_history.id_crc_errors,
814 ft_history.data_am_errors, ft_history.data_crc_errors,
815 ft_history.overrun_errors, ft_history.no_data_errors,
816 ft_history.retries);
817 if (ft_history.used & 1) {
818 TRACE(ft_t_info, "ecc statistics:\n"
819 KERN_INFO " crc_errors : %3d\n"
820 KERN_INFO " crc_failures : %3d\n"
821 KERN_INFO " ecc_failures : %3d\n"
822 KERN_INFO " sectors corrected: %3d",
823 ft_history.crc_errors, ft_history.crc_failures,
824 ft_history.ecc_failures, ft_history.corrected);
825 }
826 if (ft_history.defects > 0) {
827 TRACE(ft_t_warn, "Warning: %d media defects!",
828 ft_history.defects);
829 }
830 if (ft_history.rewinds > 0) {
831 TRACE(ft_t_info, "tape motion statistics:\n"
832 KERN_INFO "repositions : %3d",
833 ft_history.rewinds);
834 }
835 }
836 ft_failure = 1;
837 TRACE_EXIT;
838}
839
840static void ftape_init_driver(void)
841{
842 TRACE_FUN(ft_t_flow);
843
844 ft_drive_type.vendor_id = UNKNOWN_VENDOR;
845 ft_drive_type.speed = 0;
846 ft_drive_type.wake_up = unknown_wake_up;
847 ft_drive_type.name = "Unknown";
848
849 ftape_timeout.seek = 650 * FT_SECOND;
850 ftape_timeout.reset = 670 * FT_SECOND;
851 ftape_timeout.rewind = 650 * FT_SECOND;
852 ftape_timeout.head_seek = 15 * FT_SECOND;
853 ftape_timeout.stop = 5 * FT_SECOND;
854 ftape_timeout.pause = 16 * FT_SECOND;
855
856 ft_qic_std = -1;
857 ftape_tape_len = 0; /* unknown */
858 ftape_current_command = 0;
859 ftape_current_cylinder = -1;
860
861 ft_segments_per_track = 102;
862 ftape_segments_per_head = 1020;
863 ftape_segments_per_cylinder = 4;
864 ft_tracks_per_tape = 20;
865
866 ft_failure = 1;
867
868 ft_formatted = 0;
869 ft_no_tape = 1;
870 ft_write_protected = 1;
871 ft_new_tape = 1;
872
873 ft_driver_state = idle;
874
875 ft_data_rate =
876 ft_fdc_max_rate = 500;
877 ft_drive_max_rate = 0; /* triggers set_rate_test() */
878
879 ftape_init_drive_needed = 1;
880
881 ft_header_segment_1 = -1;
882 ft_header_segment_2 = -1;
883 ft_used_header_segment = -1;
884 ft_first_data_segment = -1;
885 ft_last_data_segment = -1;
886
887 ft_location.track = -1;
888 ft_location.known = 0;
889
890 ftape_tape_running = 0;
891 ftape_might_be_off_track = 1;
892
893 ftape_new_cartridge(); /* init some tape related variables */
894 ftape_init_bsm();
895 TRACE_EXIT;
896}
diff --git a/drivers/char/ftape/lowlevel/ftape-ctl.h b/drivers/char/ftape/lowlevel/ftape-ctl.h
deleted file mode 100644
index 5f5e30bc3615..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-ctl.h
+++ /dev/null
@@ -1,162 +0,0 @@
1#ifndef _FTAPE_CTL_H
2#define _FTAPE_CTL_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-ctl.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:09 $
26 *
27 * This file contains the non-standard IOCTL related definitions
28 * for the QIC-40/80/3010/3020 floppy-tape driver "ftape" for
29 * Linux.
30 */
31
32#include <linux/ioctl.h>
33#include <linux/mtio.h>
34#include <linux/ftape-vendors.h>
35
36#include "../lowlevel/ftape-rw.h"
37#include <linux/ftape-header-segment.h>
38
39typedef struct {
40 int used; /* any reading or writing done */
41 /* isr statistics */
42 unsigned int id_am_errors; /* id address mark not found */
43 unsigned int id_crc_errors; /* crc error in id address mark */
44 unsigned int data_am_errors; /* data address mark not found */
45 unsigned int data_crc_errors; /* crc error in data field */
46 unsigned int overrun_errors; /* fdc access timing problem */
47 unsigned int no_data_errors; /* sector not found */
48 unsigned int retries; /* number of tape retries */
49 /* ecc statistics */
50 unsigned int crc_errors; /* crc error in data */
51 unsigned int crc_failures; /* bad data without crc error */
52 unsigned int ecc_failures; /* failed to correct */
53 unsigned int corrected; /* total sectors corrected */
54 /* general statistics */
55 unsigned int rewinds; /* number of tape rewinds */
56 unsigned int defects; /* bad sectors due to media defects */
57} history_record;
58
59/* this structure contains * ALL * information that we want
60 * our child modules to know about, but don't want them to
61 * modify.
62 */
63typedef struct {
64 /* vendor information */
65 vendor_struct fti_drive_type;
66 /* data rates */
67 unsigned int fti_used_data_rate;
68 unsigned int fti_drive_max_rate;
69 unsigned int fti_fdc_max_rate;
70 /* drive selection, either FTAPE_SEL_A/B/C/D */
71 int fti_drive_sel;
72 /* flags set after decode the drive and tape status */
73 unsigned int fti_formatted :1;
74 unsigned int fti_no_tape :1;
75 unsigned int fti_write_protected:1;
76 unsigned int fti_new_tape :1;
77 /* values of last queried drive/tape status and error */
78 ft_drive_error fti_last_error;
79 ft_drive_status fti_last_status;
80 /* cartridge geometry */
81 unsigned int fti_tracks_per_tape;
82 unsigned int fti_segments_per_track;
83 /* location of header segments, etc. */
84 int fti_used_header_segment;
85 int fti_header_segment_1;
86 int fti_header_segment_2;
87 int fti_first_data_segment;
88 int fti_last_data_segment;
89 /* the format code as stored in the header segment */
90 ft_format_type fti_format_code;
91 /* the following is the sole reason for the ftape_set_status() call */
92 unsigned int fti_qic_std;
93 /* is tape running? */
94 volatile enum runner_status_enum fti_runner_status;
95 /* is tape reading/writing/verifying/formatting/deleting */
96 buffer_state_enum fti_state;
97 /* flags fatal hardware error */
98 unsigned int fti_failure:1;
99 /* history record */
100 history_record fti_history;
101} ftape_info;
102
103/* vendor information */
104#define ft_drive_type ftape_status.fti_drive_type
105/* data rates */
106#define ft_data_rate ftape_status.fti_used_data_rate
107#define ft_drive_max_rate ftape_status.fti_drive_max_rate
108#define ft_fdc_max_rate ftape_status.fti_fdc_max_rate
109/* drive selection, either FTAPE_SEL_A/B/C/D */
110#define ft_drive_sel ftape_status.fti_drive_sel
111/* flags set after decode the drive and tape status */
112#define ft_formatted ftape_status.fti_formatted
113#define ft_no_tape ftape_status.fti_no_tape
114#define ft_write_protected ftape_status.fti_write_protected
115#define ft_new_tape ftape_status.fti_new_tape
116/* values of last queried drive/tape status and error */
117#define ft_last_error ftape_status.fti_last_error
118#define ft_last_status ftape_status.fti_last_status
119/* cartridge geometry */
120#define ft_tracks_per_tape ftape_status.fti_tracks_per_tape
121#define ft_segments_per_track ftape_status.fti_segments_per_track
122/* the format code as stored in the header segment */
123#define ft_format_code ftape_status.fti_format_code
124/* the qic status as returned by report drive configuration */
125#define ft_qic_std ftape_status.fti_qic_std
126#define ft_used_header_segment ftape_status.fti_used_header_segment
127#define ft_header_segment_1 ftape_status.fti_header_segment_1
128#define ft_header_segment_2 ftape_status.fti_header_segment_2
129#define ft_first_data_segment ftape_status.fti_first_data_segment
130#define ft_last_data_segment ftape_status.fti_last_data_segment
131/* is tape running? */
132#define ft_runner_status ftape_status.fti_runner_status
133/* is tape reading/writing/verifying/formatting/deleting */
134#define ft_driver_state ftape_status.fti_state
135/* flags fatal hardware error */
136#define ft_failure ftape_status.fti_failure
137/* history record */
138#define ft_history ftape_status.fti_history
139
140/*
141 * ftape-ctl.c defined global vars.
142 */
143extern ftape_info ftape_status;
144extern int ftape_segments_per_head;
145extern int ftape_segments_per_cylinder;
146extern int ftape_init_drive_needed;
147
148/*
149 * ftape-ctl.c defined global functions.
150 */
151extern int ftape_mmap(struct vm_area_struct *vma);
152extern int ftape_enable(int drive_selection);
153extern void ftape_disable(void);
154extern int ftape_seek_to_bot(void);
155extern int ftape_seek_to_eot(void);
156extern int ftape_abort_operation(void);
157extern void ftape_calc_timeouts(unsigned int qic_std,
158 unsigned int data_rate,
159 unsigned int tape_len);
160extern int ftape_calibrate_data_rate(unsigned int qic_std);
161extern const ftape_info *ftape_get_status(void);
162#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-ecc.c b/drivers/char/ftape/lowlevel/ftape-ecc.c
deleted file mode 100644
index e5632f674bc8..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-ecc.c
+++ /dev/null
@@ -1,853 +0,0 @@
1/*
2 *
3 * Copyright (c) 1993 Ning and David Mosberger.
4
5 This is based on code originally written by Bas Laarhoven (bas@vimec.nl)
6 and David L. Brown, Jr., and incorporates improvements suggested by
7 Kai Harrekilde-Petersen.
8
9 This program is free software; you can redistribute it and/or
10 modify it under the terms of the GNU General Public License as
11 published by the Free Software Foundation; either version 2, or (at
12 your option) any later version.
13
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
22 USA.
23
24 *
25 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-ecc.c,v $
26 * $Revision: 1.3 $
27 * $Date: 1997/10/05 19:18:10 $
28 *
29 * This file contains the Reed-Solomon error correction code
30 * for the QIC-40/80 floppy-tape driver for Linux.
31 */
32
33#include <linux/ftape.h>
34
35#include "../lowlevel/ftape-tracing.h"
36#include "../lowlevel/ftape-ecc.h"
37
38/* Machines that are big-endian should define macro BIG_ENDIAN.
39 * Unfortunately, there doesn't appear to be a standard include file
40 * that works for all OSs.
41 */
42
43#if defined(__sparc__) || defined(__hppa)
44#define BIG_ENDIAN
45#endif /* __sparc__ || __hppa */
46
47#if defined(__mips__)
48#error Find a smart way to determine the Endianness of the MIPS CPU
49#endif
50
51/* Notice: to minimize the potential for confusion, we use r to
52 * denote the independent variable of the polynomials in the
53 * Galois Field GF(2^8). We reserve x for polynomials that
54 * that have coefficients in GF(2^8).
55 *
56 * The Galois Field in which coefficient arithmetic is performed are
57 * the polynomials over Z_2 (i.e., 0 and 1) modulo the irreducible
58 * polynomial f(r), where f(r)=r^8 + r^7 + r^2 + r + 1. A polynomial
59 * is represented as a byte with the MSB as the coefficient of r^7 and
60 * the LSB as the coefficient of r^0. For example, the binary
61 * representation of f(x) is 0x187 (of course, this doesn't fit into 8
62 * bits). In this field, the polynomial r is a primitive element.
63 * That is, r^i with i in 0,...,255 enumerates all elements in the
64 * field.
65 *
66 * The generator polynomial for the QIC-80 ECC is
67 *
68 * g(x) = x^3 + r^105*x^2 + r^105*x + 1
69 *
70 * which can be factored into:
71 *
72 * g(x) = (x-r^-1)(x-r^0)(x-r^1)
73 *
74 * the byte representation of the coefficients are:
75 *
76 * r^105 = 0xc0
77 * r^-1 = 0xc3
78 * r^0 = 0x01
79 * r^1 = 0x02
80 *
81 * Notice that r^-1 = r^254 as exponent arithmetic is performed
82 * modulo 2^8-1 = 255.
83 *
84 * For more information on Galois Fields and Reed-Solomon codes, refer
85 * to any good book. I found _An Introduction to Error Correcting
86 * Codes with Applications_ by S. A. Vanstone and P. C. van Oorschot
87 * to be a good introduction into the former. _CODING THEORY: The
88 * Essentials_ I found very useful for its concise description of
89 * Reed-Solomon encoding/decoding.
90 *
91 */
92
93typedef __u8 Matrix[3][3];
94
95/*
96 * gfpow[] is defined such that gfpow[i] returns r^i if
97 * i is in the range [0..255].
98 */
99static const __u8 gfpow[] =
100{
101 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
102 0x87, 0x89, 0x95, 0xad, 0xdd, 0x3d, 0x7a, 0xf4,
103 0x6f, 0xde, 0x3b, 0x76, 0xec, 0x5f, 0xbe, 0xfb,
104 0x71, 0xe2, 0x43, 0x86, 0x8b, 0x91, 0xa5, 0xcd,
105 0x1d, 0x3a, 0x74, 0xe8, 0x57, 0xae, 0xdb, 0x31,
106 0x62, 0xc4, 0x0f, 0x1e, 0x3c, 0x78, 0xf0, 0x67,
107 0xce, 0x1b, 0x36, 0x6c, 0xd8, 0x37, 0x6e, 0xdc,
108 0x3f, 0x7e, 0xfc, 0x7f, 0xfe, 0x7b, 0xf6, 0x6b,
109 0xd6, 0x2b, 0x56, 0xac, 0xdf, 0x39, 0x72, 0xe4,
110 0x4f, 0x9e, 0xbb, 0xf1, 0x65, 0xca, 0x13, 0x26,
111 0x4c, 0x98, 0xb7, 0xe9, 0x55, 0xaa, 0xd3, 0x21,
112 0x42, 0x84, 0x8f, 0x99, 0xb5, 0xed, 0x5d, 0xba,
113 0xf3, 0x61, 0xc2, 0x03, 0x06, 0x0c, 0x18, 0x30,
114 0x60, 0xc0, 0x07, 0x0e, 0x1c, 0x38, 0x70, 0xe0,
115 0x47, 0x8e, 0x9b, 0xb1, 0xe5, 0x4d, 0x9a, 0xb3,
116 0xe1, 0x45, 0x8a, 0x93, 0xa1, 0xc5, 0x0d, 0x1a,
117 0x34, 0x68, 0xd0, 0x27, 0x4e, 0x9c, 0xbf, 0xf9,
118 0x75, 0xea, 0x53, 0xa6, 0xcb, 0x11, 0x22, 0x44,
119 0x88, 0x97, 0xa9, 0xd5, 0x2d, 0x5a, 0xb4, 0xef,
120 0x59, 0xb2, 0xe3, 0x41, 0x82, 0x83, 0x81, 0x85,
121 0x8d, 0x9d, 0xbd, 0xfd, 0x7d, 0xfa, 0x73, 0xe6,
122 0x4b, 0x96, 0xab, 0xd1, 0x25, 0x4a, 0x94, 0xaf,
123 0xd9, 0x35, 0x6a, 0xd4, 0x2f, 0x5e, 0xbc, 0xff,
124 0x79, 0xf2, 0x63, 0xc6, 0x0b, 0x16, 0x2c, 0x58,
125 0xb0, 0xe7, 0x49, 0x92, 0xa3, 0xc1, 0x05, 0x0a,
126 0x14, 0x28, 0x50, 0xa0, 0xc7, 0x09, 0x12, 0x24,
127 0x48, 0x90, 0xa7, 0xc9, 0x15, 0x2a, 0x54, 0xa8,
128 0xd7, 0x29, 0x52, 0xa4, 0xcf, 0x19, 0x32, 0x64,
129 0xc8, 0x17, 0x2e, 0x5c, 0xb8, 0xf7, 0x69, 0xd2,
130 0x23, 0x46, 0x8c, 0x9f, 0xb9, 0xf5, 0x6d, 0xda,
131 0x33, 0x66, 0xcc, 0x1f, 0x3e, 0x7c, 0xf8, 0x77,
132 0xee, 0x5b, 0xb6, 0xeb, 0x51, 0xa2, 0xc3, 0x01
133};
134
135/*
136 * This is a log table. That is, gflog[r^i] returns i (modulo f(r)).
137 * gflog[0] is undefined and the first element is therefore not valid.
138 */
139static const __u8 gflog[256] =
140{
141 0xff, 0x00, 0x01, 0x63, 0x02, 0xc6, 0x64, 0x6a,
142 0x03, 0xcd, 0xc7, 0xbc, 0x65, 0x7e, 0x6b, 0x2a,
143 0x04, 0x8d, 0xce, 0x4e, 0xc8, 0xd4, 0xbd, 0xe1,
144 0x66, 0xdd, 0x7f, 0x31, 0x6c, 0x20, 0x2b, 0xf3,
145 0x05, 0x57, 0x8e, 0xe8, 0xcf, 0xac, 0x4f, 0x83,
146 0xc9, 0xd9, 0xd5, 0x41, 0xbe, 0x94, 0xe2, 0xb4,
147 0x67, 0x27, 0xde, 0xf0, 0x80, 0xb1, 0x32, 0x35,
148 0x6d, 0x45, 0x21, 0x12, 0x2c, 0x0d, 0xf4, 0x38,
149 0x06, 0x9b, 0x58, 0x1a, 0x8f, 0x79, 0xe9, 0x70,
150 0xd0, 0xc2, 0xad, 0xa8, 0x50, 0x75, 0x84, 0x48,
151 0xca, 0xfc, 0xda, 0x8a, 0xd6, 0x54, 0x42, 0x24,
152 0xbf, 0x98, 0x95, 0xf9, 0xe3, 0x5e, 0xb5, 0x15,
153 0x68, 0x61, 0x28, 0xba, 0xdf, 0x4c, 0xf1, 0x2f,
154 0x81, 0xe6, 0xb2, 0x3f, 0x33, 0xee, 0x36, 0x10,
155 0x6e, 0x18, 0x46, 0xa6, 0x22, 0x88, 0x13, 0xf7,
156 0x2d, 0xb8, 0x0e, 0x3d, 0xf5, 0xa4, 0x39, 0x3b,
157 0x07, 0x9e, 0x9c, 0x9d, 0x59, 0x9f, 0x1b, 0x08,
158 0x90, 0x09, 0x7a, 0x1c, 0xea, 0xa0, 0x71, 0x5a,
159 0xd1, 0x1d, 0xc3, 0x7b, 0xae, 0x0a, 0xa9, 0x91,
160 0x51, 0x5b, 0x76, 0x72, 0x85, 0xa1, 0x49, 0xeb,
161 0xcb, 0x7c, 0xfd, 0xc4, 0xdb, 0x1e, 0x8b, 0xd2,
162 0xd7, 0x92, 0x55, 0xaa, 0x43, 0x0b, 0x25, 0xaf,
163 0xc0, 0x73, 0x99, 0x77, 0x96, 0x5c, 0xfa, 0x52,
164 0xe4, 0xec, 0x5f, 0x4a, 0xb6, 0xa2, 0x16, 0x86,
165 0x69, 0xc5, 0x62, 0xfe, 0x29, 0x7d, 0xbb, 0xcc,
166 0xe0, 0xd3, 0x4d, 0x8c, 0xf2, 0x1f, 0x30, 0xdc,
167 0x82, 0xab, 0xe7, 0x56, 0xb3, 0x93, 0x40, 0xd8,
168 0x34, 0xb0, 0xef, 0x26, 0x37, 0x0c, 0x11, 0x44,
169 0x6f, 0x78, 0x19, 0x9a, 0x47, 0x74, 0xa7, 0xc1,
170 0x23, 0x53, 0x89, 0xfb, 0x14, 0x5d, 0xf8, 0x97,
171 0x2e, 0x4b, 0xb9, 0x60, 0x0f, 0xed, 0x3e, 0xe5,
172 0xf6, 0x87, 0xa5, 0x17, 0x3a, 0xa3, 0x3c, 0xb7
173};
174
175/* This is a multiplication table for the factor 0xc0 (i.e., r^105 (mod f(r)).
176 * gfmul_c0[f] returns r^105 * f(r) (modulo f(r)).
177 */
178static const __u8 gfmul_c0[256] =
179{
180 0x00, 0xc0, 0x07, 0xc7, 0x0e, 0xce, 0x09, 0xc9,
181 0x1c, 0xdc, 0x1b, 0xdb, 0x12, 0xd2, 0x15, 0xd5,
182 0x38, 0xf8, 0x3f, 0xff, 0x36, 0xf6, 0x31, 0xf1,
183 0x24, 0xe4, 0x23, 0xe3, 0x2a, 0xea, 0x2d, 0xed,
184 0x70, 0xb0, 0x77, 0xb7, 0x7e, 0xbe, 0x79, 0xb9,
185 0x6c, 0xac, 0x6b, 0xab, 0x62, 0xa2, 0x65, 0xa5,
186 0x48, 0x88, 0x4f, 0x8f, 0x46, 0x86, 0x41, 0x81,
187 0x54, 0x94, 0x53, 0x93, 0x5a, 0x9a, 0x5d, 0x9d,
188 0xe0, 0x20, 0xe7, 0x27, 0xee, 0x2e, 0xe9, 0x29,
189 0xfc, 0x3c, 0xfb, 0x3b, 0xf2, 0x32, 0xf5, 0x35,
190 0xd8, 0x18, 0xdf, 0x1f, 0xd6, 0x16, 0xd1, 0x11,
191 0xc4, 0x04, 0xc3, 0x03, 0xca, 0x0a, 0xcd, 0x0d,
192 0x90, 0x50, 0x97, 0x57, 0x9e, 0x5e, 0x99, 0x59,
193 0x8c, 0x4c, 0x8b, 0x4b, 0x82, 0x42, 0x85, 0x45,
194 0xa8, 0x68, 0xaf, 0x6f, 0xa6, 0x66, 0xa1, 0x61,
195 0xb4, 0x74, 0xb3, 0x73, 0xba, 0x7a, 0xbd, 0x7d,
196 0x47, 0x87, 0x40, 0x80, 0x49, 0x89, 0x4e, 0x8e,
197 0x5b, 0x9b, 0x5c, 0x9c, 0x55, 0x95, 0x52, 0x92,
198 0x7f, 0xbf, 0x78, 0xb8, 0x71, 0xb1, 0x76, 0xb6,
199 0x63, 0xa3, 0x64, 0xa4, 0x6d, 0xad, 0x6a, 0xaa,
200 0x37, 0xf7, 0x30, 0xf0, 0x39, 0xf9, 0x3e, 0xfe,
201 0x2b, 0xeb, 0x2c, 0xec, 0x25, 0xe5, 0x22, 0xe2,
202 0x0f, 0xcf, 0x08, 0xc8, 0x01, 0xc1, 0x06, 0xc6,
203 0x13, 0xd3, 0x14, 0xd4, 0x1d, 0xdd, 0x1a, 0xda,
204 0xa7, 0x67, 0xa0, 0x60, 0xa9, 0x69, 0xae, 0x6e,
205 0xbb, 0x7b, 0xbc, 0x7c, 0xb5, 0x75, 0xb2, 0x72,
206 0x9f, 0x5f, 0x98, 0x58, 0x91, 0x51, 0x96, 0x56,
207 0x83, 0x43, 0x84, 0x44, 0x8d, 0x4d, 0x8a, 0x4a,
208 0xd7, 0x17, 0xd0, 0x10, 0xd9, 0x19, 0xde, 0x1e,
209 0xcb, 0x0b, 0xcc, 0x0c, 0xc5, 0x05, 0xc2, 0x02,
210 0xef, 0x2f, 0xe8, 0x28, 0xe1, 0x21, 0xe6, 0x26,
211 0xf3, 0x33, 0xf4, 0x34, 0xfd, 0x3d, 0xfa, 0x3a
212};
213
214
215/* Returns V modulo 255 provided V is in the range -255,-254,...,509.
216 */
217static inline __u8 mod255(int v)
218{
219 if (v > 0) {
220 if (v < 255) {
221 return v;
222 } else {
223 return v - 255;
224 }
225 } else {
226 return v + 255;
227 }
228}
229
230
231/* Add two numbers in the field. Addition in this field is equivalent
232 * to a bit-wise exclusive OR operation---subtraction is therefore
233 * identical to addition.
234 */
235static inline __u8 gfadd(__u8 a, __u8 b)
236{
237 return a ^ b;
238}
239
240
241/* Add two vectors of numbers in the field. Each byte in A and B gets
242 * added individually.
243 */
244static inline unsigned long gfadd_long(unsigned long a, unsigned long b)
245{
246 return a ^ b;
247}
248
249
250/* Multiply two numbers in the field:
251 */
252static inline __u8 gfmul(__u8 a, __u8 b)
253{
254 if (a && b) {
255 return gfpow[mod255(gflog[a] + gflog[b])];
256 } else {
257 return 0;
258 }
259}
260
261
262/* Just like gfmul, except we have already looked up the log of the
263 * second number.
264 */
265static inline __u8 gfmul_exp(__u8 a, int b)
266{
267 if (a) {
268 return gfpow[mod255(gflog[a] + b)];
269 } else {
270 return 0;
271 }
272}
273
274
275/* Just like gfmul_exp, except that A is a vector of numbers. That
276 * is, each byte in A gets multiplied by gfpow[mod255(B)].
277 */
278static inline unsigned long gfmul_exp_long(unsigned long a, int b)
279{
280 __u8 t;
281
282 if (sizeof(long) == 4) {
283 return (
284 ((t = (__u32)a >> 24 & 0xff) ?
285 (((__u32) gfpow[mod255(gflog[t] + b)]) << 24) : 0) |
286 ((t = (__u32)a >> 16 & 0xff) ?
287 (((__u32) gfpow[mod255(gflog[t] + b)]) << 16) : 0) |
288 ((t = (__u32)a >> 8 & 0xff) ?
289 (((__u32) gfpow[mod255(gflog[t] + b)]) << 8) : 0) |
290 ((t = (__u32)a >> 0 & 0xff) ?
291 (((__u32) gfpow[mod255(gflog[t] + b)]) << 0) : 0));
292 } else if (sizeof(long) == 8) {
293 return (
294 ((t = (__u64)a >> 56 & 0xff) ?
295 (((__u64) gfpow[mod255(gflog[t] + b)]) << 56) : 0) |
296 ((t = (__u64)a >> 48 & 0xff) ?
297 (((__u64) gfpow[mod255(gflog[t] + b)]) << 48) : 0) |
298 ((t = (__u64)a >> 40 & 0xff) ?
299 (((__u64) gfpow[mod255(gflog[t] + b)]) << 40) : 0) |
300 ((t = (__u64)a >> 32 & 0xff) ?
301 (((__u64) gfpow[mod255(gflog[t] + b)]) << 32) : 0) |
302 ((t = (__u64)a >> 24 & 0xff) ?
303 (((__u64) gfpow[mod255(gflog[t] + b)]) << 24) : 0) |
304 ((t = (__u64)a >> 16 & 0xff) ?
305 (((__u64) gfpow[mod255(gflog[t] + b)]) << 16) : 0) |
306 ((t = (__u64)a >> 8 & 0xff) ?
307 (((__u64) gfpow[mod255(gflog[t] + b)]) << 8) : 0) |
308 ((t = (__u64)a >> 0 & 0xff) ?
309 (((__u64) gfpow[mod255(gflog[t] + b)]) << 0) : 0));
310 } else {
311 TRACE_FUN(ft_t_any);
312 TRACE_ABORT(-1, ft_t_err, "Error: size of long is %d bytes",
313 (int)sizeof(long));
314 }
315}
316
317
318/* Divide two numbers in the field. Returns a/b (modulo f(x)).
319 */
320static inline __u8 gfdiv(__u8 a, __u8 b)
321{
322 if (!b) {
323 TRACE_FUN(ft_t_any);
324 TRACE_ABORT(0xff, ft_t_bug, "Error: division by zero");
325 } else if (a == 0) {
326 return 0;
327 } else {
328 return gfpow[mod255(gflog[a] - gflog[b])];
329 }
330}
331
332
333/* The following functions return the inverse of the matrix of the
334 * linear system that needs to be solved to determine the error
335 * magnitudes. The first deals with matrices of rank 3, while the
336 * second deals with matrices of rank 2. The error indices are passed
337 * in arguments L0,..,L2 (0=first sector, 31=last sector). The error
338 * indices must be sorted in ascending order, i.e., L0<L1<L2.
339 *
340 * The linear system that needs to be solved for the error magnitudes
341 * is A * b = s, where s is the known vector of syndromes, b is the
342 * vector of error magnitudes and A in the ORDER=3 case:
343 *
344 * A_3 = {{1/r^L[0], 1/r^L[1], 1/r^L[2]},
345 * { 1, 1, 1},
346 * { r^L[0], r^L[1], r^L[2]}}
347 */
348static inline int gfinv3(__u8 l0,
349 __u8 l1,
350 __u8 l2,
351 Matrix Ainv)
352{
353 __u8 det;
354 __u8 t20, t10, t21, t12, t01, t02;
355 int log_det;
356
357 /* compute some intermediate results: */
358 t20 = gfpow[l2 - l0]; /* t20 = r^l2/r^l0 */
359 t10 = gfpow[l1 - l0]; /* t10 = r^l1/r^l0 */
360 t21 = gfpow[l2 - l1]; /* t21 = r^l2/r^l1 */
361 t12 = gfpow[l1 - l2 + 255]; /* t12 = r^l1/r^l2 */
362 t01 = gfpow[l0 - l1 + 255]; /* t01 = r^l0/r^l1 */
363 t02 = gfpow[l0 - l2 + 255]; /* t02 = r^l0/r^l2 */
364 /* Calculate the determinant of matrix A_3^-1 (sometimes
365 * called the Vandermonde determinant):
366 */
367 det = gfadd(t20, gfadd(t10, gfadd(t21, gfadd(t12, gfadd(t01, t02)))));
368 if (!det) {
369 TRACE_FUN(ft_t_any);
370 TRACE_ABORT(0, ft_t_err,
371 "Inversion failed (3 CRC errors, >0 CRC failures)");
372 }
373 log_det = 255 - gflog[det];
374
375 /* Now, calculate all of the coefficients:
376 */
377 Ainv[0][0]= gfmul_exp(gfadd(gfpow[l1], gfpow[l2]), log_det);
378 Ainv[0][1]= gfmul_exp(gfadd(t21, t12), log_det);
379 Ainv[0][2]= gfmul_exp(gfadd(gfpow[255 - l1], gfpow[255 - l2]),log_det);
380
381 Ainv[1][0]= gfmul_exp(gfadd(gfpow[l0], gfpow[l2]), log_det);
382 Ainv[1][1]= gfmul_exp(gfadd(t20, t02), log_det);
383 Ainv[1][2]= gfmul_exp(gfadd(gfpow[255 - l0], gfpow[255 - l2]),log_det);
384
385 Ainv[2][0]= gfmul_exp(gfadd(gfpow[l0], gfpow[l1]), log_det);
386 Ainv[2][1]= gfmul_exp(gfadd(t10, t01), log_det);
387 Ainv[2][2]= gfmul_exp(gfadd(gfpow[255 - l0], gfpow[255 - l1]),log_det);
388
389 return 1;
390}
391
392
393static inline int gfinv2(__u8 l0, __u8 l1, Matrix Ainv)
394{
395 __u8 det;
396 __u8 t1, t2;
397 int log_det;
398
399 t1 = gfpow[255 - l0];
400 t2 = gfpow[255 - l1];
401 det = gfadd(t1, t2);
402 if (!det) {
403 TRACE_FUN(ft_t_any);
404 TRACE_ABORT(0, ft_t_err,
405 "Inversion failed (2 CRC errors, >0 CRC failures)");
406 }
407 log_det = 255 - gflog[det];
408
409 /* Now, calculate all of the coefficients:
410 */
411 Ainv[0][0] = Ainv[1][0] = gfpow[log_det];
412
413 Ainv[0][1] = gfmul_exp(t2, log_det);
414 Ainv[1][1] = gfmul_exp(t1, log_det);
415
416 return 1;
417}
418
419
420/* Multiply matrix A by vector S and return result in vector B. M is
421 * assumed to be of order NxN, S and B of order Nx1.
422 */
423static inline void gfmat_mul(int n, Matrix A,
424 __u8 *s, __u8 *b)
425{
426 int i, j;
427 __u8 dot_prod;
428
429 for (i = 0; i < n; ++i) {
430 dot_prod = 0;
431 for (j = 0; j < n; ++j) {
432 dot_prod = gfadd(dot_prod, gfmul(A[i][j], s[j]));
433 }
434 b[i] = dot_prod;
435 }
436}
437
438
439
440/* The Reed Solomon ECC codes are computed over the N-th byte of each
441 * block, where N=SECTOR_SIZE. There are up to 29 blocks of data, and
442 * 3 blocks of ECC. The blocks are stored contiguously in memory. A
443 * segment, consequently, is assumed to have at least 4 blocks: one or
444 * more data blocks plus three ECC blocks.
445 *
446 * Notice: In QIC-80 speak, a CRC error is a sector with an incorrect
447 * CRC. A CRC failure is a sector with incorrect data, but
448 * a valid CRC. In the error control literature, the former
449 * is usually called "erasure", the latter "error."
450 */
451/* Compute the parity bytes for C columns of data, where C is the
452 * number of bytes that fit into a long integer. We use a linear
453 * feed-back register to do this. The parity bytes P[0], P[STRIDE],
454 * P[2*STRIDE] are computed such that:
455 *
456 * x^k * p(x) + m(x) = 0 (modulo g(x))
457 *
458 * where k = NBLOCKS,
459 * p(x) = P[0] + P[STRIDE]*x + P[2*STRIDE]*x^2, and
460 * m(x) = sum_{i=0}^k m_i*x^i.
461 * m_i = DATA[i*SECTOR_SIZE]
462 */
463static inline void set_parity(unsigned long *data,
464 int nblocks,
465 unsigned long *p,
466 int stride)
467{
468 unsigned long p0, p1, p2, t1, t2, *end;
469
470 end = data + nblocks * (FT_SECTOR_SIZE / sizeof(long));
471 p0 = p1 = p2 = 0;
472 while (data < end) {
473 /* The new parity bytes p0_i, p1_i, p2_i are computed
474 * from the old values p0_{i-1}, p1_{i-1}, p2_{i-1}
475 * recursively as:
476 *
477 * p0_i = p1_{i-1} + r^105 * (m_{i-1} - p0_{i-1})
478 * p1_i = p2_{i-1} + r^105 * (m_{i-1} - p0_{i-1})
479 * p2_i = (m_{i-1} - p0_{i-1})
480 *
481 * With the initial condition: p0_0 = p1_0 = p2_0 = 0.
482 */
483 t1 = gfadd_long(*data, p0);
484 /*
485 * Multiply each byte in t1 by 0xc0:
486 */
487 if (sizeof(long) == 4) {
488 t2= (((__u32) gfmul_c0[(__u32)t1 >> 24 & 0xff]) << 24 |
489 ((__u32) gfmul_c0[(__u32)t1 >> 16 & 0xff]) << 16 |
490 ((__u32) gfmul_c0[(__u32)t1 >> 8 & 0xff]) << 8 |
491 ((__u32) gfmul_c0[(__u32)t1 >> 0 & 0xff]) << 0);
492 } else if (sizeof(long) == 8) {
493 t2= (((__u64) gfmul_c0[(__u64)t1 >> 56 & 0xff]) << 56 |
494 ((__u64) gfmul_c0[(__u64)t1 >> 48 & 0xff]) << 48 |
495 ((__u64) gfmul_c0[(__u64)t1 >> 40 & 0xff]) << 40 |
496 ((__u64) gfmul_c0[(__u64)t1 >> 32 & 0xff]) << 32 |
497 ((__u64) gfmul_c0[(__u64)t1 >> 24 & 0xff]) << 24 |
498 ((__u64) gfmul_c0[(__u64)t1 >> 16 & 0xff]) << 16 |
499 ((__u64) gfmul_c0[(__u64)t1 >> 8 & 0xff]) << 8 |
500 ((__u64) gfmul_c0[(__u64)t1 >> 0 & 0xff]) << 0);
501 } else {
502 TRACE_FUN(ft_t_any);
503 TRACE(ft_t_err, "Error: long is of size %d",
504 (int) sizeof(long));
505 TRACE_EXIT;
506 }
507 p0 = gfadd_long(t2, p1);
508 p1 = gfadd_long(t2, p2);
509 p2 = t1;
510 data += FT_SECTOR_SIZE / sizeof(long);
511 }
512 *p = p0;
513 p += stride;
514 *p = p1;
515 p += stride;
516 *p = p2;
517 return;
518}
519
520
521/* Compute the 3 syndrome values. DATA should point to the first byte
522 * of the column for which the syndromes are desired. The syndromes
523 * are computed over the first NBLOCKS of rows. The three bytes will
524 * be placed in S[0], S[1], and S[2].
525 *
526 * S[i] is the value of the "message" polynomial m(x) evaluated at the
527 * i-th root of the generator polynomial g(x).
528 *
529 * As g(x)=(x-r^-1)(x-1)(x-r^1) we evaluate the message polynomial at
530 * x=r^-1 to get S[0], at x=r^0=1 to get S[1], and at x=r to get S[2].
531 * This could be done directly and efficiently via the Horner scheme.
532 * However, it would require multiplication tables for the factors
533 * r^-1 (0xc3) and r (0x02). The following scheme does not require
534 * any multiplication tables beyond what's needed for set_parity()
535 * anyway and is slightly faster if there are no errors and slightly
536 * slower if there are errors. The latter is hopefully the infrequent
537 * case.
538 *
539 * To understand the alternative algorithm, notice that set_parity(m,
540 * k, p) computes parity bytes such that:
541 *
542 * x^k * p(x) = m(x) (modulo g(x)).
543 *
544 * That is, to evaluate m(r^m), where r^m is a root of g(x), we can
545 * simply evaluate (r^m)^k*p(r^m). Also, notice that p is 0 if and
546 * only if s is zero. That is, if all parity bytes are 0, we know
547 * there is no error in the data and consequently there is no need to
548 * compute s(x) at all! In all other cases, we compute s(x) from p(x)
549 * by evaluating (r^m)^k*p(r^m) for m=-1, m=0, and m=1. The p(x)
550 * polynomial is evaluated via the Horner scheme.
551 */
552static int compute_syndromes(unsigned long *data, int nblocks, unsigned long *s)
553{
554 unsigned long p[3];
555
556 set_parity(data, nblocks, p, 1);
557 if (p[0] | p[1] | p[2]) {
558 /* Some of the checked columns do not have a zero
559 * syndrome. For simplicity, we compute the syndromes
560 * for all columns that we have computed the
561 * remainders for.
562 */
563 s[0] = gfmul_exp_long(
564 gfadd_long(p[0],
565 gfmul_exp_long(
566 gfadd_long(p[1],
567 gfmul_exp_long(p[2], -1)),
568 -1)),
569 -nblocks);
570 s[1] = gfadd_long(gfadd_long(p[2], p[1]), p[0]);
571 s[2] = gfmul_exp_long(
572 gfadd_long(p[0],
573 gfmul_exp_long(
574 gfadd_long(p[1],
575 gfmul_exp_long(p[2], 1)),
576 1)),
577 nblocks);
578 return 0;
579 } else {
580 return 1;
581 }
582}
583
584
585/* Correct the block in the column pointed to by DATA. There are NBAD
586 * CRC errors and their indices are in BAD_LOC[0], up to
587 * BAD_LOC[NBAD-1]. If NBAD>1, Ainv holds the inverse of the matrix
588 * of the linear system that needs to be solved to determine the error
589 * magnitudes. S[0], S[1], and S[2] are the syndrome values. If row
590 * j gets corrected, then bit j will be set in CORRECTION_MAP.
591 */
592static inline int correct_block(__u8 *data, int nblocks,
593 int nbad, int *bad_loc, Matrix Ainv,
594 __u8 *s,
595 SectorMap * correction_map)
596{
597 int ncorrected = 0;
598 int i;
599 __u8 t1, t2;
600 __u8 c0, c1, c2; /* check bytes */
601 __u8 error_mag[3], log_error_mag;
602 __u8 *dp, l, e;
603 TRACE_FUN(ft_t_any);
604
605 switch (nbad) {
606 case 0:
607 /* might have a CRC failure: */
608 if (s[0] == 0) {
609 /* more than one error */
610 TRACE_ABORT(-1, ft_t_err,
611 "ECC failed (0 CRC errors, >1 CRC failures)");
612 }
613 t1 = gfdiv(s[1], s[0]);
614 if ((bad_loc[nbad++] = gflog[t1]) >= nblocks) {
615 TRACE(ft_t_err,
616 "ECC failed (0 CRC errors, >1 CRC failures)");
617 TRACE_ABORT(-1, ft_t_err,
618 "attempt to correct data at %d", bad_loc[0]);
619 }
620 error_mag[0] = s[1];
621 break;
622 case 1:
623 t1 = gfadd(gfmul_exp(s[1], bad_loc[0]), s[2]);
624 t2 = gfadd(gfmul_exp(s[0], bad_loc[0]), s[1]);
625 if (t1 == 0 && t2 == 0) {
626 /* one erasure, no error: */
627 Ainv[0][0] = gfpow[bad_loc[0]];
628 } else if (t1 == 0 || t2 == 0) {
629 /* one erasure and more than one error: */
630 TRACE_ABORT(-1, ft_t_err,
631 "ECC failed (1 erasure, >1 error)");
632 } else {
633 /* one erasure, one error: */
634 if ((bad_loc[nbad++] = gflog[gfdiv(t1, t2)])
635 >= nblocks) {
636 TRACE(ft_t_err, "ECC failed "
637 "(1 CRC errors, >1 CRC failures)");
638 TRACE_ABORT(-1, ft_t_err,
639 "attempt to correct data at %d",
640 bad_loc[1]);
641 }
642 if (!gfinv2(bad_loc[0], bad_loc[1], Ainv)) {
643 /* inversion failed---must have more
644 * than one error
645 */
646 TRACE_EXIT -1;
647 }
648 }
649 /* FALL THROUGH TO ERROR MAGNITUDE COMPUTATION:
650 */
651 case 2:
652 case 3:
653 /* compute error magnitudes: */
654 gfmat_mul(nbad, Ainv, s, error_mag);
655 break;
656
657 default:
658 TRACE_ABORT(-1, ft_t_err,
659 "Internal Error: number of CRC errors > 3");
660 }
661
662 /* Perform correction by adding ERROR_MAG[i] to the byte at
663 * offset BAD_LOC[i]. Also add the value of the computed
664 * error polynomial to the syndrome values. If the correction
665 * was successful, the resulting check bytes should be zero
666 * (i.e., the corrected data is a valid code word).
667 */
668 c0 = s[0];
669 c1 = s[1];
670 c2 = s[2];
671 for (i = 0; i < nbad; ++i) {
672 e = error_mag[i];
673 if (e) {
674 /* correct the byte at offset L by magnitude E: */
675 l = bad_loc[i];
676 dp = &data[l * FT_SECTOR_SIZE];
677 *dp = gfadd(*dp, e);
678 *correction_map |= 1 << l;
679 ++ncorrected;
680
681 log_error_mag = gflog[e];
682 c0 = gfadd(c0, gfpow[mod255(log_error_mag - l)]);
683 c1 = gfadd(c1, e);
684 c2 = gfadd(c2, gfpow[mod255(log_error_mag + l)]);
685 }
686 }
687 if (c0 || c1 || c2) {
688 TRACE_ABORT(-1, ft_t_err,
689 "ECC self-check failed, too many errors");
690 }
691 TRACE_EXIT ncorrected;
692}
693
694
695#if defined(ECC_SANITY_CHECK) || defined(ECC_PARANOID)
696
697/* Perform a sanity check on the computed parity bytes:
698 */
699static int sanity_check(unsigned long *data, int nblocks)
700{
701 TRACE_FUN(ft_t_any);
702 unsigned long s[3];
703
704 if (!compute_syndromes(data, nblocks, s)) {
705 TRACE_ABORT(0, ft_bug,
706 "Internal Error: syndrome self-check failed");
707 }
708 TRACE_EXIT 1;
709}
710
711#endif /* defined(ECC_SANITY_CHECK) || defined(ECC_PARANOID) */
712
713/* Compute the parity for an entire segment of data.
714 */
715int ftape_ecc_set_segment_parity(struct memory_segment *mseg)
716{
717 int i;
718 __u8 *parity_bytes;
719
720 parity_bytes = &mseg->data[(mseg->blocks - 3) * FT_SECTOR_SIZE];
721 for (i = 0; i < FT_SECTOR_SIZE; i += sizeof(long)) {
722 set_parity((unsigned long *) &mseg->data[i], mseg->blocks - 3,
723 (unsigned long *) &parity_bytes[i],
724 FT_SECTOR_SIZE / sizeof(long));
725#ifdef ECC_PARANOID
726 if (!sanity_check((unsigned long *) &mseg->data[i],
727 mseg->blocks)) {
728 return -1;
729 }
730#endif /* ECC_PARANOID */
731 }
732 return 0;
733}
734
735
736/* Checks and corrects (if possible) the segment MSEG. Returns one of
737 * ECC_OK, ECC_CORRECTED, and ECC_FAILED.
738 */
739int ftape_ecc_correct_data(struct memory_segment *mseg)
740{
741 int col, i, result;
742 int ncorrected = 0;
743 int nerasures = 0; /* # of erasures (CRC errors) */
744 int erasure_loc[3]; /* erasure locations */
745 unsigned long ss[3];
746 __u8 s[3];
747 Matrix Ainv;
748 TRACE_FUN(ft_t_flow);
749
750 mseg->corrected = 0;
751
752 /* find first column that has non-zero syndromes: */
753 for (col = 0; col < FT_SECTOR_SIZE; col += sizeof(long)) {
754 if (!compute_syndromes((unsigned long *) &mseg->data[col],
755 mseg->blocks, ss)) {
756 /* something is wrong---have to fix things */
757 break;
758 }
759 }
760 if (col >= FT_SECTOR_SIZE) {
761 /* all syndromes are ok, therefore nothing to correct */
762 TRACE_EXIT ECC_OK;
763 }
764 /* count the number of CRC errors if there were any: */
765 if (mseg->read_bad) {
766 for (i = 0; i < mseg->blocks; i++) {
767 if (BAD_CHECK(mseg->read_bad, i)) {
768 if (nerasures >= 3) {
769 /* this is too much for ECC */
770 TRACE_ABORT(ECC_FAILED, ft_t_err,
771 "ECC failed (>3 CRC errors)");
772 } /* if */
773 erasure_loc[nerasures++] = i;
774 }
775 }
776 }
777 /*
778 * If there are at least 2 CRC errors, determine inverse of matrix
779 * of linear system to be solved:
780 */
781 switch (nerasures) {
782 case 2:
783 if (!gfinv2(erasure_loc[0], erasure_loc[1], Ainv)) {
784 TRACE_EXIT ECC_FAILED;
785 }
786 break;
787 case 3:
788 if (!gfinv3(erasure_loc[0], erasure_loc[1],
789 erasure_loc[2], Ainv)) {
790 TRACE_EXIT ECC_FAILED;
791 }
792 break;
793 default:
794 /* this is not an error condition... */
795 break;
796 }
797
798 do {
799 for (i = 0; i < sizeof(long); ++i) {
800 s[0] = ss[0];
801 s[1] = ss[1];
802 s[2] = ss[2];
803 if (s[0] | s[1] | s[2]) {
804#ifdef BIG_ENDIAN
805 result = correct_block(
806 &mseg->data[col + sizeof(long) - 1 - i],
807 mseg->blocks,
808 nerasures,
809 erasure_loc,
810 Ainv,
811 s,
812 &mseg->corrected);
813#else
814 result = correct_block(&mseg->data[col + i],
815 mseg->blocks,
816 nerasures,
817 erasure_loc,
818 Ainv,
819 s,
820 &mseg->corrected);
821#endif
822 if (result < 0) {
823 TRACE_EXIT ECC_FAILED;
824 }
825 ncorrected += result;
826 }
827 ss[0] >>= 8;
828 ss[1] >>= 8;
829 ss[2] >>= 8;
830 }
831
832#ifdef ECC_SANITY_CHECK
833 if (!sanity_check((unsigned long *) &mseg->data[col],
834 mseg->blocks)) {
835 TRACE_EXIT ECC_FAILED;
836 }
837#endif /* ECC_SANITY_CHECK */
838
839 /* find next column with non-zero syndromes: */
840 while ((col += sizeof(long)) < FT_SECTOR_SIZE) {
841 if (!compute_syndromes((unsigned long *)
842 &mseg->data[col], mseg->blocks, ss)) {
843 /* something is wrong---have to fix things */
844 break;
845 }
846 }
847 } while (col < FT_SECTOR_SIZE);
848 if (ncorrected && nerasures == 0) {
849 TRACE(ft_t_warn, "block contained error not caught by CRC");
850 }
851 TRACE((ncorrected > 0) ? ft_t_noise : ft_t_any, "number of corrections: %d", ncorrected);
852 TRACE_EXIT ncorrected ? ECC_CORRECTED : ECC_OK;
853}
diff --git a/drivers/char/ftape/lowlevel/ftape-ecc.h b/drivers/char/ftape/lowlevel/ftape-ecc.h
deleted file mode 100644
index 4829146fe9a0..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-ecc.h
+++ /dev/null
@@ -1,84 +0,0 @@
1#ifndef _FTAPE_ECC_H_
2#define _FTAPE_ECC_H_
3
4/*
5 * Copyright (C) 1993 Ning and David Mosberger.
6 * Original:
7 * Copyright (C) 1993 Bas Laarhoven.
8 * Copyright (C) 1992 David L. Brown, Jr.
9
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
14
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
23 USA.
24
25 *
26 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-ecc.h,v $
27 * $Revision: 1.2 $
28 * $Date: 1997/10/05 19:18:11 $
29 *
30 * This file contains the definitions for the
31 * Reed-Solomon error correction code
32 * for the QIC-40/80 tape streamer device driver.
33 */
34
35#include "../lowlevel/ftape-bsm.h"
36
37#define BAD_CLEAR(entry) ((entry)=0)
38#define BAD_SET(entry,sector) ((entry)|=(1<<(sector)))
39#define BAD_CHECK(entry,sector) ((entry)&(1<<(sector)))
40
41/*
42 * Return values for ecc_correct_data:
43 */
44enum {
45 ECC_OK, /* Data was correct. */
46 ECC_CORRECTED, /* Correctable error in data. */
47 ECC_FAILED, /* Could not correct data. */
48};
49
50/*
51 * Representation of an in memory segment. MARKED_BAD lists the
52 * sectors that were marked bad during formatting. If the N-th sector
53 * in a segment is marked bad, bit 1<<N will be set in MARKED_BAD.
54 * The sectors should be read in from the disk and packed, as if the
55 * bad sectors were not there, and the segment just contained fewer
56 * sectors. READ_SECTORS is a bitmap of errors encountered while
57 * reading the data. These offsets are relative to the packed data.
58 * BLOCKS is a count of the sectors not marked bad. This is just to
59 * prevent having to count the zero bits in MARKED_BAD each time this
60 * is needed. DATA is the actual sector packed data from (or to) the
61 * tape.
62 */
63 struct memory_segment {
64 SectorMap marked_bad;
65 SectorMap read_bad;
66 int blocks;
67 __u8 *data;
68 SectorMap corrected;
69 };
70
71/*
72 * ecc.c defined global variables:
73 */
74#ifdef TEST
75extern int ftape_ecc_tracing;
76#endif
77
78/*
79 * ecc.c defined global functions:
80 */
81extern int ftape_ecc_correct_data(struct memory_segment *data);
82extern int ftape_ecc_set_segment_parity(struct memory_segment *data);
83
84#endif /* _FTAPE_ECC_H_ */
diff --git a/drivers/char/ftape/lowlevel/ftape-format.c b/drivers/char/ftape/lowlevel/ftape-format.c
deleted file mode 100644
index 5dd4c59a3f34..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-format.c
+++ /dev/null
@@ -1,344 +0,0 @@
1/*
2 * Copyright (C) 1997 Claus-Justus Heine.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-format.c,v $
20 * $Revision: 1.2.4.1 $
21 * $Date: 1997/11/14 16:05:39 $
22 *
23 * This file contains the code to support formatting of floppy
24 * tape cartridges with the QIC-40/80/3010/3020 floppy-tape
25 * driver "ftape" for Linux.
26 */
27
28#include <linux/string.h>
29#include <linux/errno.h>
30
31#include <linux/ftape.h>
32#include <linux/qic117.h>
33#include "../lowlevel/ftape-tracing.h"
34#include "../lowlevel/ftape-io.h"
35#include "../lowlevel/ftape-ctl.h"
36#include "../lowlevel/ftape-rw.h"
37#include "../lowlevel/ftape-ecc.h"
38#include "../lowlevel/ftape-bsm.h"
39#include "../lowlevel/ftape-format.h"
40
41#if defined(TESTING)
42#define FT_FMT_SEGS_PER_BUF 50
43#else
44#define FT_FMT_SEGS_PER_BUF (FT_BUFF_SIZE/(4*FT_SECTORS_PER_SEGMENT))
45#endif
46
47static spinlock_t ftape_format_lock;
48
49/*
50 * first segment of the new buffer
51 */
52static int switch_segment;
53
54/*
55 * at most 256 segments fit into one 32 kb buffer. Even TR-1 cartridges have
56 * more than this many segments per track, so better be careful.
57 *
58 * buffer_struct *buff: buffer to store the formatting coordinates in
59 * int start: starting segment for this buffer.
60 * int spt: segments per track
61 *
62 * Note: segment ids are relative to the start of the track here.
63 */
64static void setup_format_buffer(buffer_struct *buff, int start, int spt,
65 __u8 gap3)
66{
67 int to_do = spt - start;
68 TRACE_FUN(ft_t_flow);
69
70 if (to_do > FT_FMT_SEGS_PER_BUF) {
71 to_do = FT_FMT_SEGS_PER_BUF;
72 }
73 buff->ptr = buff->address;
74 buff->remaining = to_do * FT_SECTORS_PER_SEGMENT; /* # sectors */
75 buff->bytes = buff->remaining * 4; /* need 4 bytes per sector */
76 buff->gap3 = gap3;
77 buff->segment_id = start;
78 buff->next_segment = start + to_do;
79 if (buff->next_segment >= spt) {
80 buff->next_segment = 0; /* 0 means: stop runner */
81 }
82 buff->status = waiting; /* tells the isr that it can use
83 * this buffer
84 */
85 TRACE_EXIT;
86}
87
88
89/*
90 * start formatting a new track.
91 */
92int ftape_format_track(const unsigned int track, const __u8 gap3)
93{
94 unsigned long flags;
95 buffer_struct *tail, *head;
96 int status;
97 TRACE_FUN(ft_t_flow);
98
99 TRACE_CATCH(ftape_ready_wait(ftape_timeout.pause, &status),);
100 if (track & 1) {
101 if (!(status & QIC_STATUS_AT_EOT)) {
102 TRACE_CATCH(ftape_seek_to_eot(),);
103 }
104 } else {
105 if (!(status & QIC_STATUS_AT_BOT)) {
106 TRACE_CATCH(ftape_seek_to_bot(),);
107 }
108 }
109 ftape_abort_operation(); /* this sets ft_head = ft_tail = 0 */
110 ftape_set_state(formatting);
111
112 TRACE(ft_t_noise,
113 "Formatting track %d, logical: from segment %d to %d",
114 track, track * ft_segments_per_track,
115 (track + 1) * ft_segments_per_track - 1);
116
117 /*
118 * initialize the buffer switching protocol for this track
119 */
120 head = ftape_get_buffer(ft_queue_head); /* tape isn't running yet */
121 tail = ftape_get_buffer(ft_queue_tail); /* tape isn't running yet */
122 switch_segment = 0;
123 do {
124 FT_SIGNAL_EXIT(_DONT_BLOCK);
125 setup_format_buffer(tail, switch_segment,
126 ft_segments_per_track, gap3);
127 switch_segment = tail->next_segment;
128 } while ((switch_segment != 0) &&
129 ((tail = ftape_next_buffer(ft_queue_tail)) != head));
130 /* go */
131 head->status = formatting;
132 TRACE_CATCH(ftape_seek_head_to_track(track),);
133 TRACE_CATCH(ftape_command(QIC_LOGICAL_FORWARD),);
134 spin_lock_irqsave(&ftape_format_lock, flags);
135 TRACE_CATCH(fdc_setup_formatting(head), restore_flags(flags));
136 spin_unlock_irqrestore(&ftape_format_lock, flags);
137 TRACE_EXIT 0;
138}
139
140/* return segment id of segment currently being formatted and do the
141 * buffer switching stuff.
142 */
143int ftape_format_status(unsigned int *segment_id)
144{
145 buffer_struct *tail = ftape_get_buffer(ft_queue_tail);
146 int result;
147 TRACE_FUN(ft_t_flow);
148
149 while (switch_segment != 0 &&
150 ftape_get_buffer(ft_queue_head) != tail) {
151 FT_SIGNAL_EXIT(_DONT_BLOCK);
152 /* need more buffers, first wait for empty buffer
153 */
154 TRACE_CATCH(ftape_wait_segment(formatting),);
155 /* don't worry for gap3. If we ever hit this piece of code,
156 * then all buffer already have the correct gap3 set!
157 */
158 setup_format_buffer(tail, switch_segment,
159 ft_segments_per_track, tail->gap3);
160 switch_segment = tail->next_segment;
161 if (switch_segment != 0) {
162 tail = ftape_next_buffer(ft_queue_tail);
163 }
164 }
165 /* should runner stop ?
166 */
167 if (ft_runner_status == aborting || ft_runner_status == do_abort) {
168 buffer_struct *head = ftape_get_buffer(ft_queue_head);
169 TRACE(ft_t_warn, "Error formatting segment %d",
170 ftape_get_buffer(ft_queue_head)->segment_id);
171 (void)ftape_abort_operation();
172 TRACE_EXIT (head->status != error) ? -EAGAIN : -EIO;
173 }
174 /*
175 * don't care if the timer expires, this is just kind of a
176 * "select" operation that lets the calling process sleep
177 * until something has happened
178 */
179 if (fdc_interrupt_wait(5 * FT_SECOND) < 0) {
180 TRACE(ft_t_noise, "End of track %d at segment %d",
181 ft_location.track,
182 ftape_get_buffer(ft_queue_head)->segment_id);
183 result = 1; /* end of track, unlock module */
184 } else {
185 result = 0;
186 }
187 /*
188 * the calling process should use the seg id to determine
189 * which parts of the dma buffers can be safely overwritten
190 * with new data.
191 */
192 *segment_id = ftape_get_buffer(ft_queue_head)->segment_id;
193 /*
194 * Internally we start counting segment ids from the start of
195 * each track when formatting, but externally we keep them
196 * relative to the start of the tape:
197 */
198 *segment_id += ft_location.track * ft_segments_per_track;
199 TRACE_EXIT result;
200}
201
202/*
203 * The segment id is relative to the start of the tape
204 */
205int ftape_verify_segment(const unsigned int segment_id, SectorMap *bsm)
206{
207 int result;
208 int verify_done = 0;
209 TRACE_FUN(ft_t_flow);
210
211 TRACE(ft_t_noise, "Verifying segment %d", segment_id);
212
213 if (ft_driver_state != verifying) {
214 TRACE(ft_t_noise, "calling ftape_abort_operation");
215 if (ftape_abort_operation() < 0) {
216 TRACE(ft_t_err, "ftape_abort_operation failed");
217 TRACE_EXIT -EIO;
218 }
219 }
220 *bsm = 0x00000000;
221 ftape_set_state(verifying);
222 for (;;) {
223 buffer_struct *tail;
224 /*
225 * Allow escape from this loop on signal
226 */
227 FT_SIGNAL_EXIT(_DONT_BLOCK);
228 /*
229 * Search all full buffers for the first matching the
230 * wanted segment. Clear other buffers on the fly.
231 */
232 tail = ftape_get_buffer(ft_queue_tail);
233 while (!verify_done && tail->status == done) {
234 /*
235 * Allow escape from this loop on signal !
236 */
237 FT_SIGNAL_EXIT(_DONT_BLOCK);
238 if (tail->segment_id == segment_id) {
239 /* If out buffer is already full,
240 * return its contents.
241 */
242 TRACE(ft_t_flow, "found segment in cache: %d",
243 segment_id);
244 if ((tail->soft_error_map |
245 tail->hard_error_map) != 0) {
246 TRACE(ft_t_info,"bsm[%d] = 0x%08lx",
247 segment_id,
248 (unsigned long)
249 (tail->soft_error_map |
250 tail->hard_error_map));
251 *bsm = (tail->soft_error_map |
252 tail->hard_error_map);
253 }
254 verify_done = 1;
255 } else {
256 TRACE(ft_t_flow,"zapping segment in cache: %d",
257 tail->segment_id);
258 }
259 tail->status = waiting;
260 tail = ftape_next_buffer(ft_queue_tail);
261 }
262 if (!verify_done && tail->status == verifying) {
263 if (tail->segment_id == segment_id) {
264 switch(ftape_wait_segment(verifying)) {
265 case 0:
266 break;
267 case -EINTR:
268 TRACE_ABORT(-EINTR, ft_t_warn,
269 "interrupted by "
270 "non-blockable signal");
271 break;
272 default:
273 ftape_abort_operation();
274 ftape_set_state(verifying);
275 /* be picky */
276 TRACE_ABORT(-EIO, ft_t_warn,
277 "wait_segment failed");
278 }
279 } else {
280 /* We're reading the wrong segment,
281 * stop runner.
282 */
283 TRACE(ft_t_noise, "verifying wrong segment");
284 ftape_abort_operation();
285 ftape_set_state(verifying);
286 }
287 }
288 /* should runner stop ?
289 */
290 if (ft_runner_status == aborting) {
291 buffer_struct *head = ftape_get_buffer(ft_queue_head);
292 if (head->status == error ||
293 head->status == verifying) {
294 /* no data or overrun error */
295 head->status = waiting;
296 }
297 TRACE_CATCH(ftape_dumb_stop(),);
298 } else {
299 /* If just passed last segment on tape: wait
300 * for BOT or EOT mark. Sets ft_runner_status to
301 * idle if at lEOT and successful
302 */
303 TRACE_CATCH(ftape_handle_logical_eot(),);
304 }
305 if (verify_done) {
306 TRACE_EXIT 0;
307 }
308 /* Now at least one buffer is idle!
309 * Restart runner & tape if needed.
310 */
311 /* We could optimize the following a little bit. We know that
312 * the bad sector map is empty.
313 */
314 tail = ftape_get_buffer(ft_queue_tail);
315 if (tail->status == waiting) {
316 buffer_struct *head = ftape_get_buffer(ft_queue_head);
317
318 ftape_setup_new_segment(head, segment_id, -1);
319 ftape_calc_next_cluster(head);
320 if (ft_runner_status == idle) {
321 result = ftape_start_tape(segment_id,
322 head->sector_offset);
323 switch(result) {
324 case 0:
325 break;
326 case -ETIME:
327 case -EINTR:
328 TRACE_ABORT(result, ft_t_err, "Error: "
329 "segment %d unreachable",
330 segment_id);
331 break;
332 default:
333 *bsm = EMPTY_SEGMENT;
334 TRACE_EXIT 0;
335 break;
336 }
337 }
338 head->status = verifying;
339 fdc_setup_read_write(head, FDC_VERIFY);
340 }
341 }
342 /* not reached */
343 TRACE_EXIT -EIO;
344}
diff --git a/drivers/char/ftape/lowlevel/ftape-format.h b/drivers/char/ftape/lowlevel/ftape-format.h
deleted file mode 100644
index f15161566643..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-format.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef _FTAPE_FORMAT_H
2#define _FTAPE_FORMAT_H
3
4/*
5 * Copyright (C) 1996-1997 Claus-Justus Heine.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-format.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:18:13 $
25 *
26 * This file contains the low level definitions for the
27 * formatting support for the QIC-40/80/3010/3020 floppy-tape
28 * driver "ftape" for Linux.
29 */
30
31#ifdef __KERNEL__
32extern int ftape_format_track(const unsigned int track, const __u8 gap3);
33extern int ftape_format_status(unsigned int *segment_id);
34extern int ftape_verify_segment(const unsigned int segment_id, SectorMap *bsm);
35#endif /* __KERNEL__ */
36
37#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-init.c b/drivers/char/ftape/lowlevel/ftape-init.c
deleted file mode 100644
index 4998132a81d1..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-init.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * This file contains the code that interfaces the kernel
21 * for the QIC-40/80/3010/3020 floppy-tape driver for Linux.
22 */
23
24#include <linux/module.h>
25#include <linux/errno.h>
26#include <linux/fs.h>
27#include <linux/kernel.h>
28#include <linux/signal.h>
29#include <linux/major.h>
30
31#include <linux/ftape.h>
32#include <linux/init.h>
33#include <linux/qic117.h>
34#ifdef CONFIG_ZFTAPE
35#include <linux/zftape.h>
36#endif
37
38#include "../lowlevel/ftape-init.h"
39#include "../lowlevel/ftape-io.h"
40#include "../lowlevel/ftape-read.h"
41#include "../lowlevel/ftape-write.h"
42#include "../lowlevel/ftape-ctl.h"
43#include "../lowlevel/ftape-rw.h"
44#include "../lowlevel/fdc-io.h"
45#include "../lowlevel/ftape-buffer.h"
46#include "../lowlevel/ftape-proc.h"
47#include "../lowlevel/ftape-tracing.h"
48
49
50#if defined(MODULE) && !defined(CONFIG_FT_NO_TRACE_AT_ALL)
51static int ft_tracing = -1;
52#endif
53
54
55/* Called by modules package when installing the driver
56 * or by kernel during the initialization phase
57 */
58static int __init ftape_init(void)
59{
60 TRACE_FUN(ft_t_flow);
61
62#ifdef MODULE
63#ifndef CONFIG_FT_NO_TRACE_AT_ALL
64 if (ft_tracing != -1) {
65 ftape_tracing = ft_tracing;
66 }
67#endif
68 printk(KERN_INFO FTAPE_VERSION "\n");
69 if (TRACE_LEVEL >= ft_t_info) {
70 printk(
71KERN_INFO "(c) 1993-1996 Bas Laarhoven (bas@vimec.nl)\n"
72KERN_INFO "(c) 1995-1996 Kai Harrekilde-Petersen (khp@dolphinics.no)\n"
73KERN_INFO "(c) 1996-1997 Claus-Justus Heine (claus@momo.math.rwth-aachen.de)\n"
74KERN_INFO "QIC-117 driver for QIC-40/80/3010/3020 floppy tape drives\n");
75 }
76#else /* !MODULE */
77 /* print a short no-nonsense boot message */
78 printk(KERN_INFO FTAPE_VERSION "\n");
79#endif /* MODULE */
80 TRACE(ft_t_info, "installing QIC-117 floppy tape hardware drive ... ");
81 TRACE(ft_t_info, "ftape_init @ 0x%p", ftape_init);
82 /* Allocate the DMA buffers. They are deallocated at cleanup() time.
83 */
84#ifdef TESTING
85#ifdef MODULE
86 while (ftape_set_nr_buffers(CONFIG_FT_NR_BUFFERS) < 0) {
87 ftape_sleep(FT_SECOND/20);
88 if (signal_pending(current)) {
89 (void)ftape_set_nr_buffers(0);
90 TRACE(ft_t_bug,
91 "Killed by signal while allocating buffers.");
92 TRACE_ABORT(-EINTR,
93 ft_t_bug, "Free up memory and retry");
94 }
95 }
96#else
97 TRACE_CATCH(ftape_set_nr_buffers(CONFIG_FT_NR_BUFFERS),
98 (void)ftape_set_nr_buffers(0));
99#endif
100#else
101 TRACE_CATCH(ftape_set_nr_buffers(CONFIG_FT_NR_BUFFERS),
102 (void)ftape_set_nr_buffers(0));
103#endif
104 ft_drive_sel = -1;
105 ft_failure = 1; /* inhibit any operation but open */
106 ftape_udelay_calibrate(); /* must be before fdc_wait_calibrate ! */
107 fdc_wait_calibrate();
108#if defined(CONFIG_PROC_FS) && defined(CONFIG_FT_PROC_FS)
109 (void)ftape_proc_init();
110#endif
111#ifdef CONFIG_ZFTAPE
112 (void)zft_init();
113#endif
114 TRACE_EXIT 0;
115}
116
117module_param(ft_fdc_base, uint, 0);
118MODULE_PARM_DESC(ft_fdc_base, "Base address of FDC controller.");
119module_param(ft_fdc_irq, uint, 0);
120MODULE_PARM_DESC(ft_fdc_irq, "IRQ (interrupt channel) to use.");
121module_param(ft_fdc_dma, uint, 0);
122MODULE_PARM_DESC(ft_fdc_dma, "DMA channel to use.");
123module_param(ft_fdc_threshold, uint, 0);
124MODULE_PARM_DESC(ft_fdc_threshold, "Threshold of the FDC Fifo.");
125module_param(ft_fdc_rate_limit, uint, 0);
126MODULE_PARM_DESC(ft_fdc_rate_limit, "Maximal data rate for FDC.");
127module_param(ft_probe_fc10, bool, 0);
128MODULE_PARM_DESC(ft_probe_fc10,
129 "If non-zero, probe for a Colorado FC-10/FC-20 controller.");
130module_param(ft_mach2, bool, 0);
131MODULE_PARM_DESC(ft_mach2,
132 "If non-zero, probe for a Mountain MACH-2 controller.");
133#if defined(MODULE) && !defined(CONFIG_FT_NO_TRACE_AT_ALL)
134module_param(ft_tracing, int, 0644);
135MODULE_PARM_DESC(ft_tracing,
136 "Amount of debugging output, 0 <= tracing <= 8, default 3.");
137#endif
138
139MODULE_AUTHOR(
140 "(c) 1993-1996 Bas Laarhoven (bas@vimec.nl), "
141 "(c) 1995-1996 Kai Harrekilde-Petersen (khp@dolphinics.no), "
142 "(c) 1996, 1997 Claus-Justus Heine (claus@momo.math.rwth-aachen.de)");
143MODULE_DESCRIPTION(
144 "QIC-117 driver for QIC-40/80/3010/3020 floppy tape drives.");
145MODULE_LICENSE("GPL");
146
147static void __exit ftape_exit(void)
148{
149 TRACE_FUN(ft_t_flow);
150
151#if defined(CONFIG_PROC_FS) && defined(CONFIG_FT_PROC_FS)
152 ftape_proc_destroy();
153#endif
154 (void)ftape_set_nr_buffers(0);
155 printk(KERN_INFO "ftape: unloaded.\n");
156 TRACE_EXIT;
157}
158
159module_init(ftape_init);
160module_exit(ftape_exit);
diff --git a/drivers/char/ftape/lowlevel/ftape-init.h b/drivers/char/ftape/lowlevel/ftape-init.h
deleted file mode 100644
index 99a7b8ab086f..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-init.h
+++ /dev/null
@@ -1,43 +0,0 @@
1#ifndef _FTAPE_INIT_H
2#define _FTAPE_INIT_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-init.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:16 $
26 *
27 * This file contains the definitions for the interface to
28 * the Linux kernel for floppy tape driver ftape.
29 *
30 */
31
32#include <linux/linkage.h>
33#include <linux/signal.h>
34
35#define _NEVER_BLOCK (sigmask(SIGKILL) | sigmask(SIGSTOP))
36#define _DONT_BLOCK (_NEVER_BLOCK | sigmask(SIGINT))
37#define _DO_BLOCK (sigmask(SIGPIPE))
38
39#ifndef QIC117_TAPE_MAJOR
40#define QIC117_TAPE_MAJOR 27
41#endif
42
43#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-io.c b/drivers/char/ftape/lowlevel/ftape-io.c
deleted file mode 100644
index 259015aeff55..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-io.c
+++ /dev/null
@@ -1,992 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * (C) 1996 Kai Harrekilde-Petersen,
4 * (C) 1997 Claus-Justus Heine.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 *
21 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-io.c,v $
22 * $Revision: 1.4 $
23 * $Date: 1997/11/11 14:02:36 $
24 *
25 * This file contains the general control functions for the
26 * QIC-40/80/3010/3020 floppy-tape driver "ftape" for Linux.
27 */
28
29#include <linux/errno.h>
30#include <linux/sched.h>
31#include <linux/mm.h>
32#include <asm/system.h>
33#include <linux/ioctl.h>
34#include <linux/mtio.h>
35#include <linux/delay.h>
36
37#include <linux/ftape.h>
38#include <linux/qic117.h>
39#include "../lowlevel/ftape-tracing.h"
40#include "../lowlevel/fdc-io.h"
41#include "../lowlevel/ftape-io.h"
42#include "../lowlevel/ftape-ctl.h"
43#include "../lowlevel/ftape-rw.h"
44#include "../lowlevel/ftape-write.h"
45#include "../lowlevel/ftape-read.h"
46#include "../lowlevel/ftape-init.h"
47#include "../lowlevel/ftape-calibr.h"
48
49/* Global vars.
50 */
51/* NOTE: sectors start numbering at 1, all others at 0 ! */
52ft_timeout_table ftape_timeout;
53unsigned int ftape_tape_len;
54volatile qic117_cmd_t ftape_current_command;
55const struct qic117_command_table qic117_cmds[] = QIC117_COMMANDS;
56int ftape_might_be_off_track;
57
58/* Local vars.
59 */
60static int diagnostic_mode;
61static unsigned int ftape_udelay_count;
62static unsigned int ftape_udelay_time;
63
64void ftape_udelay(unsigned int usecs)
65{
66 volatile int count = (ftape_udelay_count * usecs +
67 ftape_udelay_count - 1) / ftape_udelay_time;
68 volatile int i;
69
70 while (count-- > 0) {
71 for (i = 0; i < 20; ++i);
72 }
73}
74
75void ftape_udelay_calibrate(void)
76{
77 ftape_calibrate("ftape_udelay",
78 ftape_udelay, &ftape_udelay_count, &ftape_udelay_time);
79}
80
81/* Delay (msec) routine.
82 */
83void ftape_sleep(unsigned int time)
84{
85 TRACE_FUN(ft_t_any);
86
87 time *= 1000; /* msecs -> usecs */
88 if (time < FT_USPT) {
89 /* Time too small for scheduler, do a busy wait ! */
90 ftape_udelay(time);
91 } else {
92 long timeout;
93 unsigned long flags;
94 unsigned int ticks = (time + FT_USPT - 1) / FT_USPT;
95
96 TRACE(ft_t_any, "%d msec, %d ticks", time/1000, ticks);
97 timeout = ticks;
98 save_flags(flags);
99 sti();
100 msleep_interruptible(jiffies_to_msecs(timeout));
101 /* Mmm. Isn't current->blocked == 0xffffffff ?
102 */
103 if (signal_pending(current)) {
104 TRACE(ft_t_err, "awoken by non-blocked signal :-(");
105 }
106 restore_flags(flags);
107 }
108 TRACE_EXIT;
109}
110
111/* send a command or parameter to the drive
112 * Generates # of step pulses.
113 */
114static inline int ft_send_to_drive(int arg)
115{
116 /* Always wait for a command_timeout period to separate
117 * individuals commands and/or parameters.
118 */
119 ftape_sleep(3 * FT_MILLISECOND);
120 /* Keep cylinder nr within range, step towards home if possible.
121 */
122 if (ftape_current_cylinder >= arg) {
123 return fdc_seek(ftape_current_cylinder - arg);
124 } else {
125 return fdc_seek(ftape_current_cylinder + arg);
126 }
127}
128
129/* forward */ int ftape_report_raw_drive_status(int *status);
130
131static int ft_check_cmd_restrictions(qic117_cmd_t command)
132{
133 int status = -1;
134 TRACE_FUN(ft_t_any);
135
136 TRACE(ft_t_flow, "%s", qic117_cmds[command].name);
137 /* A new motion command during an uninterruptible (motion)
138 * command requires a ready status before the new command can
139 * be issued. Otherwise a new motion command needs to be
140 * checked against required status.
141 */
142 if (qic117_cmds[command].cmd_type == motion &&
143 qic117_cmds[ftape_current_command].non_intr) {
144 ftape_report_raw_drive_status(&status);
145 if ((status & QIC_STATUS_READY) == 0) {
146 TRACE(ft_t_noise,
147 "motion cmd (%d) during non-intr cmd (%d)",
148 command, ftape_current_command);
149 TRACE(ft_t_noise, "waiting until drive gets ready");
150 ftape_ready_wait(ftape_timeout.seek,
151 &status);
152 }
153 }
154 if (qic117_cmds[command].mask != 0) {
155 __u8 difference;
156 /* Some commands do require a certain status:
157 */
158 if (status == -1) { /* not yet set */
159 ftape_report_raw_drive_status(&status);
160 }
161 difference = ((status ^ qic117_cmds[command].state) &
162 qic117_cmds[command].mask);
163 /* Wait until the drive gets
164 * ready. This may last forever if
165 * the drive never gets ready...
166 */
167 while ((difference & QIC_STATUS_READY) != 0) {
168 TRACE(ft_t_noise, "command %d issued while not ready",
169 command);
170 TRACE(ft_t_noise, "waiting until drive gets ready");
171 if (ftape_ready_wait(ftape_timeout.seek,
172 &status) == -EINTR) {
173 /* Bail out on signal !
174 */
175 TRACE_ABORT(-EINTR, ft_t_warn,
176 "interrupted by non-blockable signal");
177 }
178 difference = ((status ^ qic117_cmds[command].state) &
179 qic117_cmds[command].mask);
180 }
181 while ((difference & QIC_STATUS_ERROR) != 0) {
182 int err;
183 qic117_cmd_t cmd;
184
185 TRACE(ft_t_noise,
186 "command %d issued while error pending",
187 command);
188 TRACE(ft_t_noise, "clearing error status");
189 ftape_report_error(&err, &cmd, 1);
190 ftape_report_raw_drive_status(&status);
191 difference = ((status ^ qic117_cmds[command].state) &
192 qic117_cmds[command].mask);
193 if ((difference & QIC_STATUS_ERROR) != 0) {
194 /* Bail out on fatal signal !
195 */
196 FT_SIGNAL_EXIT(_NEVER_BLOCK);
197 }
198 }
199 if (difference) {
200 /* Any remaining difference can't be solved
201 * here.
202 */
203 if (difference & (QIC_STATUS_CARTRIDGE_PRESENT |
204 QIC_STATUS_NEW_CARTRIDGE |
205 QIC_STATUS_REFERENCED)) {
206 TRACE(ft_t_warn,
207 "Fatal: tape removed or reinserted !");
208 ft_failure = 1;
209 } else {
210 TRACE(ft_t_err, "wrong state: 0x%02x should be: 0x%02x",
211 status & qic117_cmds[command].mask,
212 qic117_cmds[command].state);
213 }
214 TRACE_EXIT -EIO;
215 }
216 if (~status & QIC_STATUS_READY & qic117_cmds[command].mask) {
217 TRACE_ABORT(-EBUSY, ft_t_err, "Bad: still busy!");
218 }
219 }
220 TRACE_EXIT 0;
221}
222
223/* Issue a tape command:
224 */
225int ftape_command(qic117_cmd_t command)
226{
227 int result = 0;
228 static int level;
229 TRACE_FUN(ft_t_any);
230
231 if ((unsigned int)command > NR_ITEMS(qic117_cmds)) {
232 /* This is a bug we'll want to know about too.
233 */
234 TRACE_ABORT(-EIO, ft_t_bug, "bug - bad command: %d", command);
235 }
236 if (++level > 5) { /* This is a bug we'll want to know about. */
237 --level;
238 TRACE_ABORT(-EIO, ft_t_bug, "bug - recursion for command: %d",
239 command);
240 }
241 /* disable logging and restriction check for some commands,
242 * check all other commands that have a prescribed starting
243 * status.
244 */
245 if (diagnostic_mode) {
246 TRACE(ft_t_flow, "diagnostic command %d", command);
247 } else if (command == QIC_REPORT_DRIVE_STATUS ||
248 command == QIC_REPORT_NEXT_BIT) {
249 TRACE(ft_t_any, "%s", qic117_cmds[command].name);
250 } else {
251 TRACE_CATCH(ft_check_cmd_restrictions(command), --level);
252 }
253 /* Now all conditions are met or result was < 0.
254 */
255 result = ft_send_to_drive((unsigned int)command);
256 if (qic117_cmds[command].cmd_type == motion &&
257 command != QIC_LOGICAL_FORWARD && command != QIC_STOP_TAPE) {
258 ft_location.known = 0;
259 }
260 ftape_current_command = command;
261 --level;
262 TRACE_EXIT result;
263}
264
265/* Send a tape command parameter:
266 * Generates command # of step pulses.
267 * Skips tape-status call !
268 */
269int ftape_parameter(unsigned int parameter)
270{
271 TRACE_FUN(ft_t_any);
272
273 TRACE(ft_t_flow, "called with parameter = %d", parameter);
274 TRACE_EXIT ft_send_to_drive(parameter + 2);
275}
276
277/* Wait for the drive to get ready.
278 * timeout time in milli-seconds
279 * Returned status is valid if result != -EIO
280 *
281 * Should we allow to be killed by SIGINT? (^C)
282 * Would be nice at least for large timeouts.
283 */
284int ftape_ready_wait(unsigned int timeout, int *status)
285{
286 unsigned long t0;
287 unsigned int poll_delay;
288 int signal_retries;
289 TRACE_FUN(ft_t_any);
290
291 /* the following ** REALLY ** reduces the system load when
292 * e.g. one simply rewinds or retensions. The tape is slow
293 * anyway. It is really not necessary to detect error
294 * conditions with 1/10 seconds granularity
295 *
296 * On my AMD 133MHZ 486: 100 ms: 23% system load
297 * 1 sec: 5%
298 * 5 sec: 0.6%, yeah
299 */
300 if (timeout <= FT_SECOND) {
301 poll_delay = 100 * FT_MILLISECOND;
302 signal_retries = 20; /* two seconds */
303 } else if (timeout < 20 * FT_SECOND) {
304 TRACE(ft_t_flow, "setting poll delay to 1 second");
305 poll_delay = FT_SECOND;
306 signal_retries = 2; /* two seconds */
307 } else {
308 TRACE(ft_t_flow, "setting poll delay to 5 seconds");
309 poll_delay = 5 * FT_SECOND;
310 signal_retries = 1; /* five seconds */
311 }
312 for (;;) {
313 t0 = jiffies;
314 TRACE_CATCH(ftape_report_raw_drive_status(status),);
315 if (*status & QIC_STATUS_READY) {
316 TRACE_EXIT 0;
317 }
318 if (!signal_retries--) {
319 FT_SIGNAL_EXIT(_NEVER_BLOCK);
320 }
321 if ((int)timeout >= 0) {
322 /* this will fail when jiffies wraps around about
323 * once every year :-)
324 */
325 timeout -= ((jiffies - t0) * FT_SECOND) / HZ;
326 if (timeout <= 0) {
327 TRACE_ABORT(-ETIME, ft_t_err, "timeout");
328 }
329 ftape_sleep(poll_delay);
330 timeout -= poll_delay;
331 } else {
332 ftape_sleep(poll_delay);
333 }
334 }
335 TRACE_EXIT -ETIME;
336}
337
338/* Issue command and wait up to timeout milli seconds for drive ready
339 */
340int ftape_command_wait(qic117_cmd_t command, unsigned int timeout, int *status)
341{
342 int result;
343
344 /* Drive should be ready, issue command
345 */
346 result = ftape_command(command);
347 if (result >= 0) {
348 result = ftape_ready_wait(timeout, status);
349 }
350 return result;
351}
352
353static int ftape_parameter_wait(unsigned int parm, unsigned int timeout, int *status)
354{
355 int result;
356
357 /* Drive should be ready, issue command
358 */
359 result = ftape_parameter(parm);
360 if (result >= 0) {
361 result = ftape_ready_wait(timeout, status);
362 }
363 return result;
364}
365
366/*--------------------------------------------------------------------------
367 * Report operations
368 */
369
370/* Query the drive about its status. The command is sent and
371 result_length bits of status are returned (2 extra bits are read
372 for start and stop). */
373
374int ftape_report_operation(int *status,
375 qic117_cmd_t command,
376 int result_length)
377{
378 int i, st3;
379 unsigned int t0;
380 unsigned int dt;
381 TRACE_FUN(ft_t_any);
382
383 TRACE_CATCH(ftape_command(command),);
384 t0 = ftape_timestamp();
385 i = 0;
386 do {
387 ++i;
388 ftape_sleep(3 * FT_MILLISECOND); /* see remark below */
389 TRACE_CATCH(fdc_sense_drive_status(&st3),);
390 dt = ftape_timediff(t0, ftape_timestamp());
391 /* Ack should be asserted within Ttimout + Tack = 6 msec.
392 * Looks like some drives fail to do this so extend this
393 * period to 300 msec.
394 */
395 } while (!(st3 & ST3_TRACK_0) && dt < 300000);
396 if (!(st3 & ST3_TRACK_0)) {
397 TRACE(ft_t_err,
398 "No acknowledge after %u msec. (%i iter)", dt / 1000, i);
399 TRACE_ABORT(-EIO, ft_t_err, "timeout on Acknowledge");
400 }
401 /* dt may be larger than expected because of other tasks
402 * scheduled while we were sleeping.
403 */
404 if (i > 1 && dt > 6000) {
405 TRACE(ft_t_err, "Acknowledge after %u msec. (%i iter)",
406 dt / 1000, i);
407 }
408 *status = 0;
409 for (i = 0; i < result_length + 1; i++) {
410 TRACE_CATCH(ftape_command(QIC_REPORT_NEXT_BIT),);
411 TRACE_CATCH(fdc_sense_drive_status(&st3),);
412 if (i < result_length) {
413 *status |= ((st3 & ST3_TRACK_0) ? 1 : 0) << i;
414 } else if ((st3 & ST3_TRACK_0) == 0) {
415 TRACE_ABORT(-EIO, ft_t_err, "missing status stop bit");
416 }
417 }
418 /* this command will put track zero and index back into normal state */
419 (void)ftape_command(QIC_REPORT_NEXT_BIT);
420 TRACE_EXIT 0;
421}
422
423/* Report the current drive status. */
424
425int ftape_report_raw_drive_status(int *status)
426{
427 int result;
428 int count = 0;
429 TRACE_FUN(ft_t_any);
430
431 do {
432 result = ftape_report_operation(status,
433 QIC_REPORT_DRIVE_STATUS, 8);
434 } while (result < 0 && ++count <= 3);
435 if (result < 0) {
436 TRACE_ABORT(-EIO, ft_t_err,
437 "report_operation failed after %d trials", count);
438 }
439 if ((*status & 0xff) == 0xff) {
440 TRACE_ABORT(-EIO, ft_t_err,
441 "impossible drive status 0xff");
442 }
443 if (*status & QIC_STATUS_READY) {
444 ftape_current_command = QIC_NO_COMMAND; /* completed */
445 }
446 ft_last_status.status.drive_status = (__u8)(*status & 0xff);
447 TRACE_EXIT 0;
448}
449
450int ftape_report_drive_status(int *status)
451{
452 TRACE_FUN(ft_t_any);
453
454 TRACE_CATCH(ftape_report_raw_drive_status(status),);
455 if (*status & QIC_STATUS_NEW_CARTRIDGE ||
456 !(*status & QIC_STATUS_CARTRIDGE_PRESENT)) {
457 ft_failure = 1; /* will inhibit further operations */
458 TRACE_EXIT -EIO;
459 }
460 if (*status & QIC_STATUS_READY && *status & QIC_STATUS_ERROR) {
461 /* Let caller handle all errors */
462 TRACE_ABORT(1, ft_t_warn, "warning: error status set!");
463 }
464 TRACE_EXIT 0;
465}
466
467int ftape_report_error(unsigned int *error,
468 qic117_cmd_t *command, int report)
469{
470 static const ftape_error ftape_errors[] = QIC117_ERRORS;
471 int code;
472 TRACE_FUN(ft_t_any);
473
474 TRACE_CATCH(ftape_report_operation(&code, QIC_REPORT_ERROR_CODE, 16),);
475 *error = (unsigned int)(code & 0xff);
476 *command = (qic117_cmd_t)((code>>8)&0xff);
477 /* remember hardware status, maybe useful for status ioctls
478 */
479 ft_last_error.error.command = (__u8)*command;
480 ft_last_error.error.error = (__u8)*error;
481 if (!report) {
482 TRACE_EXIT 0;
483 }
484 if (*error == 0) {
485 TRACE_ABORT(0, ft_t_info, "No error");
486 }
487 TRACE(ft_t_info, "errorcode: %d", *error);
488 if (*error < NR_ITEMS(ftape_errors)) {
489 TRACE(ft_t_noise, "%sFatal ERROR:",
490 (ftape_errors[*error].fatal ? "" : "Non-"));
491 TRACE(ft_t_noise, "%s ...", ftape_errors[*error].message);
492 } else {
493 TRACE(ft_t_noise, "Unknown ERROR !");
494 }
495 if ((unsigned int)*command < NR_ITEMS(qic117_cmds) &&
496 qic117_cmds[*command].name != NULL) {
497 TRACE(ft_t_noise, "... caused by command \'%s\'",
498 qic117_cmds[*command].name);
499 } else {
500 TRACE(ft_t_noise, "... caused by unknown command %d",
501 *command);
502 }
503 TRACE_EXIT 0;
504}
505
506int ftape_report_configuration(qic_model *model,
507 unsigned int *rate,
508 int *qic_std,
509 int *tape_len)
510{
511 int result;
512 int config;
513 int status;
514 static const unsigned int qic_rates[ 4] = { 250, 2000, 500, 1000 };
515 TRACE_FUN(ft_t_any);
516
517 result = ftape_report_operation(&config,
518 QIC_REPORT_DRIVE_CONFIGURATION, 8);
519 if (result < 0) {
520 ft_last_status.status.drive_config = (__u8)0x00;
521 *model = prehistoric;
522 *rate = 500;
523 *qic_std = QIC_TAPE_QIC40;
524 *tape_len = 205;
525 TRACE_EXIT 0;
526 } else {
527 ft_last_status.status.drive_config = (__u8)(config & 0xff);
528 }
529 *rate = qic_rates[(config & QIC_CONFIG_RATE_MASK) >> QIC_CONFIG_RATE_SHIFT];
530 result = ftape_report_operation(&status, QIC_REPORT_TAPE_STATUS, 8);
531 if (result < 0) {
532 ft_last_status.status.tape_status = (__u8)0x00;
533 /* pre- QIC117 rev C spec. drive, QIC_CONFIG_80 bit is valid.
534 */
535 *qic_std = (config & QIC_CONFIG_80) ?
536 QIC_TAPE_QIC80 : QIC_TAPE_QIC40;
537 /* ?? how's about 425ft tapes? */
538 *tape_len = (config & QIC_CONFIG_LONG) ? 307 : 0;
539 *model = pre_qic117c;
540 result = 0;
541 } else {
542 ft_last_status.status.tape_status = (__u8)(status & 0xff);
543 *model = post_qic117b;
544 TRACE(ft_t_any, "report tape status result = %02x", status);
545 /* post- QIC117 rev C spec. drive, QIC_CONFIG_80 bit is
546 * invalid.
547 */
548 switch (status & QIC_TAPE_STD_MASK) {
549 case QIC_TAPE_QIC40:
550 case QIC_TAPE_QIC80:
551 case QIC_TAPE_QIC3020:
552 case QIC_TAPE_QIC3010:
553 *qic_std = status & QIC_TAPE_STD_MASK;
554 break;
555 default:
556 *qic_std = -1;
557 break;
558 }
559 switch (status & QIC_TAPE_LEN_MASK) {
560 case QIC_TAPE_205FT:
561 /* 205 or 425+ ft 550 Oe tape */
562 *tape_len = 0;
563 break;
564 case QIC_TAPE_307FT:
565 /* 307.5 ft 550 Oe Extended Length (XL) tape */
566 *tape_len = 307;
567 break;
568 case QIC_TAPE_VARIABLE:
569 /* Variable length 550 Oe tape */
570 *tape_len = 0;
571 break;
572 case QIC_TAPE_1100FT:
573 /* 1100 ft 550 Oe tape */
574 *tape_len = 1100;
575 break;
576 case QIC_TAPE_FLEX:
577 /* Variable length 900 Oe tape */
578 *tape_len = 0;
579 break;
580 default:
581 *tape_len = -1;
582 break;
583 }
584 if (*qic_std == -1 || *tape_len == -1) {
585 TRACE(ft_t_any,
586 "post qic-117b spec drive with unknown tape");
587 }
588 result = *tape_len == -1 ? -EIO : 0;
589 if (status & QIC_TAPE_WIDE) {
590 switch (*qic_std) {
591 case QIC_TAPE_QIC80:
592 TRACE(ft_t_info, "TR-1 tape detected");
593 break;
594 case QIC_TAPE_QIC3010:
595 TRACE(ft_t_info, "TR-2 tape detected");
596 break;
597 case QIC_TAPE_QIC3020:
598 TRACE(ft_t_info, "TR-3 tape detected");
599 break;
600 default:
601 TRACE(ft_t_warn,
602 "Unknown Travan tape type detected");
603 break;
604 }
605 }
606 }
607 TRACE_EXIT (result < 0) ? -EIO : 0;
608}
609
610static int ftape_report_rom_version(int *version)
611{
612
613 if (ftape_report_operation(version, QIC_REPORT_ROM_VERSION, 8) < 0) {
614 return -EIO;
615 } else {
616 return 0;
617 }
618}
619
620void ftape_report_vendor_id(unsigned int *id)
621{
622 int result;
623 TRACE_FUN(ft_t_any);
624
625 /* We'll try to get a vendor id from the drive. First
626 * according to the QIC-117 spec, a 16-bit id is requested.
627 * If that fails we'll try an 8-bit version, otherwise we'll
628 * try an undocumented query.
629 */
630 result = ftape_report_operation((int *) id, QIC_REPORT_VENDOR_ID, 16);
631 if (result < 0) {
632 result = ftape_report_operation((int *) id,
633 QIC_REPORT_VENDOR_ID, 8);
634 if (result < 0) {
635 /* The following is an undocumented call found
636 * in the CMS code.
637 */
638 result = ftape_report_operation((int *) id, 24, 8);
639 if (result < 0) {
640 *id = UNKNOWN_VENDOR;
641 } else {
642 TRACE(ft_t_noise, "got old 8 bit id: %04x",
643 *id);
644 *id |= 0x20000;
645 }
646 } else {
647 TRACE(ft_t_noise, "got 8 bit id: %04x", *id);
648 *id |= 0x10000;
649 }
650 } else {
651 TRACE(ft_t_noise, "got 16 bit id: %04x", *id);
652 }
653 if (*id == 0x0047) {
654 int version;
655 int sign;
656
657 if (ftape_report_rom_version(&version) < 0) {
658 TRACE(ft_t_bug, "report rom version failed");
659 TRACE_EXIT;
660 }
661 TRACE(ft_t_noise, "CMS rom version: %d", version);
662 ftape_command(QIC_ENTER_DIAGNOSTIC_1);
663 ftape_command(QIC_ENTER_DIAGNOSTIC_1);
664 diagnostic_mode = 1;
665 if (ftape_report_operation(&sign, 9, 8) < 0) {
666 unsigned int error;
667 qic117_cmd_t command;
668
669 ftape_report_error(&error, &command, 1);
670 ftape_command(QIC_ENTER_PRIMARY_MODE);
671 diagnostic_mode = 0;
672 TRACE_EXIT; /* failure ! */
673 } else {
674 TRACE(ft_t_noise, "CMS signature: %02x", sign);
675 }
676 if (sign == 0xa5) {
677 result = ftape_report_operation(&sign, 37, 8);
678 if (result < 0) {
679 if (version >= 63) {
680 *id = 0x8880;
681 TRACE(ft_t_noise,
682 "This is an Iomega drive !");
683 } else {
684 *id = 0x0047;
685 TRACE(ft_t_noise,
686 "This is a real CMS drive !");
687 }
688 } else {
689 *id = 0x0047;
690 TRACE(ft_t_noise, "CMS status: %d", sign);
691 }
692 } else {
693 *id = UNKNOWN_VENDOR;
694 }
695 ftape_command(QIC_ENTER_PRIMARY_MODE);
696 diagnostic_mode = 0;
697 }
698 TRACE_EXIT;
699}
700
701static int qic_rate_code(unsigned int rate)
702{
703 switch (rate) {
704 case 250:
705 return QIC_CONFIG_RATE_250;
706 case 500:
707 return QIC_CONFIG_RATE_500;
708 case 1000:
709 return QIC_CONFIG_RATE_1000;
710 case 2000:
711 return QIC_CONFIG_RATE_2000;
712 default:
713 return QIC_CONFIG_RATE_500;
714 }
715}
716
717static int ftape_set_rate_test(unsigned int *max_rate)
718{
719 unsigned int error;
720 qic117_cmd_t command;
721 int status;
722 int supported = 0;
723 TRACE_FUN(ft_t_any);
724
725 /* Check if the drive does support the select rate command
726 * by testing all different settings. If any one is accepted
727 * we assume the command is supported, else not.
728 */
729 for (*max_rate = 2000; *max_rate >= 250; *max_rate /= 2) {
730 if (ftape_command(QIC_SELECT_RATE) < 0) {
731 continue;
732 }
733 if (ftape_parameter_wait(qic_rate_code(*max_rate),
734 1 * FT_SECOND, &status) < 0) {
735 continue;
736 }
737 if (status & QIC_STATUS_ERROR) {
738 ftape_report_error(&error, &command, 0);
739 continue;
740 }
741 supported = 1; /* did accept a request */
742 break;
743 }
744 TRACE(ft_t_noise, "Select Rate command is%s supported",
745 supported ? "" : " not");
746 TRACE_EXIT supported;
747}
748
749int ftape_set_data_rate(unsigned int new_rate /* Kbps */, unsigned int qic_std)
750{
751 int status;
752 int result = 0;
753 unsigned int data_rate = new_rate;
754 static int supported;
755 int rate_changed = 0;
756 qic_model dummy_model;
757 unsigned int dummy_qic_std, dummy_tape_len;
758 TRACE_FUN(ft_t_any);
759
760 if (ft_drive_max_rate == 0) { /* first time */
761 supported = ftape_set_rate_test(&ft_drive_max_rate);
762 }
763 if (supported) {
764 ftape_command(QIC_SELECT_RATE);
765 result = ftape_parameter_wait(qic_rate_code(new_rate),
766 1 * FT_SECOND, &status);
767 if (result >= 0 && !(status & QIC_STATUS_ERROR)) {
768 rate_changed = 1;
769 }
770 }
771 TRACE_CATCH(result = ftape_report_configuration(&dummy_model,
772 &data_rate,
773 &dummy_qic_std,
774 &dummy_tape_len),);
775 if (data_rate != new_rate) {
776 if (!supported) {
777 TRACE(ft_t_warn, "Rate change not supported!");
778 } else if (rate_changed) {
779 TRACE(ft_t_warn, "Requested: %d, got %d",
780 new_rate, data_rate);
781 } else {
782 TRACE(ft_t_warn, "Rate change failed!");
783 }
784 result = -EINVAL;
785 }
786 /*
787 * Set data rate and write precompensation as specified:
788 *
789 * | QIC-40/80 | QIC-3010/3020
790 * rate | precomp | precomp
791 * ----------+-------------+--------------
792 * 250 Kbps. | 250 ns. | 0 ns.
793 * 500 Kbps. | 125 ns. | 0 ns.
794 * 1 Mbps. | 42 ns. | 0 ns.
795 * 2 Mbps | N/A | 0 ns.
796 */
797 if ((qic_std == QIC_TAPE_QIC40 && data_rate > 500) ||
798 (qic_std == QIC_TAPE_QIC80 && data_rate > 1000)) {
799 TRACE_ABORT(-EINVAL,
800 ft_t_warn, "Datarate too high for QIC-mode");
801 }
802 TRACE_CATCH(fdc_set_data_rate(data_rate),_res = -EINVAL);
803 ft_data_rate = data_rate;
804 if (qic_std == QIC_TAPE_QIC40 || qic_std == QIC_TAPE_QIC80) {
805 switch (data_rate) {
806 case 250:
807 fdc_set_write_precomp(250);
808 break;
809 default:
810 case 500:
811 fdc_set_write_precomp(125);
812 break;
813 case 1000:
814 fdc_set_write_precomp(42);
815 break;
816 }
817 } else {
818 fdc_set_write_precomp(0);
819 }
820 TRACE_EXIT result;
821}
822
823/* The next two functions are used to cope with excessive overrun errors
824 */
825int ftape_increase_threshold(void)
826{
827 TRACE_FUN(ft_t_flow);
828
829 if (fdc.type < i82077 || ft_fdc_threshold >= 12) {
830 TRACE_ABORT(-EIO, ft_t_err, "cannot increase fifo threshold");
831 }
832 if (fdc_fifo_threshold(++ft_fdc_threshold, NULL, NULL, NULL) < 0) {
833 TRACE(ft_t_err, "cannot increase fifo threshold");
834 ft_fdc_threshold --;
835 fdc_reset();
836 }
837 TRACE(ft_t_info, "New FIFO threshold: %d", ft_fdc_threshold);
838 TRACE_EXIT 0;
839}
840
841int ftape_half_data_rate(void)
842{
843 if (ft_data_rate < 500) {
844 return -1;
845 }
846 if (ftape_set_data_rate(ft_data_rate / 2, ft_qic_std) < 0) {
847 return -EIO;
848 }
849 ftape_calc_timeouts(ft_qic_std, ft_data_rate, ftape_tape_len);
850 return 0;
851}
852
853/* Seek the head to the specified track.
854 */
855int ftape_seek_head_to_track(unsigned int track)
856{
857 int status;
858 TRACE_FUN(ft_t_any);
859
860 ft_location.track = -1; /* remains set in case of error */
861 if (track >= ft_tracks_per_tape) {
862 TRACE_ABORT(-EINVAL, ft_t_bug, "track out of bounds");
863 }
864 TRACE(ft_t_flow, "seeking track %d", track);
865 TRACE_CATCH(ftape_command(QIC_SEEK_HEAD_TO_TRACK),);
866 TRACE_CATCH(ftape_parameter_wait(track, ftape_timeout.head_seek,
867 &status),);
868 ft_location.track = track;
869 ftape_might_be_off_track = 0;
870 TRACE_EXIT 0;
871}
872
873int ftape_wakeup_drive(wake_up_types method)
874{
875 int status;
876 int motor_on = 0;
877 TRACE_FUN(ft_t_any);
878
879 switch (method) {
880 case wake_up_colorado:
881 TRACE_CATCH(ftape_command(QIC_PHANTOM_SELECT),);
882 TRACE_CATCH(ftape_parameter(0 /* ft_drive_sel ?? */),);
883 break;
884 case wake_up_mountain:
885 TRACE_CATCH(ftape_command(QIC_SOFT_SELECT),);
886 ftape_sleep(FT_MILLISECOND); /* NEEDED */
887 TRACE_CATCH(ftape_parameter(18),);
888 break;
889 case wake_up_insight:
890 ftape_sleep(100 * FT_MILLISECOND);
891 motor_on = 1;
892 fdc_motor(motor_on); /* enable is done by motor-on */
893 case no_wake_up:
894 break;
895 default:
896 TRACE_EXIT -ENODEV; /* unknown wakeup method */
897 break;
898 }
899 /* If wakeup succeeded we shouldn't get an error here..
900 */
901 TRACE_CATCH(ftape_report_raw_drive_status(&status),
902 if (motor_on) {
903 fdc_motor(0);
904 });
905 TRACE_EXIT 0;
906}
907
908int ftape_put_drive_to_sleep(wake_up_types method)
909{
910 TRACE_FUN(ft_t_any);
911
912 switch (method) {
913 case wake_up_colorado:
914 TRACE_CATCH(ftape_command(QIC_PHANTOM_DESELECT),);
915 break;
916 case wake_up_mountain:
917 TRACE_CATCH(ftape_command(QIC_SOFT_DESELECT),);
918 break;
919 case wake_up_insight:
920 fdc_motor(0); /* enable is done by motor-on */
921 case no_wake_up: /* no wakeup / no sleep ! */
922 break;
923 default:
924 TRACE_EXIT -ENODEV; /* unknown wakeup method */
925 }
926 TRACE_EXIT 0;
927}
928
929int ftape_reset_drive(void)
930{
931 int result = 0;
932 int status;
933 unsigned int err_code;
934 qic117_cmd_t err_command;
935 int i;
936 TRACE_FUN(ft_t_any);
937
938 /* We want to re-establish contact with our drive. Fire a
939 * number of reset commands (single step pulses) and pray for
940 * success.
941 */
942 for (i = 0; i < 2; ++i) {
943 TRACE(ft_t_flow, "Resetting fdc");
944 fdc_reset();
945 ftape_sleep(10 * FT_MILLISECOND);
946 TRACE(ft_t_flow, "Reset command to drive");
947 result = ftape_command(QIC_RESET);
948 if (result == 0) {
949 ftape_sleep(1 * FT_SECOND); /* drive not
950 * accessible
951 * during 1 second
952 */
953 TRACE(ft_t_flow, "Re-selecting drive");
954
955 /* Strange, the QIC-117 specs don't mention
956 * this but the drive gets deselected after a
957 * soft reset ! So we need to enable it
958 * again.
959 */
960 if (ftape_wakeup_drive(ft_drive_type.wake_up) < 0) {
961 TRACE(ft_t_err, "Wakeup failed !");
962 }
963 TRACE(ft_t_flow, "Waiting until drive gets ready");
964 result= ftape_ready_wait(ftape_timeout.reset, &status);
965 if (result == 0 && (status & QIC_STATUS_ERROR)) {
966 result = ftape_report_error(&err_code,
967 &err_command, 1);
968 if (result == 0 && err_code == 27) {
969 /* Okay, drive saw reset
970 * command and responded as it
971 * should
972 */
973 break;
974 } else {
975 result = -EIO;
976 }
977 } else {
978 result = -EIO;
979 }
980 }
981 FT_SIGNAL_EXIT(_DONT_BLOCK);
982 }
983 if (result != 0) {
984 TRACE(ft_t_err, "General failure to reset tape drive");
985 } else {
986 /* Restore correct settings: keep original rate
987 */
988 ftape_set_data_rate(ft_data_rate, ft_qic_std);
989 }
990 ftape_init_drive_needed = 1;
991 TRACE_EXIT result;
992}
diff --git a/drivers/char/ftape/lowlevel/ftape-io.h b/drivers/char/ftape/lowlevel/ftape-io.h
deleted file mode 100644
index 26a7baad8717..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-io.h
+++ /dev/null
@@ -1,90 +0,0 @@
1#ifndef _FTAPE_IO_H
2#define _FTAPE_IO_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven,
6 * (C) 1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-io.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:18 $
26 *
27 * This file contains definitions for the glue part of the
28 * QIC-40/80/3010/3020 floppy-tape driver "ftape" for Linux.
29 */
30
31#include <linux/qic117.h>
32#include <linux/ftape-vendors.h>
33
34typedef struct {
35 unsigned int seek;
36 unsigned int reset;
37 unsigned int rewind;
38 unsigned int head_seek;
39 unsigned int stop;
40 unsigned int pause;
41} ft_timeout_table;
42
43typedef enum {
44 prehistoric, pre_qic117c, post_qic117b, post_qic117d
45} qic_model;
46
47/*
48 * ftape-io.c defined global vars.
49 */
50extern ft_timeout_table ftape_timeout;
51extern unsigned int ftape_tape_len;
52extern volatile qic117_cmd_t ftape_current_command;
53extern const struct qic117_command_table qic117_cmds[];
54extern int ftape_might_be_off_track;
55
56/*
57 * ftape-io.c defined global functions.
58 */
59extern void ftape_udelay(unsigned int usecs);
60extern void ftape_udelay_calibrate(void);
61extern void ftape_sleep(unsigned int time);
62extern void ftape_report_vendor_id(unsigned int *id);
63extern int ftape_command(qic117_cmd_t command);
64extern int ftape_command_wait(qic117_cmd_t command,
65 unsigned int timeout,
66 int *status);
67extern int ftape_parameter(unsigned int parameter);
68extern int ftape_report_operation(int *status,
69 qic117_cmd_t command,
70 int result_length);
71extern int ftape_report_configuration(qic_model *model,
72 unsigned int *rate,
73 int *qic_std,
74 int *tape_len);
75extern int ftape_report_drive_status(int *status);
76extern int ftape_report_raw_drive_status(int *status);
77extern int ftape_report_status(int *status);
78extern int ftape_ready_wait(unsigned int timeout, int *status);
79extern int ftape_seek_head_to_track(unsigned int track);
80extern int ftape_set_data_rate(unsigned int new_rate, unsigned int qic_std);
81extern int ftape_report_error(unsigned int *error,
82 qic117_cmd_t *command,
83 int report);
84extern int ftape_reset_drive(void);
85extern int ftape_put_drive_to_sleep(wake_up_types method);
86extern int ftape_wakeup_drive(wake_up_types method);
87extern int ftape_increase_threshold(void);
88extern int ftape_half_data_rate(void);
89
90#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-proc.c b/drivers/char/ftape/lowlevel/ftape-proc.c
deleted file mode 100644
index e805b15e0a12..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-proc.c
+++ /dev/null
@@ -1,214 +0,0 @@
1/*
2 * Copyright (C) 1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-proc.c,v $
20 * $Revision: 1.11 $
21 * $Date: 1997/10/24 14:47:37 $
22 *
23 * This file contains the procfs interface for the
24 * QIC-40/80/3010/3020 floppy-tape driver "ftape" for Linux.
25
26 * Old code removed, switched to dynamic proc entry.
27 */
28
29
30#if defined(CONFIG_PROC_FS) && defined(CONFIG_FT_PROC_FS)
31
32#include <linux/proc_fs.h>
33
34#include <linux/ftape.h>
35#include <linux/init.h>
36#include <linux/qic117.h>
37
38#include "../lowlevel/ftape-io.h"
39#include "../lowlevel/ftape-ctl.h"
40#include "../lowlevel/ftape-proc.h"
41#include "../lowlevel/ftape-tracing.h"
42
43static size_t get_driver_info(char *buf)
44{
45 const char *debug_level[] = { "bugs" ,
46 "errors",
47 "warnings",
48 "informational",
49 "noisy",
50 "program flow",
51 "fdc and dma",
52 "data flow",
53 "anything" };
54
55 return sprintf(buf,
56 "version : %s\n"
57 "used data rate: %d kbit/sec\n"
58 "dma memory : %d kb\n"
59 "debug messages: %s\n",
60 FTAPE_VERSION,
61 ft_data_rate,
62 FT_BUFF_SIZE * ft_nr_buffers >> 10,
63 debug_level[TRACE_LEVEL]);
64}
65
66static size_t get_tapedrive_info(char *buf)
67{
68 return sprintf(buf,
69 "vendor id : 0x%04x\n"
70 "drive name: %s\n"
71 "wind speed: %d ips\n"
72 "wakeup : %s\n"
73 "max. rate : %d kbit/sec\n",
74 ft_drive_type.vendor_id,
75 ft_drive_type.name,
76 ft_drive_type.speed,
77 ((ft_drive_type.wake_up == no_wake_up)
78 ? "No wakeup needed" :
79 ((ft_drive_type.wake_up == wake_up_colorado)
80 ? "Colorado" :
81 ((ft_drive_type.wake_up == wake_up_mountain)
82 ? "Mountain" :
83 ((ft_drive_type.wake_up == wake_up_insight)
84 ? "Motor on" :
85 "Unknown")))),
86 ft_drive_max_rate);
87}
88
89static size_t get_cartridge_info(char *buf)
90{
91 if (ftape_init_drive_needed) {
92 return sprintf(buf, "uninitialized\n");
93 }
94 if (ft_no_tape) {
95 return sprintf(buf, "no cartridge inserted\n");
96 }
97 return sprintf(buf,
98 "segments : %5d\n"
99 "tracks : %5d\n"
100 "length : %5dft\n"
101 "formatted : %3s\n"
102 "writable : %3s\n"
103 "QIC spec. : QIC-%s\n"
104 "fmt-code : %1d\n",
105 ft_segments_per_track,
106 ft_tracks_per_tape,
107 ftape_tape_len,
108 (ft_formatted == 1) ? "yes" : "no",
109 (ft_write_protected == 1) ? "no" : "yes",
110 ((ft_qic_std == QIC_TAPE_QIC40) ? "40" :
111 ((ft_qic_std == QIC_TAPE_QIC80) ? "80" :
112 ((ft_qic_std == QIC_TAPE_QIC3010) ? "3010" :
113 ((ft_qic_std == QIC_TAPE_QIC3020) ? "3020" :
114 "???")))),
115 ft_format_code);
116}
117
118static size_t get_controller_info(char *buf)
119{
120 const char *fdc_name[] = { "no fdc",
121 "i8272",
122 "i82077",
123 "i82077AA",
124 "Colorado FC-10 or FC-20",
125 "i82078",
126 "i82078_1" };
127
128 return sprintf(buf,
129 "FDC type : %s\n"
130 "FDC base : 0x%03x\n"
131 "FDC irq : %d\n"
132 "FDC dma : %d\n"
133 "FDC thr. : %d\n"
134 "max. rate : %d kbit/sec\n",
135 ft_mach2 ? "Mountain MACH-2" : fdc_name[fdc.type],
136 fdc.sra, fdc.irq, fdc.dma,
137 ft_fdc_threshold, ft_fdc_max_rate);
138}
139
140static size_t get_history_info(char *buf)
141{
142 size_t len;
143
144 len = sprintf(buf,
145 "\nFDC isr statistics\n"
146 " id_am_errors : %3d\n"
147 " id_crc_errors : %3d\n"
148 " data_am_errors : %3d\n"
149 " data_crc_errors : %3d\n"
150 " overrun_errors : %3d\n"
151 " no_data_errors : %3d\n"
152 " retries : %3d\n",
153 ft_history.id_am_errors, ft_history.id_crc_errors,
154 ft_history.data_am_errors, ft_history.data_crc_errors,
155 ft_history.overrun_errors, ft_history.no_data_errors,
156 ft_history.retries);
157 len += sprintf(buf + len,
158 "\nECC statistics\n"
159 " crc_errors : %3d\n"
160 " crc_failures : %3d\n"
161 " ecc_failures : %3d\n"
162 " sectors corrected: %3d\n",
163 ft_history.crc_errors, ft_history.crc_failures,
164 ft_history.ecc_failures, ft_history.corrected);
165 len += sprintf(buf + len,
166 "\ntape quality statistics\n"
167 " media defects : %3d\n",
168 ft_history.defects);
169 len += sprintf(buf + len,
170 "\ntape motion statistics\n"
171 " repositions : %3d\n",
172 ft_history.rewinds);
173 return len;
174}
175
176static int ftape_read_proc(char *page, char **start, off_t off,
177 int count, int *eof, void *data)
178{
179 char *ptr = page;
180 size_t len;
181
182 ptr += sprintf(ptr, "Kernel Driver\n\n");
183 ptr += get_driver_info(ptr);
184 ptr += sprintf(ptr, "\nTape Drive\n\n");
185 ptr += get_tapedrive_info(ptr);
186 ptr += sprintf(ptr, "\nFDC Controller\n\n");
187 ptr += get_controller_info(ptr);
188 ptr += sprintf(ptr, "\nTape Cartridge\n\n");
189 ptr += get_cartridge_info(ptr);
190 ptr += sprintf(ptr, "\nHistory Record\n\n");
191 ptr += get_history_info(ptr);
192
193 len = strlen(page);
194 *start = NULL;
195 if (off+count >= len) {
196 *eof = 1;
197 } else {
198 *eof = 0;
199 }
200 return len;
201}
202
203int __init ftape_proc_init(void)
204{
205 return create_proc_read_entry("ftape", 0, &proc_root,
206 ftape_read_proc, NULL) != NULL;
207}
208
209void ftape_proc_destroy(void)
210{
211 remove_proc_entry("ftape", &proc_root);
212}
213
214#endif /* defined(CONFIG_PROC_FS) && defined(CONFIG_FT_PROC_FS) */
diff --git a/drivers/char/ftape/lowlevel/ftape-proc.h b/drivers/char/ftape/lowlevel/ftape-proc.h
deleted file mode 100644
index 264dfcc1d22d..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-proc.h
+++ /dev/null
@@ -1,35 +0,0 @@
1#ifndef _FTAPE_PROC_H
2#define _FTAPE_PROC_H
3
4/*
5 * Copyright (C) 1997 Claus-Justus Heine
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-proc.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:18:20 $
25 *
26 * This file contains definitions for the procfs interface of the
27 * QIC-40/80/3010/3020 floppy-tape driver "ftape" for Linux.
28 */
29
30#include <linux/proc_fs.h>
31
32extern int ftape_proc_init(void);
33extern void ftape_proc_destroy(void);
34
35#endif
diff --git a/drivers/char/ftape/lowlevel/ftape-read.c b/drivers/char/ftape/lowlevel/ftape-read.c
deleted file mode 100644
index d967d8cd86dc..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-read.c
+++ /dev/null
@@ -1,621 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-read.c,v $
21 * $Revision: 1.6 $
22 * $Date: 1997/10/21 14:39:22 $
23 *
24 * This file contains the reading code
25 * for the QIC-117 floppy-tape driver for Linux.
26 *
27 */
28
29#include <linux/string.h>
30#include <linux/errno.h>
31#include <linux/mm.h>
32
33#include <linux/ftape.h>
34#include <linux/qic117.h>
35#include "../lowlevel/ftape-tracing.h"
36#include "../lowlevel/ftape-read.h"
37#include "../lowlevel/ftape-io.h"
38#include "../lowlevel/ftape-ctl.h"
39#include "../lowlevel/ftape-rw.h"
40#include "../lowlevel/ftape-write.h"
41#include "../lowlevel/ftape-ecc.h"
42#include "../lowlevel/ftape-bsm.h"
43
44/* Global vars.
45 */
46
47/* Local vars.
48 */
49
50void ftape_zap_read_buffers(void)
51{
52 int i;
53
54 for (i = 0; i < ft_nr_buffers; ++i) {
55/* changed to "fit" with dynamic allocation of tape_buffer. --khp */
56 ft_buffer[i]->status = waiting;
57 ft_buffer[i]->bytes = 0;
58 ft_buffer[i]->skip = 0;
59 ft_buffer[i]->retry = 0;
60 }
61/* ftape_reset_buffer(); */
62}
63
64static SectorMap convert_sector_map(buffer_struct * buff)
65{
66 int i = 0;
67 SectorMap bad_map = ftape_get_bad_sector_entry(buff->segment_id);
68 SectorMap src_map = buff->soft_error_map | buff->hard_error_map;
69 SectorMap dst_map = 0;
70 TRACE_FUN(ft_t_any);
71
72 if (bad_map || src_map) {
73 TRACE(ft_t_flow, "bad_map = 0x%08lx", (long) bad_map);
74 TRACE(ft_t_flow, "src_map = 0x%08lx", (long) src_map);
75 }
76 while (bad_map) {
77 while ((bad_map & 1) == 0) {
78 if (src_map & 1) {
79 dst_map |= (1 << i);
80 }
81 src_map >>= 1;
82 bad_map >>= 1;
83 ++i;
84 }
85 /* (bad_map & 1) == 1 */
86 src_map >>= 1;
87 bad_map >>= 1;
88 }
89 if (src_map) {
90 dst_map |= (src_map << i);
91 }
92 if (dst_map) {
93 TRACE(ft_t_flow, "dst_map = 0x%08lx", (long) dst_map);
94 }
95 TRACE_EXIT dst_map;
96}
97
98static int correct_and_copy_fraction(buffer_struct *buff, __u8 * destination,
99 int start, int size)
100{
101 struct memory_segment mseg;
102 int result;
103 SectorMap read_bad;
104 TRACE_FUN(ft_t_any);
105
106 mseg.read_bad = convert_sector_map(buff);
107 mseg.marked_bad = 0; /* not used... */
108 mseg.blocks = buff->bytes / FT_SECTOR_SIZE;
109 mseg.data = buff->address;
110 /* If there are no data sectors we can skip this segment.
111 */
112 if (mseg.blocks <= 3) {
113 TRACE_ABORT(0, ft_t_noise, "empty segment");
114 }
115 read_bad = mseg.read_bad;
116 ft_history.crc_errors += count_ones(read_bad);
117 result = ftape_ecc_correct_data(&mseg);
118 if (read_bad != 0 || mseg.corrected != 0) {
119 TRACE(ft_t_noise, "crc error map: 0x%08lx", (unsigned long)read_bad);
120 TRACE(ft_t_noise, "corrected map: 0x%08lx", (unsigned long)mseg.corrected);
121 ft_history.corrected += count_ones(mseg.corrected);
122 }
123 if (result == ECC_CORRECTED || result == ECC_OK) {
124 if (result == ECC_CORRECTED) {
125 TRACE(ft_t_info, "ecc corrected segment: %d", buff->segment_id);
126 }
127 if(start < 0) {
128 start= 0;
129 }
130 if((start+size) > ((mseg.blocks - 3) * FT_SECTOR_SIZE)) {
131 size = (mseg.blocks - 3) * FT_SECTOR_SIZE - start;
132 }
133 if (size < 0) {
134 size= 0;
135 }
136 if(size > 0) {
137 memcpy(destination + start, mseg.data + start, size);
138 }
139 if ((read_bad ^ mseg.corrected) & mseg.corrected) {
140 /* sectors corrected without crc errors set */
141 ft_history.crc_failures++;
142 }
143 TRACE_EXIT size; /* (mseg.blocks - 3) * FT_SECTOR_SIZE; */
144 } else {
145 ft_history.ecc_failures++;
146 TRACE_ABORT(-EAGAIN,
147 ft_t_err, "ecc failure on segment %d",
148 buff->segment_id);
149 }
150 TRACE_EXIT 0;
151}
152
153/* Read given segment into buffer at address.
154 */
155int ftape_read_segment_fraction(const int segment_id,
156 void *address,
157 const ft_read_mode_t read_mode,
158 const int start,
159 const int size)
160{
161 int result = 0;
162 int retry = 0;
163 int bytes_read = 0;
164 int read_done = 0;
165 TRACE_FUN(ft_t_flow);
166
167 ft_history.used |= 1;
168 TRACE(ft_t_data_flow, "segment_id = %d", segment_id);
169 if (ft_driver_state != reading) {
170 TRACE(ft_t_noise, "calling ftape_abort_operation");
171 TRACE_CATCH(ftape_abort_operation(),);
172 ftape_set_state(reading);
173 }
174 for(;;) {
175 buffer_struct *tail;
176 /* Allow escape from this loop on signal !
177 */
178 FT_SIGNAL_EXIT(_DONT_BLOCK);
179 /* Search all full buffers for the first matching the
180 * wanted segment. Clear other buffers on the fly.
181 */
182 tail = ftape_get_buffer(ft_queue_tail);
183 while (!read_done && tail->status == done) {
184 /* Allow escape from this loop on signal !
185 */
186 FT_SIGNAL_EXIT(_DONT_BLOCK);
187 if (tail->segment_id == segment_id) {
188 /* If out buffer is already full,
189 * return its contents.
190 */
191 TRACE(ft_t_flow, "found segment in cache: %d",
192 segment_id);
193 if (tail->deleted) {
194 /* Return a value that
195 * read_header_segment
196 * understands. As this
197 * should only occur when
198 * searching for the header
199 * segments it shouldn't be
200 * misinterpreted elsewhere.
201 */
202 TRACE_EXIT 0;
203 }
204 result = correct_and_copy_fraction(
205 tail,
206 address,
207 start,
208 size);
209 TRACE(ft_t_flow, "segment contains (bytes): %d",
210 result);
211 if (result < 0) {
212 if (result != -EAGAIN) {
213 TRACE_EXIT result;
214 }
215 /* keep read_done == 0, will
216 * trigger
217 * ftape_abort_operation
218 * because reading wrong
219 * segment.
220 */
221 TRACE(ft_t_err, "ecc failed, retry");
222 ++retry;
223 } else {
224 read_done = 1;
225 bytes_read = result;
226 }
227 } else {
228 TRACE(ft_t_flow,"zapping segment in cache: %d",
229 tail->segment_id);
230 }
231 tail->status = waiting;
232 tail = ftape_next_buffer(ft_queue_tail);
233 }
234 if (!read_done && tail->status == reading) {
235 if (tail->segment_id == segment_id) {
236 switch(ftape_wait_segment(reading)) {
237 case 0:
238 break;
239 case -EINTR:
240 TRACE_ABORT(-EINTR, ft_t_warn,
241 "interrupted by "
242 "non-blockable signal");
243 break;
244 default:
245 TRACE(ft_t_noise,
246 "wait_segment failed");
247 ftape_abort_operation();
248 ftape_set_state(reading);
249 break;
250 }
251 } else {
252 /* We're reading the wrong segment,
253 * stop runner.
254 */
255 TRACE(ft_t_noise, "reading wrong segment");
256 ftape_abort_operation();
257 ftape_set_state(reading);
258 }
259 }
260 /* should runner stop ?
261 */
262 if (ft_runner_status == aborting) {
263 buffer_struct *head = ftape_get_buffer(ft_queue_head);
264 switch(head->status) {
265 case error:
266 ft_history.defects +=
267 count_ones(head->hard_error_map);
268 case reading:
269 head->status = waiting;
270 break;
271 default:
272 break;
273 }
274 TRACE_CATCH(ftape_dumb_stop(),);
275 } else {
276 /* If just passed last segment on tape: wait
277 * for BOT or EOT mark. Sets ft_runner_status to
278 * idle if at lEOT and successful
279 */
280 TRACE_CATCH(ftape_handle_logical_eot(),);
281 }
282 /* If we got a segment: quit, or else retry up to limit.
283 *
284 * If segment to read is empty, do not start runner for it,
285 * but wait for next read call.
286 */
287 if (read_done ||
288 ftape_get_bad_sector_entry(segment_id) == EMPTY_SEGMENT ) {
289 /* bytes_read = 0; should still be zero */
290 TRACE_EXIT bytes_read;
291
292 }
293 if (retry > FT_RETRIES_ON_ECC_ERROR) {
294 ft_history.defects++;
295 TRACE_ABORT(-ENODATA, ft_t_err,
296 "too many retries on ecc failure");
297 }
298 /* Now at least one buffer is empty !
299 * Restart runner & tape if needed.
300 */
301 TRACE(ft_t_any, "head: %d, tail: %d, ft_runner_status: %d",
302 ftape_buffer_id(ft_queue_head),
303 ftape_buffer_id(ft_queue_tail),
304 ft_runner_status);
305 TRACE(ft_t_any, "buffer[].status, [head]: %d, [tail]: %d",
306 ftape_get_buffer(ft_queue_head)->status,
307 ftape_get_buffer(ft_queue_tail)->status);
308 tail = ftape_get_buffer(ft_queue_tail);
309 if (tail->status == waiting) {
310 buffer_struct *head = ftape_get_buffer(ft_queue_head);
311
312 ftape_setup_new_segment(head, segment_id, -1);
313 if (read_mode == FT_RD_SINGLE) {
314 /* disable read-ahead */
315 head->next_segment = 0;
316 }
317 ftape_calc_next_cluster(head);
318 if (ft_runner_status == idle) {
319 result = ftape_start_tape(segment_id,
320 head->sector_offset);
321 if (result < 0) {
322 TRACE_ABORT(result, ft_t_err, "Error: "
323 "segment %d unreachable",
324 segment_id);
325 }
326 }
327 head->status = reading;
328 fdc_setup_read_write(head, FDC_READ);
329 }
330 }
331 /* not reached */
332 TRACE_EXIT -EIO;
333}
334
335int ftape_read_header_segment(__u8 *address)
336{
337 int result;
338 int header_segment;
339 int first_failed = 0;
340 int status;
341 TRACE_FUN(ft_t_flow);
342
343 ft_used_header_segment = -1;
344 TRACE_CATCH(ftape_report_drive_status(&status),);
345 TRACE(ft_t_flow, "reading...");
346 /* We're looking for the first header segment.
347 * A header segment cannot contain bad sectors, therefor at the
348 * tape start, segments with bad sectors are (according to QIC-40/80)
349 * written with deleted data marks and must be skipped.
350 */
351 memset(address, '\0', (FT_SECTORS_PER_SEGMENT - 3) * FT_SECTOR_SIZE);
352 result = 0;
353#define HEADER_SEGMENT_BOUNDARY 68 /* why not 42? */
354 for (header_segment = 0;
355 header_segment < HEADER_SEGMENT_BOUNDARY && result == 0;
356 ++header_segment) {
357 /* Set no read-ahead, the isr will force read-ahead whenever
358 * it encounters deleted data !
359 */
360 result = ftape_read_segment(header_segment,
361 address,
362 FT_RD_SINGLE);
363 if (result < 0 && !first_failed) {
364 TRACE(ft_t_err, "header segment damaged, trying backup");
365 first_failed = 1;
366 result = 0; /* force read of next (backup) segment */
367 }
368 }
369 if (result < 0 || header_segment >= HEADER_SEGMENT_BOUNDARY) {
370 TRACE_ABORT(-EIO, ft_t_err,
371 "no readable header segment found");
372 }
373 TRACE_CATCH(ftape_abort_operation(),);
374 ft_used_header_segment = header_segment;
375 result = ftape_decode_header_segment(address);
376 TRACE_EXIT result;
377}
378
379int ftape_decode_header_segment(__u8 *address)
380{
381 unsigned int max_floppy_side;
382 unsigned int max_floppy_track;
383 unsigned int max_floppy_sector;
384 unsigned int new_tape_len;
385 TRACE_FUN(ft_t_flow);
386
387 if (GET4(address, FT_SIGNATURE) == FT_D2G_MAGIC) {
388 /* Ditto 2GB header segment. They encrypt the bad sector map.
389 * We decrypt it and store them in normal format.
390 * I hope this is correct.
391 */
392 int i;
393 TRACE(ft_t_warn,
394 "Found Ditto 2GB tape, "
395 "trying to decrypt bad sector map");
396 for (i=256; i < 29 * FT_SECTOR_SIZE; i++) {
397 address[i] = ~(address[i] - (i&0xff));
398 }
399 PUT4(address, 0,FT_HSEG_MAGIC);
400 } else if (GET4(address, FT_SIGNATURE) != FT_HSEG_MAGIC) {
401 TRACE_ABORT(-EIO, ft_t_err,
402 "wrong signature in header segment");
403 }
404 ft_format_code = (ft_format_type) address[FT_FMT_CODE];
405 if (ft_format_code != fmt_big) {
406 ft_header_segment_1 = GET2(address, FT_HSEG_1);
407 ft_header_segment_2 = GET2(address, FT_HSEG_2);
408 ft_first_data_segment = GET2(address, FT_FRST_SEG);
409 ft_last_data_segment = GET2(address, FT_LAST_SEG);
410 } else {
411 ft_header_segment_1 = GET4(address, FT_6_HSEG_1);
412 ft_header_segment_2 = GET4(address, FT_6_HSEG_2);
413 ft_first_data_segment = GET4(address, FT_6_FRST_SEG);
414 ft_last_data_segment = GET4(address, FT_6_LAST_SEG);
415 }
416 TRACE(ft_t_noise, "first data segment: %d", ft_first_data_segment);
417 TRACE(ft_t_noise, "last data segment: %d", ft_last_data_segment);
418 TRACE(ft_t_noise, "header segments are %d and %d",
419 ft_header_segment_1, ft_header_segment_2);
420
421 /* Verify tape parameters...
422 * QIC-40/80 spec: tape_parameters:
423 *
424 * segments-per-track segments_per_track
425 * tracks-per-cartridge tracks_per_tape
426 * max-floppy-side (segments_per_track *
427 * tracks_per_tape - 1) /
428 * ftape_segments_per_head
429 * max-floppy-track ftape_segments_per_head /
430 * ftape_segments_per_cylinder - 1
431 * max-floppy-sector ftape_segments_per_cylinder *
432 * FT_SECTORS_PER_SEGMENT
433 */
434 ft_segments_per_track = GET2(address, FT_SPT);
435 ft_tracks_per_tape = address[FT_TPC];
436 max_floppy_side = address[FT_FHM];
437 max_floppy_track = address[FT_FTM];
438 max_floppy_sector = address[FT_FSM];
439 TRACE(ft_t_noise, "(fmt/spt/tpc/fhm/ftm/fsm) = %d/%d/%d/%d/%d/%d",
440 ft_format_code, ft_segments_per_track, ft_tracks_per_tape,
441 max_floppy_side, max_floppy_track, max_floppy_sector);
442 new_tape_len = ftape_tape_len;
443 switch (ft_format_code) {
444 case fmt_425ft:
445 new_tape_len = 425;
446 break;
447 case fmt_normal:
448 if (ftape_tape_len == 0) { /* otherwise 307 ft */
449 new_tape_len = 205;
450 }
451 break;
452 case fmt_1100ft:
453 new_tape_len = 1100;
454 break;
455 case fmt_var:{
456 int segments_per_1000_inch = 1; /* non-zero default for switch */
457 switch (ft_qic_std) {
458 case QIC_TAPE_QIC40:
459 segments_per_1000_inch = 332;
460 break;
461 case QIC_TAPE_QIC80:
462 segments_per_1000_inch = 488;
463 break;
464 case QIC_TAPE_QIC3010:
465 segments_per_1000_inch = 730;
466 break;
467 case QIC_TAPE_QIC3020:
468 segments_per_1000_inch = 1430;
469 break;
470 }
471 new_tape_len = (1000 * ft_segments_per_track +
472 (segments_per_1000_inch - 1)) / segments_per_1000_inch;
473 break;
474 }
475 case fmt_big:{
476 int segments_per_1000_inch = 1; /* non-zero default for switch */
477 switch (ft_qic_std) {
478 case QIC_TAPE_QIC40:
479 segments_per_1000_inch = 332;
480 break;
481 case QIC_TAPE_QIC80:
482 segments_per_1000_inch = 488;
483 break;
484 case QIC_TAPE_QIC3010:
485 segments_per_1000_inch = 730;
486 break;
487 case QIC_TAPE_QIC3020:
488 segments_per_1000_inch = 1430;
489 break;
490 default:
491 TRACE_ABORT(-EIO, ft_t_bug,
492 "%x QIC-standard with fmt-code %d, please report",
493 ft_qic_std, ft_format_code);
494 }
495 new_tape_len = ((1000 * ft_segments_per_track +
496 (segments_per_1000_inch - 1)) /
497 segments_per_1000_inch);
498 break;
499 }
500 default:
501 TRACE_ABORT(-EIO, ft_t_err,
502 "unknown tape format, please report !");
503 }
504 if (new_tape_len != ftape_tape_len) {
505 ftape_tape_len = new_tape_len;
506 TRACE(ft_t_info, "calculated tape length is %d ft",
507 ftape_tape_len);
508 ftape_calc_timeouts(ft_qic_std, ft_data_rate, ftape_tape_len);
509 }
510 if (ft_segments_per_track == 0 && ft_tracks_per_tape == 0 &&
511 max_floppy_side == 0 && max_floppy_track == 0 &&
512 max_floppy_sector == 0) {
513 /* QIC-40 Rev E and earlier has no values in the header.
514 */
515 ft_segments_per_track = 68;
516 ft_tracks_per_tape = 20;
517 max_floppy_side = 1;
518 max_floppy_track = 169;
519 max_floppy_sector = 128;
520 }
521 /* This test will compensate for the wrong parameter on tapes
522 * formatted by Conner software.
523 */
524 if (ft_segments_per_track == 150 &&
525 ft_tracks_per_tape == 28 &&
526 max_floppy_side == 7 &&
527 max_floppy_track == 149 &&
528 max_floppy_sector == 128) {
529TRACE(ft_t_info, "the famous CONNER bug: max_floppy_side off by one !");
530 max_floppy_side = 6;
531 }
532 /* These tests will compensate for the wrong parameter on tapes
533 * formatted by ComByte Windows software.
534 *
535 * First, for 205 foot tapes
536 */
537 if (ft_segments_per_track == 100 &&
538 ft_tracks_per_tape == 28 &&
539 max_floppy_side == 9 &&
540 max_floppy_track == 149 &&
541 max_floppy_sector == 128) {
542TRACE(ft_t_info, "the ComByte bug: max_floppy_side incorrect!");
543 max_floppy_side = 4;
544 }
545 /* Next, for 307 foot tapes. */
546 if (ft_segments_per_track == 150 &&
547 ft_tracks_per_tape == 28 &&
548 max_floppy_side == 9 &&
549 max_floppy_track == 149 &&
550 max_floppy_sector == 128) {
551TRACE(ft_t_info, "the ComByte bug: max_floppy_side incorrect!");
552 max_floppy_side = 6;
553 }
554 /* This test will compensate for the wrong parameter on tapes
555 * formatted by Colorado Windows software.
556 */
557 if (ft_segments_per_track == 150 &&
558 ft_tracks_per_tape == 28 &&
559 max_floppy_side == 6 &&
560 max_floppy_track == 150 &&
561 max_floppy_sector == 128) {
562TRACE(ft_t_info, "the famous Colorado bug: max_floppy_track off by one !");
563 max_floppy_track = 149;
564 }
565 ftape_segments_per_head = ((max_floppy_sector/FT_SECTORS_PER_SEGMENT) *
566 (max_floppy_track + 1));
567 /* This test will compensate for some bug reported by Dima
568 * Brodsky. Seems to be a Colorado bug, either. (freebee
569 * Imation tape shipped together with Colorado T3000
570 */
571 if ((ft_format_code == fmt_var || ft_format_code == fmt_big) &&
572 ft_tracks_per_tape == 50 &&
573 max_floppy_side == 54 &&
574 max_floppy_track == 255 &&
575 max_floppy_sector == 128) {
576TRACE(ft_t_info, "the famous ??? bug: max_floppy_track off by one !");
577 max_floppy_track = 254;
578 }
579 /*
580 * Verify drive_configuration with tape parameters
581 */
582 if (ftape_segments_per_head == 0 || ftape_segments_per_cylinder == 0 ||
583 ((ft_segments_per_track * ft_tracks_per_tape - 1) / ftape_segments_per_head
584 != max_floppy_side) ||
585 (ftape_segments_per_head / ftape_segments_per_cylinder - 1 != max_floppy_track) ||
586 (ftape_segments_per_cylinder * FT_SECTORS_PER_SEGMENT != max_floppy_sector)
587#ifdef TESTING
588 || ((ft_format_code == fmt_var || ft_format_code == fmt_big) &&
589 (max_floppy_track != 254 || max_floppy_sector != 128))
590#endif
591 ) {
592 char segperheadz = ftape_segments_per_head ? ' ' : '?';
593 char segpercylz = ftape_segments_per_cylinder ? ' ' : '?';
594 TRACE(ft_t_err,"Tape parameters inconsistency, please report");
595 TRACE(ft_t_err, "reported = %d/%d/%d/%d/%d/%d",
596 ft_format_code,
597 ft_segments_per_track,
598 ft_tracks_per_tape,
599 max_floppy_side,
600 max_floppy_track,
601 max_floppy_sector);
602 TRACE(ft_t_err, "required = %d/%d/%d/%d%c/%d%c/%d",
603 ft_format_code,
604 ft_segments_per_track,
605 ft_tracks_per_tape,
606 ftape_segments_per_head ?
607 ((ft_segments_per_track * ft_tracks_per_tape -1) /
608 ftape_segments_per_head ) :
609 (ft_segments_per_track * ft_tracks_per_tape -1),
610 segperheadz,
611 ftape_segments_per_cylinder ?
612 (ftape_segments_per_head /
613 ftape_segments_per_cylinder - 1 ) :
614 ftape_segments_per_head - 1,
615 segpercylz,
616 (ftape_segments_per_cylinder * FT_SECTORS_PER_SEGMENT));
617 TRACE_EXIT -EIO;
618 }
619 ftape_extract_bad_sector_map(address);
620 TRACE_EXIT 0;
621}
diff --git a/drivers/char/ftape/lowlevel/ftape-read.h b/drivers/char/ftape/lowlevel/ftape-read.h
deleted file mode 100644
index 069f99f2a984..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-read.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _FTAPE_READ_H
2#define _FTAPE_READ_H
3
4/*
5 * Copyright (C) 1994-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-read.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:22 $
26 *
27 * This file contains the definitions for the read functions
28 * for the QIC-117 floppy-tape driver for Linux.
29 *
30 */
31
32/* ftape-read.c defined global functions.
33 */
34typedef enum {
35 FT_RD_SINGLE = 0,
36 FT_RD_AHEAD = 1,
37} ft_read_mode_t;
38
39extern int ftape_read_header_segment(__u8 *address);
40extern int ftape_decode_header_segment(__u8 *address);
41extern int ftape_read_segment_fraction(const int segment,
42 void *address,
43 const ft_read_mode_t read_mode,
44 const int start,
45 const int size);
46#define ftape_read_segment(segment, address, read_mode) \
47 ftape_read_segment_fraction(segment, address, read_mode, \
48 0, FT_SEGMENT_SIZE)
49extern void ftape_zap_read_buffers(void);
50
51#endif /* _FTAPE_READ_H */
diff --git a/drivers/char/ftape/lowlevel/ftape-rw.c b/drivers/char/ftape/lowlevel/ftape-rw.c
deleted file mode 100644
index c0d6dc2cbfd3..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-rw.c
+++ /dev/null
@@ -1,1092 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-rw.c,v $
21 * $Revision: 1.7 $
22 * $Date: 1997/10/28 14:26:49 $
23 *
24 * This file contains some common code for the segment read and
25 * segment write routines for the QIC-117 floppy-tape driver for
26 * Linux.
27 */
28
29#include <linux/string.h>
30#include <linux/errno.h>
31
32#include <linux/ftape.h>
33#include <linux/qic117.h>
34#include "../lowlevel/ftape-tracing.h"
35#include "../lowlevel/ftape-rw.h"
36#include "../lowlevel/fdc-io.h"
37#include "../lowlevel/ftape-init.h"
38#include "../lowlevel/ftape-io.h"
39#include "../lowlevel/ftape-ctl.h"
40#include "../lowlevel/ftape-read.h"
41#include "../lowlevel/ftape-ecc.h"
42#include "../lowlevel/ftape-bsm.h"
43
44/* Global vars.
45 */
46int ft_nr_buffers;
47buffer_struct *ft_buffer[FT_MAX_NR_BUFFERS];
48static volatile int ft_head;
49static volatile int ft_tail; /* not volatile but need same type as head */
50int fdc_setup_error;
51location_record ft_location = {-1, 0};
52volatile int ftape_tape_running;
53
54/* Local vars.
55 */
56static int overrun_count_offset;
57static int inhibit_correction;
58
59/* maxmimal allowed overshoot when fast seeking
60 */
61#define OVERSHOOT_LIMIT 10
62
63/* Increment cyclic buffer nr.
64 */
65buffer_struct *ftape_next_buffer(ft_buffer_queue_t pos)
66{
67 switch (pos) {
68 case ft_queue_head:
69 if (++ft_head >= ft_nr_buffers) {
70 ft_head = 0;
71 }
72 return ft_buffer[ft_head];
73 case ft_queue_tail:
74 if (++ft_tail >= ft_nr_buffers) {
75 ft_tail = 0;
76 }
77 return ft_buffer[ft_tail];
78 default:
79 return NULL;
80 }
81}
82int ftape_buffer_id(ft_buffer_queue_t pos)
83{
84 switch(pos) {
85 case ft_queue_head: return ft_head;
86 case ft_queue_tail: return ft_tail;
87 default: return -1;
88 }
89}
90buffer_struct *ftape_get_buffer(ft_buffer_queue_t pos)
91{
92 switch(pos) {
93 case ft_queue_head: return ft_buffer[ft_head];
94 case ft_queue_tail: return ft_buffer[ft_tail];
95 default: return NULL;
96 }
97}
98void ftape_reset_buffer(void)
99{
100 ft_head = ft_tail = 0;
101}
102
103buffer_state_enum ftape_set_state(buffer_state_enum new_state)
104{
105 buffer_state_enum old_state = ft_driver_state;
106
107 ft_driver_state = new_state;
108 return old_state;
109}
110/* Calculate Floppy Disk Controller and DMA parameters for a segment.
111 * head: selects buffer struct in array.
112 * offset: number of physical sectors to skip (including bad ones).
113 * count: number of physical sectors to handle (including bad ones).
114 */
115static int setup_segment(buffer_struct * buff,
116 int segment_id,
117 unsigned int sector_offset,
118 unsigned int sector_count,
119 int retry)
120{
121 SectorMap offset_mask;
122 SectorMap mask;
123 TRACE_FUN(ft_t_any);
124
125 buff->segment_id = segment_id;
126 buff->sector_offset = sector_offset;
127 buff->remaining = sector_count;
128 buff->head = segment_id / ftape_segments_per_head;
129 buff->cyl = (segment_id % ftape_segments_per_head) / ftape_segments_per_cylinder;
130 buff->sect = (segment_id % ftape_segments_per_cylinder) * FT_SECTORS_PER_SEGMENT + 1;
131 buff->deleted = 0;
132 offset_mask = (1 << buff->sector_offset) - 1;
133 mask = ftape_get_bad_sector_entry(segment_id) & offset_mask;
134 while (mask) {
135 if (mask & 1) {
136 offset_mask >>= 1; /* don't count bad sector */
137 }
138 mask >>= 1;
139 }
140 buff->data_offset = count_ones(offset_mask); /* good sectors to skip */
141 buff->ptr = buff->address + buff->data_offset * FT_SECTOR_SIZE;
142 TRACE(ft_t_flow, "data offset = %d sectors", buff->data_offset);
143 if (retry) {
144 buff->soft_error_map &= offset_mask; /* keep skipped part */
145 } else {
146 buff->hard_error_map = buff->soft_error_map = 0;
147 }
148 buff->bad_sector_map = ftape_get_bad_sector_entry(buff->segment_id);
149 if (buff->bad_sector_map != 0) {
150 TRACE(ft_t_noise, "segment: %d, bad sector map: %08lx",
151 buff->segment_id, (long)buff->bad_sector_map);
152 } else {
153 TRACE(ft_t_flow, "segment: %d", buff->segment_id);
154 }
155 if (buff->sector_offset > 0) {
156 buff->bad_sector_map >>= buff->sector_offset;
157 }
158 if (buff->sector_offset != 0 || buff->remaining != FT_SECTORS_PER_SEGMENT) {
159 TRACE(ft_t_flow, "sector offset = %d, count = %d",
160 buff->sector_offset, buff->remaining);
161 }
162 /* Segments with 3 or less sectors are not written with valid
163 * data because there is no space left for the ecc. The
164 * data written is whatever happens to be in the buffer.
165 * Reading such a segment will return a zero byte-count.
166 * To allow us to read/write segments with all bad sectors
167 * we fake one readable sector in the segment. This
168 * prevents having to handle these segments in a very
169 * special way. It is not important if the reading of this
170 * bad sector fails or not (the data is ignored). It is
171 * only read to keep the driver running.
172 *
173 * The QIC-40/80 spec. has no information on how to handle
174 * this case, so this is my interpretation.
175 */
176 if (buff->bad_sector_map == EMPTY_SEGMENT) {
177 TRACE(ft_t_flow, "empty segment %d, fake first sector good",
178 buff->segment_id);
179 if (buff->ptr != buff->address) {
180 TRACE(ft_t_bug, "This is a bug: %p/%p",
181 buff->ptr, buff->address);
182 }
183 buff->bad_sector_map = FAKE_SEGMENT;
184 }
185 fdc_setup_error = 0;
186 buff->next_segment = segment_id + 1;
187 TRACE_EXIT 0;
188}
189
190/* Calculate Floppy Disk Controller and DMA parameters for a new segment.
191 */
192int ftape_setup_new_segment(buffer_struct * buff, int segment_id, int skip)
193{
194 int result = 0;
195 static int old_segment_id = -1;
196 static buffer_state_enum old_ft_driver_state = idle;
197 int retry = 0;
198 unsigned offset = 0;
199 int count = FT_SECTORS_PER_SEGMENT;
200 TRACE_FUN(ft_t_flow);
201
202 TRACE(ft_t_flow, "%s segment %d (old = %d)",
203 (ft_driver_state == reading || ft_driver_state == verifying)
204 ? "reading" : "writing",
205 segment_id, old_segment_id);
206 if (ft_driver_state != old_ft_driver_state) { /* when verifying */
207 old_segment_id = -1;
208 old_ft_driver_state = ft_driver_state;
209 }
210 if (segment_id == old_segment_id) {
211 ++buff->retry;
212 ++ft_history.retries;
213 TRACE(ft_t_flow, "setting up for retry nr %d", buff->retry);
214 retry = 1;
215 if (skip && buff->skip > 0) { /* allow skip on retry */
216 offset = buff->skip;
217 count -= offset;
218 TRACE(ft_t_flow, "skipping %d sectors", offset);
219 }
220 } else {
221 buff->retry = 0;
222 buff->skip = 0;
223 old_segment_id = segment_id;
224 }
225 result = setup_segment(buff, segment_id, offset, count, retry);
226 TRACE_EXIT result;
227}
228
229/* Determine size of next cluster of good sectors.
230 */
231int ftape_calc_next_cluster(buffer_struct * buff)
232{
233 /* Skip bad sectors.
234 */
235 while (buff->remaining > 0 && (buff->bad_sector_map & 1) != 0) {
236 buff->bad_sector_map >>= 1;
237 ++buff->sector_offset;
238 --buff->remaining;
239 }
240 /* Find next cluster of good sectors
241 */
242 if (buff->bad_sector_map == 0) { /* speed up */
243 buff->sector_count = buff->remaining;
244 } else {
245 SectorMap map = buff->bad_sector_map;
246
247 buff->sector_count = 0;
248 while (buff->sector_count < buff->remaining && (map & 1) == 0) {
249 ++buff->sector_count;
250 map >>= 1;
251 }
252 }
253 return buff->sector_count;
254}
255
256/* if just passed the last segment on a track, wait for BOT
257 * or EOT mark.
258 */
259int ftape_handle_logical_eot(void)
260{
261 TRACE_FUN(ft_t_flow);
262
263 if (ft_runner_status == logical_eot) {
264 int status;
265
266 TRACE(ft_t_noise, "tape at logical EOT");
267 TRACE_CATCH(ftape_ready_wait(ftape_timeout.seek, &status),);
268 if ((status & (QIC_STATUS_AT_BOT | QIC_STATUS_AT_EOT)) == 0) {
269 TRACE_ABORT(-EIO, ft_t_err, "eot/bot not reached");
270 }
271 ft_runner_status = end_of_tape;
272 }
273 if (ft_runner_status == end_of_tape) {
274 TRACE(ft_t_noise, "runner stopped because of logical EOT");
275 ft_runner_status = idle;
276 }
277 TRACE_EXIT 0;
278}
279
280static int check_bot_eot(int status)
281{
282 TRACE_FUN(ft_t_flow);
283
284 if (status & (QIC_STATUS_AT_BOT | QIC_STATUS_AT_EOT)) {
285 ft_location.bot = ((ft_location.track & 1) == 0 ?
286 (status & QIC_STATUS_AT_BOT) != 0:
287 (status & QIC_STATUS_AT_EOT) != 0);
288 ft_location.eot = !ft_location.bot;
289 ft_location.segment = (ft_location.track +
290 (ft_location.bot ? 0 : 1)) * ft_segments_per_track - 1;
291 ft_location.sector = -1;
292 ft_location.known = 1;
293 TRACE(ft_t_flow, "tape at logical %s",
294 ft_location.bot ? "bot" : "eot");
295 TRACE(ft_t_flow, "segment = %d", ft_location.segment);
296 } else {
297 ft_location.known = 0;
298 }
299 TRACE_EXIT ft_location.known;
300}
301
302/* Read Id of first sector passing tape head.
303 */
304static int ftape_read_id(void)
305{
306 int status;
307 __u8 out[2];
308 TRACE_FUN(ft_t_any);
309
310 /* Assume tape is running on entry, be able to handle
311 * situation where it stopped or is stopping.
312 */
313 ft_location.known = 0; /* default is location not known */
314 out[0] = FDC_READID;
315 out[1] = ft_drive_sel;
316 TRACE_CATCH(fdc_command(out, 2),);
317 switch (fdc_interrupt_wait(20 * FT_SECOND)) {
318 case 0:
319 if (fdc_sect == 0) {
320 if (ftape_report_drive_status(&status) >= 0 &&
321 (status & QIC_STATUS_READY)) {
322 ftape_tape_running = 0;
323 TRACE(ft_t_flow, "tape has stopped");
324 check_bot_eot(status);
325 }
326 } else {
327 ft_location.known = 1;
328 ft_location.segment = (ftape_segments_per_head
329 * fdc_head
330 + ftape_segments_per_cylinder
331 * fdc_cyl
332 + (fdc_sect - 1)
333 / FT_SECTORS_PER_SEGMENT);
334 ft_location.sector = ((fdc_sect - 1)
335 % FT_SECTORS_PER_SEGMENT);
336 ft_location.eot = ft_location.bot = 0;
337 }
338 break;
339 case -ETIME:
340 /* Didn't find id on tape, must be near end: Wait
341 * until stopped.
342 */
343 if (ftape_ready_wait(FT_FOREVER, &status) >= 0) {
344 ftape_tape_running = 0;
345 TRACE(ft_t_flow, "tape has stopped");
346 check_bot_eot(status);
347 }
348 break;
349 default:
350 /* Interrupted or otherwise failing
351 * fdc_interrupt_wait()
352 */
353 TRACE(ft_t_err, "fdc_interrupt_wait failed");
354 break;
355 }
356 if (!ft_location.known) {
357 TRACE_ABORT(-EIO, ft_t_flow, "no id found");
358 }
359 if (ft_location.sector == 0) {
360 TRACE(ft_t_flow, "passing segment %d/%d",
361 ft_location.segment, ft_location.sector);
362 } else {
363 TRACE(ft_t_fdc_dma, "passing segment %d/%d",
364 ft_location.segment, ft_location.sector);
365 }
366 TRACE_EXIT 0;
367}
368
369static int logical_forward(void)
370{
371 ftape_tape_running = 1;
372 return ftape_command(QIC_LOGICAL_FORWARD);
373}
374
375int ftape_stop_tape(int *pstatus)
376{
377 int retry = 0;
378 int result;
379 TRACE_FUN(ft_t_flow);
380
381 do {
382 result = ftape_command_wait(QIC_STOP_TAPE,
383 ftape_timeout.stop, pstatus);
384 if (result == 0) {
385 if ((*pstatus & QIC_STATUS_READY) == 0) {
386 result = -EIO;
387 } else {
388 ftape_tape_running = 0;
389 }
390 }
391 } while (result < 0 && ++retry <= 3);
392 if (result < 0) {
393 TRACE(ft_t_err, "failed ! (fatal)");
394 }
395 TRACE_EXIT result;
396}
397
398int ftape_dumb_stop(void)
399{
400 int result;
401 int status;
402 TRACE_FUN(ft_t_flow);
403
404 /* Abort current fdc operation if it's busy (probably read
405 * or write operation pending) with a reset.
406 */
407 if (fdc_ready_wait(100 /* usec */) < 0) {
408 TRACE(ft_t_noise, "aborting fdc operation");
409 fdc_reset();
410 }
411 /* Reading id's after the last segment on a track may fail
412 * but eventually the drive will become ready (logical eot).
413 */
414 result = ftape_report_drive_status(&status);
415 ft_location.known = 0;
416 do {
417 if (result == 0 && status & QIC_STATUS_READY) {
418 /* Tape is not running any more.
419 */
420 TRACE(ft_t_noise, "tape already halted");
421 check_bot_eot(status);
422 ftape_tape_running = 0;
423 } else if (ftape_tape_running) {
424 /* Tape is (was) still moving.
425 */
426#ifdef TESTING
427 ftape_read_id();
428#endif
429 result = ftape_stop_tape(&status);
430 } else {
431 /* Tape not yet ready but stopped.
432 */
433 result = ftape_ready_wait(ftape_timeout.pause,&status);
434 }
435 } while (ftape_tape_running
436 && !(sigtestsetmask(&current->pending.signal, _NEVER_BLOCK)));
437#ifndef TESTING
438 ft_location.known = 0;
439#endif
440 if (ft_runner_status == aborting || ft_runner_status == do_abort) {
441 ft_runner_status = idle;
442 }
443 TRACE_EXIT result;
444}
445
446/* Wait until runner has finished tail buffer.
447 *
448 */
449int ftape_wait_segment(buffer_state_enum state)
450{
451 int status;
452 int result = 0;
453 TRACE_FUN(ft_t_flow);
454
455 while (ft_buffer[ft_tail]->status == state) {
456 TRACE(ft_t_flow, "state: %d", ft_buffer[ft_tail]->status);
457 /* First buffer still being worked on, wait up to timeout.
458 *
459 * Note: we check two times for being killed. 50
460 * seconds are quite long. Note that
461 * fdc_interrupt_wait() is not killable by any
462 * means. ftape_read_segment() wants us to return
463 * -EINTR in case of a signal.
464 */
465 FT_SIGNAL_EXIT(_DONT_BLOCK);
466 result = fdc_interrupt_wait(50 * FT_SECOND);
467 FT_SIGNAL_EXIT(_DONT_BLOCK);
468 if (result < 0) {
469 TRACE_ABORT(result,
470 ft_t_err, "fdc_interrupt_wait failed");
471 }
472 if (fdc_setup_error) {
473 /* recover... FIXME */
474 TRACE_ABORT(-EIO, ft_t_err, "setup error");
475 }
476 }
477 if (ft_buffer[ft_tail]->status != error) {
478 TRACE_EXIT 0;
479 }
480 TRACE_CATCH(ftape_report_drive_status(&status),);
481 TRACE(ft_t_noise, "ftape_report_drive_status: 0x%02x", status);
482 if ((status & QIC_STATUS_READY) &&
483 (status & QIC_STATUS_ERROR)) {
484 unsigned int error;
485 qic117_cmd_t command;
486
487 /* Report and clear error state.
488 * In case the drive can't operate at the selected
489 * rate, select the next lower data rate.
490 */
491 ftape_report_error(&error, &command, 1);
492 if (error == 31 && command == QIC_LOGICAL_FORWARD) {
493 /* drive does not accept this data rate */
494 if (ft_data_rate > 250) {
495 TRACE(ft_t_info,
496 "Probable data rate conflict");
497 TRACE(ft_t_info,
498 "Lowering data rate to %d Kbps",
499 ft_data_rate / 2);
500 ftape_half_data_rate();
501 if (ft_buffer[ft_tail]->retry > 0) {
502 /* give it a chance */
503 --ft_buffer[ft_tail]->retry;
504 }
505 } else {
506 /* no rate is accepted... */
507 TRACE(ft_t_err, "We're dead :(");
508 }
509 } else {
510 TRACE(ft_t_err, "Unknown error");
511 }
512 TRACE_EXIT -EIO; /* g.p. error */
513 }
514 TRACE_EXIT 0;
515}
516
517/* forward */ static int seek_forward(int segment_id, int fast);
518
519static int fast_seek(int count, int reverse)
520{
521 int result = 0;
522 int status;
523 TRACE_FUN(ft_t_flow);
524
525 if (count > 0) {
526 /* If positioned at begin or end of tape, fast seeking needs
527 * special treatment.
528 * Starting from logical bot needs a (slow) seek to the first
529 * segment before the high speed seek. Most drives do this
530 * automatically but some older don't, so we treat them
531 * all the same.
532 * Starting from logical eot is even more difficult because
533 * we cannot (slow) reverse seek to the last segment.
534 * TO BE IMPLEMENTED.
535 */
536 inhibit_correction = 0;
537 if (ft_location.known &&
538 ((ft_location.bot && !reverse) ||
539 (ft_location.eot && reverse))) {
540 if (!reverse) {
541 /* (slow) skip to first segment on a track
542 */
543 seek_forward(ft_location.track * ft_segments_per_track, 0);
544 --count;
545 } else {
546 /* When seeking backwards from
547 * end-of-tape the number of erased
548 * gaps found seems to be higher than
549 * expected. Therefor the drive must
550 * skip some more segments than
551 * calculated, but we don't know how
552 * many. Thus we will prevent the
553 * re-calculation of offset and
554 * overshoot when seeking backwards.
555 */
556 inhibit_correction = 1;
557 count += 3; /* best guess */
558 }
559 }
560 } else {
561 TRACE(ft_t_flow, "warning: zero or negative count: %d", count);
562 }
563 if (count > 0) {
564 int i;
565 int nibbles = count > 255 ? 3 : 2;
566
567 if (count > 4095) {
568 TRACE(ft_t_noise, "skipping clipped at 4095 segment");
569 count = 4095;
570 }
571 /* Issue this tape command first. */
572 if (!reverse) {
573 TRACE(ft_t_noise, "skipping %d segment(s)", count);
574 result = ftape_command(nibbles == 3 ?
575 QIC_SKIP_EXTENDED_FORWARD : QIC_SKIP_FORWARD);
576 } else {
577 TRACE(ft_t_noise, "backing up %d segment(s)", count);
578 result = ftape_command(nibbles == 3 ?
579 QIC_SKIP_EXTENDED_REVERSE : QIC_SKIP_REVERSE);
580 }
581 if (result < 0) {
582 TRACE(ft_t_noise, "Skip command failed");
583 } else {
584 --count; /* 0 means one gap etc. */
585 for (i = 0; i < nibbles; ++i) {
586 if (result >= 0) {
587 result = ftape_parameter(count & 15);
588 count /= 16;
589 }
590 }
591 result = ftape_ready_wait(ftape_timeout.rewind, &status);
592 if (result >= 0) {
593 ftape_tape_running = 0;
594 }
595 }
596 }
597 TRACE_EXIT result;
598}
599
600static int validate(int id)
601{
602 /* Check to see if position found is off-track as reported
603 * once. Because all tracks in one direction lie next to
604 * each other, if off-track the error will be approximately
605 * 2 * ft_segments_per_track.
606 */
607 if (ft_location.track == -1) {
608 return 1; /* unforseen situation, don't generate error */
609 } else {
610 /* Use margin of ft_segments_per_track on both sides
611 * because ftape needs some margin and the error we're
612 * looking for is much larger !
613 */
614 int lo = (ft_location.track - 1) * ft_segments_per_track;
615 int hi = (ft_location.track + 2) * ft_segments_per_track;
616
617 return (id >= lo && id < hi);
618 }
619}
620
621static int seek_forward(int segment_id, int fast)
622{
623 int failures = 0;
624 int count;
625 static int margin = 1; /* fixed: stop this before target */
626 static int overshoot = 1;
627 static int min_count = 8;
628 int expected = -1;
629 int target = segment_id - margin;
630 int fast_seeking;
631 int prev_segment = ft_location.segment;
632 TRACE_FUN(ft_t_flow);
633
634 if (!ft_location.known) {
635 TRACE_ABORT(-EIO, ft_t_err,
636 "fatal: cannot seek from unknown location");
637 }
638 if (!validate(segment_id)) {
639 ftape_sleep(1 * FT_SECOND);
640 ft_failure = 1;
641 TRACE_ABORT(-EIO, ft_t_err,
642 "fatal: head off track (bad hardware?)");
643 }
644 TRACE(ft_t_noise, "from %d/%d to %d/0 - %d",
645 ft_location.segment, ft_location.sector,segment_id,margin);
646 count = target - ft_location.segment - overshoot;
647 fast_seeking = (fast &&
648 count > (min_count + (ft_location.bot ? 1 : 0)));
649 if (fast_seeking) {
650 TRACE(ft_t_noise, "fast skipping %d segments", count);
651 expected = segment_id - margin;
652 fast_seek(count, 0);
653 }
654 if (!ftape_tape_running) {
655 logical_forward();
656 }
657 while (ft_location.segment < segment_id) {
658 /* This requires at least one sector in a (bad) segment to
659 * have a valid and readable sector id !
660 * It looks like this is not guaranteed, so we must try
661 * to find a way to skip an EMPTY_SEGMENT. !!! FIXME !!!
662 */
663 if (ftape_read_id() < 0 || !ft_location.known ||
664 sigtestsetmask(&current->pending.signal, _DONT_BLOCK)) {
665 ft_location.known = 0;
666 if (!ftape_tape_running ||
667 ++failures > FT_SECTORS_PER_SEGMENT) {
668 TRACE_ABORT(-EIO, ft_t_err,
669 "read_id failed completely");
670 }
671 FT_SIGNAL_EXIT(_DONT_BLOCK);
672 TRACE(ft_t_flow, "read_id failed, retry (%d)",
673 failures);
674 continue;
675 }
676 if (fast_seeking) {
677 TRACE(ft_t_noise, "ended at %d/%d (%d,%d)",
678 ft_location.segment, ft_location.sector,
679 overshoot, inhibit_correction);
680 if (!inhibit_correction &&
681 (ft_location.segment < expected ||
682 ft_location.segment > expected + margin)) {
683 int error = ft_location.segment - expected;
684 TRACE(ft_t_noise,
685 "adjusting overshoot from %d to %d",
686 overshoot, overshoot + error);
687 overshoot += error;
688 /* All overshoots have the same
689 * direction, so it should never
690 * become negative, but who knows.
691 */
692 if (overshoot < -5 ||
693 overshoot > OVERSHOOT_LIMIT) {
694 if (overshoot < 0) {
695 /* keep sane value */
696 overshoot = -5;
697 } else {
698 /* keep sane value */
699 overshoot = OVERSHOOT_LIMIT;
700 }
701 TRACE(ft_t_noise,
702 "clipped overshoot to %d",
703 overshoot);
704 }
705 }
706 fast_seeking = 0;
707 }
708 if (ft_location.known) {
709 if (ft_location.segment > prev_segment + 1) {
710 TRACE(ft_t_noise,
711 "missed segment %d while skipping",
712 prev_segment + 1);
713 }
714 prev_segment = ft_location.segment;
715 }
716 }
717 if (ft_location.segment > segment_id) {
718 TRACE_ABORT(-EIO,
719 ft_t_noise, "failed: skip ended at segment %d/%d",
720 ft_location.segment, ft_location.sector);
721 }
722 TRACE_EXIT 0;
723}
724
725static int skip_reverse(int segment_id, int *pstatus)
726{
727 int failures = 0;
728 static int overshoot = 1;
729 static int min_rewind = 2; /* 1 + overshoot */
730 static const int margin = 1; /* stop this before target */
731 int expected = 0;
732 int count = 1;
733 int short_seek;
734 int target = segment_id - margin;
735 TRACE_FUN(ft_t_flow);
736
737 if (ft_location.known && !validate(segment_id)) {
738 ftape_sleep(1 * FT_SECOND);
739 ft_failure = 1;
740 TRACE_ABORT(-EIO, ft_t_err,
741 "fatal: head off track (bad hardware?)");
742 }
743 do {
744 if (!ft_location.known) {
745 TRACE(ft_t_warn, "warning: location not known");
746 }
747 TRACE(ft_t_noise, "from %d/%d to %d/0 - %d",
748 ft_location.segment, ft_location.sector,
749 segment_id, margin);
750 /* min_rewind == 1 + overshoot_when_doing_minimum_rewind
751 * overshoot == overshoot_when_doing_larger_rewind
752 * Initially min_rewind == 1 + overshoot, optimization
753 * of both values will be done separately.
754 * overshoot and min_rewind can be negative as both are
755 * sums of three components:
756 * any_overshoot == rewind_overshoot -
757 * stop_overshoot -
758 * start_overshoot
759 */
760 if (ft_location.segment - target - (min_rewind - 1) < 1) {
761 short_seek = 1;
762 } else {
763 count = ft_location.segment - target - overshoot;
764 short_seek = (count < 1);
765 }
766 if (short_seek) {
767 count = 1; /* do shortest rewind */
768 expected = ft_location.segment - min_rewind;
769 if (expected/ft_segments_per_track != ft_location.track) {
770 expected = (ft_location.track *
771 ft_segments_per_track);
772 }
773 } else {
774 expected = target;
775 }
776 fast_seek(count, 1);
777 logical_forward();
778 if (ftape_read_id() < 0 || !ft_location.known ||
779 (sigtestsetmask(&current->pending.signal, _DONT_BLOCK))) {
780 if ((!ftape_tape_running && !ft_location.known) ||
781 ++failures > FT_SECTORS_PER_SEGMENT) {
782 TRACE_ABORT(-EIO, ft_t_err,
783 "read_id failed completely");
784 }
785 FT_SIGNAL_EXIT(_DONT_BLOCK);
786 TRACE_CATCH(ftape_report_drive_status(pstatus),);
787 TRACE(ft_t_noise, "ftape_read_id failed, retry (%d)",
788 failures);
789 continue;
790 }
791 TRACE(ft_t_noise, "ended at %d/%d (%d,%d,%d)",
792 ft_location.segment, ft_location.sector,
793 min_rewind, overshoot, inhibit_correction);
794 if (!inhibit_correction &&
795 (ft_location.segment < expected ||
796 ft_location.segment > expected + margin)) {
797 int error = expected - ft_location.segment;
798 if (short_seek) {
799 TRACE(ft_t_noise,
800 "adjusting min_rewind from %d to %d",
801 min_rewind, min_rewind + error);
802 min_rewind += error;
803 if (min_rewind < -5) {
804 /* is this right ? FIXME ! */
805 /* keep sane value */
806 min_rewind = -5;
807 TRACE(ft_t_noise,
808 "clipped min_rewind to %d",
809 min_rewind);
810 }
811 } else {
812 TRACE(ft_t_noise,
813 "adjusting overshoot from %d to %d",
814 overshoot, overshoot + error);
815 overshoot += error;
816 if (overshoot < -5 ||
817 overshoot > OVERSHOOT_LIMIT) {
818 if (overshoot < 0) {
819 /* keep sane value */
820 overshoot = -5;
821 } else {
822 /* keep sane value */
823 overshoot = OVERSHOOT_LIMIT;
824 }
825 TRACE(ft_t_noise,
826 "clipped overshoot to %d",
827 overshoot);
828 }
829 }
830 }
831 } while (ft_location.segment > segment_id);
832 if (ft_location.known) {
833 TRACE(ft_t_noise, "current location: %d/%d",
834 ft_location.segment, ft_location.sector);
835 }
836 TRACE_EXIT 0;
837}
838
839static int determine_position(void)
840{
841 int retry = 0;
842 int status;
843 int result;
844 TRACE_FUN(ft_t_flow);
845
846 if (!ftape_tape_running) {
847 /* This should only happen if tape is stopped by isr.
848 */
849 TRACE(ft_t_flow, "waiting for tape stop");
850 if (ftape_ready_wait(ftape_timeout.pause, &status) < 0) {
851 TRACE(ft_t_flow, "drive still running (fatal)");
852 ftape_tape_running = 1; /* ? */
853 }
854 } else {
855 ftape_report_drive_status(&status);
856 }
857 if (status & QIC_STATUS_READY) {
858 /* Drive must be ready to check error state !
859 */
860 TRACE(ft_t_flow, "drive is ready");
861 if (status & QIC_STATUS_ERROR) {
862 unsigned int error;
863 qic117_cmd_t command;
864
865 /* Report and clear error state, try to continue.
866 */
867 TRACE(ft_t_flow, "error status set");
868 ftape_report_error(&error, &command, 1);
869 ftape_ready_wait(ftape_timeout.reset, &status);
870 ftape_tape_running = 0; /* ? */
871 }
872 if (check_bot_eot(status)) {
873 if (ft_location.bot) {
874 if ((status & QIC_STATUS_READY) == 0) {
875 /* tape moving away from
876 * bot/eot, let's see if we
877 * can catch up with the first
878 * segment on this track.
879 */
880 } else {
881 TRACE(ft_t_flow,
882 "start tape from logical bot");
883 logical_forward(); /* start moving */
884 }
885 } else {
886 if ((status & QIC_STATUS_READY) == 0) {
887 TRACE(ft_t_noise, "waiting for logical end of track");
888 result = ftape_ready_wait(ftape_timeout.reset, &status);
889 /* error handling needed ? */
890 } else {
891 TRACE(ft_t_noise,
892 "tape at logical end of track");
893 }
894 }
895 } else {
896 TRACE(ft_t_flow, "start tape");
897 logical_forward(); /* start moving */
898 ft_location.known = 0; /* not cleared by logical forward ! */
899 }
900 }
901 /* tape should be moving now, start reading id's
902 */
903 while (!ft_location.known &&
904 retry++ < FT_SECTORS_PER_SEGMENT &&
905 (result = ftape_read_id()) < 0) {
906
907 TRACE(ft_t_flow, "location unknown");
908
909 /* exit on signal
910 */
911 FT_SIGNAL_EXIT(_DONT_BLOCK);
912
913 /* read-id somehow failed, tape may
914 * have reached end or some other
915 * error happened.
916 */
917 TRACE(ft_t_flow, "read-id failed");
918 TRACE_CATCH(ftape_report_drive_status(&status),);
919 TRACE(ft_t_err, "ftape_report_drive_status: 0x%02x", status);
920 if (status & QIC_STATUS_READY) {
921 ftape_tape_running = 0;
922 TRACE(ft_t_noise, "tape stopped for unknown reason! "
923 "status = 0x%02x", status);
924 if (status & QIC_STATUS_ERROR ||
925 !check_bot_eot(status)) {
926 /* oops, tape stopped but not at end!
927 */
928 TRACE_EXIT -EIO;
929 }
930 }
931 }
932 TRACE(ft_t_flow,
933 "tape is positioned at segment %d", ft_location.segment);
934 TRACE_EXIT ft_location.known ? 0 : -EIO;
935}
936
937/* Get the tape running and position it just before the
938 * requested segment.
939 * Seek tape-track and reposition as needed.
940 */
941int ftape_start_tape(int segment_id, int sector_offset)
942{
943 int track = segment_id / ft_segments_per_track;
944 int result = -EIO;
945 int status;
946 static int last_segment = -1;
947 static int bad_bus_timing = 0;
948 /* number of segments passing the head between starting the tape
949 * and being able to access the first sector.
950 */
951 static int start_offset = 1;
952 int retry;
953 TRACE_FUN(ft_t_flow);
954
955 /* If sector_offset > 0, seek into wanted segment instead of
956 * into previous.
957 * This allows error recovery if a part of the segment is bad
958 * (erased) causing the tape drive to generate an index pulse
959 * thus causing a no-data error before the requested sector
960 * is reached.
961 */
962 ftape_tape_running = 0;
963 TRACE(ft_t_noise, "target segment: %d/%d%s", segment_id, sector_offset,
964 ft_buffer[ft_head]->retry > 0 ? " retry" : "");
965 if (ft_buffer[ft_head]->retry > 0) { /* this is a retry */
966 int dist = segment_id - last_segment;
967
968 if ((int)ft_history.overrun_errors < overrun_count_offset) {
969 overrun_count_offset = ft_history.overrun_errors;
970 } else if (dist < 0 || dist > 50) {
971 overrun_count_offset = ft_history.overrun_errors;
972 } else if ((ft_history.overrun_errors -
973 overrun_count_offset) >= 8) {
974 if (ftape_increase_threshold() >= 0) {
975 --ft_buffer[ft_head]->retry;
976 overrun_count_offset =
977 ft_history.overrun_errors;
978 TRACE(ft_t_warn, "increased threshold because "
979 "of excessive overrun errors");
980 } else if (!bad_bus_timing && ft_data_rate >= 1000) {
981 ftape_half_data_rate();
982 --ft_buffer[ft_head]->retry;
983 bad_bus_timing = 1;
984 overrun_count_offset =
985 ft_history.overrun_errors;
986 TRACE(ft_t_warn, "reduced datarate because "
987 "of excessive overrun errors");
988 }
989 }
990 }
991 last_segment = segment_id;
992 if (ft_location.track != track ||
993 (ftape_might_be_off_track && ft_buffer[ft_head]->retry== 0)) {
994 /* current track unknown or not equal to destination
995 */
996 ftape_ready_wait(ftape_timeout.seek, &status);
997 ftape_seek_head_to_track(track);
998 /* overrun_count_offset = ft_history.overrun_errors; */
999 }
1000 result = -EIO;
1001 retry = 0;
1002 while (result < 0 &&
1003 retry++ <= 5 &&
1004 !ft_failure &&
1005 !(sigtestsetmask(&current->pending.signal, _DONT_BLOCK))) {
1006
1007 if (retry && start_offset < 5) {
1008 start_offset ++;
1009 }
1010 /* Check if we are able to catch the requested
1011 * segment in time.
1012 */
1013 if ((ft_location.known || (determine_position() == 0)) &&
1014 ft_location.segment >=
1015 (segment_id -
1016 ((ftape_tape_running || ft_location.bot)
1017 ? 0 : start_offset))) {
1018 /* Too far ahead (in or past target segment).
1019 */
1020 if (ftape_tape_running) {
1021 if ((result = ftape_stop_tape(&status)) < 0) {
1022 TRACE(ft_t_err,
1023 "stop tape failed with code %d",
1024 result);
1025 break;
1026 }
1027 TRACE(ft_t_noise, "tape stopped");
1028 ftape_tape_running = 0;
1029 }
1030 TRACE(ft_t_noise, "repositioning");
1031 ++ft_history.rewinds;
1032 if (segment_id % ft_segments_per_track < start_offset){
1033 TRACE(ft_t_noise, "end of track condition\n"
1034 KERN_INFO "segment_id : %d\n"
1035 KERN_INFO "ft_segments_per_track: %d\n"
1036 KERN_INFO "start_offset : %d",
1037 segment_id, ft_segments_per_track,
1038 start_offset);
1039
1040 /* If seeking to first segments on
1041 * track better do a complete rewind
1042 * to logical begin of track to get a
1043 * more steady tape motion.
1044 */
1045 result = ftape_command_wait(
1046 (ft_location.track & 1)
1047 ? QIC_PHYSICAL_FORWARD
1048 : QIC_PHYSICAL_REVERSE,
1049 ftape_timeout.rewind, &status);
1050 check_bot_eot(status); /* update location */
1051 } else {
1052 result= skip_reverse(segment_id - start_offset,
1053 &status);
1054 }
1055 }
1056 if (!ft_location.known) {
1057 TRACE(ft_t_bug, "panic: location not known");
1058 result = -EIO;
1059 continue; /* while() will check for failure */
1060 }
1061 TRACE(ft_t_noise, "current segment: %d/%d",
1062 ft_location.segment, ft_location.sector);
1063 /* We're on the right track somewhere before the
1064 * wanted segment. Start tape movement if needed and
1065 * skip to just before or inside the requested
1066 * segment. Keep tape running.
1067 */
1068 result = 0;
1069 if (ft_location.segment <
1070 (segment_id - ((ftape_tape_running || ft_location.bot)
1071 ? 0 : start_offset))) {
1072 if (sector_offset > 0) {
1073 result = seek_forward(segment_id,
1074 retry <= 3);
1075 } else {
1076 result = seek_forward(segment_id - 1,
1077 retry <= 3);
1078 }
1079 }
1080 if (result == 0 &&
1081 ft_location.segment !=
1082 (segment_id - (sector_offset > 0 ? 0 : 1))) {
1083 result = -EIO;
1084 }
1085 }
1086 if (result < 0) {
1087 TRACE(ft_t_err, "failed to reposition");
1088 } else {
1089 ft_runner_status = running;
1090 }
1091 TRACE_EXIT result;
1092}
diff --git a/drivers/char/ftape/lowlevel/ftape-rw.h b/drivers/char/ftape/lowlevel/ftape-rw.h
deleted file mode 100644
index 32f4feeb887c..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-rw.h
+++ /dev/null
@@ -1,111 +0,0 @@
1#ifndef _FTAPE_RW_H
2#define _FTAPE_RW_H
3
4/*
5 * Copyright (C) 1993-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-rw.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:25 $
26 *
27 * This file contains the definitions for the read and write
28 * functions for the QIC-117 floppy-tape driver for Linux.
29 *
30 * Claus-Justus Heine (1996/09/20): Add definition of format code 6
31 * Claus-Justus Heine (1996/10/04): Changed GET/PUT macros to cast to (__u8 *)
32 *
33 */
34
35#include "../lowlevel/fdc-io.h"
36#include "../lowlevel/ftape-init.h"
37#include "../lowlevel/ftape-bsm.h"
38
39#include <asm/unaligned.h>
40
41#define GET2(address, offset) get_unaligned((__u16*)((__u8 *)address + offset))
42#define GET4(address, offset) get_unaligned((__u32*)((__u8 *)address + offset))
43#define GET8(address, offset) get_unaligned((__u64*)((__u8 *)address + offset))
44#define PUT2(address, offset , value) put_unaligned((value), (__u16*)((__u8 *)address + offset))
45#define PUT4(address, offset , value) put_unaligned((value), (__u32*)((__u8 *)address + offset))
46#define PUT8(address, offset , value) put_unaligned((value), (__u64*)((__u8 *)address + offset))
47
48enum runner_status_enum {
49 idle = 0,
50 running,
51 do_abort,
52 aborting,
53 logical_eot,
54 end_of_tape,
55};
56
57typedef enum ft_buffer_queue {
58 ft_queue_head = 0,
59 ft_queue_tail = 1
60} ft_buffer_queue_t;
61
62
63typedef struct {
64 int track; /* tape head position */
65 volatile int segment; /* current segment */
66 volatile int sector; /* sector offset within current segment */
67 volatile unsigned int bot; /* logical begin of track */
68 volatile unsigned int eot; /* logical end of track */
69 volatile unsigned int known; /* validates bot, segment, sector */
70} location_record;
71
72/* Count nr of 1's in pattern.
73 */
74static inline int count_ones(unsigned long mask)
75{
76 int bits;
77
78 for (bits = 0; mask != 0; mask >>= 1) {
79 if (mask & 1) {
80 ++bits;
81 }
82 }
83 return bits;
84}
85
86#define FT_MAX_NR_BUFFERS 16 /* arbitrary value */
87/* ftape-rw.c defined global vars.
88 */
89extern buffer_struct *ft_buffer[FT_MAX_NR_BUFFERS];
90extern int ft_nr_buffers;
91extern location_record ft_location;
92extern volatile int ftape_tape_running;
93
94/* ftape-rw.c defined global functions.
95 */
96extern int ftape_setup_new_segment(buffer_struct * buff,
97 int segment_id,
98 int offset);
99extern int ftape_calc_next_cluster(buffer_struct * buff);
100extern buffer_struct *ftape_next_buffer (ft_buffer_queue_t pos);
101extern buffer_struct *ftape_get_buffer (ft_buffer_queue_t pos);
102extern int ftape_buffer_id (ft_buffer_queue_t pos);
103extern void ftape_reset_buffer(void);
104extern void ftape_tape_parameters(__u8 drive_configuration);
105extern int ftape_wait_segment(buffer_state_enum state);
106extern int ftape_dumb_stop(void);
107extern int ftape_start_tape(int segment_id, int offset);
108extern int ftape_stop_tape(int *pstatus);
109extern int ftape_handle_logical_eot(void);
110extern buffer_state_enum ftape_set_state(buffer_state_enum new_state);
111#endif /* _FTAPE_RW_H */
diff --git a/drivers/char/ftape/lowlevel/ftape-setup.c b/drivers/char/ftape/lowlevel/ftape-setup.c
deleted file mode 100644
index 678340acd0b7..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-setup.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * Copyright (C) 1996, 1997 Claus-Justus Heine.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-setup.c,v $
20 * $Revision: 1.7 $
21 * $Date: 1997/10/10 09:57:06 $
22 *
23 * This file contains the code for processing the kernel command
24 * line options for the QIC-40/80/3010/3020 floppy-tape driver
25 * "ftape" for Linux.
26 */
27
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/mm.h>
31
32#include <linux/ftape.h>
33#include <linux/init.h>
34#include "../lowlevel/ftape-tracing.h"
35#include "../lowlevel/fdc-io.h"
36
37static struct param_table {
38 const char *name;
39 int *var;
40 int def_param;
41 int min;
42 int max;
43} config_params[] __initdata = {
44#ifndef CONFIG_FT_NO_TRACE_AT_ALL
45 { "tracing", &ftape_tracing, 3, ft_t_bug, ft_t_any},
46#endif
47 { "ioport", &ft_fdc_base, CONFIG_FT_FDC_BASE, 0x0, 0xfff},
48 { "irq", &ft_fdc_irq, CONFIG_FT_FDC_IRQ, 2, 15},
49 { "dma", &ft_fdc_dma, CONFIG_FT_FDC_DMA, 0, 3},
50 { "threshold", &ft_fdc_threshold, CONFIG_FT_FDC_THR, 1, 16},
51 { "datarate", &ft_fdc_rate_limit, CONFIG_FT_FDC_MAX_RATE, 500, 2000},
52 { "fc10", &ft_probe_fc10, CONFIG_FT_PROBE_FC10, 0, 1},
53 { "mach2", &ft_mach2, CONFIG_FT_MACH2, 0, 1}
54};
55
56static int __init ftape_setup(char *str)
57{
58 int i;
59 int param;
60 int ints[2];
61
62 TRACE_FUN(ft_t_flow);
63
64 str = get_options(str, ARRAY_SIZE(ints), ints);
65 if (str) {
66 for (i=0; i < NR_ITEMS(config_params); i++) {
67 if (strcmp(str,config_params[i].name) == 0){
68 if (ints[0]) {
69 param = ints[1];
70 } else {
71 param = config_params[i].def_param;
72 }
73 if (param < config_params[i].min ||
74 param > config_params[i].max) {
75 TRACE(ft_t_err,
76 "parameter %s out of range %d ... %d",
77 config_params[i].name,
78 config_params[i].min,
79 config_params[i].max);
80 goto out;
81 }
82 if(config_params[i].var) {
83 TRACE(ft_t_info, "%s=%d", str, param);
84 *config_params[i].var = param;
85 }
86 goto out;
87 }
88 }
89 }
90 if (str) {
91 TRACE(ft_t_err, "unknown ftape option [%s]", str);
92
93 TRACE(ft_t_err, "allowed options are:");
94 for (i=0; i < NR_ITEMS(config_params); i++) {
95 TRACE(ft_t_err, " %s",config_params[i].name);
96 }
97 } else {
98 TRACE(ft_t_err, "botched ftape option");
99 }
100 out:
101 TRACE_EXIT 1;
102}
103
104__setup("ftape=", ftape_setup);
diff --git a/drivers/char/ftape/lowlevel/ftape-tracing.c b/drivers/char/ftape/lowlevel/ftape-tracing.c
deleted file mode 100644
index 7fdc6567440b..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-tracing.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * Copyright (C) 1993-1996 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-tracing.c,v $
21 * $Revision: 1.2 $
22 * $Date: 1997/10/05 19:18:27 $
23 *
24 * This file contains the reading code
25 * for the QIC-117 floppy-tape driver for Linux.
26 */
27
28#include <linux/ftape.h>
29#include "../lowlevel/ftape-tracing.h"
30
31/* Global vars.
32 */
33/* tracing
34 * set it to: to log :
35 * 0 bugs
36 * 1 + errors
37 * 2 + warnings
38 * 3 + information
39 * 4 + more information
40 * 5 + program flow
41 * 6 + fdc/dma info
42 * 7 + data flow
43 * 8 + everything else
44 */
45ft_trace_t ftape_tracing = ft_t_info; /* Default level: information and up */
46int ftape_function_nest_level;
47
48/* Local vars.
49 */
50static __u8 trace_id;
51static char spacing[] = "* ";
52
53void ftape_trace_call(const char *file, const char *name)
54{
55 char *indent;
56
57 /* Since printk seems not to work with "%*s" format
58 * we'll use this work-around.
59 */
60 if (ftape_function_nest_level < 0) {
61 printk(KERN_INFO "function nest level (%d) < 0\n",
62 ftape_function_nest_level);
63 ftape_function_nest_level = 0;
64 }
65 if (ftape_function_nest_level < sizeof(spacing)) {
66 indent = (spacing +
67 sizeof(spacing) - 1 -
68 ftape_function_nest_level);
69 } else {
70 indent = spacing;
71 }
72 printk(KERN_INFO "[%03d]%s+%s (%s)\n",
73 (int) trace_id++, indent, file, name);
74}
75
76void ftape_trace_exit(const char *file, const char *name)
77{
78 char *indent;
79
80 /* Since printk seems not to work with "%*s" format
81 * we'll use this work-around.
82 */
83 if (ftape_function_nest_level < 0) {
84 printk(KERN_INFO "function nest level (%d) < 0\n", ftape_function_nest_level);
85 ftape_function_nest_level = 0;
86 }
87 if (ftape_function_nest_level < sizeof(spacing)) {
88 indent = (spacing +
89 sizeof(spacing) - 1 -
90 ftape_function_nest_level);
91 } else {
92 indent = spacing;
93 }
94 printk(KERN_INFO "[%03d]%s-%s (%s)\n",
95 (int) trace_id++, indent, file, name);
96}
97
98void ftape_trace_log(const char *file, const char *function)
99{
100 char *indent;
101
102 /* Since printk seems not to work with "%*s" format
103 * we'll use this work-around.
104 */
105 if (ftape_function_nest_level < 0) {
106 printk(KERN_INFO "function nest level (%d) < 0\n", ftape_function_nest_level);
107 ftape_function_nest_level = 0;
108 }
109 if (ftape_function_nest_level < sizeof(spacing)) {
110 indent = (spacing +
111 sizeof(spacing) - 1 -
112 ftape_function_nest_level);
113 } else {
114 indent = spacing;
115 }
116 printk(KERN_INFO "[%03d]%s%s (%s) - ",
117 (int) trace_id++, indent, file, function);
118}
diff --git a/drivers/char/ftape/lowlevel/ftape-tracing.h b/drivers/char/ftape/lowlevel/ftape-tracing.h
deleted file mode 100644
index 2950810c7085..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-tracing.h
+++ /dev/null
@@ -1,179 +0,0 @@
1#ifndef _FTAPE_TRACING_H
2#define _FTAPE_TRACING_H
3
4/*
5 * Copyright (C) 1994-1996 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-tracing.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:18:28 $
26 *
27 * This file contains definitions that eases the debugging of the
28 * QIC-40/80/3010/3020 floppy-tape driver "ftape" for Linux.
29 */
30
31#include <linux/kernel.h>
32
33/*
34 * Be very careful with TRACE_EXIT and TRACE_ABORT.
35 *
36 * if (something) TRACE_EXIT error;
37 *
38 * will NOT work. Use
39 *
40 * if (something) {
41 * TRACE_EXIT error;
42 * }
43 *
44 * instead. Maybe a bit dangerous, but save lots of lines of code.
45 */
46
47#define LL_X "%d/%d KB"
48#define LL(x) (unsigned int)((__u64)(x)>>10), (unsigned int)((x)&1023)
49
50typedef enum {
51 ft_t_nil = -1,
52 ft_t_bug,
53 ft_t_err,
54 ft_t_warn,
55 ft_t_info,
56 ft_t_noise,
57 ft_t_flow,
58 ft_t_fdc_dma,
59 ft_t_data_flow,
60 ft_t_any
61} ft_trace_t;
62
63#ifdef CONFIG_FT_NO_TRACE_AT_ALL
64/* the compiler will optimize away most TRACE() macros
65 */
66#define FT_TRACE_TOP_LEVEL ft_t_bug
67#define TRACE_FUN(level) do {} while(0)
68#define TRACE_EXIT return
69#define TRACE(l, m, i...) \
70{ \
71 if ((ft_trace_t)(l) == FT_TRACE_TOP_LEVEL) { \
72 printk(KERN_INFO"ftape%s(%s):\n" \
73 KERN_INFO m".\n" ,__FILE__, __FUNCTION__ , ##i); \
74 } \
75}
76#define SET_TRACE_LEVEL(l) if ((l) == (l)) do {} while(0)
77#define TRACE_LEVEL FT_TRACE_TOP_LEVEL
78
79#else
80
81#ifdef CONFIG_FT_NO_TRACE
82/* the compiler will optimize away many TRACE() macros
83 * the ftape_simple_trace_call() function simply increments
84 * the function nest level.
85 */
86#define FT_TRACE_TOP_LEVEL ft_t_warn
87#define TRACE_FUN(level) ftape_function_nest_level++
88#define TRACE_EXIT ftape_function_nest_level--; return
89
90#else
91#ifdef CONFIG_FT_FULL_DEBUG
92#define FT_TRACE_TOP_LEVEL ft_t_any
93#else
94#define FT_TRACE_TOP_LEVEL ft_t_flow
95#endif
96#define TRACE_FUN(level) \
97 const ft_trace_t _tracing = level; \
98 if (ftape_tracing >= (ft_trace_t)(level) && \
99 (ft_trace_t)(level) <= FT_TRACE_TOP_LEVEL) \
100 ftape_trace_call(__FILE__, __FUNCTION__); \
101 ftape_function_nest_level ++;
102
103#define TRACE_EXIT \
104 --ftape_function_nest_level; \
105 if (ftape_tracing >= (ft_trace_t)(_tracing) && \
106 (ft_trace_t)(_tracing) <= FT_TRACE_TOP_LEVEL) \
107 ftape_trace_exit(__FILE__, __FUNCTION__); \
108 return
109
110#endif
111
112#define TRACE(l, m, i...) \
113{ \
114 if (ftape_tracing >= (ft_trace_t)(l) && \
115 (ft_trace_t)(l) <= FT_TRACE_TOP_LEVEL) { \
116 ftape_trace_log(__FILE__, __FUNCTION__); \
117 printk(m".\n" ,##i); \
118 } \
119}
120
121#define SET_TRACE_LEVEL(l) \
122{ \
123 if ((ft_trace_t)(l) <= FT_TRACE_TOP_LEVEL) { \
124 ftape_tracing = (ft_trace_t)(l); \
125 } else { \
126 ftape_tracing = FT_TRACE_TOP_LEVEL; \
127 } \
128}
129#define TRACE_LEVEL \
130((ftape_tracing <= FT_TRACE_TOP_LEVEL) ? ftape_tracing : FT_TRACE_TOP_LEVEL)
131
132
133/* Global variables declared in tracing.c
134 */
135extern ft_trace_t ftape_tracing; /* sets default level */
136extern int ftape_function_nest_level;
137
138/* Global functions declared in tracing.c
139 */
140extern void ftape_trace_call(const char *file, const char *name);
141extern void ftape_trace_exit(const char *file, const char *name);
142extern void ftape_trace_log (const char *file, const char *name);
143
144#endif /* !defined(CONFIG_FT_NO_TRACE_AT_ALL) */
145
146/*
147 * Abort with a message.
148 */
149#define TRACE_ABORT(res, i...) \
150{ \
151 TRACE(i); \
152 TRACE_EXIT res; \
153}
154
155/* The following transforms the common "if(result < 0) ... " into a
156 * one-liner.
157 */
158#define _TRACE_CATCH(level, fun, action) \
159{ \
160 int _res = (fun); \
161 if (_res < 0) { \
162 do { action /* */ ; } while(0); \
163 TRACE_ABORT(_res, level, "%s failed: %d", #fun, _res); \
164 } \
165}
166
167#define TRACE_CATCH(fun, fail) _TRACE_CATCH(ft_t_err, fun, fail)
168
169/* Abort the current function when signalled. This doesn't belong here,
170 * but rather into ftape-rw.h (maybe)
171 */
172#define FT_SIGNAL_EXIT(sig_mask) \
173 if (sigtestsetmask(&current->pending.signal, sig_mask)) { \
174 TRACE_ABORT(-EINTR, \
175 ft_t_warn, \
176 "interrupted by non-blockable signal"); \
177 }
178
179#endif /* _FTAPE_TRACING_H */
diff --git a/drivers/char/ftape/lowlevel/ftape-write.c b/drivers/char/ftape/lowlevel/ftape-write.c
deleted file mode 100644
index 45601ec801ee..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-write.c
+++ /dev/null
@@ -1,336 +0,0 @@
1/*
2 * Copyright (C) 1993-1995 Bas Laarhoven,
3 * (C) 1996-1997 Claus-Justus Heine.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to
17 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-write.c,v $
21 * $Revision: 1.3.4.1 $
22 * $Date: 1997/11/14 18:07:04 $
23 *
24 * This file contains the writing code
25 * for the QIC-117 floppy-tape driver for Linux.
26 */
27
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/mm.h>
31
32#include <linux/ftape.h>
33#include <linux/qic117.h>
34#include "../lowlevel/ftape-tracing.h"
35#include "../lowlevel/ftape-write.h"
36#include "../lowlevel/ftape-read.h"
37#include "../lowlevel/ftape-io.h"
38#include "../lowlevel/ftape-ctl.h"
39#include "../lowlevel/ftape-rw.h"
40#include "../lowlevel/ftape-ecc.h"
41#include "../lowlevel/ftape-bsm.h"
42#include "../lowlevel/fdc-isr.h"
43
44/* Global vars.
45 */
46
47/* Local vars.
48 */
49static int last_write_failed;
50
51void ftape_zap_write_buffers(void)
52{
53 int i;
54
55 for (i = 0; i < ft_nr_buffers; ++i) {
56 ft_buffer[i]->status = done;
57 }
58 ftape_reset_buffer();
59}
60
61static int copy_and_gen_ecc(void *destination,
62 const void *source,
63 const SectorMap bad_sector_map)
64{
65 int result;
66 struct memory_segment mseg;
67 int bads = count_ones(bad_sector_map);
68 TRACE_FUN(ft_t_any);
69
70 if (bads > 0) {
71 TRACE(ft_t_noise, "bad sectors in map: %d", bads);
72 }
73 if (bads + 3 >= FT_SECTORS_PER_SEGMENT) {
74 TRACE(ft_t_noise, "empty segment");
75 mseg.blocks = 0; /* skip entire segment */
76 result = 0; /* nothing written */
77 } else {
78 mseg.blocks = FT_SECTORS_PER_SEGMENT - bads;
79 mseg.data = destination;
80 memcpy(mseg.data, source, (mseg.blocks - 3) * FT_SECTOR_SIZE);
81 result = ftape_ecc_set_segment_parity(&mseg);
82 if (result < 0) {
83 TRACE(ft_t_err, "ecc_set_segment_parity failed");
84 } else {
85 result = (mseg.blocks - 3) * FT_SECTOR_SIZE;
86 }
87 }
88 TRACE_EXIT result;
89}
90
91
92int ftape_start_writing(const ft_write_mode_t mode)
93{
94 buffer_struct *head = ftape_get_buffer(ft_queue_head);
95 int segment_id = head->segment_id;
96 int result;
97 buffer_state_enum wanted_state = (mode == FT_WR_DELETE
98 ? deleting
99 : writing);
100 TRACE_FUN(ft_t_flow);
101
102 if ((ft_driver_state != wanted_state) || head->status != waiting) {
103 TRACE_EXIT 0;
104 }
105 ftape_setup_new_segment(head, segment_id, 1);
106 if (mode == FT_WR_SINGLE) {
107 /* stop tape instead of pause */
108 head->next_segment = 0;
109 }
110 ftape_calc_next_cluster(head); /* prepare */
111 head->status = ft_driver_state; /* either writing or deleting */
112 if (ft_runner_status == idle) {
113 TRACE(ft_t_noise,
114 "starting runner for segment %d", segment_id);
115 TRACE_CATCH(ftape_start_tape(segment_id,head->sector_offset),);
116 } else {
117 TRACE(ft_t_noise, "runner not idle, not starting tape");
118 }
119 /* go */
120 result = fdc_setup_read_write(head, (mode == FT_WR_DELETE
121 ? FDC_WRITE_DELETED : FDC_WRITE));
122 ftape_set_state(wanted_state); /* should not be necessary */
123 TRACE_EXIT result;
124}
125
126/* Wait until all data is actually written to tape.
127 *
128 * There is a problem: when the tape runs into logical EOT, then this
129 * failes. We need to restart the runner in this case.
130 */
131int ftape_loop_until_writes_done(void)
132{
133 buffer_struct *head;
134 TRACE_FUN(ft_t_flow);
135
136 while ((ft_driver_state == writing || ft_driver_state == deleting) &&
137 ftape_get_buffer(ft_queue_head)->status != done) {
138 /* set the runner status to idle if at lEOT */
139 TRACE_CATCH(ftape_handle_logical_eot(), last_write_failed = 1);
140 /* restart the tape if necessary */
141 if (ft_runner_status == idle) {
142 TRACE(ft_t_noise, "runner is idle, restarting");
143 if (ft_driver_state == deleting) {
144 TRACE_CATCH(ftape_start_writing(FT_WR_DELETE),
145 last_write_failed = 1);
146 } else {
147 TRACE_CATCH(ftape_start_writing(FT_WR_MULTI),
148 last_write_failed = 1);
149 }
150 }
151 TRACE(ft_t_noise, "tail: %d, head: %d",
152 ftape_buffer_id(ft_queue_tail),
153 ftape_buffer_id(ft_queue_head));
154 TRACE_CATCH(fdc_interrupt_wait(5 * FT_SECOND),
155 last_write_failed = 1);
156 head = ftape_get_buffer(ft_queue_head);
157 if (head->status == error) {
158 /* Allow escape from loop when signaled !
159 */
160 FT_SIGNAL_EXIT(_DONT_BLOCK);
161 if (head->hard_error_map != 0) {
162 /* Implement hard write error recovery here
163 */
164 }
165 /* retry this one */
166 head->status = waiting;
167 if (ft_runner_status == aborting) {
168 ftape_dumb_stop();
169 }
170 if (ft_runner_status != idle) {
171 TRACE_ABORT(-EIO, ft_t_err,
172 "unexpected state: "
173 "ft_runner_status != idle");
174 }
175 ftape_start_writing(ft_driver_state == deleting
176 ? FT_WR_MULTI : FT_WR_DELETE);
177 }
178 TRACE(ft_t_noise, "looping until writes done");
179 }
180 ftape_set_state(idle);
181 TRACE_EXIT 0;
182}
183
184/* Write given segment from buffer at address to tape.
185 */
186static int write_segment(const int segment_id,
187 const void *address,
188 const ft_write_mode_t write_mode)
189{
190 int bytes_written = 0;
191 buffer_struct *tail;
192 buffer_state_enum wanted_state = (write_mode == FT_WR_DELETE
193 ? deleting : writing);
194 TRACE_FUN(ft_t_flow);
195
196 TRACE(ft_t_noise, "segment_id = %d", segment_id);
197 if (ft_driver_state != wanted_state) {
198 if (ft_driver_state == deleting ||
199 wanted_state == deleting) {
200 TRACE_CATCH(ftape_loop_until_writes_done(),);
201 }
202 TRACE(ft_t_noise, "calling ftape_abort_operation");
203 TRACE_CATCH(ftape_abort_operation(),);
204 ftape_zap_write_buffers();
205 ftape_set_state(wanted_state);
206 }
207 /* if all buffers full we'll have to wait...
208 */
209 ftape_wait_segment(wanted_state);
210 tail = ftape_get_buffer(ft_queue_tail);
211 switch(tail->status) {
212 case done:
213 ft_history.defects += count_ones(tail->hard_error_map);
214 break;
215 case waiting:
216 /* this could happen with multiple EMPTY_SEGMENTs, but
217 * shouldn't happen any more as we re-start the runner even
218 * with an empty segment.
219 */
220 bytes_written = -EAGAIN;
221 break;
222 case error:
223 /* setup for a retry
224 */
225 tail->status = waiting;
226 bytes_written = -EAGAIN; /* force retry */
227 if (tail->hard_error_map != 0) {
228 TRACE(ft_t_warn,
229 "warning: %d hard error(s) in written segment",
230 count_ones(tail->hard_error_map));
231 TRACE(ft_t_noise, "hard_error_map = 0x%08lx",
232 (long)tail->hard_error_map);
233 /* Implement hard write error recovery here
234 */
235 }
236 break;
237 default:
238 TRACE_ABORT(-EIO, ft_t_err,
239 "wait for empty segment failed, tail status: %d",
240 tail->status);
241 }
242 /* should runner stop ?
243 */
244 if (ft_runner_status == aborting) {
245 buffer_struct *head = ftape_get_buffer(ft_queue_head);
246 if (head->status == wanted_state) {
247 head->status = done; /* ???? */
248 }
249 /* don't call abort_operation(), we don't want to zap
250 * the dma buffers
251 */
252 TRACE_CATCH(ftape_dumb_stop(),);
253 } else {
254 /* If just passed last segment on tape: wait for BOT
255 * or EOT mark. Sets ft_runner_status to idle if at lEOT
256 * and successful
257 */
258 TRACE_CATCH(ftape_handle_logical_eot(),);
259 }
260 if (tail->status == done) {
261 /* now at least one buffer is empty, fill it with our
262 * data. skip bad sectors and generate ecc.
263 * copy_and_gen_ecc return nr of bytes written, range
264 * 0..29 Kb inclusive!
265 *
266 * Empty segments are handled inside coyp_and_gen_ecc()
267 */
268 if (write_mode != FT_WR_DELETE) {
269 TRACE_CATCH(bytes_written = copy_and_gen_ecc(
270 tail->address, address,
271 ftape_get_bad_sector_entry(segment_id)),);
272 }
273 tail->segment_id = segment_id;
274 tail->status = waiting;
275 tail = ftape_next_buffer(ft_queue_tail);
276 }
277 /* Start tape only if all buffers full or flush mode.
278 * This will give higher probability of streaming.
279 */
280 if (ft_runner_status != running &&
281 ((tail->status == waiting &&
282 ftape_get_buffer(ft_queue_head) == tail) ||
283 write_mode != FT_WR_ASYNC)) {
284 TRACE_CATCH(ftape_start_writing(write_mode),);
285 }
286 TRACE_EXIT bytes_written;
287}
288
289/* Write as much as fits from buffer to the given segment on tape
290 * and handle retries.
291 * Return the number of bytes written (>= 0), or:
292 * -EIO write failed
293 * -EINTR interrupted by signal
294 * -ENOSPC device full
295 */
296int ftape_write_segment(const int segment_id,
297 const void *buffer,
298 const ft_write_mode_t flush)
299{
300 int retry = 0;
301 int result;
302 TRACE_FUN(ft_t_flow);
303
304 ft_history.used |= 2;
305 if (segment_id >= ft_tracks_per_tape*ft_segments_per_track) {
306 /* tape full */
307 TRACE_ABORT(-ENOSPC, ft_t_err,
308 "invalid segment id: %d (max %d)",
309 segment_id,
310 ft_tracks_per_tape * ft_segments_per_track -1);
311 }
312 for (;;) {
313 if ((result = write_segment(segment_id, buffer, flush)) >= 0) {
314 if (result == 0) { /* empty segment */
315 TRACE(ft_t_noise,
316 "empty segment, nothing written");
317 }
318 TRACE_EXIT result;
319 }
320 if (result == -EAGAIN) {
321 if (++retry > 100) { /* give up */
322 TRACE_ABORT(-EIO, ft_t_err,
323 "write failed, >100 retries in segment");
324 }
325 TRACE(ft_t_warn, "write error, retry %d (%d)",
326 retry,
327 ftape_get_buffer(ft_queue_tail)->segment_id);
328 } else {
329 TRACE_ABORT(result, ft_t_err,
330 "write_segment failed, error: %d", result);
331 }
332 /* Allow escape from loop when signaled !
333 */
334 FT_SIGNAL_EXIT(_DONT_BLOCK);
335 }
336}
diff --git a/drivers/char/ftape/lowlevel/ftape-write.h b/drivers/char/ftape/lowlevel/ftape-write.h
deleted file mode 100644
index 0e7f898b7af9..000000000000
--- a/drivers/char/ftape/lowlevel/ftape-write.h
+++ /dev/null
@@ -1,53 +0,0 @@
1#ifndef _FTAPE_WRITE_H
2#define _FTAPE_WRITE_H
3
4/*
5 * Copyright (C) 1994-1995 Bas Laarhoven,
6 * (C) 1996-1997 Claus-Justus Heine.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape-write.h,v $
24 $Author: claus $
25 *
26 $Revision: 1.2 $
27 $Date: 1997/10/05 19:18:30 $
28 $State: Exp $
29 *
30 * This file contains the definitions for the write functions
31 * for the QIC-117 floppy-tape driver for Linux.
32 *
33 */
34
35
36/* ftape-write.c defined global functions.
37 */
38typedef enum {
39 FT_WR_ASYNC = 0, /* start tape only when all buffers are full */
40 FT_WR_MULTI = 1, /* start tape, but don't necessarily stop */
41 FT_WR_SINGLE = 2, /* write a single segment and stop afterwards */
42 FT_WR_DELETE = 3 /* write deleted data marks */
43} ft_write_mode_t;
44
45extern int ftape_start_writing(const ft_write_mode_t mode);
46extern int ftape_write_segment(const int segment,
47 const void *address,
48 const ft_write_mode_t flushing);
49extern void ftape_zap_write_buffers(void);
50extern int ftape_loop_until_writes_done(void);
51
52#endif /* _FTAPE_WRITE_H */
53
diff --git a/drivers/char/ftape/lowlevel/ftape_syms.c b/drivers/char/ftape/lowlevel/ftape_syms.c
deleted file mode 100644
index 8e0dc4a07ca6..000000000000
--- a/drivers/char/ftape/lowlevel/ftape_syms.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Copyright (C) 1996-1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/ftape_syms.c,v $
20 * $Revision: 1.4 $
21 * $Date: 1997/10/17 00:03:51 $
22 *
23 * This file contains the symbols that the ftape low level
24 * part of the QIC-40/80/3010/3020 floppy-tape driver "ftape"
25 * exports to its high level clients
26 */
27
28#include <linux/module.h>
29
30#include <linux/ftape.h>
31#include "../lowlevel/ftape-tracing.h"
32#include "../lowlevel/ftape-init.h"
33#include "../lowlevel/fdc-io.h"
34#include "../lowlevel/ftape-read.h"
35#include "../lowlevel/ftape-write.h"
36#include "../lowlevel/ftape-io.h"
37#include "../lowlevel/ftape-ctl.h"
38#include "../lowlevel/ftape-rw.h"
39#include "../lowlevel/ftape-bsm.h"
40#include "../lowlevel/ftape-buffer.h"
41#include "../lowlevel/ftape-format.h"
42
43/* bad sector handling from ftape-bsm.c */
44EXPORT_SYMBOL(ftape_get_bad_sector_entry);
45EXPORT_SYMBOL(ftape_find_end_of_bsm_list);
46/* from ftape-rw.c */
47EXPORT_SYMBOL(ftape_set_state);
48/* from ftape-ctl.c */
49EXPORT_SYMBOL(ftape_seek_to_bot);
50EXPORT_SYMBOL(ftape_seek_to_eot);
51EXPORT_SYMBOL(ftape_abort_operation);
52EXPORT_SYMBOL(ftape_get_status);
53EXPORT_SYMBOL(ftape_enable);
54EXPORT_SYMBOL(ftape_disable);
55EXPORT_SYMBOL(ftape_mmap);
56EXPORT_SYMBOL(ftape_calibrate_data_rate);
57/* from ftape-io.c */
58EXPORT_SYMBOL(ftape_reset_drive);
59EXPORT_SYMBOL(ftape_command);
60EXPORT_SYMBOL(ftape_parameter);
61EXPORT_SYMBOL(ftape_ready_wait);
62EXPORT_SYMBOL(ftape_report_operation);
63EXPORT_SYMBOL(ftape_report_error);
64/* from ftape-read.c */
65EXPORT_SYMBOL(ftape_read_segment_fraction);
66EXPORT_SYMBOL(ftape_zap_read_buffers);
67EXPORT_SYMBOL(ftape_read_header_segment);
68EXPORT_SYMBOL(ftape_decode_header_segment);
69/* from ftape-write.c */
70EXPORT_SYMBOL(ftape_write_segment);
71EXPORT_SYMBOL(ftape_start_writing);
72EXPORT_SYMBOL(ftape_loop_until_writes_done);
73/* from ftape-buffer.h */
74EXPORT_SYMBOL(ftape_set_nr_buffers);
75/* from ftape-format.h */
76EXPORT_SYMBOL(ftape_format_track);
77EXPORT_SYMBOL(ftape_format_status);
78EXPORT_SYMBOL(ftape_verify_segment);
79/* from tracing.c */
80#ifndef CONFIG_FT_NO_TRACE_AT_ALL
81EXPORT_SYMBOL(ftape_tracing);
82EXPORT_SYMBOL(ftape_function_nest_level);
83EXPORT_SYMBOL(ftape_trace_call);
84EXPORT_SYMBOL(ftape_trace_exit);
85EXPORT_SYMBOL(ftape_trace_log);
86#endif
87
diff --git a/drivers/char/ftape/zftape/Makefile b/drivers/char/ftape/zftape/Makefile
deleted file mode 100644
index 6d91c1f77c05..000000000000
--- a/drivers/char/ftape/zftape/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
1#
2# Copyright (C) 1996, 1997 Claus-Justus Heine.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2, or (at your option)
7# any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; see the file COPYING. If not, write to
16# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17#
18# $Source: /homes/cvs/ftape-stacked/ftape/zftape/Makefile,v $
19# $Revision: 1.4 $
20# $Date: 1997/10/05 19:18:58 $
21#
22# Makefile for the QIC-40/80/3010/3020 zftape interface VFS to
23# ftape
24#
25
26
27# ZFT_OBSOLETE - enable the MTIOC_ZFTAPE_GETBLKSZ ioctl. You should
28# leave this enabled for compatibility with taper.
29
30obj-$(CONFIG_ZFTAPE) += zftape.o
31
32zftape-objs := zftape-rw.o zftape-ctl.o zftape-read.o \
33 zftape-write.o zftape-vtbl.o zftape-eof.o \
34 zftape-init.o zftape-buffers.o zftape_syms.o
35
36EXTRA_CFLAGS := -DZFT_OBSOLETE
diff --git a/drivers/char/ftape/zftape/zftape-buffers.c b/drivers/char/ftape/zftape/zftape-buffers.c
deleted file mode 100644
index 7ebce2ec7897..000000000000
--- a/drivers/char/ftape/zftape/zftape-buffers.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Copyright (C) 1995-1997 Claus-Justus Heine.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-buffers.c,v $
20 * $Revision: 1.2 $
21 * $Date: 1997/10/05 19:18:59 $
22 *
23 * This file contains the dynamic buffer allocation routines
24 * of zftape
25 */
26
27#include <linux/errno.h>
28#include <linux/mm.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31
32#include <linux/zftape.h>
33
34#include <linux/vmalloc.h>
35
36#include "../zftape/zftape-init.h"
37#include "../zftape/zftape-eof.h"
38#include "../zftape/zftape-ctl.h"
39#include "../zftape/zftape-write.h"
40#include "../zftape/zftape-read.h"
41#include "../zftape/zftape-rw.h"
42#include "../zftape/zftape-vtbl.h"
43
44/* global variables
45 */
46
47/* local varibales
48 */
49static unsigned int used_memory;
50static unsigned int peak_memory;
51
52void zft_memory_stats(void)
53{
54 TRACE_FUN(ft_t_flow);
55
56 TRACE(ft_t_noise, "Memory usage (vmalloc allocations):\n"
57 KERN_INFO "total allocated: %d\n"
58 KERN_INFO "peak allocation: %d",
59 used_memory, peak_memory);
60 peak_memory = used_memory;
61 TRACE_EXIT;
62}
63
64int zft_vcalloc_once(void *new, size_t size)
65{
66 TRACE_FUN(ft_t_flow);
67 if (zft_vmalloc_once(new, size) < 0) {
68 TRACE_EXIT -ENOMEM;
69 }
70 memset(*(void **)new, '\0', size);
71 TRACE_EXIT 0;
72}
73int zft_vmalloc_once(void *new, size_t size)
74{
75 TRACE_FUN(ft_t_flow);
76
77 if (*(void **)new != NULL || size == 0) {
78 TRACE_EXIT 0;
79 }
80 if ((*(void **)new = vmalloc(size)) == NULL) {
81 TRACE_EXIT -ENOMEM;
82 }
83 used_memory += size;
84 if (peak_memory < used_memory) {
85 peak_memory = used_memory;
86 }
87 TRACE_ABORT(0, ft_t_noise,
88 "allocated buffer @ %p, %zd bytes", *(void **)new, size);
89}
90int zft_vmalloc_always(void *new, size_t size)
91{
92 TRACE_FUN(ft_t_flow);
93
94 zft_vfree(new, size);
95 TRACE_EXIT zft_vmalloc_once(new, size);
96}
97void zft_vfree(void *old, size_t size)
98{
99 TRACE_FUN(ft_t_flow);
100
101 if (*(void **)old) {
102 vfree(*(void **)old);
103 used_memory -= size;
104 TRACE(ft_t_noise, "released buffer @ %p, %zd bytes",
105 *(void **)old, size);
106 *(void **)old = NULL;
107 }
108 TRACE_EXIT;
109}
110
111void *zft_kmalloc(size_t size)
112{
113 void *new;
114
115 while ((new = kmalloc(size, GFP_KERNEL)) == NULL) {
116 msleep_interruptible(100);
117 }
118 memset(new, 0, size);
119 used_memory += size;
120 if (peak_memory < used_memory) {
121 peak_memory = used_memory;
122 }
123 return new;
124}
125
126void zft_kfree(void *old, size_t size)
127{
128 kfree(old);
129 used_memory -= size;
130}
131
132/* there are some more buffers that are allocated on demand.
133 * cleanup_module() calles this function to be sure to have released
134 * them
135 */
136void zft_uninit_mem(void)
137{
138 TRACE_FUN(ft_t_flow);
139
140 zft_vfree(&zft_hseg_buf, FT_SEGMENT_SIZE);
141 zft_vfree(&zft_deblock_buf, FT_SEGMENT_SIZE); zft_deblock_segment = -1;
142 zft_free_vtbl();
143 if (zft_cmpr_lock(0 /* don't load */) == 0) {
144 (*zft_cmpr_ops->cleanup)();
145 (*zft_cmpr_ops->reset)(); /* unlock it again */
146 }
147 zft_memory_stats();
148 TRACE_EXIT;
149}
diff --git a/drivers/char/ftape/zftape/zftape-buffers.h b/drivers/char/ftape/zftape/zftape-buffers.h
deleted file mode 100644
index 798e3128c682..000000000000
--- a/drivers/char/ftape/zftape/zftape-buffers.h
+++ /dev/null
@@ -1,55 +0,0 @@
1#ifndef _FTAPE_DYNMEM_H
2#define _FTAPE_DYNMEM_H
3
4/*
5 * Copyright (C) 1995-1997 Claus-Justus Heine.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-buffers.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:18:59 $
25 *
26 * memory allocation routines.
27 *
28 */
29
30/* we do not allocate all of the really large buffer memory before
31 * someone tries to open the drive. ftape_open() may fail with
32 * -ENOMEM, but that's better having 200k of vmalloced memory which
33 * cannot be swapped out.
34 */
35
36extern void zft_memory_stats(void);
37extern int zft_vmalloc_once(void *new, size_t size);
38extern int zft_vcalloc_once(void *new, size_t size);
39extern int zft_vmalloc_always(void *new, size_t size);
40extern void zft_vfree(void *old, size_t size);
41extern void *zft_kmalloc(size_t size);
42extern void zft_kfree(void *old, size_t size);
43
44/* called by cleanup_module()
45 */
46extern void zft_uninit_mem(void);
47
48#endif
49
50
51
52
53
54
55
diff --git a/drivers/char/ftape/zftape/zftape-ctl.c b/drivers/char/ftape/zftape/zftape-ctl.c
deleted file mode 100644
index 22ba0f5d00cf..000000000000
--- a/drivers/char/ftape/zftape/zftape-ctl.c
+++ /dev/null
@@ -1,1417 +0,0 @@
1/*
2 * Copyright (C) 1996, 1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-ctl.c,v $
20 * $Revision: 1.2.6.2 $
21 * $Date: 1997/11/14 18:07:33 $
22 *
23 * This file contains the non-read/write zftape functions
24 * for the QIC-40/80/3010/3020 floppy-tape driver for Linux.
25 */
26
27#include <linux/errno.h>
28#include <linux/mm.h>
29#include <linux/module.h>
30#include <linux/fcntl.h>
31
32#include <linux/zftape.h>
33
34#include <asm/uaccess.h>
35
36#include "../zftape/zftape-init.h"
37#include "../zftape/zftape-eof.h"
38#include "../zftape/zftape-ctl.h"
39#include "../zftape/zftape-write.h"
40#include "../zftape/zftape-read.h"
41#include "../zftape/zftape-rw.h"
42#include "../zftape/zftape-vtbl.h"
43
44/* Global vars.
45 */
46int zft_write_protected; /* this is when cartridge rdonly or O_RDONLY */
47int zft_header_read;
48int zft_offline;
49unsigned int zft_unit;
50int zft_resid;
51int zft_mt_compression;
52
53/* Local vars.
54 */
55static int going_offline;
56
57typedef int (mt_fun)(int *argptr);
58typedef int (*mt_funp)(int *argptr);
59typedef struct
60{
61 mt_funp function;
62 unsigned offline : 1; /* op permitted if offline or no_tape */
63 unsigned write_protected : 1; /* op permitted if write-protected */
64 unsigned not_formatted : 1; /* op permitted if tape not formatted */
65 unsigned raw_mode : 1; /* op permitted if zft_mode == 0 */
66 unsigned need_idle_state : 1; /* need to call def_idle_state */
67 char *name;
68} fun_entry;
69
70static mt_fun mt_dummy, mt_reset, mt_fsr, mt_bsr, mt_rew, mt_offl, mt_nop,
71 mt_weof, mt_erase, mt_ras2, mt_setblk, mt_setdensity,
72 mt_seek, mt_tell, mt_reten, mt_eom, mt_fsf, mt_bsf,
73 mt_fsfm, mt_bsfm, mt_setdrvbuffer, mt_compression;
74
75static fun_entry mt_funs[]=
76{
77 {mt_reset , 1, 1, 1, 1, 0, "MT_RESET" }, /* 0 */
78 {mt_fsf , 0, 1, 0, 0, 1, "MT_FSF" },
79 {mt_bsf , 0, 1, 0, 0, 1, "MT_BSF" },
80 {mt_fsr , 0, 1, 0, 1, 1, "MT_FSR" },
81 {mt_bsr , 0, 1, 0, 1, 1, "MT_BSR" },
82 {mt_weof , 0, 0, 0, 0, 0, "MT_WEOF" }, /* 5 */
83 {mt_rew , 0, 1, 1, 1, 0, "MT_REW" },
84 {mt_offl , 0, 1, 1, 1, 0, "MT_OFFL" },
85 {mt_nop , 1, 1, 1, 1, 0, "MT_NOP" },
86 {mt_reten , 0, 1, 1, 1, 0, "MT_RETEN" },
87 {mt_bsfm , 0, 1, 0, 0, 1, "MT_BSFM" }, /* 10 */
88 {mt_fsfm , 0, 1, 0, 0, 1, "MT_FSFM" },
89 {mt_eom , 0, 1, 0, 0, 1, "MT_EOM" },
90 {mt_erase , 0, 0, 0, 1, 0, "MT_ERASE" },
91 {mt_dummy , 1, 1, 1, 1, 0, "MT_RAS1" },
92 {mt_ras2 , 0, 0, 0, 1, 0, "MT_RAS2" },
93 {mt_dummy , 1, 1, 1, 1, 0, "MT_RAS3" },
94 {mt_dummy , 1, 1, 1, 1, 0, "UNKNOWN" },
95 {mt_dummy , 1, 1, 1, 1, 0, "UNKNOWN" },
96 {mt_dummy , 1, 1, 1, 1, 0, "UNKNOWN" },
97 {mt_setblk , 1, 1, 1, 1, 1, "MT_SETBLK"}, /* 20 */
98 {mt_setdensity , 1, 1, 1, 1, 0, "MT_SETDENSITY"},
99 {mt_seek , 0, 1, 0, 1, 1, "MT_SEEK" },
100 {mt_dummy , 0, 1, 0, 1, 1, "MT_TELL" }, /* wr-only ?! */
101 {mt_setdrvbuffer, 1, 1, 1, 1, 0, "MT_SETDRVBUFFER" },
102 {mt_dummy , 1, 1, 1, 1, 0, "MT_FSS" }, /* 25 */
103 {mt_dummy , 1, 1, 1, 1, 0, "MT_BSS" },
104 {mt_dummy , 1, 1, 1, 1, 0, "MT_WSM" },
105 {mt_dummy , 1, 1, 1, 1, 0, "MT_LOCK" },
106 {mt_dummy , 1, 1, 1, 1, 0, "MT_UNLOCK"},
107 {mt_dummy , 1, 1, 1, 1, 0, "MT_LOAD" }, /* 30 */
108 {mt_dummy , 1, 1, 1, 1, 0, "MT_UNLOAD"},
109 {mt_compression , 1, 1, 1, 0, 1, "MT_COMPRESSION"},
110 {mt_dummy , 1, 1, 1, 1, 0, "MT_SETPART"},
111 {mt_dummy , 1, 1, 1, 1, 0, "MT_MKPART"}
112};
113
114#define NR_MT_CMDS NR_ITEMS(mt_funs)
115
116void zft_reset_position(zft_position *pos)
117{
118 TRACE_FUN(ft_t_flow);
119
120 pos->seg_byte_pos =
121 pos->volume_pos = 0;
122 if (zft_header_read) {
123 /* need to keep track of the volume table and
124 * compression map. We therefor simply
125 * position at the beginning of the first
126 * volume. This covers old ftape archives as
127 * well has various flavours of the
128 * compression map segments. The worst case is
129 * that the compression map shows up as a
130 * additional volume in front of all others.
131 */
132 pos->seg_pos = zft_find_volume(0)->start_seg;
133 pos->tape_pos = zft_calc_tape_pos(pos->seg_pos);
134 } else {
135 pos->tape_pos = 0;
136 pos->seg_pos = -1;
137 }
138 zft_just_before_eof = 0;
139 zft_deblock_segment = -1;
140 zft_io_state = zft_idle;
141 zft_zap_read_buffers();
142 zft_prevent_flush();
143 /* unlock the compresison module if it is loaded.
144 * The zero arg means not to try to load the module.
145 */
146 if (zft_cmpr_lock(0) == 0) {
147 (*zft_cmpr_ops->reset)(); /* unlock */
148 }
149 TRACE_EXIT;
150}
151
152static void zft_init_driver(void)
153{
154 TRACE_FUN(ft_t_flow);
155
156 zft_resid =
157 zft_header_read =
158 zft_old_ftape =
159 zft_offline =
160 zft_write_protected =
161 going_offline =
162 zft_mt_compression =
163 zft_header_changed =
164 zft_volume_table_changed =
165 zft_written_segments = 0;
166 zft_blk_sz = CONFIG_ZFT_DFLT_BLK_SZ;
167 zft_reset_position(&zft_pos); /* does most of the stuff */
168 ftape_zap_read_buffers();
169 ftape_set_state(idle);
170 TRACE_EXIT;
171}
172
173int zft_def_idle_state(void)
174{
175 int result = 0;
176 TRACE_FUN(ft_t_flow);
177
178 if (!zft_header_read) {
179 result = zft_read_header_segments();
180 } else if ((result = zft_flush_buffers()) >= 0 && zft_qic_mode) {
181 /* don't move past eof
182 */
183 (void)zft_close_volume(&zft_pos);
184 }
185 if (ftape_abort_operation() < 0) {
186 TRACE(ft_t_warn, "ftape_abort_operation() failed");
187 result = -EIO;
188 }
189 /* clear remaining read buffers */
190 zft_zap_read_buffers();
191 zft_io_state = zft_idle;
192 TRACE_EXIT result;
193}
194
195/*****************************************************************************
196 * *
197 * functions for the MTIOCTOP commands *
198 * *
199 *****************************************************************************/
200
201static int mt_dummy(int *dummy)
202{
203 TRACE_FUN(ft_t_flow);
204
205 TRACE_EXIT -ENOSYS;
206}
207
208static int mt_reset(int *dummy)
209{
210 TRACE_FUN(ft_t_flow);
211
212 (void)ftape_seek_to_bot();
213 TRACE_CATCH(ftape_reset_drive(),
214 zft_init_driver(); zft_uninit_mem(); zft_offline = 1);
215 /* fake a re-open of the device. This will set all flage and
216 * allocate buffers as appropriate. The new tape condition will
217 * force the open routine to do anything we need.
218 */
219 TRACE_CATCH(_zft_open(-1 /* fake reopen */, 0 /* dummy */),);
220 TRACE_EXIT 0;
221}
222
223static int mt_fsf(int *arg)
224{
225 int result;
226 TRACE_FUN(ft_t_flow);
227
228 result = zft_skip_volumes(*arg, &zft_pos);
229 zft_just_before_eof = 0;
230 TRACE_EXIT result;
231}
232
233static int mt_bsf(int *arg)
234{
235 int result = 0;
236 TRACE_FUN(ft_t_flow);
237
238 if (*arg != 0) {
239 result = zft_skip_volumes(-*arg + 1, &zft_pos);
240 }
241 TRACE_EXIT result;
242}
243
244static int seek_block(__s64 data_offset,
245 __s64 block_increment,
246 zft_position *pos)
247{
248 int result = 0;
249 __s64 new_block_pos;
250 __s64 vol_block_count;
251 const zft_volinfo *volume;
252 int exceed;
253 TRACE_FUN(ft_t_flow);
254
255 volume = zft_find_volume(pos->seg_pos);
256 if (volume->start_seg == 0 || volume->end_seg == 0) {
257 TRACE_EXIT -EIO;
258 }
259 new_block_pos = (zft_div_blksz(data_offset, volume->blk_sz)
260 + block_increment);
261 vol_block_count = zft_div_blksz(volume->size, volume->blk_sz);
262 if (new_block_pos < 0) {
263 TRACE(ft_t_noise,
264 "new_block_pos " LL_X " < 0", LL(new_block_pos));
265 zft_resid = (int)new_block_pos;
266 new_block_pos = 0;
267 exceed = 1;
268 } else if (new_block_pos > vol_block_count) {
269 TRACE(ft_t_noise,
270 "new_block_pos " LL_X " exceeds size of volume " LL_X,
271 LL(new_block_pos), LL(vol_block_count));
272 zft_resid = (int)(vol_block_count - new_block_pos);
273 new_block_pos = vol_block_count;
274 exceed = 1;
275 } else {
276 exceed = 0;
277 }
278 if (zft_use_compression && volume->use_compression) {
279 TRACE_CATCH(zft_cmpr_lock(1 /* try to load */),);
280 result = (*zft_cmpr_ops->seek)(new_block_pos, pos, volume,
281 zft_deblock_buf);
282 pos->tape_pos = zft_calc_tape_pos(pos->seg_pos);
283 pos->tape_pos += pos->seg_byte_pos;
284 } else {
285 pos->volume_pos = zft_mul_blksz(new_block_pos, volume->blk_sz);
286 pos->tape_pos = zft_calc_tape_pos(volume->start_seg);
287 pos->tape_pos += pos->volume_pos;
288 pos->seg_pos = zft_calc_seg_byte_coord(&pos->seg_byte_pos,
289 pos->tape_pos);
290 }
291 zft_just_before_eof = volume->size == pos->volume_pos;
292 if (zft_just_before_eof) {
293 /* why this? because zft_file_no checks agains start
294 * and end segment of a volume. We do not want to
295 * advance to the next volume with this function.
296 */
297 TRACE(ft_t_noise, "set zft_just_before_eof");
298 zft_position_before_eof(pos, volume);
299 }
300 TRACE(ft_t_noise, "\n"
301 KERN_INFO "new_seg_pos : %d\n"
302 KERN_INFO "new_tape_pos: " LL_X "\n"
303 KERN_INFO "vol_size : " LL_X "\n"
304 KERN_INFO "seg_byte_pos: %d\n"
305 KERN_INFO "blk_sz : %d",
306 pos->seg_pos, LL(pos->tape_pos),
307 LL(volume->size), pos->seg_byte_pos,
308 volume->blk_sz);
309 if (!exceed) {
310 zft_resid = new_block_pos - zft_div_blksz(pos->volume_pos,
311 volume->blk_sz);
312 }
313 if (zft_resid < 0) {
314 zft_resid = -zft_resid;
315 }
316 TRACE_EXIT ((exceed || zft_resid != 0) && result >= 0) ? -EINVAL : result;
317}
318
319static int mt_fsr(int *arg)
320{
321 int result;
322 TRACE_FUN(ft_t_flow);
323
324 result = seek_block(zft_pos.volume_pos, *arg, &zft_pos);
325 TRACE_EXIT result;
326}
327
328static int mt_bsr(int *arg)
329{
330 int result;
331 TRACE_FUN(ft_t_flow);
332
333 result = seek_block(zft_pos.volume_pos, -*arg, &zft_pos);
334 TRACE_EXIT result;
335}
336
337static int mt_weof(int *arg)
338{
339 int result;
340 TRACE_FUN(ft_t_flow);
341
342 TRACE_CATCH(zft_flush_buffers(),);
343 result = zft_weof(*arg, &zft_pos);
344 TRACE_EXIT result;
345}
346
347static int mt_rew(int *dummy)
348{
349 int result;
350 TRACE_FUN(ft_t_flow);
351
352 if(zft_header_read) {
353 (void)zft_def_idle_state();
354 }
355 result = ftape_seek_to_bot();
356 zft_reset_position(&zft_pos);
357 TRACE_EXIT result;
358}
359
360static int mt_offl(int *dummy)
361{
362 int result;
363 TRACE_FUN(ft_t_flow);
364
365 going_offline= 1;
366 result = mt_rew(NULL);
367 TRACE_EXIT result;
368}
369
370static int mt_nop(int *dummy)
371{
372 TRACE_FUN(ft_t_flow);
373 /* should we set tape status?
374 */
375 if (!zft_offline) { /* offline includes no_tape */
376 (void)zft_def_idle_state();
377 }
378 TRACE_EXIT 0;
379}
380
381static int mt_reten(int *dummy)
382{
383 int result;
384 TRACE_FUN(ft_t_flow);
385
386 if(zft_header_read) {
387 (void)zft_def_idle_state();
388 }
389 result = ftape_seek_to_eot();
390 if (result >= 0) {
391 result = ftape_seek_to_bot();
392 }
393 TRACE_EXIT(result);
394}
395
396static int fsfbsfm(int arg, zft_position *pos)
397{
398 const zft_volinfo *vtbl;
399 __s64 block_pos;
400 TRACE_FUN(ft_t_flow);
401
402 /* What to do? This should seek to the next file-mark and
403 * position BEFORE. That is, a next write would just extend
404 * the current file. Well. Let's just seek to the end of the
405 * current file, if count == 1. If count > 1, then do a
406 * "mt_fsf(count - 1)", and then seek to the end of that file.
407 * If count == 0, do nothing
408 */
409 if (arg == 0) {
410 TRACE_EXIT 0;
411 }
412 zft_just_before_eof = 0;
413 TRACE_CATCH(zft_skip_volumes(arg < 0 ? arg : arg-1, pos),
414 if (arg > 0) {
415 zft_resid ++;
416 });
417 vtbl = zft_find_volume(pos->seg_pos);
418 block_pos = zft_div_blksz(vtbl->size, vtbl->blk_sz);
419 (void)seek_block(0, block_pos, pos);
420 if (pos->volume_pos != vtbl->size) {
421 zft_just_before_eof = 0;
422 zft_resid = 1;
423 /* we didn't managed to go there */
424 TRACE_ABORT(-EIO, ft_t_err,
425 "wanted file position " LL_X ", arrived at " LL_X,
426 LL(vtbl->size), LL(pos->volume_pos));
427 }
428 zft_just_before_eof = 1;
429 TRACE_EXIT 0;
430}
431
432static int mt_bsfm(int *arg)
433{
434 int result;
435 TRACE_FUN(ft_t_flow);
436
437 result = fsfbsfm(-*arg, &zft_pos);
438 TRACE_EXIT result;
439}
440
441static int mt_fsfm(int *arg)
442{
443 int result;
444 TRACE_FUN(ft_t_flow);
445
446 result = fsfbsfm(*arg, &zft_pos);
447 TRACE_EXIT result;
448}
449
450static int mt_eom(int *dummy)
451{
452 TRACE_FUN(ft_t_flow);
453
454 zft_skip_to_eom(&zft_pos);
455 TRACE_EXIT 0;
456}
457
458static int mt_erase(int *dummy)
459{
460 int result;
461 TRACE_FUN(ft_t_flow);
462
463 result = zft_erase();
464 TRACE_EXIT result;
465}
466
467static int mt_ras2(int *dummy)
468{
469 int result;
470 TRACE_FUN(ft_t_flow);
471
472 result = -ENOSYS;
473 TRACE_EXIT result;
474}
475
476/* Sets the new blocksize in BYTES
477 *
478 */
479static int mt_setblk(int *new_size)
480{
481 TRACE_FUN(ft_t_flow);
482
483 if((unsigned int)(*new_size) > ZFT_MAX_BLK_SZ) {
484 TRACE_ABORT(-EINVAL, ft_t_info,
485 "desired blk_sz (%d) should be <= %d bytes",
486 *new_size, ZFT_MAX_BLK_SZ);
487 }
488 if ((*new_size & (FT_SECTOR_SIZE-1)) != 0) {
489 TRACE_ABORT(-EINVAL, ft_t_info,
490 "desired blk_sz (%d) must be a multiple of %d bytes",
491 *new_size, FT_SECTOR_SIZE);
492 }
493 if (*new_size == 0) {
494 if (zft_use_compression) {
495 TRACE_ABORT(-EINVAL, ft_t_info,
496 "Variable block size not yet "
497 "supported with compression");
498 }
499 *new_size = 1;
500 }
501 zft_blk_sz = *new_size;
502 TRACE_EXIT 0;
503}
504
505static int mt_setdensity(int *arg)
506{
507 TRACE_FUN(ft_t_flow);
508
509 SET_TRACE_LEVEL(*arg);
510 TRACE(TRACE_LEVEL, "tracing set to %d", TRACE_LEVEL);
511 if ((int)TRACE_LEVEL != *arg) {
512 TRACE_EXIT -EINVAL;
513 }
514 TRACE_EXIT 0;
515}
516
517static int mt_seek(int *new_block_pos)
518{
519 int result= 0;
520 TRACE_FUN(ft_t_any);
521
522 result = seek_block(0, (__s64)*new_block_pos, &zft_pos);
523 TRACE_EXIT result;
524}
525
526/* OK, this is totally different from SCSI, but the worst thing that can
527 * happen is that there is not enough defragmentated memory that can be
528 * allocated. Also, there is a hardwired limit of 16 dma buffers in the
529 * stock ftape module. This shouldn't bring the system down.
530 *
531 * NOTE: the argument specifies the total number of dma buffers to use.
532 * The driver needs at least 3 buffers to function at all.
533 *
534 */
535static int mt_setdrvbuffer(int *cnt)
536{
537 TRACE_FUN(ft_t_flow);
538
539 if (*cnt < 3) {
540 TRACE_EXIT -EINVAL;
541 }
542 TRACE_CATCH(ftape_set_nr_buffers(*cnt),);
543 TRACE_EXIT 0;
544}
545/* return the block position from start of volume
546 */
547static int mt_tell(int *arg)
548{
549 TRACE_FUN(ft_t_flow);
550
551 *arg = zft_div_blksz(zft_pos.volume_pos,
552 zft_find_volume(zft_pos.seg_pos)->blk_sz);
553 TRACE_EXIT 0;
554}
555
556static int mt_compression(int *arg)
557{
558 TRACE_FUN(ft_t_flow);
559
560 /* Ok. We could also check whether compression is available at
561 * all by trying to load the compression module. We could
562 * also check for a block size of 1 byte which is illegal
563 * with compression. Instead of doing it here we rely on
564 * zftape_write() to do the proper checks.
565 */
566 if ((unsigned int)*arg > 1) {
567 TRACE_EXIT -EINVAL;
568 }
569 if (*arg != 0 && zft_blk_sz == 1) { /* variable block size */
570 TRACE_ABORT(-EINVAL, ft_t_info,
571 "Compression not yet supported "
572 "with variable block size");
573 }
574 zft_mt_compression = *arg;
575 if ((zft_unit & ZFT_ZIP_MODE) == 0) {
576 zft_use_compression = zft_mt_compression;
577 }
578 TRACE_EXIT 0;
579}
580
581/* check whether write access is allowed. Write access is denied when
582 * + zft_write_protected == 1 -- this accounts for either hard write
583 * protection of the cartridge or for
584 * O_RDONLY access mode of the tape device
585 * + zft_offline == 1 -- this meany that there is either no tape
586 * or that the MTOFFLINE ioctl has been
587 * previously issued (`soft eject')
588 * + ft_formatted == 0 -- this means that the cartridge is not
589 * formatted
590 * Then we distinuguish two cases. When zft_qic_mode is TRUE, then we try
591 * to emulate a `traditional' (aka SCSI like) UN*X tape device. Therefore we
592 * deny writes when
593 * + zft_qic_mode ==1 &&
594 * (!zft_tape_at_lbot() && -- tape no at logical BOT
595 * !(zft_tape_at_eom() || -- tape not at logical EOM (or EOD)
596 * (zft_tape_at_eom() &&
597 * zft_old_ftape()))) -- we can't add new volume to tapes
598 * written by old ftape because ftape
599 * don't use the volume table
600 *
601 * when the drive is in true raw mode (aka /dev/rawft0) then we don't
602 * care about LBOT and EOM conditions. This device is intended for a
603 * user level program that wants to truly implement the QIC-80 compliance
604 * at the logical data layout level of the cartridge, i.e. implement all
605 * that volume table and volume directory stuff etc.<
606 */
607int zft_check_write_access(zft_position *pos)
608{
609 TRACE_FUN(ft_t_flow);
610
611 if (zft_offline) { /* offline includes no_tape */
612 TRACE_ABORT(-ENXIO,
613 ft_t_info, "tape is offline or no cartridge");
614 }
615 if (!ft_formatted) {
616 TRACE_ABORT(-EACCES, ft_t_info, "tape is not formatted");
617 }
618 if (zft_write_protected) {
619 TRACE_ABORT(-EACCES, ft_t_info, "cartridge write protected");
620 }
621 if (zft_qic_mode) {
622 /* check BOT condition */
623 if (!zft_tape_at_lbot(pos)) {
624 /* protect cartridges written by old ftape if
625 * not at BOT because they use the vtbl
626 * segment for storing data
627 */
628 if (zft_old_ftape) {
629 TRACE_ABORT(-EACCES, ft_t_warn,
630 "Cannot write to cartridges written by old ftape when not at BOT");
631 }
632 /* not at BOT, but allow writes at EOD, of course
633 */
634 if (!zft_tape_at_eod(pos)) {
635 TRACE_ABORT(-EACCES, ft_t_info,
636 "tape not at BOT and not at EOD");
637 }
638 }
639 /* fine. Now the tape is either at BOT or at EOD. */
640 }
641 /* or in raw mode in which case we don't care about BOT and EOD */
642 TRACE_EXIT 0;
643}
644
645/* OPEN routine called by kernel-interface code
646 *
647 * NOTE: this is also called by mt_reset() with dev_minor == -1
648 * to fake a reopen after a reset.
649 */
650int _zft_open(unsigned int dev_minor, unsigned int access_mode)
651{
652 static unsigned int tape_unit;
653 static unsigned int file_access_mode;
654 int result;
655 TRACE_FUN(ft_t_flow);
656
657 if ((int)dev_minor == -1) {
658 /* fake reopen */
659 zft_unit = tape_unit;
660 access_mode = file_access_mode;
661 zft_init_driver(); /* reset all static data to defaults */
662 } else {
663 tape_unit = dev_minor;
664 file_access_mode = access_mode;
665 if ((result = ftape_enable(FTAPE_SEL(dev_minor))) < 0) {
666 TRACE_ABORT(-ENXIO, ft_t_err,
667 "ftape_enable failed: %d", result);
668 }
669 if (ft_new_tape || ft_no_tape || !ft_formatted ||
670 (FTAPE_SEL(zft_unit) != FTAPE_SEL(dev_minor)) ||
671 (zft_unit & ZFT_RAW_MODE) != (dev_minor & ZFT_RAW_MODE)) {
672 /* reset all static data to defaults,
673 */
674 zft_init_driver();
675 }
676 zft_unit = dev_minor;
677 }
678 zft_set_flags(zft_unit); /* decode the minor bits */
679 if (zft_blk_sz == 1 && zft_use_compression) {
680 ftape_disable(); /* resets ft_no_tape */
681 TRACE_ABORT(-ENODEV, ft_t_warn, "Variable block size not yet "
682 "supported with compression");
683 }
684 /* no need for most of the buffers when no tape or not
685 * formatted. for the read/write operations, it is the
686 * regardless whether there is no tape, a not-formatted tape
687 * or the whether the driver is soft offline.
688 * Nevertheless we allow some ioctls with non-formatted tapes,
689 * like rewind and reset.
690 */
691 if (ft_no_tape || !ft_formatted) {
692 zft_uninit_mem();
693 }
694 if (ft_no_tape) {
695 zft_offline = 1; /* so we need not test two variables */
696 }
697 if ((access_mode == O_WRONLY || access_mode == O_RDWR) &&
698 (ft_write_protected || ft_no_tape)) {
699 ftape_disable(); /* resets ft_no_tape */
700 TRACE_ABORT(ft_no_tape ? -ENXIO : -EROFS,
701 ft_t_warn, "wrong access mode %s cartridge",
702 ft_no_tape ? "without a" : "with write protected");
703 }
704 zft_write_protected = (access_mode == O_RDONLY ||
705 ft_write_protected != 0);
706 if (zft_write_protected) {
707 TRACE(ft_t_noise,
708 "read only access mode: %d, "
709 "drive write protected: %d",
710 access_mode == O_RDONLY,
711 ft_write_protected != 0);
712 }
713 if (!zft_offline) {
714 TRACE_CATCH(zft_vmalloc_once(&zft_deblock_buf,FT_SEGMENT_SIZE),
715 ftape_disable());
716 }
717 /* zft_seg_pos should be greater than the vtbl segpos but not
718 * if in compatibility mode and only after we read in the
719 * header segments
720 *
721 * might also be a problem if the user makes a backup with a
722 * *qft* device and rewinds it with a raw device.
723 */
724 if (zft_qic_mode &&
725 !zft_old_ftape &&
726 zft_pos.seg_pos >= 0 &&
727 zft_header_read &&
728 zft_pos.seg_pos <= ft_first_data_segment) {
729 TRACE(ft_t_noise, "you probably mixed up the zftape devices!");
730 zft_reset_position(&zft_pos);
731 }
732 TRACE_EXIT 0;
733}
734
735/* RELEASE routine called by kernel-interface code
736 */
737int _zft_close(void)
738{
739 int result = 0;
740 TRACE_FUN(ft_t_flow);
741
742 if (zft_offline) {
743 /* call the hardware release routine. Puts the drive offline */
744 ftape_disable();
745 TRACE_EXIT 0;
746 }
747 if (!(ft_write_protected || zft_old_ftape)) {
748 result = zft_flush_buffers();
749 TRACE(ft_t_noise, "writing file mark at current position");
750 if (zft_qic_mode && zft_close_volume(&zft_pos) == 0) {
751 zft_move_past_eof(&zft_pos);
752 }
753 if ((zft_tape_at_lbot(&zft_pos) ||
754 !(zft_unit & FTAPE_NO_REWIND))) {
755 if (result >= 0) {
756 result = zft_update_header_segments();
757 } else {
758 TRACE(ft_t_err,
759 "Error: unable to update header segments");
760 }
761 }
762 }
763 ftape_abort_operation();
764 if (!(zft_unit & FTAPE_NO_REWIND)) {
765 TRACE(ft_t_noise, "rewinding tape");
766 if (ftape_seek_to_bot() < 0 && result >= 0) {
767 result = -EIO; /* keep old value */
768 }
769 zft_reset_position(&zft_pos);
770 }
771 zft_zap_read_buffers();
772 /* now free up memory as much as possible. We don't destroy
773 * the deblock buffer if it containes a valid segment.
774 */
775 if (zft_deblock_segment == -1) {
776 zft_vfree(&zft_deblock_buf, FT_SEGMENT_SIZE);
777 }
778 /* high level driver status, forces creation of a new volume
779 * when calling ftape_write again and not zft_just_before_eof
780 */
781 zft_io_state = zft_idle;
782 if (going_offline) {
783 zft_init_driver();
784 zft_uninit_mem();
785 going_offline = 0;
786 zft_offline = 1;
787 } else if (zft_cmpr_lock(0 /* don't load */) == 0) {
788 (*zft_cmpr_ops->reset)(); /* unlock it again */
789 }
790 zft_memory_stats();
791 /* call the hardware release routine. Puts the drive offline */
792 ftape_disable();
793 TRACE_EXIT result;
794}
795
796/*
797 * the wrapper function around the wrapper MTIOCTOP ioctl
798 */
799static int mtioctop(struct mtop *mtop, int arg_size)
800{
801 int result = 0;
802 fun_entry *mt_fun_entry;
803 TRACE_FUN(ft_t_flow);
804
805 if (arg_size != sizeof(struct mtop) || mtop->mt_op >= NR_MT_CMDS) {
806 TRACE_EXIT -EINVAL;
807 }
808 TRACE(ft_t_noise, "calling MTIOCTOP command: %s",
809 mt_funs[mtop->mt_op].name);
810 mt_fun_entry= &mt_funs[mtop->mt_op];
811 zft_resid = mtop->mt_count;
812 if (!mt_fun_entry->offline && zft_offline) {
813 if (ft_no_tape) {
814 TRACE_ABORT(-ENXIO, ft_t_info, "no tape present");
815 } else {
816 TRACE_ABORT(-ENXIO, ft_t_info, "drive is offline");
817 }
818 }
819 if (!mt_fun_entry->not_formatted && !ft_formatted) {
820 TRACE_ABORT(-EACCES, ft_t_info, "tape is not formatted");
821 }
822 if (!mt_fun_entry->write_protected) {
823 TRACE_CATCH(zft_check_write_access(&zft_pos),);
824 }
825 if (mt_fun_entry->need_idle_state && !(zft_offline || !ft_formatted)) {
826 TRACE_CATCH(zft_def_idle_state(),);
827 }
828 if (!zft_qic_mode && !mt_fun_entry->raw_mode) {
829 TRACE_ABORT(-EACCES, ft_t_info,
830"Drive needs to be in QIC-80 compatibility mode for this command");
831 }
832 result = (mt_fun_entry->function)(&mtop->mt_count);
833 if (zft_tape_at_lbot(&zft_pos)) {
834 TRACE_CATCH(zft_update_header_segments(),);
835 }
836 if (result >= 0) {
837 zft_resid = 0;
838 }
839 TRACE_EXIT result;
840}
841
842/*
843 * standard MTIOCGET ioctl
844 */
845static int mtiocget(struct mtget *mtget, int arg_size)
846{
847 const zft_volinfo *volume;
848 __s64 max_tape_pos;
849 TRACE_FUN(ft_t_flow);
850
851 if (arg_size != sizeof(struct mtget)) {
852 TRACE_ABORT(-EINVAL, ft_t_info, "bad argument size: %d",
853 arg_size);
854 }
855 mtget->mt_type = ft_drive_type.vendor_id + 0x800000;
856 mtget->mt_dsreg = ft_last_status.space;
857 mtget->mt_erreg = ft_last_error.space; /* error register */
858 mtget->mt_resid = zft_resid; /* residuum of writes, reads and
859 * MTIOCTOP commands
860 */
861 if (!zft_offline) { /* neither no_tape nor soft offline */
862 mtget->mt_gstat = GMT_ONLINE(~0UL);
863 /* should rather return the status of the cartridge
864 * than the access mode of the file, therefor use
865 * ft_write_protected, not zft_write_protected
866 */
867 if (ft_write_protected) {
868 mtget->mt_gstat |= GMT_WR_PROT(~0UL);
869 }
870 if(zft_header_read) { /* this catches non-formatted */
871 volume = zft_find_volume(zft_pos.seg_pos);
872 mtget->mt_fileno = volume->count;
873 max_tape_pos = zft_capacity - zft_blk_sz;
874 if (zft_use_compression) {
875 max_tape_pos -= ZFT_CMPR_OVERHEAD;
876 }
877 if (zft_tape_at_eod(&zft_pos)) {
878 mtget->mt_gstat |= GMT_EOD(~0UL);
879 }
880 if (zft_pos.tape_pos > max_tape_pos) {
881 mtget->mt_gstat |= GMT_EOT(~0UL);
882 }
883 mtget->mt_blkno = zft_div_blksz(zft_pos.volume_pos,
884 volume->blk_sz);
885 if (zft_just_before_eof) {
886 mtget->mt_gstat |= GMT_EOF(~0UL);
887 }
888 if (zft_tape_at_lbot(&zft_pos)) {
889 mtget->mt_gstat |= GMT_BOT(~0UL);
890 }
891 } else {
892 mtget->mt_fileno = mtget->mt_blkno = -1;
893 if (mtget->mt_dsreg & QIC_STATUS_AT_BOT) {
894 mtget->mt_gstat |= GMT_BOT(~0UL);
895 }
896 }
897 } else {
898 if (ft_no_tape) {
899 mtget->mt_gstat = GMT_DR_OPEN(~0UL);
900 } else {
901 mtget->mt_gstat = 0UL;
902 }
903 mtget->mt_fileno = mtget->mt_blkno = -1;
904 }
905 TRACE_EXIT 0;
906}
907
908#ifdef MTIOCRDFTSEG
909/*
910 * Read a floppy tape segment. This is useful for manipulating the
911 * volume table, and read the old header segment before re-formatting
912 * the cartridge.
913 */
914static int mtiocrdftseg(struct mtftseg * mtftseg, int arg_size)
915{
916 TRACE_FUN(ft_t_flow);
917
918 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOCRDFTSEG");
919 if (zft_qic_mode) {
920 TRACE_ABORT(-EACCES, ft_t_info,
921 "driver needs to be in raw mode for this ioctl");
922 }
923 if (arg_size != sizeof(struct mtftseg)) {
924 TRACE_ABORT(-EINVAL, ft_t_info, "bad argument size: %d",
925 arg_size);
926 }
927 if (zft_offline) {
928 TRACE_EXIT -ENXIO;
929 }
930 if (mtftseg->mt_mode != FT_RD_SINGLE &&
931 mtftseg->mt_mode != FT_RD_AHEAD) {
932 TRACE_ABORT(-EINVAL, ft_t_info, "invalid read mode");
933 }
934 if (!ft_formatted) {
935 TRACE_EXIT -EACCES; /* -ENXIO ? */
936
937 }
938 if (!zft_header_read) {
939 TRACE_CATCH(zft_def_idle_state(),);
940 }
941 if (mtftseg->mt_segno > ft_last_data_segment) {
942 TRACE_ABORT(-EINVAL, ft_t_info, "segment number is too large");
943 }
944 mtftseg->mt_result = ftape_read_segment(mtftseg->mt_segno,
945 zft_deblock_buf,
946 mtftseg->mt_mode);
947 if (mtftseg->mt_result < 0) {
948 /* a negativ result is not an ioctl error. if
949 * the user wants to read damaged tapes,
950 * it's up to her/him
951 */
952 TRACE_EXIT 0;
953 }
954 if (copy_to_user(mtftseg->mt_data,
955 zft_deblock_buf,
956 mtftseg->mt_result) != 0) {
957 TRACE_EXIT -EFAULT;
958 }
959 TRACE_EXIT 0;
960}
961#endif
962
963#ifdef MTIOCWRFTSEG
964/*
965 * write a floppy tape segment. This version features writing of
966 * deleted address marks, and gracefully ignores the (software)
967 * ft_formatted flag to support writing of header segments after
968 * formatting.
969 */
970static int mtiocwrftseg(struct mtftseg * mtftseg, int arg_size)
971{
972 int result;
973 TRACE_FUN(ft_t_flow);
974
975 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOCWRFTSEG");
976 if (zft_write_protected || zft_qic_mode) {
977 TRACE_EXIT -EACCES;
978 }
979 if (arg_size != sizeof(struct mtftseg)) {
980 TRACE_ABORT(-EINVAL, ft_t_info, "bad argument size: %d",
981 arg_size);
982 }
983 if (zft_offline) {
984 TRACE_EXIT -ENXIO;
985 }
986 if (mtftseg->mt_mode != FT_WR_ASYNC &&
987 mtftseg->mt_mode != FT_WR_MULTI &&
988 mtftseg->mt_mode != FT_WR_SINGLE &&
989 mtftseg->mt_mode != FT_WR_DELETE) {
990 TRACE_ABORT(-EINVAL, ft_t_info, "invalid write mode");
991 }
992 /*
993 * We don't check for ft_formatted, because this gives
994 * only the software status of the driver.
995 *
996 * We assume that the user knows what it is
997 * doing. And rely on the low level stuff to fail
998 * when the tape isn't formatted. We only make sure
999 * that The header segment buffer is allocated,
1000 * because it holds the bad sector map.
1001 */
1002 if (zft_hseg_buf == NULL) {
1003 TRACE_EXIT -ENXIO;
1004 }
1005 if (mtftseg->mt_mode != FT_WR_DELETE) {
1006 if (copy_from_user(zft_deblock_buf,
1007 mtftseg->mt_data,
1008 FT_SEGMENT_SIZE) != 0) {
1009 TRACE_EXIT -EFAULT;
1010 }
1011 }
1012 mtftseg->mt_result = ftape_write_segment(mtftseg->mt_segno,
1013 zft_deblock_buf,
1014 mtftseg->mt_mode);
1015 if (mtftseg->mt_result >= 0 && mtftseg->mt_mode == FT_WR_SINGLE) {
1016 /*
1017 * a negativ result is not an ioctl error. if
1018 * the user wants to write damaged tapes,
1019 * it's up to her/him
1020 */
1021 if ((result = ftape_loop_until_writes_done()) < 0) {
1022 mtftseg->mt_result = result;
1023 }
1024 }
1025 TRACE_EXIT 0;
1026}
1027#endif
1028
1029#ifdef MTIOCVOLINFO
1030/*
1031 * get information about volume positioned at.
1032 */
1033static int mtiocvolinfo(struct mtvolinfo *volinfo, int arg_size)
1034{
1035 const zft_volinfo *volume;
1036 TRACE_FUN(ft_t_flow);
1037
1038 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOCVOLINFO");
1039 if (arg_size != sizeof(struct mtvolinfo)) {
1040 TRACE_ABORT(-EINVAL,
1041 ft_t_info, "bad argument size: %d", arg_size);
1042 }
1043 if (zft_offline) {
1044 TRACE_EXIT -ENXIO;
1045 }
1046 if (!ft_formatted) {
1047 TRACE_EXIT -EACCES;
1048 }
1049 TRACE_CATCH(zft_def_idle_state(),);
1050 volume = zft_find_volume(zft_pos.seg_pos);
1051 volinfo->mt_volno = volume->count;
1052 volinfo->mt_blksz = volume->blk_sz == 1 ? 0 : volume->blk_sz;
1053 volinfo->mt_size = volume->size >> 10;
1054 volinfo->mt_rawsize = ((zft_calc_tape_pos(volume->end_seg + 1) >> 10) -
1055 (zft_calc_tape_pos(volume->start_seg) >> 10));
1056 volinfo->mt_cmpr = volume->use_compression;
1057 TRACE_EXIT 0;
1058}
1059#endif
1060
1061#ifdef ZFT_OBSOLETE
1062static int mtioc_zftape_getblksz(struct mtblksz *blksz, int arg_size)
1063{
1064 TRACE_FUN(ft_t_flow);
1065
1066 TRACE(ft_t_noise, "\n"
1067 KERN_INFO "Mag tape ioctl command: MTIOC_ZTAPE_GETBLKSZ\n"
1068 KERN_INFO "This ioctl is here merely for compatibility.\n"
1069 KERN_INFO "Please use MTIOCVOLINFO instead");
1070 if (arg_size != sizeof(struct mtblksz)) {
1071 TRACE_ABORT(-EINVAL,
1072 ft_t_info, "bad argument size: %d", arg_size);
1073 }
1074 if (zft_offline) {
1075 TRACE_EXIT -ENXIO;
1076 }
1077 if (!ft_formatted) {
1078 TRACE_EXIT -EACCES;
1079 }
1080 TRACE_CATCH(zft_def_idle_state(),);
1081 blksz->mt_blksz = zft_find_volume(zft_pos.seg_pos)->blk_sz;
1082 TRACE_EXIT 0;
1083}
1084#endif
1085
1086#ifdef MTIOCGETSIZE
1087/*
1088 * get the capacity of the tape cartridge.
1089 */
1090static int mtiocgetsize(struct mttapesize *size, int arg_size)
1091{
1092 TRACE_FUN(ft_t_flow);
1093
1094 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOC_ZFTAPE_GETSIZE");
1095 if (arg_size != sizeof(struct mttapesize)) {
1096 TRACE_ABORT(-EINVAL,
1097 ft_t_info, "bad argument size: %d", arg_size);
1098 }
1099 if (zft_offline) {
1100 TRACE_EXIT -ENXIO;
1101 }
1102 if (!ft_formatted) {
1103 TRACE_EXIT -EACCES;
1104 }
1105 TRACE_CATCH(zft_def_idle_state(),);
1106 size->mt_capacity = (unsigned int)(zft_capacity>>10);
1107 size->mt_used = (unsigned int)(zft_get_eom_pos()>>10);
1108 TRACE_EXIT 0;
1109}
1110#endif
1111
1112static int mtiocpos(struct mtpos *mtpos, int arg_size)
1113{
1114 int result;
1115 TRACE_FUN(ft_t_flow);
1116
1117 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOCPOS");
1118 if (arg_size != sizeof(struct mtpos)) {
1119 TRACE_ABORT(-EINVAL,
1120 ft_t_info, "bad argument size: %d", arg_size);
1121 }
1122 result = mt_tell((int *)&mtpos->mt_blkno);
1123 TRACE_EXIT result;
1124}
1125
1126#ifdef MTIOCFTFORMAT
1127/*
1128 * formatting of floppy tape cartridges. This is intended to be used
1129 * together with the MTIOCFTCMD ioctl and the new mmap feature
1130 */
1131
1132/*
1133 * This function uses ftape_decode_header_segment() to inform the low
1134 * level ftape module about the new parameters.
1135 *
1136 * It erases the hseg_buf. The calling process must specify all
1137 * parameters to assure proper operation.
1138 *
1139 * return values: -EINVAL - wrong argument size
1140 * -EINVAL - if ftape_decode_header_segment() failed.
1141 */
1142static int set_format_parms(struct ftfmtparms *p, __u8 *hseg_buf)
1143{
1144 ft_trace_t old_level = TRACE_LEVEL;
1145 TRACE_FUN(ft_t_flow);
1146
1147 TRACE(ft_t_noise, "MTIOCFTFORMAT operation FTFMT_SETPARMS");
1148 memset(hseg_buf, 0, FT_SEGMENT_SIZE);
1149 PUT4(hseg_buf, FT_SIGNATURE, FT_HSEG_MAGIC);
1150
1151 /* fill in user specified parameters
1152 */
1153 hseg_buf[FT_FMT_CODE] = (__u8)p->ft_fmtcode;
1154 PUT2(hseg_buf, FT_SPT, p->ft_spt);
1155 hseg_buf[FT_TPC] = (__u8)p->ft_tpc;
1156 hseg_buf[FT_FHM] = (__u8)p->ft_fhm;
1157 hseg_buf[FT_FTM] = (__u8)p->ft_ftm;
1158
1159 /* fill in sane defaults to make ftape happy.
1160 */
1161 hseg_buf[FT_FSM] = (__u8)128; /* 128 is hard wired all over ftape */
1162 if (p->ft_fmtcode == fmt_big) {
1163 PUT4(hseg_buf, FT_6_HSEG_1, 0);
1164 PUT4(hseg_buf, FT_6_HSEG_2, 1);
1165 PUT4(hseg_buf, FT_6_FRST_SEG, 2);
1166 PUT4(hseg_buf, FT_6_LAST_SEG, p->ft_spt * p->ft_tpc - 1);
1167 } else {
1168 PUT2(hseg_buf, FT_HSEG_1, 0);
1169 PUT2(hseg_buf, FT_HSEG_2, 1);
1170 PUT2(hseg_buf, FT_FRST_SEG, 2);
1171 PUT2(hseg_buf, FT_LAST_SEG, p->ft_spt * p->ft_tpc - 1);
1172 }
1173
1174 /* Synchronize with the low level module. This is particularly
1175 * needed for unformatted cartridges as the QIC std was previously
1176 * unknown BUT is needed to set data rate and to calculate timeouts.
1177 */
1178 TRACE_CATCH(ftape_calibrate_data_rate(p->ft_qicstd&QIC_TAPE_STD_MASK),
1179 _res = -EINVAL);
1180
1181 /* The following will also recalcualte the timeouts for the tape
1182 * length and QIC std we want to format to.
1183 * abort with -EINVAL rather than -EIO
1184 */
1185 SET_TRACE_LEVEL(ft_t_warn);
1186 TRACE_CATCH(ftape_decode_header_segment(hseg_buf),
1187 SET_TRACE_LEVEL(old_level); _res = -EINVAL);
1188 SET_TRACE_LEVEL(old_level);
1189 TRACE_EXIT 0;
1190}
1191
1192/*
1193 * Return the internal SOFTWARE status of the kernel driver. This does
1194 * NOT query the tape drive about its status.
1195 */
1196static int get_format_parms(struct ftfmtparms *p, __u8 *hseg_buffer)
1197{
1198 TRACE_FUN(ft_t_flow);
1199
1200 TRACE(ft_t_noise, "MTIOCFTFORMAT operation FTFMT_GETPARMS");
1201 p->ft_qicstd = ft_qic_std;
1202 p->ft_fmtcode = ft_format_code;
1203 p->ft_fhm = hseg_buffer[FT_FHM];
1204 p->ft_ftm = hseg_buffer[FT_FTM];
1205 p->ft_spt = ft_segments_per_track;
1206 p->ft_tpc = ft_tracks_per_tape;
1207 TRACE_EXIT 0;
1208}
1209
1210static int mtiocftformat(struct mtftformat *mtftformat, int arg_size)
1211{
1212 int result;
1213 union fmt_arg *arg = &mtftformat->fmt_arg;
1214 TRACE_FUN(ft_t_flow);
1215
1216 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOCFTFORMAT");
1217 if (zft_offline) {
1218 if (ft_no_tape) {
1219 TRACE_ABORT(-ENXIO, ft_t_info, "no tape present");
1220 } else {
1221 TRACE_ABORT(-ENXIO, ft_t_info, "drive is offline");
1222 }
1223 }
1224 if (zft_qic_mode) {
1225 TRACE_ABORT(-EACCES, ft_t_info,
1226 "driver needs to be in raw mode for this ioctl");
1227 }
1228 if (zft_hseg_buf == NULL) {
1229 TRACE_CATCH(zft_vcalloc_once(&zft_hseg_buf, FT_SEGMENT_SIZE),);
1230 }
1231 zft_header_read = 0;
1232 switch(mtftformat->fmt_op) {
1233 case FTFMT_SET_PARMS:
1234 TRACE_CATCH(set_format_parms(&arg->fmt_parms, zft_hseg_buf),);
1235 TRACE_EXIT 0;
1236 case FTFMT_GET_PARMS:
1237 TRACE_CATCH(get_format_parms(&arg->fmt_parms, zft_hseg_buf),);
1238 TRACE_EXIT 0;
1239 case FTFMT_FORMAT_TRACK:
1240 if ((ft_formatted && zft_check_write_access(&zft_pos) < 0) ||
1241 (!ft_formatted && zft_write_protected)) {
1242 TRACE_ABORT(-EACCES, ft_t_info, "Write access denied");
1243 }
1244 TRACE_CATCH(ftape_format_track(arg->fmt_track.ft_track,
1245 arg->fmt_track.ft_gap3),);
1246 TRACE_EXIT 0;
1247 case FTFMT_STATUS:
1248 TRACE_CATCH(ftape_format_status(&arg->fmt_status.ft_segment),);
1249 TRACE_EXIT 0;
1250 case FTFMT_VERIFY:
1251 TRACE_CATCH(ftape_verify_segment(arg->fmt_verify.ft_segment,
1252 (SectorMap *)&arg->fmt_verify.ft_bsm),);
1253 TRACE_EXIT 0;
1254 default:
1255 TRACE_ABORT(-EINVAL, ft_t_err, "Invalid format operation");
1256 }
1257 TRACE_EXIT result;
1258}
1259#endif
1260
1261#ifdef MTIOCFTCMD
1262/*
1263 * send a QIC-117 command to the drive, with optional timeouts,
1264 * parameter and result bits. This is intended to be used together
1265 * with the formatting ioctl.
1266 */
1267static int mtiocftcmd(struct mtftcmd *ftcmd, int arg_size)
1268{
1269 int i;
1270 TRACE_FUN(ft_t_flow);
1271
1272 TRACE(ft_t_noise, "Mag tape ioctl command: MTIOCFTCMD");
1273 if (!capable(CAP_SYS_ADMIN)) {
1274 TRACE_ABORT(-EPERM, ft_t_info,
1275 "need CAP_SYS_ADMIN capability to send raw qic-117 commands");
1276 }
1277 if (zft_qic_mode) {
1278 TRACE_ABORT(-EACCES, ft_t_info,
1279 "driver needs to be in raw mode for this ioctl");
1280 }
1281 if (arg_size != sizeof(struct mtftcmd)) {
1282 TRACE_ABORT(-EINVAL,
1283 ft_t_info, "bad argument size: %d", arg_size);
1284 }
1285 if (ftcmd->ft_wait_before) {
1286 TRACE_CATCH(ftape_ready_wait(ftcmd->ft_wait_before,
1287 &ftcmd->ft_status),);
1288 }
1289 if (ftcmd->ft_status & QIC_STATUS_ERROR)
1290 goto ftmtcmd_error;
1291 if (ftcmd->ft_result_bits != 0) {
1292 TRACE_CATCH(ftape_report_operation(&ftcmd->ft_result,
1293 ftcmd->ft_cmd,
1294 ftcmd->ft_result_bits),);
1295 } else {
1296 TRACE_CATCH(ftape_command(ftcmd->ft_cmd),);
1297 if (ftcmd->ft_status & QIC_STATUS_ERROR)
1298 goto ftmtcmd_error;
1299 for (i = 0; i < ftcmd->ft_parm_cnt; i++) {
1300 TRACE_CATCH(ftape_parameter(ftcmd->ft_parms[i]&0x0f),);
1301 if (ftcmd->ft_status & QIC_STATUS_ERROR)
1302 goto ftmtcmd_error;
1303 }
1304 }
1305 if (ftcmd->ft_wait_after != 0) {
1306 TRACE_CATCH(ftape_ready_wait(ftcmd->ft_wait_after,
1307 &ftcmd->ft_status),);
1308 }
1309ftmtcmd_error:
1310 if (ftcmd->ft_status & QIC_STATUS_ERROR) {
1311 TRACE(ft_t_noise, "error status set");
1312 TRACE_CATCH(ftape_report_error(&ftcmd->ft_error,
1313 &ftcmd->ft_cmd, 1),);
1314 }
1315 TRACE_EXIT 0; /* this is not an i/o error */
1316}
1317#endif
1318
1319/* IOCTL routine called by kernel-interface code
1320 */
1321int _zft_ioctl(unsigned int command, void __user * arg)
1322{
1323 int result;
1324 union { struct mtop mtop;
1325 struct mtget mtget;
1326 struct mtpos mtpos;
1327#ifdef MTIOCRDFTSEG
1328 struct mtftseg mtftseg;
1329#endif
1330#ifdef MTIOCVOLINFO
1331 struct mtvolinfo mtvolinfo;
1332#endif
1333#ifdef MTIOCGETSIZE
1334 struct mttapesize mttapesize;
1335#endif
1336#ifdef MTIOCFTFORMAT
1337 struct mtftformat mtftformat;
1338#endif
1339#ifdef ZFT_OBSOLETE
1340 struct mtblksz mtblksz;
1341#endif
1342#ifdef MTIOCFTCMD
1343 struct mtftcmd mtftcmd;
1344#endif
1345 } krnl_arg;
1346 int arg_size = _IOC_SIZE(command);
1347 int dir = _IOC_DIR(command);
1348 TRACE_FUN(ft_t_flow);
1349
1350 /* This check will only catch arguments that are too large !
1351 */
1352 if (dir & (_IOC_READ | _IOC_WRITE) && arg_size > sizeof(krnl_arg)) {
1353 TRACE_ABORT(-EINVAL,
1354 ft_t_info, "bad argument size: %d", arg_size);
1355 }
1356 if (dir & _IOC_WRITE) {
1357 if (copy_from_user(&krnl_arg, arg, arg_size) != 0) {
1358 TRACE_EXIT -EFAULT;
1359 }
1360 }
1361 TRACE(ft_t_flow, "called with ioctl command: 0x%08x", command);
1362 switch (command) {
1363 case MTIOCTOP:
1364 result = mtioctop(&krnl_arg.mtop, arg_size);
1365 break;
1366 case MTIOCGET:
1367 result = mtiocget(&krnl_arg.mtget, arg_size);
1368 break;
1369 case MTIOCPOS:
1370 result = mtiocpos(&krnl_arg.mtpos, arg_size);
1371 break;
1372#ifdef MTIOCVOLINFO
1373 case MTIOCVOLINFO:
1374 result = mtiocvolinfo(&krnl_arg.mtvolinfo, arg_size);
1375 break;
1376#endif
1377#ifdef ZFT_OBSOLETE
1378 case MTIOC_ZFTAPE_GETBLKSZ:
1379 result = mtioc_zftape_getblksz(&krnl_arg.mtblksz, arg_size);
1380 break;
1381#endif
1382#ifdef MTIOCRDFTSEG
1383 case MTIOCRDFTSEG: /* read a segment via ioctl */
1384 result = mtiocrdftseg(&krnl_arg.mtftseg, arg_size);
1385 break;
1386#endif
1387#ifdef MTIOCWRFTSEG
1388 case MTIOCWRFTSEG: /* write a segment via ioctl */
1389 result = mtiocwrftseg(&krnl_arg.mtftseg, arg_size);
1390 break;
1391#endif
1392#ifdef MTIOCGETSIZE
1393 case MTIOCGETSIZE:
1394 result = mtiocgetsize(&krnl_arg.mttapesize, arg_size);
1395 break;
1396#endif
1397#ifdef MTIOCFTFORMAT
1398 case MTIOCFTFORMAT:
1399 result = mtiocftformat(&krnl_arg.mtftformat, arg_size);
1400 break;
1401#endif
1402#ifdef MTIOCFTCMD
1403 case MTIOCFTCMD:
1404 result = mtiocftcmd(&krnl_arg.mtftcmd, arg_size);
1405 break;
1406#endif
1407 default:
1408 result = -EINVAL;
1409 break;
1410 }
1411 if ((result >= 0) && (dir & _IOC_READ)) {
1412 if (copy_to_user(arg, &krnl_arg, arg_size) != 0) {
1413 TRACE_EXIT -EFAULT;
1414 }
1415 }
1416 TRACE_EXIT result;
1417}
diff --git a/drivers/char/ftape/zftape/zftape-ctl.h b/drivers/char/ftape/zftape/zftape-ctl.h
deleted file mode 100644
index 8e6f2d7ac74e..000000000000
--- a/drivers/char/ftape/zftape/zftape-ctl.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef _ZFTAPE_CTL_H
2#define _ZFTAPE_CTL_H
3
4/*
5 * Copyright (C) 1996, 1997 Claus-Justus Heine.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-ctl.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:19:02 $
25 *
26 * This file contains the non-standard IOCTL related definitions
27 * for the QIC-40/80 floppy-tape driver for Linux.
28 */
29
30#include <linux/ioctl.h>
31#include <linux/mtio.h>
32
33#include "../zftape/zftape-rw.h"
34
35#ifdef CONFIG_ZFTAPE_MODULE
36#define ftape_status (*zft_status)
37#endif
38
39extern int zft_offline;
40extern int zft_mt_compression;
41extern int zft_write_protected;
42extern int zft_header_read;
43extern unsigned int zft_unit;
44extern int zft_resid;
45
46extern void zft_reset_position(zft_position *pos);
47extern int zft_check_write_access(zft_position *pos);
48extern int zft_def_idle_state(void);
49
50/* hooks for the VFS interface
51 */
52extern int _zft_open(unsigned int dev_minor, unsigned int access_mode);
53extern int _zft_close(void);
54extern int _zft_ioctl(unsigned int command, void __user *arg);
55#endif
56
57
58
diff --git a/drivers/char/ftape/zftape/zftape-eof.c b/drivers/char/ftape/zftape/zftape-eof.c
deleted file mode 100644
index dcadcaee9ac1..000000000000
--- a/drivers/char/ftape/zftape/zftape-eof.c
+++ /dev/null
@@ -1,199 +0,0 @@
1/*
2 * I use these routines just to decide when I have to fake a
3 * volume-table to preserve compatibility to original ftape.
4 */
5/*
6 * Copyright (C) 1994-1995 Bas Laarhoven.
7 *
8 * Modified for zftape 1996, 1997 Claus Heine.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23
24 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-eof.c,v $
25 * $Revision: 1.2 $
26 * $Date: 1997/10/05 19:19:02 $
27 *
28 * This file contains the eof mark handling code
29 * for the QIC-40/80 floppy-tape driver for Linux.
30 */
31
32#include <linux/string.h>
33#include <linux/errno.h>
34
35#include <linux/zftape.h>
36
37#include "../zftape/zftape-init.h"
38#include "../zftape/zftape-rw.h"
39#include "../zftape/zftape-eof.h"
40
41/* Global vars.
42 */
43
44/* a copy of the failed sector log from the header segment.
45 */
46eof_mark_union *zft_eof_map;
47
48/* number of eof marks (entries in bad sector log) on tape.
49 */
50int zft_nr_eof_marks = -1;
51
52
53/* Local vars.
54 */
55
56static char linux_tape_label[] = "Linux raw format V";
57enum {
58 min_fmt_version = 1, max_fmt_version = 2
59};
60static unsigned ftape_fmt_version = 0;
61
62
63/* Ftape (mis)uses the bad sector log to record end-of-file marks.
64 * Initially (when the tape is erased) all entries in the bad sector
65 * log are added to the tape's bad sector map. The bad sector log then
66 * is cleared.
67 *
68 * The bad sector log normally contains entries of the form:
69 * even 16-bit word: segment number of bad sector
70 * odd 16-bit word: encoded date
71 * There can be a total of 448 entries (1792 bytes).
72 *
73 * My guess is that no program is using this bad sector log (the *
74 * format seems useless as there is no indication of the bad sector
75 * itself, only the segment) However, if any program does use the bad
76 * sector log, the format used by ftape will let the program think
77 * there are some bad sectors and no harm is done.
78 *
79 * The eof mark entries that ftape stores in the bad sector log: even
80 * 16-bit word: segment number of eof mark odd 16-bit word: sector
81 * number of eof mark [1..32]
82 *
83 * The zft_eof_map as maintained is a sorted list of eof mark entries.
84 *
85 *
86 * The tape name field in the header segments is used to store a linux
87 * tape identification string and a version number. This way the tape
88 * can be recognized as a Linux raw format tape when using tools under
89 * other OS's.
90 *
91 * 'Wide' QIC tapes (format code 4) don't have a failed sector list
92 * anymore. That space is used for the (longer) bad sector map that
93 * now is a variable length list too. We now store our end-of-file
94 * marker list after the bad-sector-map on tape. The list is delimited
95 * by a (__u32) 0 entry.
96 */
97
98int zft_ftape_validate_label(char *label)
99{
100 static char tmp_label[45];
101 int result = 0;
102 TRACE_FUN(ft_t_any);
103
104 memcpy(tmp_label, label, FT_LABEL_SZ);
105 tmp_label[FT_LABEL_SZ] = '\0';
106 TRACE(ft_t_noise, "tape label = `%s'", tmp_label);
107 ftape_fmt_version = 0;
108 if (memcmp(label, linux_tape_label, strlen(linux_tape_label)) == 0) {
109 int pos = strlen(linux_tape_label);
110 while (label[pos] >= '0' && label[pos] <= '9') {
111 ftape_fmt_version *= 10;
112 ftape_fmt_version = label[ pos++] - '0';
113 }
114 result = (ftape_fmt_version >= min_fmt_version &&
115 ftape_fmt_version <= max_fmt_version);
116 }
117 TRACE(ft_t_noise, "format version = %d", ftape_fmt_version);
118 TRACE_EXIT result;
119}
120
121static __u8 * find_end_of_eof_list(__u8 * ptr, __u8 * limit)
122{
123 while (ptr + 3 < limit) {
124
125 if (get_unaligned((__u32*)ptr)) {
126 ptr += sizeof(__u32);
127 } else {
128 return ptr;
129 }
130 }
131 return NULL;
132}
133
134void zft_ftape_extract_file_marks(__u8* address)
135{
136 int i;
137 TRACE_FUN(ft_t_any);
138
139 zft_eof_map = NULL;
140 if (ft_format_code == fmt_var || ft_format_code == fmt_big) {
141 __u8* end;
142 __u8* start = ftape_find_end_of_bsm_list(address);
143
144 zft_nr_eof_marks = 0;
145 if (start) {
146 start += 3; /* skip end of list mark */
147 end = find_end_of_eof_list(start,
148 address + FT_SEGMENT_SIZE);
149 if (end && end - start <= FT_FSL_SIZE) {
150 zft_nr_eof_marks = ((end - start) /
151 sizeof(eof_mark_union));
152 zft_eof_map = (eof_mark_union *)start;
153 } else {
154 TRACE(ft_t_err,
155 "EOF Mark List is too long or damaged!");
156 }
157 } else {
158 TRACE(ft_t_err,
159 "Bad Sector List is too long or damaged !");
160 }
161 } else {
162 zft_eof_map = (eof_mark_union *)&address[FT_FSL];
163 zft_nr_eof_marks = GET2(address, FT_FSL_CNT);
164 }
165 TRACE(ft_t_noise, "number of file marks: %d", zft_nr_eof_marks);
166 if (ftape_fmt_version == 1) {
167 TRACE(ft_t_info, "swapping version 1 fields");
168 /* version 1 format uses swapped sector and segment
169 * fields, correct that !
170 */
171 for (i = 0; i < zft_nr_eof_marks; ++i) {
172 __u16 tmp = GET2(&zft_eof_map[i].mark.segment,0);
173 PUT2(&zft_eof_map[i].mark.segment, 0,
174 GET2(&zft_eof_map[i].mark.date,0));
175 PUT2(&zft_eof_map[i].mark.date, 0, tmp);
176 }
177 }
178 for (i = 0; i < zft_nr_eof_marks; ++i) {
179 TRACE(ft_t_noise, "eof mark: %5d/%2d",
180 GET2(&zft_eof_map[i].mark.segment, 0),
181 GET2(&zft_eof_map[i].mark.date,0));
182 }
183 TRACE_EXIT;
184}
185
186void zft_clear_ftape_file_marks(void)
187{
188 TRACE_FUN(ft_t_flow);
189 /* Clear failed sector log: remove all tape marks. We
190 * don't use old ftape-style EOF-marks.
191 */
192 TRACE(ft_t_info, "Clearing old ftape's eof map");
193 memset(zft_eof_map, 0, zft_nr_eof_marks * sizeof(__u32));
194 zft_nr_eof_marks = 0;
195 PUT2(zft_hseg_buf, FT_FSL_CNT, 0); /* nr of eof-marks */
196 zft_header_changed = 1;
197 zft_update_label(zft_hseg_buf);
198 TRACE_EXIT;
199}
diff --git a/drivers/char/ftape/zftape/zftape-eof.h b/drivers/char/ftape/zftape/zftape-eof.h
deleted file mode 100644
index 26568c26c518..000000000000
--- a/drivers/char/ftape/zftape/zftape-eof.h
+++ /dev/null
@@ -1,52 +0,0 @@
1#ifndef _ZFTAPE_EOF_H
2#define _ZFTAPE_EOF_H
3
4/*
5 * Copyright (C) 1994-1995 Bas Laarhoven.
6 * adaptaed for zftape 1996, 1997 by Claus Heine
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-eof.h,v $
24 * $Revision: 1.2 $
25 * $Date: 1997/10/05 19:19:03 $
26 *
27 * Definitions and declarations for the end of file markers
28 * for the QIC-40/80 floppy-tape driver for Linux.
29 */
30
31#include <linux/ftape-header-segment.h>
32#include "../zftape/zftape-buffers.h"
33/* failed sector log size (only used if format code != 4).
34 */
35
36typedef union {
37 ft_fsl_entry mark;
38 __u32 entry;
39} eof_mark_union;
40
41/* ftape-eof.c defined global vars.
42 */
43extern int zft_nr_eof_marks;
44extern eof_mark_union *zft_eof_map;
45
46/* ftape-eof.c defined global functions.
47 */
48extern void zft_ftape_extract_file_marks(__u8* address);
49extern int zft_ftape_validate_label(char* label);
50extern void zft_clear_ftape_file_marks(void);
51
52#endif
diff --git a/drivers/char/ftape/zftape/zftape-init.c b/drivers/char/ftape/zftape/zftape-init.c
deleted file mode 100644
index 164a1aa77a2f..000000000000
--- a/drivers/char/ftape/zftape/zftape-init.c
+++ /dev/null
@@ -1,377 +0,0 @@
1/*
2 * Copyright (C) 1996, 1997 Claus-Justus Heine.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * This file contains the code that registers the zftape frontend
20 * to the ftape floppy tape driver for Linux
21 */
22
23#include <linux/module.h>
24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/kernel.h>
27#include <linux/signal.h>
28#include <linux/major.h>
29#include <linux/slab.h>
30#ifdef CONFIG_KMOD
31#include <linux/kmod.h>
32#endif
33#include <linux/fcntl.h>
34#include <linux/smp_lock.h>
35
36#include <linux/zftape.h>
37#include <linux/init.h>
38#include <linux/device.h>
39
40#include "../zftape/zftape-init.h"
41#include "../zftape/zftape-read.h"
42#include "../zftape/zftape-write.h"
43#include "../zftape/zftape-ctl.h"
44#include "../zftape/zftape-buffers.h"
45
46MODULE_AUTHOR("(c) 1996, 1997 Claus-Justus Heine "
47 "(claus@momo.math.rwth-aachen.de)");
48MODULE_DESCRIPTION(ZFTAPE_VERSION " - "
49 "VFS interface for the Linux floppy tape driver. "
50 "Support for QIC-113 compatible volume table "
51 "and builtin compression (lzrw3 algorithm)");
52MODULE_SUPPORTED_DEVICE("char-major-27");
53MODULE_LICENSE("GPL");
54
55/* Global vars.
56 */
57struct zft_cmpr_ops *zft_cmpr_ops = NULL;
58const ftape_info *zft_status;
59
60/* Local vars.
61 */
62static unsigned long busy_flag;
63
64static sigset_t orig_sigmask;
65
66/* the interface to the kernel vfs layer
67 */
68
69/* Note about llseek():
70 *
71 * st.c and tpqic.c update fp->f_pos but don't implment llseek() and
72 * initialize the llseek component of the file_ops struct with NULL.
73 * This means that the user will get the default seek, but the tape
74 * device will not respect the new position, but happily read from the
75 * old position. Think a zftape specific llseek() function would be
76 * better, returning -ESPIPE. TODO.
77 */
78
79static int zft_open (struct inode *ino, struct file *filep);
80static int zft_close(struct inode *ino, struct file *filep);
81static int zft_ioctl(struct inode *ino, struct file *filep,
82 unsigned int command, unsigned long arg);
83static int zft_mmap(struct file *filep, struct vm_area_struct *vma);
84static ssize_t zft_read (struct file *fp, char __user *buff,
85 size_t req_len, loff_t *ppos);
86static ssize_t zft_write(struct file *fp, const char __user *buff,
87 size_t req_len, loff_t *ppos);
88
89static const struct file_operations zft_cdev =
90{
91 .owner = THIS_MODULE,
92 .read = zft_read,
93 .write = zft_write,
94 .ioctl = zft_ioctl,
95 .mmap = zft_mmap,
96 .open = zft_open,
97 .release = zft_close,
98};
99
100static struct class *zft_class;
101
102/* Open floppy tape device
103 */
104static int zft_open(struct inode *ino, struct file *filep)
105{
106 int result;
107 TRACE_FUN(ft_t_flow);
108
109 nonseekable_open(ino, filep);
110 TRACE(ft_t_flow, "called for minor %d", iminor(ino));
111 if ( test_and_set_bit(0,&busy_flag) ) {
112 TRACE_ABORT(-EBUSY, ft_t_warn, "failed: already busy");
113 }
114 if ((iminor(ino) & ~(ZFT_MINOR_OP_MASK | FTAPE_NO_REWIND))
115 >
116 FTAPE_SEL_D) {
117 clear_bit(0,&busy_flag);
118 TRACE_ABORT(-ENXIO, ft_t_err, "failed: invalid unit nr");
119 }
120 orig_sigmask = current->blocked;
121 sigfillset(&current->blocked);
122 result = _zft_open(iminor(ino), filep->f_flags & O_ACCMODE);
123 if (result < 0) {
124 current->blocked = orig_sigmask; /* restore mask */
125 clear_bit(0,&busy_flag);
126 TRACE_ABORT(result, ft_t_err, "_ftape_open failed");
127 } else {
128 /* Mask signals that will disturb proper operation of the
129 * program that is calling.
130 */
131 current->blocked = orig_sigmask;
132 sigaddsetmask (&current->blocked, _DO_BLOCK);
133 TRACE_EXIT 0;
134 }
135}
136
137/* Close floppy tape device
138 */
139static int zft_close(struct inode *ino, struct file *filep)
140{
141 int result;
142 TRACE_FUN(ft_t_flow);
143
144 if ( !test_bit(0,&busy_flag) || iminor(ino) != zft_unit) {
145 TRACE(ft_t_err, "failed: not busy or wrong unit");
146 TRACE_EXIT 0;
147 }
148 sigfillset(&current->blocked);
149 result = _zft_close();
150 if (result < 0) {
151 TRACE(ft_t_err, "_zft_close failed");
152 }
153 current->blocked = orig_sigmask; /* restore before open state */
154 clear_bit(0,&busy_flag);
155 TRACE_EXIT 0;
156}
157
158/* Ioctl for floppy tape device
159 */
160static int zft_ioctl(struct inode *ino, struct file *filep,
161 unsigned int command, unsigned long arg)
162{
163 int result = -EIO;
164 sigset_t old_sigmask;
165 TRACE_FUN(ft_t_flow);
166
167 if ( !test_bit(0,&busy_flag) || iminor(ino) != zft_unit || ft_failure) {
168 TRACE_ABORT(-EIO, ft_t_err,
169 "failed: not busy, failure or wrong unit");
170 }
171 old_sigmask = current->blocked; /* save mask */
172 sigfillset(&current->blocked);
173 /* This will work as long as sizeof(void *) == sizeof(long) */
174 result = _zft_ioctl(command, (void __user *) arg);
175 current->blocked = old_sigmask; /* restore mask */
176 TRACE_EXIT result;
177}
178
179/* Ioctl for floppy tape device
180 */
181static int zft_mmap(struct file *filep, struct vm_area_struct *vma)
182{
183 int result = -EIO;
184 sigset_t old_sigmask;
185 TRACE_FUN(ft_t_flow);
186
187 if ( !test_bit(0,&busy_flag) ||
188 iminor(filep->f_dentry->d_inode) != zft_unit ||
189 ft_failure)
190 {
191 TRACE_ABORT(-EIO, ft_t_err,
192 "failed: not busy, failure or wrong unit");
193 }
194 old_sigmask = current->blocked; /* save mask */
195 sigfillset(&current->blocked);
196 if ((result = ftape_mmap(vma)) >= 0) {
197#ifndef MSYNC_BUG_WAS_FIXED
198 static struct vm_operations_struct dummy = { NULL, };
199 vma->vm_ops = &dummy;
200#endif
201 }
202 current->blocked = old_sigmask; /* restore mask */
203 TRACE_EXIT result;
204}
205
206/* Read from floppy tape device
207 */
208static ssize_t zft_read(struct file *fp, char __user *buff,
209 size_t req_len, loff_t *ppos)
210{
211 int result = -EIO;
212 sigset_t old_sigmask;
213 struct inode *ino = fp->f_dentry->d_inode;
214 TRACE_FUN(ft_t_flow);
215
216 TRACE(ft_t_data_flow, "called with count: %ld", (unsigned long)req_len);
217 if (!test_bit(0,&busy_flag) || iminor(ino) != zft_unit || ft_failure) {
218 TRACE_ABORT(-EIO, ft_t_err,
219 "failed: not busy, failure or wrong unit");
220 }
221 old_sigmask = current->blocked; /* save mask */
222 sigfillset(&current->blocked);
223 result = _zft_read(buff, req_len);
224 current->blocked = old_sigmask; /* restore mask */
225 TRACE(ft_t_data_flow, "return with count: %d", result);
226 TRACE_EXIT result;
227}
228
229/* Write to tape device
230 */
231static ssize_t zft_write(struct file *fp, const char __user *buff,
232 size_t req_len, loff_t *ppos)
233{
234 int result = -EIO;
235 sigset_t old_sigmask;
236 struct inode *ino = fp->f_dentry->d_inode;
237 TRACE_FUN(ft_t_flow);
238
239 TRACE(ft_t_flow, "called with count: %ld", (unsigned long)req_len);
240 if (!test_bit(0,&busy_flag) || iminor(ino) != zft_unit || ft_failure) {
241 TRACE_ABORT(-EIO, ft_t_err,
242 "failed: not busy, failure or wrong unit");
243 }
244 old_sigmask = current->blocked; /* save mask */
245 sigfillset(&current->blocked);
246 result = _zft_write(buff, req_len);
247 current->blocked = old_sigmask; /* restore mask */
248 TRACE(ft_t_data_flow, "return with count: %d", result);
249 TRACE_EXIT result;
250}
251
252/* END OF VFS INTERFACE
253 *
254 *****************************************************************************/
255
256/* driver/module initialization
257 */
258
259/* the compression module has to call this function to hook into the zftape
260 * code
261 */
262int zft_cmpr_register(struct zft_cmpr_ops *new_ops)
263{
264 TRACE_FUN(ft_t_flow);
265
266 if (zft_cmpr_ops != NULL) {
267 TRACE_EXIT -EBUSY;
268 } else {
269 zft_cmpr_ops = new_ops;
270 TRACE_EXIT 0;
271 }
272}
273
274/* lock the zft-compressor() module.
275 */
276int zft_cmpr_lock(int try_to_load)
277{
278 if (zft_cmpr_ops == NULL) {
279#ifdef CONFIG_KMOD
280 if (try_to_load) {
281 request_module("zft-compressor");
282 if (zft_cmpr_ops == NULL) {
283 return -ENOSYS;
284 }
285 } else {
286 return -ENOSYS;
287 }
288#else
289 return -ENOSYS;
290#endif
291 }
292 (*zft_cmpr_ops->lock)();
293 return 0;
294}
295
296#ifdef CONFIG_ZFT_COMPRESSOR
297extern int zft_compressor_init(void);
298#endif
299
300/* Called by modules package when installing the driver or by kernel
301 * during the initialization phase
302 */
303int __init zft_init(void)
304{
305 int i;
306 TRACE_FUN(ft_t_flow);
307
308#ifdef MODULE
309 printk(KERN_INFO ZFTAPE_VERSION "\n");
310 if (TRACE_LEVEL >= ft_t_info) {
311 printk(
312KERN_INFO
313"(c) 1996, 1997 Claus-Justus Heine (claus@momo.math.rwth-aachen.de)\n"
314KERN_INFO
315"vfs interface for ftape floppy tape driver.\n"
316KERN_INFO
317"Support for QIC-113 compatible volume table, dynamic memory allocation\n"
318KERN_INFO
319"and builtin compression (lzrw3 algorithm).\n");
320 }
321#else /* !MODULE */
322 /* print a short no-nonsense boot message */
323 printk(KERN_INFO ZFTAPE_VERSION "\n");
324#endif /* MODULE */
325 TRACE(ft_t_info, "zft_init @ 0x%p", zft_init);
326 TRACE(ft_t_info,
327 "installing zftape VFS interface for ftape driver ...");
328 TRACE_CATCH(register_chrdev(QIC117_TAPE_MAJOR, "zft", &zft_cdev),);
329
330 zft_class = class_create(THIS_MODULE, "zft");
331 for (i = 0; i < 4; i++) {
332 class_device_create(zft_class, NULL, MKDEV(QIC117_TAPE_MAJOR, i), NULL, "qft%i", i);
333 class_device_create(zft_class, NULL, MKDEV(QIC117_TAPE_MAJOR, i + 4), NULL, "nqft%i", i);
334 class_device_create(zft_class, NULL, MKDEV(QIC117_TAPE_MAJOR, i + 16), NULL, "zqft%i", i);
335 class_device_create(zft_class, NULL, MKDEV(QIC117_TAPE_MAJOR, i + 20), NULL, "nzqft%i", i);
336 class_device_create(zft_class, NULL, MKDEV(QIC117_TAPE_MAJOR, i + 32), NULL, "rawqft%i", i);
337 class_device_create(zft_class, NULL, MKDEV(QIC117_TAPE_MAJOR, i + 36), NULL, "nrawrawqft%i", i);
338 }
339
340#ifdef CONFIG_ZFT_COMPRESSOR
341 (void)zft_compressor_init();
342#endif
343 zft_status = ftape_get_status(); /* fetch global data of ftape
344 * hardware driver
345 */
346 TRACE_EXIT 0;
347}
348
349
350/* Called by modules package when removing the driver
351 */
352static void zft_exit(void)
353{
354 int i;
355 TRACE_FUN(ft_t_flow);
356
357 if (unregister_chrdev(QIC117_TAPE_MAJOR, "zft") != 0) {
358 TRACE(ft_t_warn, "failed");
359 } else {
360 TRACE(ft_t_info, "successful");
361 }
362 for (i = 0; i < 4; i++) {
363 class_device_destroy(zft_class, MKDEV(QIC117_TAPE_MAJOR, i));
364 class_device_destroy(zft_class, MKDEV(QIC117_TAPE_MAJOR, i + 4));
365 class_device_destroy(zft_class, MKDEV(QIC117_TAPE_MAJOR, i + 16));
366 class_device_destroy(zft_class, MKDEV(QIC117_TAPE_MAJOR, i + 20));
367 class_device_destroy(zft_class, MKDEV(QIC117_TAPE_MAJOR, i + 32));
368 class_device_destroy(zft_class, MKDEV(QIC117_TAPE_MAJOR, i + 36));
369 }
370 class_destroy(zft_class);
371 zft_uninit_mem(); /* release remaining memory, if any */
372 printk(KERN_INFO "zftape successfully unloaded.\n");
373 TRACE_EXIT;
374}
375
376module_init(zft_init);
377module_exit(zft_exit);
diff --git a/drivers/char/ftape/zftape/zftape-init.h b/drivers/char/ftape/zftape/zftape-init.h
deleted file mode 100644
index 937e5d48c20e..000000000000
--- a/drivers/char/ftape/zftape/zftape-init.h
+++ /dev/null
@@ -1,77 +0,0 @@
1#ifndef _ZFTAPE_INIT_H
2#define _ZFTAPE_INIT_H
3
4/*
5 * Copyright (C) 1996, 1997 Claus Heine.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-init.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:19:05 $
25 *
26 * This file contains definitions and macro for the vfs
27 * interface defined by zftape
28 *
29 */
30
31#include <linux/ftape-header-segment.h>
32
33#include "../lowlevel/ftape-tracing.h"
34#include "../lowlevel/ftape-ctl.h"
35#include "../lowlevel/ftape-read.h"
36#include "../lowlevel/ftape-write.h"
37#include "../lowlevel/ftape-bsm.h"
38#include "../lowlevel/ftape-io.h"
39#include "../lowlevel/ftape-buffer.h"
40#include "../lowlevel/ftape-format.h"
41
42#include "../zftape/zftape-rw.h"
43
44#ifdef MODULE
45#define ftape_status (*zft_status)
46#endif
47
48extern const ftape_info *zft_status; /* needed for zftape-vtbl.h */
49
50#include "../zftape/zftape-vtbl.h"
51
52struct zft_cmpr_ops {
53 int (*write)(int *write_cnt,
54 __u8 *dst_buf, const int seg_sz,
55 const __u8 __user *src_buf, const int req_len,
56 const zft_position *pos, const zft_volinfo *volume);
57 int (*read)(int *read_cnt,
58 __u8 __user *dst_buf, const int req_len,
59 const __u8 *src_buf, const int seg_sz,
60 const zft_position *pos, const zft_volinfo *volume);
61 int (*seek)(unsigned int new_block_pos,
62 zft_position *pos, const zft_volinfo *volume,
63 __u8 *buffer);
64 void (*lock) (void);
65 void (*reset) (void);
66 void (*cleanup)(void);
67};
68
69extern struct zft_cmpr_ops *zft_cmpr_ops;
70/* zftape-init.c defined global functions.
71 */
72extern int zft_cmpr_register(struct zft_cmpr_ops *new_ops);
73extern int zft_cmpr_lock(int try_to_load);
74
75#endif
76
77
diff --git a/drivers/char/ftape/zftape/zftape-read.c b/drivers/char/ftape/zftape/zftape-read.c
deleted file mode 100644
index 214bf03dce68..000000000000
--- a/drivers/char/ftape/zftape/zftape-read.c
+++ /dev/null
@@ -1,377 +0,0 @@
1/*
2 * Copyright (C) 1996, 1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-read.c,v $
20 * $Revision: 1.2 $
21 * $Date: 1997/10/05 19:19:06 $
22 *
23 * This file contains the high level reading code
24 * for the QIC-117 floppy-tape driver for Linux.
25 */
26
27#include <linux/errno.h>
28#include <linux/mm.h>
29
30#include <linux/zftape.h>
31
32#include <asm/uaccess.h>
33
34#include "../zftape/zftape-init.h"
35#include "../zftape/zftape-eof.h"
36#include "../zftape/zftape-ctl.h"
37#include "../zftape/zftape-write.h"
38#include "../zftape/zftape-read.h"
39#include "../zftape/zftape-rw.h"
40#include "../zftape/zftape-vtbl.h"
41
42/* Global vars.
43 */
44int zft_just_before_eof;
45
46/* Local vars.
47 */
48static int buf_len_rd;
49
50void zft_zap_read_buffers(void)
51{
52 buf_len_rd = 0;
53}
54
55int zft_read_header_segments(void)
56{
57 TRACE_FUN(ft_t_flow);
58
59 zft_header_read = 0;
60 TRACE_CATCH(zft_vmalloc_once(&zft_hseg_buf, FT_SEGMENT_SIZE),);
61 TRACE_CATCH(ftape_read_header_segment(zft_hseg_buf),);
62 TRACE(ft_t_info, "Segments written since first format: %d",
63 (int)GET4(zft_hseg_buf, FT_SEG_CNT));
64 zft_qic113 = (ft_format_code != fmt_normal &&
65 ft_format_code != fmt_1100ft &&
66 ft_format_code != fmt_425ft);
67 TRACE(ft_t_info, "ft_first_data_segment: %d, ft_last_data_segment: %d",
68 ft_first_data_segment, ft_last_data_segment);
69 zft_capacity = zft_get_capacity();
70 zft_old_ftape = zft_ftape_validate_label(&zft_hseg_buf[FT_LABEL]);
71 if (zft_old_ftape) {
72 TRACE(ft_t_info,
73"Found old ftaped tape, emulating eof marks, entering read-only mode");
74 zft_ftape_extract_file_marks(zft_hseg_buf);
75 TRACE_CATCH(zft_fake_volume_headers(zft_eof_map,
76 zft_nr_eof_marks),);
77 } else {
78 /* the specs say that the volume table must be
79 * initialized with zeroes during formatting, so it
80 * MUST be readable, i.e. contain vaid ECC
81 * information.
82 */
83 TRACE_CATCH(ftape_read_segment(ft_first_data_segment,
84 zft_deblock_buf,
85 FT_RD_SINGLE),);
86 TRACE_CATCH(zft_extract_volume_headers(zft_deblock_buf),);
87 }
88 zft_header_read = 1;
89 zft_set_flags(zft_unit);
90 zft_reset_position(&zft_pos);
91 TRACE_EXIT 0;
92}
93
94int zft_fetch_segment_fraction(const unsigned int segment, void *buffer,
95 const ft_read_mode_t read_mode,
96 const unsigned int start,
97 const unsigned int size)
98{
99 int seg_sz;
100 TRACE_FUN(ft_t_flow);
101
102 if (segment == zft_deblock_segment) {
103 TRACE(ft_t_data_flow,
104 "re-using segment %d already in deblock buffer",
105 segment);
106 seg_sz = zft_get_seg_sz(segment);
107 if (start > seg_sz) {
108 TRACE_ABORT(-EINVAL, ft_t_bug,
109 "trying to read beyond end of segment:\n"
110 KERN_INFO "seg_sz : %d\n"
111 KERN_INFO "start : %d\n"
112 KERN_INFO "segment: %d",
113 seg_sz, start, segment);
114 }
115 if ((start + size) > seg_sz) {
116 TRACE_EXIT seg_sz - start;
117 }
118 TRACE_EXIT size;
119 }
120 seg_sz = ftape_read_segment_fraction(segment, buffer, read_mode,
121 start, size);
122 TRACE(ft_t_data_flow, "segment %d, result %d", segment, seg_sz);
123 if ((int)seg_sz >= 0 && start == 0 && size == FT_SEGMENT_SIZE) {
124 /* this implicitly assumes that we are always called with
125 * buffer == zft_deblock_buf
126 */
127 zft_deblock_segment = segment;
128 } else {
129 zft_deblock_segment = -1;
130 }
131 TRACE_EXIT seg_sz;
132}
133
134/*
135 * out:
136 *
137 * int *read_cnt: the number of bytes we removed from the
138 * zft_deblock_buf (result)
139 *
140 * int *to_do : the remaining size of the read-request. Is changed.
141 *
142 * in:
143 *
144 * char *buff : buff is the address of the upper part of the user
145 * buffer, that hasn't been filled with data yet.
146 * int buf_pos_read: copy of buf_pos_rd
147 * int buf_len_read: copy of buf_len_rd
148 * char *zft_deblock_buf: ftape_zft_deblock_buf
149 *
150 * returns the amount of data actually copied to the user-buffer
151 *
152 * to_do MUST NOT SHRINK except to indicate an EOT. In this case to_do
153 * has to be set to 0. We cannot return -ENOSPC, because we return the
154 * amount of data actually * copied to the user-buffer
155 */
156static int zft_simple_read (int *read_cnt,
157 __u8 __user *dst_buf,
158 const int to_do,
159 const __u8 *src_buf,
160 const int seg_sz,
161 const zft_position *pos,
162 const zft_volinfo *volume)
163{
164 TRACE_FUN(ft_t_flow);
165
166 if (seg_sz - pos->seg_byte_pos < to_do) {
167 *read_cnt = seg_sz - pos->seg_byte_pos;
168 } else {
169 *read_cnt = to_do;
170 }
171 if (copy_to_user(dst_buf,
172 src_buf + pos->seg_byte_pos, *read_cnt) != 0) {
173 TRACE_EXIT -EFAULT;
174 }
175 TRACE(ft_t_noise, "nr bytes just read: %d", *read_cnt);
176 TRACE_EXIT *read_cnt;
177}
178
179/* req_len: gets clipped due to EOT of EOF.
180 * req_clipped: is a flag indicating whether req_len was clipped or not
181 * volume: contains information on current volume (blk_sz etc.)
182 */
183static int check_read_access(int *req_len,
184 const zft_volinfo **volume,
185 int *req_clipped,
186 const zft_position *pos)
187{
188 static __s64 remaining;
189 static int eod;
190 TRACE_FUN(ft_t_flow);
191
192 if (zft_io_state != zft_reading) {
193 if (zft_offline) { /* offline includes no_tape */
194 TRACE_ABORT(-ENXIO, ft_t_warn,
195 "tape is offline or no cartridge");
196 }
197 if (!ft_formatted) {
198 TRACE_ABORT(-EACCES,
199 ft_t_warn, "tape is not formatted");
200 }
201 /* now enter defined state, read header segment if not
202 * already done and flush write buffers
203 */
204 TRACE_CATCH(zft_def_idle_state(),);
205 zft_io_state = zft_reading;
206 if (zft_tape_at_eod(pos)) {
207 eod = 1;
208 TRACE_EXIT 1;
209 }
210 eod = 0;
211 *volume = zft_find_volume(pos->seg_pos);
212 /* get the space left until EOF */
213 remaining = zft_check_for_eof(*volume, pos);
214 buf_len_rd = 0;
215 TRACE(ft_t_noise, "remaining: " LL_X ", vol_no: %d",
216 LL(remaining), (*volume)->count);
217 } else if (zft_tape_at_eod(pos)) {
218 if (++eod > 2) {
219 TRACE_EXIT -EIO; /* st.c also returns -EIO */
220 } else {
221 TRACE_EXIT 1;
222 }
223 }
224 if ((*req_len % (*volume)->blk_sz) != 0) {
225 /* this message is informational only. The user gets the
226 * proper return value
227 */
228 TRACE_ABORT(-EINVAL, ft_t_info,
229 "req_len %d not a multiple of block size %d",
230 *req_len, (*volume)->blk_sz);
231 }
232 /* As GNU tar doesn't accept partial read counts when the
233 * multiple volume flag is set, we make sure to return the
234 * requested amount of data. Except, of course, at the end of
235 * the tape or file mark.
236 */
237 remaining -= *req_len;
238 if (remaining <= 0) {
239 TRACE(ft_t_noise,
240 "clipped request from %d to %d.",
241 *req_len, (int)(*req_len + remaining));
242 *req_len += remaining;
243 *req_clipped = 1;
244 } else {
245 *req_clipped = 0;
246 }
247 TRACE_EXIT 0;
248}
249
250/* this_segs_size: the current segment's size.
251 * buff: the USER-SPACE buffer provided by the calling function.
252 * req_len: how much data should be read at most.
253 * volume: contains information on current volume (blk_sz etc.)
254 */
255static int empty_deblock_buf(__u8 __user *usr_buf, const int req_len,
256 const __u8 *src_buf, const int seg_sz,
257 zft_position *pos,
258 const zft_volinfo *volume)
259{
260 int cnt;
261 int result = 0;
262 TRACE_FUN(ft_t_flow);
263
264 TRACE(ft_t_data_flow, "this_segs_size: %d", seg_sz);
265 if (zft_use_compression && volume->use_compression) {
266 TRACE_CATCH(zft_cmpr_lock(1 /* try to load */),);
267 TRACE_CATCH(result= (*zft_cmpr_ops->read)(&cnt,
268 usr_buf, req_len,
269 src_buf, seg_sz,
270 pos, volume),);
271 } else {
272 TRACE_CATCH(result= zft_simple_read (&cnt,
273 usr_buf, req_len,
274 src_buf, seg_sz,
275 pos, volume),);
276 }
277 pos->volume_pos += result;
278 pos->tape_pos += cnt;
279 pos->seg_byte_pos += cnt;
280 buf_len_rd -= cnt; /* remaining bytes in buffer */
281 TRACE(ft_t_data_flow, "buf_len_rd: %d, cnt: %d", buf_len_rd, cnt);
282 if(pos->seg_byte_pos >= seg_sz) {
283 pos->seg_pos++;
284 pos->seg_byte_pos = 0;
285 }
286 TRACE(ft_t_data_flow, "bytes moved out of deblock-buffer: %d", cnt);
287 TRACE_EXIT result;
288}
289
290
291/* note: we store the segment id of the segment that is inside the
292 * deblock buffer. This spares a lot of ftape_read_segment()s when we
293 * use small block-sizes. The block-size may be 1kb (SECTOR_SIZE). In
294 * this case a MTFSR 28 maybe still inside the same segment.
295 */
296int _zft_read(char __user *buff, int req_len)
297{
298 int req_clipped;
299 int result = 0;
300 int bytes_read = 0;
301 static unsigned int seg_sz = 0;
302 static const zft_volinfo *volume = NULL;
303 TRACE_FUN(ft_t_flow);
304
305 zft_resid = req_len;
306 result = check_read_access(&req_len, &volume,
307 &req_clipped, &zft_pos);
308 switch(result) {
309 case 0:
310 break; /* nothing special */
311 case 1:
312 TRACE(ft_t_noise, "EOD reached");
313 TRACE_EXIT 0; /* EOD */
314 default:
315 TRACE_ABORT(result, ft_t_noise,
316 "check_read_access() failed with result %d",
317 result);
318 TRACE_EXIT result;
319 }
320 while (req_len > 0) {
321 /* Allow escape from this loop on signal !
322 */
323 FT_SIGNAL_EXIT(_DONT_BLOCK);
324 /* buf_len_rd == 0 means that we need to read a new
325 * segment.
326 */
327 if (buf_len_rd == 0) {
328 while((result = zft_fetch_segment(zft_pos.seg_pos,
329 zft_deblock_buf,
330 FT_RD_AHEAD)) == 0) {
331 zft_pos.seg_pos ++;
332 zft_pos.seg_byte_pos = 0;
333 }
334 if (result < 0) {
335 zft_resid -= bytes_read;
336 TRACE_ABORT(result, ft_t_noise,
337 "zft_fetch_segment(): %d",
338 result);
339 }
340 seg_sz = result;
341 buf_len_rd = seg_sz - zft_pos.seg_byte_pos;
342 }
343 TRACE_CATCH(result = empty_deblock_buf(buff,
344 req_len,
345 zft_deblock_buf,
346 seg_sz,
347 &zft_pos,
348 volume),
349 zft_resid -= bytes_read);
350 TRACE(ft_t_data_flow, "bytes just read: %d", result);
351 bytes_read += result; /* what we got so far */
352 buff += result; /* index in user-buffer */
353 req_len -= result; /* what's left from req_len */
354 } /* while (req_len > 0) */
355 if (req_clipped) {
356 TRACE(ft_t_data_flow,
357 "maybe partial count because of eof mark");
358 if (zft_just_before_eof && bytes_read == 0) {
359 /* req_len was > 0, but user didn't get
360 * anything the user has read in the eof-mark
361 */
362 zft_move_past_eof(&zft_pos);
363 ftape_abort_operation();
364 } else {
365 /* don't skip to the next file before the user
366 * tried to read a second time past EOF Just
367 * mark that we are at EOF and maybe decrement
368 * zft_seg_pos to stay in the same volume;
369 */
370 zft_just_before_eof = 1;
371 zft_position_before_eof(&zft_pos, volume);
372 TRACE(ft_t_noise, "just before eof");
373 }
374 }
375 zft_resid -= result; /* for MTSTATUS */
376 TRACE_EXIT bytes_read;
377}
diff --git a/drivers/char/ftape/zftape/zftape-read.h b/drivers/char/ftape/zftape/zftape-read.h
deleted file mode 100644
index 42941de0c23a..000000000000
--- a/drivers/char/ftape/zftape/zftape-read.h
+++ /dev/null
@@ -1,53 +0,0 @@
1#ifndef _ZFTAPE_READ_H
2#define _ZFTAPE_READ_H
3
4/*
5 * Copyright (C) 1996, 1997 Claus-Justus Heine
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-read.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:19:07 $
25 *
26 * This file contains the definitions for the read functions
27 * for the zftape driver for Linux.
28 *
29 */
30
31#include "../lowlevel/ftape-read.h"
32
33/* ftape-read.c defined global vars.
34 */
35extern int zft_just_before_eof;
36
37/* ftape-read.c defined global functions.
38 */
39extern void zft_zap_read_buffers(void);
40extern int zft_read_header_segments(void);
41extern int zft_fetch_segment_fraction(const unsigned int segment,
42 void *buffer,
43 const ft_read_mode_t read_mode,
44 const unsigned int start,
45 const unsigned int size);
46#define zft_fetch_segment(segment, address, read_mode) \
47 zft_fetch_segment_fraction(segment, address, read_mode, \
48 0, FT_SEGMENT_SIZE)
49/* hook for the VFS interface
50 */
51extern int _zft_read(char __user *buff, int req_len);
52
53#endif /* _ZFTAPE_READ_H */
diff --git a/drivers/char/ftape/zftape/zftape-rw.c b/drivers/char/ftape/zftape/zftape-rw.c
deleted file mode 100644
index dab634686885..000000000000
--- a/drivers/char/ftape/zftape/zftape-rw.c
+++ /dev/null
@@ -1,375 +0,0 @@
1/*
2 * Copyright (C) 1996, 1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-rw.c,v $
20 * $Revision: 1.2 $
21 * $Date: 1997/10/05 19:19:08 $
22 *
23 * This file contains some common code for the r/w code for
24 * zftape.
25 */
26
27#include <linux/errno.h>
28#include <linux/mm.h>
29
30#include <linux/zftape.h>
31#include "../zftape/zftape-init.h"
32#include "../zftape/zftape-eof.h"
33#include "../zftape/zftape-ctl.h"
34#include "../zftape/zftape-write.h"
35#include "../zftape/zftape-read.h"
36#include "../zftape/zftape-rw.h"
37#include "../zftape/zftape-vtbl.h"
38
39/* Global vars.
40 */
41
42__u8 *zft_deblock_buf;
43__u8 *zft_hseg_buf;
44int zft_deblock_segment = -1;
45zft_status_enum zft_io_state = zft_idle;
46int zft_header_changed;
47int zft_qic113; /* conform to old specs. and old zftape */
48int zft_use_compression;
49zft_position zft_pos = {
50 -1, /* seg_pos */
51 0, /* seg_byte_pos */
52 0, /* tape_pos */
53 0 /* volume_pos */
54};
55unsigned int zft_blk_sz = CONFIG_ZFT_DFLT_BLK_SZ;
56__s64 zft_capacity;
57
58unsigned int zft_written_segments;
59int zft_label_changed;
60
61/* Local vars.
62 */
63
64unsigned int zft_get_seg_sz(unsigned int segment)
65{
66 int size;
67 TRACE_FUN(ft_t_any);
68
69 size = FT_SEGMENT_SIZE -
70 count_ones(ftape_get_bad_sector_entry(segment))*FT_SECTOR_SIZE;
71 if (size > 0) {
72 TRACE_EXIT (unsigned)size;
73 } else {
74 TRACE_EXIT 0;
75 }
76}
77
78/* ftape_set_flags(). Claus-Justus Heine, 1994/1995
79 */
80void zft_set_flags(unsigned minor_unit)
81{
82 TRACE_FUN(ft_t_flow);
83
84 zft_use_compression = zft_qic_mode = 0;
85 switch (minor_unit & ZFT_MINOR_OP_MASK) {
86 case (ZFT_Q80_MODE | ZFT_ZIP_MODE):
87 case ZFT_ZIP_MODE:
88 zft_use_compression = 1;
89 case 0:
90 case ZFT_Q80_MODE:
91 zft_qic_mode = 1;
92 if (zft_mt_compression) { /* override the default */
93 zft_use_compression = 1;
94 }
95 break;
96 case ZFT_RAW_MODE:
97 TRACE(ft_t_noise, "switching to raw mode");
98 break;
99 default:
100 TRACE(ft_t_warn, "Warning:\n"
101 KERN_INFO "Wrong combination of minor device bits.\n"
102 KERN_INFO "Switching to raw read-only mode.");
103 zft_write_protected = 1;
104 break;
105 }
106 TRACE_EXIT;
107}
108
109/* computes the segment and byte offset inside the segment
110 * corresponding to tape_pos.
111 *
112 * tape_pos gives the offset in bytes from the beginning of the
113 * ft_first_data_segment *seg_byte_pos is the offset in the current
114 * segment in bytes
115 *
116 * Of, if this routine was called often one should cache the last data
117 * pos it was called with, but actually this is only needed in
118 * ftape_seek_block(), that is, almost never.
119 */
120int zft_calc_seg_byte_coord(int *seg_byte_pos, __s64 tape_pos)
121{
122 int segment;
123 int seg_sz;
124 TRACE_FUN(ft_t_flow);
125
126 if (tape_pos == 0) {
127 *seg_byte_pos = 0;
128 segment = ft_first_data_segment;
129 } else {
130 seg_sz = 0;
131
132 for (segment = ft_first_data_segment;
133 ((tape_pos > 0) && (segment <= ft_last_data_segment));
134 segment++) {
135 seg_sz = zft_get_seg_sz(segment);
136 tape_pos -= seg_sz;
137 }
138 if(tape_pos >= 0) {
139 /* the case tape_pos > != 0 means that the
140 * argument tape_pos lies beyond the EOT.
141 */
142 *seg_byte_pos= 0;
143 } else { /* tape_pos < 0 */
144 segment--;
145 *seg_byte_pos= tape_pos + seg_sz;
146 }
147 }
148 TRACE_EXIT(segment);
149}
150
151/* ftape_calc_tape_pos().
152 *
153 * computes the offset in bytes from the beginning of the
154 * ft_first_data_segment inverse to ftape_calc_seg_byte_coord
155 *
156 * We should do some caching. But how:
157 *
158 * Each time the header segments are read in, this routine is called
159 * with ft_tracks_per_tape*segments_per_track argumnet. So this should be
160 * the time to reset the cache.
161 *
162 * Also, it might be in the future that the bad sector map gets
163 * changed. -> reset the cache
164 */
165static int seg_pos;
166static __s64 tape_pos;
167
168__s64 zft_get_capacity(void)
169{
170 seg_pos = ft_first_data_segment;
171 tape_pos = 0;
172
173 while (seg_pos <= ft_last_data_segment) {
174 tape_pos += zft_get_seg_sz(seg_pos ++);
175 }
176 return tape_pos;
177}
178
179__s64 zft_calc_tape_pos(int segment)
180{
181 int d1, d2, d3;
182 TRACE_FUN(ft_t_any);
183
184 if (segment > ft_last_data_segment) {
185 TRACE_EXIT zft_capacity;
186 }
187 if (segment < ft_first_data_segment) {
188 TRACE_EXIT 0;
189 }
190 d2 = segment - seg_pos;
191 if (-d2 > 10) {
192 d1 = segment - ft_first_data_segment;
193 if (-d2 > d1) {
194 tape_pos = 0;
195 seg_pos = ft_first_data_segment;
196 d2 = d1;
197 }
198 }
199 if (d2 > 10) {
200 d3 = ft_last_data_segment - segment;
201 if (d2 > d3) {
202 tape_pos = zft_capacity;
203 seg_pos = ft_last_data_segment + 1;
204 d2 = -d3;
205 }
206 }
207 if (d2 > 0) {
208 while (seg_pos < segment) {
209 tape_pos += zft_get_seg_sz(seg_pos++);
210 }
211 } else {
212 while (seg_pos > segment) {
213 tape_pos -= zft_get_seg_sz(--seg_pos);
214 }
215 }
216 TRACE(ft_t_noise, "new cached pos: %d", seg_pos);
217
218 TRACE_EXIT tape_pos;
219}
220
221/* copy Z-label string to buffer, keeps track of the correct offset in
222 * `buffer'
223 */
224void zft_update_label(__u8 *buffer)
225{
226 TRACE_FUN(ft_t_flow);
227
228 if (strncmp(&buffer[FT_LABEL], ZFTAPE_LABEL,
229 sizeof(ZFTAPE_LABEL)-1) != 0) {
230 TRACE(ft_t_info, "updating label from \"%s\" to \"%s\"",
231 &buffer[FT_LABEL], ZFTAPE_LABEL);
232 strcpy(&buffer[FT_LABEL], ZFTAPE_LABEL);
233 memset(&buffer[FT_LABEL] + sizeof(ZFTAPE_LABEL) - 1, ' ',
234 FT_LABEL_SZ - sizeof(ZFTAPE_LABEL + 1));
235 PUT4(buffer, FT_LABEL_DATE, 0);
236 zft_label_changed = zft_header_changed = 1; /* changed */
237 }
238 TRACE_EXIT;
239}
240
241int zft_verify_write_segments(unsigned int segment,
242 __u8 *data, size_t size,
243 __u8 *buffer)
244{
245 int result;
246 __u8 *write_buf;
247 __u8 *src_buf;
248 int single;
249 int seg_pos;
250 int seg_sz;
251 int remaining;
252 ft_write_mode_t write_mode;
253 TRACE_FUN(ft_t_flow);
254
255 seg_pos = segment;
256 seg_sz = zft_get_seg_sz(seg_pos);
257 src_buf = data;
258 single = size <= seg_sz;
259 remaining = size;
260 do {
261 TRACE(ft_t_noise, "\n"
262 KERN_INFO "remaining: %d\n"
263 KERN_INFO "seg_sz : %d\n"
264 KERN_INFO "segment : %d",
265 remaining, seg_sz, seg_pos);
266 if (remaining == seg_sz) {
267 write_buf = src_buf;
268 write_mode = single ? FT_WR_SINGLE : FT_WR_MULTI;
269 remaining = 0;
270 } else if (remaining > seg_sz) {
271 write_buf = src_buf;
272 write_mode = FT_WR_ASYNC; /* don't start tape */
273 remaining -= seg_sz;
274 } else { /* remaining < seg_sz */
275 write_buf = buffer;
276 memcpy(write_buf, src_buf, remaining);
277 memset(&write_buf[remaining],'\0',seg_sz-remaining);
278 write_mode = single ? FT_WR_SINGLE : FT_WR_MULTI;
279 remaining = 0;
280 }
281 if ((result = ftape_write_segment(seg_pos,
282 write_buf,
283 write_mode)) != seg_sz) {
284 TRACE(ft_t_err, "Error: "
285 "Couldn't write segment %d", seg_pos);
286 TRACE_EXIT result < 0 ? result : -EIO; /* bail out */
287 }
288 zft_written_segments ++;
289 seg_sz = zft_get_seg_sz(++seg_pos);
290 src_buf += result;
291 } while (remaining > 0);
292 if (ftape_get_status()->fti_state == writing) {
293 TRACE_CATCH(ftape_loop_until_writes_done(),);
294 TRACE_CATCH(ftape_abort_operation(),);
295 zft_prevent_flush();
296 }
297 seg_pos = segment;
298 src_buf = data;
299 remaining = size;
300 do {
301 TRACE_CATCH(result = ftape_read_segment(seg_pos, buffer,
302 single ? FT_RD_SINGLE
303 : FT_RD_AHEAD),);
304 if (memcmp(src_buf, buffer,
305 remaining > result ? result : remaining) != 0) {
306 TRACE_ABORT(-EIO, ft_t_err,
307 "Failed to verify written segment %d",
308 seg_pos);
309 }
310 remaining -= result;
311 TRACE(ft_t_noise, "verify successful:\n"
312 KERN_INFO "segment : %d\n"
313 KERN_INFO "segsize : %d\n"
314 KERN_INFO "remaining: %d",
315 seg_pos, result, remaining);
316 src_buf += seg_sz;
317 seg_pos++;
318 } while (remaining > 0);
319 TRACE_EXIT size;
320}
321
322
323/* zft_erase(). implemented compression-handling
324 *
325 * calculate the first data-segment when using/not using compression.
326 *
327 * update header-segment and compression-map-segment.
328 */
329int zft_erase(void)
330{
331 int result = 0;
332 TRACE_FUN(ft_t_flow);
333
334 if (!zft_header_read) {
335 TRACE_CATCH(zft_vmalloc_once((void **)&zft_hseg_buf,
336 FT_SEGMENT_SIZE),);
337 /* no need to read the vtbl and compression map */
338 TRACE_CATCH(ftape_read_header_segment(zft_hseg_buf),);
339 if ((zft_old_ftape =
340 zft_ftape_validate_label(&zft_hseg_buf[FT_LABEL]))) {
341 zft_ftape_extract_file_marks(zft_hseg_buf);
342 }
343 TRACE(ft_t_noise,
344 "ft_first_data_segment: %d, ft_last_data_segment: %d",
345 ft_first_data_segment, ft_last_data_segment);
346 zft_qic113 = (ft_format_code != fmt_normal &&
347 ft_format_code != fmt_1100ft &&
348 ft_format_code != fmt_425ft);
349 }
350 if (zft_old_ftape) {
351 zft_clear_ftape_file_marks();
352 zft_old_ftape = 0; /* no longer old ftape */
353 }
354 PUT2(zft_hseg_buf, FT_CMAP_START, 0);
355 zft_volume_table_changed = 1;
356 zft_capacity = zft_get_capacity();
357 zft_init_vtbl();
358 /* the rest must be done in ftape_update_header_segments
359 */
360 zft_header_read = 1;
361 zft_header_changed = 1; /* force update of timestamp */
362 result = zft_update_header_segments();
363
364 ftape_abort_operation();
365
366 zft_reset_position(&zft_pos);
367 zft_set_flags (zft_unit);
368 TRACE_EXIT result;
369}
370
371unsigned int zft_get_time(void)
372{
373 unsigned int date = FT_TIME_STAMP(2097, 11, 30, 23, 59, 59); /* fun */
374 return date;
375}
diff --git a/drivers/char/ftape/zftape/zftape-rw.h b/drivers/char/ftape/zftape/zftape-rw.h
deleted file mode 100644
index 1ceec22b60bd..000000000000
--- a/drivers/char/ftape/zftape/zftape-rw.h
+++ /dev/null
@@ -1,101 +0,0 @@
1#ifndef _ZFTAPE_RW_H
2#define _ZFTAPE_RW_H
3
4/*
5 * Copyright (C) 1996, 1997 Claus-Justus Heine.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-rw.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:19:09 $
25 *
26 * This file contains the definitions for the read and write
27 * functions for the QIC-117 floppy-tape driver for Linux.
28 *
29 */
30
31#include "../zftape/zftape-buffers.h"
32
33#define SEGMENTS_PER_TAPE (ft_segments_per_track * ft_tracks_per_tape)
34
35/* QIC-113 Rev. G says that `a maximum of 63488 raw bytes may be
36 * compressed into a single frame'.
37 * Maybe we should stick to 32kb to make it more `beautiful'
38 */
39#define ZFT_MAX_BLK_SZ (62*1024) /* bytes */
40#if !defined(CONFIG_ZFT_DFLT_BLK_SZ)
41# define CONFIG_ZFT_DFLT_BLK_SZ (10*1024) /* bytes, default of gnu tar */
42#elif CONFIG_ZFT_DFLT_BLK_SZ == 0
43# undef CONFIG_ZFT_DFLT_BLK_SZ
44# define CONFIG_ZFT_DFLT_BLK_SZ 1
45#elif (CONFIG_ZFT_DFLT_BLK_SZ % 1024) != 0
46# error CONFIG_ZFT_DFLT_BLK_SZ must be 1 or a multiple of 1024
47#endif
48/* The *optional* compression routines need some overhead per tape
49 * block for their purposes. Instead of asking the actual compression
50 * implementation how much it needs, we restrict this overhead to be
51 * maximal of ZFT_CMPT_OVERHEAD size. We need this for EOT
52 * conditions. The tape is assumed to be logical at EOT when the
53 * distance from the physical EOT is less than
54 * one tape block + ZFT_CMPR_OVERHEAD
55 */
56#define ZFT_CMPR_OVERHEAD 16 /* bytes */
57
58typedef enum
59{
60 zft_idle = 0,
61 zft_reading,
62 zft_writing,
63} zft_status_enum;
64
65typedef struct /* all values measured in bytes */
66{
67 int seg_pos; /* segment currently positioned at */
68 int seg_byte_pos; /* offset in current segment */
69 __s64 tape_pos; /* real offset from BOT */
70 __s64 volume_pos; /* pos. in uncompressed data stream in
71 * current volume
72 */
73} zft_position;
74
75extern zft_position zft_pos;
76extern __u8 *zft_deblock_buf;
77extern __u8 *zft_hseg_buf;
78extern int zft_deblock_segment;
79extern zft_status_enum zft_io_state;
80extern int zft_header_changed;
81extern int zft_qic113; /* conform to old specs. and old zftape */
82extern int zft_use_compression;
83extern unsigned int zft_blk_sz;
84extern __s64 zft_capacity;
85extern unsigned int zft_written_segments;
86extern int zft_label_changed;
87
88/* zftape-rw.c exported functions
89 */
90extern unsigned int zft_get_seg_sz(unsigned int segment);
91extern void zft_set_flags(unsigned int minor_unit);
92extern int zft_calc_seg_byte_coord(int *seg_byte_pos, __s64 tape_pos);
93extern __s64 zft_calc_tape_pos(int segment);
94extern __s64 zft_get_capacity(void);
95extern void zft_update_label(__u8 *buffer);
96extern int zft_erase(void);
97extern int zft_verify_write_segments(unsigned int segment,
98 __u8 *data, size_t size, __u8 *buffer);
99extern unsigned int zft_get_time(void);
100#endif /* _ZFTAPE_RW_H */
101
diff --git a/drivers/char/ftape/zftape/zftape-vtbl.c b/drivers/char/ftape/zftape/zftape-vtbl.c
deleted file mode 100644
index ad7f8be6340b..000000000000
--- a/drivers/char/ftape/zftape/zftape-vtbl.c
+++ /dev/null
@@ -1,757 +0,0 @@
1/*
2 * Copyright (c) 1995-1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or
5 modify it under the terms of the GNU General Public License as
6 published by the Free Software Foundation; either version 2, or (at
7 your option) any later version.
8
9 This program is distributed in the hope that it will be useful, but
10 WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
17 USA.
18
19 *
20 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-vtbl.c,v $
21 * $Revision: 1.7.6.1 $
22 * $Date: 1997/11/24 13:48:31 $
23 *
24 * This file defines a volume table as defined in various QIC
25 * standards.
26 *
27 * This is a minimal implementation, just allowing ordinary DOS
28 * :( prgrams to identify the cartridge as used.
29 */
30
31#include <linux/errno.h>
32#include <linux/mm.h>
33#include <linux/slab.h>
34
35#include <linux/zftape.h>
36#include "../zftape/zftape-init.h"
37#include "../zftape/zftape-eof.h"
38#include "../zftape/zftape-ctl.h"
39#include "../zftape/zftape-write.h"
40#include "../zftape/zftape-read.h"
41#include "../zftape/zftape-rw.h"
42#include "../zftape/zftape-vtbl.h"
43
44#define ZFT_CMAP_HACK /* leave this defined to hide the compression map */
45
46/*
47 * global variables
48 */
49int zft_qic_mode = 1; /* use the vtbl */
50int zft_old_ftape; /* prevents old ftaped tapes to be overwritten */
51int zft_volume_table_changed; /* for write_header_segments() */
52
53/*
54 * private variables (only exported for inline functions)
55 */
56LIST_HEAD(zft_vtbl);
57
58/* We could also allocate these dynamically when extracting the volume table
59 * sizeof(zft_volinfo) is about 32 or something close to that
60 */
61static zft_volinfo tape_vtbl;
62static zft_volinfo eot_vtbl;
63static zft_volinfo *cur_vtbl;
64
65static inline void zft_new_vtbl_entry(void)
66{
67 struct list_head *tmp = &zft_last_vtbl->node;
68 zft_volinfo *new = zft_kmalloc(sizeof(zft_volinfo));
69
70 list_add(&new->node, tmp);
71 new->count = zft_eom_vtbl->count ++;
72}
73
74void zft_free_vtbl(void)
75{
76 for (;;) {
77 struct list_head *tmp = zft_vtbl.prev;
78 zft_volinfo *vtbl;
79
80 if (tmp == &zft_vtbl)
81 break;
82 list_del(tmp);
83 vtbl = list_entry(tmp, zft_volinfo, node);
84 zft_kfree(vtbl, sizeof(zft_volinfo));
85 }
86 INIT_LIST_HEAD(&zft_vtbl);
87 cur_vtbl = NULL;
88}
89
90/* initialize vtbl, called by ftape_new_cartridge()
91 */
92void zft_init_vtbl(void)
93{
94 zft_volinfo *new;
95
96 zft_free_vtbl();
97
98 /* Create the two dummy vtbl entries
99 */
100 new = zft_kmalloc(sizeof(zft_volinfo));
101 list_add(&new->node, &zft_vtbl);
102 new = zft_kmalloc(sizeof(zft_volinfo));
103 list_add(&new->node, &zft_vtbl);
104 zft_head_vtbl->end_seg = ft_first_data_segment;
105 zft_head_vtbl->blk_sz = zft_blk_sz;
106 zft_head_vtbl->count = -1;
107 zft_eom_vtbl->start_seg = ft_first_data_segment + 1;
108 zft_eom_vtbl->end_seg = ft_last_data_segment + 1;
109 zft_eom_vtbl->blk_sz = zft_blk_sz;
110 zft_eom_vtbl->count = 0;
111
112 /* Reset the pointer for zft_find_volume()
113 */
114 cur_vtbl = zft_eom_vtbl;
115
116 /* initialize the dummy vtbl entries for zft_qic_mode == 0
117 */
118 eot_vtbl.start_seg = ft_last_data_segment + 1;
119 eot_vtbl.end_seg = ft_last_data_segment + 1;
120 eot_vtbl.blk_sz = zft_blk_sz;
121 eot_vtbl.count = -1;
122 tape_vtbl.start_seg = ft_first_data_segment;
123 tape_vtbl.end_seg = ft_last_data_segment;
124 tape_vtbl.blk_sz = zft_blk_sz;
125 tape_vtbl.size = zft_capacity;
126 tape_vtbl.count = 0;
127}
128
129/* check for a valid VTBL signature.
130 */
131static int vtbl_signature_valid(__u8 signature[4])
132{
133 const char *vtbl_ids[] = VTBL_IDS; /* valid signatures */
134 int j;
135
136 for (j = 0;
137 (j < NR_ITEMS(vtbl_ids)) && (memcmp(signature, vtbl_ids[j], 4) != 0);
138 j++);
139 return j < NR_ITEMS(vtbl_ids);
140}
141
142/* We used to store the block-size of the volume in the volume-label,
143 * using the keyword "blocksize". The blocksize written to the
144 * volume-label is in bytes.
145 *
146 * We use this now only for compatibility with old zftape version. We
147 * store the blocksize directly as binary number in the vendor
148 * extension part of the volume entry.
149 */
150static int check_volume_label(const char *label, int *blk_sz)
151{
152 int valid_format;
153 char *blocksize;
154 TRACE_FUN(ft_t_flow);
155
156 TRACE(ft_t_noise, "called with \"%s\" / \"%s\"", label, ZFT_VOL_NAME);
157 if (strncmp(label, ZFT_VOL_NAME, strlen(ZFT_VOL_NAME)) != 0) {
158 *blk_sz = 1; /* smallest block size that we allow */
159 valid_format = 0;
160 } else {
161 TRACE(ft_t_noise, "got old style zftape vtbl entry");
162 /* get the default blocksize */
163 /* use the kernel strstr() */
164 blocksize= strstr(label, " blocksize ");
165 if (blocksize) {
166 blocksize += strlen(" blocksize ");
167 for(*blk_sz= 0;
168 *blocksize >= '0' && *blocksize <= '9';
169 blocksize++) {
170 *blk_sz *= 10;
171 *blk_sz += *blocksize - '0';
172 }
173 if (*blk_sz > ZFT_MAX_BLK_SZ) {
174 *blk_sz= 1;
175 valid_format= 0;
176 } else {
177 valid_format = 1;
178 }
179 } else {
180 *blk_sz= 1;
181 valid_format= 0;
182 }
183 }
184 TRACE_EXIT valid_format;
185}
186
187/* check for a zftape volume
188 */
189static int check_volume(__u8 *entry, zft_volinfo *volume)
190{
191 TRACE_FUN(ft_t_flow);
192
193 if(strncmp(&entry[VTBL_EXT+EXT_ZFTAPE_SIG], ZFTAPE_SIG,
194 strlen(ZFTAPE_SIG)) == 0) {
195 TRACE(ft_t_noise, "got new style zftape vtbl entry");
196 volume->blk_sz = GET2(entry, VTBL_EXT+EXT_ZFTAPE_BLKSZ);
197 volume->qic113 = entry[VTBL_EXT+EXT_ZFTAPE_QIC113];
198 TRACE_EXIT 1;
199 } else {
200 TRACE_EXIT check_volume_label(&entry[VTBL_DESC], &volume->blk_sz);
201 }
202}
203
204
205/* create zftape specific vtbl entry, the volume bounds are inserted
206 * in the calling function, zft_create_volume_headers()
207 */
208static void create_zft_volume(__u8 *entry, zft_volinfo *vtbl)
209{
210 TRACE_FUN(ft_t_flow);
211
212 memset(entry, 0, VTBL_SIZE);
213 memcpy(&entry[VTBL_SIG], VTBL_ID, 4);
214 sprintf(&entry[VTBL_DESC], ZFT_VOL_NAME" %03d", vtbl->count);
215 entry[VTBL_FLAGS] = (VTBL_FL_NOT_VERIFIED | VTBL_FL_SEG_SPANNING);
216 entry[VTBL_M_NO] = 1; /* multi_cartridge_count */
217 strcpy(&entry[VTBL_EXT+EXT_ZFTAPE_SIG], ZFTAPE_SIG);
218 PUT2(entry, VTBL_EXT+EXT_ZFTAPE_BLKSZ, vtbl->blk_sz);
219 if (zft_qic113) {
220 PUT8(entry, VTBL_DATA_SIZE, vtbl->size);
221 entry[VTBL_CMPR] = VTBL_CMPR_UNREG;
222 if (vtbl->use_compression) { /* use compression: */
223 entry[VTBL_CMPR] |= VTBL_CMPR_USED;
224 }
225 entry[VTBL_EXT+EXT_ZFTAPE_QIC113] = 1;
226 } else {
227 PUT4(entry, VTBL_DATA_SIZE, vtbl->size);
228 entry[VTBL_K_CMPR] = VTBL_CMPR_UNREG;
229 if (vtbl->use_compression) { /* use compression: */
230 entry[VTBL_K_CMPR] |= VTBL_CMPR_USED;
231 }
232 }
233 if (ft_format_code == fmt_big) {
234 /* SCSI like vtbl, store the number of used
235 * segments as 4 byte value
236 */
237 PUT4(entry, VTBL_SCSI_SEGS, vtbl->end_seg-vtbl->start_seg + 1);
238 } else {
239 /* normal, QIC-80MC like vtbl
240 */
241 PUT2(entry, VTBL_START, vtbl->start_seg);
242 PUT2(entry, VTBL_END, vtbl->end_seg);
243 }
244 TRACE_EXIT;
245}
246
247/* this one creates the volume headers for each volume. It is assumed
248 * that buffer already contains the old volume-table, so that vtbl
249 * entries without the zft_volume flag set can savely be ignored.
250 */
251static void zft_create_volume_headers(__u8 *buffer)
252{
253 __u8 *entry;
254 struct list_head *tmp;
255 zft_volinfo *vtbl;
256 TRACE_FUN(ft_t_flow);
257
258#ifdef ZFT_CMAP_HACK
259 if((strncmp(&buffer[VTBL_EXT+EXT_ZFTAPE_SIG], ZFTAPE_SIG,
260 strlen(ZFTAPE_SIG)) == 0) &&
261 buffer[VTBL_EXT+EXT_ZFTAPE_CMAP] != 0) {
262 TRACE(ft_t_noise, "deleting cmap volume");
263 memmove(buffer, buffer + VTBL_SIZE,
264 FT_SEGMENT_SIZE - VTBL_SIZE);
265 }
266#endif
267 entry = buffer;
268 for (tmp = zft_head_vtbl->node.next;
269 tmp != &zft_eom_vtbl->node;
270 tmp = tmp->next) {
271 vtbl = list_entry(tmp, zft_volinfo, node);
272 /* we now fill in the values only for newly created volumes.
273 */
274 if (vtbl->new_volume) {
275 create_zft_volume(entry, vtbl);
276 vtbl->new_volume = 0; /* clear the flag */
277 }
278
279 DUMP_VOLINFO(ft_t_noise, &entry[VTBL_DESC], vtbl);
280 entry += VTBL_SIZE;
281 }
282 memset(entry, 0, FT_SEGMENT_SIZE - zft_eom_vtbl->count * VTBL_SIZE);
283 TRACE_EXIT;
284}
285
286/* write volume table to tape. Calls zft_create_volume_headers()
287 */
288int zft_update_volume_table(unsigned int segment)
289{
290 int result = 0;
291 __u8 *verify_buf = NULL;
292 TRACE_FUN(ft_t_flow);
293
294 TRACE_CATCH(result = ftape_read_segment(ft_first_data_segment,
295 zft_deblock_buf,
296 FT_RD_SINGLE),);
297 zft_create_volume_headers(zft_deblock_buf);
298 TRACE(ft_t_noise, "writing volume table segment %d", segment);
299 if (zft_vmalloc_once(&verify_buf, FT_SEGMENT_SIZE) == 0) {
300 TRACE_CATCH(zft_verify_write_segments(segment,
301 zft_deblock_buf, result,
302 verify_buf),
303 zft_vfree(&verify_buf, FT_SEGMENT_SIZE));
304 zft_vfree(&verify_buf, FT_SEGMENT_SIZE);
305 } else {
306 TRACE_CATCH(ftape_write_segment(segment, zft_deblock_buf,
307 FT_WR_SINGLE),);
308 }
309 TRACE_EXIT 0;
310}
311
312/* non zftape volumes are handled in raw mode. Thus we need to
313 * calculate the raw amount of data contained in those segments.
314 */
315static void extract_alien_volume(__u8 *entry, zft_volinfo *vtbl)
316{
317 TRACE_FUN(ft_t_flow);
318
319 vtbl->size = (zft_calc_tape_pos(zft_last_vtbl->end_seg+1) -
320 zft_calc_tape_pos(zft_last_vtbl->start_seg));
321 vtbl->use_compression = 0;
322 vtbl->qic113 = zft_qic113;
323 if (vtbl->qic113) {
324 TRACE(ft_t_noise,
325 "Fake alien volume's size from " LL_X " to " LL_X,
326 LL(GET8(entry, VTBL_DATA_SIZE)), LL(vtbl->size));
327 } else {
328 TRACE(ft_t_noise,
329 "Fake alien volume's size from %d to " LL_X,
330 (int)GET4(entry, VTBL_DATA_SIZE), LL(vtbl->size));
331 }
332 TRACE_EXIT;
333}
334
335
336/* extract an zftape specific volume
337 */
338static void extract_zft_volume(__u8 *entry, zft_volinfo *vtbl)
339{
340 TRACE_FUN(ft_t_flow);
341
342 if (vtbl->qic113) {
343 vtbl->size = GET8(entry, VTBL_DATA_SIZE);
344 vtbl->use_compression =
345 (entry[VTBL_CMPR] & VTBL_CMPR_USED) != 0;
346 } else {
347 vtbl->size = GET4(entry, VTBL_DATA_SIZE);
348 if (entry[VTBL_K_CMPR] & VTBL_CMPR_UNREG) {
349 vtbl->use_compression =
350 (entry[VTBL_K_CMPR] & VTBL_CMPR_USED) != 0;
351 } else if (entry[VTBL_CMPR] & VTBL_CMPR_UNREG) {
352 vtbl->use_compression =
353 (entry[VTBL_CMPR] & VTBL_CMPR_USED) != 0;
354 } else {
355 TRACE(ft_t_warn, "Geeh! There is something wrong:\n"
356 KERN_INFO "QIC compression (Rev = K): %x\n"
357 KERN_INFO "QIC compression (Rev > K): %x",
358 entry[VTBL_K_CMPR], entry[VTBL_CMPR]);
359 }
360 }
361 TRACE_EXIT;
362}
363
364/* extract the volume table from buffer. "buffer" must already contain
365 * the vtbl-segment
366 */
367int zft_extract_volume_headers(__u8 *buffer)
368{
369 __u8 *entry;
370 TRACE_FUN(ft_t_flow);
371
372 zft_init_vtbl();
373 entry = buffer;
374#ifdef ZFT_CMAP_HACK
375 if ((strncmp(&entry[VTBL_EXT+EXT_ZFTAPE_SIG], ZFTAPE_SIG,
376 strlen(ZFTAPE_SIG)) == 0) &&
377 entry[VTBL_EXT+EXT_ZFTAPE_CMAP] != 0) {
378 TRACE(ft_t_noise, "ignoring cmap volume");
379 entry += VTBL_SIZE;
380 }
381#endif
382 /* the end of the vtbl is indicated by an invalid signature
383 */
384 while (vtbl_signature_valid(&entry[VTBL_SIG]) &&
385 (entry - buffer) < FT_SEGMENT_SIZE) {
386 zft_new_vtbl_entry();
387 if (ft_format_code == fmt_big) {
388 /* SCSI like vtbl, stores only the number of
389 * segments used
390 */
391 unsigned int num_segments= GET4(entry, VTBL_SCSI_SEGS);
392 zft_last_vtbl->start_seg = zft_eom_vtbl->start_seg;
393 zft_last_vtbl->end_seg =
394 zft_last_vtbl->start_seg + num_segments - 1;
395 } else {
396 /* `normal', QIC-80 like vtbl
397 */
398 zft_last_vtbl->start_seg = GET2(entry, VTBL_START);
399 zft_last_vtbl->end_seg = GET2(entry, VTBL_END);
400 }
401 zft_eom_vtbl->start_seg = zft_last_vtbl->end_seg + 1;
402 /* check if we created this volume and get the
403 * blk_sz
404 */
405 zft_last_vtbl->zft_volume = check_volume(entry, zft_last_vtbl);
406 if (zft_last_vtbl->zft_volume == 0) {
407 extract_alien_volume(entry, zft_last_vtbl);
408 } else {
409 extract_zft_volume(entry, zft_last_vtbl);
410 }
411 DUMP_VOLINFO(ft_t_noise, &entry[VTBL_DESC], zft_last_vtbl);
412 entry +=VTBL_SIZE;
413 }
414#if 0
415/*
416 * undefine to test end of tape handling
417 */
418 zft_new_vtbl_entry();
419 zft_last_vtbl->start_seg = zft_eom_vtbl->start_seg;
420 zft_last_vtbl->end_seg = ft_last_data_segment - 10;
421 zft_last_vtbl->blk_sz = zft_blk_sz;
422 zft_last_vtbl->zft_volume = 1;
423 zft_last_vtbl->qic113 = zft_qic113;
424 zft_last_vtbl->size = (zft_calc_tape_pos(zft_last_vtbl->end_seg+1)
425 - zft_calc_tape_pos(zft_last_vtbl->start_seg));
426#endif
427 TRACE_EXIT 0;
428}
429
430/* this functions translates the failed_sector_log, misused as
431 * EOF-marker list, into a virtual volume table. The table mustn't be
432 * written to tape, because this would occupy the first data segment,
433 * which should be the volume table, but is actually the first segment
434 * that is filled with data (when using standard ftape). We assume,
435 * that we get a non-empty failed_sector_log.
436 */
437int zft_fake_volume_headers (eof_mark_union *eof_map, int num_failed_sectors)
438{
439 unsigned int segment, sector;
440 int have_eom = 0;
441 int vol_no;
442 TRACE_FUN(ft_t_flow);
443
444 if ((num_failed_sectors >= 2) &&
445 (GET2(&eof_map[num_failed_sectors - 1].mark.segment, 0)
446 ==
447 GET2(&eof_map[num_failed_sectors - 2].mark.segment, 0) + 1) &&
448 (GET2(&eof_map[num_failed_sectors - 1].mark.date, 0) == 1)) {
449 /* this should be eom. We keep the remainder of the
450 * tape as another volume.
451 */
452 have_eom = 1;
453 }
454 zft_init_vtbl();
455 zft_eom_vtbl->start_seg = ft_first_data_segment;
456 for(vol_no = 0; vol_no < num_failed_sectors - have_eom; vol_no ++) {
457 zft_new_vtbl_entry();
458
459 segment = GET2(&eof_map[vol_no].mark.segment, 0);
460 sector = GET2(&eof_map[vol_no].mark.date, 0);
461
462 zft_last_vtbl->start_seg = zft_eom_vtbl->start_seg;
463 zft_last_vtbl->end_seg = segment;
464 zft_eom_vtbl->start_seg = segment + 1;
465 zft_last_vtbl->blk_sz = 1;
466 zft_last_vtbl->size =
467 (zft_calc_tape_pos(zft_last_vtbl->end_seg)
468 - zft_calc_tape_pos(zft_last_vtbl->start_seg)
469 + (sector-1) * FT_SECTOR_SIZE);
470 TRACE(ft_t_noise,
471 "failed sector log: segment: %d, sector: %d",
472 segment, sector);
473 DUMP_VOLINFO(ft_t_noise, "Faked volume", zft_last_vtbl);
474 }
475 if (!have_eom) {
476 zft_new_vtbl_entry();
477 zft_last_vtbl->start_seg = zft_eom_vtbl->start_seg;
478 zft_last_vtbl->end_seg = ft_last_data_segment;
479 zft_eom_vtbl->start_seg = ft_last_data_segment + 1;
480 zft_last_vtbl->size = zft_capacity;
481 zft_last_vtbl->size -= zft_calc_tape_pos(zft_last_vtbl->start_seg);
482 zft_last_vtbl->blk_sz = 1;
483 DUMP_VOLINFO(ft_t_noise, "Faked volume",zft_last_vtbl);
484 }
485 TRACE_EXIT 0;
486}
487
488/* update the internal volume table
489 *
490 * if before start of last volume: erase all following volumes if
491 * inside a volume: set end of volume to infinity
492 *
493 * this function is intended to be called every time _ftape_write() is
494 * called
495 *
496 * return: 0 if no new volume was created, 1 if a new volume was
497 * created
498 *
499 * NOTE: we don't need to check for zft_mode as ftape_write() does
500 * that already. This function gets never called without accessing
501 * zftape via the *qft* devices
502 */
503
504int zft_open_volume(zft_position *pos, int blk_sz, int use_compression)
505{
506 TRACE_FUN(ft_t_flow);
507
508 if (!zft_qic_mode) {
509 TRACE_EXIT 0;
510 }
511 if (zft_tape_at_lbot(pos)) {
512 zft_init_vtbl();
513 if(zft_old_ftape) {
514 /* clear old ftape's eof marks */
515 zft_clear_ftape_file_marks();
516 zft_old_ftape = 0; /* no longer old ftape */
517 }
518 zft_reset_position(pos);
519 }
520 if (pos->seg_pos != zft_last_vtbl->end_seg + 1) {
521 TRACE_ABORT(-EIO, ft_t_bug,
522 "BUG: seg_pos: %d, zft_last_vtbl->end_seg: %d",
523 pos->seg_pos, zft_last_vtbl->end_seg);
524 }
525 TRACE(ft_t_noise, "create new volume");
526 if (zft_eom_vtbl->count >= ZFT_MAX_VOLUMES) {
527 TRACE_ABORT(-ENOSPC, ft_t_err,
528 "Error: maxmimal number of volumes exhausted "
529 "(maxmimum is %d)", ZFT_MAX_VOLUMES);
530 }
531 zft_new_vtbl_entry();
532 pos->volume_pos = pos->seg_byte_pos = 0;
533 zft_last_vtbl->start_seg = pos->seg_pos;
534 zft_last_vtbl->end_seg = ft_last_data_segment; /* infinity */
535 zft_last_vtbl->blk_sz = blk_sz;
536 zft_last_vtbl->size = zft_capacity;
537 zft_last_vtbl->zft_volume = 1;
538 zft_last_vtbl->use_compression = use_compression;
539 zft_last_vtbl->qic113 = zft_qic113;
540 zft_last_vtbl->new_volume = 1;
541 zft_last_vtbl->open = 1;
542 zft_volume_table_changed = 1;
543 zft_eom_vtbl->start_seg = ft_last_data_segment + 1;
544 TRACE_EXIT 0;
545}
546
547/* perform mtfsf, mtbsf, not allowed without zft_qic_mode
548 */
549int zft_skip_volumes(int count, zft_position *pos)
550{
551 const zft_volinfo *vtbl;
552 TRACE_FUN(ft_t_flow);
553
554 TRACE(ft_t_noise, "count: %d", count);
555
556 vtbl= zft_find_volume(pos->seg_pos);
557 while (count > 0 && vtbl != zft_eom_vtbl) {
558 vtbl = list_entry(vtbl->node.next, zft_volinfo, node);
559 count --;
560 }
561 while (count < 0 && vtbl != zft_first_vtbl) {
562 vtbl = list_entry(vtbl->node.prev, zft_volinfo, node);
563 count ++;
564 }
565 pos->seg_pos = vtbl->start_seg;
566 pos->seg_byte_pos = 0;
567 pos->volume_pos = 0;
568 pos->tape_pos = zft_calc_tape_pos(pos->seg_pos);
569 zft_just_before_eof = vtbl->size == 0;
570 if (zft_cmpr_ops) {
571 (*zft_cmpr_ops->reset)();
572 }
573 zft_deblock_segment = -1; /* no need to keep cache */
574 TRACE(ft_t_noise, "repositioning to:\n"
575 KERN_INFO "zft_seg_pos : %d\n"
576 KERN_INFO "zft_seg_byte_pos : %d\n"
577 KERN_INFO "zft_tape_pos : " LL_X "\n"
578 KERN_INFO "zft_volume_pos : " LL_X "\n"
579 KERN_INFO "file number : %d",
580 pos->seg_pos, pos->seg_byte_pos,
581 LL(pos->tape_pos), LL(pos->volume_pos), vtbl->count);
582 zft_resid = count < 0 ? -count : count;
583 TRACE_EXIT zft_resid ? -EINVAL : 0;
584}
585
586/* the following simply returns the raw data position of the EOM
587 * marker, MTIOCSIZE ioctl
588 */
589__s64 zft_get_eom_pos(void)
590{
591 if (zft_qic_mode) {
592 return zft_calc_tape_pos(zft_eom_vtbl->start_seg);
593 } else {
594 /* there is only one volume in raw mode */
595 return zft_capacity;
596 }
597}
598
599/* skip to eom, used for MTEOM
600 */
601void zft_skip_to_eom(zft_position *pos)
602{
603 TRACE_FUN(ft_t_flow);
604 pos->seg_pos = zft_eom_vtbl->start_seg;
605 pos->seg_byte_pos =
606 pos->volume_pos =
607 zft_just_before_eof = 0;
608 pos->tape_pos = zft_calc_tape_pos(pos->seg_pos);
609 TRACE(ft_t_noise, "ftape positioned to segment %d, data pos " LL_X,
610 pos->seg_pos, LL(pos->tape_pos));
611 TRACE_EXIT;
612}
613
614/* write an EOF-marker by setting zft_last_vtbl->end_seg to seg_pos.
615 * NOTE: this function assumes that zft_last_vtbl points to a valid
616 * vtbl entry
617 *
618 * NOTE: this routine always positions before the EOF marker
619 */
620int zft_close_volume(zft_position *pos)
621{
622 TRACE_FUN(ft_t_any);
623
624 if (zft_vtbl_empty || !zft_last_vtbl->open) { /* should not happen */
625 TRACE(ft_t_noise, "There are no volumes to finish");
626 TRACE_EXIT -EIO;
627 }
628 if (pos->seg_byte_pos == 0 &&
629 pos->seg_pos != zft_last_vtbl->start_seg) {
630 pos->seg_pos --;
631 pos->seg_byte_pos = zft_get_seg_sz(pos->seg_pos);
632 }
633 zft_last_vtbl->end_seg = pos->seg_pos;
634 zft_last_vtbl->size = pos->volume_pos;
635 zft_volume_table_changed = 1;
636 zft_just_before_eof = 1;
637 zft_eom_vtbl->start_seg = zft_last_vtbl->end_seg + 1;
638 zft_last_vtbl->open = 0; /* closed */
639 TRACE_EXIT 0;
640}
641
642/* write count file-marks at current position.
643 *
644 * The tape is positioned after the eof-marker, that is at byte 0 of
645 * the segment following the eof-marker
646 *
647 * this function is only allowed in zft_qic_mode
648 *
649 * Only allowed when tape is at BOT or EOD.
650 */
651int zft_weof(unsigned int count, zft_position *pos)
652{
653
654 TRACE_FUN(ft_t_flow);
655
656 if (!count) { /* write zero EOF marks should be a real no-op */
657 TRACE_EXIT 0;
658 }
659 zft_volume_table_changed = 1;
660 if (zft_tape_at_lbot(pos)) {
661 zft_init_vtbl();
662 if(zft_old_ftape) {
663 /* clear old ftape's eof marks */
664 zft_clear_ftape_file_marks();
665 zft_old_ftape = 0; /* no longer old ftape */
666 }
667 }
668 if (zft_last_vtbl->open) {
669 zft_close_volume(pos);
670 zft_move_past_eof(pos);
671 count --;
672 }
673 /* now it's easy, just append eof-marks, that is empty
674 * volumes, to the end of the already recorded media.
675 */
676 while (count > 0 &&
677 pos->seg_pos <= ft_last_data_segment &&
678 zft_eom_vtbl->count < ZFT_MAX_VOLUMES) {
679 TRACE(ft_t_noise,
680 "Writing zero sized file at segment %d", pos->seg_pos);
681 zft_new_vtbl_entry();
682 zft_last_vtbl->start_seg = pos->seg_pos;
683 zft_last_vtbl->end_seg = pos->seg_pos;
684 zft_last_vtbl->size = 0;
685 zft_last_vtbl->blk_sz = zft_blk_sz;
686 zft_last_vtbl->zft_volume = 1;
687 zft_last_vtbl->use_compression = 0;
688 pos->tape_pos += zft_get_seg_sz(pos->seg_pos);
689 zft_eom_vtbl->start_seg = ++ pos->seg_pos;
690 count --;
691 }
692 if (count > 0) {
693 /* there are two possibilities: end of tape, or the
694 * maximum number of files is exhausted.
695 */
696 zft_resid = count;
697 TRACE(ft_t_noise,"Number of marks NOT written: %d", zft_resid);
698 if (zft_eom_vtbl->count == ZFT_MAX_VOLUMES) {
699 TRACE_ABORT(-EINVAL, ft_t_warn,
700 "maximum allowed number of files "
701 "exhausted: %d", ZFT_MAX_VOLUMES);
702 } else {
703 TRACE_ABORT(-ENOSPC,
704 ft_t_noise, "reached end of tape");
705 }
706 }
707 TRACE_EXIT 0;
708}
709
710const zft_volinfo *zft_find_volume(unsigned int seg_pos)
711{
712 TRACE_FUN(ft_t_flow);
713
714 TRACE(ft_t_any, "called with seg_pos %d",seg_pos);
715 if (!zft_qic_mode) {
716 if (seg_pos > ft_last_data_segment) {
717 TRACE_EXIT &eot_vtbl;
718 }
719 tape_vtbl.blk_sz = zft_blk_sz;
720 TRACE_EXIT &tape_vtbl;
721 }
722 if (seg_pos < zft_first_vtbl->start_seg) {
723 TRACE_EXIT (cur_vtbl = zft_first_vtbl);
724 }
725 while (seg_pos > cur_vtbl->end_seg) {
726 cur_vtbl = list_entry(cur_vtbl->node.next, zft_volinfo, node);
727 TRACE(ft_t_noise, "%d - %d", cur_vtbl->start_seg, cur_vtbl->end_seg);
728 }
729 while (seg_pos < cur_vtbl->start_seg) {
730 cur_vtbl = list_entry(cur_vtbl->node.prev, zft_volinfo, node);
731 TRACE(ft_t_noise, "%d - %d", cur_vtbl->start_seg, cur_vtbl->end_seg);
732 }
733 if (seg_pos > cur_vtbl->end_seg || seg_pos < cur_vtbl->start_seg) {
734 TRACE(ft_t_bug, "This cannot happen");
735 }
736 DUMP_VOLINFO(ft_t_noise, "", cur_vtbl);
737 TRACE_EXIT cur_vtbl;
738}
739
740/* this function really assumes that we are just before eof
741 */
742void zft_move_past_eof(zft_position *pos)
743{
744 TRACE_FUN(ft_t_flow);
745
746 TRACE(ft_t_noise, "old seg. pos: %d", pos->seg_pos);
747 pos->tape_pos += zft_get_seg_sz(pos->seg_pos++) - pos->seg_byte_pos;
748 pos->seg_byte_pos = 0;
749 pos->volume_pos = 0;
750 if (zft_cmpr_ops) {
751 (*zft_cmpr_ops->reset)();
752 }
753 zft_just_before_eof = 0;
754 zft_deblock_segment = -1; /* no need to cache it anymore */
755 TRACE(ft_t_noise, "new seg. pos: %d", pos->seg_pos);
756 TRACE_EXIT;
757}
diff --git a/drivers/char/ftape/zftape/zftape-vtbl.h b/drivers/char/ftape/zftape/zftape-vtbl.h
deleted file mode 100644
index f31d196d1759..000000000000
--- a/drivers/char/ftape/zftape/zftape-vtbl.h
+++ /dev/null
@@ -1,227 +0,0 @@
1#ifndef _ZFTAPE_VTBL_H
2#define _ZFTAPE_VTBL_H
3
4/*
5 * Copyright (c) 1995-1997 Claus-Justus Heine
6
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2, or (at
10 your option) any later version.
11
12 This program is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
20 USA.
21
22 *
23 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-vtbl.h,v $
24 * $Revision: 1.3 $
25 * $Date: 1997/10/28 14:30:09 $
26 *
27 * This file defines a volume table as defined in the QIC-80
28 * development standards.
29 */
30
31#include <linux/list.h>
32
33#include "../lowlevel/ftape-tracing.h"
34
35#include "../zftape/zftape-eof.h"
36#include "../zftape/zftape-ctl.h"
37#include "../zftape/zftape-rw.h"
38
39#define VTBL_SIZE 128 /* bytes */
40
41/* The following are offsets in the vtbl. */
42#define VTBL_SIG 0
43#define VTBL_START 4
44#define VTBL_END 6
45#define VTBL_DESC 8
46#define VTBL_DATE 52
47#define VTBL_FLAGS 56
48#define VTBL_FL_VENDOR_SPECIFIC (1<<0)
49#define VTBL_FL_MUTLI_CARTRIDGE (1<<1)
50#define VTBL_FL_NOT_VERIFIED (1<<2)
51#define VTBL_FL_REDIR_INHIBIT (1<<3)
52#define VTBL_FL_SEG_SPANNING (1<<4)
53#define VTBL_FL_DIRECTORY_LAST (1<<5)
54#define VTBL_FL_RESERVED_6 (1<<6)
55#define VTBL_FL_RESERVED_7 (1<<7)
56#define VTBL_M_NO 57
57#define VTBL_EXT 58
58#define EXT_ZFTAPE_SIG 0
59#define EXT_ZFTAPE_BLKSZ 10
60#define EXT_ZFTAPE_CMAP 12
61#define EXT_ZFTAPE_QIC113 13
62#define VTBL_PWD 84
63#define VTBL_DIR_SIZE 92
64#define VTBL_DATA_SIZE 96
65#define VTBL_OS_VERSION 104
66#define VTBL_SRC_DRIVE 106
67#define VTBL_DEV 122
68#define VTBL_RESERVED_1 123
69#define VTBL_CMPR 124
70#define VTBL_CMPR_UNREG 0x3f
71#define VTBL_CMPR_USED 0x80
72#define VTBL_FMT 125
73#define VTBL_RESERVED_2 126
74#define VTBL_RESERVED_3 127
75/* compatibility with pre revision K */
76#define VTBL_K_CMPR 120
77
78/* the next is used by QIC-3020 tapes with format code 6 (>2^16
79 * segments) It is specified in QIC-113, Rev. G, Section 5 (SCSI
80 * volume table). The difference is simply, that we only store the
81 * number of segments used, not the starting segment.
82 */
83#define VTBL_SCSI_SEGS 4 /* is a 4 byte value */
84
85/* one vtbl is 128 bytes, that results in a maximum number of
86 * 29*1024/128 = 232 volumes.
87 */
88#define ZFT_MAX_VOLUMES (FT_SEGMENT_SIZE/VTBL_SIZE)
89#define VTBL_ID "VTBL"
90#define VTBL_IDS { VTBL_ID, "XTBL", "UTID", "EXVT" } /* other valid ids */
91#define ZFT_VOL_NAME "zftape volume" /* volume label used by me */
92#define ZFTAPE_SIG "LINUX ZFT"
93
94/* global variables
95 */
96typedef struct zft_internal_vtbl
97{
98 struct list_head node;
99 int count;
100 unsigned int start_seg; /* 32 bits are enough for now */
101 unsigned int end_seg; /* 32 bits are enough for now */
102 __s64 size; /* uncompressed size */
103 unsigned int blk_sz; /* block size for this volume */
104 unsigned int zft_volume :1; /* zftape created this volume */
105 unsigned int use_compression:1; /* compressed volume */
106 unsigned int qic113 :1; /* layout of compressed block
107 * info and vtbl conforms to
108 * QIC-113, Rev. G
109 */
110 unsigned int new_volume :1; /* it was created by us, this
111 * run. this allows the
112 * fields that aren't really
113 * used by zftape to be filled
114 * in by some user level
115 * program.
116 */
117 unsigned int open :1; /* just in progress of being
118 * written
119 */
120} zft_volinfo;
121
122extern struct list_head zft_vtbl;
123#define zft_head_vtbl list_entry(zft_vtbl.next, zft_volinfo, node)
124#define zft_eom_vtbl list_entry(zft_vtbl.prev, zft_volinfo, node)
125#define zft_last_vtbl list_entry(zft_eom_vtbl->node.prev, zft_volinfo, node)
126#define zft_first_vtbl list_entry(zft_head_vtbl->node.next, zft_volinfo, node)
127#define zft_vtbl_empty (zft_eom_vtbl->node.prev == &zft_head_vtbl->node)
128
129#define DUMP_VOLINFO(level, desc, info) \
130{ \
131 char tmp[21]; \
132 strlcpy(tmp, desc, sizeof(tmp)); \
133 TRACE(level, "Volume %d:\n" \
134 KERN_INFO "description : %s\n" \
135 KERN_INFO "first segment: %d\n" \
136 KERN_INFO "last segment: %d\n" \
137 KERN_INFO "size : " LL_X "\n" \
138 KERN_INFO "block size : %d\n" \
139 KERN_INFO "compression : %d\n" \
140 KERN_INFO "zftape volume: %d\n" \
141 KERN_INFO "QIC-113 conf.: %d", \
142 (info)->count, tmp, (info)->start_seg, (info)->end_seg, \
143 LL((info)->size), (info)->blk_sz, \
144 (info)->use_compression != 0, (info)->zft_volume != 0, \
145 (info)->qic113 != 0); \
146}
147
148extern int zft_qic_mode;
149extern int zft_old_ftape;
150extern int zft_volume_table_changed;
151
152/* exported functions */
153extern void zft_init_vtbl (void);
154extern void zft_free_vtbl (void);
155extern int zft_extract_volume_headers(__u8 *buffer);
156extern int zft_update_volume_table (unsigned int segment);
157extern int zft_open_volume (zft_position *pos,
158 int blk_sz, int use_compression);
159extern int zft_close_volume (zft_position *pos);
160extern const zft_volinfo *zft_find_volume(unsigned int seg_pos);
161extern int zft_skip_volumes (int count, zft_position *pos);
162extern __s64 zft_get_eom_pos (void);
163extern void zft_skip_to_eom (zft_position *pos);
164extern int zft_fake_volume_headers (eof_mark_union *eof_map,
165 int num_failed_sectors);
166extern int zft_weof (unsigned int count, zft_position *pos);
167extern void zft_move_past_eof (zft_position *pos);
168
169static inline int zft_tape_at_eod (const zft_position *pos);
170static inline int zft_tape_at_lbot (const zft_position *pos);
171static inline void zft_position_before_eof (zft_position *pos,
172 const zft_volinfo *volume);
173static inline __s64 zft_check_for_eof(const zft_volinfo *vtbl,
174 const zft_position *pos);
175
176/* this function decrements the zft_seg_pos counter if we are right
177 * at the beginning of a segment. This is to handle fsfm/bsfm -- we
178 * need to position before the eof mark. NOTE: zft_tape_pos is not
179 * changed
180 */
181static inline void zft_position_before_eof(zft_position *pos,
182 const zft_volinfo *volume)
183{
184 TRACE_FUN(ft_t_flow);
185
186 if (pos->seg_pos == volume->end_seg + 1 && pos->seg_byte_pos == 0) {
187 pos->seg_pos --;
188 pos->seg_byte_pos = zft_get_seg_sz(pos->seg_pos);
189 }
190 TRACE_EXIT;
191}
192
193/* Mmmh. Is the position at the end of the last volume, that is right
194 * before the last EOF mark also logical an EOD condition?
195 */
196static inline int zft_tape_at_eod(const zft_position *pos)
197{
198 TRACE_FUN(ft_t_any);
199
200 if (zft_qic_mode) {
201 TRACE_EXIT (pos->seg_pos >= zft_eom_vtbl->start_seg ||
202 zft_last_vtbl->open);
203 } else {
204 TRACE_EXIT pos->seg_pos > ft_last_data_segment;
205 }
206}
207
208static inline int zft_tape_at_lbot(const zft_position *pos)
209{
210 if (zft_qic_mode) {
211 return (pos->seg_pos <= zft_first_vtbl->start_seg &&
212 pos->volume_pos == 0);
213 } else {
214 return (pos->seg_pos <= ft_first_data_segment &&
215 pos->volume_pos == 0);
216 }
217}
218
219/* This one checks for EOF. return remaing space (may be negative)
220 */
221static inline __s64 zft_check_for_eof(const zft_volinfo *vtbl,
222 const zft_position *pos)
223{
224 return (__s64)(vtbl->size - pos->volume_pos);
225}
226
227#endif /* _ZFTAPE_VTBL_H */
diff --git a/drivers/char/ftape/zftape/zftape-write.c b/drivers/char/ftape/zftape/zftape-write.c
deleted file mode 100644
index 94327b8c97b9..000000000000
--- a/drivers/char/ftape/zftape/zftape-write.c
+++ /dev/null
@@ -1,483 +0,0 @@
1/*
2 * Copyright (C) 1996, 1997 Claus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-write.c,v $
20 * $Revision: 1.3 $
21 * $Date: 1997/11/06 00:50:29 $
22 *
23 * This file contains the writing code
24 * for the QIC-117 floppy-tape driver for Linux.
25 */
26
27#include <linux/errno.h>
28#include <linux/mm.h>
29
30#include <linux/zftape.h>
31
32#include <asm/uaccess.h>
33
34#include "../zftape/zftape-init.h"
35#include "../zftape/zftape-eof.h"
36#include "../zftape/zftape-ctl.h"
37#include "../zftape/zftape-write.h"
38#include "../zftape/zftape-read.h"
39#include "../zftape/zftape-rw.h"
40#include "../zftape/zftape-vtbl.h"
41
42/* Global vars.
43 */
44
45/* Local vars.
46 */
47static int last_write_failed;
48static int need_flush;
49
50void zft_prevent_flush(void)
51{
52 need_flush = 0;
53}
54
55static int zft_write_header_segments(__u8* buffer)
56{
57 int header_1_ok = 0;
58 int header_2_ok = 0;
59 unsigned int time_stamp;
60 TRACE_FUN(ft_t_noise);
61
62 TRACE_CATCH(ftape_abort_operation(),);
63 ftape_seek_to_bot(); /* prevents extra rewind */
64 if (GET4(buffer, 0) != FT_HSEG_MAGIC) {
65 TRACE_ABORT(-EIO, ft_t_err,
66 "wrong header signature found, aborting");
67 }
68 /* Be optimistic: */
69 PUT4(buffer, FT_SEG_CNT,
70 zft_written_segments + GET4(buffer, FT_SEG_CNT) + 2);
71 if ((time_stamp = zft_get_time()) != 0) {
72 PUT4(buffer, FT_WR_DATE, time_stamp);
73 if (zft_label_changed) {
74 PUT4(buffer, FT_LABEL_DATE, time_stamp);
75 }
76 }
77 TRACE(ft_t_noise,
78 "writing first header segment %d", ft_header_segment_1);
79 header_1_ok = zft_verify_write_segments(ft_header_segment_1,
80 buffer, FT_SEGMENT_SIZE,
81 zft_deblock_buf) >= 0;
82 TRACE(ft_t_noise,
83 "writing second header segment %d", ft_header_segment_2);
84 header_2_ok = zft_verify_write_segments(ft_header_segment_2,
85 buffer, FT_SEGMENT_SIZE,
86 zft_deblock_buf) >= 0;
87 if (!header_1_ok) {
88 TRACE(ft_t_warn, "Warning: "
89 "update of first header segment failed");
90 }
91 if (!header_2_ok) {
92 TRACE(ft_t_warn, "Warning: "
93 "update of second header segment failed");
94 }
95 if (!header_1_ok && !header_2_ok) {
96 TRACE_ABORT(-EIO, ft_t_err, "Error: "
97 "update of both header segments failed.");
98 }
99 TRACE_EXIT 0;
100}
101
102int zft_update_header_segments(void)
103{
104 TRACE_FUN(ft_t_noise);
105
106 /* must NOT use zft_write_protected, as it also includes the
107 * file access mode. But we also want to update when soft
108 * write protection is enabled (O_RDONLY)
109 */
110 if (ft_write_protected || zft_old_ftape) {
111 TRACE_ABORT(0, ft_t_noise, "Tape set read-only: no update");
112 }
113 if (!zft_header_read) {
114 TRACE_ABORT(0, ft_t_noise, "Nothing to update");
115 }
116 if (!zft_header_changed) {
117 zft_header_changed = zft_written_segments > 0;
118 }
119 if (!zft_header_changed && !zft_volume_table_changed) {
120 TRACE_ABORT(0, ft_t_noise, "Nothing to update");
121 }
122 TRACE(ft_t_noise, "Updating header segments");
123 if (ftape_get_status()->fti_state == writing) {
124 TRACE_CATCH(ftape_loop_until_writes_done(),);
125 }
126 TRACE_CATCH(ftape_abort_operation(),);
127
128 zft_deblock_segment = -1; /* invalidate the cache */
129 if (zft_header_changed) {
130 TRACE_CATCH(zft_write_header_segments(zft_hseg_buf),);
131 }
132 if (zft_volume_table_changed) {
133 TRACE_CATCH(zft_update_volume_table(ft_first_data_segment),);
134 }
135 zft_header_changed =
136 zft_volume_table_changed =
137 zft_label_changed =
138 zft_written_segments = 0;
139 TRACE_CATCH(ftape_abort_operation(),);
140 ftape_seek_to_bot();
141 TRACE_EXIT 0;
142}
143
144static int read_merge_buffer(int seg_pos, __u8 *buffer, int offset, int seg_sz)
145{
146 int result = 0;
147 const ft_trace_t old_tracing = TRACE_LEVEL;
148 TRACE_FUN(ft_t_flow);
149
150 if (zft_qic_mode) {
151 /* writing in the middle of a volume is NOT allowed
152 *
153 */
154 TRACE(ft_t_noise, "No need to read a segment");
155 memset(buffer + offset, 0, seg_sz - offset);
156 TRACE_EXIT 0;
157 }
158 TRACE(ft_t_any, "waiting");
159 ftape_start_writing(FT_WR_MULTI);
160 TRACE_CATCH(ftape_loop_until_writes_done(),);
161
162 TRACE(ft_t_noise, "trying to read segment %d from offset %d",
163 seg_pos, offset);
164 SET_TRACE_LEVEL(ft_t_bug);
165 result = zft_fetch_segment_fraction(seg_pos, buffer,
166 FT_RD_SINGLE,
167 offset, seg_sz - offset);
168 SET_TRACE_LEVEL(old_tracing);
169 if (result != (seg_sz - offset)) {
170 TRACE(ft_t_noise, "Ignore error: read_segment() result: %d",
171 result);
172 memset(buffer + offset, 0, seg_sz - offset);
173 }
174 TRACE_EXIT 0;
175}
176
177/* flush the write buffer to tape and write an eof-marker at the
178 * current position if not in raw mode. This function always
179 * positions the tape before the eof-marker. _ftape_close() should
180 * then advance to the next segment.
181 *
182 * the parameter "finish_volume" describes whether to position before
183 * or after the possibly created file-mark. We always position after
184 * the file-mark when called from ftape_close() and a flush was needed
185 * (that is ftape_write() was the last tape operation before calling
186 * ftape_flush) But we always position before the file-mark when this
187 * function get's called from outside ftape_close()
188 */
189int zft_flush_buffers(void)
190{
191 int result;
192 int data_remaining;
193 int this_segs_size;
194 TRACE_FUN(ft_t_flow);
195
196 TRACE(ft_t_data_flow,
197 "entered, ftape_state = %d", ftape_get_status()->fti_state);
198 if (ftape_get_status()->fti_state != writing && !need_flush) {
199 TRACE_ABORT(0, ft_t_noise, "no need for flush");
200 }
201 zft_io_state = zft_idle; /* triggers some initializations for the
202 * read and write routines
203 */
204 if (last_write_failed) {
205 ftape_abort_operation();
206 TRACE_EXIT -EIO;
207 }
208 TRACE(ft_t_noise, "flushing write buffers");
209 this_segs_size = zft_get_seg_sz(zft_pos.seg_pos);
210 if (this_segs_size == zft_pos.seg_byte_pos) {
211 zft_pos.seg_pos ++;
212 data_remaining = zft_pos.seg_byte_pos = 0;
213 } else {
214 data_remaining = zft_pos.seg_byte_pos;
215 }
216 /* If there is any data not written to tape yet, append zero's
217 * up to the end of the sector (if using compression) or merge
218 * it with the data existing on the tape Then write the
219 * segment(s) to tape.
220 */
221 TRACE(ft_t_noise, "Position:\n"
222 KERN_INFO "seg_pos : %d\n"
223 KERN_INFO "byte pos : %d\n"
224 KERN_INFO "remaining: %d",
225 zft_pos.seg_pos, zft_pos.seg_byte_pos, data_remaining);
226 if (data_remaining > 0) {
227 do {
228 this_segs_size = zft_get_seg_sz(zft_pos.seg_pos);
229 if (this_segs_size > data_remaining) {
230 TRACE_CATCH(read_merge_buffer(zft_pos.seg_pos,
231 zft_deblock_buf,
232 data_remaining,
233 this_segs_size),
234 last_write_failed = 1);
235 }
236 result = ftape_write_segment(zft_pos.seg_pos,
237 zft_deblock_buf,
238 FT_WR_MULTI);
239 if (result != this_segs_size) {
240 TRACE(ft_t_err, "flush buffers failed");
241 zft_pos.tape_pos -= zft_pos.seg_byte_pos;
242 zft_pos.seg_byte_pos = 0;
243
244 last_write_failed = 1;
245 TRACE_EXIT result;
246 }
247 zft_written_segments ++;
248 TRACE(ft_t_data_flow,
249 "flush, moved out buffer: %d", result);
250 /* need next segment for more data (empty segments?)
251 */
252 if (result < data_remaining) {
253 if (result > 0) {
254 /* move remainder to buffer beginning
255 */
256 memmove(zft_deblock_buf,
257 zft_deblock_buf + result,
258 FT_SEGMENT_SIZE - result);
259 }
260 }
261 data_remaining -= result;
262 zft_pos.seg_pos ++;
263 } while (data_remaining > 0);
264 TRACE(ft_t_any, "result: %d", result);
265 zft_deblock_segment = --zft_pos.seg_pos;
266 if (data_remaining == 0) { /* first byte next segment */
267 zft_pos.seg_byte_pos = this_segs_size;
268 } else { /* after data previous segment, data_remaining < 0 */
269 zft_pos.seg_byte_pos = data_remaining + result;
270 }
271 } else {
272 TRACE(ft_t_noise, "zft_deblock_buf empty");
273 zft_pos.seg_pos --;
274 zft_pos.seg_byte_pos = zft_get_seg_sz (zft_pos.seg_pos);
275 ftape_start_writing(FT_WR_MULTI);
276 }
277 TRACE(ft_t_any, "waiting");
278 if ((result = ftape_loop_until_writes_done()) < 0) {
279 /* that's really bad. What to to with zft_tape_pos?
280 */
281 TRACE(ft_t_err, "flush buffers failed");
282 }
283 TRACE(ft_t_any, "zft_seg_pos: %d, zft_seg_byte_pos: %d",
284 zft_pos.seg_pos, zft_pos.seg_byte_pos);
285 last_write_failed =
286 need_flush = 0;
287 TRACE_EXIT result;
288}
289
290/* return-value: the number of bytes removed from the user-buffer
291 *
292 * out:
293 * int *write_cnt: how much actually has been moved to the
294 * zft_deblock_buf
295 * int req_len : MUST NOT BE CHANGED, except at EOT, in
296 * which case it may be adjusted
297 * in :
298 * char *buff : the user buffer
299 * int buf_pos_write : copy of buf_len_wr int
300 * this_segs_size : the size in bytes of the actual segment
301 * char
302 * *zft_deblock_buf : zft_deblock_buf
303 */
304static int zft_simple_write(int *cnt,
305 __u8 *dst_buf, const int seg_sz,
306 const __u8 __user *src_buf, const int req_len,
307 const zft_position *pos,const zft_volinfo *volume)
308{
309 int space_left;
310 TRACE_FUN(ft_t_flow);
311
312 /* volume->size holds the tape capacity while volume is open */
313 if (pos->tape_pos + volume->blk_sz > volume->size) {
314 TRACE_EXIT -ENOSPC;
315 }
316 /* remaining space in this segment, NOT zft_deblock_buf
317 */
318 space_left = seg_sz - pos->seg_byte_pos;
319 *cnt = req_len < space_left ? req_len : space_left;
320 if (copy_from_user(dst_buf + pos->seg_byte_pos, src_buf, *cnt) != 0) {
321 TRACE_EXIT -EFAULT;
322 }
323 TRACE_EXIT *cnt;
324}
325
326static int check_write_access(int req_len,
327 const zft_volinfo **volume,
328 zft_position *pos,
329 const unsigned int blk_sz)
330{
331 int result;
332 TRACE_FUN(ft_t_flow);
333
334 if ((req_len % zft_blk_sz) != 0) {
335 TRACE_ABORT(-EINVAL, ft_t_info,
336 "write-count %d must be multiple of block-size %d",
337 req_len, blk_sz);
338 }
339 if (zft_io_state == zft_writing) {
340 /* all other error conditions have been checked earlier
341 */
342 TRACE_EXIT 0;
343 }
344 zft_io_state = zft_idle;
345 TRACE_CATCH(zft_check_write_access(pos),);
346 /* If we haven't read the header segment yet, do it now.
347 * This will verify the configuration, get the bad sector
348 * table and read the volume table segment
349 */
350 if (!zft_header_read) {
351 TRACE_CATCH(zft_read_header_segments(),);
352 }
353 /* fine. Now the tape is either at BOT or at EOD,
354 * Write start of volume now
355 */
356 TRACE_CATCH(zft_open_volume(pos, blk_sz, zft_use_compression),);
357 *volume = zft_find_volume(pos->seg_pos);
358 DUMP_VOLINFO(ft_t_noise, "", *volume);
359 zft_just_before_eof = 0;
360 /* now merge with old data if necessary */
361 if (!zft_qic_mode && pos->seg_byte_pos != 0){
362 result = zft_fetch_segment(pos->seg_pos,
363 zft_deblock_buf,
364 FT_RD_SINGLE);
365 if (result < 0) {
366 if (result == -EINTR || result == -ENOSPC) {
367 TRACE_EXIT result;
368 }
369 TRACE(ft_t_noise,
370 "ftape_read_segment() result: %d. "
371 "This might be normal when using "
372 "a newly\nformatted tape", result);
373 memset(zft_deblock_buf, '\0', pos->seg_byte_pos);
374 }
375 }
376 zft_io_state = zft_writing;
377 TRACE_EXIT 0;
378}
379
380static int fill_deblock_buf(__u8 *dst_buf, const int seg_sz,
381 zft_position *pos, const zft_volinfo *volume,
382 const char __user *usr_buf, const int req_len)
383{
384 int cnt = 0;
385 int result = 0;
386 TRACE_FUN(ft_t_flow);
387
388 if (seg_sz == 0) {
389 TRACE_ABORT(0, ft_t_data_flow, "empty segment");
390 }
391 TRACE(ft_t_data_flow, "\n"
392 KERN_INFO "remaining req_len: %d\n"
393 KERN_INFO " buf_pos: %d",
394 req_len, pos->seg_byte_pos);
395 /* zft_deblock_buf will not contain a valid segment any longer */
396 zft_deblock_segment = -1;
397 if (zft_use_compression) {
398 TRACE_CATCH(zft_cmpr_lock(1 /* try to load */),);
399 TRACE_CATCH(result= (*zft_cmpr_ops->write)(&cnt,
400 dst_buf, seg_sz,
401 usr_buf, req_len,
402 pos, volume),);
403 } else {
404 TRACE_CATCH(result= zft_simple_write(&cnt,
405 dst_buf, seg_sz,
406 usr_buf, req_len,
407 pos, volume),);
408 }
409 pos->volume_pos += result;
410 pos->seg_byte_pos += cnt;
411 pos->tape_pos += cnt;
412 TRACE(ft_t_data_flow, "\n"
413 KERN_INFO "removed from user-buffer : %d bytes.\n"
414 KERN_INFO "copied to zft_deblock_buf: %d bytes.\n"
415 KERN_INFO "zft_tape_pos : " LL_X " bytes.",
416 result, cnt, LL(pos->tape_pos));
417 TRACE_EXIT result;
418}
419
420
421/* called by the kernel-interface routine "zft_write()"
422 */
423int _zft_write(const char __user *buff, int req_len)
424{
425 int result = 0;
426 int written = 0;
427 int write_cnt;
428 int seg_sz;
429 static const zft_volinfo *volume = NULL;
430 TRACE_FUN(ft_t_flow);
431
432 zft_resid = req_len;
433 last_write_failed = 1; /* reset to 0 when successful */
434 /* check if write is allowed
435 */
436 TRACE_CATCH(check_write_access(req_len, &volume,&zft_pos,zft_blk_sz),);
437 while (req_len > 0) {
438 /* Allow us to escape from this loop with a signal !
439 */
440 FT_SIGNAL_EXIT(_DONT_BLOCK);
441 seg_sz = zft_get_seg_sz(zft_pos.seg_pos);
442 if ((write_cnt = fill_deblock_buf(zft_deblock_buf,
443 seg_sz,
444 &zft_pos,
445 volume,
446 buff,
447 req_len)) < 0) {
448 zft_resid -= written;
449 if (write_cnt == -ENOSPC) {
450 /* leave the remainder to flush_buffers()
451 */
452 TRACE(ft_t_info, "No space left on device");
453 last_write_failed = 0;
454 if (!need_flush) {
455 need_flush = written > 0;
456 }
457 TRACE_EXIT written > 0 ? written : -ENOSPC;
458 } else {
459 TRACE_EXIT result;
460 }
461 }
462 if (zft_pos.seg_byte_pos == seg_sz) {
463 TRACE_CATCH(ftape_write_segment(zft_pos.seg_pos,
464 zft_deblock_buf,
465 FT_WR_ASYNC),
466 zft_resid -= written);
467 zft_written_segments ++;
468 zft_pos.seg_byte_pos = 0;
469 zft_deblock_segment = zft_pos.seg_pos;
470 ++zft_pos.seg_pos;
471 }
472 written += write_cnt;
473 buff += write_cnt;
474 req_len -= write_cnt;
475 } /* while (req_len > 0) */
476 TRACE(ft_t_data_flow, "remaining in blocking buffer: %d",
477 zft_pos.seg_byte_pos);
478 TRACE(ft_t_data_flow, "just written bytes: %d", written);
479 last_write_failed = 0;
480 zft_resid -= written;
481 need_flush = need_flush || written > 0;
482 TRACE_EXIT written; /* bytes written */
483}
diff --git a/drivers/char/ftape/zftape/zftape-write.h b/drivers/char/ftape/zftape/zftape-write.h
deleted file mode 100644
index ea887015b493..000000000000
--- a/drivers/char/ftape/zftape/zftape-write.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _ZFTAPE_WRITE_H
2#define _ZFTAPE_WRITE_H
3
4/*
5 * Copyright (C) 1996, 1997 Claus-Justus Heine
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 *
22 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape-write.h,v $
23 * $Revision: 1.2 $
24 * $Date: 1997/10/05 19:19:13 $
25 *
26 * This file contains the definitions for the write functions
27 * for the zftape driver for Linux.
28 *
29 */
30
31extern int zft_flush_buffers(void);
32extern int zft_update_header_segments(void);
33extern void zft_prevent_flush(void);
34
35/* hook for the VFS interface
36 */
37extern int _zft_write(const char __user *buff, int req_len);
38#endif /* _ZFTAPE_WRITE_H */
diff --git a/drivers/char/ftape/zftape/zftape_syms.c b/drivers/char/ftape/zftape/zftape_syms.c
deleted file mode 100644
index 2db1401682df..000000000000
--- a/drivers/char/ftape/zftape/zftape_syms.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * Copyright (C) 1997 Claus-Justus Heine
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
7 any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 *
19 * $Source: /homes/cvs/ftape-stacked/ftape/zftape/zftape_syms.c,v $
20 * $Revision: 1.3 $
21 * $Date: 1997/10/05 19:19:14 $
22 *
23 * This file contains the symbols that the zftape frontend to
24 * the ftape floppy tape driver exports
25 */
26
27#include <linux/module.h>
28
29#include <linux/zftape.h>
30
31#include "../zftape/zftape-init.h"
32#include "../zftape/zftape-read.h"
33#include "../zftape/zftape-buffers.h"
34#include "../zftape/zftape-ctl.h"
35
36/* zftape-init.c */
37EXPORT_SYMBOL(zft_cmpr_register);
38/* zftape-read.c */
39EXPORT_SYMBOL(zft_fetch_segment_fraction);
40/* zftape-buffers.c */
41EXPORT_SYMBOL(zft_vmalloc_once);
42EXPORT_SYMBOL(zft_vmalloc_always);
43EXPORT_SYMBOL(zft_vfree);
diff --git a/drivers/char/hw_random/core.c b/drivers/char/hw_random/core.c
index 154a81d328c1..ebace201bec6 100644
--- a/drivers/char/hw_random/core.c
+++ b/drivers/char/hw_random/core.c
@@ -162,7 +162,8 @@ static struct miscdevice rng_miscdev = {
162}; 162};
163 163
164 164
165static ssize_t hwrng_attr_current_store(struct class_device *class, 165static ssize_t hwrng_attr_current_store(struct device *dev,
166 struct device_attribute *attr,
166 const char *buf, size_t len) 167 const char *buf, size_t len)
167{ 168{
168 int err; 169 int err;
@@ -192,7 +193,8 @@ static ssize_t hwrng_attr_current_store(struct class_device *class,
192 return err ? : len; 193 return err ? : len;
193} 194}
194 195
195static ssize_t hwrng_attr_current_show(struct class_device *class, 196static ssize_t hwrng_attr_current_show(struct device *dev,
197 struct device_attribute *attr,
196 char *buf) 198 char *buf)
197{ 199{
198 int err; 200 int err;
@@ -210,7 +212,8 @@ static ssize_t hwrng_attr_current_show(struct class_device *class,
210 return ret; 212 return ret;
211} 213}
212 214
213static ssize_t hwrng_attr_available_show(struct class_device *class, 215static ssize_t hwrng_attr_available_show(struct device *dev,
216 struct device_attribute *attr,
214 char *buf) 217 char *buf)
215{ 218{
216 int err; 219 int err;
@@ -234,20 +237,18 @@ static ssize_t hwrng_attr_available_show(struct class_device *class,
234 return ret; 237 return ret;
235} 238}
236 239
237static CLASS_DEVICE_ATTR(rng_current, S_IRUGO | S_IWUSR, 240static DEVICE_ATTR(rng_current, S_IRUGO | S_IWUSR,
238 hwrng_attr_current_show, 241 hwrng_attr_current_show,
239 hwrng_attr_current_store); 242 hwrng_attr_current_store);
240static CLASS_DEVICE_ATTR(rng_available, S_IRUGO, 243static DEVICE_ATTR(rng_available, S_IRUGO,
241 hwrng_attr_available_show, 244 hwrng_attr_available_show,
242 NULL); 245 NULL);
243 246
244 247
245static void unregister_miscdev(void) 248static void unregister_miscdev(void)
246{ 249{
247 class_device_remove_file(rng_miscdev.class, 250 device_remove_file(rng_miscdev.this_device, &dev_attr_rng_available);
248 &class_device_attr_rng_available); 251 device_remove_file(rng_miscdev.this_device, &dev_attr_rng_current);
249 class_device_remove_file(rng_miscdev.class,
250 &class_device_attr_rng_current);
251 misc_deregister(&rng_miscdev); 252 misc_deregister(&rng_miscdev);
252} 253}
253 254
@@ -258,20 +259,19 @@ static int register_miscdev(void)
258 err = misc_register(&rng_miscdev); 259 err = misc_register(&rng_miscdev);
259 if (err) 260 if (err)
260 goto out; 261 goto out;
261 err = class_device_create_file(rng_miscdev.class, 262 err = device_create_file(rng_miscdev.this_device,
262 &class_device_attr_rng_current); 263 &dev_attr_rng_current);
263 if (err) 264 if (err)
264 goto err_misc_dereg; 265 goto err_misc_dereg;
265 err = class_device_create_file(rng_miscdev.class, 266 err = device_create_file(rng_miscdev.this_device,
266 &class_device_attr_rng_available); 267 &dev_attr_rng_available);
267 if (err) 268 if (err)
268 goto err_remove_current; 269 goto err_remove_current;
269out: 270out:
270 return err; 271 return err;
271 272
272err_remove_current: 273err_remove_current:
273 class_device_remove_file(rng_miscdev.class, 274 device_remove_file(rng_miscdev.this_device, &dev_attr_rng_current);
274 &class_device_attr_rng_current);
275err_misc_dereg: 275err_misc_dereg:
276 misc_deregister(&rng_miscdev); 276 misc_deregister(&rng_miscdev);
277 goto out; 277 goto out;
diff --git a/drivers/char/mem.c b/drivers/char/mem.c
index 55473371b7c6..e67eef4867ba 100644
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -980,10 +980,10 @@ static int __init chr_dev_init(void)
980 980
981 mem_class = class_create(THIS_MODULE, "mem"); 981 mem_class = class_create(THIS_MODULE, "mem");
982 for (i = 0; i < ARRAY_SIZE(devlist); i++) 982 for (i = 0; i < ARRAY_SIZE(devlist); i++)
983 class_device_create(mem_class, NULL, 983 device_create(mem_class, NULL,
984 MKDEV(MEM_MAJOR, devlist[i].minor), 984 MKDEV(MEM_MAJOR, devlist[i].minor),
985 NULL, devlist[i].name); 985 devlist[i].name);
986 986
987 return 0; 987 return 0;
988} 988}
989 989
diff --git a/drivers/char/misc.c b/drivers/char/misc.c
index 62ebe09656e3..7a484fc7cb9e 100644
--- a/drivers/char/misc.c
+++ b/drivers/char/misc.c
@@ -169,11 +169,6 @@ fail:
169 return err; 169 return err;
170} 170}
171 171
172/*
173 * TODO for 2.7:
174 * - add a struct kref to struct miscdevice and make all usages of
175 * them dynamic.
176 */
177static struct class *misc_class; 172static struct class *misc_class;
178 173
179static const struct file_operations misc_fops = { 174static const struct file_operations misc_fops = {
@@ -228,10 +223,10 @@ int misc_register(struct miscdevice * misc)
228 misc_minors[misc->minor >> 3] |= 1 << (misc->minor & 7); 223 misc_minors[misc->minor >> 3] |= 1 << (misc->minor & 7);
229 dev = MKDEV(MISC_MAJOR, misc->minor); 224 dev = MKDEV(MISC_MAJOR, misc->minor);
230 225
231 misc->class = class_device_create(misc_class, NULL, dev, misc->dev, 226 misc->this_device = device_create(misc_class, misc->parent, dev,
232 "%s", misc->name); 227 "%s", misc->name);
233 if (IS_ERR(misc->class)) { 228 if (IS_ERR(misc->this_device)) {
234 err = PTR_ERR(misc->class); 229 err = PTR_ERR(misc->this_device);
235 goto out; 230 goto out;
236 } 231 }
237 232
@@ -264,7 +259,7 @@ int misc_deregister(struct miscdevice * misc)
264 259
265 down(&misc_sem); 260 down(&misc_sem);
266 list_del(&misc->list); 261 list_del(&misc->list);
267 class_device_destroy(misc_class, MKDEV(MISC_MAJOR, misc->minor)); 262 device_destroy(misc_class, MKDEV(MISC_MAJOR, misc->minor));
268 if (i < DYNAMIC_MINORS && i>0) { 263 if (i < DYNAMIC_MINORS && i>0) {
269 misc_minors[i>>3] &= ~(1 << (misc->minor & 7)); 264 misc_minors[i>>3] &= ~(1 << (misc->minor & 7));
270 } 265 }
diff --git a/drivers/char/ppdev.c b/drivers/char/ppdev.c
index efc485edad1c..c1e3dd837fc8 100644
--- a/drivers/char/ppdev.c
+++ b/drivers/char/ppdev.c
@@ -752,13 +752,13 @@ static const struct file_operations pp_fops = {
752 752
753static void pp_attach(struct parport *port) 753static void pp_attach(struct parport *port)
754{ 754{
755 class_device_create(ppdev_class, NULL, MKDEV(PP_MAJOR, port->number), 755 device_create(ppdev_class, NULL, MKDEV(PP_MAJOR, port->number),
756 NULL, "parport%d", port->number); 756 "parport%d", port->number);
757} 757}
758 758
759static void pp_detach(struct parport *port) 759static void pp_detach(struct parport *port)
760{ 760{
761 class_device_destroy(ppdev_class, MKDEV(PP_MAJOR, port->number)); 761 device_destroy(ppdev_class, MKDEV(PP_MAJOR, port->number));
762} 762}
763 763
764static struct parport_driver pp_driver = { 764static struct parport_driver pp_driver = {
diff --git a/drivers/char/random.c b/drivers/char/random.c
index fa764688cad1..4c6782a1ecdb 100644
--- a/drivers/char/random.c
+++ b/drivers/char/random.c
@@ -1466,8 +1466,8 @@ static __init int seqgen_init(void)
1466late_initcall(seqgen_init); 1466late_initcall(seqgen_init);
1467 1467
1468#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) 1468#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
1469__u32 secure_tcpv6_sequence_number(__u32 *saddr, __u32 *daddr, 1469__u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr,
1470 __u16 sport, __u16 dport) 1470 __be16 sport, __be16 dport)
1471{ 1471{
1472 struct timeval tv; 1472 struct timeval tv;
1473 __u32 seq; 1473 __u32 seq;
@@ -1479,10 +1479,10 @@ __u32 secure_tcpv6_sequence_number(__u32 *saddr, __u32 *daddr,
1479 */ 1479 */
1480 1480
1481 memcpy(hash, saddr, 16); 1481 memcpy(hash, saddr, 16);
1482 hash[4]=(sport << 16) + dport; 1482 hash[4]=((__force u16)sport << 16) + (__force u16)dport;
1483 memcpy(&hash[5],keyptr->secret,sizeof(__u32) * 7); 1483 memcpy(&hash[5],keyptr->secret,sizeof(__u32) * 7);
1484 1484
1485 seq = twothirdsMD4Transform(daddr, hash) & HASH_MASK; 1485 seq = twothirdsMD4Transform((const __u32 *)daddr, hash) & HASH_MASK;
1486 seq += keyptr->count; 1486 seq += keyptr->count;
1487 1487
1488 do_gettimeofday(&tv); 1488 do_gettimeofday(&tv);
@@ -1496,7 +1496,7 @@ EXPORT_SYMBOL(secure_tcpv6_sequence_number);
1496/* The code below is shamelessly stolen from secure_tcp_sequence_number(). 1496/* The code below is shamelessly stolen from secure_tcp_sequence_number().
1497 * All blames to Andrey V. Savochkin <saw@msu.ru>. 1497 * All blames to Andrey V. Savochkin <saw@msu.ru>.
1498 */ 1498 */
1499__u32 secure_ip_id(__u32 daddr) 1499__u32 secure_ip_id(__be32 daddr)
1500{ 1500{
1501 struct keydata *keyptr; 1501 struct keydata *keyptr;
1502 __u32 hash[4]; 1502 __u32 hash[4];
@@ -1508,7 +1508,7 @@ __u32 secure_ip_id(__u32 daddr)
1508 * The dest ip address is placed in the starting vector, 1508 * The dest ip address is placed in the starting vector,
1509 * which is then hashed with random data. 1509 * which is then hashed with random data.
1510 */ 1510 */
1511 hash[0] = daddr; 1511 hash[0] = (__force __u32)daddr;
1512 hash[1] = keyptr->secret[9]; 1512 hash[1] = keyptr->secret[9];
1513 hash[2] = keyptr->secret[10]; 1513 hash[2] = keyptr->secret[10];
1514 hash[3] = keyptr->secret[11]; 1514 hash[3] = keyptr->secret[11];
@@ -1518,8 +1518,8 @@ __u32 secure_ip_id(__u32 daddr)
1518 1518
1519#ifdef CONFIG_INET 1519#ifdef CONFIG_INET
1520 1520
1521__u32 secure_tcp_sequence_number(__u32 saddr, __u32 daddr, 1521__u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr,
1522 __u16 sport, __u16 dport) 1522 __be16 sport, __be16 dport)
1523{ 1523{
1524 struct timeval tv; 1524 struct timeval tv;
1525 __u32 seq; 1525 __u32 seq;
@@ -1532,9 +1532,9 @@ __u32 secure_tcp_sequence_number(__u32 saddr, __u32 daddr,
1532 * Note that the words are placed into the starting vector, which is 1532 * Note that the words are placed into the starting vector, which is
1533 * then mixed with a partial MD4 over random data. 1533 * then mixed with a partial MD4 over random data.
1534 */ 1534 */
1535 hash[0]=saddr; 1535 hash[0]=(__force u32)saddr;
1536 hash[1]=daddr; 1536 hash[1]=(__force u32)daddr;
1537 hash[2]=(sport << 16) + dport; 1537 hash[2]=((__force u16)sport << 16) + (__force u16)dport;
1538 hash[3]=keyptr->secret[11]; 1538 hash[3]=keyptr->secret[11];
1539 1539
1540 seq = half_md4_transform(hash, keyptr->secret) & HASH_MASK; 1540 seq = half_md4_transform(hash, keyptr->secret) & HASH_MASK;
@@ -1559,7 +1559,7 @@ __u32 secure_tcp_sequence_number(__u32 saddr, __u32 daddr,
1559EXPORT_SYMBOL(secure_tcp_sequence_number); 1559EXPORT_SYMBOL(secure_tcp_sequence_number);
1560 1560
1561/* Generate secure starting point for ephemeral IPV4 transport port search */ 1561/* Generate secure starting point for ephemeral IPV4 transport port search */
1562u32 secure_ipv4_port_ephemeral(__u32 saddr, __u32 daddr, __u16 dport) 1562u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport)
1563{ 1563{
1564 struct keydata *keyptr = get_keyptr(); 1564 struct keydata *keyptr = get_keyptr();
1565 u32 hash[4]; 1565 u32 hash[4];
@@ -1568,25 +1568,25 @@ u32 secure_ipv4_port_ephemeral(__u32 saddr, __u32 daddr, __u16 dport)
1568 * Pick a unique starting offset for each ephemeral port search 1568 * Pick a unique starting offset for each ephemeral port search
1569 * (saddr, daddr, dport) and 48bits of random data. 1569 * (saddr, daddr, dport) and 48bits of random data.
1570 */ 1570 */
1571 hash[0] = saddr; 1571 hash[0] = (__force u32)saddr;
1572 hash[1] = daddr; 1572 hash[1] = (__force u32)daddr;
1573 hash[2] = dport ^ keyptr->secret[10]; 1573 hash[2] = (__force u32)dport ^ keyptr->secret[10];
1574 hash[3] = keyptr->secret[11]; 1574 hash[3] = keyptr->secret[11];
1575 1575
1576 return half_md4_transform(hash, keyptr->secret); 1576 return half_md4_transform(hash, keyptr->secret);
1577} 1577}
1578 1578
1579#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) 1579#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
1580u32 secure_ipv6_port_ephemeral(const __u32 *saddr, const __u32 *daddr, __u16 dport) 1580u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, __be16 dport)
1581{ 1581{
1582 struct keydata *keyptr = get_keyptr(); 1582 struct keydata *keyptr = get_keyptr();
1583 u32 hash[12]; 1583 u32 hash[12];
1584 1584
1585 memcpy(hash, saddr, 16); 1585 memcpy(hash, saddr, 16);
1586 hash[4] = dport; 1586 hash[4] = (__force u32)dport;
1587 memcpy(&hash[5],keyptr->secret,sizeof(__u32) * 7); 1587 memcpy(&hash[5],keyptr->secret,sizeof(__u32) * 7);
1588 1588
1589 return twothirdsMD4Transform(daddr, hash); 1589 return twothirdsMD4Transform((const __u32 *)daddr, hash);
1590} 1590}
1591#endif 1591#endif
1592 1592
@@ -1595,17 +1595,17 @@ u32 secure_ipv6_port_ephemeral(const __u32 *saddr, const __u32 *daddr, __u16 dpo
1595 * bit's 32-47 increase every key exchange 1595 * bit's 32-47 increase every key exchange
1596 * 0-31 hash(source, dest) 1596 * 0-31 hash(source, dest)
1597 */ 1597 */
1598u64 secure_dccp_sequence_number(__u32 saddr, __u32 daddr, 1598u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr,
1599 __u16 sport, __u16 dport) 1599 __be16 sport, __be16 dport)
1600{ 1600{
1601 struct timeval tv; 1601 struct timeval tv;
1602 u64 seq; 1602 u64 seq;
1603 __u32 hash[4]; 1603 __u32 hash[4];
1604 struct keydata *keyptr = get_keyptr(); 1604 struct keydata *keyptr = get_keyptr();
1605 1605
1606 hash[0] = saddr; 1606 hash[0] = (__force u32)saddr;
1607 hash[1] = daddr; 1607 hash[1] = (__force u32)daddr;
1608 hash[2] = (sport << 16) + dport; 1608 hash[2] = ((__force u16)sport << 16) + (__force u16)dport;
1609 hash[3] = keyptr->secret[11]; 1609 hash[3] = keyptr->secret[11];
1610 1610
1611 seq = half_md4_transform(hash, keyptr->secret); 1611 seq = half_md4_transform(hash, keyptr->secret);
@@ -1641,7 +1641,7 @@ unsigned int get_random_int(void)
1641 * drain on it), and uses halfMD4Transform within the second. We 1641 * drain on it), and uses halfMD4Transform within the second. We
1642 * also mix it with jiffies and the PID: 1642 * also mix it with jiffies and the PID:
1643 */ 1643 */
1644 return secure_ip_id(current->pid + jiffies); 1644 return secure_ip_id((__force __be32)(current->pid + jiffies));
1645} 1645}
1646 1646
1647/* 1647/*
diff --git a/drivers/char/raw.c b/drivers/char/raw.c
index 89b718e326e5..3b32313f6eb4 100644
--- a/drivers/char/raw.c
+++ b/drivers/char/raw.c
@@ -127,9 +127,9 @@ raw_ioctl(struct inode *inode, struct file *filp,
127 127
128static void bind_device(struct raw_config_request *rq) 128static void bind_device(struct raw_config_request *rq)
129{ 129{
130 class_device_destroy(raw_class, MKDEV(RAW_MAJOR, rq->raw_minor)); 130 device_destroy(raw_class, MKDEV(RAW_MAJOR, rq->raw_minor));
131 class_device_create(raw_class, NULL, MKDEV(RAW_MAJOR, rq->raw_minor), 131 device_create(raw_class, NULL, MKDEV(RAW_MAJOR, rq->raw_minor),
132 NULL, "raw%d", rq->raw_minor); 132 "raw%d", rq->raw_minor);
133} 133}
134 134
135/* 135/*
@@ -200,7 +200,7 @@ static int raw_ctl_ioctl(struct inode *inode, struct file *filp,
200 if (rq.block_major == 0 && rq.block_minor == 0) { 200 if (rq.block_major == 0 && rq.block_minor == 0) {
201 /* unbind */ 201 /* unbind */
202 rawdev->binding = NULL; 202 rawdev->binding = NULL;
203 class_device_destroy(raw_class, 203 device_destroy(raw_class,
204 MKDEV(RAW_MAJOR, rq.raw_minor)); 204 MKDEV(RAW_MAJOR, rq.raw_minor));
205 } else { 205 } else {
206 rawdev->binding = bdget(dev); 206 rawdev->binding = bdget(dev);
@@ -283,7 +283,7 @@ static int __init raw_init(void)
283 ret = PTR_ERR(raw_class); 283 ret = PTR_ERR(raw_class);
284 goto error_region; 284 goto error_region;
285 } 285 }
286 class_device_create(raw_class, NULL, MKDEV(RAW_MAJOR, 0), NULL, "rawctl"); 286 device_create(raw_class, NULL, MKDEV(RAW_MAJOR, 0), "rawctl");
287 287
288 return 0; 288 return 0;
289 289
@@ -295,7 +295,7 @@ error:
295 295
296static void __exit raw_exit(void) 296static void __exit raw_exit(void)
297{ 297{
298 class_device_destroy(raw_class, MKDEV(RAW_MAJOR, 0)); 298 device_destroy(raw_class, MKDEV(RAW_MAJOR, 0));
299 class_destroy(raw_class); 299 class_destroy(raw_class);
300 cdev_del(&raw_cdev); 300 cdev_del(&raw_cdev);
301 unregister_chrdev_region(MKDEV(RAW_MAJOR, 0), MAX_RAW_MINORS); 301 unregister_chrdev_region(MKDEV(RAW_MAJOR, 0), MAX_RAW_MINORS);
diff --git a/drivers/char/rio/riocmd.c b/drivers/char/rio/riocmd.c
index 4df6ab2206a1..167ebc84e8d7 100644
--- a/drivers/char/rio/riocmd.c
+++ b/drivers/char/rio/riocmd.c
@@ -922,7 +922,7 @@ int RIOUnUse(unsigned long iPortP, struct CmdBlk *CmdBlkP)
922** 922**
923** Packet is an actual packet structure to be filled in with the packet 923** Packet is an actual packet structure to be filled in with the packet
924** information associated with the command. You need to fill in everything, 924** information associated with the command. You need to fill in everything,
925** as the command processore doesn't process the command packet in any way. 925** as the command processor doesn't process the command packet in any way.
926** 926**
927** The PreFuncP is called before the packet is enqueued on the host rup. 927** The PreFuncP is called before the packet is enqueued on the host rup.
928** PreFuncP is called as (*PreFuncP)(PreArg, CmdBlkP);. PreFuncP must 928** PreFuncP is called as (*PreFuncP)(PreArg, CmdBlkP);. PreFuncP must
diff --git a/drivers/char/rio/rioinit.c b/drivers/char/rio/rioinit.c
index 99f3df02b61c..0794844369d6 100644
--- a/drivers/char/rio/rioinit.c
+++ b/drivers/char/rio/rioinit.c
@@ -222,7 +222,7 @@ int RIOBoardTest(unsigned long paddr, void __iomem *caddr, unsigned char type, i
222** which value will be written into memory. 222** which value will be written into memory.
223** Call with op set to zero means that the RAM will not be read and checked 223** Call with op set to zero means that the RAM will not be read and checked
224** before it is written. 224** before it is written.
225** Call with op not zero, and the RAM will be read and compated with val[op-1] 225** Call with op not zero and the RAM will be read and compared with val[op-1]
226** to check that the data from the previous phase was retained. 226** to check that the data from the previous phase was retained.
227*/ 227*/
228 228
diff --git a/drivers/char/rio/rioparam.c b/drivers/char/rio/rioparam.c
index 1066d9760704..bb498d24adcc 100644
--- a/drivers/char/rio/rioparam.c
+++ b/drivers/char/rio/rioparam.c
@@ -87,8 +87,8 @@ static char *_rioparam_c_sccs_ = "@(#)rioparam.c 1.3";
87** command bit set onto the port. The command bit is in the len field, 87** command bit set onto the port. The command bit is in the len field,
88** and gets ORed in with the actual byte count. 88** and gets ORed in with the actual byte count.
89** 89**
90** When you send a packet with the command bit set, then the first 90** When you send a packet with the command bit set the first
91** data byte ( data[0] ) is interpretted as the command to execute. 91** data byte (data[0]) is interpreted as the command to execute.
92** It also governs what data structure overlay should accompany the packet. 92** It also governs what data structure overlay should accompany the packet.
93** Commands are defined in cirrus/cirrus.h 93** Commands are defined in cirrus/cirrus.h
94** 94**
@@ -103,7 +103,7 @@ static char *_rioparam_c_sccs_ = "@(#)rioparam.c 1.3";
103** 103**
104** Most commands do not use the remaining bytes in the data array. The 104** Most commands do not use the remaining bytes in the data array. The
105** exceptions are OPEN MOPEN and CONFIG. (NB. As with the SI CONFIG and 105** exceptions are OPEN MOPEN and CONFIG. (NB. As with the SI CONFIG and
106** OPEN are currently analagous). With these three commands the following 106** OPEN are currently analogous). With these three commands the following
107** 11 data bytes are all used to pass config information such as baud rate etc. 107** 11 data bytes are all used to pass config information such as baud rate etc.
108** The fields are also defined in cirrus.h. Some contain straightforward 108** The fields are also defined in cirrus.h. Some contain straightforward
109** information such as the transmit XON character. Two contain the transmit and 109** information such as the transmit XON character. Two contain the transmit and
diff --git a/drivers/char/tlclk.c b/drivers/char/tlclk.c
index 2444a0e24b31..244d30a03fef 100644
--- a/drivers/char/tlclk.c
+++ b/drivers/char/tlclk.c
@@ -792,15 +792,14 @@ static int __init tlclk_init(void)
792 ret = misc_register(&tlclk_miscdev); 792 ret = misc_register(&tlclk_miscdev);
793 if (ret < 0) { 793 if (ret < 0) {
794 printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret); 794 printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
795 ret = -EBUSY;
796 goto out3; 795 goto out3;
797 } 796 }
798 797
799 tlclk_device = platform_device_register_simple("telco_clock", 798 tlclk_device = platform_device_register_simple("telco_clock",
800 -1, NULL, 0); 799 -1, NULL, 0);
801 if (!tlclk_device) { 800 if (IS_ERR(tlclk_device)) {
802 printk(KERN_ERR "tlclk: platform_device_register failed.\n"); 801 printk(KERN_ERR "tlclk: platform_device_register failed.\n");
803 ret = -EBUSY; 802 ret = PTR_ERR(tlclk_device);
804 goto out4; 803 goto out4;
805 } 804 }
806 805
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c
index 36f91a655275..774fa861169a 100644
--- a/drivers/char/tpm/tpm.c
+++ b/drivers/char/tpm/tpm.c
@@ -1130,7 +1130,7 @@ struct tpm_chip *tpm_register_hardware(struct device *dev, const struct tpm_vend
1130 scnprintf(devname, DEVNAME_SIZE, "%s%d", "tpm", chip->dev_num); 1130 scnprintf(devname, DEVNAME_SIZE, "%s%d", "tpm", chip->dev_num);
1131 chip->vendor.miscdev.name = devname; 1131 chip->vendor.miscdev.name = devname;
1132 1132
1133 chip->vendor.miscdev.dev = dev; 1133 chip->vendor.miscdev.parent = dev;
1134 chip->dev = get_device(dev); 1134 chip->dev = get_device(dev);
1135 1135
1136 if (misc_register(&chip->vendor.miscdev)) { 1136 if (misc_register(&chip->vendor.miscdev)) {
diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c
index 83e9e7d9b58c..b3cfc8bc613c 100644
--- a/drivers/char/tty_io.c
+++ b/drivers/char/tty_io.c
@@ -3615,7 +3615,8 @@ static struct class *tty_class;
3615 * This field is optional, if there is no known struct device 3615 * This field is optional, if there is no known struct device
3616 * for this tty device it can be set to NULL safely. 3616 * for this tty device it can be set to NULL safely.
3617 * 3617 *
3618 * Returns a pointer to the class device (or ERR_PTR(-EFOO) on error). 3618 * Returns a pointer to the struct device for this tty device
3619 * (or ERR_PTR(-EFOO) on error).
3619 * 3620 *
3620 * This call is required to be made to register an individual tty device 3621 * This call is required to be made to register an individual tty device
3621 * if the tty driver's flags have the TTY_DRIVER_DYNAMIC_DEV bit set. If 3622 * if the tty driver's flags have the TTY_DRIVER_DYNAMIC_DEV bit set. If
@@ -3625,8 +3626,8 @@ static struct class *tty_class;
3625 * Locking: ?? 3626 * Locking: ??
3626 */ 3627 */
3627 3628
3628struct class_device *tty_register_device(struct tty_driver *driver, 3629struct device *tty_register_device(struct tty_driver *driver, unsigned index,
3629 unsigned index, struct device *device) 3630 struct device *device)
3630{ 3631{
3631 char name[64]; 3632 char name[64];
3632 dev_t dev = MKDEV(driver->major, driver->minor_start) + index; 3633 dev_t dev = MKDEV(driver->major, driver->minor_start) + index;
@@ -3642,7 +3643,7 @@ struct class_device *tty_register_device(struct tty_driver *driver,
3642 else 3643 else
3643 tty_line_name(driver, index, name); 3644 tty_line_name(driver, index, name);
3644 3645
3645 return class_device_create(tty_class, NULL, dev, device, "%s", name); 3646 return device_create(tty_class, device, dev, name);
3646} 3647}
3647 3648
3648/** 3649/**
@@ -3658,7 +3659,7 @@ struct class_device *tty_register_device(struct tty_driver *driver,
3658 3659
3659void tty_unregister_device(struct tty_driver *driver, unsigned index) 3660void tty_unregister_device(struct tty_driver *driver, unsigned index)
3660{ 3661{
3661 class_device_destroy(tty_class, MKDEV(driver->major, driver->minor_start) + index); 3662 device_destroy(tty_class, MKDEV(driver->major, driver->minor_start) + index);
3662} 3663}
3663 3664
3664EXPORT_SYMBOL(tty_register_device); 3665EXPORT_SYMBOL(tty_register_device);
@@ -3898,20 +3899,20 @@ static int __init tty_init(void)
3898 if (cdev_add(&tty_cdev, MKDEV(TTYAUX_MAJOR, 0), 1) || 3899 if (cdev_add(&tty_cdev, MKDEV(TTYAUX_MAJOR, 0), 1) ||
3899 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 0), 1, "/dev/tty") < 0) 3900 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 0), 1, "/dev/tty") < 0)
3900 panic("Couldn't register /dev/tty driver\n"); 3901 panic("Couldn't register /dev/tty driver\n");
3901 class_device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 0), NULL, "tty"); 3902 device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 0), "tty");
3902 3903
3903 cdev_init(&console_cdev, &console_fops); 3904 cdev_init(&console_cdev, &console_fops);
3904 if (cdev_add(&console_cdev, MKDEV(TTYAUX_MAJOR, 1), 1) || 3905 if (cdev_add(&console_cdev, MKDEV(TTYAUX_MAJOR, 1), 1) ||
3905 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 1), 1, "/dev/console") < 0) 3906 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 1), 1, "/dev/console") < 0)
3906 panic("Couldn't register /dev/console driver\n"); 3907 panic("Couldn't register /dev/console driver\n");
3907 class_device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 1), NULL, "console"); 3908 device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 1), "console");
3908 3909
3909#ifdef CONFIG_UNIX98_PTYS 3910#ifdef CONFIG_UNIX98_PTYS
3910 cdev_init(&ptmx_cdev, &ptmx_fops); 3911 cdev_init(&ptmx_cdev, &ptmx_fops);
3911 if (cdev_add(&ptmx_cdev, MKDEV(TTYAUX_MAJOR, 2), 1) || 3912 if (cdev_add(&ptmx_cdev, MKDEV(TTYAUX_MAJOR, 2), 1) ||
3912 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 2), 1, "/dev/ptmx") < 0) 3913 register_chrdev_region(MKDEV(TTYAUX_MAJOR, 2), 1, "/dev/ptmx") < 0)
3913 panic("Couldn't register /dev/ptmx driver\n"); 3914 panic("Couldn't register /dev/ptmx driver\n");
3914 class_device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 2), NULL, "ptmx"); 3915 device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 2), "ptmx");
3915#endif 3916#endif
3916 3917
3917#ifdef CONFIG_VT 3918#ifdef CONFIG_VT
@@ -3919,7 +3920,7 @@ static int __init tty_init(void)
3919 if (cdev_add(&vc0_cdev, MKDEV(TTY_MAJOR, 0), 1) || 3920 if (cdev_add(&vc0_cdev, MKDEV(TTY_MAJOR, 0), 1) ||
3920 register_chrdev_region(MKDEV(TTY_MAJOR, 0), 1, "/dev/vc/0") < 0) 3921 register_chrdev_region(MKDEV(TTY_MAJOR, 0), 1, "/dev/vc/0") < 0)
3921 panic("Couldn't register /dev/tty0 driver\n"); 3922 panic("Couldn't register /dev/tty0 driver\n");
3922 class_device_create(tty_class, NULL, MKDEV(TTY_MAJOR, 0), NULL, "tty0"); 3923 device_create(tty_class, NULL, MKDEV(TTY_MAJOR, 0), "tty0");
3923 3924
3924 vty_init(); 3925 vty_init();
3925#endif 3926#endif
diff --git a/drivers/char/vc_screen.c b/drivers/char/vc_screen.c
index bd7a98c6ea7a..f442b574b44a 100644
--- a/drivers/char/vc_screen.c
+++ b/drivers/char/vc_screen.c
@@ -476,16 +476,16 @@ static struct class *vc_class;
476 476
477void vcs_make_sysfs(struct tty_struct *tty) 477void vcs_make_sysfs(struct tty_struct *tty)
478{ 478{
479 class_device_create(vc_class, NULL, MKDEV(VCS_MAJOR, tty->index + 1), 479 device_create(vc_class, NULL, MKDEV(VCS_MAJOR, tty->index + 1),
480 NULL, "vcs%u", tty->index + 1); 480 "vcs%u", tty->index + 1);
481 class_device_create(vc_class, NULL, MKDEV(VCS_MAJOR, tty->index + 129), 481 device_create(vc_class, NULL, MKDEV(VCS_MAJOR, tty->index + 129),
482 NULL, "vcsa%u", tty->index + 1); 482 "vcsa%u", tty->index + 1);
483} 483}
484 484
485void vcs_remove_sysfs(struct tty_struct *tty) 485void vcs_remove_sysfs(struct tty_struct *tty)
486{ 486{
487 class_device_destroy(vc_class, MKDEV(VCS_MAJOR, tty->index + 1)); 487 device_destroy(vc_class, MKDEV(VCS_MAJOR, tty->index + 1));
488 class_device_destroy(vc_class, MKDEV(VCS_MAJOR, tty->index + 129)); 488 device_destroy(vc_class, MKDEV(VCS_MAJOR, tty->index + 129));
489} 489}
490 490
491int __init vcs_init(void) 491int __init vcs_init(void)
@@ -494,7 +494,7 @@ int __init vcs_init(void)
494 panic("unable to get major %d for vcs device", VCS_MAJOR); 494 panic("unable to get major %d for vcs device", VCS_MAJOR);
495 vc_class = class_create(THIS_MODULE, "vc"); 495 vc_class = class_create(THIS_MODULE, "vc");
496 496
497 class_device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 0), NULL, "vcs"); 497 device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 0), "vcs");
498 class_device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 128), NULL, "vcsa"); 498 device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 128), "vcsa");
499 return 0; 499 return 0;
500} 500}
diff --git a/drivers/char/vt.c b/drivers/char/vt.c
index 8ee04adc37f0..75ff0286e1ad 100644
--- a/drivers/char/vt.c
+++ b/drivers/char/vt.c
@@ -112,7 +112,7 @@
112struct con_driver { 112struct con_driver {
113 const struct consw *con; 113 const struct consw *con;
114 const char *desc; 114 const char *desc;
115 struct class_device *class_dev; 115 struct device *dev;
116 int node; 116 int node;
117 int first; 117 int first;
118 int last; 118 int last;
@@ -3023,10 +3023,10 @@ static inline int vt_unbind(struct con_driver *con)
3023} 3023}
3024#endif /* CONFIG_VT_HW_CONSOLE_BINDING */ 3024#endif /* CONFIG_VT_HW_CONSOLE_BINDING */
3025 3025
3026static ssize_t store_bind(struct class_device *class_device, 3026static ssize_t store_bind(struct device *dev, struct device_attribute *attr,
3027 const char *buf, size_t count) 3027 const char *buf, size_t count)
3028{ 3028{
3029 struct con_driver *con = class_get_devdata(class_device); 3029 struct con_driver *con = dev_get_drvdata(dev);
3030 int bind = simple_strtoul(buf, NULL, 0); 3030 int bind = simple_strtoul(buf, NULL, 0);
3031 3031
3032 if (bind) 3032 if (bind)
@@ -3037,17 +3037,19 @@ static ssize_t store_bind(struct class_device *class_device,
3037 return count; 3037 return count;
3038} 3038}
3039 3039
3040static ssize_t show_bind(struct class_device *class_device, char *buf) 3040static ssize_t show_bind(struct device *dev, struct device_attribute *attr,
3041 char *buf)
3041{ 3042{
3042 struct con_driver *con = class_get_devdata(class_device); 3043 struct con_driver *con = dev_get_drvdata(dev);
3043 int bind = con_is_bound(con->con); 3044 int bind = con_is_bound(con->con);
3044 3045
3045 return snprintf(buf, PAGE_SIZE, "%i\n", bind); 3046 return snprintf(buf, PAGE_SIZE, "%i\n", bind);
3046} 3047}
3047 3048
3048static ssize_t show_name(struct class_device *class_device, char *buf) 3049static ssize_t show_name(struct device *dev, struct device_attribute *attr,
3050 char *buf)
3049{ 3051{
3050 struct con_driver *con = class_get_devdata(class_device); 3052 struct con_driver *con = dev_get_drvdata(dev);
3051 3053
3052 return snprintf(buf, PAGE_SIZE, "%s %s\n", 3054 return snprintf(buf, PAGE_SIZE, "%s %s\n",
3053 (con->flag & CON_DRIVER_FLAG_MODULE) ? "(M)" : "(S)", 3055 (con->flag & CON_DRIVER_FLAG_MODULE) ? "(M)" : "(S)",
@@ -3055,43 +3057,40 @@ static ssize_t show_name(struct class_device *class_device, char *buf)
3055 3057
3056} 3058}
3057 3059
3058static struct class_device_attribute class_device_attrs[] = { 3060static struct device_attribute device_attrs[] = {
3059 __ATTR(bind, S_IRUGO|S_IWUSR, show_bind, store_bind), 3061 __ATTR(bind, S_IRUGO|S_IWUSR, show_bind, store_bind),
3060 __ATTR(name, S_IRUGO, show_name, NULL), 3062 __ATTR(name, S_IRUGO, show_name, NULL),
3061}; 3063};
3062 3064
3063static int vtconsole_init_class_device(struct con_driver *con) 3065static int vtconsole_init_device(struct con_driver *con)
3064{ 3066{
3065 int i; 3067 int i;
3066 int error = 0; 3068 int error = 0;
3067 3069
3068 con->flag |= CON_DRIVER_FLAG_ATTR; 3070 con->flag |= CON_DRIVER_FLAG_ATTR;
3069 class_set_devdata(con->class_dev, con); 3071 dev_set_drvdata(con->dev, con);
3070 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++) { 3072 for (i = 0; i < ARRAY_SIZE(device_attrs); i++) {
3071 error = class_device_create_file(con->class_dev, 3073 error = device_create_file(con->dev, &device_attrs[i]);
3072 &class_device_attrs[i]);
3073 if (error) 3074 if (error)
3074 break; 3075 break;
3075 } 3076 }
3076 3077
3077 if (error) { 3078 if (error) {
3078 while (--i >= 0) 3079 while (--i >= 0)
3079 class_device_remove_file(con->class_dev, 3080 device_remove_file(con->dev, &device_attrs[i]);
3080 &class_device_attrs[i]);
3081 con->flag &= ~CON_DRIVER_FLAG_ATTR; 3081 con->flag &= ~CON_DRIVER_FLAG_ATTR;
3082 } 3082 }
3083 3083
3084 return error; 3084 return error;
3085} 3085}
3086 3086
3087static void vtconsole_deinit_class_device(struct con_driver *con) 3087static void vtconsole_deinit_device(struct con_driver *con)
3088{ 3088{
3089 int i; 3089 int i;
3090 3090
3091 if (con->flag & CON_DRIVER_FLAG_ATTR) { 3091 if (con->flag & CON_DRIVER_FLAG_ATTR) {
3092 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++) 3092 for (i = 0; i < ARRAY_SIZE(device_attrs); i++)
3093 class_device_remove_file(con->class_dev, 3093 device_remove_file(con->dev, &device_attrs[i]);
3094 &class_device_attrs[i]);
3095 con->flag &= ~CON_DRIVER_FLAG_ATTR; 3094 con->flag &= ~CON_DRIVER_FLAG_ATTR;
3096 } 3095 }
3097} 3096}
@@ -3179,18 +3178,17 @@ int register_con_driver(const struct consw *csw, int first, int last)
3179 if (retval) 3178 if (retval)
3180 goto err; 3179 goto err;
3181 3180
3182 con_driver->class_dev = class_device_create(vtconsole_class, NULL, 3181 con_driver->dev = device_create(vtconsole_class, NULL,
3183 MKDEV(0, con_driver->node), 3182 MKDEV(0, con_driver->node),
3184 NULL, "vtcon%i", 3183 "vtcon%i", con_driver->node);
3185 con_driver->node);
3186 3184
3187 if (IS_ERR(con_driver->class_dev)) { 3185 if (IS_ERR(con_driver->dev)) {
3188 printk(KERN_WARNING "Unable to create class_device for %s; " 3186 printk(KERN_WARNING "Unable to create device for %s; "
3189 "errno = %ld\n", con_driver->desc, 3187 "errno = %ld\n", con_driver->desc,
3190 PTR_ERR(con_driver->class_dev)); 3188 PTR_ERR(con_driver->dev));
3191 con_driver->class_dev = NULL; 3189 con_driver->dev = NULL;
3192 } else { 3190 } else {
3193 vtconsole_init_class_device(con_driver); 3191 vtconsole_init_device(con_driver);
3194 } 3192 }
3195 3193
3196err: 3194err:
@@ -3226,12 +3224,12 @@ int unregister_con_driver(const struct consw *csw)
3226 3224
3227 if (con_driver->con == csw && 3225 if (con_driver->con == csw &&
3228 con_driver->flag & CON_DRIVER_FLAG_MODULE) { 3226 con_driver->flag & CON_DRIVER_FLAG_MODULE) {
3229 vtconsole_deinit_class_device(con_driver); 3227 vtconsole_deinit_device(con_driver);
3230 class_device_destroy(vtconsole_class, 3228 device_destroy(vtconsole_class,
3231 MKDEV(0, con_driver->node)); 3229 MKDEV(0, con_driver->node));
3232 con_driver->con = NULL; 3230 con_driver->con = NULL;
3233 con_driver->desc = NULL; 3231 con_driver->desc = NULL;
3234 con_driver->class_dev = NULL; 3232 con_driver->dev = NULL;
3235 con_driver->node = 0; 3233 con_driver->node = 0;
3236 con_driver->flag = 0; 3234 con_driver->flag = 0;
3237 con_driver->first = 0; 3235 con_driver->first = 0;
@@ -3289,19 +3287,18 @@ static int __init vtconsole_class_init(void)
3289 for (i = 0; i < MAX_NR_CON_DRIVER; i++) { 3287 for (i = 0; i < MAX_NR_CON_DRIVER; i++) {
3290 struct con_driver *con = &registered_con_driver[i]; 3288 struct con_driver *con = &registered_con_driver[i];
3291 3289
3292 if (con->con && !con->class_dev) { 3290 if (con->con && !con->dev) {
3293 con->class_dev = 3291 con->dev = device_create(vtconsole_class, NULL,
3294 class_device_create(vtconsole_class, NULL, 3292 MKDEV(0, con->node),
3295 MKDEV(0, con->node), NULL, 3293 "vtcon%i", con->node);
3296 "vtcon%i", con->node);
3297 3294
3298 if (IS_ERR(con->class_dev)) { 3295 if (IS_ERR(con->dev)) {
3299 printk(KERN_WARNING "Unable to create " 3296 printk(KERN_WARNING "Unable to create "
3300 "class_device for %s; errno = %ld\n", 3297 "device for %s; errno = %ld\n",
3301 con->desc, PTR_ERR(con->class_dev)); 3298 con->desc, PTR_ERR(con->dev));
3302 con->class_dev = NULL; 3299 con->dev = NULL;
3303 } else { 3300 } else {
3304 vtconsole_init_class_device(con); 3301 vtconsole_init_device(con);
3305 } 3302 }
3306 } 3303 }
3307 } 3304 }
diff --git a/drivers/char/watchdog/Kconfig b/drivers/char/watchdog/Kconfig
index 0187b1185323..ea09d0c974ea 100644
--- a/drivers/char/watchdog/Kconfig
+++ b/drivers/char/watchdog/Kconfig
@@ -340,6 +340,14 @@ config ITCO_WDT
340 To compile this driver as a module, choose M here: the 340 To compile this driver as a module, choose M here: the
341 module will be called iTCO_wdt. 341 module will be called iTCO_wdt.
342 342
343config ITCO_VENDOR_SUPPORT
344 bool "Intel TCO Timer/Watchdog Specific Vendor Support"
345 depends on ITCO_WDT
346 ---help---
347 Add vendor specific support to the intel TCO timer based watchdog
348 devices. At this moment we only have additional support for some
349 SuperMicro Inc. motherboards.
350
343config SC1200_WDT 351config SC1200_WDT
344 tristate "National Semiconductor PC87307/PC97307 (ala SC1200) Watchdog" 352 tristate "National Semiconductor PC87307/PC97307 (ala SC1200) Watchdog"
345 depends on WATCHDOG && X86 353 depends on WATCHDOG && X86
@@ -363,6 +371,20 @@ config SCx200_WDT
363 371
364 If compiled as a module, it will be called scx200_wdt. 372 If compiled as a module, it will be called scx200_wdt.
365 373
374config PC87413_WDT
375 tristate "NS PC87413 watchdog"
376 depends on WATCHDOG && X86
377 ---help---
378 This is the driver for the hardware watchdog on the PC87413 chipset
379 This watchdog simply watches your kernel to make sure it doesn't
380 freeze, and if it does, it reboots your computer after a certain
381 amount of time.
382
383 To compile this driver as a module, choose M here: the
384 module will be called pc87413_wdt.
385
386 Most people will say N.
387
366config 60XX_WDT 388config 60XX_WDT
367 tristate "SBC-60XX Watchdog Timer" 389 tristate "SBC-60XX Watchdog Timer"
368 depends on WATCHDOG && X86 390 depends on WATCHDOG && X86
@@ -553,6 +575,16 @@ config INDYDOG
553 timer expired and no process has written to /dev/watchdog during 575 timer expired and no process has written to /dev/watchdog during
554 that time. 576 that time.
555 577
578config WDT_RM9K_GPI
579 tristate "RM9000/GPI hardware watchdog"
580 depends on WATCHDOG && CPU_RM9000
581 help
582 Watchdog implementation using the GPI hardware found on
583 PMC-Sierra RM9xxx CPUs.
584
585 To compile this driver as a module, choose M here: the
586 module will be called rm9k_wdt.
587
556# S390 Architecture 588# S390 Architecture
557 589
558config ZVM_WATCHDOG 590config ZVM_WATCHDOG
diff --git a/drivers/char/watchdog/Makefile b/drivers/char/watchdog/Makefile
index 36440497047c..2cd8ff8d10ac 100644
--- a/drivers/char/watchdog/Makefile
+++ b/drivers/char/watchdog/Makefile
@@ -47,9 +47,10 @@ obj-$(CONFIG_IBMASR) += ibmasr.o
47obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o 47obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
48obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o 48obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o
49obj-$(CONFIG_I8XX_TCO) += i8xx_tco.o 49obj-$(CONFIG_I8XX_TCO) += i8xx_tco.o
50obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o 50obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o iTCO_vendor_support.o
51obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o 51obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
52obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o 52obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
53obj-$(CONFIG_PC87413_WDT) += pc87413_wdt.o
53obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o 54obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
54obj-$(CONFIG_SBC8360_WDT) += sbc8360.o 55obj-$(CONFIG_SBC8360_WDT) += sbc8360.o
55obj-$(CONFIG_CPU5_WDT) += cpu5wdt.o 56obj-$(CONFIG_CPU5_WDT) += cpu5wdt.o
@@ -72,6 +73,7 @@ obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o
72 73
73# MIPS Architecture 74# MIPS Architecture
74obj-$(CONFIG_INDYDOG) += indydog.o 75obj-$(CONFIG_INDYDOG) += indydog.o
76obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
75 77
76# S390 Architecture 78# S390 Architecture
77 79
diff --git a/drivers/char/watchdog/iTCO_vendor_support.c b/drivers/char/watchdog/iTCO_vendor_support.c
new file mode 100644
index 000000000000..415083990097
--- /dev/null
+++ b/drivers/char/watchdog/iTCO_vendor_support.c
@@ -0,0 +1,307 @@
1/*
2 * intel TCO vendor specific watchdog driver support
3 *
4 * (c) Copyright 2006 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 */
15
16/*
17 * Includes, defines, variables, module parameters, ...
18 */
19
20/* Module and version information */
21#define DRV_NAME "iTCO_vendor_support"
22#define DRV_VERSION "1.01"
23#define DRV_RELDATE "11-Nov-2006"
24#define PFX DRV_NAME ": "
25
26/* Includes */
27#include <linux/module.h> /* For module specific items */
28#include <linux/moduleparam.h> /* For new moduleparam's */
29#include <linux/types.h> /* For standard types (like size_t) */
30#include <linux/errno.h> /* For the -ENODEV/... values */
31#include <linux/kernel.h> /* For printk/panic/... */
32#include <linux/init.h> /* For __init/__exit/... */
33#include <linux/ioport.h> /* For io-port access */
34
35#include <asm/io.h> /* For inb/outb/... */
36
37/* iTCO defines */
38#define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */
39#define TCOBASE acpibase + 0x60 /* TCO base address */
40#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
41
42/* List of vendor support modes */
43#define SUPERMICRO_OLD_BOARD 1 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
44#define SUPERMICRO_NEW_BOARD 2 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
45
46static int vendorsupport = 0;
47module_param(vendorsupport, int, 0);
48MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+");
49
50/*
51 * Vendor Specific Support
52 */
53
54/*
55 * Vendor Support: 1
56 * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
57 * iTCO chipset: ICH2
58 *
59 * Code contributed by: R. Seretny <lkpatches@paypc.com>
60 * Documentation obtained by R. Seretny from SuperMicro Technical Support
61 *
62 * To enable Watchdog function:
63 * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
64 * This setting enables SMI to clear the watchdog expired flag.
65 * If BIOS or CPU fail which may cause SMI hang, then system will
66 * reboot. When application starts to use watchdog function,
67 * application has to take over the control from SMI.
68 *
69 * For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
70 * function.
71 *
72 * Note: The system will reboot when Expire Flag is set TWICE.
73 * So, if the watchdog timer is 20 seconds, then the maximum hang
74 * time is about 40 seconds, and the minimum hang time is about
75 * 20.6 seconds.
76 */
77
78static void supermicro_old_pre_start(unsigned long acpibase)
79{
80 unsigned long val32;
81
82 val32 = inl(SMI_EN);
83 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
84 outl(val32, SMI_EN); /* Needed to activate watchdog */
85}
86
87static void supermicro_old_pre_stop(unsigned long acpibase)
88{
89 unsigned long val32;
90
91 val32 = inl(SMI_EN);
92 val32 &= 0x00002000; /* Turn on SMI clearing watchdog */
93 outl(val32, SMI_EN); /* Needed to deactivate watchdog */
94}
95
96static void supermicro_old_pre_keepalive(unsigned long acpibase)
97{
98 /* Reload TCO Timer (done in iTCO_wdt_keepalive) + */
99 /* Clear "Expire Flag" (Bit 3 of TC01_STS register) */
100 outb(0x08, TCO1_STS);
101}
102
103/*
104 * Vendor Support: 2
105 * Board: Super Micro Computer Inc. P4SBx, P4DPx
106 * iTCO chipset: ICH4
107 *
108 * Code contributed by: R. Seretny <lkpatches@paypc.com>
109 * Documentation obtained by R. Seretny from SuperMicro Technical Support
110 *
111 * To enable Watchdog function:
112 * 1. BIOS
113 * For P4SBx:
114 * BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
115 * For P4DPx:
116 * BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
117 * This setting enables or disables Watchdog function. When enabled, the
118 * default watchdog timer is set to be 5 minutes (about 4’35â€). It is
119 * enough to load and run the OS. The application (service or driver) has
120 * to take over the control once OS is running up and before watchdog
121 * expires.
122 *
123 * 2. JUMPER
124 * For P4SBx: JP39
125 * For P4DPx: JP37
126 * This jumper is used for safety. Closed is enabled. This jumper
127 * prevents user enables watchdog in BIOS by accident.
128 *
129 * To enable Watch Dog function, both BIOS and JUMPER must be enabled.
130 *
131 * The documentation lists motherboards P4SBx and P4DPx series as of
132 * 20-March-2002. However, this code works flawlessly with much newer
133 * motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
134 *
135 * The original iTCO driver as written does not actually reset the
136 * watchdog timer on these machines, as a result they reboot after five
137 * minutes.
138 *
139 * NOTE: You may leave the Watchdog function disabled in the SuperMicro
140 * BIOS to avoid a "boot-race"... This driver will enable watchdog
141 * functionality even if it's disabled in the BIOS once the /dev/watchdog
142 * file is opened.
143 */
144
145/* I/O Port's */
146#define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */
147#define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */
148
149/* Control Register's */
150#define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */
151#define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */
152
153#define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */
154
155#define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */
156
157#define SM_ENDWATCH 0xAA /* Watchdog lock control page */
158
159#define SM_COUNTMODE 0xf5 /* Watchdog count mode select */
160 /* (Bit 3: 0 = seconds, 1 = minutes */
161
162#define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */
163
164#define SM_RESETCONTROL 0xf7 /* Watchdog reset control */
165 /* Bit 6: timer is reset by kbd interrupt */
166 /* Bit 7: timer is reset by mouse interrupt */
167
168static void supermicro_new_unlock_watchdog(void)
169{
170 outb(SM_WATCHPAGE, SM_REGINDEX); /* Write 0x87 to port 0x2e twice */
171 outb(SM_WATCHPAGE, SM_REGINDEX);
172
173 outb(SM_CTLPAGESW, SM_REGINDEX); /* Switch to watchdog control page */
174 outb(SM_CTLPAGE, SM_DATAIO);
175}
176
177static void supermicro_new_lock_watchdog(void)
178{
179 outb(SM_ENDWATCH, SM_REGINDEX);
180}
181
182static void supermicro_new_pre_start(unsigned int heartbeat)
183{
184 unsigned int val;
185
186 supermicro_new_unlock_watchdog();
187
188 /* Watchdog timer setting needs to be in seconds*/
189 outb(SM_COUNTMODE, SM_REGINDEX);
190 val = inb(SM_DATAIO);
191 val &= 0xF7;
192 outb(val, SM_DATAIO);
193
194 /* Write heartbeat interval to WDOG */
195 outb (SM_WATCHTIMER, SM_REGINDEX);
196 outb((heartbeat & 255), SM_DATAIO);
197
198 /* Make sure keyboard/mouse interrupts don't interfere */
199 outb(SM_RESETCONTROL, SM_REGINDEX);
200 val = inb(SM_DATAIO);
201 val &= 0x3f;
202 outb(val, SM_DATAIO);
203
204 /* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
205 outb(SM_WATCHENABLE, SM_REGINDEX);
206 val = inb(SM_DATAIO);
207 val |= 0x01;
208 outb(val, SM_DATAIO);
209
210 supermicro_new_lock_watchdog();
211}
212
213static void supermicro_new_pre_stop(void)
214{
215 unsigned int val;
216
217 supermicro_new_unlock_watchdog();
218
219 /* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
220 outb(SM_WATCHENABLE, SM_REGINDEX);
221 val = inb(SM_DATAIO);
222 val &= 0xFE;
223 outb(val, SM_DATAIO);
224
225 supermicro_new_lock_watchdog();
226}
227
228static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
229{
230 supermicro_new_unlock_watchdog();
231
232 /* reset watchdog timeout to heartveat value */
233 outb(SM_WATCHTIMER, SM_REGINDEX);
234 outb((heartbeat & 255), SM_DATAIO);
235
236 supermicro_new_lock_watchdog();
237}
238
239/*
240 * Generic Support Functions
241 */
242
243void iTCO_vendor_pre_start(unsigned long acpibase,
244 unsigned int heartbeat)
245{
246 if (vendorsupport == SUPERMICRO_OLD_BOARD)
247 supermicro_old_pre_start(acpibase);
248 else if (vendorsupport == SUPERMICRO_NEW_BOARD)
249 supermicro_new_pre_start(heartbeat);
250}
251EXPORT_SYMBOL(iTCO_vendor_pre_start);
252
253void iTCO_vendor_pre_stop(unsigned long acpibase)
254{
255 if (vendorsupport == SUPERMICRO_OLD_BOARD)
256 supermicro_old_pre_stop(acpibase);
257 else if (vendorsupport == SUPERMICRO_NEW_BOARD)
258 supermicro_new_pre_stop();
259}
260EXPORT_SYMBOL(iTCO_vendor_pre_stop);
261
262void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
263{
264 if (vendorsupport == SUPERMICRO_OLD_BOARD)
265 supermicro_old_pre_keepalive(acpibase);
266 else if (vendorsupport == SUPERMICRO_NEW_BOARD)
267 supermicro_new_pre_set_heartbeat(heartbeat);
268}
269EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);
270
271void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
272{
273 if (vendorsupport == SUPERMICRO_NEW_BOARD)
274 supermicro_new_pre_set_heartbeat(heartbeat);
275}
276EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);
277
278int iTCO_vendor_check_noreboot_on(void)
279{
280 switch(vendorsupport) {
281 case SUPERMICRO_OLD_BOARD:
282 return 0;
283 default:
284 return 1;
285 }
286}
287EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);
288
289static int __init iTCO_vendor_init_module(void)
290{
291 printk (KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
292 return 0;
293}
294
295static void __exit iTCO_vendor_exit_module(void)
296{
297 printk (KERN_INFO PFX "Module Unloaded\n");
298}
299
300module_init(iTCO_vendor_init_module);
301module_exit(iTCO_vendor_exit_module);
302
303MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, R. Seretny <lkpatches@paypc.com>");
304MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
305MODULE_VERSION(DRV_VERSION);
306MODULE_LICENSE("GPL");
307
diff --git a/drivers/char/watchdog/iTCO_wdt.c b/drivers/char/watchdog/iTCO_wdt.c
index b6f29cb8bd39..7eac922df867 100644
--- a/drivers/char/watchdog/iTCO_wdt.c
+++ b/drivers/char/watchdog/iTCO_wdt.c
@@ -48,8 +48,8 @@
48 48
49/* Module and version information */ 49/* Module and version information */
50#define DRV_NAME "iTCO_wdt" 50#define DRV_NAME "iTCO_wdt"
51#define DRV_VERSION "1.00" 51#define DRV_VERSION "1.01"
52#define DRV_RELDATE "08-Oct-2006" 52#define DRV_RELDATE "11-Nov-2006"
53#define PFX DRV_NAME ": " 53#define PFX DRV_NAME ": "
54 54
55/* Includes */ 55/* Includes */
@@ -189,6 +189,21 @@ static int nowayout = WATCHDOG_NOWAYOUT;
189module_param(nowayout, int, 0); 189module_param(nowayout, int, 0);
190MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)"); 190MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
191 191
192/* iTCO Vendor Specific Support hooks */
193#ifdef CONFIG_ITCO_VENDOR_SUPPORT
194extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
195extern void iTCO_vendor_pre_stop(unsigned long);
196extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
197extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
198extern int iTCO_vendor_check_noreboot_on(void);
199#else
200#define iTCO_vendor_pre_start(acpibase, heartbeat) {}
201#define iTCO_vendor_pre_stop(acpibase) {}
202#define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
203#define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
204#define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
205#endif
206
192/* 207/*
193 * Some TCO specific functions 208 * Some TCO specific functions
194 */ 209 */
@@ -249,6 +264,8 @@ static int iTCO_wdt_start(void)
249 264
250 spin_lock(&iTCO_wdt_private.io_lock); 265 spin_lock(&iTCO_wdt_private.io_lock);
251 266
267 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
268
252 /* disable chipset's NO_REBOOT bit */ 269 /* disable chipset's NO_REBOOT bit */
253 if (iTCO_wdt_unset_NO_REBOOT_bit()) { 270 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
254 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n"); 271 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
@@ -273,6 +290,8 @@ static int iTCO_wdt_stop(void)
273 290
274 spin_lock(&iTCO_wdt_private.io_lock); 291 spin_lock(&iTCO_wdt_private.io_lock);
275 292
293 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
294
276 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ 295 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
277 val = inw(TCO1_CNT); 296 val = inw(TCO1_CNT);
278 val |= 0x0800; 297 val |= 0x0800;
@@ -293,6 +312,8 @@ static int iTCO_wdt_keepalive(void)
293{ 312{
294 spin_lock(&iTCO_wdt_private.io_lock); 313 spin_lock(&iTCO_wdt_private.io_lock);
295 314
315 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
316
296 /* Reload the timer by writing to the TCO Timer Counter register */ 317 /* Reload the timer by writing to the TCO Timer Counter register */
297 if (iTCO_wdt_private.iTCO_version == 2) { 318 if (iTCO_wdt_private.iTCO_version == 2) {
298 outw(0x01, TCO_RLD); 319 outw(0x01, TCO_RLD);
@@ -319,6 +340,8 @@ static int iTCO_wdt_set_heartbeat(int t)
319 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) 340 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
320 return -EINVAL; 341 return -EINVAL;
321 342
343 iTCO_vendor_pre_set_heartbeat(tmrval);
344
322 /* Write new heartbeat to watchdog */ 345 /* Write new heartbeat to watchdog */
323 if (iTCO_wdt_private.iTCO_version == 2) { 346 if (iTCO_wdt_private.iTCO_version == 2) {
324 spin_lock(&iTCO_wdt_private.io_lock); 347 spin_lock(&iTCO_wdt_private.io_lock);
@@ -569,7 +592,7 @@ static int iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent,
569 } 592 }
570 593
571 /* Check chipset's NO_REBOOT bit */ 594 /* Check chipset's NO_REBOOT bit */
572 if (iTCO_wdt_unset_NO_REBOOT_bit()) { 595 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
573 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n"); 596 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
574 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ 597 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
575 goto out; 598 goto out;
diff --git a/drivers/char/watchdog/pc87413_wdt.c b/drivers/char/watchdog/pc87413_wdt.c
new file mode 100644
index 000000000000..1d447e32af41
--- /dev/null
+++ b/drivers/char/watchdog/pc87413_wdt.c
@@ -0,0 +1,635 @@
1/*
2 * NS pc87413-wdt Watchdog Timer driver for Linux 2.6.x.x
3 *
4 * This code is based on wdt.c with original copyright.
5 *
6 * (C) Copyright 2006 Sven Anders, <anders@anduras.de>
7 * and Marcus Junker, <junker@anduras.de>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Neither Sven Anders, Marcus Junker nor ANDURAS AG
15 * admit liability nor provide warranty for any of this software.
16 * This material is provided "AS-IS" and at no charge.
17 *
18 * Release 1.1
19 */
20
21#include <linux/module.h>
22#include <linux/types.h>
23#include <linux/miscdevice.h>
24#include <linux/watchdog.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/notifier.h>
28#include <linux/fs.h>
29#include <linux/reboot.h>
30#include <linux/init.h>
31#include <linux/spinlock.h>
32#include <linux/moduleparam.h>
33#include <linux/version.h>
34
35#include <asm/io.h>
36#include <asm/uaccess.h>
37#include <asm/system.h>
38
39/* #define DEBUG 1 */
40
41#define DEFAULT_TIMEOUT 1 /* 1 minute */
42#define MAX_TIMEOUT 255
43
44#define VERSION "1.1"
45#define MODNAME "pc87413 WDT"
46#define PFX MODNAME ": "
47#define DPFX MODNAME " - DEBUG: "
48
49#define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */
50#define WDT_DATA_IO_PORT (WDT_INDEX_IO_PORT+1)
51#define SWC_LDN 0x04
52#define SIOCFG2 0x22 /* Serial IO register */
53#define WDCTL 0x10 /* Watchdog-Timer-Controll-Register */
54#define WDTO 0x11 /* Watchdog timeout register */
55#define WDCFG 0x12 /* Watchdog config register */
56
57static int io = 0x2E; /* Address used on Portwell Boards */
58
59static int timeout = DEFAULT_TIMEOUT; /* timeout value */
60static unsigned long timer_enabled = 0; /* is the timer enabled? */
61
62static char expect_close; /* is the close expected? */
63
64static spinlock_t io_lock; /* to guard the watchdog from io races */
65
66static int nowayout = WATCHDOG_NOWAYOUT;
67
68/* -- Low level function ----------------------------------------*/
69
70/* Select pins for Watchdog output */
71
72static inline void pc87413_select_wdt_out (void)
73{
74 unsigned int cr_data = 0;
75
76 /* Step 1: Select multiple pin,pin55,as WDT output */
77
78 outb_p(SIOCFG2, WDT_INDEX_IO_PORT);
79
80 cr_data = inb (WDT_DATA_IO_PORT);
81
82 cr_data |= 0x80; /* Set Bit7 to 1*/
83 outb_p(SIOCFG2, WDT_INDEX_IO_PORT);
84
85 outb_p(cr_data, WDT_DATA_IO_PORT);
86
87#ifdef DEBUG
88 printk(KERN_INFO DPFX "Select multiple pin,pin55,as WDT output:"
89 " Bit7 to 1: %d\n", cr_data);
90#endif
91}
92
93/* Enable SWC functions */
94
95static inline void pc87413_enable_swc(void)
96{
97 unsigned int cr_data=0;
98
99 /* Step 2: Enable SWC functions */
100
101 outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */
102 outb_p(SWC_LDN, WDT_DATA_IO_PORT);
103
104 outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */
105 cr_data = inb(WDT_DATA_IO_PORT);
106 cr_data |= 0x01; /* Set Bit0 to 1 */
107 outb_p(0x30, WDT_INDEX_IO_PORT);
108 outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */
109
110#ifdef DEBUG
111 printk(KERN_INFO DPFX "pc87413 - Enable SWC functions\n");
112#endif
113}
114
115/* Read SWC I/O base address */
116
117static inline unsigned int pc87413_get_swc_base(void)
118{
119 unsigned int swc_base_addr = 0;
120 unsigned char addr_l, addr_h = 0;
121
122 /* Step 3: Read SWC I/O Base Address */
123
124 outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */
125 addr_h = inb(WDT_DATA_IO_PORT);
126
127 outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */
128
129 addr_l = inb(WDT_DATA_IO_PORT);
130
131 swc_base_addr = (addr_h << 8) + addr_l;
132
133#ifdef DEBUG
134 printk(KERN_INFO DPFX "Read SWC I/O Base Address: low %d, high %d,"
135 " res %d\n", addr_l, addr_h, swc_base_addr);
136#endif
137
138 return swc_base_addr;
139}
140
141/* Select Bank 3 of SWC */
142
143static inline void pc87413_swc_bank3(unsigned int swc_base_addr)
144{
145 /* Step 4: Select Bank3 of SWC */
146
147 outb_p(inb(swc_base_addr + 0x0f) | 0x03, swc_base_addr + 0x0f);
148
149#ifdef DEBUG
150 printk(KERN_INFO DPFX "Select Bank3 of SWC\n");
151#endif
152}
153
154/* Set watchdog timeout to x minutes */
155
156static inline void pc87413_programm_wdto(unsigned int swc_base_addr,
157 char pc87413_time)
158{
159 /* Step 5: Programm WDTO, Twd. */
160
161 outb_p(pc87413_time, swc_base_addr + WDTO);
162
163#ifdef DEBUG
164 printk(KERN_INFO DPFX "Set WDTO to %d minutes\n", pc87413_time);
165#endif
166}
167
168/* Enable WDEN */
169
170static inline void pc87413_enable_wden(unsigned int swc_base_addr)
171{
172 /* Step 6: Enable WDEN */
173
174 outb_p(inb (swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL);
175
176#ifdef DEBUG
177 printk(KERN_INFO DPFX "Enable WDEN\n");
178#endif
179}
180
181/* Enable SW_WD_TREN */
182static inline void pc87413_enable_sw_wd_tren(unsigned int swc_base_addr)
183{
184 /* Enable SW_WD_TREN */
185
186 outb_p(inb (swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG);
187
188#ifdef DEBUG
189 printk(KERN_INFO DPFX "Enable SW_WD_TREN\n");
190#endif
191}
192
193/* Disable SW_WD_TREN */
194
195static inline void pc87413_disable_sw_wd_tren(unsigned int swc_base_addr)
196{
197 /* Disable SW_WD_TREN */
198
199 outb_p(inb (swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG);
200
201#ifdef DEBUG
202 printk(KERN_INFO DPFX "pc87413 - Disable SW_WD_TREN\n");
203#endif
204}
205
206/* Enable SW_WD_TRG */
207
208static inline void pc87413_enable_sw_wd_trg(unsigned int swc_base_addr)
209{
210 /* Enable SW_WD_TRG */
211
212 outb_p(inb (swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL);
213
214#ifdef DEBUG
215 printk(KERN_INFO DPFX "pc87413 - Enable SW_WD_TRG\n");
216#endif
217}
218
219/* Disable SW_WD_TRG */
220
221static inline void pc87413_disable_sw_wd_trg(unsigned int swc_base_addr)
222{
223 /* Disable SW_WD_TRG */
224
225 outb_p(inb (swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL);
226
227#ifdef DEBUG
228 printk(KERN_INFO DPFX "Disable SW_WD_TRG\n");
229#endif
230}
231
232/* -- Higher level functions ------------------------------------*/
233
234/* Enable the watchdog */
235
236static void pc87413_enable(void)
237{
238 unsigned int swc_base_addr;
239
240 spin_lock(&io_lock);
241
242 pc87413_select_wdt_out();
243 pc87413_enable_swc();
244 swc_base_addr = pc87413_get_swc_base();
245 pc87413_swc_bank3(swc_base_addr);
246 pc87413_programm_wdto(swc_base_addr, timeout);
247 pc87413_enable_wden(swc_base_addr);
248 pc87413_enable_sw_wd_tren(swc_base_addr);
249 pc87413_enable_sw_wd_trg(swc_base_addr);
250
251 spin_unlock(&io_lock);
252}
253
254/* Disable the watchdog */
255
256static void pc87413_disable(void)
257{
258 unsigned int swc_base_addr;
259
260 spin_lock(&io_lock);
261
262 pc87413_select_wdt_out();
263 pc87413_enable_swc();
264 swc_base_addr = pc87413_get_swc_base();
265 pc87413_swc_bank3(swc_base_addr);
266 pc87413_disable_sw_wd_tren(swc_base_addr);
267 pc87413_disable_sw_wd_trg(swc_base_addr);
268 pc87413_programm_wdto(swc_base_addr, 0);
269
270 spin_unlock(&io_lock);
271}
272
273/* Refresh the watchdog */
274
275static void pc87413_refresh(void)
276{
277 unsigned int swc_base_addr;
278
279 spin_lock(&io_lock);
280
281 pc87413_select_wdt_out();
282 pc87413_enable_swc();
283 swc_base_addr = pc87413_get_swc_base();
284 pc87413_swc_bank3(swc_base_addr);
285 pc87413_disable_sw_wd_tren(swc_base_addr);
286 pc87413_disable_sw_wd_trg(swc_base_addr);
287 pc87413_programm_wdto(swc_base_addr, timeout);
288 pc87413_enable_wden(swc_base_addr);
289 pc87413_enable_sw_wd_tren(swc_base_addr);
290 pc87413_enable_sw_wd_trg(swc_base_addr);
291
292 spin_unlock(&io_lock);
293}
294
295/* -- File operations -------------------------------------------*/
296
297/**
298 * pc87413_open:
299 * @inode: inode of device
300 * @file: file handle to device
301 *
302 */
303
304static int pc87413_open(struct inode *inode, struct file *file)
305{
306 /* /dev/watchdog can only be opened once */
307
308 if (test_and_set_bit(0, &timer_enabled))
309 return -EBUSY;
310
311 if (nowayout)
312 __module_get(THIS_MODULE);
313
314 /* Reload and activate timer */
315 pc87413_refresh();
316
317 printk(KERN_INFO MODNAME "Watchdog enabled. Timeout set to"
318 " %d minute(s).\n", timeout);
319
320 return nonseekable_open(inode, file);
321}
322
323/**
324 * pc87413_release:
325 * @inode: inode to board
326 * @file: file handle to board
327 *
328 * The watchdog has a configurable API. There is a religious dispute
329 * between people who want their watchdog to be able to shut down and
330 * those who want to be sure if the watchdog manager dies the machine
331 * reboots. In the former case we disable the counters, in the latter
332 * case you have to open it again very soon.
333 */
334
335static int pc87413_release(struct inode *inode, struct file *file)
336{
337 /* Shut off the timer. */
338
339 if (expect_close == 42) {
340 pc87413_disable();
341 printk(KERN_INFO MODNAME "Watchdog disabled,"
342 " sleeping again...\n");
343 } else {
344 printk(KERN_CRIT MODNAME "Unexpected close, not stopping"
345 " watchdog!\n");
346 pc87413_refresh();
347 }
348
349 clear_bit(0, &timer_enabled);
350 expect_close = 0;
351
352 return 0;
353}
354
355/**
356 * pc87413_status:
357 *
358 * return, if the watchdog is enabled (timeout is set...)
359 */
360
361
362static int pc87413_status(void)
363{
364 return 0; /* currently not supported */
365}
366
367/**
368 * pc87413_write:
369 * @file: file handle to the watchdog
370 * @data: data buffer to write
371 * @len: length in bytes
372 * @ppos: pointer to the position to write. No seeks allowed
373 *
374 * A write to a watchdog device is defined as a keepalive signal. Any
375 * write of data will do, as we we don't define content meaning.
376 */
377
378static ssize_t pc87413_write(struct file *file, const char __user *data,
379 size_t len, loff_t *ppos)
380{
381 /* See if we got the magic character 'V' and reload the timer */
382 if (len) {
383 if (!nowayout) {
384 size_t i;
385
386 /* reset expect flag */
387 expect_close = 0;
388
389 /* scan to see whether or not we got the magic character */
390 for (i = 0; i != len; i++) {
391 char c;
392 if (get_user(c, data+i))
393 return -EFAULT;
394 if (c == 'V')
395 expect_close = 42;
396 }
397 }
398
399 /* someone wrote to us, we should reload the timer */
400 pc87413_refresh();
401 }
402 return len;
403}
404
405/**
406 * pc87413_ioctl:
407 * @inode: inode of the device
408 * @file: file handle to the device
409 * @cmd: watchdog command
410 * @arg: argument pointer
411 *
412 * The watchdog API defines a common set of functions for all watchdogs
413 * according to their available features. We only actually usefully support
414 * querying capabilities and current status.
415 */
416
417static int pc87413_ioctl(struct inode *inode, struct file *file,
418 unsigned int cmd, unsigned long arg)
419{
420 int new_timeout;
421
422 union {
423 struct watchdog_info __user *ident;
424 int __user *i;
425 } uarg;
426
427 static struct watchdog_info ident = {
428 .options = WDIOF_KEEPALIVEPING |
429 WDIOF_SETTIMEOUT |
430 WDIOF_MAGICCLOSE,
431 .firmware_version = 1,
432 .identity = "PC87413(HF/F) watchdog"
433 };
434
435 uarg.i = (int __user *)arg;
436
437 switch(cmd) {
438 default:
439 return -ENOTTY;
440
441 case WDIOC_GETSUPPORT:
442 return copy_to_user(uarg.ident, &ident,
443 sizeof(ident)) ? -EFAULT : 0;
444
445 case WDIOC_GETSTATUS:
446 return put_user(pc87413_status(), uarg.i);
447
448 case WDIOC_GETBOOTSTATUS:
449 return put_user(0, uarg.i);
450
451 case WDIOC_KEEPALIVE:
452 pc87413_refresh();
453#ifdef DEBUG
454 printk(KERN_INFO DPFX "keepalive\n");
455#endif
456 return 0;
457
458 case WDIOC_SETTIMEOUT:
459 if (get_user(new_timeout, uarg.i))
460 return -EFAULT;
461
462 // the API states this is given in secs
463 new_timeout /= 60;
464
465 if (new_timeout < 0 || new_timeout > MAX_TIMEOUT)
466 return -EINVAL;
467
468 timeout = new_timeout;
469 pc87413_refresh();
470
471 // fall through and return the new timeout...
472
473 case WDIOC_GETTIMEOUT:
474
475 new_timeout = timeout * 60;
476
477 return put_user(new_timeout, uarg.i);
478
479 case WDIOC_SETOPTIONS:
480 {
481 int options, retval = -EINVAL;
482
483 if (get_user(options, uarg.i))
484 return -EFAULT;
485
486 if (options & WDIOS_DISABLECARD) {
487 pc87413_disable();
488 retval = 0;
489 }
490
491 if (options & WDIOS_ENABLECARD) {
492 pc87413_enable();
493 retval = 0;
494 }
495
496 return retval;
497 }
498 }
499}
500
501/* -- Notifier funtions -----------------------------------------*/
502
503/**
504 * notify_sys:
505 * @this: our notifier block
506 * @code: the event being reported
507 * @unused: unused
508 *
509 * Our notifier is called on system shutdowns. We want to turn the card
510 * off at reboot otherwise the machine will reboot again during memory
511 * test or worse yet during the following fsck. This would suck, in fact
512 * trust me - if it happens it does suck.
513 */
514
515static int pc87413_notify_sys(struct notifier_block *this,
516 unsigned long code,
517 void *unused)
518{
519 if (code == SYS_DOWN || code == SYS_HALT)
520 {
521 /* Turn the card off */
522 pc87413_disable();
523 }
524 return NOTIFY_DONE;
525}
526
527/* -- Module's structures ---------------------------------------*/
528
529static struct file_operations pc87413_fops = {
530 .owner = THIS_MODULE,
531 .llseek = no_llseek,
532 .write = pc87413_write,
533 .ioctl = pc87413_ioctl,
534 .open = pc87413_open,
535 .release = pc87413_release,
536};
537
538static struct notifier_block pc87413_notifier =
539{
540 .notifier_call = pc87413_notify_sys,
541};
542
543static struct miscdevice pc87413_miscdev=
544{
545 .minor = WATCHDOG_MINOR,
546 .name = "watchdog",
547 .fops = &pc87413_fops
548};
549
550/* -- Module init functions -------------------------------------*/
551
552/**
553 * pc87413_init: module's "constructor"
554 *
555 * Set up the WDT watchdog board. All we have to do is grab the
556 * resources we require and bitch if anyone beat us to them.
557 * The open() function will actually kick the board off.
558 */
559
560static int __init pc87413_init(void)
561{
562 int ret;
563
564 spin_lock_init(&io_lock);
565
566 printk(KERN_INFO PFX "Version " VERSION " at io 0x%X\n", WDT_INDEX_IO_PORT);
567
568 /* request_region(io, 2, "pc87413"); */
569
570 ret = register_reboot_notifier(&pc87413_notifier);
571 if (ret != 0) {
572 printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n",
573 ret);
574 }
575
576 ret = misc_register(&pc87413_miscdev);
577
578 if (ret != 0) {
579 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
580 WATCHDOG_MINOR, ret);
581 unregister_reboot_notifier(&pc87413_notifier);
582 return ret;
583 }
584
585 printk(KERN_INFO PFX "initialized. timeout=%d min \n", timeout);
586
587 pc87413_enable();
588
589 return 0;
590}
591
592/**
593 * pc87413_exit: module's "destructor"
594 *
595 * Unload the watchdog. You cannot do this with any file handles open.
596 * If your watchdog is set to continue ticking on close and you unload
597 * it, well it keeps ticking. We won't get the interrupt but the board
598 * will not touch PC memory so all is fine. You just have to load a new
599 * module in 60 seconds or reboot.
600 */
601
602static void __exit pc87413_exit(void)
603{
604 /* Stop the timer before we leave */
605 if (!nowayout)
606 {
607 pc87413_disable();
608 printk(KERN_INFO MODNAME "Watchdog disabled.\n");
609 }
610
611 misc_deregister(&pc87413_miscdev);
612 unregister_reboot_notifier(&pc87413_notifier);
613 /* release_region(io,2); */
614
615 printk(MODNAME " watchdog component driver removed.\n");
616}
617
618module_init(pc87413_init);
619module_exit(pc87413_exit);
620
621MODULE_AUTHOR("Sven Anders <anders@anduras.de>, Marcus Junker <junker@anduras.de>,");
622MODULE_DESCRIPTION("PC87413 WDT driver");
623MODULE_LICENSE("GPL");
624
625MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
626
627module_param(io, int, 0);
628MODULE_PARM_DESC(io, MODNAME " I/O port (default: " __MODULE_STRING(io) ").");
629
630module_param(timeout, int, 0);
631MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes (default=" __MODULE_STRING(timeout) ").");
632
633module_param(nowayout, int, 0);
634MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
635
diff --git a/drivers/char/watchdog/pcwd_usb.c b/drivers/char/watchdog/pcwd_usb.c
index bda45334d802..e275dd4a705d 100644
--- a/drivers/char/watchdog/pcwd_usb.c
+++ b/drivers/char/watchdog/pcwd_usb.c
@@ -561,8 +561,7 @@ static struct notifier_block usb_pcwd_notifier = {
561 */ 561 */
562static inline void usb_pcwd_delete (struct usb_pcwd_private *usb_pcwd) 562static inline void usb_pcwd_delete (struct usb_pcwd_private *usb_pcwd)
563{ 563{
564 if (usb_pcwd->intr_urb != NULL) 564 usb_free_urb(usb_pcwd->intr_urb);
565 usb_free_urb (usb_pcwd->intr_urb);
566 if (usb_pcwd->intr_buffer != NULL) 565 if (usb_pcwd->intr_buffer != NULL)
567 usb_buffer_free(usb_pcwd->udev, usb_pcwd->intr_size, 566 usb_buffer_free(usb_pcwd->udev, usb_pcwd->intr_size,
568 usb_pcwd->intr_buffer, usb_pcwd->intr_dma); 567 usb_pcwd->intr_buffer, usb_pcwd->intr_dma);
diff --git a/drivers/char/watchdog/rm9k_wdt.c b/drivers/char/watchdog/rm9k_wdt.c
new file mode 100644
index 000000000000..ec3909371c21
--- /dev/null
+++ b/drivers/char/watchdog/rm9k_wdt.c
@@ -0,0 +1,420 @@
1/*
2 * Watchdog implementation for GPI h/w found on PMC-Sierra RM9xxx
3 * chips.
4 *
5 * Copyright (C) 2004 by Basler Vision Technologies AG
6 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/platform_device.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/interrupt.h>
27#include <linux/fs.h>
28#include <linux/reboot.h>
29#include <linux/notifier.h>
30#include <linux/miscdevice.h>
31#include <linux/watchdog.h>
32#include <asm/io.h>
33#include <asm/atomic.h>
34#include <asm/processor.h>
35#include <asm/uaccess.h>
36#include <asm/system.h>
37#include <asm/rm9k-ocd.h>
38
39#include <rm9k_wdt.h>
40
41
42#define CLOCK 125000000
43#define MAX_TIMEOUT_SECONDS 32
44#define CPCCR 0x0080
45#define CPGIG1SR 0x0044
46#define CPGIG1ER 0x0054
47
48
49/* Function prototypes */
50static irqreturn_t wdt_gpi_irqhdl(int, void *, struct pt_regs *);
51static void wdt_gpi_start(void);
52static void wdt_gpi_stop(void);
53static void wdt_gpi_set_timeout(unsigned int);
54static int wdt_gpi_open(struct inode *, struct file *);
55static int wdt_gpi_release(struct inode *, struct file *);
56static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t, loff_t *);
57static long wdt_gpi_ioctl(struct file *, unsigned int, unsigned long);
58static int wdt_gpi_notify(struct notifier_block *, unsigned long, void *);
59static const struct resource *wdt_gpi_get_resource(struct platform_device *, const char *, unsigned int);
60static int __init wdt_gpi_probe(struct device *);
61static int __exit wdt_gpi_remove(struct device *);
62
63
64static const char wdt_gpi_name[] = "wdt_gpi";
65static atomic_t opencnt;
66static int expect_close;
67static int locked;
68
69
70/* These are set from device resources */
71static void __iomem * wd_regs;
72static unsigned int wd_irq, wd_ctr;
73
74
75/* Module arguments */
76static int timeout = MAX_TIMEOUT_SECONDS;
77module_param(timeout, int, 0444);
78MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
79
80static unsigned long resetaddr = 0xbffdc200;
81module_param(resetaddr, ulong, 0444);
82MODULE_PARM_DESC(resetaddr, "Address to write to to force a reset");
83
84static unsigned long flagaddr = 0xbffdc104;
85module_param(flagaddr, ulong, 0444);
86MODULE_PARM_DESC(flagaddr, "Address to write to boot flags to");
87
88static int powercycle;
89module_param(powercycle, bool, 0444);
90MODULE_PARM_DESC(powercycle, "Cycle power if watchdog expires");
91
92static int nowayout = WATCHDOG_NOWAYOUT;
93module_param(nowayout, bool, 0444);
94MODULE_PARM_DESC(nowayout, "Watchdog cannot be disabled once started");
95
96
97/* Interrupt handler */
98static irqreturn_t wdt_gpi_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
99{
100 if (!unlikely(__raw_readl(wd_regs + 0x0008) & 0x1))
101 return IRQ_NONE;
102 __raw_writel(0x1, wd_regs + 0x0008);
103
104
105 printk(KERN_CRIT "%s: watchdog expired - resetting system\n",
106 wdt_gpi_name);
107
108 *(volatile char *) flagaddr |= 0x01;
109 *(volatile char *) resetaddr = powercycle ? 0x01 : 0x2;
110 iob();
111 while (1)
112 cpu_relax();
113}
114
115
116/* Watchdog functions */
117static void wdt_gpi_start(void)
118{
119 u32 reg;
120
121 lock_titan_regs();
122 reg = titan_readl(CPGIG1ER);
123 titan_writel(reg | (0x100 << wd_ctr), CPGIG1ER);
124 iob();
125 unlock_titan_regs();
126}
127
128static void wdt_gpi_stop(void)
129{
130 u32 reg;
131
132 lock_titan_regs();
133 reg = titan_readl(CPCCR) & ~(0xf << (wd_ctr * 4));
134 titan_writel(reg, CPCCR);
135 reg = titan_readl(CPGIG1ER);
136 titan_writel(reg & ~(0x100 << wd_ctr), CPGIG1ER);
137 iob();
138 unlock_titan_regs();
139}
140
141static void wdt_gpi_set_timeout(unsigned int to)
142{
143 u32 reg;
144 const u32 wdval = (to * CLOCK) & ~0x0000000f;
145
146 lock_titan_regs();
147 reg = titan_readl(CPCCR) & ~(0xf << (wd_ctr * 4));
148 titan_writel(reg, CPCCR);
149 wmb();
150 __raw_writel(wdval, wd_regs + 0x0000);
151 wmb();
152 titan_writel(reg | (0x2 << (wd_ctr * 4)), CPCCR);
153 wmb();
154 titan_writel(reg | (0x5 << (wd_ctr * 4)), CPCCR);
155 iob();
156 unlock_titan_regs();
157}
158
159
160/* /dev/watchdog operations */
161static int wdt_gpi_open(struct inode *inode, struct file *file)
162{
163 int res;
164
165 if (unlikely(atomic_dec_if_positive(&opencnt) < 0))
166 return -EBUSY;
167
168 expect_close = 0;
169 if (locked) {
170 module_put(THIS_MODULE);
171 free_irq(wd_irq, &miscdev);
172 locked = 0;
173 }
174
175 res = request_irq(wd_irq, wdt_gpi_irqhdl, SA_SHIRQ | SA_INTERRUPT,
176 wdt_gpi_name, &miscdev);
177 if (unlikely(res))
178 return res;
179
180 wdt_gpi_set_timeout(timeout);
181 wdt_gpi_start();
182
183 printk(KERN_INFO "%s: watchdog started, timeout = %u seconds\n",
184 wdt_gpi_name, timeout);
185 return nonseekable_open(inode, file);
186}
187
188static int wdt_gpi_release(struct inode *inode, struct file *file)
189{
190 if (nowayout) {
191 printk(KERN_INFO "%s: no way out - watchdog left running\n",
192 wdt_gpi_name);
193 __module_get(THIS_MODULE);
194 locked = 1;
195 } else {
196 if (expect_close) {
197 wdt_gpi_stop();
198 free_irq(wd_irq, &miscdev);
199 printk(KERN_INFO "%s: watchdog stopped\n", wdt_gpi_name);
200 } else {
201 printk(KERN_CRIT "%s: unexpected close() -"
202 " watchdog left running\n",
203 wdt_gpi_name);
204 wdt_gpi_set_timeout(timeout);
205 __module_get(THIS_MODULE);
206 locked = 1;
207 }
208 }
209
210 atomic_inc(&opencnt);
211 return 0;
212}
213
214static ssize_t
215wdt_gpi_write(struct file *f, const char __user *d, size_t s, loff_t *o)
216{
217 char val;
218
219 wdt_gpi_set_timeout(timeout);
220 expect_close = (s > 0) && !get_user(val, d) && (val == 'V');
221 return s ? 1 : 0;
222}
223
224static long
225wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
226{
227 long res = -ENOTTY;
228 const long size = _IOC_SIZE(cmd);
229 int stat;
230 void __user *argp = (void __user *)arg;
231 static struct watchdog_info wdinfo = {
232 .identity = "RM9xxx/GPI watchdog",
233 .firmware_version = 0,
234 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING
235 };
236
237 if (unlikely(_IOC_TYPE(cmd) != WATCHDOG_IOCTL_BASE))
238 return -ENOTTY;
239
240 if ((_IOC_DIR(cmd) & _IOC_READ)
241 && !access_ok(VERIFY_WRITE, arg, size))
242 return -EFAULT;
243
244 if ((_IOC_DIR(cmd) & _IOC_WRITE)
245 && !access_ok(VERIFY_READ, arg, size))
246 return -EFAULT;
247
248 expect_close = 0;
249
250 switch (cmd) {
251 case WDIOC_GETSUPPORT:
252 wdinfo.options = nowayout ?
253 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING :
254 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE;
255 res = __copy_to_user(argp, &wdinfo, size) ? -EFAULT : size;
256 break;
257
258 case WDIOC_GETSTATUS:
259 break;
260
261 case WDIOC_GETBOOTSTATUS:
262 stat = (*(volatile char *) flagaddr & 0x01)
263 ? WDIOF_CARDRESET : 0;
264 res = __copy_to_user(argp, &stat, size) ?
265 -EFAULT : size;
266 break;
267
268 case WDIOC_SETOPTIONS:
269 break;
270
271 case WDIOC_KEEPALIVE:
272 wdt_gpi_set_timeout(timeout);
273 res = size;
274 break;
275
276 case WDIOC_SETTIMEOUT:
277 {
278 int val;
279 if (unlikely(__copy_from_user(&val, argp, size))) {
280 res = -EFAULT;
281 break;
282 }
283
284 if (val > MAX_TIMEOUT_SECONDS)
285 val = MAX_TIMEOUT_SECONDS;
286 timeout = val;
287 wdt_gpi_set_timeout(val);
288 res = size;
289 printk(KERN_INFO "%s: timeout set to %u seconds\n",
290 wdt_gpi_name, timeout);
291 }
292 break;
293
294 case WDIOC_GETTIMEOUT:
295 res = __copy_to_user(argp, &timeout, size) ?
296 -EFAULT : size;
297 break;
298 }
299
300 return res;
301}
302
303
304/* Shutdown notifier */
305static int
306wdt_gpi_notify(struct notifier_block *this, unsigned long code, void *unused)
307{
308 if (code == SYS_DOWN || code == SYS_HALT)
309 wdt_gpi_stop();
310
311 return NOTIFY_DONE;
312}
313
314
315/* Kernel interfaces */
316static struct file_operations fops = {
317 .owner = THIS_MODULE,
318 .open = wdt_gpi_open,
319 .release = wdt_gpi_release,
320 .write = wdt_gpi_write,
321 .unlocked_ioctl = wdt_gpi_ioctl,
322};
323
324static struct miscdevice miscdev = {
325 .minor = WATCHDOG_MINOR,
326 .name = wdt_gpi_name,
327 .fops = &fops,
328};
329
330static struct notifier_block wdt_gpi_shutdown = {
331 .notifier_call = wdt_gpi_notify,
332};
333
334
335/* Init & exit procedures */
336static const struct resource *
337wdt_gpi_get_resource(struct platform_device *pdv, const char *name,
338 unsigned int type)
339{
340 char buf[80];
341 if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
342 return NULL;
343 return platform_get_resource_byname(pdv, type, buf);
344}
345
346/* No hotplugging on the platform bus - use __init */
347static int __init wdt_gpi_probe(struct device *dev)
348{
349 int res;
350 struct platform_device * const pdv = to_platform_device(dev);
351 const struct resource
352 * const rr = wdt_gpi_get_resource(pdv, WDT_RESOURCE_REGS,
353 IORESOURCE_MEM),
354 * const ri = wdt_gpi_get_resource(pdv, WDT_RESOURCE_IRQ,
355 IORESOURCE_IRQ),
356 * const rc = wdt_gpi_get_resource(pdv, WDT_RESOURCE_COUNTER,
357 0);
358
359 if (unlikely(!rr || !ri || !rc))
360 return -ENXIO;
361
362 wd_regs = ioremap_nocache(rr->start, rr->end + 1 - rr->start);
363 if (unlikely(!wd_regs))
364 return -ENOMEM;
365 wd_irq = ri->start;
366 wd_ctr = rc->start;
367 res = misc_register(&miscdev);
368 if (res)
369 iounmap(wd_regs);
370 else
371 register_reboot_notifier(&wdt_gpi_shutdown);
372 return res;
373}
374
375static int __exit wdt_gpi_remove(struct device *dev)
376{
377 int res;
378
379 unregister_reboot_notifier(&wdt_gpi_shutdown);
380 res = misc_deregister(&miscdev);
381 iounmap(wd_regs);
382 wd_regs = NULL;
383 return res;
384}
385
386
387/* Device driver init & exit */
388static struct device_driver wdt_gpi_driver = {
389 .name = (char *) wdt_gpi_name,
390 .bus = &platform_bus_type,
391 .owner = THIS_MODULE,
392 .probe = wdt_gpi_probe,
393 .remove = __exit_p(wdt_gpi_remove),
394 .shutdown = NULL,
395 .suspend = NULL,
396 .resume = NULL,
397};
398
399static int __init wdt_gpi_init_module(void)
400{
401 atomic_set(&opencnt, 1);
402 if (timeout > MAX_TIMEOUT_SECONDS)
403 timeout = MAX_TIMEOUT_SECONDS;
404 return driver_register(&wdt_gpi_driver);
405}
406
407static void __exit wdt_gpi_cleanup_module(void)
408{
409 driver_unregister(&wdt_gpi_driver);
410}
411
412module_init(wdt_gpi_init_module);
413module_exit(wdt_gpi_cleanup_module);
414
415MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
416MODULE_DESCRIPTION("Basler eXcite watchdog driver for gpi devices");
417MODULE_VERSION("0.1");
418MODULE_LICENSE("GPL");
419MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
420
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 510816c16da3..04bee524e31a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -125,6 +125,7 @@ config I2C_I801
125 ICH7 125 ICH7
126 ESB2 126 ESB2
127 ICH8 127 ICH8
128 ICH9
128 129
129 This driver can also be built as a module. If so, the module 130 This driver can also be built as a module. If so, the module
130 will be called i2c-i801. 131 will be called i2c-i801.
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index bbb2fbee836f..c7be2fdbd86b 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -33,6 +33,7 @@
33 ICH7 27DA 33 ICH7 27DA
34 ESB2 269B 34 ESB2 269B
35 ICH8 283E 35 ICH8 283E
36 ICH9 2930
36 This driver supports several versions of Intel's I/O Controller Hubs (ICH). 37 This driver supports several versions of Intel's I/O Controller Hubs (ICH).
37 For SMBus support, they are similar to the PIIX4 and are part 38 For SMBus support, they are similar to the PIIX4 and are part
38 of Intel's '810' and other chipsets. 39 of Intel's '810' and other chipsets.
@@ -457,6 +458,7 @@ static struct pci_device_id i801_ids[] = {
457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
461 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
460 { 0, } 462 { 0, }
461}; 463};
462 464
diff --git a/drivers/i2c/busses/i2c-ixp4xx.c b/drivers/i2c/busses/i2c-ixp4xx.c
index 05fffb9415a2..68fe863f9d54 100644
--- a/drivers/i2c/busses/i2c-ixp4xx.c
+++ b/drivers/i2c/busses/i2c-ixp4xx.c
@@ -138,7 +138,7 @@ static int ixp4xx_i2c_probe(struct platform_device *plat_dev)
138 gpio_line_set(gpio->sda_pin, 0); 138 gpio_line_set(gpio->sda_pin, 0);
139 139
140 err = i2c_bit_add_bus(&drv_data->adapter); 140 err = i2c_bit_add_bus(&drv_data->adapter);
141 if (err != 0) 141 if (err) {
142 printk(KERN_ERR "ERROR: Could not install %s\n", plat_dev->dev.bus_id); 142 printk(KERN_ERR "ERROR: Could not install %s\n", plat_dev->dev.bus_id);
143 143
144 kfree(drv_data); 144 kfree(drv_data);
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index 3f869033ed70..94a4e9a3013c 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -42,7 +42,7 @@ static struct i2c_driver i2cdev_driver;
42struct i2c_dev { 42struct i2c_dev {
43 struct list_head list; 43 struct list_head list;
44 struct i2c_adapter *adap; 44 struct i2c_adapter *adap;
45 struct class_device *class_dev; 45 struct device *dev;
46}; 46};
47 47
48#define I2C_MINORS 256 48#define I2C_MINORS 256
@@ -92,15 +92,16 @@ static void return_i2c_dev(struct i2c_dev *i2c_dev)
92 spin_unlock(&i2c_dev_list_lock); 92 spin_unlock(&i2c_dev_list_lock);
93} 93}
94 94
95static ssize_t show_adapter_name(struct class_device *class_dev, char *buf) 95static ssize_t show_adapter_name(struct device *dev,
96 struct device_attribute *attr, char *buf)
96{ 97{
97 struct i2c_dev *i2c_dev = i2c_dev_get_by_minor(MINOR(class_dev->devt)); 98 struct i2c_dev *i2c_dev = i2c_dev_get_by_minor(MINOR(dev->devt));
98 99
99 if (!i2c_dev) 100 if (!i2c_dev)
100 return -ENODEV; 101 return -ENODEV;
101 return sprintf(buf, "%s\n", i2c_dev->adap->name); 102 return sprintf(buf, "%s\n", i2c_dev->adap->name);
102} 103}
103static CLASS_DEVICE_ATTR(name, S_IRUGO, show_adapter_name, NULL); 104static DEVICE_ATTR(name, S_IRUGO, show_adapter_name, NULL);
104 105
105static ssize_t i2cdev_read (struct file *file, char __user *buf, size_t count, 106static ssize_t i2cdev_read (struct file *file, char __user *buf, size_t count,
106 loff_t *offset) 107 loff_t *offset)
@@ -413,15 +414,14 @@ static int i2cdev_attach_adapter(struct i2c_adapter *adap)
413 return PTR_ERR(i2c_dev); 414 return PTR_ERR(i2c_dev);
414 415
415 /* register this i2c device with the driver core */ 416 /* register this i2c device with the driver core */
416 i2c_dev->class_dev = class_device_create(i2c_dev_class, NULL, 417 i2c_dev->dev = device_create(i2c_dev_class, &adap->dev,
417 MKDEV(I2C_MAJOR, adap->nr), 418 MKDEV(I2C_MAJOR, adap->nr),
418 &adap->dev, "i2c-%d", 419 "i2c-%d", adap->nr);
419 adap->nr); 420 if (!i2c_dev->dev) {
420 if (!i2c_dev->class_dev) {
421 res = -ENODEV; 421 res = -ENODEV;
422 goto error; 422 goto error;
423 } 423 }
424 res = class_device_create_file(i2c_dev->class_dev, &class_device_attr_name); 424 res = device_create_file(i2c_dev->dev, &dev_attr_name);
425 if (res) 425 if (res)
426 goto error_destroy; 426 goto error_destroy;
427 427
@@ -429,7 +429,7 @@ static int i2cdev_attach_adapter(struct i2c_adapter *adap)
429 adap->name, adap->nr); 429 adap->name, adap->nr);
430 return 0; 430 return 0;
431error_destroy: 431error_destroy:
432 class_device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr)); 432 device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr));
433error: 433error:
434 return_i2c_dev(i2c_dev); 434 return_i2c_dev(i2c_dev);
435 kfree(i2c_dev); 435 kfree(i2c_dev);
@@ -444,9 +444,9 @@ static int i2cdev_detach_adapter(struct i2c_adapter *adap)
444 if (!i2c_dev) /* attach_adapter must have failed */ 444 if (!i2c_dev) /* attach_adapter must have failed */
445 return 0; 445 return 0;
446 446
447 class_device_remove_file(i2c_dev->class_dev, &class_device_attr_name); 447 device_remove_file(i2c_dev->dev, &dev_attr_name);
448 return_i2c_dev(i2c_dev); 448 return_i2c_dev(i2c_dev);
449 class_device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr)); 449 device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr));
450 kfree(i2c_dev); 450 kfree(i2c_dev);
451 451
452 pr_debug("i2c-dev: adapter [%s] unregistered\n", adap->name); 452 pr_debug("i2c-dev: adapter [%s] unregistered\n", adap->name);
diff --git a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c
index 8ccee9c769f8..e3a267622bb6 100644
--- a/drivers/ide/ide-floppy.c
+++ b/drivers/ide/ide-floppy.c
@@ -1635,7 +1635,7 @@ static int idefloppy_begin_format(ide_drive_t *drive, int __user *arg)
1635/* 1635/*
1636** Get ATAPI_FORMAT_UNIT progress indication. 1636** Get ATAPI_FORMAT_UNIT progress indication.
1637** 1637**
1638** Userland gives a pointer to an int. The int is set to a progresss 1638** Userland gives a pointer to an int. The int is set to a progress
1639** indicator 0-65536, with 65536=100%. 1639** indicator 0-65536, with 65536=100%.
1640** 1640**
1641** If the drive does not support format progress indication, we just check 1641** If the drive does not support format progress indication, we just check
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index 244f7eb7006d..cfad09accf52 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -768,14 +768,7 @@ ioc4_ide_init(void)
768 return ioc4_register_submodule(&ioc4_ide_submodule); 768 return ioc4_register_submodule(&ioc4_ide_submodule);
769} 769}
770 770
771static void __devexit
772ioc4_ide_exit(void)
773{
774 ioc4_unregister_submodule(&ioc4_ide_submodule);
775}
776
777late_initcall(ioc4_ide_init); /* Call only after IDE init is done */ 771late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
778module_exit(ioc4_ide_exit);
779 772
780MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon"); 773MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
781MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card"); 774MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
diff --git a/drivers/infiniband/core/addr.c b/drivers/infiniband/core/addr.c
index 84b2f5cb3722..af939796750d 100644
--- a/drivers/infiniband/core/addr.c
+++ b/drivers/infiniband/core/addr.c
@@ -139,7 +139,7 @@ static void queue_req(struct addr_req *req)
139 139
140 mutex_lock(&lock); 140 mutex_lock(&lock);
141 list_for_each_entry_reverse(temp_req, &req_list, list) { 141 list_for_each_entry_reverse(temp_req, &req_list, list) {
142 if (time_after(req->timeout, temp_req->timeout)) 142 if (time_after_eq(req->timeout, temp_req->timeout))
143 break; 143 break;
144 } 144 }
145 145
@@ -225,19 +225,17 @@ static void process_req(struct work_struct *work)
225 225
226 mutex_lock(&lock); 226 mutex_lock(&lock);
227 list_for_each_entry_safe(req, temp_req, &req_list, list) { 227 list_for_each_entry_safe(req, temp_req, &req_list, list) {
228 if (req->status) { 228 if (req->status == -ENODATA) {
229 src_in = (struct sockaddr_in *) &req->src_addr; 229 src_in = (struct sockaddr_in *) &req->src_addr;
230 dst_in = (struct sockaddr_in *) &req->dst_addr; 230 dst_in = (struct sockaddr_in *) &req->dst_addr;
231 req->status = addr_resolve_remote(src_in, dst_in, 231 req->status = addr_resolve_remote(src_in, dst_in,
232 req->addr); 232 req->addr);
233 if (req->status && time_after_eq(jiffies, req->timeout))
234 req->status = -ETIMEDOUT;
235 else if (req->status == -ENODATA)
236 continue;
233 } 237 }
234 if (req->status && time_after(jiffies, req->timeout)) 238 list_move_tail(&req->list, &done_list);
235 req->status = -ETIMEDOUT;
236 else if (req->status == -ENODATA)
237 continue;
238
239 list_del(&req->list);
240 list_add_tail(&req->list, &done_list);
241 } 239 }
242 240
243 if (!list_empty(&req_list)) { 241 if (!list_empty(&req_list)) {
@@ -347,8 +345,7 @@ void rdma_addr_cancel(struct rdma_dev_addr *addr)
347 if (req->addr == addr) { 345 if (req->addr == addr) {
348 req->status = -ECANCELED; 346 req->status = -ECANCELED;
349 req->timeout = jiffies; 347 req->timeout = jiffies;
350 list_del(&req->list); 348 list_move(&req->list, &req_list);
351 list_add(&req->list, &req_list);
352 set_timeout(req->timeout); 349 set_timeout(req->timeout);
353 break; 350 break;
354 } 351 }
diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c
index e1990f531d0a..79c937bf6962 100644
--- a/drivers/infiniband/core/cm.c
+++ b/drivers/infiniband/core/cm.c
@@ -147,12 +147,12 @@ struct cm_id_private {
147 __be32 rq_psn; 147 __be32 rq_psn;
148 int timeout_ms; 148 int timeout_ms;
149 enum ib_mtu path_mtu; 149 enum ib_mtu path_mtu;
150 __be16 pkey;
150 u8 private_data_len; 151 u8 private_data_len;
151 u8 max_cm_retries; 152 u8 max_cm_retries;
152 u8 peer_to_peer; 153 u8 peer_to_peer;
153 u8 responder_resources; 154 u8 responder_resources;
154 u8 initiator_depth; 155 u8 initiator_depth;
155 u8 local_ack_timeout;
156 u8 retry_count; 156 u8 retry_count;
157 u8 rnr_retry_count; 157 u8 rnr_retry_count;
158 u8 service_timeout; 158 u8 service_timeout;
@@ -240,11 +240,10 @@ static void * cm_copy_private_data(const void *private_data,
240 if (!private_data || !private_data_len) 240 if (!private_data || !private_data_len)
241 return NULL; 241 return NULL;
242 242
243 data = kmalloc(private_data_len, GFP_KERNEL); 243 data = kmemdup(private_data, private_data_len, GFP_KERNEL);
244 if (!data) 244 if (!data)
245 return ERR_PTR(-ENOMEM); 245 return ERR_PTR(-ENOMEM);
246 246
247 memcpy(data, private_data, private_data_len);
248 return data; 247 return data;
249} 248}
250 249
@@ -690,7 +689,7 @@ static void cm_enter_timewait(struct cm_id_private *cm_id_priv)
690 * timewait before notifying the user that we've exited timewait. 689 * timewait before notifying the user that we've exited timewait.
691 */ 690 */
692 cm_id_priv->id.state = IB_CM_TIMEWAIT; 691 cm_id_priv->id.state = IB_CM_TIMEWAIT;
693 wait_time = cm_convert_to_ms(cm_id_priv->local_ack_timeout); 692 wait_time = cm_convert_to_ms(cm_id_priv->av.packet_life_time + 1);
694 queue_delayed_work(cm.wq, &cm_id_priv->timewait_info->work.work, 693 queue_delayed_work(cm.wq, &cm_id_priv->timewait_info->work.work,
695 msecs_to_jiffies(wait_time)); 694 msecs_to_jiffies(wait_time));
696 cm_id_priv->timewait_info = NULL; 695 cm_id_priv->timewait_info = NULL;
@@ -1009,6 +1008,7 @@ int ib_send_cm_req(struct ib_cm_id *cm_id,
1009 cm_id_priv->responder_resources = param->responder_resources; 1008 cm_id_priv->responder_resources = param->responder_resources;
1010 cm_id_priv->retry_count = param->retry_count; 1009 cm_id_priv->retry_count = param->retry_count;
1011 cm_id_priv->path_mtu = param->primary_path->mtu; 1010 cm_id_priv->path_mtu = param->primary_path->mtu;
1011 cm_id_priv->pkey = param->primary_path->pkey;
1012 cm_id_priv->qp_type = param->qp_type; 1012 cm_id_priv->qp_type = param->qp_type;
1013 1013
1014 ret = cm_alloc_msg(cm_id_priv, &cm_id_priv->msg); 1014 ret = cm_alloc_msg(cm_id_priv, &cm_id_priv->msg);
@@ -1023,8 +1023,6 @@ int ib_send_cm_req(struct ib_cm_id *cm_id,
1023 1023
1024 cm_id_priv->local_qpn = cm_req_get_local_qpn(req_msg); 1024 cm_id_priv->local_qpn = cm_req_get_local_qpn(req_msg);
1025 cm_id_priv->rq_psn = cm_req_get_starting_psn(req_msg); 1025 cm_id_priv->rq_psn = cm_req_get_starting_psn(req_msg);
1026 cm_id_priv->local_ack_timeout =
1027 cm_req_get_primary_local_ack_timeout(req_msg);
1028 1026
1029 spin_lock_irqsave(&cm_id_priv->lock, flags); 1027 spin_lock_irqsave(&cm_id_priv->lock, flags);
1030 ret = ib_post_send_mad(cm_id_priv->msg, NULL); 1028 ret = ib_post_send_mad(cm_id_priv->msg, NULL);
@@ -1409,9 +1407,8 @@ static int cm_req_handler(struct cm_work *work)
1409 cm_id_priv->initiator_depth = cm_req_get_resp_res(req_msg); 1407 cm_id_priv->initiator_depth = cm_req_get_resp_res(req_msg);
1410 cm_id_priv->responder_resources = cm_req_get_init_depth(req_msg); 1408 cm_id_priv->responder_resources = cm_req_get_init_depth(req_msg);
1411 cm_id_priv->path_mtu = cm_req_get_path_mtu(req_msg); 1409 cm_id_priv->path_mtu = cm_req_get_path_mtu(req_msg);
1410 cm_id_priv->pkey = req_msg->pkey;
1412 cm_id_priv->sq_psn = cm_req_get_starting_psn(req_msg); 1411 cm_id_priv->sq_psn = cm_req_get_starting_psn(req_msg);
1413 cm_id_priv->local_ack_timeout =
1414 cm_req_get_primary_local_ack_timeout(req_msg);
1415 cm_id_priv->retry_count = cm_req_get_retry_count(req_msg); 1412 cm_id_priv->retry_count = cm_req_get_retry_count(req_msg);
1416 cm_id_priv->rnr_retry_count = cm_req_get_rnr_retry_count(req_msg); 1413 cm_id_priv->rnr_retry_count = cm_req_get_rnr_retry_count(req_msg);
1417 cm_id_priv->qp_type = cm_req_get_qp_type(req_msg); 1414 cm_id_priv->qp_type = cm_req_get_qp_type(req_msg);
@@ -1715,7 +1712,7 @@ static int cm_establish_handler(struct cm_work *work)
1715 unsigned long flags; 1712 unsigned long flags;
1716 int ret; 1713 int ret;
1717 1714
1718 /* See comment in ib_cm_establish about lookup. */ 1715 /* See comment in cm_establish about lookup. */
1719 cm_id_priv = cm_acquire_id(work->local_id, work->remote_id); 1716 cm_id_priv = cm_acquire_id(work->local_id, work->remote_id);
1720 if (!cm_id_priv) 1717 if (!cm_id_priv)
1721 return -EINVAL; 1718 return -EINVAL;
@@ -2401,11 +2398,16 @@ int ib_send_cm_lap(struct ib_cm_id *cm_id,
2401 cm_id_priv = container_of(cm_id, struct cm_id_private, id); 2398 cm_id_priv = container_of(cm_id, struct cm_id_private, id);
2402 spin_lock_irqsave(&cm_id_priv->lock, flags); 2399 spin_lock_irqsave(&cm_id_priv->lock, flags);
2403 if (cm_id->state != IB_CM_ESTABLISHED || 2400 if (cm_id->state != IB_CM_ESTABLISHED ||
2404 cm_id->lap_state != IB_CM_LAP_IDLE) { 2401 (cm_id->lap_state != IB_CM_LAP_UNINIT &&
2402 cm_id->lap_state != IB_CM_LAP_IDLE)) {
2405 ret = -EINVAL; 2403 ret = -EINVAL;
2406 goto out; 2404 goto out;
2407 } 2405 }
2408 2406
2407 ret = cm_init_av_by_path(alternate_path, &cm_id_priv->alt_av);
2408 if (ret)
2409 goto out;
2410
2409 ret = cm_alloc_msg(cm_id_priv, &msg); 2411 ret = cm_alloc_msg(cm_id_priv, &msg);
2410 if (ret) 2412 if (ret)
2411 goto out; 2413 goto out;
@@ -2430,7 +2432,8 @@ out: spin_unlock_irqrestore(&cm_id_priv->lock, flags);
2430} 2432}
2431EXPORT_SYMBOL(ib_send_cm_lap); 2433EXPORT_SYMBOL(ib_send_cm_lap);
2432 2434
2433static void cm_format_path_from_lap(struct ib_sa_path_rec *path, 2435static void cm_format_path_from_lap(struct cm_id_private *cm_id_priv,
2436 struct ib_sa_path_rec *path,
2434 struct cm_lap_msg *lap_msg) 2437 struct cm_lap_msg *lap_msg)
2435{ 2438{
2436 memset(path, 0, sizeof *path); 2439 memset(path, 0, sizeof *path);
@@ -2442,10 +2445,10 @@ static void cm_format_path_from_lap(struct ib_sa_path_rec *path,
2442 path->hop_limit = lap_msg->alt_hop_limit; 2445 path->hop_limit = lap_msg->alt_hop_limit;
2443 path->traffic_class = cm_lap_get_traffic_class(lap_msg); 2446 path->traffic_class = cm_lap_get_traffic_class(lap_msg);
2444 path->reversible = 1; 2447 path->reversible = 1;
2445 /* pkey is same as in REQ */ 2448 path->pkey = cm_id_priv->pkey;
2446 path->sl = cm_lap_get_sl(lap_msg); 2449 path->sl = cm_lap_get_sl(lap_msg);
2447 path->mtu_selector = IB_SA_EQ; 2450 path->mtu_selector = IB_SA_EQ;
2448 /* mtu is same as in REQ */ 2451 path->mtu = cm_id_priv->path_mtu;
2449 path->rate_selector = IB_SA_EQ; 2452 path->rate_selector = IB_SA_EQ;
2450 path->rate = cm_lap_get_packet_rate(lap_msg); 2453 path->rate = cm_lap_get_packet_rate(lap_msg);
2451 path->packet_life_time_selector = IB_SA_EQ; 2454 path->packet_life_time_selector = IB_SA_EQ;
@@ -2471,7 +2474,7 @@ static int cm_lap_handler(struct cm_work *work)
2471 2474
2472 param = &work->cm_event.param.lap_rcvd; 2475 param = &work->cm_event.param.lap_rcvd;
2473 param->alternate_path = &work->path[0]; 2476 param->alternate_path = &work->path[0];
2474 cm_format_path_from_lap(param->alternate_path, lap_msg); 2477 cm_format_path_from_lap(cm_id_priv, param->alternate_path, lap_msg);
2475 work->cm_event.private_data = &lap_msg->private_data; 2478 work->cm_event.private_data = &lap_msg->private_data;
2476 2479
2477 spin_lock_irqsave(&cm_id_priv->lock, flags); 2480 spin_lock_irqsave(&cm_id_priv->lock, flags);
@@ -2479,6 +2482,7 @@ static int cm_lap_handler(struct cm_work *work)
2479 goto unlock; 2482 goto unlock;
2480 2483
2481 switch (cm_id_priv->id.lap_state) { 2484 switch (cm_id_priv->id.lap_state) {
2485 case IB_CM_LAP_UNINIT:
2482 case IB_CM_LAP_IDLE: 2486 case IB_CM_LAP_IDLE:
2483 break; 2487 break;
2484 case IB_CM_MRA_LAP_SENT: 2488 case IB_CM_MRA_LAP_SENT:
@@ -2501,6 +2505,10 @@ static int cm_lap_handler(struct cm_work *work)
2501 2505
2502 cm_id_priv->id.lap_state = IB_CM_LAP_RCVD; 2506 cm_id_priv->id.lap_state = IB_CM_LAP_RCVD;
2503 cm_id_priv->tid = lap_msg->hdr.tid; 2507 cm_id_priv->tid = lap_msg->hdr.tid;
2508 cm_init_av_for_response(work->port, work->mad_recv_wc->wc,
2509 work->mad_recv_wc->recv_buf.grh,
2510 &cm_id_priv->av);
2511 cm_init_av_by_path(param->alternate_path, &cm_id_priv->alt_av);
2504 ret = atomic_inc_and_test(&cm_id_priv->work_count); 2512 ret = atomic_inc_and_test(&cm_id_priv->work_count);
2505 if (!ret) 2513 if (!ret)
2506 list_add_tail(&work->list, &cm_id_priv->work_list); 2514 list_add_tail(&work->list, &cm_id_priv->work_list);
@@ -3039,7 +3047,7 @@ static void cm_work_handler(struct work_struct *_work)
3039 cm_free_work(work); 3047 cm_free_work(work);
3040} 3048}
3041 3049
3042int ib_cm_establish(struct ib_cm_id *cm_id) 3050static int cm_establish(struct ib_cm_id *cm_id)
3043{ 3051{
3044 struct cm_id_private *cm_id_priv; 3052 struct cm_id_private *cm_id_priv;
3045 struct cm_work *work; 3053 struct cm_work *work;
@@ -3087,7 +3095,44 @@ int ib_cm_establish(struct ib_cm_id *cm_id)
3087out: 3095out:
3088 return ret; 3096 return ret;
3089} 3097}
3090EXPORT_SYMBOL(ib_cm_establish); 3098
3099static int cm_migrate(struct ib_cm_id *cm_id)
3100{
3101 struct cm_id_private *cm_id_priv;
3102 unsigned long flags;
3103 int ret = 0;
3104
3105 cm_id_priv = container_of(cm_id, struct cm_id_private, id);
3106 spin_lock_irqsave(&cm_id_priv->lock, flags);
3107 if (cm_id->state == IB_CM_ESTABLISHED &&
3108 (cm_id->lap_state == IB_CM_LAP_UNINIT ||
3109 cm_id->lap_state == IB_CM_LAP_IDLE)) {
3110 cm_id->lap_state = IB_CM_LAP_IDLE;
3111 cm_id_priv->av = cm_id_priv->alt_av;
3112 } else
3113 ret = -EINVAL;
3114 spin_unlock_irqrestore(&cm_id_priv->lock, flags);
3115
3116 return ret;
3117}
3118
3119int ib_cm_notify(struct ib_cm_id *cm_id, enum ib_event_type event)
3120{
3121 int ret;
3122
3123 switch (event) {
3124 case IB_EVENT_COMM_EST:
3125 ret = cm_establish(cm_id);
3126 break;
3127 case IB_EVENT_PATH_MIG:
3128 ret = cm_migrate(cm_id);
3129 break;
3130 default:
3131 ret = -EINVAL;
3132 }
3133 return ret;
3134}
3135EXPORT_SYMBOL(ib_cm_notify);
3091 3136
3092static void cm_recv_handler(struct ib_mad_agent *mad_agent, 3137static void cm_recv_handler(struct ib_mad_agent *mad_agent,
3093 struct ib_mad_recv_wc *mad_recv_wc) 3138 struct ib_mad_recv_wc *mad_recv_wc)
@@ -3172,8 +3217,7 @@ static int cm_init_qp_init_attr(struct cm_id_private *cm_id_priv,
3172 case IB_CM_ESTABLISHED: 3217 case IB_CM_ESTABLISHED:
3173 *qp_attr_mask = IB_QP_STATE | IB_QP_ACCESS_FLAGS | 3218 *qp_attr_mask = IB_QP_STATE | IB_QP_ACCESS_FLAGS |
3174 IB_QP_PKEY_INDEX | IB_QP_PORT; 3219 IB_QP_PKEY_INDEX | IB_QP_PORT;
3175 qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE | 3220 qp_attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
3176 IB_ACCESS_REMOTE_WRITE;
3177 if (cm_id_priv->responder_resources) 3221 if (cm_id_priv->responder_resources)
3178 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ | 3222 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ |
3179 IB_ACCESS_REMOTE_ATOMIC; 3223 IB_ACCESS_REMOTE_ATOMIC;
@@ -3221,6 +3265,9 @@ static int cm_init_qp_rtr_attr(struct cm_id_private *cm_id_priv,
3221 if (cm_id_priv->alt_av.ah_attr.dlid) { 3265 if (cm_id_priv->alt_av.ah_attr.dlid) {
3222 *qp_attr_mask |= IB_QP_ALT_PATH; 3266 *qp_attr_mask |= IB_QP_ALT_PATH;
3223 qp_attr->alt_port_num = cm_id_priv->alt_av.port->port_num; 3267 qp_attr->alt_port_num = cm_id_priv->alt_av.port->port_num;
3268 qp_attr->alt_pkey_index = cm_id_priv->alt_av.pkey_index;
3269 qp_attr->alt_timeout =
3270 cm_id_priv->alt_av.packet_life_time + 1;
3224 qp_attr->alt_ah_attr = cm_id_priv->alt_av.ah_attr; 3271 qp_attr->alt_ah_attr = cm_id_priv->alt_av.ah_attr;
3225 } 3272 }
3226 ret = 0; 3273 ret = 0;
@@ -3247,19 +3294,31 @@ static int cm_init_qp_rts_attr(struct cm_id_private *cm_id_priv,
3247 case IB_CM_REP_SENT: 3294 case IB_CM_REP_SENT:
3248 case IB_CM_MRA_REP_RCVD: 3295 case IB_CM_MRA_REP_RCVD:
3249 case IB_CM_ESTABLISHED: 3296 case IB_CM_ESTABLISHED:
3250 *qp_attr_mask = IB_QP_STATE | IB_QP_SQ_PSN; 3297 if (cm_id_priv->id.lap_state == IB_CM_LAP_UNINIT) {
3251 qp_attr->sq_psn = be32_to_cpu(cm_id_priv->sq_psn); 3298 *qp_attr_mask = IB_QP_STATE | IB_QP_SQ_PSN;
3252 if (cm_id_priv->qp_type == IB_QPT_RC) { 3299 qp_attr->sq_psn = be32_to_cpu(cm_id_priv->sq_psn);
3253 *qp_attr_mask |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | 3300 if (cm_id_priv->qp_type == IB_QPT_RC) {
3254 IB_QP_RNR_RETRY | 3301 *qp_attr_mask |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT |
3255 IB_QP_MAX_QP_RD_ATOMIC; 3302 IB_QP_RNR_RETRY |
3256 qp_attr->timeout = cm_id_priv->local_ack_timeout; 3303 IB_QP_MAX_QP_RD_ATOMIC;
3257 qp_attr->retry_cnt = cm_id_priv->retry_count; 3304 qp_attr->timeout =
3258 qp_attr->rnr_retry = cm_id_priv->rnr_retry_count; 3305 cm_id_priv->av.packet_life_time + 1;
3259 qp_attr->max_rd_atomic = cm_id_priv->initiator_depth; 3306 qp_attr->retry_cnt = cm_id_priv->retry_count;
3260 } 3307 qp_attr->rnr_retry = cm_id_priv->rnr_retry_count;
3261 if (cm_id_priv->alt_av.ah_attr.dlid) { 3308 qp_attr->max_rd_atomic =
3262 *qp_attr_mask |= IB_QP_PATH_MIG_STATE; 3309 cm_id_priv->initiator_depth;
3310 }
3311 if (cm_id_priv->alt_av.ah_attr.dlid) {
3312 *qp_attr_mask |= IB_QP_PATH_MIG_STATE;
3313 qp_attr->path_mig_state = IB_MIG_REARM;
3314 }
3315 } else {
3316 *qp_attr_mask = IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE;
3317 qp_attr->alt_port_num = cm_id_priv->alt_av.port->port_num;
3318 qp_attr->alt_pkey_index = cm_id_priv->alt_av.pkey_index;
3319 qp_attr->alt_timeout =
3320 cm_id_priv->alt_av.packet_life_time + 1;
3321 qp_attr->alt_ah_attr = cm_id_priv->alt_av.ah_attr;
3263 qp_attr->path_mig_state = IB_MIG_REARM; 3322 qp_attr->path_mig_state = IB_MIG_REARM;
3264 } 3323 }
3265 ret = 0; 3324 ret = 0;
diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c
index 189f73f3f721..985a6b564d8f 100644
--- a/drivers/infiniband/core/cma.c
+++ b/drivers/infiniband/core/cma.c
@@ -344,7 +344,7 @@ static int cma_init_ib_qp(struct rdma_id_private *id_priv, struct ib_qp *qp)
344 return ret; 344 return ret;
345 345
346 qp_attr.qp_state = IB_QPS_INIT; 346 qp_attr.qp_state = IB_QPS_INIT;
347 qp_attr.qp_access_flags = IB_ACCESS_LOCAL_WRITE; 347 qp_attr.qp_access_flags = 0;
348 qp_attr.port_num = id_priv->id.port_num; 348 qp_attr.port_num = id_priv->id.port_num;
349 return ib_modify_qp(qp, &qp_attr, IB_QP_STATE | IB_QP_ACCESS_FLAGS | 349 return ib_modify_qp(qp, &qp_attr, IB_QP_STATE | IB_QP_ACCESS_FLAGS |
350 IB_QP_PKEY_INDEX | IB_QP_PORT); 350 IB_QP_PKEY_INDEX | IB_QP_PORT);
@@ -935,13 +935,8 @@ static int cma_req_handler(struct ib_cm_id *cm_id, struct ib_cm_event *ib_event)
935 mutex_lock(&lock); 935 mutex_lock(&lock);
936 ret = cma_acquire_dev(conn_id); 936 ret = cma_acquire_dev(conn_id);
937 mutex_unlock(&lock); 937 mutex_unlock(&lock);
938 if (ret) { 938 if (ret)
939 ret = -ENODEV; 939 goto release_conn_id;
940 cma_exch(conn_id, CMA_DESTROYING);
941 cma_release_remove(conn_id);
942 rdma_destroy_id(&conn_id->id);
943 goto out;
944 }
945 940
946 conn_id->cm_id.ib = cm_id; 941 conn_id->cm_id.ib = cm_id;
947 cm_id->context = conn_id; 942 cm_id->context = conn_id;
@@ -951,13 +946,17 @@ static int cma_req_handler(struct ib_cm_id *cm_id, struct ib_cm_event *ib_event)
951 ret = cma_notify_user(conn_id, RDMA_CM_EVENT_CONNECT_REQUEST, 0, 946 ret = cma_notify_user(conn_id, RDMA_CM_EVENT_CONNECT_REQUEST, 0,
952 ib_event->private_data + offset, 947 ib_event->private_data + offset,
953 IB_CM_REQ_PRIVATE_DATA_SIZE - offset); 948 IB_CM_REQ_PRIVATE_DATA_SIZE - offset);
954 if (ret) { 949 if (!ret)
955 /* Destroy the CM ID by returning a non-zero value. */ 950 goto out;
956 conn_id->cm_id.ib = NULL; 951
957 cma_exch(conn_id, CMA_DESTROYING); 952 /* Destroy the CM ID by returning a non-zero value. */
958 cma_release_remove(conn_id); 953 conn_id->cm_id.ib = NULL;
959 rdma_destroy_id(&conn_id->id); 954
960 } 955release_conn_id:
956 cma_exch(conn_id, CMA_DESTROYING);
957 cma_release_remove(conn_id);
958 rdma_destroy_id(&conn_id->id);
959
961out: 960out:
962 cma_release_remove(listen_id); 961 cma_release_remove(listen_id);
963 return ret; 962 return ret;
@@ -1481,19 +1480,18 @@ static int cma_bind_loopback(struct rdma_id_private *id_priv)
1481 u8 p; 1480 u8 p;
1482 1481
1483 mutex_lock(&lock); 1482 mutex_lock(&lock);
1483 if (list_empty(&dev_list)) {
1484 ret = -ENODEV;
1485 goto out;
1486 }
1484 list_for_each_entry(cma_dev, &dev_list, list) 1487 list_for_each_entry(cma_dev, &dev_list, list)
1485 for (p = 1; p <= cma_dev->device->phys_port_cnt; ++p) 1488 for (p = 1; p <= cma_dev->device->phys_port_cnt; ++p)
1486 if (!ib_query_port (cma_dev->device, p, &port_attr) && 1489 if (!ib_query_port(cma_dev->device, p, &port_attr) &&
1487 port_attr.state == IB_PORT_ACTIVE) 1490 port_attr.state == IB_PORT_ACTIVE)
1488 goto port_found; 1491 goto port_found;
1489 1492
1490 if (!list_empty(&dev_list)) { 1493 p = 1;
1491 p = 1; 1494 cma_dev = list_entry(dev_list.next, struct cma_device, list);
1492 cma_dev = list_entry(dev_list.next, struct cma_device, list);
1493 } else {
1494 ret = -ENODEV;
1495 goto out;
1496 }
1497 1495
1498port_found: 1496port_found:
1499 ret = ib_get_cached_gid(cma_dev->device, p, 0, &gid); 1497 ret = ib_get_cached_gid(cma_dev->device, p, 0, &gid);
@@ -2123,8 +2121,6 @@ static void cma_add_one(struct ib_device *device)
2123 2121
2124 cma_dev->device = device; 2122 cma_dev->device = device;
2125 cma_dev->node_guid = device->node_guid; 2123 cma_dev->node_guid = device->node_guid;
2126 if (!cma_dev->node_guid)
2127 goto err;
2128 2124
2129 init_completion(&cma_dev->comp); 2125 init_completion(&cma_dev->comp);
2130 atomic_set(&cma_dev->refcount, 1); 2126 atomic_set(&cma_dev->refcount, 1);
@@ -2136,9 +2132,6 @@ static void cma_add_one(struct ib_device *device)
2136 list_for_each_entry(id_priv, &listen_any_list, list) 2132 list_for_each_entry(id_priv, &listen_any_list, list)
2137 cma_listen_on_dev(id_priv, cma_dev); 2133 cma_listen_on_dev(id_priv, cma_dev);
2138 mutex_unlock(&lock); 2134 mutex_unlock(&lock);
2139 return;
2140err:
2141 kfree(cma_dev);
2142} 2135}
2143 2136
2144static int cma_remove_id_dev(struct rdma_id_private *id_priv) 2137static int cma_remove_id_dev(struct rdma_id_private *id_priv)
diff --git a/drivers/infiniband/core/iwcm.c b/drivers/infiniband/core/iwcm.c
index 9bfa785252dc..1039ad57d53b 100644
--- a/drivers/infiniband/core/iwcm.c
+++ b/drivers/infiniband/core/iwcm.c
@@ -80,7 +80,7 @@ struct iwcm_work {
80 * 1) in the event upcall, cm_event_handler(), for a listening cm_id. If 80 * 1) in the event upcall, cm_event_handler(), for a listening cm_id. If
81 * the backlog is exceeded, then no more connection request events will 81 * the backlog is exceeded, then no more connection request events will
82 * be processed. cm_event_handler() returns -ENOMEM in this case. Its up 82 * be processed. cm_event_handler() returns -ENOMEM in this case. Its up
83 * to the provider to reject the connectino request. 83 * to the provider to reject the connection request.
84 * 2) in the connection request workqueue handler, cm_conn_req_handler(). 84 * 2) in the connection request workqueue handler, cm_conn_req_handler().
85 * If work elements cannot be allocated for the new connect request cm_id, 85 * If work elements cannot be allocated for the new connect request cm_id,
86 * then IWCM will call the provider reject method. This is ok since 86 * then IWCM will call the provider reject method. This is ok since
@@ -131,26 +131,25 @@ static int alloc_work_entries(struct iwcm_id_private *cm_id_priv, int count)
131} 131}
132 132
133/* 133/*
134 * Save private data from incoming connection requests in the 134 * Save private data from incoming connection requests to
135 * cm_id_priv so the low level driver doesn't have to. Adjust 135 * iw_cm_event, so the low level driver doesn't have to. Adjust
136 * the event ptr to point to the local copy. 136 * the event ptr to point to the local copy.
137 */ 137 */
138static int copy_private_data(struct iwcm_id_private *cm_id_priv, 138static int copy_private_data(struct iw_cm_event *event)
139 struct iw_cm_event *event)
140{ 139{
141 void *p; 140 void *p;
142 141
143 p = kmalloc(event->private_data_len, GFP_ATOMIC); 142 p = kmemdup(event->private_data, event->private_data_len, GFP_ATOMIC);
144 if (!p) 143 if (!p)
145 return -ENOMEM; 144 return -ENOMEM;
146 memcpy(p, event->private_data, event->private_data_len);
147 event->private_data = p; 145 event->private_data = p;
148 return 0; 146 return 0;
149} 147}
150 148
151/* 149/*
152 * Release a reference on cm_id. If the last reference is being removed 150 * Release a reference on cm_id. If the last reference is being
153 * and iw_destroy_cm_id is waiting, wake up the waiting thread. 151 * released, enable the waiting thread (in iw_destroy_cm_id) to
152 * get woken up, and return 1 if a thread is already waiting.
154 */ 153 */
155static int iwcm_deref_id(struct iwcm_id_private *cm_id_priv) 154static int iwcm_deref_id(struct iwcm_id_private *cm_id_priv)
156{ 155{
@@ -243,7 +242,7 @@ static int iwcm_modify_qp_sqd(struct ib_qp *qp)
243/* 242/*
244 * CM_ID <-- CLOSING 243 * CM_ID <-- CLOSING
245 * 244 *
246 * Block if a passive or active connection is currenlty being processed. Then 245 * Block if a passive or active connection is currently being processed. Then
247 * process the event as follows: 246 * process the event as follows:
248 * - If we are ESTABLISHED, move to CLOSING and modify the QP state 247 * - If we are ESTABLISHED, move to CLOSING and modify the QP state
249 * based on the abrupt flag 248 * based on the abrupt flag
@@ -408,7 +407,7 @@ int iw_cm_listen(struct iw_cm_id *cm_id, int backlog)
408{ 407{
409 struct iwcm_id_private *cm_id_priv; 408 struct iwcm_id_private *cm_id_priv;
410 unsigned long flags; 409 unsigned long flags;
411 int ret = 0; 410 int ret;
412 411
413 cm_id_priv = container_of(cm_id, struct iwcm_id_private, id); 412 cm_id_priv = container_of(cm_id, struct iwcm_id_private, id);
414 413
@@ -535,7 +534,7 @@ EXPORT_SYMBOL(iw_cm_accept);
535int iw_cm_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *iw_param) 534int iw_cm_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *iw_param)
536{ 535{
537 struct iwcm_id_private *cm_id_priv; 536 struct iwcm_id_private *cm_id_priv;
538 int ret = 0; 537 int ret;
539 unsigned long flags; 538 unsigned long flags;
540 struct ib_qp *qp; 539 struct ib_qp *qp;
541 540
@@ -620,7 +619,7 @@ static void cm_conn_req_handler(struct iwcm_id_private *listen_id_priv,
620 spin_lock_irqsave(&listen_id_priv->lock, flags); 619 spin_lock_irqsave(&listen_id_priv->lock, flags);
621 if (listen_id_priv->state != IW_CM_STATE_LISTEN) { 620 if (listen_id_priv->state != IW_CM_STATE_LISTEN) {
622 spin_unlock_irqrestore(&listen_id_priv->lock, flags); 621 spin_unlock_irqrestore(&listen_id_priv->lock, flags);
623 return; 622 goto out;
624 } 623 }
625 spin_unlock_irqrestore(&listen_id_priv->lock, flags); 624 spin_unlock_irqrestore(&listen_id_priv->lock, flags);
626 625
@@ -629,7 +628,7 @@ static void cm_conn_req_handler(struct iwcm_id_private *listen_id_priv,
629 listen_id_priv->id.context); 628 listen_id_priv->id.context);
630 /* If the cm_id could not be created, ignore the request */ 629 /* If the cm_id could not be created, ignore the request */
631 if (IS_ERR(cm_id)) 630 if (IS_ERR(cm_id))
632 return; 631 goto out;
633 632
634 cm_id->provider_data = iw_event->provider_data; 633 cm_id->provider_data = iw_event->provider_data;
635 cm_id->local_addr = iw_event->local_addr; 634 cm_id->local_addr = iw_event->local_addr;
@@ -642,7 +641,7 @@ static void cm_conn_req_handler(struct iwcm_id_private *listen_id_priv,
642 if (ret) { 641 if (ret) {
643 iw_cm_reject(cm_id, NULL, 0); 642 iw_cm_reject(cm_id, NULL, 0);
644 iw_destroy_cm_id(cm_id); 643 iw_destroy_cm_id(cm_id);
645 return; 644 goto out;
646 } 645 }
647 646
648 /* Call the client CM handler */ 647 /* Call the client CM handler */
@@ -654,6 +653,7 @@ static void cm_conn_req_handler(struct iwcm_id_private *listen_id_priv,
654 kfree(cm_id); 653 kfree(cm_id);
655 } 654 }
656 655
656out:
657 if (iw_event->private_data_len) 657 if (iw_event->private_data_len)
658 kfree(iw_event->private_data); 658 kfree(iw_event->private_data);
659} 659}
@@ -674,7 +674,7 @@ static int cm_conn_est_handler(struct iwcm_id_private *cm_id_priv,
674 struct iw_cm_event *iw_event) 674 struct iw_cm_event *iw_event)
675{ 675{
676 unsigned long flags; 676 unsigned long flags;
677 int ret = 0; 677 int ret;
678 678
679 spin_lock_irqsave(&cm_id_priv->lock, flags); 679 spin_lock_irqsave(&cm_id_priv->lock, flags);
680 680
@@ -704,7 +704,7 @@ static int cm_conn_rep_handler(struct iwcm_id_private *cm_id_priv,
704 struct iw_cm_event *iw_event) 704 struct iw_cm_event *iw_event)
705{ 705{
706 unsigned long flags; 706 unsigned long flags;
707 int ret = 0; 707 int ret;
708 708
709 spin_lock_irqsave(&cm_id_priv->lock, flags); 709 spin_lock_irqsave(&cm_id_priv->lock, flags);
710 /* 710 /*
@@ -830,8 +830,8 @@ static int process_event(struct iwcm_id_private *cm_id_priv,
830 */ 830 */
831static void cm_work_handler(struct work_struct *_work) 831static void cm_work_handler(struct work_struct *_work)
832{ 832{
833 struct iwcm_work lwork, *work = 833 struct iwcm_work *work = container_of(_work, struct iwcm_work, work);
834 container_of(_work, struct iwcm_work, work); 834 struct iw_cm_event levent;
835 struct iwcm_id_private *cm_id_priv = work->cm_id; 835 struct iwcm_id_private *cm_id_priv = work->cm_id;
836 unsigned long flags; 836 unsigned long flags;
837 int empty; 837 int empty;
@@ -844,11 +844,11 @@ static void cm_work_handler(struct work_struct *_work)
844 struct iwcm_work, list); 844 struct iwcm_work, list);
845 list_del_init(&work->list); 845 list_del_init(&work->list);
846 empty = list_empty(&cm_id_priv->work_list); 846 empty = list_empty(&cm_id_priv->work_list);
847 lwork = *work; 847 levent = work->event;
848 put_work(work); 848 put_work(work);
849 spin_unlock_irqrestore(&cm_id_priv->lock, flags); 849 spin_unlock_irqrestore(&cm_id_priv->lock, flags);
850 850
851 ret = process_event(cm_id_priv, &work->event); 851 ret = process_event(cm_id_priv, &levent);
852 if (ret) { 852 if (ret) {
853 set_bit(IWCM_F_CALLBACK_DESTROY, &cm_id_priv->flags); 853 set_bit(IWCM_F_CALLBACK_DESTROY, &cm_id_priv->flags);
854 destroy_cm_id(&cm_id_priv->id); 854 destroy_cm_id(&cm_id_priv->id);
@@ -907,7 +907,7 @@ static int cm_event_handler(struct iw_cm_id *cm_id,
907 if ((work->event.event == IW_CM_EVENT_CONNECT_REQUEST || 907 if ((work->event.event == IW_CM_EVENT_CONNECT_REQUEST ||
908 work->event.event == IW_CM_EVENT_CONNECT_REPLY) && 908 work->event.event == IW_CM_EVENT_CONNECT_REPLY) &&
909 work->event.private_data_len) { 909 work->event.private_data_len) {
910 ret = copy_private_data(cm_id_priv, &work->event); 910 ret = copy_private_data(&work->event);
911 if (ret) { 911 if (ret) {
912 put_work(work); 912 put_work(work);
913 goto out; 913 goto out;
diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c
index 5a54ac35e961..15f38d94b3a8 100644
--- a/drivers/infiniband/core/mad.c
+++ b/drivers/infiniband/core/mad.c
@@ -46,7 +46,7 @@ MODULE_DESCRIPTION("kernel IB MAD API");
46MODULE_AUTHOR("Hal Rosenstock"); 46MODULE_AUTHOR("Hal Rosenstock");
47MODULE_AUTHOR("Sean Hefty"); 47MODULE_AUTHOR("Sean Hefty");
48 48
49static kmem_cache_t *ib_mad_cache; 49static struct kmem_cache *ib_mad_cache;
50 50
51static struct list_head ib_mad_port_list; 51static struct list_head ib_mad_port_list;
52static u32 ib_mad_client_id = 0; 52static u32 ib_mad_client_id = 0;
diff --git a/drivers/infiniband/core/ucm.c b/drivers/infiniband/core/ucm.c
index ad4f4d5c2924..f15220a0ee75 100644
--- a/drivers/infiniband/core/ucm.c
+++ b/drivers/infiniband/core/ucm.c
@@ -161,12 +161,14 @@ static void ib_ucm_cleanup_events(struct ib_ucm_context *ctx)
161 struct ib_ucm_event, ctx_list); 161 struct ib_ucm_event, ctx_list);
162 list_del(&uevent->file_list); 162 list_del(&uevent->file_list);
163 list_del(&uevent->ctx_list); 163 list_del(&uevent->ctx_list);
164 mutex_unlock(&ctx->file->file_mutex);
164 165
165 /* clear incoming connections. */ 166 /* clear incoming connections. */
166 if (ib_ucm_new_cm_id(uevent->resp.event)) 167 if (ib_ucm_new_cm_id(uevent->resp.event))
167 ib_destroy_cm_id(uevent->cm_id); 168 ib_destroy_cm_id(uevent->cm_id);
168 169
169 kfree(uevent); 170 kfree(uevent);
171 mutex_lock(&ctx->file->file_mutex);
170 } 172 }
171 mutex_unlock(&ctx->file->file_mutex); 173 mutex_unlock(&ctx->file->file_mutex);
172} 174}
@@ -328,20 +330,18 @@ static int ib_ucm_event_process(struct ib_cm_event *evt,
328 } 330 }
329 331
330 if (uvt->data_len) { 332 if (uvt->data_len) {
331 uvt->data = kmalloc(uvt->data_len, GFP_KERNEL); 333 uvt->data = kmemdup(evt->private_data, uvt->data_len, GFP_KERNEL);
332 if (!uvt->data) 334 if (!uvt->data)
333 goto err1; 335 goto err1;
334 336
335 memcpy(uvt->data, evt->private_data, uvt->data_len);
336 uvt->resp.present |= IB_UCM_PRES_DATA; 337 uvt->resp.present |= IB_UCM_PRES_DATA;
337 } 338 }
338 339
339 if (uvt->info_len) { 340 if (uvt->info_len) {
340 uvt->info = kmalloc(uvt->info_len, GFP_KERNEL); 341 uvt->info = kmemdup(info, uvt->info_len, GFP_KERNEL);
341 if (!uvt->info) 342 if (!uvt->info)
342 goto err2; 343 goto err2;
343 344
344 memcpy(uvt->info, info, uvt->info_len);
345 uvt->resp.present |= IB_UCM_PRES_INFO; 345 uvt->resp.present |= IB_UCM_PRES_INFO;
346 } 346 }
347 return 0; 347 return 0;
@@ -685,11 +685,11 @@ out:
685 return result; 685 return result;
686} 686}
687 687
688static ssize_t ib_ucm_establish(struct ib_ucm_file *file, 688static ssize_t ib_ucm_notify(struct ib_ucm_file *file,
689 const char __user *inbuf, 689 const char __user *inbuf,
690 int in_len, int out_len) 690 int in_len, int out_len)
691{ 691{
692 struct ib_ucm_establish cmd; 692 struct ib_ucm_notify cmd;
693 struct ib_ucm_context *ctx; 693 struct ib_ucm_context *ctx;
694 int result; 694 int result;
695 695
@@ -700,7 +700,7 @@ static ssize_t ib_ucm_establish(struct ib_ucm_file *file,
700 if (IS_ERR(ctx)) 700 if (IS_ERR(ctx))
701 return PTR_ERR(ctx); 701 return PTR_ERR(ctx);
702 702
703 result = ib_cm_establish(ctx->cm_id); 703 result = ib_cm_notify(ctx->cm_id, (enum ib_event_type) cmd.event);
704 ib_ucm_ctx_put(ctx); 704 ib_ucm_ctx_put(ctx);
705 return result; 705 return result;
706} 706}
@@ -1107,7 +1107,7 @@ static ssize_t (*ucm_cmd_table[])(struct ib_ucm_file *file,
1107 [IB_USER_CM_CMD_DESTROY_ID] = ib_ucm_destroy_id, 1107 [IB_USER_CM_CMD_DESTROY_ID] = ib_ucm_destroy_id,
1108 [IB_USER_CM_CMD_ATTR_ID] = ib_ucm_attr_id, 1108 [IB_USER_CM_CMD_ATTR_ID] = ib_ucm_attr_id,
1109 [IB_USER_CM_CMD_LISTEN] = ib_ucm_listen, 1109 [IB_USER_CM_CMD_LISTEN] = ib_ucm_listen,
1110 [IB_USER_CM_CMD_ESTABLISH] = ib_ucm_establish, 1110 [IB_USER_CM_CMD_NOTIFY] = ib_ucm_notify,
1111 [IB_USER_CM_CMD_SEND_REQ] = ib_ucm_send_req, 1111 [IB_USER_CM_CMD_SEND_REQ] = ib_ucm_send_req,
1112 [IB_USER_CM_CMD_SEND_REP] = ib_ucm_send_rep, 1112 [IB_USER_CM_CMD_SEND_REP] = ib_ucm_send_rep,
1113 [IB_USER_CM_CMD_SEND_RTU] = ib_ucm_send_rtu, 1113 [IB_USER_CM_CMD_SEND_RTU] = ib_ucm_send_rtu,
diff --git a/drivers/infiniband/hw/amso1100/c2.h b/drivers/infiniband/hw/amso1100/c2.h
index 1b17dcdd0505..04a9db5de881 100644
--- a/drivers/infiniband/hw/amso1100/c2.h
+++ b/drivers/infiniband/hw/amso1100/c2.h
@@ -302,7 +302,7 @@ struct c2_dev {
302 unsigned long pa; /* PA device memory */ 302 unsigned long pa; /* PA device memory */
303 void **qptr_array; 303 void **qptr_array;
304 304
305 kmem_cache_t *host_msg_cache; 305 struct kmem_cache *host_msg_cache;
306 306
307 struct list_head cca_link; /* adapter list */ 307 struct list_head cca_link; /* adapter list */
308 struct list_head eh_wakeup_list; /* event wakeup list */ 308 struct list_head eh_wakeup_list; /* event wakeup list */
diff --git a/drivers/infiniband/hw/amso1100/c2_qp.c b/drivers/infiniband/hw/amso1100/c2_qp.c
index 5bcf697aa335..179d005ed4a5 100644
--- a/drivers/infiniband/hw/amso1100/c2_qp.c
+++ b/drivers/infiniband/hw/amso1100/c2_qp.c
@@ -564,6 +564,32 @@ int c2_alloc_qp(struct c2_dev *c2dev,
564 return err; 564 return err;
565} 565}
566 566
567static inline void c2_lock_cqs(struct c2_cq *send_cq, struct c2_cq *recv_cq)
568{
569 if (send_cq == recv_cq)
570 spin_lock_irq(&send_cq->lock);
571 else if (send_cq > recv_cq) {
572 spin_lock_irq(&send_cq->lock);
573 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
574 } else {
575 spin_lock_irq(&recv_cq->lock);
576 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
577 }
578}
579
580static inline void c2_unlock_cqs(struct c2_cq *send_cq, struct c2_cq *recv_cq)
581{
582 if (send_cq == recv_cq)
583 spin_unlock_irq(&send_cq->lock);
584 else if (send_cq > recv_cq) {
585 spin_unlock(&recv_cq->lock);
586 spin_unlock_irq(&send_cq->lock);
587 } else {
588 spin_unlock(&send_cq->lock);
589 spin_unlock_irq(&recv_cq->lock);
590 }
591}
592
567void c2_free_qp(struct c2_dev *c2dev, struct c2_qp *qp) 593void c2_free_qp(struct c2_dev *c2dev, struct c2_qp *qp)
568{ 594{
569 struct c2_cq *send_cq; 595 struct c2_cq *send_cq;
@@ -576,15 +602,9 @@ void c2_free_qp(struct c2_dev *c2dev, struct c2_qp *qp)
576 * Lock CQs here, so that CQ polling code can do QP lookup 602 * Lock CQs here, so that CQ polling code can do QP lookup
577 * without taking a lock. 603 * without taking a lock.
578 */ 604 */
579 spin_lock_irq(&send_cq->lock); 605 c2_lock_cqs(send_cq, recv_cq);
580 if (send_cq != recv_cq)
581 spin_lock(&recv_cq->lock);
582
583 c2_free_qpn(c2dev, qp->qpn); 606 c2_free_qpn(c2dev, qp->qpn);
584 607 c2_unlock_cqs(send_cq, recv_cq);
585 if (send_cq != recv_cq)
586 spin_unlock(&recv_cq->lock);
587 spin_unlock_irq(&send_cq->lock);
588 608
589 /* 609 /*
590 * Destory qp in the rnic... 610 * Destory qp in the rnic...
diff --git a/drivers/infiniband/hw/amso1100/c2_rnic.c b/drivers/infiniband/hw/amso1100/c2_rnic.c
index 623dc95f91df..1687c511cb2f 100644
--- a/drivers/infiniband/hw/amso1100/c2_rnic.c
+++ b/drivers/infiniband/hw/amso1100/c2_rnic.c
@@ -441,7 +441,7 @@ static int c2_rnic_close(struct c2_dev *c2dev)
441 * involves initalizing the various limits and resouce pools that 441 * involves initalizing the various limits and resouce pools that
442 * comprise the RNIC instance. 442 * comprise the RNIC instance.
443 */ 443 */
444int c2_rnic_init(struct c2_dev *c2dev) 444int __devinit c2_rnic_init(struct c2_dev *c2dev)
445{ 445{
446 int err; 446 int err;
447 u32 qsize, msgsize; 447 u32 qsize, msgsize;
@@ -611,7 +611,7 @@ int c2_rnic_init(struct c2_dev *c2dev)
611/* 611/*
612 * Called by c2_remove to cleanup the RNIC resources. 612 * Called by c2_remove to cleanup the RNIC resources.
613 */ 613 */
614void c2_rnic_term(struct c2_dev *c2dev) 614void __devexit c2_rnic_term(struct c2_dev *c2dev)
615{ 615{
616 616
617 /* Close the open adapter instance */ 617 /* Close the open adapter instance */
diff --git a/drivers/infiniband/hw/ehca/ehca_main.c b/drivers/infiniband/hw/ehca/ehca_main.c
index 01f5aa9cb56d..3d1c1c535038 100644
--- a/drivers/infiniband/hw/ehca/ehca_main.c
+++ b/drivers/infiniband/hw/ehca/ehca_main.c
@@ -52,7 +52,7 @@
52MODULE_LICENSE("Dual BSD/GPL"); 52MODULE_LICENSE("Dual BSD/GPL");
53MODULE_AUTHOR("Christoph Raisch <raisch@de.ibm.com>"); 53MODULE_AUTHOR("Christoph Raisch <raisch@de.ibm.com>");
54MODULE_DESCRIPTION("IBM eServer HCA InfiniBand Device Driver"); 54MODULE_DESCRIPTION("IBM eServer HCA InfiniBand Device Driver");
55MODULE_VERSION("SVNEHCA_0018"); 55MODULE_VERSION("SVNEHCA_0019");
56 56
57int ehca_open_aqp1 = 0; 57int ehca_open_aqp1 = 0;
58int ehca_debug_level = 0; 58int ehca_debug_level = 0;
@@ -790,7 +790,7 @@ int __init ehca_module_init(void)
790 int ret; 790 int ret;
791 791
792 printk(KERN_INFO "eHCA Infiniband Device Driver " 792 printk(KERN_INFO "eHCA Infiniband Device Driver "
793 "(Rel.: SVNEHCA_0018)\n"); 793 "(Rel.: SVNEHCA_0019)\n");
794 idr_init(&ehca_qp_idr); 794 idr_init(&ehca_qp_idr);
795 idr_init(&ehca_cq_idr); 795 idr_init(&ehca_cq_idr);
796 spin_lock_init(&ehca_qp_idr_lock); 796 spin_lock_init(&ehca_qp_idr_lock);
diff --git a/drivers/infiniband/hw/ehca/ehca_qp.c b/drivers/infiniband/hw/ehca/ehca_qp.c
index cf3e50ee2d06..8682aa50c707 100644
--- a/drivers/infiniband/hw/ehca/ehca_qp.c
+++ b/drivers/infiniband/hw/ehca/ehca_qp.c
@@ -732,8 +732,7 @@ static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
732 u64 h_ret; 732 u64 h_ret;
733 struct ipz_queue *squeue; 733 struct ipz_queue *squeue;
734 void *bad_send_wqe_p, *bad_send_wqe_v; 734 void *bad_send_wqe_p, *bad_send_wqe_v;
735 void *squeue_start_p, *squeue_end_p; 735 u64 q_ofs;
736 void *squeue_start_v, *squeue_end_v;
737 struct ehca_wqe *wqe; 736 struct ehca_wqe *wqe;
738 int qp_num = my_qp->ib_qp.qp_num; 737 int qp_num = my_qp->ib_qp.qp_num;
739 738
@@ -755,26 +754,23 @@ static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
755 if (ehca_debug_level) 754 if (ehca_debug_level)
756 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num); 755 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
757 squeue = &my_qp->ipz_squeue; 756 squeue = &my_qp->ipz_squeue;
758 squeue_start_p = (void*)virt_to_abs(ipz_qeit_calc(squeue, 0L)); 757 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
759 squeue_end_p = squeue_start_p+squeue->queue_length; 758 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
760 squeue_start_v = abs_to_virt((u64)squeue_start_p); 759 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
761 squeue_end_v = abs_to_virt((u64)squeue_end_p); 760 return -EFAULT;
762 ehca_dbg(&shca->ib_device, "qp_num=%x squeue_start_v=%p squeue_end_v=%p", 761 }
763 qp_num, squeue_start_v, squeue_end_v);
764 762
765 /* loop sets wqe's purge bit */ 763 /* loop sets wqe's purge bit */
766 wqe = (struct ehca_wqe*)bad_send_wqe_v; 764 wqe = (struct ehca_wqe*)ipz_qeit_calc(squeue, q_ofs);
767 *bad_wqe_cnt = 0; 765 *bad_wqe_cnt = 0;
768 while (wqe->optype != 0xff && wqe->wqef != 0xff) { 766 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
769 if (ehca_debug_level) 767 if (ehca_debug_level)
770 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num); 768 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
771 wqe->nr_of_data_seg = 0; /* suppress data access */ 769 wqe->nr_of_data_seg = 0; /* suppress data access */
772 wqe->wqef = WQEF_PURGE; /* WQE to be purged */ 770 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
773 wqe = (struct ehca_wqe*)((u8*)wqe+squeue->qe_size); 771 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
772 wqe = (struct ehca_wqe*)ipz_qeit_calc(squeue, q_ofs);
774 *bad_wqe_cnt = (*bad_wqe_cnt)+1; 773 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
775 if ((void*)wqe >= squeue_end_v) {
776 wqe = squeue_start_v;
777 }
778 } 774 }
779 /* 775 /*
780 * bad wqe will be reprocessed and ignored when pol_cq() is called, 776 * bad wqe will be reprocessed and ignored when pol_cq() is called,
diff --git a/drivers/infiniband/hw/ehca/ipz_pt_fn.c b/drivers/infiniband/hw/ehca/ipz_pt_fn.c
index e028ff1588cc..bf7a40088f61 100644
--- a/drivers/infiniband/hw/ehca/ipz_pt_fn.c
+++ b/drivers/infiniband/hw/ehca/ipz_pt_fn.c
@@ -70,6 +70,19 @@ void *ipz_qeit_eq_get_inc(struct ipz_queue *queue)
70 return ret; 70 return ret;
71} 71}
72 72
73int ipz_queue_abs_to_offset(struct ipz_queue *queue, u64 addr, u64 *q_offset)
74{
75 int i;
76 for (i = 0; i < queue->queue_length / queue->pagesize; i++) {
77 u64 page = (u64)virt_to_abs(queue->queue_pages[i]);
78 if (addr >= page && addr < page + queue->pagesize) {
79 *q_offset = addr - page + i * queue->pagesize;
80 return 0;
81 }
82 }
83 return -EINVAL;
84}
85
73int ipz_queue_ctor(struct ipz_queue *queue, 86int ipz_queue_ctor(struct ipz_queue *queue,
74 const u32 nr_of_pages, 87 const u32 nr_of_pages,
75 const u32 pagesize, const u32 qe_size, const u32 nr_of_sg) 88 const u32 pagesize, const u32 qe_size, const u32 nr_of_sg)
diff --git a/drivers/infiniband/hw/ehca/ipz_pt_fn.h b/drivers/infiniband/hw/ehca/ipz_pt_fn.h
index 2f13509d5257..dc3bda2634b7 100644
--- a/drivers/infiniband/hw/ehca/ipz_pt_fn.h
+++ b/drivers/infiniband/hw/ehca/ipz_pt_fn.h
@@ -150,6 +150,21 @@ static inline void *ipz_qeit_reset(struct ipz_queue *queue)
150 return ipz_qeit_get(queue); 150 return ipz_qeit_get(queue);
151} 151}
152 152
153/*
154 * return the q_offset corresponding to an absolute address
155 */
156int ipz_queue_abs_to_offset(struct ipz_queue *queue, u64 addr, u64 *q_offset);
157
158/*
159 * return the next queue offset. don't modify the queue.
160 */
161static inline u64 ipz_queue_advance_offset(struct ipz_queue *queue, u64 offset)
162{
163 offset += queue->qe_size;
164 if (offset >= queue->queue_length) offset = 0;
165 return offset;
166}
167
153/* struct generic page table */ 168/* struct generic page table */
154struct ipz_pt { 169struct ipz_pt {
155 u64 entries[EHCA_PT_ENTRIES]; 170 u64 entries[EHCA_PT_ENTRIES];
diff --git a/drivers/infiniband/hw/ipath/ipath_verbs.c b/drivers/infiniband/hw/ipath/ipath_verbs.c
index a5456108dbad..acdee33ee1f8 100644
--- a/drivers/infiniband/hw/ipath/ipath_verbs.c
+++ b/drivers/infiniband/hw/ipath/ipath_verbs.c
@@ -1487,7 +1487,7 @@ int ipath_register_ib_device(struct ipath_devdata *dd)
1487 idev->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA; 1487 idev->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1488 idev->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS; 1488 idev->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1489 idev->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS; 1489 idev->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1490 idev->pma_counter_select[5] = IB_PMA_PORT_XMIT_WAIT; 1490 idev->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1491 idev->link_width_enabled = 3; /* 1x or 4x */ 1491 idev->link_width_enabled = 3; /* 1x or 4x */
1492 1492
1493 /* Snapshot current HW counters to "clear" them. */ 1493 /* Snapshot current HW counters to "clear" them. */
diff --git a/drivers/infiniband/hw/mthca/mthca_av.c b/drivers/infiniband/hw/mthca/mthca_av.c
index 69599455aca2..57cdc1bc5f50 100644
--- a/drivers/infiniband/hw/mthca/mthca_av.c
+++ b/drivers/infiniband/hw/mthca/mthca_av.c
@@ -33,7 +33,6 @@
33 * $Id: mthca_av.c 1349 2004-12-16 21:09:43Z roland $ 33 * $Id: mthca_av.c 1349 2004-12-16 21:09:43Z roland $
34 */ 34 */
35 35
36#include <linux/init.h>
37#include <linux/string.h> 36#include <linux/string.h>
38#include <linux/slab.h> 37#include <linux/slab.h>
39 38
@@ -323,7 +322,7 @@ int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr)
323 return 0; 322 return 0;
324} 323}
325 324
326int __devinit mthca_init_av_table(struct mthca_dev *dev) 325int mthca_init_av_table(struct mthca_dev *dev)
327{ 326{
328 int err; 327 int err;
329 328
diff --git a/drivers/infiniband/hw/mthca/mthca_cq.c b/drivers/infiniband/hw/mthca/mthca_cq.c
index 149b36901239..283d50b76c3d 100644
--- a/drivers/infiniband/hw/mthca/mthca_cq.c
+++ b/drivers/infiniband/hw/mthca/mthca_cq.c
@@ -36,7 +36,6 @@
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $ 36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37 */ 37 */
38 38
39#include <linux/init.h>
40#include <linux/hardirq.h> 39#include <linux/hardirq.h>
41 40
42#include <asm/io.h> 41#include <asm/io.h>
@@ -970,7 +969,7 @@ void mthca_free_cq(struct mthca_dev *dev,
970 mthca_free_mailbox(dev, mailbox); 969 mthca_free_mailbox(dev, mailbox);
971} 970}
972 971
973int __devinit mthca_init_cq_table(struct mthca_dev *dev) 972int mthca_init_cq_table(struct mthca_dev *dev)
974{ 973{
975 int err; 974 int err;
976 975
diff --git a/drivers/infiniband/hw/mthca/mthca_eq.c b/drivers/infiniband/hw/mthca/mthca_eq.c
index e284e0613a94..8ec9fa1ff9ea 100644
--- a/drivers/infiniband/hw/mthca/mthca_eq.c
+++ b/drivers/infiniband/hw/mthca/mthca_eq.c
@@ -33,7 +33,6 @@
33 * $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $ 33 * $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $
34 */ 34 */
35 35
36#include <linux/init.h>
37#include <linux/errno.h> 36#include <linux/errno.h>
38#include <linux/interrupt.h> 37#include <linux/interrupt.h>
39#include <linux/pci.h> 38#include <linux/pci.h>
@@ -479,10 +478,10 @@ static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr)
479 return IRQ_HANDLED; 478 return IRQ_HANDLED;
480} 479}
481 480
482static int __devinit mthca_create_eq(struct mthca_dev *dev, 481static int mthca_create_eq(struct mthca_dev *dev,
483 int nent, 482 int nent,
484 u8 intr, 483 u8 intr,
485 struct mthca_eq *eq) 484 struct mthca_eq *eq)
486{ 485{
487 int npages; 486 int npages;
488 u64 *dma_list = NULL; 487 u64 *dma_list = NULL;
@@ -664,9 +663,9 @@ static void mthca_free_irqs(struct mthca_dev *dev)
664 dev->eq_table.eq + i); 663 dev->eq_table.eq + i);
665} 664}
666 665
667static int __devinit mthca_map_reg(struct mthca_dev *dev, 666static int mthca_map_reg(struct mthca_dev *dev,
668 unsigned long offset, unsigned long size, 667 unsigned long offset, unsigned long size,
669 void __iomem **map) 668 void __iomem **map)
670{ 669{
671 unsigned long base = pci_resource_start(dev->pdev, 0); 670 unsigned long base = pci_resource_start(dev->pdev, 0);
672 671
@@ -691,7 +690,7 @@ static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset,
691 iounmap(map); 690 iounmap(map);
692} 691}
693 692
694static int __devinit mthca_map_eq_regs(struct mthca_dev *dev) 693static int mthca_map_eq_regs(struct mthca_dev *dev)
695{ 694{
696 if (mthca_is_memfree(dev)) { 695 if (mthca_is_memfree(dev)) {
697 /* 696 /*
@@ -781,7 +780,7 @@ static void mthca_unmap_eq_regs(struct mthca_dev *dev)
781 } 780 }
782} 781}
783 782
784int __devinit mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt) 783int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
785{ 784{
786 int ret; 785 int ret;
787 u8 status; 786 u8 status;
@@ -825,7 +824,7 @@ void mthca_unmap_eq_icm(struct mthca_dev *dev)
825 __free_page(dev->eq_table.icm_page); 824 __free_page(dev->eq_table.icm_page);
826} 825}
827 826
828int __devinit mthca_init_eq_table(struct mthca_dev *dev) 827int mthca_init_eq_table(struct mthca_dev *dev)
829{ 828{
830 int err; 829 int err;
831 u8 status; 830 u8 status;
diff --git a/drivers/infiniband/hw/mthca/mthca_mad.c b/drivers/infiniband/hw/mthca/mthca_mad.c
index 45e106f14807..acfa41d968ee 100644
--- a/drivers/infiniband/hw/mthca/mthca_mad.c
+++ b/drivers/infiniband/hw/mthca/mthca_mad.c
@@ -317,7 +317,7 @@ err:
317 return ret; 317 return ret;
318} 318}
319 319
320void __devexit mthca_free_agents(struct mthca_dev *dev) 320void mthca_free_agents(struct mthca_dev *dev)
321{ 321{
322 struct ib_mad_agent *agent; 322 struct ib_mad_agent *agent;
323 int p, q; 323 int p, q;
diff --git a/drivers/infiniband/hw/mthca/mthca_main.c b/drivers/infiniband/hw/mthca/mthca_main.c
index 47ea02148368..0491ec7a7c0a 100644
--- a/drivers/infiniband/hw/mthca/mthca_main.c
+++ b/drivers/infiniband/hw/mthca/mthca_main.c
@@ -98,7 +98,7 @@ static struct mthca_profile default_profile = {
98 .uarc_size = 1 << 18, /* Arbel only */ 98 .uarc_size = 1 << 18, /* Arbel only */
99}; 99};
100 100
101static int __devinit mthca_tune_pci(struct mthca_dev *mdev) 101static int mthca_tune_pci(struct mthca_dev *mdev)
102{ 102{
103 int cap; 103 int cap;
104 u16 val; 104 u16 val;
@@ -143,7 +143,7 @@ static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
143 return 0; 143 return 0;
144} 144}
145 145
146static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim) 146static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
147{ 147{
148 int err; 148 int err;
149 u8 status; 149 u8 status;
@@ -255,7 +255,7 @@ static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim
255 return 0; 255 return 0;
256} 256}
257 257
258static int __devinit mthca_init_tavor(struct mthca_dev *mdev) 258static int mthca_init_tavor(struct mthca_dev *mdev)
259{ 259{
260 u8 status; 260 u8 status;
261 int err; 261 int err;
@@ -333,7 +333,7 @@ err_disable:
333 return err; 333 return err;
334} 334}
335 335
336static int __devinit mthca_load_fw(struct mthca_dev *mdev) 336static int mthca_load_fw(struct mthca_dev *mdev)
337{ 337{
338 u8 status; 338 u8 status;
339 int err; 339 int err;
@@ -379,10 +379,10 @@ err_free:
379 return err; 379 return err;
380} 380}
381 381
382static int __devinit mthca_init_icm(struct mthca_dev *mdev, 382static int mthca_init_icm(struct mthca_dev *mdev,
383 struct mthca_dev_lim *dev_lim, 383 struct mthca_dev_lim *dev_lim,
384 struct mthca_init_hca_param *init_hca, 384 struct mthca_init_hca_param *init_hca,
385 u64 icm_size) 385 u64 icm_size)
386{ 386{
387 u64 aux_pages; 387 u64 aux_pages;
388 u8 status; 388 u8 status;
@@ -575,7 +575,7 @@ static void mthca_free_icms(struct mthca_dev *mdev)
575 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm); 575 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
576} 576}
577 577
578static int __devinit mthca_init_arbel(struct mthca_dev *mdev) 578static int mthca_init_arbel(struct mthca_dev *mdev)
579{ 579{
580 struct mthca_dev_lim dev_lim; 580 struct mthca_dev_lim dev_lim;
581 struct mthca_profile profile; 581 struct mthca_profile profile;
@@ -683,7 +683,7 @@ static void mthca_close_hca(struct mthca_dev *mdev)
683 mthca_SYS_DIS(mdev, &status); 683 mthca_SYS_DIS(mdev, &status);
684} 684}
685 685
686static int __devinit mthca_init_hca(struct mthca_dev *mdev) 686static int mthca_init_hca(struct mthca_dev *mdev)
687{ 687{
688 u8 status; 688 u8 status;
689 int err; 689 int err;
@@ -720,7 +720,7 @@ err_close:
720 return err; 720 return err;
721} 721}
722 722
723static int __devinit mthca_setup_hca(struct mthca_dev *dev) 723static int mthca_setup_hca(struct mthca_dev *dev)
724{ 724{
725 int err; 725 int err;
726 u8 status; 726 u8 status;
@@ -875,8 +875,7 @@ err_uar_table_free:
875 return err; 875 return err;
876} 876}
877 877
878static int __devinit mthca_request_regions(struct pci_dev *pdev, 878static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
879 int ddr_hidden)
880{ 879{
881 int err; 880 int err;
882 881
@@ -928,7 +927,7 @@ static void mthca_release_regions(struct pci_dev *pdev,
928 MTHCA_HCR_SIZE); 927 MTHCA_HCR_SIZE);
929} 928}
930 929
931static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev) 930static int mthca_enable_msi_x(struct mthca_dev *mdev)
932{ 931{
933 struct msix_entry entries[3]; 932 struct msix_entry entries[3];
934 int err; 933 int err;
@@ -1213,7 +1212,7 @@ int __mthca_restart_one(struct pci_dev *pdev)
1213} 1212}
1214 1213
1215static int __devinit mthca_init_one(struct pci_dev *pdev, 1214static int __devinit mthca_init_one(struct pci_dev *pdev,
1216 const struct pci_device_id *id) 1215 const struct pci_device_id *id)
1217{ 1216{
1218 static int mthca_version_printed = 0; 1217 static int mthca_version_printed = 0;
1219 int ret; 1218 int ret;
diff --git a/drivers/infiniband/hw/mthca/mthca_mcg.c b/drivers/infiniband/hw/mthca/mthca_mcg.c
index 47ca8a9b7247..a8ad072be074 100644
--- a/drivers/infiniband/hw/mthca/mthca_mcg.c
+++ b/drivers/infiniband/hw/mthca/mthca_mcg.c
@@ -32,7 +32,6 @@
32 * $Id: mthca_mcg.c 1349 2004-12-16 21:09:43Z roland $ 32 * $Id: mthca_mcg.c 1349 2004-12-16 21:09:43Z roland $
33 */ 33 */
34 34
35#include <linux/init.h>
36#include <linux/string.h> 35#include <linux/string.h>
37#include <linux/slab.h> 36#include <linux/slab.h>
38 37
@@ -371,7 +370,7 @@ int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
371 return err; 370 return err;
372} 371}
373 372
374int __devinit mthca_init_mcg_table(struct mthca_dev *dev) 373int mthca_init_mcg_table(struct mthca_dev *dev)
375{ 374{
376 int err; 375 int err;
377 int table_size = dev->limits.num_mgms + dev->limits.num_amgms; 376 int table_size = dev->limits.num_mgms + dev->limits.num_amgms;
diff --git a/drivers/infiniband/hw/mthca/mthca_mr.c b/drivers/infiniband/hw/mthca/mthca_mr.c
index a486dec1707e..f71ffa88db3a 100644
--- a/drivers/infiniband/hw/mthca/mthca_mr.c
+++ b/drivers/infiniband/hw/mthca/mthca_mr.c
@@ -34,7 +34,6 @@
34 */ 34 */
35 35
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/init.h>
38#include <linux/errno.h> 37#include <linux/errno.h>
39 38
40#include "mthca_dev.h" 39#include "mthca_dev.h"
@@ -135,7 +134,7 @@ static void mthca_buddy_free(struct mthca_buddy *buddy, u32 seg, int order)
135 spin_unlock(&buddy->lock); 134 spin_unlock(&buddy->lock);
136} 135}
137 136
138static int __devinit mthca_buddy_init(struct mthca_buddy *buddy, int max_order) 137static int mthca_buddy_init(struct mthca_buddy *buddy, int max_order)
139{ 138{
140 int i, s; 139 int i, s;
141 140
@@ -759,7 +758,7 @@ void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
759 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW; 758 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
760} 759}
761 760
762int __devinit mthca_init_mr_table(struct mthca_dev *dev) 761int mthca_init_mr_table(struct mthca_dev *dev)
763{ 762{
764 unsigned long addr; 763 unsigned long addr;
765 int err, i; 764 int err, i;
diff --git a/drivers/infiniband/hw/mthca/mthca_pd.c b/drivers/infiniband/hw/mthca/mthca_pd.c
index 59df51614c85..c1e950764bd8 100644
--- a/drivers/infiniband/hw/mthca/mthca_pd.c
+++ b/drivers/infiniband/hw/mthca/mthca_pd.c
@@ -34,7 +34,6 @@
34 * $Id: mthca_pd.c 1349 2004-12-16 21:09:43Z roland $ 34 * $Id: mthca_pd.c 1349 2004-12-16 21:09:43Z roland $
35 */ 35 */
36 36
37#include <linux/init.h>
38#include <linux/errno.h> 37#include <linux/errno.h>
39 38
40#include "mthca_dev.h" 39#include "mthca_dev.h"
@@ -69,7 +68,7 @@ void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd)
69 mthca_free(&dev->pd_table.alloc, pd->pd_num); 68 mthca_free(&dev->pd_table.alloc, pd->pd_num);
70} 69}
71 70
72int __devinit mthca_init_pd_table(struct mthca_dev *dev) 71int mthca_init_pd_table(struct mthca_dev *dev)
73{ 72{
74 return mthca_alloc_init(&dev->pd_table.alloc, 73 return mthca_alloc_init(&dev->pd_table.alloc,
75 dev->limits.num_pds, 74 dev->limits.num_pds,
diff --git a/drivers/infiniband/hw/mthca/mthca_provider.c b/drivers/infiniband/hw/mthca/mthca_provider.c
index fc67f780581b..21422a3336ad 100644
--- a/drivers/infiniband/hw/mthca/mthca_provider.c
+++ b/drivers/infiniband/hw/mthca/mthca_provider.c
@@ -1100,11 +1100,10 @@ static struct ib_fmr *mthca_alloc_fmr(struct ib_pd *pd, int mr_access_flags,
1100 struct mthca_fmr *fmr; 1100 struct mthca_fmr *fmr;
1101 int err; 1101 int err;
1102 1102
1103 fmr = kmalloc(sizeof *fmr, GFP_KERNEL); 1103 fmr = kmemdup(fmr_attr, sizeof *fmr, GFP_KERNEL);
1104 if (!fmr) 1104 if (!fmr)
1105 return ERR_PTR(-ENOMEM); 1105 return ERR_PTR(-ENOMEM);
1106 1106
1107 memcpy(&fmr->attr, fmr_attr, sizeof *fmr_attr);
1108 err = mthca_fmr_alloc(to_mdev(pd->device), to_mpd(pd)->pd_num, 1107 err = mthca_fmr_alloc(to_mdev(pd->device), to_mpd(pd)->pd_num,
1109 convert_access(mr_access_flags), fmr); 1108 convert_access(mr_access_flags), fmr);
1110 1109
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c
index 6a7822e0fc19..33e3ba7937f1 100644
--- a/drivers/infiniband/hw/mthca/mthca_qp.c
+++ b/drivers/infiniband/hw/mthca/mthca_qp.c
@@ -35,7 +35,6 @@
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $ 35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */ 36 */
37 37
38#include <linux/init.h>
39#include <linux/string.h> 38#include <linux/string.h>
40#include <linux/slab.h> 39#include <linux/slab.h>
41 40
@@ -2241,7 +2240,7 @@ void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2241 *new_wqe = 0; 2240 *new_wqe = 0;
2242} 2241}
2243 2242
2244int __devinit mthca_init_qp_table(struct mthca_dev *dev) 2243int mthca_init_qp_table(struct mthca_dev *dev)
2245{ 2244{
2246 int err; 2245 int err;
2247 u8 status; 2246 u8 status;
diff --git a/drivers/infiniband/hw/mthca/mthca_srq.c b/drivers/infiniband/hw/mthca/mthca_srq.c
index f5d7677d1079..34d2c4768962 100644
--- a/drivers/infiniband/hw/mthca/mthca_srq.c
+++ b/drivers/infiniband/hw/mthca/mthca_srq.c
@@ -120,7 +120,7 @@ static void mthca_arbel_init_srq_context(struct mthca_dev *dev,
120 120
121 memset(context, 0, sizeof *context); 121 memset(context, 0, sizeof *context);
122 122
123 logsize = long_log2(srq->max) + srq->wqe_shift; 123 logsize = long_log2(srq->max);
124 context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn); 124 context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn);
125 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); 125 context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
126 context->db_index = cpu_to_be32(srq->db_index); 126 context->db_index = cpu_to_be32(srq->db_index);
@@ -715,7 +715,7 @@ int mthca_max_srq_sge(struct mthca_dev *dev)
715 sizeof (struct mthca_data_seg)); 715 sizeof (struct mthca_data_seg));
716} 716}
717 717
718int __devinit mthca_init_srq_table(struct mthca_dev *dev) 718int mthca_init_srq_table(struct mthca_dev *dev)
719{ 719{
720 int err; 720 int err;
721 721
diff --git a/drivers/infiniband/ulp/ipoib/ipoib.h b/drivers/infiniband/ulp/ipoib/ipoib.h
index 3b2ee0eba05e..99547996aba2 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib.h
+++ b/drivers/infiniband/ulp/ipoib/ipoib.h
@@ -233,7 +233,7 @@ static inline struct ipoib_neigh **to_ipoib_neigh(struct neighbour *neigh)
233} 233}
234 234
235struct ipoib_neigh *ipoib_neigh_alloc(struct neighbour *neigh); 235struct ipoib_neigh *ipoib_neigh_alloc(struct neighbour *neigh);
236void ipoib_neigh_free(struct ipoib_neigh *neigh); 236void ipoib_neigh_free(struct net_device *dev, struct ipoib_neigh *neigh);
237 237
238extern struct workqueue_struct *ipoib_workqueue; 238extern struct workqueue_struct *ipoib_workqueue;
239 239
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
index 71114a8c12b9..c09280243726 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
@@ -264,7 +264,7 @@ static void path_free(struct net_device *dev, struct ipoib_path *path)
264 if (neigh->ah) 264 if (neigh->ah)
265 ipoib_put_ah(neigh->ah); 265 ipoib_put_ah(neigh->ah);
266 266
267 ipoib_neigh_free(neigh); 267 ipoib_neigh_free(dev, neigh);
268 } 268 }
269 269
270 spin_unlock_irqrestore(&priv->lock, flags); 270 spin_unlock_irqrestore(&priv->lock, flags);
@@ -525,10 +525,11 @@ static void neigh_add_path(struct sk_buff *skb, struct net_device *dev)
525 ipoib_send(dev, skb, path->ah, IPOIB_QPN(skb->dst->neighbour->ha)); 525 ipoib_send(dev, skb, path->ah, IPOIB_QPN(skb->dst->neighbour->ha));
526 } else { 526 } else {
527 neigh->ah = NULL; 527 neigh->ah = NULL;
528 __skb_queue_tail(&neigh->queue, skb);
529 528
530 if (!path->query && path_rec_start(dev, path)) 529 if (!path->query && path_rec_start(dev, path))
531 goto err_list; 530 goto err_list;
531
532 __skb_queue_tail(&neigh->queue, skb);
532 } 533 }
533 534
534 spin_unlock(&priv->lock); 535 spin_unlock(&priv->lock);
@@ -538,7 +539,7 @@ err_list:
538 list_del(&neigh->list); 539 list_del(&neigh->list);
539 540
540err_path: 541err_path:
541 ipoib_neigh_free(neigh); 542 ipoib_neigh_free(dev, neigh);
542 ++priv->stats.tx_dropped; 543 ++priv->stats.tx_dropped;
543 dev_kfree_skb_any(skb); 544 dev_kfree_skb_any(skb);
544 545
@@ -655,7 +656,7 @@ static int ipoib_start_xmit(struct sk_buff *skb, struct net_device *dev)
655 */ 656 */
656 ipoib_put_ah(neigh->ah); 657 ipoib_put_ah(neigh->ah);
657 list_del(&neigh->list); 658 list_del(&neigh->list);
658 ipoib_neigh_free(neigh); 659 ipoib_neigh_free(dev, neigh);
659 spin_unlock(&priv->lock); 660 spin_unlock(&priv->lock);
660 ipoib_path_lookup(skb, dev); 661 ipoib_path_lookup(skb, dev);
661 goto out; 662 goto out;
@@ -786,7 +787,7 @@ static void ipoib_neigh_destructor(struct neighbour *n)
786 if (neigh->ah) 787 if (neigh->ah)
787 ah = neigh->ah; 788 ah = neigh->ah;
788 list_del(&neigh->list); 789 list_del(&neigh->list);
789 ipoib_neigh_free(neigh); 790 ipoib_neigh_free(n->dev, neigh);
790 } 791 }
791 792
792 spin_unlock_irqrestore(&priv->lock, flags); 793 spin_unlock_irqrestore(&priv->lock, flags);
@@ -809,9 +810,15 @@ struct ipoib_neigh *ipoib_neigh_alloc(struct neighbour *neighbour)
809 return neigh; 810 return neigh;
810} 811}
811 812
812void ipoib_neigh_free(struct ipoib_neigh *neigh) 813void ipoib_neigh_free(struct net_device *dev, struct ipoib_neigh *neigh)
813{ 814{
815 struct ipoib_dev_priv *priv = netdev_priv(dev);
816 struct sk_buff *skb;
814 *to_ipoib_neigh(neigh->neighbour) = NULL; 817 *to_ipoib_neigh(neigh->neighbour) = NULL;
818 while ((skb = __skb_dequeue(&neigh->queue))) {
819 ++priv->stats.tx_dropped;
820 dev_kfree_skb_any(skb);
821 }
815 kfree(neigh); 822 kfree(neigh);
816} 823}
817 824
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c
index f0a4fac1a215..b04b72ca32ed 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c
@@ -114,7 +114,7 @@ static void ipoib_mcast_free(struct ipoib_mcast *mcast)
114 */ 114 */
115 if (neigh->ah) 115 if (neigh->ah)
116 ipoib_put_ah(neigh->ah); 116 ipoib_put_ah(neigh->ah);
117 ipoib_neigh_free(neigh); 117 ipoib_neigh_free(dev, neigh);
118 } 118 }
119 119
120 spin_unlock_irqrestore(&priv->lock, flags); 120 spin_unlock_irqrestore(&priv->lock, flags);
diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.h b/drivers/infiniband/ulp/iser/iscsi_iser.h
index 9c53916f28c2..234e5b061a75 100644
--- a/drivers/infiniband/ulp/iser/iscsi_iser.h
+++ b/drivers/infiniband/ulp/iser/iscsi_iser.h
@@ -283,7 +283,7 @@ struct iser_global {
283 struct mutex connlist_mutex; 283 struct mutex connlist_mutex;
284 struct list_head connlist; /* all iSER IB connections */ 284 struct list_head connlist; /* all iSER IB connections */
285 285
286 kmem_cache_t *desc_cache; 286 struct kmem_cache *desc_cache;
287}; 287};
288 288
289extern struct iser_global ig; 289extern struct iser_global ig;
diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
index 214f66195af2..a6289595557b 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.c
+++ b/drivers/infiniband/ulp/srp/ib_srp.c
@@ -1177,9 +1177,11 @@ static int srp_cm_handler(struct ib_cm_id *cm_id, struct ib_cm_event *event)
1177 break; 1177 break;
1178 } 1178 }
1179 1179
1180 target->status = srp_alloc_iu_bufs(target); 1180 if (!target->rx_ring[0]) {
1181 if (target->status) 1181 target->status = srp_alloc_iu_bufs(target);
1182 break; 1182 if (target->status)
1183 break;
1184 }
1183 1185
1184 qp_attr = kmalloc(sizeof *qp_attr, GFP_KERNEL); 1186 qp_attr = kmalloc(sizeof *qp_attr, GFP_KERNEL);
1185 if (!qp_attr) { 1187 if (!qp_attr) {
@@ -1717,7 +1719,8 @@ static ssize_t srp_create_target(struct class_device *class_dev,
1717 if (!target_host) 1719 if (!target_host)
1718 return -ENOMEM; 1720 return -ENOMEM;
1719 1721
1720 target_host->max_lun = SRP_MAX_LUN; 1722 target_host->max_lun = SRP_MAX_LUN;
1723 target_host->max_cmd_len = sizeof ((struct srp_cmd *) (void *) 0L)->cdb;
1721 1724
1722 target = host_to_target(target_host); 1725 target = host_to_target(target_host);
1723 1726
diff --git a/drivers/input/joystick/iforce/iforce-usb.c b/drivers/input/joystick/iforce/iforce-usb.c
index 105112fb7b57..80cdebcbcb99 100644
--- a/drivers/input/joystick/iforce/iforce-usb.c
+++ b/drivers/input/joystick/iforce/iforce-usb.c
@@ -178,9 +178,9 @@ static int iforce_usb_probe(struct usb_interface *intf,
178 178
179fail: 179fail:
180 if (iforce) { 180 if (iforce) {
181 if (iforce->irq) usb_free_urb(iforce->irq); 181 usb_free_urb(iforce->irq);
182 if (iforce->out) usb_free_urb(iforce->out); 182 usb_free_urb(iforce->out);
183 if (iforce->ctrl) usb_free_urb(iforce->ctrl); 183 usb_free_urb(iforce->ctrl);
184 kfree(iforce); 184 kfree(iforce);
185 } 185 }
186 186
diff --git a/drivers/input/serio/serio_raw.c b/drivers/input/serio/serio_raw.c
index ba2a2035d648..7c8d0399ae82 100644
--- a/drivers/input/serio/serio_raw.c
+++ b/drivers/input/serio/serio_raw.c
@@ -297,7 +297,7 @@ static int serio_raw_connect(struct serio *serio, struct serio_driver *drv)
297 297
298 serio_raw->dev.minor = PSMOUSE_MINOR; 298 serio_raw->dev.minor = PSMOUSE_MINOR;
299 serio_raw->dev.name = serio_raw->name; 299 serio_raw->dev.name = serio_raw->name;
300 serio_raw->dev.dev = &serio->dev; 300 serio_raw->dev.parent = &serio->dev;
301 serio_raw->dev.fops = &serio_raw_fops; 301 serio_raw->dev.fops = &serio_raw_fops;
302 302
303 err = misc_register(&serio_raw->dev); 303 err = misc_register(&serio_raw->dev);
diff --git a/drivers/isdn/gigaset/common.c b/drivers/isdn/gigaset/common.c
index 5800beeebb85..defd5743dba6 100644
--- a/drivers/isdn/gigaset/common.c
+++ b/drivers/isdn/gigaset/common.c
@@ -702,7 +702,7 @@ struct cardstate *gigaset_initcs(struct gigaset_driver *drv, int channels,
702 cs->open_count = 0; 702 cs->open_count = 0;
703 cs->dev = NULL; 703 cs->dev = NULL;
704 cs->tty = NULL; 704 cs->tty = NULL;
705 cs->class = NULL; 705 cs->tty_dev = NULL;
706 cs->cidmode = cidmode != 0; 706 cs->cidmode = cidmode != 0;
707 707
708 //if(onechannel) { //FIXME 708 //if(onechannel) { //FIXME
diff --git a/drivers/isdn/gigaset/gigaset.h b/drivers/isdn/gigaset/gigaset.h
index 884bd72c1bf4..06298cc52bf5 100644
--- a/drivers/isdn/gigaset/gigaset.h
+++ b/drivers/isdn/gigaset/gigaset.h
@@ -444,7 +444,7 @@ struct cardstate {
444 struct gigaset_driver *driver; 444 struct gigaset_driver *driver;
445 unsigned minor_index; 445 unsigned minor_index;
446 struct device *dev; 446 struct device *dev;
447 struct class_device *class; 447 struct device *tty_dev;
448 448
449 const struct gigaset_ops *ops; 449 const struct gigaset_ops *ops;
450 450
diff --git a/drivers/isdn/gigaset/interface.c b/drivers/isdn/gigaset/interface.c
index 596f3aebe2f7..7edea015867e 100644
--- a/drivers/isdn/gigaset/interface.c
+++ b/drivers/isdn/gigaset/interface.c
@@ -625,13 +625,13 @@ void gigaset_if_init(struct cardstate *cs)
625 return; 625 return;
626 626
627 tasklet_init(&cs->if_wake_tasklet, &if_wake, (unsigned long) cs); 627 tasklet_init(&cs->if_wake_tasklet, &if_wake, (unsigned long) cs);
628 cs->class = tty_register_device(drv->tty, cs->minor_index, NULL); 628 cs->tty_dev = tty_register_device(drv->tty, cs->minor_index, NULL);
629 629
630 if (!IS_ERR(cs->class)) 630 if (!IS_ERR(cs->tty_dev))
631 class_set_devdata(cs->class, cs); 631 dev_set_drvdata(cs->tty_dev, cs);
632 else { 632 else {
633 warn("could not register device to the tty subsystem"); 633 warn("could not register device to the tty subsystem");
634 cs->class = NULL; 634 cs->tty_dev = NULL;
635 } 635 }
636} 636}
637 637
@@ -645,7 +645,7 @@ void gigaset_if_free(struct cardstate *cs)
645 645
646 tasklet_disable(&cs->if_wake_tasklet); 646 tasklet_disable(&cs->if_wake_tasklet);
647 tasklet_kill(&cs->if_wake_tasklet); 647 tasklet_kill(&cs->if_wake_tasklet);
648 cs->class = NULL; 648 cs->tty_dev = NULL;
649 tty_unregister_device(drv->tty, cs->minor_index); 649 tty_unregister_device(drv->tty, cs->minor_index);
650} 650}
651 651
diff --git a/drivers/isdn/gigaset/proc.c b/drivers/isdn/gigaset/proc.c
index 9ad840e95dbe..e767afa55abf 100644
--- a/drivers/isdn/gigaset/proc.c
+++ b/drivers/isdn/gigaset/proc.c
@@ -16,11 +16,12 @@
16#include "gigaset.h" 16#include "gigaset.h"
17#include <linux/ctype.h> 17#include <linux/ctype.h>
18 18
19static ssize_t show_cidmode(struct class_device *class, char *buf) 19static ssize_t show_cidmode(struct device *dev,
20 struct device_attribute *attr, char *buf)
20{ 21{
21 int ret; 22 int ret;
22 unsigned long flags; 23 unsigned long flags;
23 struct cardstate *cs = class_get_devdata(class); 24 struct cardstate *cs = dev_get_drvdata(dev);
24 25
25 spin_lock_irqsave(&cs->lock, flags); 26 spin_lock_irqsave(&cs->lock, flags);
26 ret = sprintf(buf, "%u\n", cs->cidmode); 27 ret = sprintf(buf, "%u\n", cs->cidmode);
@@ -29,10 +30,10 @@ static ssize_t show_cidmode(struct class_device *class, char *buf)
29 return ret; 30 return ret;
30} 31}
31 32
32static ssize_t set_cidmode(struct class_device *class, 33static ssize_t set_cidmode(struct device *dev, struct device_attribute *attr,
33 const char *buf, size_t count) 34 const char *buf, size_t count)
34{ 35{
35 struct cardstate *cs = class_get_devdata(class); 36 struct cardstate *cs = dev_get_drvdata(dev);
36 long int value; 37 long int value;
37 char *end; 38 char *end;
38 39
@@ -64,25 +65,25 @@ static ssize_t set_cidmode(struct class_device *class,
64 return count; 65 return count;
65} 66}
66 67
67static CLASS_DEVICE_ATTR(cidmode, S_IRUGO|S_IWUSR, show_cidmode, set_cidmode); 68static DEVICE_ATTR(cidmode, S_IRUGO|S_IWUSR, show_cidmode, set_cidmode);
68 69
69/* free sysfs for device */ 70/* free sysfs for device */
70void gigaset_free_dev_sysfs(struct cardstate *cs) 71void gigaset_free_dev_sysfs(struct cardstate *cs)
71{ 72{
72 if (!cs->class) 73 if (!cs->tty_dev)
73 return; 74 return;
74 75
75 gig_dbg(DEBUG_INIT, "removing sysfs entries"); 76 gig_dbg(DEBUG_INIT, "removing sysfs entries");
76 class_device_remove_file(cs->class, &class_device_attr_cidmode); 77 device_remove_file(cs->tty_dev, &dev_attr_cidmode);
77} 78}
78 79
79/* initialize sysfs for device */ 80/* initialize sysfs for device */
80void gigaset_init_dev_sysfs(struct cardstate *cs) 81void gigaset_init_dev_sysfs(struct cardstate *cs)
81{ 82{
82 if (!cs->class) 83 if (!cs->tty_dev)
83 return; 84 return;
84 85
85 gig_dbg(DEBUG_INIT, "setting up sysfs"); 86 gig_dbg(DEBUG_INIT, "setting up sysfs");
86 if (class_device_create_file(cs->class, &class_device_attr_cidmode)) 87 if (device_create_file(cs->tty_dev, &dev_attr_cidmode))
87 dev_err(cs->dev, "could not create sysfs attribute\n"); 88 dev_err(cs->dev, "could not create sysfs attribute\n");
88} 89}
diff --git a/drivers/isdn/gigaset/usb-gigaset.c b/drivers/isdn/gigaset/usb-gigaset.c
index 4ffa9eb1c28e..5ebf49ac9b23 100644
--- a/drivers/isdn/gigaset/usb-gigaset.c
+++ b/drivers/isdn/gigaset/usb-gigaset.c
@@ -815,14 +815,11 @@ static int gigaset_probe(struct usb_interface *interface,
815 return 0; 815 return 0;
816 816
817error: 817error:
818 if (ucs->read_urb) 818 usb_kill_urb(ucs->read_urb);
819 usb_kill_urb(ucs->read_urb);
820 kfree(ucs->bulk_out_buffer); 819 kfree(ucs->bulk_out_buffer);
821 if (ucs->bulk_out_urb != NULL) 820 usb_free_urb(ucs->bulk_out_urb);
822 usb_free_urb(ucs->bulk_out_urb);
823 kfree(cs->inbuf[0].rcvbuf); 821 kfree(cs->inbuf[0].rcvbuf);
824 if (ucs->read_urb != NULL) 822 usb_free_urb(ucs->read_urb);
825 usb_free_urb(ucs->read_urb);
826 usb_set_intfdata(interface, NULL); 823 usb_set_intfdata(interface, NULL);
827 ucs->read_urb = ucs->bulk_out_urb = NULL; 824 ucs->read_urb = ucs->bulk_out_urb = NULL;
828 cs->inbuf[0].rcvbuf = ucs->bulk_out_buffer = NULL; 825 cs->inbuf[0].rcvbuf = ucs->bulk_out_buffer = NULL;
@@ -850,11 +847,9 @@ static void gigaset_disconnect(struct usb_interface *interface)
850 usb_kill_urb(ucs->bulk_out_urb); /* FIXME: only if active? */ 847 usb_kill_urb(ucs->bulk_out_urb); /* FIXME: only if active? */
851 848
852 kfree(ucs->bulk_out_buffer); 849 kfree(ucs->bulk_out_buffer);
853 if (ucs->bulk_out_urb != NULL) 850 usb_free_urb(ucs->bulk_out_urb);
854 usb_free_urb(ucs->bulk_out_urb);
855 kfree(cs->inbuf[0].rcvbuf); 851 kfree(cs->inbuf[0].rcvbuf);
856 if (ucs->read_urb != NULL) 852 usb_free_urb(ucs->read_urb);
857 usb_free_urb(ucs->read_urb);
858 ucs->read_urb = ucs->bulk_out_urb = NULL; 853 ucs->read_urb = ucs->bulk_out_urb = NULL;
859 cs->inbuf[0].rcvbuf = ucs->bulk_out_buffer = NULL; 854 cs->inbuf[0].rcvbuf = ucs->bulk_out_buffer = NULL;
860 855
diff --git a/drivers/isdn/hardware/eicon/os_4bri.c b/drivers/isdn/hardware/eicon/os_4bri.c
index 11e6f937c1e4..7b4ec3f60dbf 100644
--- a/drivers/isdn/hardware/eicon/os_4bri.c
+++ b/drivers/isdn/hardware/eicon/os_4bri.c
@@ -464,7 +464,7 @@ int diva_4bri_init_card(diva_os_xdi_adapter_t * a)
464 464
465/* 465/*
466** Cleanup function will be called for master adapter only 466** Cleanup function will be called for master adapter only
467** this is garanteed by design: cleanup callback is set 467** this is guaranteed by design: cleanup callback is set
468** by master adapter only 468** by master adapter only
469*/ 469*/
470static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t * a) 470static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t * a)
diff --git a/drivers/isdn/hisax/hfc4s8s_l1.h b/drivers/isdn/hisax/hfc4s8s_l1.h
index e8f9c077fa85..9d5d2a56b4e9 100644
--- a/drivers/isdn/hisax/hfc4s8s_l1.h
+++ b/drivers/isdn/hisax/hfc4s8s_l1.h
@@ -16,7 +16,7 @@
16 16
17/* 17/*
18* include Genero generated HFC-4S/8S header file hfc48scu.h 18* include Genero generated HFC-4S/8S header file hfc48scu.h
19* for comlete register description. This will define _HFC48SCU_H_ 19* for complete register description. This will define _HFC48SCU_H_
20* to prevent redefinitions 20* to prevent redefinitions
21*/ 21*/
22 22
diff --git a/drivers/isdn/hisax/isdnl2.c b/drivers/isdn/hisax/isdnl2.c
index 6d0431725555..cd3b5ad53491 100644
--- a/drivers/isdn/hisax/isdnl2.c
+++ b/drivers/isdn/hisax/isdnl2.c
@@ -1442,7 +1442,7 @@ l2_tei_remove(struct FsmInst *fi, int event, void *arg)
1442} 1442}
1443 1443
1444static void 1444static void
1445l2_st14_persistant_da(struct FsmInst *fi, int event, void *arg) 1445l2_st14_persistent_da(struct FsmInst *fi, int event, void *arg)
1446{ 1446{
1447 struct PStack *st = fi->userdata; 1447 struct PStack *st = fi->userdata;
1448 1448
@@ -1453,7 +1453,7 @@ l2_st14_persistant_da(struct FsmInst *fi, int event, void *arg)
1453} 1453}
1454 1454
1455static void 1455static void
1456l2_st5_persistant_da(struct FsmInst *fi, int event, void *arg) 1456l2_st5_persistent_da(struct FsmInst *fi, int event, void *arg)
1457{ 1457{
1458 struct PStack *st = fi->userdata; 1458 struct PStack *st = fi->userdata;
1459 1459
@@ -1466,7 +1466,7 @@ l2_st5_persistant_da(struct FsmInst *fi, int event, void *arg)
1466} 1466}
1467 1467
1468static void 1468static void
1469l2_st6_persistant_da(struct FsmInst *fi, int event, void *arg) 1469l2_st6_persistent_da(struct FsmInst *fi, int event, void *arg)
1470{ 1470{
1471 struct PStack *st = fi->userdata; 1471 struct PStack *st = fi->userdata;
1472 1472
@@ -1477,7 +1477,7 @@ l2_st6_persistant_da(struct FsmInst *fi, int event, void *arg)
1477} 1477}
1478 1478
1479static void 1479static void
1480l2_persistant_da(struct FsmInst *fi, int event, void *arg) 1480l2_persistent_da(struct FsmInst *fi, int event, void *arg)
1481{ 1481{
1482 struct PStack *st = fi->userdata; 1482 struct PStack *st = fi->userdata;
1483 1483
@@ -1612,14 +1612,14 @@ static struct FsmNode L2FnList[] __initdata =
1612 {ST_L2_6, EV_L2_FRAME_ERROR, l2_frame_error}, 1612 {ST_L2_6, EV_L2_FRAME_ERROR, l2_frame_error},
1613 {ST_L2_7, EV_L2_FRAME_ERROR, l2_frame_error_reest}, 1613 {ST_L2_7, EV_L2_FRAME_ERROR, l2_frame_error_reest},
1614 {ST_L2_8, EV_L2_FRAME_ERROR, l2_frame_error_reest}, 1614 {ST_L2_8, EV_L2_FRAME_ERROR, l2_frame_error_reest},
1615 {ST_L2_1, EV_L1_DEACTIVATE, l2_st14_persistant_da}, 1615 {ST_L2_1, EV_L1_DEACTIVATE, l2_st14_persistent_da},
1616 {ST_L2_2, EV_L1_DEACTIVATE, l2_st24_tei_remove}, 1616 {ST_L2_2, EV_L1_DEACTIVATE, l2_st24_tei_remove},
1617 {ST_L2_3, EV_L1_DEACTIVATE, l2_st3_tei_remove}, 1617 {ST_L2_3, EV_L1_DEACTIVATE, l2_st3_tei_remove},
1618 {ST_L2_4, EV_L1_DEACTIVATE, l2_st14_persistant_da}, 1618 {ST_L2_4, EV_L1_DEACTIVATE, l2_st14_persistent_da},
1619 {ST_L2_5, EV_L1_DEACTIVATE, l2_st5_persistant_da}, 1619 {ST_L2_5, EV_L1_DEACTIVATE, l2_st5_persistent_da},
1620 {ST_L2_6, EV_L1_DEACTIVATE, l2_st6_persistant_da}, 1620 {ST_L2_6, EV_L1_DEACTIVATE, l2_st6_persistent_da},
1621 {ST_L2_7, EV_L1_DEACTIVATE, l2_persistant_da}, 1621 {ST_L2_7, EV_L1_DEACTIVATE, l2_persistent_da},
1622 {ST_L2_8, EV_L1_DEACTIVATE, l2_persistant_da}, 1622 {ST_L2_8, EV_L1_DEACTIVATE, l2_persistent_da},
1623}; 1623};
1624 1624
1625#define L2_FN_COUNT (sizeof(L2FnList)/sizeof(struct FsmNode)) 1625#define L2_FN_COUNT (sizeof(L2FnList)/sizeof(struct FsmNode))
diff --git a/drivers/media/dvb/cinergyT2/cinergyT2.c b/drivers/media/dvb/cinergyT2/cinergyT2.c
index dd0bcbe140bd..8458ff3f351e 100644
--- a/drivers/media/dvb/cinergyT2/cinergyT2.c
+++ b/drivers/media/dvb/cinergyT2/cinergyT2.c
@@ -275,8 +275,7 @@ static void cinergyt2_free_stream_urbs (struct cinergyt2 *cinergyt2)
275 int i; 275 int i;
276 276
277 for (i=0; i<STREAM_URB_COUNT; i++) 277 for (i=0; i<STREAM_URB_COUNT; i++)
278 if (cinergyt2->stream_urb[i]) 278 usb_free_urb(cinergyt2->stream_urb[i]);
279 usb_free_urb(cinergyt2->stream_urb[i]);
280 279
281 usb_buffer_free(cinergyt2->udev, STREAM_URB_COUNT*STREAM_BUF_SIZE, 280 usb_buffer_free(cinergyt2->udev, STREAM_URB_COUNT*STREAM_BUF_SIZE,
282 cinergyt2->streambuf, cinergyt2->streambuf_dmahandle); 281 cinergyt2->streambuf, cinergyt2->streambuf_dmahandle);
@@ -320,8 +319,7 @@ static void cinergyt2_stop_stream_xfer (struct cinergyt2 *cinergyt2)
320 cinergyt2_control_stream_transfer(cinergyt2, 0); 319 cinergyt2_control_stream_transfer(cinergyt2, 0);
321 320
322 for (i=0; i<STREAM_URB_COUNT; i++) 321 for (i=0; i<STREAM_URB_COUNT; i++)
323 if (cinergyt2->stream_urb[i]) 322 usb_kill_urb(cinergyt2->stream_urb[i]);
324 usb_kill_urb(cinergyt2->stream_urb[i]);
325} 323}
326 324
327static int cinergyt2_start_stream_xfer (struct cinergyt2 *cinergyt2) 325static int cinergyt2_start_stream_xfer (struct cinergyt2 *cinergyt2)
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index 53304e6991ac..a2ab2eebfc68 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -348,7 +348,7 @@ static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wra
348 348
349static void dvb_frontend_swzigzag(struct dvb_frontend *fe) 349static void dvb_frontend_swzigzag(struct dvb_frontend *fe)
350{ 350{
351 fe_status_t s; 351 fe_status_t s = 0;
352 struct dvb_frontend_private *fepriv = fe->frontend_priv; 352 struct dvb_frontend_private *fepriv = fe->frontend_priv;
353 353
354 /* if we've got no parameters, just keep idling */ 354 /* if we've got no parameters, just keep idling */
diff --git a/drivers/media/dvb/frontends/tda10086.c b/drivers/media/dvb/frontends/tda10086.c
index 7456b0b9976b..4c27a2d90a38 100644
--- a/drivers/media/dvb/frontends/tda10086.c
+++ b/drivers/media/dvb/frontends/tda10086.c
@@ -441,6 +441,10 @@ static int tda10086_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
441 441
442 dprintk ("%s\n", __FUNCTION__); 442 dprintk ("%s\n", __FUNCTION__);
443 443
444 // check for invalid symbol rate
445 if (fe_params->u.qpsk.symbol_rate < 500000)
446 return -EINVAL;
447
444 // calculate the updated frequency (note: we convert from Hz->kHz) 448 // calculate the updated frequency (note: we convert from Hz->kHz)
445 tmp64 = tda10086_read_byte(state, 0x52); 449 tmp64 = tda10086_read_byte(state, 0x52);
446 tmp64 |= (tda10086_read_byte(state, 0x51) << 8); 450 tmp64 |= (tda10086_read_byte(state, 0x51) << 8);
diff --git a/drivers/media/dvb/ttpci/budget-patch.c b/drivers/media/dvb/ttpci/budget-patch.c
index fc1267b8c892..9a155396d6ac 100644
--- a/drivers/media/dvb/ttpci/budget-patch.c
+++ b/drivers/media/dvb/ttpci/budget-patch.c
@@ -500,14 +500,14 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
500 500
501/* New design (By Emard) 501/* New design (By Emard)
502** this rps1 code will copy internal HS event to GPIO3 pin. 502** this rps1 code will copy internal HS event to GPIO3 pin.
503** GPIO3 is in budget-patch hardware connectd to port B VSYNC 503** GPIO3 is in budget-patch hardware connected to port B VSYNC
504 504
505** HS is an internal event of 7146, accessible with RPS 505** HS is an internal event of 7146, accessible with RPS
506** and temporarily raised high every n lines 506** and temporarily raised high every n lines
507** (n in defined in the RPS_THRESH1 counter threshold) 507** (n in defined in the RPS_THRESH1 counter threshold)
508** I think HS is raised high on the beginning of the n-th line 508** I think HS is raised high on the beginning of the n-th line
509** and remains high until this n-th line that triggered 509** and remains high until this n-th line that triggered
510** it is completely received. When the receiption of n-th line 510** it is completely received. When the reception of n-th line
511** ends, HS is lowered. 511** ends, HS is lowered.
512 512
513** To transmit data over DMA, 7146 needs changing state at 513** To transmit data over DMA, 7146 needs changing state at
@@ -541,7 +541,7 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
541** hardware debug note: a working budget card (including budget patch) 541** hardware debug note: a working budget card (including budget patch)
542** with vpeirq() interrupt setup in mode "0x90" (every 64K) will 542** with vpeirq() interrupt setup in mode "0x90" (every 64K) will
543** generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes 543** generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
544** and that means 3*25=75 Hz of interrupt freqency, as seen by 544** and that means 3*25=75 Hz of interrupt frequency, as seen by
545** watch cat /proc/interrupts 545** watch cat /proc/interrupts
546** 546**
547** If this frequency is 3x lower (and data received in the DMA 547** If this frequency is 3x lower (and data received in the DMA
@@ -550,7 +550,7 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
550** this means VSYNC line is not connected in the hardware. 550** this means VSYNC line is not connected in the hardware.
551** (check soldering pcb and pins) 551** (check soldering pcb and pins)
552** The same behaviour of missing VSYNC can be duplicated on budget 552** The same behaviour of missing VSYNC can be duplicated on budget
553** cards, by seting DD1_INIT trigger mode 7 in 3rd nibble. 553** cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
554*/ 554*/
555 555
556 // Setup RPS1 "program" (p35) 556 // Setup RPS1 "program" (p35)
diff --git a/drivers/media/dvb/ttpci/budget.c b/drivers/media/dvb/ttpci/budget.c
index e58f0391e9d1..56f1c80defc6 100644
--- a/drivers/media/dvb/ttpci/budget.c
+++ b/drivers/media/dvb/ttpci/budget.c
@@ -46,6 +46,10 @@
46#include "lnbp21.h" 46#include "lnbp21.h"
47#include "bsru6.h" 47#include "bsru6.h"
48 48
49static int diseqc_method;
50module_param(diseqc_method, int, 0444);
51MODULE_PARM_DESC(diseqc_method, "Select DiSEqC method for subsystem id 13c2:1003, 0: default, 1: more reliable (for newer revisions only)");
52
49static void Set22K (struct budget *budget, int state) 53static void Set22K (struct budget *budget, int state)
50{ 54{
51 struct saa7146_dev *dev=budget->dev; 55 struct saa7146_dev *dev=budget->dev;
@@ -382,6 +386,11 @@ static void frontend_init(struct budget *budget)
382 if (budget->dvb_frontend) { 386 if (budget->dvb_frontend) {
383 budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; 387 budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
384 budget->dvb_frontend->tuner_priv = &budget->i2c_adap; 388 budget->dvb_frontend->tuner_priv = &budget->i2c_adap;
389 if (budget->dev->pci->subsystem_device == 0x1003 && diseqc_method == 0) {
390 budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd;
391 budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst;
392 budget->dvb_frontend->ops.set_tone = budget_set_tone;
393 }
385 break; 394 break;
386 } 395 }
387 break; 396 break;
diff --git a/drivers/media/dvb/ttusb-dec/ttusb_dec.c b/drivers/media/dvb/ttusb-dec/ttusb_dec.c
index a1c9fa9919ea..8135f3e76aeb 100644
--- a/drivers/media/dvb/ttusb-dec/ttusb_dec.c
+++ b/drivers/media/dvb/ttusb-dec/ttusb_dec.c
@@ -1135,8 +1135,7 @@ static void ttusb_dec_free_iso_urbs(struct ttusb_dec *dec)
1135 dprintk("%s\n", __FUNCTION__); 1135 dprintk("%s\n", __FUNCTION__);
1136 1136
1137 for (i = 0; i < ISO_BUF_COUNT; i++) 1137 for (i = 0; i < ISO_BUF_COUNT; i++)
1138 if (dec->iso_urb[i]) 1138 usb_free_urb(dec->iso_urb[i]);
1139 usb_free_urb(dec->iso_urb[i]);
1140 1139
1141 pci_free_consistent(NULL, 1140 pci_free_consistent(NULL,
1142 ISO_FRAME_SIZE * (FRAMES_PER_ISO_BUF * 1141 ISO_FRAME_SIZE * (FRAMES_PER_ISO_BUF *
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index bf267552941f..b8fde5cf4735 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -24,7 +24,7 @@ config VIDEO_HELPER_CHIPS_AUTO
24 decode audio/video standards. This option will autoselect 24 decode audio/video standards. This option will autoselect
25 all pertinent modules to each selected video module. 25 all pertinent modules to each selected video module.
26 26
27 Unselect this only if you know exaclty what you are doing, since 27 Unselect this only if you know exactly what you are doing, since
28 it may break support on some boards. 28 it may break support on some boards.
29 29
30 In doubt, say Y. 30 In doubt, say Y.
diff --git a/drivers/media/video/et61x251/et61x251_core.c b/drivers/media/video/et61x251/et61x251_core.c
index f786ab11d2cd..86e353b26b53 100644
--- a/drivers/media/video/et61x251/et61x251_core.c
+++ b/drivers/media/video/et61x251/et61x251_core.c
@@ -1182,8 +1182,6 @@ static void et61x251_release_resources(struct et61x251_device* cam)
1182 video_set_drvdata(cam->v4ldev, NULL); 1182 video_set_drvdata(cam->v4ldev, NULL);
1183 video_unregister_device(cam->v4ldev); 1183 video_unregister_device(cam->v4ldev);
1184 1184
1185 usb_put_dev(cam->usbdev);
1186
1187 mutex_unlock(&et61x251_sysfs_lock); 1185 mutex_unlock(&et61x251_sysfs_lock);
1188 1186
1189 kfree(cam->control_buffer); 1187 kfree(cam->control_buffer);
@@ -1275,6 +1273,7 @@ static int et61x251_release(struct inode* inode, struct file* filp)
1275 1273
1276 if (cam->state & DEV_DISCONNECTED) { 1274 if (cam->state & DEV_DISCONNECTED) {
1277 et61x251_release_resources(cam); 1275 et61x251_release_resources(cam);
1276 usb_put_dev(cam->usbdev);
1278 mutex_unlock(&cam->dev_mutex); 1277 mutex_unlock(&cam->dev_mutex);
1279 kfree(cam); 1278 kfree(cam);
1280 return 0; 1279 return 0;
diff --git a/drivers/media/video/pvrusb2/pvrusb2-hdw.c b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
index f920e0ccacd3..1f787333d18c 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-hdw.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
@@ -1953,8 +1953,8 @@ struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1953 return hdw; 1953 return hdw;
1954 fail: 1954 fail:
1955 if (hdw) { 1955 if (hdw) {
1956 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb); 1956 usb_free_urb(hdw->ctl_read_urb);
1957 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb); 1957 usb_free_urb(hdw->ctl_write_urb);
1958 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer); 1958 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1959 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer); 1959 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1960 if (hdw->controls) kfree(hdw->controls); 1960 if (hdw->controls) kfree(hdw->controls);
@@ -2575,12 +2575,10 @@ static void pvr2_ctl_timeout(unsigned long data)
2575 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 2575 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2576 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 2576 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2577 hdw->ctl_timeout_flag = !0; 2577 hdw->ctl_timeout_flag = !0;
2578 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) { 2578 if (hdw->ctl_write_pend_flag)
2579 usb_unlink_urb(hdw->ctl_write_urb); 2579 usb_unlink_urb(hdw->ctl_write_urb);
2580 } 2580 if (hdw->ctl_read_pend_flag)
2581 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2582 usb_unlink_urb(hdw->ctl_read_urb); 2581 usb_unlink_urb(hdw->ctl_read_urb);
2583 }
2584 } 2582 }
2585} 2583}
2586 2584
diff --git a/drivers/media/video/pvrusb2/pvrusb2-io.c b/drivers/media/video/pvrusb2/pvrusb2-io.c
index 70aa63eba0cb..57fb32033543 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-io.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-io.c
@@ -289,7 +289,7 @@ static void pvr2_buffer_done(struct pvr2_buffer *bp)
289 pvr2_buffer_set_none(bp); 289 pvr2_buffer_set_none(bp);
290 bp->signature = 0; 290 bp->signature = 0;
291 bp->stream = NULL; 291 bp->stream = NULL;
292 if (bp->purb) usb_free_urb(bp->purb); 292 usb_free_urb(bp->purb);
293 pvr2_trace(PVR2_TRACE_BUF_POOL,"/*---TRACE_FLOW---*/" 293 pvr2_trace(PVR2_TRACE_BUF_POOL,"/*---TRACE_FLOW---*/"
294 " bufferDone %p",bp); 294 " bufferDone %p",bp);
295} 295}
diff --git a/drivers/media/video/pwc/pwc-if.c b/drivers/media/video/pwc/pwc-if.c
index 46c114830884..a996aad79276 100644
--- a/drivers/media/video/pwc/pwc-if.c
+++ b/drivers/media/video/pwc/pwc-if.c
@@ -866,11 +866,9 @@ int pwc_isoc_init(struct pwc_device *pdev)
866 } 866 }
867 if (ret) { 867 if (ret) {
868 /* De-allocate in reverse order */ 868 /* De-allocate in reverse order */
869 while (i >= 0) { 869 while (i--) {
870 if (pdev->sbuf[i].urb != NULL) 870 usb_free_urb(pdev->sbuf[i].urb);
871 usb_free_urb(pdev->sbuf[i].urb);
872 pdev->sbuf[i].urb = NULL; 871 pdev->sbuf[i].urb = NULL;
873 i--;
874 } 872 }
875 return ret; 873 return ret;
876 } 874 }
@@ -1095,8 +1093,7 @@ static int pwc_video_open(struct inode *inode, struct file *file)
1095 PWC_DEBUG_OPEN(">> video_open called(vdev = 0x%p).\n", vdev); 1093 PWC_DEBUG_OPEN(">> video_open called(vdev = 0x%p).\n", vdev);
1096 1094
1097 pdev = (struct pwc_device *)vdev->priv; 1095 pdev = (struct pwc_device *)vdev->priv;
1098 if (pdev == NULL) 1096 BUG_ON(!pdev);
1099 BUG();
1100 if (pdev->vopen) { 1097 if (pdev->vopen) {
1101 PWC_DEBUG_OPEN("I'm busy, someone is using the device.\n"); 1098 PWC_DEBUG_OPEN("I'm busy, someone is using the device.\n");
1102 return -EBUSY; 1099 return -EBUSY;
diff --git a/drivers/media/video/saa6588.c b/drivers/media/video/saa6588.c
index 8ba05c214ca7..92eabf88a09b 100644
--- a/drivers/media/video/saa6588.c
+++ b/drivers/media/video/saa6588.c
@@ -212,8 +212,10 @@ static void read_from_buf(struct saa6588 *s, struct rds_command *a)
212 if (rd_blocks > s->block_count) 212 if (rd_blocks > s->block_count)
213 rd_blocks = s->block_count; 213 rd_blocks = s->block_count;
214 214
215 if (!rd_blocks) 215 if (!rd_blocks) {
216 spin_unlock_irqrestore(&s->lock, flags);
216 return; 217 return;
218 }
217 219
218 for (i = 0; i < rd_blocks; i++) { 220 for (i = 0; i < rd_blocks; i++) {
219 if (block_to_user_buf(s, buf_ptr)) { 221 if (block_to_user_buf(s, buf_ptr)) {
diff --git a/drivers/media/video/saa7115.c b/drivers/media/video/saa7115.c
index c5719f7bd1ac..f28398dd9d93 100644
--- a/drivers/media/video/saa7115.c
+++ b/drivers/media/video/saa7115.c
@@ -1464,8 +1464,6 @@ static int saa711x_attach(struct i2c_adapter *adapter, int address, int kind)
1464 client->driver = &i2c_driver_saa711x; 1464 client->driver = &i2c_driver_saa711x;
1465 snprintf(client->name, sizeof(client->name) - 1, "saa7115"); 1465 snprintf(client->name, sizeof(client->name) - 1, "saa7115");
1466 1466
1467 v4l_dbg(1, debug, client, "detecting saa7115 client on address 0x%x\n", address << 1);
1468
1469 for (i=0;i<0x0f;i++) { 1467 for (i=0;i<0x0f;i++) {
1470 saa711x_write(client, 0, i); 1468 saa711x_write(client, 0, i);
1471 name[i] = (saa711x_read(client, 0) &0x0f) +'0'; 1469 name[i] = (saa711x_read(client, 0) &0x0f) +'0';
@@ -1477,6 +1475,13 @@ static int saa711x_attach(struct i2c_adapter *adapter, int address, int kind)
1477 saa711x_write(client, 0, 5); 1475 saa711x_write(client, 0, 5);
1478 chip_id = saa711x_read(client, 0) & 0x0f; 1476 chip_id = saa711x_read(client, 0) & 0x0f;
1479 1477
1478 /* Check whether this chip is part of the saa711x series */
1479 if (memcmp(name, "1f711", 5)) {
1480 v4l_dbg(1, debug, client, "chip found @ 0x%x (ID %s) does not match a known saa711x chip.\n",
1481 address << 1, name);
1482 return 0;
1483 }
1484
1480 snprintf(client->name, sizeof(client->name) - 1, "saa711%d",chip_id); 1485 snprintf(client->name, sizeof(client->name) - 1, "saa711%d",chip_id);
1481 v4l_info(client, "saa711%d found (%s) @ 0x%x (%s)\n", chip_id, name, address << 1, adapter->name); 1486 v4l_info(client, "saa711%d found (%s) @ 0x%x (%s)\n", chip_id, name, address << 1, adapter->name);
1482 1487
diff --git a/drivers/media/video/sn9c102/sn9c102_core.c b/drivers/media/video/sn9c102/sn9c102_core.c
index a4702d3c2aca..18458d46c0ff 100644
--- a/drivers/media/video/sn9c102/sn9c102_core.c
+++ b/drivers/media/video/sn9c102/sn9c102_core.c
@@ -775,7 +775,7 @@ static int sn9c102_start_transfer(struct sn9c102_device* cam)
775 return 0; 775 return 0;
776 776
777free_urbs: 777free_urbs:
778 for (i = 0; (i < SN9C102_URBS) && cam->urb[i]; i++) 778 for (i = 0; i < SN9C102_URBS; i++)
779 usb_free_urb(cam->urb[i]); 779 usb_free_urb(cam->urb[i]);
780 780
781free_buffers: 781free_buffers:
@@ -1462,8 +1462,6 @@ static void sn9c102_release_resources(struct sn9c102_device* cam)
1462 video_set_drvdata(cam->v4ldev, NULL); 1462 video_set_drvdata(cam->v4ldev, NULL);
1463 video_unregister_device(cam->v4ldev); 1463 video_unregister_device(cam->v4ldev);
1464 1464
1465 usb_put_dev(cam->usbdev);
1466
1467 mutex_unlock(&sn9c102_sysfs_lock); 1465 mutex_unlock(&sn9c102_sysfs_lock);
1468 1466
1469 kfree(cam->control_buffer); 1467 kfree(cam->control_buffer);
@@ -1555,6 +1553,7 @@ static int sn9c102_release(struct inode* inode, struct file* filp)
1555 1553
1556 if (cam->state & DEV_DISCONNECTED) { 1554 if (cam->state & DEV_DISCONNECTED) {
1557 sn9c102_release_resources(cam); 1555 sn9c102_release_resources(cam);
1556 usb_put_dev(cam->usbdev);
1558 mutex_unlock(&cam->dev_mutex); 1557 mutex_unlock(&cam->dev_mutex);
1559 kfree(cam); 1558 kfree(cam);
1560 return 0; 1559 return 0;
diff --git a/drivers/media/video/usbvideo/quickcam_messenger.c b/drivers/media/video/usbvideo/quickcam_messenger.c
index 9a26b9484aae..bbf2beeeb449 100644
--- a/drivers/media/video/usbvideo/quickcam_messenger.c
+++ b/drivers/media/video/usbvideo/quickcam_messenger.c
@@ -190,8 +190,7 @@ static int qcm_alloc_int_urb(struct qcm *cam)
190 190
191static void qcm_free_int(struct qcm *cam) 191static void qcm_free_int(struct qcm *cam)
192{ 192{
193 if (cam->button_urb) 193 usb_free_urb(cam->button_urb);
194 usb_free_urb(cam->button_urb);
195} 194}
196#endif /* CONFIG_INPUT */ 195#endif /* CONFIG_INPUT */
197 196
diff --git a/drivers/media/video/zc0301/zc0301_core.c b/drivers/media/video/zc0301/zc0301_core.c
index 5b5563424422..52d0f759ee00 100644
--- a/drivers/media/video/zc0301/zc0301_core.c
+++ b/drivers/media/video/zc0301/zc0301_core.c
@@ -489,7 +489,7 @@ static int zc0301_start_transfer(struct zc0301_device* cam)
489 return 0; 489 return 0;
490 490
491free_urbs: 491free_urbs:
492 for (i = 0; (i < ZC0301_URBS) && cam->urb[i]; i++) 492 for (i = 0; i < ZC0301_URBS; i++)
493 usb_free_urb(cam->urb[i]); 493 usb_free_urb(cam->urb[i]);
494 494
495free_buffers: 495free_buffers:
diff --git a/drivers/message/fusion/mptbase.c b/drivers/message/fusion/mptbase.c
index e5c72719debc..051b7c5b8f03 100644
--- a/drivers/message/fusion/mptbase.c
+++ b/drivers/message/fusion/mptbase.c
@@ -6185,7 +6185,7 @@ mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
6185 "Abort", /* 12h */ 6185 "Abort", /* 12h */
6186 "IO Not Yet Executed", /* 13h */ 6186 "IO Not Yet Executed", /* 13h */
6187 "IO Executed", /* 14h */ 6187 "IO Executed", /* 14h */
6188 "Persistant Reservation Out Not Affiliation Owner", /* 15h */ 6188 "Persistent Reservation Out Not Affiliation Owner", /* 15h */
6189 "Open Transmit DMA Abort", /* 16h */ 6189 "Open Transmit DMA Abort", /* 16h */
6190 "IO Device Missing Delay Retry", /* 17h */ 6190 "IO Device Missing Delay Retry", /* 17h */
6191 NULL, /* 18h */ 6191 NULL, /* 18h */
diff --git a/drivers/message/i2o/pci.c b/drivers/message/i2o/pci.c
index 62f1ac08332c..8287f95c8c42 100644
--- a/drivers/message/i2o/pci.c
+++ b/drivers/message/i2o/pci.c
@@ -320,7 +320,6 @@ static int __devinit i2o_pci_probe(struct pci_dev *pdev,
320 struct i2o_controller *c; 320 struct i2o_controller *c;
321 int rc; 321 int rc;
322 struct pci_dev *i960 = NULL; 322 struct pci_dev *i960 = NULL;
323 int enabled = pdev->is_enabled;
324 323
325 printk(KERN_INFO "i2o: Checking for PCI I2O controllers...\n"); 324 printk(KERN_INFO "i2o: Checking for PCI I2O controllers...\n");
326 325
@@ -330,12 +329,11 @@ static int __devinit i2o_pci_probe(struct pci_dev *pdev,
330 return -ENODEV; 329 return -ENODEV;
331 } 330 }
332 331
333 if (!enabled) 332 if ((rc = pci_enable_device(pdev))) {
334 if ((rc = pci_enable_device(pdev))) { 333 printk(KERN_WARNING "i2o: couldn't enable device %s\n",
335 printk(KERN_WARNING "i2o: couldn't enable device %s\n", 334 pci_name(pdev));
336 pci_name(pdev)); 335 return rc;
337 return rc; 336 }
338 }
339 337
340 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { 338 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
341 printk(KERN_WARNING "i2o: no suitable DMA found for %s\n", 339 printk(KERN_WARNING "i2o: no suitable DMA found for %s\n",
@@ -442,8 +440,7 @@ static int __devinit i2o_pci_probe(struct pci_dev *pdev,
442 i2o_iop_free(c); 440 i2o_iop_free(c);
443 441
444 disable: 442 disable:
445 if (!enabled) 443 pci_disable_device(pdev);
446 pci_disable_device(pdev);
447 444
448 return rc; 445 return rc;
449} 446}
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ea41852ec8cd..f4f8ccaf5455 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -40,7 +40,7 @@ config MMC_ARMMMCI
40 If unsure, say N. 40 If unsure, say N.
41 41
42config MMC_PXA 42config MMC_PXA
43 tristate "Intel PXA255 Multimedia Card Interface support" 43 tristate "Intel PXA25x/26x/27x Multimedia Card Interface support"
44 depends on ARCH_PXA && MMC 44 depends on ARCH_PXA && MMC
45 help 45 help
46 This selects the Intel(R) PXA(R) Multimedia card Interface. 46 This selects the Intel(R) PXA(R) Multimedia card Interface.
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c
index 494b23fb0a01..6495cd8a9306 100644
--- a/drivers/mmc/at91_mci.c
+++ b/drivers/mmc/at91_mci.c
@@ -793,7 +793,7 @@ int at91_mci_get_ro(struct mmc_host *mmc)
793 return read_only; 793 return read_only;
794} 794}
795 795
796static struct mmc_host_ops at91_mci_ops = { 796static const struct mmc_host_ops at91_mci_ops = {
797 .request = at91_mci_request, 797 .request = at91_mci_request,
798 .set_ios = at91_mci_set_ios, 798 .set_ios = at91_mci_set_ios,
799 .get_ro = at91_mci_get_ro, 799 .get_ro = at91_mci_get_ro,
diff --git a/drivers/mmc/au1xmmc.c b/drivers/mmc/au1xmmc.c
index 53ffcbb14a97..447fba5825fd 100644
--- a/drivers/mmc/au1xmmc.c
+++ b/drivers/mmc/au1xmmc.c
@@ -875,7 +875,7 @@ static void au1xmmc_init_dma(struct au1xmmc_host *host)
875 host->rx_chan = rxchan; 875 host->rx_chan = rxchan;
876} 876}
877 877
878struct mmc_host_ops au1xmmc_ops = { 878struct const mmc_host_ops au1xmmc_ops = {
879 .request = au1xmmc_request, 879 .request = au1xmmc_request,
880 .set_ios = au1xmmc_set_ios, 880 .set_ios = au1xmmc_set_ios,
881}; 881};
diff --git a/drivers/mmc/imxmmc.c b/drivers/mmc/imxmmc.c
index 659d4a822cc5..06e7fcd19221 100644
--- a/drivers/mmc/imxmmc.c
+++ b/drivers/mmc/imxmmc.c
@@ -877,7 +877,7 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
877 } 877 }
878} 878}
879 879
880static struct mmc_host_ops imxmci_ops = { 880static const struct mmc_host_ops imxmci_ops = {
881 .request = imxmci_request, 881 .request = imxmci_request,
882 .set_ios = imxmci_set_ios, 882 .set_ios = imxmci_set_ios,
883}; 883};
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 21fd39e4a20f..6f2a282e2b97 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -4,6 +4,7 @@
4 * Copyright (C) 2003-2004 Russell King, All Rights Reserved. 4 * Copyright (C) 2003-2004 Russell King, All Rights Reserved.
5 * SD support Copyright (C) 2004 Ian Molton, All Rights Reserved. 5 * SD support Copyright (C) 2004 Ian Molton, All Rights Reserved.
6 * SD support Copyright (C) 2005 Pierre Ossman, All Rights Reserved. 6 * SD support Copyright (C) 2005 Pierre Ossman, All Rights Reserved.
7 * MMCv4 support Copyright (C) 2006 Philip Langdale, All Rights Reserved.
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -396,23 +397,23 @@ static int mmc_select_card(struct mmc_host *host, struct mmc_card *card)
396 return err; 397 return err;
397 398
398 /* 399 /*
399 * Default bus width is 1 bit. 400 * We can only change the bus width of SD cards when
400 */ 401 * they are selected so we have to put the handling
401 host->ios.bus_width = MMC_BUS_WIDTH_1;
402
403 /*
404 * We can only change the bus width of the selected
405 * card so therefore we have to put the handling
406 * here. 402 * here.
403 *
404 * The card is in 1 bit mode by default so
405 * we only need to change if it supports the
406 * wider version.
407 */ 407 */
408 if (host->caps & MMC_CAP_4_BIT_DATA) { 408 if (mmc_card_sd(card) &&
409 (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) {
410
409 /* 411 /*
410 * The card is in 1 bit mode by default so 412 * Default bus width is 1 bit.
411 * we only need to change if it supports the 413 */
412 * wider version. 414 host->ios.bus_width = MMC_BUS_WIDTH_1;
413 */ 415
414 if (mmc_card_sd(card) && 416 if (host->caps & MMC_CAP_4_BIT_DATA) {
415 (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) {
416 struct mmc_command cmd; 417 struct mmc_command cmd;
417 cmd.opcode = SD_APP_SET_BUS_WIDTH; 418 cmd.opcode = SD_APP_SET_BUS_WIDTH;
418 cmd.arg = SD_BUS_WIDTH_4; 419 cmd.arg = SD_BUS_WIDTH_4;
@@ -453,11 +454,11 @@ static void mmc_deselect_cards(struct mmc_host *host)
453 454
454static inline void mmc_delay(unsigned int ms) 455static inline void mmc_delay(unsigned int ms)
455{ 456{
456 if (ms < HZ / 1000) { 457 if (ms < 1000 / HZ) {
457 yield(); 458 cond_resched();
458 mdelay(ms); 459 mdelay(ms);
459 } else { 460 } else {
460 msleep_interruptible (ms); 461 msleep(ms);
461 } 462 }
462} 463}
463 464
@@ -953,6 +954,137 @@ static void mmc_read_csds(struct mmc_host *host)
953 } 954 }
954} 955}
955 956
957static void mmc_process_ext_csds(struct mmc_host *host)
958{
959 int err;
960 struct mmc_card *card;
961
962 struct mmc_request mrq;
963 struct mmc_command cmd;
964 struct mmc_data data;
965
966 struct scatterlist sg;
967
968 /*
969 * As the ext_csd is so large and mostly unused, we don't store the
970 * raw block in mmc_card.
971 */
972 u8 *ext_csd;
973 ext_csd = kmalloc(512, GFP_KERNEL);
974 if (!ext_csd) {
975 printk("%s: could not allocate a buffer to receive the ext_csd."
976 "mmc v4 cards will be treated as v3.\n",
977 mmc_hostname(host));
978 return;
979 }
980
981 list_for_each_entry(card, &host->cards, node) {
982 if (card->state & (MMC_STATE_DEAD|MMC_STATE_PRESENT))
983 continue;
984 if (mmc_card_sd(card))
985 continue;
986 if (card->csd.mmca_vsn < CSD_SPEC_VER_4)
987 continue;
988
989 err = mmc_select_card(host, card);
990 if (err != MMC_ERR_NONE) {
991 mmc_card_set_dead(card);
992 continue;
993 }
994
995 memset(&cmd, 0, sizeof(struct mmc_command));
996
997 cmd.opcode = MMC_SEND_EXT_CSD;
998 cmd.arg = 0;
999 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1000
1001 memset(&data, 0, sizeof(struct mmc_data));
1002
1003 mmc_set_data_timeout(&data, card, 0);
1004
1005 data.blksz = 512;
1006 data.blocks = 1;
1007 data.flags = MMC_DATA_READ;
1008 data.sg = &sg;
1009 data.sg_len = 1;
1010
1011 memset(&mrq, 0, sizeof(struct mmc_request));
1012
1013 mrq.cmd = &cmd;
1014 mrq.data = &data;
1015
1016 sg_init_one(&sg, ext_csd, 512);
1017
1018 mmc_wait_for_req(host, &mrq);
1019
1020 if (cmd.error != MMC_ERR_NONE || data.error != MMC_ERR_NONE) {
1021 mmc_card_set_dead(card);
1022 continue;
1023 }
1024
1025 switch (ext_csd[EXT_CSD_CARD_TYPE]) {
1026 case EXT_CSD_CARD_TYPE_52 | EXT_CSD_CARD_TYPE_26:
1027 card->ext_csd.hs_max_dtr = 52000000;
1028 break;
1029 case EXT_CSD_CARD_TYPE_26:
1030 card->ext_csd.hs_max_dtr = 26000000;
1031 break;
1032 default:
1033 /* MMC v4 spec says this cannot happen */
1034 printk("%s: card is mmc v4 but doesn't support "
1035 "any high-speed modes.\n",
1036 mmc_hostname(card->host));
1037 mmc_card_set_bad(card);
1038 continue;
1039 }
1040
1041 /* Activate highspeed support. */
1042 cmd.opcode = MMC_SWITCH;
1043 cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
1044 (EXT_CSD_HS_TIMING << 16) |
1045 (1 << 8) |
1046 EXT_CSD_CMD_SET_NORMAL;
1047 cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
1048
1049 err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
1050 if (err != MMC_ERR_NONE) {
1051 printk("%s: failed to switch card to mmc v4 "
1052 "high-speed mode.\n",
1053 mmc_hostname(card->host));
1054 continue;
1055 }
1056
1057 mmc_card_set_highspeed(card);
1058
1059 /* Check for host support for wide-bus modes. */
1060 if (!(host->caps & MMC_CAP_4_BIT_DATA)) {
1061 continue;
1062 }
1063
1064 /* Activate 4-bit support. */
1065 cmd.opcode = MMC_SWITCH;
1066 cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
1067 (EXT_CSD_BUS_WIDTH << 16) |
1068 (EXT_CSD_BUS_WIDTH_4 << 8) |
1069 EXT_CSD_CMD_SET_NORMAL;
1070 cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
1071
1072 err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
1073 if (err != MMC_ERR_NONE) {
1074 printk("%s: failed to switch card to "
1075 "mmc v4 4-bit bus mode.\n",
1076 mmc_hostname(card->host));
1077 continue;
1078 }
1079
1080 host->ios.bus_width = MMC_BUS_WIDTH_4;
1081 }
1082
1083 kfree(ext_csd);
1084
1085 mmc_deselect_cards(host);
1086}
1087
956static void mmc_read_scrs(struct mmc_host *host) 1088static void mmc_read_scrs(struct mmc_host *host)
957{ 1089{
958 int err; 1090 int err;
@@ -1025,14 +1157,133 @@ static void mmc_read_scrs(struct mmc_host *host)
1025 mmc_deselect_cards(host); 1157 mmc_deselect_cards(host);
1026} 1158}
1027 1159
1160static void mmc_read_switch_caps(struct mmc_host *host)
1161{
1162 int err;
1163 struct mmc_card *card;
1164 struct mmc_request mrq;
1165 struct mmc_command cmd;
1166 struct mmc_data data;
1167 unsigned char *status;
1168 struct scatterlist sg;
1169
1170 status = kmalloc(64, GFP_KERNEL);
1171 if (!status) {
1172 printk(KERN_WARNING "%s: Unable to allocate buffer for "
1173 "reading switch capabilities.\n",
1174 mmc_hostname(host));
1175 return;
1176 }
1177
1178 list_for_each_entry(card, &host->cards, node) {
1179 if (card->state & (MMC_STATE_DEAD|MMC_STATE_PRESENT))
1180 continue;
1181 if (!mmc_card_sd(card))
1182 continue;
1183 if (card->scr.sda_vsn < SCR_SPEC_VER_1)
1184 continue;
1185
1186 err = mmc_select_card(host, card);
1187 if (err != MMC_ERR_NONE) {
1188 mmc_card_set_dead(card);
1189 continue;
1190 }
1191
1192 memset(&cmd, 0, sizeof(struct mmc_command));
1193
1194 cmd.opcode = SD_SWITCH;
1195 cmd.arg = 0x00FFFFF1;
1196 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1197
1198 memset(&data, 0, sizeof(struct mmc_data));
1199
1200 mmc_set_data_timeout(&data, card, 0);
1201
1202 data.blksz = 64;
1203 data.blocks = 1;
1204 data.flags = MMC_DATA_READ;
1205 data.sg = &sg;
1206 data.sg_len = 1;
1207
1208 memset(&mrq, 0, sizeof(struct mmc_request));
1209
1210 mrq.cmd = &cmd;
1211 mrq.data = &data;
1212
1213 sg_init_one(&sg, status, 64);
1214
1215 mmc_wait_for_req(host, &mrq);
1216
1217 if (cmd.error != MMC_ERR_NONE || data.error != MMC_ERR_NONE) {
1218 mmc_card_set_dead(card);
1219 continue;
1220 }
1221
1222 if (status[13] & 0x02)
1223 card->sw_caps.hs_max_dtr = 50000000;
1224
1225 memset(&cmd, 0, sizeof(struct mmc_command));
1226
1227 cmd.opcode = SD_SWITCH;
1228 cmd.arg = 0x80FFFFF1;
1229 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1230
1231 memset(&data, 0, sizeof(struct mmc_data));
1232
1233 mmc_set_data_timeout(&data, card, 0);
1234
1235 data.blksz = 64;
1236 data.blocks = 1;
1237 data.flags = MMC_DATA_READ;
1238 data.sg = &sg;
1239 data.sg_len = 1;
1240
1241 memset(&mrq, 0, sizeof(struct mmc_request));
1242
1243 mrq.cmd = &cmd;
1244 mrq.data = &data;
1245
1246 sg_init_one(&sg, status, 64);
1247
1248 mmc_wait_for_req(host, &mrq);
1249
1250 if (cmd.error != MMC_ERR_NONE || data.error != MMC_ERR_NONE) {
1251 mmc_card_set_dead(card);
1252 continue;
1253 }
1254
1255 if ((status[16] & 0xF) != 1) {
1256 printk(KERN_WARNING "%s: Problem switching card "
1257 "into high-speed mode!\n",
1258 mmc_hostname(host));
1259 continue;
1260 }
1261
1262 mmc_card_set_highspeed(card);
1263 }
1264
1265 kfree(status);
1266
1267 mmc_deselect_cards(host);
1268}
1269
1028static unsigned int mmc_calculate_clock(struct mmc_host *host) 1270static unsigned int mmc_calculate_clock(struct mmc_host *host)
1029{ 1271{
1030 struct mmc_card *card; 1272 struct mmc_card *card;
1031 unsigned int max_dtr = host->f_max; 1273 unsigned int max_dtr = host->f_max;
1032 1274
1033 list_for_each_entry(card, &host->cards, node) 1275 list_for_each_entry(card, &host->cards, node)
1034 if (!mmc_card_dead(card) && max_dtr > card->csd.max_dtr) 1276 if (!mmc_card_dead(card)) {
1035 max_dtr = card->csd.max_dtr; 1277 if (mmc_card_highspeed(card) && mmc_card_sd(card)) {
1278 if (max_dtr > card->sw_caps.hs_max_dtr)
1279 max_dtr = card->sw_caps.hs_max_dtr;
1280 } else if (mmc_card_highspeed(card) && !mmc_card_sd(card)) {
1281 if (max_dtr > card->ext_csd.hs_max_dtr)
1282 max_dtr = card->ext_csd.hs_max_dtr;
1283 } else if (max_dtr > card->csd.max_dtr) {
1284 max_dtr = card->csd.max_dtr;
1285 }
1286 }
1036 1287
1037 pr_debug("%s: selected %d.%03dMHz transfer rate\n", 1288 pr_debug("%s: selected %d.%03dMHz transfer rate\n",
1038 mmc_hostname(host), 1289 mmc_hostname(host),
@@ -1150,8 +1401,11 @@ static void mmc_setup(struct mmc_host *host)
1150 1401
1151 mmc_read_csds(host); 1402 mmc_read_csds(host);
1152 1403
1153 if (host->mode == MMC_MODE_SD) 1404 if (host->mode == MMC_MODE_SD) {
1154 mmc_read_scrs(host); 1405 mmc_read_scrs(host);
1406 mmc_read_switch_caps(host);
1407 } else
1408 mmc_process_ext_csds(host);
1155} 1409}
1156 1410
1157 1411
diff --git a/drivers/mmc/mmc_block.c b/drivers/mmc/mmc_block.c
index f9027c8db792..87713572293f 100644
--- a/drivers/mmc/mmc_block.c
+++ b/drivers/mmc/mmc_block.c
@@ -83,7 +83,6 @@ static void mmc_blk_put(struct mmc_blk_data *md)
83 md->usage--; 83 md->usage--;
84 if (md->usage == 0) { 84 if (md->usage == 0) {
85 put_disk(md->disk); 85 put_disk(md->disk);
86 mmc_cleanup_queue(&md->queue);
87 kfree(md); 86 kfree(md);
88 } 87 }
89 mutex_unlock(&open_lock); 88 mutex_unlock(&open_lock);
@@ -225,10 +224,10 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
225 struct mmc_blk_data *md = mq->data; 224 struct mmc_blk_data *md = mq->data;
226 struct mmc_card *card = md->queue.card; 225 struct mmc_card *card = md->queue.card;
227 struct mmc_blk_request brq; 226 struct mmc_blk_request brq;
228 int ret; 227 int ret = 1;
229 228
230 if (mmc_card_claim_host(card)) 229 if (mmc_card_claim_host(card))
231 goto cmd_err; 230 goto flush_queue;
232 231
233 do { 232 do {
234 struct mmc_command cmd; 233 struct mmc_command cmd;
@@ -345,8 +344,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
345 return 1; 344 return 1;
346 345
347 cmd_err: 346 cmd_err:
348 ret = 1;
349
350 /* 347 /*
351 * If this is an SD card and we're writing, we can first 348 * If this is an SD card and we're writing, we can first
352 * mark the known good sectors as ok. 349 * mark the known good sectors as ok.
@@ -380,6 +377,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
380 377
381 mmc_card_release_host(card); 378 mmc_card_release_host(card);
382 379
380flush_queue:
383 spin_lock_irq(&md->lock); 381 spin_lock_irq(&md->lock);
384 while (ret) { 382 while (ret) {
385 ret = end_that_request_chunk(req, 0, 383 ret = end_that_request_chunk(req, 0,
@@ -553,12 +551,11 @@ static void mmc_blk_remove(struct mmc_card *card)
553 if (md) { 551 if (md) {
554 int devidx; 552 int devidx;
555 553
554 /* Stop new requests from getting into the queue */
556 del_gendisk(md->disk); 555 del_gendisk(md->disk);
557 556
558 /* 557 /* Then flush out any already in there */
559 * I think this is needed. 558 mmc_cleanup_queue(&md->queue);
560 */
561 md->disk->queue = NULL;
562 559
563 devidx = md->disk->first_minor >> MMC_SHIFT; 560 devidx = md->disk->first_minor >> MMC_SHIFT;
564 __clear_bit(devidx, dev_use); 561 __clear_bit(devidx, dev_use);
diff --git a/drivers/mmc/mmc_queue.c b/drivers/mmc/mmc_queue.c
index 4ccdd82b680f..a17423a4ed8f 100644
--- a/drivers/mmc/mmc_queue.c
+++ b/drivers/mmc/mmc_queue.c
@@ -10,13 +10,13 @@
10 */ 10 */
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/blkdev.h> 12#include <linux/blkdev.h>
13#include <linux/kthread.h>
13 14
14#include <linux/mmc/card.h> 15#include <linux/mmc/card.h>
15#include <linux/mmc/host.h> 16#include <linux/mmc/host.h>
16#include "mmc_queue.h" 17#include "mmc_queue.h"
17 18
18#define MMC_QUEUE_EXIT (1 << 0) 19#define MMC_QUEUE_SUSPENDED (1 << 0)
19#define MMC_QUEUE_SUSPENDED (1 << 1)
20 20
21/* 21/*
22 * Prepare a MMC request. Essentially, this means passing the 22 * Prepare a MMC request. Essentially, this means passing the
@@ -59,7 +59,6 @@ static int mmc_queue_thread(void *d)
59{ 59{
60 struct mmc_queue *mq = d; 60 struct mmc_queue *mq = d;
61 struct request_queue *q = mq->queue; 61 struct request_queue *q = mq->queue;
62 DECLARE_WAITQUEUE(wait, current);
63 62
64 /* 63 /*
65 * Set iothread to ensure that we aren't put to sleep by 64 * Set iothread to ensure that we aren't put to sleep by
@@ -67,12 +66,7 @@ static int mmc_queue_thread(void *d)
67 */ 66 */
68 current->flags |= PF_MEMALLOC|PF_NOFREEZE; 67 current->flags |= PF_MEMALLOC|PF_NOFREEZE;
69 68
70 daemonize("mmcqd");
71
72 complete(&mq->thread_complete);
73
74 down(&mq->thread_sem); 69 down(&mq->thread_sem);
75 add_wait_queue(&mq->thread_wq, &wait);
76 do { 70 do {
77 struct request *req = NULL; 71 struct request *req = NULL;
78 72
@@ -84,7 +78,7 @@ static int mmc_queue_thread(void *d)
84 spin_unlock_irq(q->queue_lock); 78 spin_unlock_irq(q->queue_lock);
85 79
86 if (!req) { 80 if (!req) {
87 if (mq->flags & MMC_QUEUE_EXIT) 81 if (kthread_should_stop())
88 break; 82 break;
89 up(&mq->thread_sem); 83 up(&mq->thread_sem);
90 schedule(); 84 schedule();
@@ -95,10 +89,8 @@ static int mmc_queue_thread(void *d)
95 89
96 mq->issue_fn(mq, req); 90 mq->issue_fn(mq, req);
97 } while (1); 91 } while (1);
98 remove_wait_queue(&mq->thread_wq, &wait);
99 up(&mq->thread_sem); 92 up(&mq->thread_sem);
100 93
101 complete_and_exit(&mq->thread_complete, 0);
102 return 0; 94 return 0;
103} 95}
104 96
@@ -111,9 +103,22 @@ static int mmc_queue_thread(void *d)
111static void mmc_request(request_queue_t *q) 103static void mmc_request(request_queue_t *q)
112{ 104{
113 struct mmc_queue *mq = q->queuedata; 105 struct mmc_queue *mq = q->queuedata;
106 struct request *req;
107 int ret;
108
109 if (!mq) {
110 printk(KERN_ERR "MMC: killing requests for dead queue\n");
111 while ((req = elv_next_request(q)) != NULL) {
112 do {
113 ret = end_that_request_chunk(req, 0,
114 req->current_nr_sectors << 9);
115 } while (ret);
116 }
117 return;
118 }
114 119
115 if (!mq->req) 120 if (!mq->req)
116 wake_up(&mq->thread_wq); 121 wake_up_process(mq->thread);
117} 122}
118 123
119/** 124/**
@@ -130,8 +135,8 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, spinlock_t *lock
130 u64 limit = BLK_BOUNCE_HIGH; 135 u64 limit = BLK_BOUNCE_HIGH;
131 int ret; 136 int ret;
132 137
133 if (host->dev->dma_mask && *host->dev->dma_mask) 138 if (mmc_dev(host)->dma_mask && *mmc_dev(host)->dma_mask)
134 limit = *host->dev->dma_mask; 139 limit = *mmc_dev(host)->dma_mask;
135 140
136 mq->card = card; 141 mq->card = card;
137 mq->queue = blk_init_queue(mmc_request, lock); 142 mq->queue = blk_init_queue(mmc_request, lock);
@@ -152,36 +157,40 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, spinlock_t *lock
152 GFP_KERNEL); 157 GFP_KERNEL);
153 if (!mq->sg) { 158 if (!mq->sg) {
154 ret = -ENOMEM; 159 ret = -ENOMEM;
155 goto cleanup; 160 goto cleanup_queue;
156 } 161 }
157 162
158 init_completion(&mq->thread_complete);
159 init_waitqueue_head(&mq->thread_wq);
160 init_MUTEX(&mq->thread_sem); 163 init_MUTEX(&mq->thread_sem);
161 164
162 ret = kernel_thread(mmc_queue_thread, mq, CLONE_KERNEL); 165 mq->thread = kthread_run(mmc_queue_thread, mq, "mmcqd");
163 if (ret >= 0) { 166 if (IS_ERR(mq->thread)) {
164 wait_for_completion(&mq->thread_complete); 167 ret = PTR_ERR(mq->thread);
165 init_completion(&mq->thread_complete); 168 goto free_sg;
166 ret = 0;
167 goto out;
168 } 169 }
169 170
170 cleanup: 171 return 0;
172
173 free_sg:
171 kfree(mq->sg); 174 kfree(mq->sg);
172 mq->sg = NULL; 175 mq->sg = NULL;
173 176 cleanup_queue:
174 blk_cleanup_queue(mq->queue); 177 blk_cleanup_queue(mq->queue);
175 out:
176 return ret; 178 return ret;
177} 179}
178EXPORT_SYMBOL(mmc_init_queue); 180EXPORT_SYMBOL(mmc_init_queue);
179 181
180void mmc_cleanup_queue(struct mmc_queue *mq) 182void mmc_cleanup_queue(struct mmc_queue *mq)
181{ 183{
182 mq->flags |= MMC_QUEUE_EXIT; 184 request_queue_t *q = mq->queue;
183 wake_up(&mq->thread_wq); 185 unsigned long flags;
184 wait_for_completion(&mq->thread_complete); 186
187 /* Mark that we should start throwing out stragglers */
188 spin_lock_irqsave(q->queue_lock, flags);
189 q->queuedata = NULL;
190 spin_unlock_irqrestore(q->queue_lock, flags);
191
192 /* Then terminate our worker thread */
193 kthread_stop(mq->thread);
185 194
186 kfree(mq->sg); 195 kfree(mq->sg);
187 mq->sg = NULL; 196 mq->sg = NULL;
diff --git a/drivers/mmc/mmc_queue.h b/drivers/mmc/mmc_queue.h
index 7182d2f69b4e..c9f139e764f6 100644
--- a/drivers/mmc/mmc_queue.h
+++ b/drivers/mmc/mmc_queue.h
@@ -6,8 +6,7 @@ struct task_struct;
6 6
7struct mmc_queue { 7struct mmc_queue {
8 struct mmc_card *card; 8 struct mmc_card *card;
9 struct completion thread_complete; 9 struct task_struct *thread;
10 wait_queue_head_t thread_wq;
11 struct semaphore thread_sem; 10 struct semaphore thread_sem;
12 unsigned int flags; 11 unsigned int flags;
13 struct request *req; 12 struct request *req;
diff --git a/drivers/mmc/mmc_sysfs.c b/drivers/mmc/mmc_sysfs.c
index fd9a5fc6db7b..e334acd045bc 100644
--- a/drivers/mmc/mmc_sysfs.c
+++ b/drivers/mmc/mmc_sysfs.c
@@ -199,7 +199,7 @@ void mmc_init_card(struct mmc_card *card, struct mmc_host *host)
199 memset(card, 0, sizeof(struct mmc_card)); 199 memset(card, 0, sizeof(struct mmc_card));
200 card->host = host; 200 card->host = host;
201 device_initialize(&card->dev); 201 device_initialize(&card->dev);
202 card->dev.parent = card->host->dev; 202 card->dev.parent = mmc_dev(host);
203 card->dev.bus = &mmc_bus_type; 203 card->dev.bus = &mmc_bus_type;
204 card->dev.release = mmc_release_card; 204 card->dev.release = mmc_release_card;
205} 205}
@@ -242,7 +242,7 @@ void mmc_remove_card(struct mmc_card *card)
242} 242}
243 243
244 244
245static void mmc_host_classdev_release(struct class_device *dev) 245static void mmc_host_classdev_release(struct device *dev)
246{ 246{
247 struct mmc_host *host = cls_dev_to_mmc_host(dev); 247 struct mmc_host *host = cls_dev_to_mmc_host(dev);
248 kfree(host); 248 kfree(host);
@@ -250,7 +250,7 @@ static void mmc_host_classdev_release(struct class_device *dev)
250 250
251static struct class mmc_host_class = { 251static struct class mmc_host_class = {
252 .name = "mmc_host", 252 .name = "mmc_host",
253 .release = mmc_host_classdev_release, 253 .dev_release = mmc_host_classdev_release,
254}; 254};
255 255
256static DEFINE_IDR(mmc_host_idr); 256static DEFINE_IDR(mmc_host_idr);
@@ -267,10 +267,10 @@ struct mmc_host *mmc_alloc_host_sysfs(int extra, struct device *dev)
267 if (host) { 267 if (host) {
268 memset(host, 0, sizeof(struct mmc_host) + extra); 268 memset(host, 0, sizeof(struct mmc_host) + extra);
269 269
270 host->dev = dev; 270 host->parent = dev;
271 host->class_dev.dev = host->dev; 271 host->class_dev.parent = dev;
272 host->class_dev.class = &mmc_host_class; 272 host->class_dev.class = &mmc_host_class;
273 class_device_initialize(&host->class_dev); 273 device_initialize(&host->class_dev);
274 } 274 }
275 275
276 return host; 276 return host;
@@ -292,10 +292,10 @@ int mmc_add_host_sysfs(struct mmc_host *host)
292 if (err) 292 if (err)
293 return err; 293 return err;
294 294
295 snprintf(host->class_dev.class_id, BUS_ID_SIZE, 295 snprintf(host->class_dev.bus_id, BUS_ID_SIZE,
296 "mmc%d", host->index); 296 "mmc%d", host->index);
297 297
298 return class_device_add(&host->class_dev); 298 return device_add(&host->class_dev);
299} 299}
300 300
301/* 301/*
@@ -303,7 +303,7 @@ int mmc_add_host_sysfs(struct mmc_host *host)
303 */ 303 */
304void mmc_remove_host_sysfs(struct mmc_host *host) 304void mmc_remove_host_sysfs(struct mmc_host *host)
305{ 305{
306 class_device_del(&host->class_dev); 306 device_del(&host->class_dev);
307 307
308 spin_lock(&mmc_host_lock); 308 spin_lock(&mmc_host_lock);
309 idr_remove(&mmc_host_idr, host->index); 309 idr_remove(&mmc_host_idr, host->index);
@@ -315,7 +315,7 @@ void mmc_remove_host_sysfs(struct mmc_host *host)
315 */ 315 */
316void mmc_free_host_sysfs(struct mmc_host *host) 316void mmc_free_host_sysfs(struct mmc_host *host)
317{ 317{
318 class_device_put(&host->class_dev); 318 put_device(&host->class_dev);
319} 319}
320 320
321static struct workqueue_struct *workqueue; 321static struct workqueue_struct *workqueue;
diff --git a/drivers/mmc/mmci.c b/drivers/mmc/mmci.c
index 828503c4ee62..e9b80e920266 100644
--- a/drivers/mmc/mmci.c
+++ b/drivers/mmc/mmci.c
@@ -443,7 +443,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
443 } 443 }
444} 444}
445 445
446static struct mmc_host_ops mmci_ops = { 446static const struct mmc_host_ops mmci_ops = {
447 .request = mmci_request, 447 .request = mmci_request,
448 .set_ios = mmci_set_ios, 448 .set_ios = mmci_set_ios,
449}; 449};
diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c
index 762fa2895891..435d331e772a 100644
--- a/drivers/mmc/omap.c
+++ b/drivers/mmc/omap.c
@@ -38,7 +38,57 @@
38#include <asm/arch/fpga.h> 38#include <asm/arch/fpga.h>
39#include <asm/arch/tps65010.h> 39#include <asm/arch/tps65010.h>
40 40
41#include "omap.h" 41#define OMAP_MMC_REG_CMD 0x00
42#define OMAP_MMC_REG_ARGL 0x04
43#define OMAP_MMC_REG_ARGH 0x08
44#define OMAP_MMC_REG_CON 0x0c
45#define OMAP_MMC_REG_STAT 0x10
46#define OMAP_MMC_REG_IE 0x14
47#define OMAP_MMC_REG_CTO 0x18
48#define OMAP_MMC_REG_DTO 0x1c
49#define OMAP_MMC_REG_DATA 0x20
50#define OMAP_MMC_REG_BLEN 0x24
51#define OMAP_MMC_REG_NBLK 0x28
52#define OMAP_MMC_REG_BUF 0x2c
53#define OMAP_MMC_REG_SDIO 0x34
54#define OMAP_MMC_REG_REV 0x3c
55#define OMAP_MMC_REG_RSP0 0x40
56#define OMAP_MMC_REG_RSP1 0x44
57#define OMAP_MMC_REG_RSP2 0x48
58#define OMAP_MMC_REG_RSP3 0x4c
59#define OMAP_MMC_REG_RSP4 0x50
60#define OMAP_MMC_REG_RSP5 0x54
61#define OMAP_MMC_REG_RSP6 0x58
62#define OMAP_MMC_REG_RSP7 0x5c
63#define OMAP_MMC_REG_IOSR 0x60
64#define OMAP_MMC_REG_SYSC 0x64
65#define OMAP_MMC_REG_SYSS 0x68
66
67#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
68#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
69#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
70#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
71#define OMAP_MMC_STAT_A_FULL (1 << 10)
72#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
73#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
74#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
75#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
76#define OMAP_MMC_STAT_END_BUSY (1 << 4)
77#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
78#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
79#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
80
81#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
82#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
83
84/*
85 * Command types
86 */
87#define OMAP_MMC_CMDTYPE_BC 0
88#define OMAP_MMC_CMDTYPE_BCR 1
89#define OMAP_MMC_CMDTYPE_AC 2
90#define OMAP_MMC_CMDTYPE_ADTC 3
91
42 92
43#define DRIVER_NAME "mmci-omap" 93#define DRIVER_NAME "mmci-omap"
44#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) 94#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
@@ -60,8 +110,9 @@ struct mmc_omap_host {
60 unsigned char id; /* 16xx chips have 2 MMC blocks */ 110 unsigned char id; /* 16xx chips have 2 MMC blocks */
61 struct clk * iclk; 111 struct clk * iclk;
62 struct clk * fclk; 112 struct clk * fclk;
63 struct resource *res; 113 struct resource *mem_res;
64 void __iomem *base; 114 void __iomem *virt_base;
115 unsigned int phys_base;
65 int irq; 116 int irq;
66 unsigned char bus_mode; 117 unsigned char bus_mode;
67 unsigned char hw_bus_mode; 118 unsigned char hw_bus_mode;
@@ -191,16 +242,16 @@ mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
191 242
192 clk_enable(host->fclk); 243 clk_enable(host->fclk);
193 244
194 OMAP_MMC_WRITE(host->base, CTO, 200); 245 OMAP_MMC_WRITE(host, CTO, 200);
195 OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff); 246 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
196 OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16); 247 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
197 OMAP_MMC_WRITE(host->base, IE, 248 OMAP_MMC_WRITE(host, IE,
198 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | 249 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
199 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | 250 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
200 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | 251 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
201 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | 252 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
202 OMAP_MMC_STAT_END_OF_DATA); 253 OMAP_MMC_STAT_END_OF_DATA);
203 OMAP_MMC_WRITE(host->base, CMD, cmdreg); 254 OMAP_MMC_WRITE(host, CMD, cmdreg);
204} 255}
205 256
206static void 257static void
@@ -296,22 +347,22 @@ mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
296 if (cmd->flags & MMC_RSP_136) { 347 if (cmd->flags & MMC_RSP_136) {
297 /* response type 2 */ 348 /* response type 2 */
298 cmd->resp[3] = 349 cmd->resp[3] =
299 OMAP_MMC_READ(host->base, RSP0) | 350 OMAP_MMC_READ(host, RSP0) |
300 (OMAP_MMC_READ(host->base, RSP1) << 16); 351 (OMAP_MMC_READ(host, RSP1) << 16);
301 cmd->resp[2] = 352 cmd->resp[2] =
302 OMAP_MMC_READ(host->base, RSP2) | 353 OMAP_MMC_READ(host, RSP2) |
303 (OMAP_MMC_READ(host->base, RSP3) << 16); 354 (OMAP_MMC_READ(host, RSP3) << 16);
304 cmd->resp[1] = 355 cmd->resp[1] =
305 OMAP_MMC_READ(host->base, RSP4) | 356 OMAP_MMC_READ(host, RSP4) |
306 (OMAP_MMC_READ(host->base, RSP5) << 16); 357 (OMAP_MMC_READ(host, RSP5) << 16);
307 cmd->resp[0] = 358 cmd->resp[0] =
308 OMAP_MMC_READ(host->base, RSP6) | 359 OMAP_MMC_READ(host, RSP6) |
309 (OMAP_MMC_READ(host->base, RSP7) << 16); 360 (OMAP_MMC_READ(host, RSP7) << 16);
310 } else { 361 } else {
311 /* response types 1, 1b, 3, 4, 5, 6 */ 362 /* response types 1, 1b, 3, 4, 5, 6 */
312 cmd->resp[0] = 363 cmd->resp[0] =
313 OMAP_MMC_READ(host->base, RSP6) | 364 OMAP_MMC_READ(host, RSP6) |
314 (OMAP_MMC_READ(host->base, RSP7) << 16); 365 (OMAP_MMC_READ(host, RSP7) << 16);
315 } 366 }
316 } 367 }
317 368
@@ -354,9 +405,9 @@ mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
354 host->data->bytes_xfered += n; 405 host->data->bytes_xfered += n;
355 406
356 if (write) { 407 if (write) {
357 __raw_writesw(host->base + OMAP_MMC_REG_DATA, host->buffer, n); 408 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
358 } else { 409 } else {
359 __raw_readsw(host->base + OMAP_MMC_REG_DATA, host->buffer, n); 410 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
360 } 411 }
361} 412}
362 413
@@ -386,11 +437,11 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
386 int transfer_error; 437 int transfer_error;
387 438
388 if (host->cmd == NULL && host->data == NULL) { 439 if (host->cmd == NULL && host->data == NULL) {
389 status = OMAP_MMC_READ(host->base, STAT); 440 status = OMAP_MMC_READ(host, STAT);
390 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status); 441 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
391 if (status != 0) { 442 if (status != 0) {
392 OMAP_MMC_WRITE(host->base, STAT, status); 443 OMAP_MMC_WRITE(host, STAT, status);
393 OMAP_MMC_WRITE(host->base, IE, 0); 444 OMAP_MMC_WRITE(host, IE, 0);
394 } 445 }
395 return IRQ_HANDLED; 446 return IRQ_HANDLED;
396 } 447 }
@@ -399,8 +450,8 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
399 end_transfer = 0; 450 end_transfer = 0;
400 transfer_error = 0; 451 transfer_error = 0;
401 452
402 while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) { 453 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
403 OMAP_MMC_WRITE(host->base, STAT, status); 454 OMAP_MMC_WRITE(host, STAT, status);
404#ifdef CONFIG_MMC_DEBUG 455#ifdef CONFIG_MMC_DEBUG
405 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", 456 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
406 status, host->cmd != NULL ? host->cmd->opcode : -1); 457 status, host->cmd != NULL ? host->cmd->opcode : -1);
@@ -470,8 +521,8 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
470 521
471 if (status & OMAP_MMC_STAT_CARD_ERR) { 522 if (status & OMAP_MMC_STAT_CARD_ERR) {
472 if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) { 523 if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
473 u32 response = OMAP_MMC_READ(host->base, RSP6) 524 u32 response = OMAP_MMC_READ(host, RSP6)
474 | (OMAP_MMC_READ(host->base, RSP7) << 16); 525 | (OMAP_MMC_READ(host, RSP7) << 16);
475 /* STOP sometimes sets must-ignore bits */ 526 /* STOP sometimes sets must-ignore bits */
476 if (!(response & (R1_CC_ERROR 527 if (!(response & (R1_CC_ERROR
477 | R1_ILLEGAL_COMMAND 528 | R1_ILLEGAL_COMMAND
@@ -530,12 +581,6 @@ static void mmc_omap_switch_timer(unsigned long arg)
530 schedule_work(&host->switch_work); 581 schedule_work(&host->switch_work);
531} 582}
532 583
533/* FIXME: Handle card insertion and removal properly. Maybe use a mask
534 * for MMC state? */
535static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
536{
537}
538
539static void mmc_omap_switch_handler(void *data) 584static void mmc_omap_switch_handler(void *data)
540{ 585{
541 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 586 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
@@ -581,7 +626,7 @@ mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
581 int dst_port = 0; 626 int dst_port = 0;
582 int sync_dev = 0; 627 int sync_dev = 0;
583 628
584 data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA; 629 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
585 frame = data->blksz; 630 frame = data->blksz;
586 count = sg_dma_len(sg); 631 count = sg_dma_len(sg);
587 632
@@ -640,10 +685,9 @@ mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
640 } 685 }
641 686
642 /* Max limit for DMA frame count is 0xffff */ 687 /* Max limit for DMA frame count is 0xffff */
643 if (unlikely(count > 0xffff)) 688 BUG_ON(count > 0xffff);
644 BUG();
645 689
646 OMAP_MMC_WRITE(host->base, BUF, buf); 690 OMAP_MMC_WRITE(host, BUF, buf);
647 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16, 691 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
648 frame, count, OMAP_DMA_SYNC_FRAME, 692 frame, count, OMAP_DMA_SYNC_FRAME,
649 sync_dev, 0); 693 sync_dev, 0);
@@ -728,11 +772,11 @@ static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_reques
728{ 772{
729 u16 reg; 773 u16 reg;
730 774
731 reg = OMAP_MMC_READ(host->base, SDIO); 775 reg = OMAP_MMC_READ(host, SDIO);
732 reg &= ~(1 << 5); 776 reg &= ~(1 << 5);
733 OMAP_MMC_WRITE(host->base, SDIO, reg); 777 OMAP_MMC_WRITE(host, SDIO, reg);
734 /* Set maximum timeout */ 778 /* Set maximum timeout */
735 OMAP_MMC_WRITE(host->base, CTO, 0xff); 779 OMAP_MMC_WRITE(host, CTO, 0xff);
736} 780}
737 781
738static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) 782static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
@@ -746,14 +790,14 @@ static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_reque
746 timeout = req->data->timeout_clks + req->data->timeout_ns / 500; 790 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
747 791
748 /* Check if we need to use timeout multiplier register */ 792 /* Check if we need to use timeout multiplier register */
749 reg = OMAP_MMC_READ(host->base, SDIO); 793 reg = OMAP_MMC_READ(host, SDIO);
750 if (timeout > 0xffff) { 794 if (timeout > 0xffff) {
751 reg |= (1 << 5); 795 reg |= (1 << 5);
752 timeout /= 1024; 796 timeout /= 1024;
753 } else 797 } else
754 reg &= ~(1 << 5); 798 reg &= ~(1 << 5);
755 OMAP_MMC_WRITE(host->base, SDIO, reg); 799 OMAP_MMC_WRITE(host, SDIO, reg);
756 OMAP_MMC_WRITE(host->base, DTO, timeout); 800 OMAP_MMC_WRITE(host, DTO, timeout);
757} 801}
758 802
759static void 803static void
@@ -765,19 +809,18 @@ mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
765 809
766 host->data = data; 810 host->data = data;
767 if (data == NULL) { 811 if (data == NULL) {
768 OMAP_MMC_WRITE(host->base, BLEN, 0); 812 OMAP_MMC_WRITE(host, BLEN, 0);
769 OMAP_MMC_WRITE(host->base, NBLK, 0); 813 OMAP_MMC_WRITE(host, NBLK, 0);
770 OMAP_MMC_WRITE(host->base, BUF, 0); 814 OMAP_MMC_WRITE(host, BUF, 0);
771 host->dma_in_use = 0; 815 host->dma_in_use = 0;
772 set_cmd_timeout(host, req); 816 set_cmd_timeout(host, req);
773 return; 817 return;
774 } 818 }
775 819
776
777 block_size = data->blksz; 820 block_size = data->blksz;
778 821
779 OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1); 822 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
780 OMAP_MMC_WRITE(host->base, BLEN, block_size - 1); 823 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
781 set_data_timeout(host, req); 824 set_data_timeout(host, req);
782 825
783 /* cope with calling layer confusion; it issues "single 826 /* cope with calling layer confusion; it issues "single
@@ -819,7 +862,7 @@ mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
819 862
820 /* Revert to PIO? */ 863 /* Revert to PIO? */
821 if (!use_dma) { 864 if (!use_dma) {
822 OMAP_MMC_WRITE(host->base, BUF, 0x1f1f); 865 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
823 host->total_bytes_left = data->blocks * block_size; 866 host->total_bytes_left = data->blocks * block_size;
824 host->sg_len = sg_len; 867 host->sg_len = sg_len;
825 mmc_omap_sg_to_buf(host); 868 mmc_omap_sg_to_buf(host);
@@ -845,7 +888,6 @@ static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
845static void innovator_fpga_socket_power(int on) 888static void innovator_fpga_socket_power(int on)
846{ 889{
847#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) 890#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
848
849 if (on) { 891 if (on) {
850 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3), 892 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
851 OMAP1510_FPGA_POWER); 893 OMAP1510_FPGA_POWER);
@@ -871,8 +913,8 @@ static void mmc_omap_power(struct mmc_omap_host *host, int on)
871 /* GPIO 4 of TPS65010 sends SD_EN signal */ 913 /* GPIO 4 of TPS65010 sends SD_EN signal */
872 tps65010_set_gpio_out_value(GPIO4, HIGH); 914 tps65010_set_gpio_out_value(GPIO4, HIGH);
873 else if (cpu_is_omap24xx()) { 915 else if (cpu_is_omap24xx()) {
874 u16 reg = OMAP_MMC_READ(host->base, CON); 916 u16 reg = OMAP_MMC_READ(host, CON);
875 OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11)); 917 OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
876 } else 918 } else
877 if (host->power_pin >= 0) 919 if (host->power_pin >= 0)
878 omap_set_gpio_dataout(host->power_pin, 1); 920 omap_set_gpio_dataout(host->power_pin, 1);
@@ -884,8 +926,8 @@ static void mmc_omap_power(struct mmc_omap_host *host, int on)
884 else if (machine_is_omap_h3()) 926 else if (machine_is_omap_h3())
885 tps65010_set_gpio_out_value(GPIO4, LOW); 927 tps65010_set_gpio_out_value(GPIO4, LOW);
886 else if (cpu_is_omap24xx()) { 928 else if (cpu_is_omap24xx()) {
887 u16 reg = OMAP_MMC_READ(host->base, CON); 929 u16 reg = OMAP_MMC_READ(host, CON);
888 OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11)); 930 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
889 } else 931 } else
890 if (host->power_pin >= 0) 932 if (host->power_pin >= 0)
891 omap_set_gpio_dataout(host->power_pin, 0); 933 omap_set_gpio_dataout(host->power_pin, 0);
@@ -927,7 +969,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
927 case MMC_POWER_UP: 969 case MMC_POWER_UP:
928 case MMC_POWER_ON: 970 case MMC_POWER_ON:
929 mmc_omap_power(host, 1); 971 mmc_omap_power(host, 1);
930 dsor |= 1<<11; 972 dsor |= 1 << 11;
931 break; 973 break;
932 } 974 }
933 975
@@ -941,14 +983,14 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
941 * which results in the while loop below getting stuck. 983 * which results in the while loop below getting stuck.
942 * Writing to the CON register twice seems to do the trick. */ 984 * Writing to the CON register twice seems to do the trick. */
943 for (i = 0; i < 2; i++) 985 for (i = 0; i < 2; i++)
944 OMAP_MMC_WRITE(host->base, CON, dsor); 986 OMAP_MMC_WRITE(host, CON, dsor);
945 if (ios->power_mode == MMC_POWER_UP) { 987 if (ios->power_mode == MMC_POWER_UP) {
946 /* Send clock cycles, poll completion */ 988 /* Send clock cycles, poll completion */
947 OMAP_MMC_WRITE(host->base, IE, 0); 989 OMAP_MMC_WRITE(host, IE, 0);
948 OMAP_MMC_WRITE(host->base, STAT, 0xffff); 990 OMAP_MMC_WRITE(host, STAT, 0xffff);
949 OMAP_MMC_WRITE(host->base, CMD, 1<<7); 991 OMAP_MMC_WRITE(host, CMD, 1 << 7);
950 while (0 == (OMAP_MMC_READ(host->base, STAT) & 1)); 992 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
951 OMAP_MMC_WRITE(host->base, STAT, 1); 993 OMAP_MMC_WRITE(host, STAT, 1);
952 } 994 }
953 clk_disable(host->fclk); 995 clk_disable(host->fclk);
954} 996}
@@ -960,7 +1002,7 @@ static int mmc_omap_get_ro(struct mmc_host *mmc)
960 return host->wp_pin && omap_get_gpio_datain(host->wp_pin); 1002 return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
961} 1003}
962 1004
963static struct mmc_host_ops mmc_omap_ops = { 1005static const struct mmc_host_ops mmc_omap_ops = {
964 .request = mmc_omap_request, 1006 .request = mmc_omap_request,
965 .set_ios = mmc_omap_set_ios, 1007 .set_ios = mmc_omap_set_ios,
966 .get_ro = mmc_omap_get_ro, 1008 .get_ro = mmc_omap_get_ro,
@@ -971,25 +1013,29 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
971 struct omap_mmc_conf *minfo = pdev->dev.platform_data; 1013 struct omap_mmc_conf *minfo = pdev->dev.platform_data;
972 struct mmc_host *mmc; 1014 struct mmc_host *mmc;
973 struct mmc_omap_host *host = NULL; 1015 struct mmc_omap_host *host = NULL;
974 struct resource *r; 1016 struct resource *res;
975 int ret = 0; 1017 int ret = 0;
976 int irq; 1018 int irq;
977 1019
978 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1020 if (minfo == NULL) {
1021 dev_err(&pdev->dev, "platform data missing\n");
1022 return -ENXIO;
1023 }
1024
1025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
979 irq = platform_get_irq(pdev, 0); 1026 irq = platform_get_irq(pdev, 0);
980 if (!r || irq < 0) 1027 if (res == NULL || irq < 0)
981 return -ENXIO; 1028 return -ENXIO;
982 1029
983 r = request_mem_region(pdev->resource[0].start, 1030 res = request_mem_region(res->start, res->end - res->start + 1,
984 pdev->resource[0].end - pdev->resource[0].start + 1, 1031 pdev->name);
985 pdev->name); 1032 if (res == NULL)
986 if (!r)
987 return -EBUSY; 1033 return -EBUSY;
988 1034
989 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); 1035 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
990 if (!mmc) { 1036 if (mmc == NULL) {
991 ret = -ENOMEM; 1037 ret = -ENOMEM;
992 goto out; 1038 goto err_free_mem_region;
993 } 1039 }
994 1040
995 host = mmc_priv(mmc); 1041 host = mmc_priv(mmc);
@@ -1001,13 +1047,13 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
1001 host->dma_timer.data = (unsigned long) host; 1047 host->dma_timer.data = (unsigned long) host;
1002 1048
1003 host->id = pdev->id; 1049 host->id = pdev->id;
1004 host->res = r; 1050 host->mem_res = res;
1005 host->irq = irq; 1051 host->irq = irq;
1006 1052
1007 if (cpu_is_omap24xx()) { 1053 if (cpu_is_omap24xx()) {
1008 host->iclk = clk_get(&pdev->dev, "mmc_ick"); 1054 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1009 if (IS_ERR(host->iclk)) 1055 if (IS_ERR(host->iclk))
1010 goto out; 1056 goto err_free_mmc_host;
1011 clk_enable(host->iclk); 1057 clk_enable(host->iclk);
1012 } 1058 }
1013 1059
@@ -1018,7 +1064,7 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
1018 1064
1019 if (IS_ERR(host->fclk)) { 1065 if (IS_ERR(host->fclk)) {
1020 ret = PTR_ERR(host->fclk); 1066 ret = PTR_ERR(host->fclk);
1021 goto out; 1067 goto err_free_iclk;
1022 } 1068 }
1023 1069
1024 /* REVISIT: 1070 /* REVISIT:
@@ -1031,14 +1077,15 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
1031 host->use_dma = 1; 1077 host->use_dma = 1;
1032 host->dma_ch = -1; 1078 host->dma_ch = -1;
1033 1079
1034 host->irq = pdev->resource[1].start; 1080 host->irq = irq;
1035 host->base = (void __iomem*)IO_ADDRESS(r->start); 1081 host->phys_base = host->mem_res->start;
1082 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1036 1083
1037 mmc->ops = &mmc_omap_ops; 1084 mmc->ops = &mmc_omap_ops;
1038 mmc->f_min = 400000; 1085 mmc->f_min = 400000;
1039 mmc->f_max = 24000000; 1086 mmc->f_max = 24000000;
1040 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; 1087 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1041 mmc->caps = MMC_CAP_BYTEBLOCK; 1088 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1042 1089
1043 if (minfo->wire4) 1090 if (minfo->wire4)
1044 mmc->caps |= MMC_CAP_4_BIT_DATA; 1091 mmc->caps |= MMC_CAP_4_BIT_DATA;
@@ -1056,20 +1103,18 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
1056 if ((ret = omap_request_gpio(host->power_pin)) != 0) { 1103 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1057 dev_err(mmc_dev(host->mmc), 1104 dev_err(mmc_dev(host->mmc),
1058 "Unable to get GPIO pin for MMC power\n"); 1105 "Unable to get GPIO pin for MMC power\n");
1059 goto out; 1106 goto err_free_fclk;
1060 } 1107 }
1061 omap_set_gpio_direction(host->power_pin, 0); 1108 omap_set_gpio_direction(host->power_pin, 0);
1062 } 1109 }
1063 1110
1064 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); 1111 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1065 if (ret) 1112 if (ret)
1066 goto out; 1113 goto err_free_power_gpio;
1067 1114
1068 host->dev = &pdev->dev; 1115 host->dev = &pdev->dev;
1069 platform_set_drvdata(pdev, host); 1116 platform_set_drvdata(pdev, host);
1070 1117
1071 mmc_add_host(mmc);
1072
1073 if (host->switch_pin >= 0) { 1118 if (host->switch_pin >= 0) {
1074 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host); 1119 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
1075 init_timer(&host->switch_timer); 1120 init_timer(&host->switch_timer);
@@ -1107,10 +1152,11 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
1107 schedule_work(&host->switch_work); 1152 schedule_work(&host->switch_work);
1108 } 1153 }
1109 1154
1110no_switch: 1155 mmc_add_host(mmc);
1156
1111 return 0; 1157 return 0;
1112 1158
1113out: 1159no_switch:
1114 /* FIXME: Free other resources too. */ 1160 /* FIXME: Free other resources too. */
1115 if (host) { 1161 if (host) {
1116 if (host->iclk && !IS_ERR(host->iclk)) 1162 if (host->iclk && !IS_ERR(host->iclk))
@@ -1119,6 +1165,20 @@ out:
1119 clk_put(host->fclk); 1165 clk_put(host->fclk);
1120 mmc_free_host(host->mmc); 1166 mmc_free_host(host->mmc);
1121 } 1167 }
1168err_free_power_gpio:
1169 if (host->power_pin >= 0)
1170 omap_free_gpio(host->power_pin);
1171err_free_fclk:
1172 clk_put(host->fclk);
1173err_free_iclk:
1174 if (host->iclk != NULL) {
1175 clk_disable(host->iclk);
1176 clk_put(host->iclk);
1177 }
1178err_free_mmc_host:
1179 mmc_free_host(host->mmc);
1180err_free_mem_region:
1181 release_mem_region(res->start, res->end - res->start + 1);
1122 return ret; 1182 return ret;
1123} 1183}
1124 1184
@@ -1128,30 +1188,31 @@ static int mmc_omap_remove(struct platform_device *pdev)
1128 1188
1129 platform_set_drvdata(pdev, NULL); 1189 platform_set_drvdata(pdev, NULL);
1130 1190
1131 if (host) { 1191 BUG_ON(host == NULL);
1132 mmc_remove_host(host->mmc); 1192
1133 free_irq(host->irq, host); 1193 mmc_remove_host(host->mmc);
1134 1194 free_irq(host->irq, host);
1135 if (host->power_pin >= 0) 1195
1136 omap_free_gpio(host->power_pin); 1196 if (host->power_pin >= 0)
1137 if (host->switch_pin >= 0) { 1197 omap_free_gpio(host->power_pin);
1138 device_remove_file(&pdev->dev, &dev_attr_enable_poll); 1198 if (host->switch_pin >= 0) {
1139 device_remove_file(&pdev->dev, &dev_attr_cover_switch); 1199 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1140 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host); 1200 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1141 omap_free_gpio(host->switch_pin); 1201 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1142 host->switch_pin = -1; 1202 omap_free_gpio(host->switch_pin);
1143 del_timer_sync(&host->switch_timer); 1203 host->switch_pin = -1;
1144 flush_scheduled_work(); 1204 del_timer_sync(&host->switch_timer);
1145 } 1205 flush_scheduled_work();
1146 if (host->iclk && !IS_ERR(host->iclk))
1147 clk_put(host->iclk);
1148 if (host->fclk && !IS_ERR(host->fclk))
1149 clk_put(host->fclk);
1150 mmc_free_host(host->mmc);
1151 } 1206 }
1207 if (host->iclk && !IS_ERR(host->iclk))
1208 clk_put(host->iclk);
1209 if (host->fclk && !IS_ERR(host->fclk))
1210 clk_put(host->fclk);
1152 1211
1153 release_mem_region(pdev->resource[0].start, 1212 release_mem_region(pdev->resource[0].start,
1154 pdev->resource[0].end - pdev->resource[0].start + 1); 1213 pdev->resource[0].end - pdev->resource[0].start + 1);
1214
1215 mmc_free_host(host->mmc);
1155 1216
1156 return 0; 1217 return 0;
1157} 1218}
diff --git a/drivers/mmc/omap.h b/drivers/mmc/omap.h
deleted file mode 100644
index c954d355a5e3..000000000000
--- a/drivers/mmc/omap.h
+++ /dev/null
@@ -1,55 +0,0 @@
1#ifndef DRIVERS_MEDIA_MMC_OMAP_H
2#define DRIVERS_MEDIA_MMC_OMAP_H
3
4#define OMAP_MMC_REG_CMD 0x00
5#define OMAP_MMC_REG_ARGL 0x04
6#define OMAP_MMC_REG_ARGH 0x08
7#define OMAP_MMC_REG_CON 0x0c
8#define OMAP_MMC_REG_STAT 0x10
9#define OMAP_MMC_REG_IE 0x14
10#define OMAP_MMC_REG_CTO 0x18
11#define OMAP_MMC_REG_DTO 0x1c
12#define OMAP_MMC_REG_DATA 0x20
13#define OMAP_MMC_REG_BLEN 0x24
14#define OMAP_MMC_REG_NBLK 0x28
15#define OMAP_MMC_REG_BUF 0x2c
16#define OMAP_MMC_REG_SDIO 0x34
17#define OMAP_MMC_REG_REV 0x3c
18#define OMAP_MMC_REG_RSP0 0x40
19#define OMAP_MMC_REG_RSP1 0x44
20#define OMAP_MMC_REG_RSP2 0x48
21#define OMAP_MMC_REG_RSP3 0x4c
22#define OMAP_MMC_REG_RSP4 0x50
23#define OMAP_MMC_REG_RSP5 0x54
24#define OMAP_MMC_REG_RSP6 0x58
25#define OMAP_MMC_REG_RSP7 0x5c
26#define OMAP_MMC_REG_IOSR 0x60
27#define OMAP_MMC_REG_SYSC 0x64
28#define OMAP_MMC_REG_SYSS 0x68
29
30#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
31#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
32#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
33#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
34#define OMAP_MMC_STAT_A_FULL (1 << 10)
35#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
36#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
37#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
38#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
39#define OMAP_MMC_STAT_END_BUSY (1 << 4)
40#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
41#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
42#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
43
44#define OMAP_MMC_READ(base, reg) __raw_readw((base) + OMAP_MMC_REG_##reg)
45#define OMAP_MMC_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MMC_REG_##reg)
46
47/*
48 * Command types
49 */
50#define OMAP_MMC_CMDTYPE_BC 0
51#define OMAP_MMC_CMDTYPE_BCR 1
52#define OMAP_MMC_CMDTYPE_AC 2
53#define OMAP_MMC_CMDTYPE_ADTC 3
54
55#endif
diff --git a/drivers/mmc/pxamci.c b/drivers/mmc/pxamci.c
index a526698b8c91..471e9f4e0530 100644
--- a/drivers/mmc/pxamci.c
+++ b/drivers/mmc/pxamci.c
@@ -393,7 +393,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
393 host->clkrt, host->cmdat); 393 host->clkrt, host->cmdat);
394} 394}
395 395
396static struct mmc_host_ops pxamci_ops = { 396static const struct mmc_host_ops pxamci_ops = {
397 .request = pxamci_request, 397 .request = pxamci_request,
398 .get_ro = pxamci_get_ro, 398 .get_ro = pxamci_get_ro,
399 .set_ios = pxamci_set_ios, 399 .set_ios = pxamci_set_ios,
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 9a7d39b7cdbf..cd98117632d3 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -616,6 +616,7 @@ static void sdhci_finish_command(struct sdhci_host *host)
616static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 616static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
617{ 617{
618 int div; 618 int div;
619 u8 ctrl;
619 u16 clk; 620 u16 clk;
620 unsigned long timeout; 621 unsigned long timeout;
621 622
@@ -624,6 +625,13 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
624 625
625 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 626 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
626 627
628 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
629 if (clock > 25000000)
630 ctrl |= SDHCI_CTRL_HISPD;
631 else
632 ctrl &= ~SDHCI_CTRL_HISPD;
633 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
634
627 if (clock == 0) 635 if (clock == 0)
628 goto out; 636 goto out;
629 637
@@ -784,7 +792,7 @@ static int sdhci_get_ro(struct mmc_host *mmc)
784 return !(present & SDHCI_WRITE_PROTECT); 792 return !(present & SDHCI_WRITE_PROTECT);
785} 793}
786 794
787static struct mmc_host_ops sdhci_ops = { 795static const struct mmc_host_ops sdhci_ops = {
788 .request = sdhci_request, 796 .request = sdhci_request,
789 .set_ios = sdhci_set_ios, 797 .set_ios = sdhci_set_ios,
790 .get_ro = sdhci_get_ro, 798 .get_ro = sdhci_get_ro,
@@ -1291,6 +1299,13 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1291 else if (caps & SDHCI_CAN_VDD_180) 1299 else if (caps & SDHCI_CAN_VDD_180)
1292 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19; 1300 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1293 1301
1302 if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
1303 printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
1304 " but no high speed support.\n",
1305 host->slot_descr);
1306 mmc->f_max = 25000000;
1307 }
1308
1294 if (mmc->ocr_avail == 0) { 1309 if (mmc->ocr_avail == 0) {
1295 printk(KERN_ERR "%s: Hardware doesn't report any " 1310 printk(KERN_ERR "%s: Hardware doesn't report any "
1296 "support voltages.\n", host->slot_descr); 1311 "support voltages.\n", host->slot_descr);
diff --git a/drivers/mmc/sdhci.h b/drivers/mmc/sdhci.h
index 72a67937afe0..f9d1a0a6f03a 100644
--- a/drivers/mmc/sdhci.h
+++ b/drivers/mmc/sdhci.h
@@ -71,6 +71,7 @@
71#define SDHCI_HOST_CONTROL 0x28 71#define SDHCI_HOST_CONTROL 0x28
72#define SDHCI_CTRL_LED 0x01 72#define SDHCI_CTRL_LED 0x01
73#define SDHCI_CTRL_4BITBUS 0x02 73#define SDHCI_CTRL_4BITBUS 0x02
74#define SDHCI_CTRL_HISPD 0x04
74 75
75#define SDHCI_POWER_CONTROL 0x29 76#define SDHCI_POWER_CONTROL 0x29
76#define SDHCI_POWER_ON 0x01 77#define SDHCI_POWER_ON 0x01
@@ -138,6 +139,7 @@
138#define SDHCI_CLOCK_BASE_SHIFT 8 139#define SDHCI_CLOCK_BASE_SHIFT 8
139#define SDHCI_MAX_BLOCK_MASK 0x00030000 140#define SDHCI_MAX_BLOCK_MASK 0x00030000
140#define SDHCI_MAX_BLOCK_SHIFT 16 141#define SDHCI_MAX_BLOCK_SHIFT 16
142#define SDHCI_CAN_DO_HISPD 0x00200000
141#define SDHCI_CAN_DO_DMA 0x00400000 143#define SDHCI_CAN_DO_DMA 0x00400000
142#define SDHCI_CAN_VDD_330 0x01000000 144#define SDHCI_CAN_VDD_330 0x01000000
143#define SDHCI_CAN_VDD_300 0x02000000 145#define SDHCI_CAN_VDD_300 0x02000000
diff --git a/drivers/mmc/wbsd.c b/drivers/mmc/wbsd.c
index ced309b37a8f..7a282672f8e9 100644
--- a/drivers/mmc/wbsd.c
+++ b/drivers/mmc/wbsd.c
@@ -1021,7 +1021,7 @@ static int wbsd_get_ro(struct mmc_host *mmc)
1021 return csr & WBSD_WRPT; 1021 return csr & WBSD_WRPT;
1022} 1022}
1023 1023
1024static struct mmc_host_ops wbsd_ops = { 1024static const struct mmc_host_ops wbsd_ops = {
1025 .request = wbsd_request, 1025 .request = wbsd_request,
1026 .set_ios = wbsd_set_ios, 1026 .set_ios = wbsd_set_ios,
1027 .get_ro = wbsd_get_ro, 1027 .get_ro = wbsd_get_ro,
@@ -1488,7 +1488,7 @@ static void __devinit wbsd_request_dma(struct wbsd_host *host, int dma)
1488 /* 1488 /*
1489 * Translate the address to a physical address. 1489 * Translate the address to a physical address.
1490 */ 1490 */
1491 host->dma_addr = dma_map_single(host->mmc->dev, host->dma_buffer, 1491 host->dma_addr = dma_map_single(mmc_dev(host->mmc), host->dma_buffer,
1492 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL); 1492 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
1493 1493
1494 /* 1494 /*
@@ -1512,7 +1512,7 @@ kfree:
1512 */ 1512 */
1513 BUG_ON(1); 1513 BUG_ON(1);
1514 1514
1515 dma_unmap_single(host->mmc->dev, host->dma_addr, 1515 dma_unmap_single(mmc_dev(host->mmc), host->dma_addr,
1516 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL); 1516 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
1517 host->dma_addr = (dma_addr_t)NULL; 1517 host->dma_addr = (dma_addr_t)NULL;
1518 1518
@@ -1530,7 +1530,7 @@ err:
1530static void __devexit wbsd_release_dma(struct wbsd_host *host) 1530static void __devexit wbsd_release_dma(struct wbsd_host *host)
1531{ 1531{
1532 if (host->dma_addr) { 1532 if (host->dma_addr) {
1533 dma_unmap_single(host->mmc->dev, host->dma_addr, 1533 dma_unmap_single(mmc_dev(host->mmc), host->dma_addr,
1534 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL); 1534 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
1535 } 1535 }
1536 kfree(host->dma_buffer); 1536 kfree(host->dma_buffer);
diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c
index 7ea49a0d5ec3..296159ec5189 100644
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
@@ -1087,7 +1087,7 @@ static int inval_cache_and_wait_for_operation(
1087 } 1087 }
1088 spin_lock(chip->mutex); 1088 spin_lock(chip->mutex);
1089 1089
1090 if (chip->state != chip_state) { 1090 while (chip->state != chip_state) {
1091 /* Someone's suspended the operation: sleep */ 1091 /* Someone's suspended the operation: sleep */
1092 DECLARE_WAITQUEUE(wait, current); 1092 DECLARE_WAITQUEUE(wait, current);
1093 set_current_state(TASK_UNINTERRUPTIBLE); 1093 set_current_state(TASK_UNINTERRUPTIBLE);
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 24747bdc3e19..d132ed571f13 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -607,7 +607,7 @@ config MTD_BAST_MAXSIZE
607 default "4" 607 default "4"
608 608
609config MTD_SHARP_SL 609config MTD_SHARP_SL
610 bool "ROM maped on Sharp SL Series" 610 bool "ROM mapped on Sharp SL Series"
611 depends on MTD && ARCH_PXA 611 depends on MTD && ARCH_PXA
612 help 612 help
613 This enables access to the flash chip on the Sharp SL Series of PDAs. 613 This enables access to the flash chip on the Sharp SL Series of PDAs.
diff --git a/drivers/mtd/maps/cfi_flagadm.c b/drivers/mtd/maps/cfi_flagadm.c
index 92b5d883d7b0..65e5ee552010 100644
--- a/drivers/mtd/maps/cfi_flagadm.c
+++ b/drivers/mtd/maps/cfi_flagadm.c
@@ -80,7 +80,7 @@ struct mtd_partition flagadm_parts[] = {
80 .size = FLASH_PARTITION2_SIZE 80 .size = FLASH_PARTITION2_SIZE
81 }, 81 },
82 { 82 {
83 .name = "Persistant storage", 83 .name = "Persistent storage",
84 .offset = FLASH_PARTITION3_ADDR, 84 .offset = FLASH_PARTITION3_ADDR,
85 .size = FLASH_PARTITION3_SIZE 85 .size = FLASH_PARTITION3_SIZE
86 } 86 }
diff --git a/drivers/net/8390.c b/drivers/net/8390.c
index 3d1c599ac3cb..a82807641dcf 100644
--- a/drivers/net/8390.c
+++ b/drivers/net/8390.c
@@ -1,1104 +1,40 @@
1/* 8390.c: A general NS8390 ethernet driver core for linux. */ 1/* 8390 core for usual drivers */
2/*
3 Written 1992-94 by Donald Becker.
4
5 Copyright 1993 United States Government as represented by the
6 Director, National Security Agency.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16
17 This is the chip-specific code for many 8390-based ethernet adaptors.
18 This is not a complete driver, it must be combined with board-specific
19 code such as ne.c, wd.c, 3c503.c, etc.
20
21 Seeing how at least eight drivers use this code, (not counting the
22 PCMCIA ones either) it is easy to break some card by what seems like
23 a simple innocent change. Please contact me or Donald if you think
24 you have found something that needs changing. -- PG
25
26
27 Changelog:
28
29 Paul Gortmaker : remove set_bit lock, other cleanups.
30 Paul Gortmaker : add ei_get_8390_hdr() so we can pass skb's to
31 ei_block_input() for eth_io_copy_and_sum().
32 Paul Gortmaker : exchange static int ei_pingpong for a #define,
33 also add better Tx error handling.
34 Paul Gortmaker : rewrite Rx overrun handling as per NS specs.
35 Alexey Kuznetsov : use the 8390's six bit hash multicast filter.
36 Paul Gortmaker : tweak ANK's above multicast changes a bit.
37 Paul Gortmaker : update packet statistics for v2.1.x
38 Alan Cox : support arbitary stupid port mappings on the
39 68K Macintosh. Support >16bit I/O spaces
40 Paul Gortmaker : add kmod support for auto-loading of the 8390
41 module by all drivers that require it.
42 Alan Cox : Spinlocking work, added 'BUG_83C690'
43 Paul Gortmaker : Separate out Tx timeout code from Tx path.
44 Paul Gortmaker : Remove old unused single Tx buffer code.
45 Hayato Fujiwara : Add m32r support.
46 Paul Gortmaker : use skb_padto() instead of stack scratch area
47
48 Sources:
49 The National Semiconductor LAN Databook, and the 3Com 3c503 databook.
50
51 */
52 2
53static const char version[] = 3static const char version[] =
54 "8390.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n"; 4 "8390.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
55 5
56#include <linux/module.h> 6#include "lib8390.c"
57#include <linux/kernel.h>
58#include <linux/jiffies.h>
59#include <linux/fs.h>
60#include <linux/types.h>
61#include <linux/string.h>
62#include <linux/bitops.h>
63#include <asm/system.h>
64#include <asm/uaccess.h>
65#include <asm/io.h>
66#include <asm/irq.h>
67#include <linux/delay.h>
68#include <linux/errno.h>
69#include <linux/fcntl.h>
70#include <linux/in.h>
71#include <linux/interrupt.h>
72#include <linux/init.h>
73#include <linux/crc32.h>
74
75#include <linux/netdevice.h>
76#include <linux/etherdevice.h>
77
78#define NS8390_CORE
79#include "8390.h"
80
81#define BUG_83C690
82
83/* These are the operational function interfaces to board-specific
84 routines.
85 void reset_8390(struct net_device *dev)
86 Resets the board associated with DEV, including a hardware reset of
87 the 8390. This is only called when there is a transmit timeout, and
88 it is always followed by 8390_init().
89 void block_output(struct net_device *dev, int count, const unsigned char *buf,
90 int start_page)
91 Write the COUNT bytes of BUF to the packet buffer at START_PAGE. The
92 "page" value uses the 8390's 256-byte pages.
93 void get_8390_hdr(struct net_device *dev, struct e8390_hdr *hdr, int ring_page)
94 Read the 4 byte, page aligned 8390 header. *If* there is a
95 subsequent read, it will be of the rest of the packet.
96 void block_input(struct net_device *dev, int count, struct sk_buff *skb, int ring_offset)
97 Read COUNT bytes from the packet buffer into the skb data area. Start
98 reading from RING_OFFSET, the address as the 8390 sees it. This will always
99 follow the read of the 8390 header.
100*/
101#define ei_reset_8390 (ei_local->reset_8390)
102#define ei_block_output (ei_local->block_output)
103#define ei_block_input (ei_local->block_input)
104#define ei_get_8390_hdr (ei_local->get_8390_hdr)
105
106/* use 0 for production, 1 for verification, >2 for debug */
107#ifndef ei_debug
108int ei_debug = 1;
109#endif
110
111/* Index to functions. */
112static void ei_tx_intr(struct net_device *dev);
113static void ei_tx_err(struct net_device *dev);
114static void ei_tx_timeout(struct net_device *dev);
115static void ei_receive(struct net_device *dev);
116static void ei_rx_overrun(struct net_device *dev);
117
118/* Routines generic to NS8390-based boards. */
119static void NS8390_trigger_send(struct net_device *dev, unsigned int length,
120 int start_page);
121static void set_multicast_list(struct net_device *dev);
122static void do_set_multicast_list(struct net_device *dev);
123
124/*
125 * SMP and the 8390 setup.
126 *
127 * The 8390 isnt exactly designed to be multithreaded on RX/TX. There is
128 * a page register that controls bank and packet buffer access. We guard
129 * this with ei_local->page_lock. Nobody should assume or set the page other
130 * than zero when the lock is not held. Lock holders must restore page 0
131 * before unlocking. Even pure readers must take the lock to protect in
132 * page 0.
133 *
134 * To make life difficult the chip can also be very slow. We therefore can't
135 * just use spinlocks. For the longer lockups we disable the irq the device
136 * sits on and hold the lock. We must hold the lock because there is a dual
137 * processor case other than interrupts (get stats/set multicast list in
138 * parallel with each other and transmit).
139 *
140 * Note: in theory we can just disable the irq on the card _but_ there is
141 * a latency on SMP irq delivery. So we can easily go "disable irq" "sync irqs"
142 * enter lock, take the queued irq. So we waddle instead of flying.
143 *
144 * Finally by special arrangement for the purpose of being generally
145 * annoying the transmit function is called bh atomic. That places
146 * restrictions on the user context callers as disable_irq won't save
147 * them.
148 */
149
150
151 7
152/**
153 * ei_open - Open/initialize the board.
154 * @dev: network device to initialize
155 *
156 * This routine goes all-out, setting everything
157 * up anew at each open, even though many of these registers should only
158 * need to be set once at boot.
159 */
160int ei_open(struct net_device *dev) 8int ei_open(struct net_device *dev)
161{ 9{
162 unsigned long flags; 10 return __ei_open(dev);
163 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
164
165 /* The card I/O part of the driver (e.g. 3c503) can hook a Tx timeout
166 wrapper that does e.g. media check & then calls ei_tx_timeout. */
167 if (dev->tx_timeout == NULL)
168 dev->tx_timeout = ei_tx_timeout;
169 if (dev->watchdog_timeo <= 0)
170 dev->watchdog_timeo = TX_TIMEOUT;
171
172 /*
173 * Grab the page lock so we own the register set, then call
174 * the init function.
175 */
176
177 spin_lock_irqsave(&ei_local->page_lock, flags);
178 NS8390_init(dev, 1);
179 /* Set the flag before we drop the lock, That way the IRQ arrives
180 after its set and we get no silly warnings */
181 netif_start_queue(dev);
182 spin_unlock_irqrestore(&ei_local->page_lock, flags);
183 ei_local->irqlock = 0;
184 return 0;
185} 11}
186 12
187/**
188 * ei_close - shut down network device
189 * @dev: network device to close
190 *
191 * Opposite of ei_open(). Only used when "ifconfig <devname> down" is done.
192 */
193int ei_close(struct net_device *dev) 13int ei_close(struct net_device *dev)
194{ 14{
195 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev); 15 return __ei_close(dev);
196 unsigned long flags;
197
198 /*
199 * Hold the page lock during close
200 */
201
202 spin_lock_irqsave(&ei_local->page_lock, flags);
203 NS8390_init(dev, 0);
204 spin_unlock_irqrestore(&ei_local->page_lock, flags);
205 netif_stop_queue(dev);
206 return 0;
207}
208
209/**
210 * ei_tx_timeout - handle transmit time out condition
211 * @dev: network device which has apparently fallen asleep
212 *
213 * Called by kernel when device never acknowledges a transmit has
214 * completed (or failed) - i.e. never posted a Tx related interrupt.
215 */
216
217void ei_tx_timeout(struct net_device *dev)
218{
219 long e8390_base = dev->base_addr;
220 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
221 int txsr, isr, tickssofar = jiffies - dev->trans_start;
222 unsigned long flags;
223
224#if defined(CONFIG_M32R) && defined(CONFIG_SMP)
225 unsigned long icucr;
226
227 local_irq_save(flags);
228 icucr = inl(M32R_ICU_CR1_PORTL);
229 icucr |= M32R_ICUCR_ISMOD11;
230 outl(icucr, M32R_ICU_CR1_PORTL);
231 local_irq_restore(flags);
232#endif
233 ei_local->stat.tx_errors++;
234
235 spin_lock_irqsave(&ei_local->page_lock, flags);
236 txsr = inb(e8390_base+EN0_TSR);
237 isr = inb(e8390_base+EN0_ISR);
238 spin_unlock_irqrestore(&ei_local->page_lock, flags);
239
240 printk(KERN_DEBUG "%s: Tx timed out, %s TSR=%#2x, ISR=%#2x, t=%d.\n",
241 dev->name, (txsr & ENTSR_ABT) ? "excess collisions." :
242 (isr) ? "lost interrupt?" : "cable problem?", txsr, isr, tickssofar);
243
244 if (!isr && !ei_local->stat.tx_packets)
245 {
246 /* The 8390 probably hasn't gotten on the cable yet. */
247 ei_local->interface_num ^= 1; /* Try a different xcvr. */
248 }
249
250 /* Ugly but a reset can be slow, yet must be protected */
251
252 disable_irq_nosync_lockdep(dev->irq);
253 spin_lock(&ei_local->page_lock);
254
255 /* Try to restart the card. Perhaps the user has fixed something. */
256 ei_reset_8390(dev);
257 NS8390_init(dev, 1);
258
259 spin_unlock(&ei_local->page_lock);
260 enable_irq_lockdep(dev->irq);
261 netif_wake_queue(dev);
262}
263
264/**
265 * ei_start_xmit - begin packet transmission
266 * @skb: packet to be sent
267 * @dev: network device to which packet is sent
268 *
269 * Sends a packet to an 8390 network device.
270 */
271
272static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
273{
274 long e8390_base = dev->base_addr;
275 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
276 int send_length = skb->len, output_page;
277 unsigned long flags;
278 char buf[ETH_ZLEN];
279 char *data = skb->data;
280
281 if (skb->len < ETH_ZLEN) {
282 memset(buf, 0, ETH_ZLEN); /* more efficient than doing just the needed bits */
283 memcpy(buf, data, skb->len);
284 send_length = ETH_ZLEN;
285 data = buf;
286 }
287
288 /* Mask interrupts from the ethercard.
289 SMP: We have to grab the lock here otherwise the IRQ handler
290 on another CPU can flip window and race the IRQ mask set. We end
291 up trashing the mcast filter not disabling irqs if we don't lock */
292
293 spin_lock_irqsave(&ei_local->page_lock, flags);
294 outb_p(0x00, e8390_base + EN0_IMR);
295 spin_unlock_irqrestore(&ei_local->page_lock, flags);
296
297
298 /*
299 * Slow phase with lock held.
300 */
301
302 disable_irq_nosync_lockdep_irqsave(dev->irq, &flags);
303
304 spin_lock(&ei_local->page_lock);
305
306 ei_local->irqlock = 1;
307
308 /*
309 * We have two Tx slots available for use. Find the first free
310 * slot, and then perform some sanity checks. With two Tx bufs,
311 * you get very close to transmitting back-to-back packets. With
312 * only one Tx buf, the transmitter sits idle while you reload the
313 * card, leaving a substantial gap between each transmitted packet.
314 */
315
316 if (ei_local->tx1 == 0)
317 {
318 output_page = ei_local->tx_start_page;
319 ei_local->tx1 = send_length;
320 if (ei_debug && ei_local->tx2 > 0)
321 printk(KERN_DEBUG "%s: idle transmitter tx2=%d, lasttx=%d, txing=%d.\n",
322 dev->name, ei_local->tx2, ei_local->lasttx, ei_local->txing);
323 }
324 else if (ei_local->tx2 == 0)
325 {
326 output_page = ei_local->tx_start_page + TX_PAGES/2;
327 ei_local->tx2 = send_length;
328 if (ei_debug && ei_local->tx1 > 0)
329 printk(KERN_DEBUG "%s: idle transmitter, tx1=%d, lasttx=%d, txing=%d.\n",
330 dev->name, ei_local->tx1, ei_local->lasttx, ei_local->txing);
331 }
332 else
333 { /* We should never get here. */
334 if (ei_debug)
335 printk(KERN_DEBUG "%s: No Tx buffers free! tx1=%d tx2=%d last=%d\n",
336 dev->name, ei_local->tx1, ei_local->tx2, ei_local->lasttx);
337 ei_local->irqlock = 0;
338 netif_stop_queue(dev);
339 outb_p(ENISR_ALL, e8390_base + EN0_IMR);
340 spin_unlock(&ei_local->page_lock);
341 enable_irq_lockdep_irqrestore(dev->irq, &flags);
342 ei_local->stat.tx_errors++;
343 return 1;
344 }
345
346 /*
347 * Okay, now upload the packet and trigger a send if the transmitter
348 * isn't already sending. If it is busy, the interrupt handler will
349 * trigger the send later, upon receiving a Tx done interrupt.
350 */
351
352 ei_block_output(dev, send_length, data, output_page);
353
354 if (! ei_local->txing)
355 {
356 ei_local->txing = 1;
357 NS8390_trigger_send(dev, send_length, output_page);
358 dev->trans_start = jiffies;
359 if (output_page == ei_local->tx_start_page)
360 {
361 ei_local->tx1 = -1;
362 ei_local->lasttx = -1;
363 }
364 else
365 {
366 ei_local->tx2 = -1;
367 ei_local->lasttx = -2;
368 }
369 }
370 else ei_local->txqueue++;
371
372 if (ei_local->tx1 && ei_local->tx2)
373 netif_stop_queue(dev);
374 else
375 netif_start_queue(dev);
376
377 /* Turn 8390 interrupts back on. */
378 ei_local->irqlock = 0;
379 outb_p(ENISR_ALL, e8390_base + EN0_IMR);
380
381 spin_unlock(&ei_local->page_lock);
382 enable_irq_lockdep_irqrestore(dev->irq, &flags);
383
384 dev_kfree_skb (skb);
385 ei_local->stat.tx_bytes += send_length;
386
387 return 0;
388} 16}
389 17
390/**
391 * ei_interrupt - handle the interrupts from an 8390
392 * @irq: interrupt number
393 * @dev_id: a pointer to the net_device
394 *
395 * Handle the ether interface interrupts. We pull packets from
396 * the 8390 via the card specific functions and fire them at the networking
397 * stack. We also handle transmit completions and wake the transmit path if
398 * necessary. We also update the counters and do other housekeeping as
399 * needed.
400 */
401
402irqreturn_t ei_interrupt(int irq, void *dev_id) 18irqreturn_t ei_interrupt(int irq, void *dev_id)
403{ 19{
404 struct net_device *dev = dev_id; 20 return __ei_interrupt(irq, dev_id);
405 long e8390_base;
406 int interrupts, nr_serviced = 0;
407 struct ei_device *ei_local;
408
409 e8390_base = dev->base_addr;
410 ei_local = netdev_priv(dev);
411
412 /*
413 * Protect the irq test too.
414 */
415
416 spin_lock(&ei_local->page_lock);
417
418 if (ei_local->irqlock)
419 {
420#if 1 /* This might just be an interrupt for a PCI device sharing this line */
421 /* The "irqlock" check is only for testing. */
422 printk(ei_local->irqlock
423 ? "%s: Interrupted while interrupts are masked! isr=%#2x imr=%#2x.\n"
424 : "%s: Reentering the interrupt handler! isr=%#2x imr=%#2x.\n",
425 dev->name, inb_p(e8390_base + EN0_ISR),
426 inb_p(e8390_base + EN0_IMR));
427#endif
428 spin_unlock(&ei_local->page_lock);
429 return IRQ_NONE;
430 }
431
432 /* Change to page 0 and read the intr status reg. */
433 outb_p(E8390_NODMA+E8390_PAGE0, e8390_base + E8390_CMD);
434 if (ei_debug > 3)
435 printk(KERN_DEBUG "%s: interrupt(isr=%#2.2x).\n", dev->name,
436 inb_p(e8390_base + EN0_ISR));
437
438 /* !!Assumption!! -- we stay in page 0. Don't break this. */
439 while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0
440 && ++nr_serviced < MAX_SERVICE)
441 {
442 if (!netif_running(dev)) {
443 printk(KERN_WARNING "%s: interrupt from stopped card\n", dev->name);
444 /* rmk - acknowledge the interrupts */
445 outb_p(interrupts, e8390_base + EN0_ISR);
446 interrupts = 0;
447 break;
448 }
449 if (interrupts & ENISR_OVER)
450 ei_rx_overrun(dev);
451 else if (interrupts & (ENISR_RX+ENISR_RX_ERR))
452 {
453 /* Got a good (?) packet. */
454 ei_receive(dev);
455 }
456 /* Push the next to-transmit packet through. */
457 if (interrupts & ENISR_TX)
458 ei_tx_intr(dev);
459 else if (interrupts & ENISR_TX_ERR)
460 ei_tx_err(dev);
461
462 if (interrupts & ENISR_COUNTERS)
463 {
464 ei_local->stat.rx_frame_errors += inb_p(e8390_base + EN0_COUNTER0);
465 ei_local->stat.rx_crc_errors += inb_p(e8390_base + EN0_COUNTER1);
466 ei_local->stat.rx_missed_errors+= inb_p(e8390_base + EN0_COUNTER2);
467 outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */
468 }
469
470 /* Ignore any RDC interrupts that make it back to here. */
471 if (interrupts & ENISR_RDC)
472 {
473 outb_p(ENISR_RDC, e8390_base + EN0_ISR);
474 }
475
476 outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, e8390_base + E8390_CMD);
477 }
478
479 if (interrupts && ei_debug)
480 {
481 outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, e8390_base + E8390_CMD);
482 if (nr_serviced >= MAX_SERVICE)
483 {
484 /* 0xFF is valid for a card removal */
485 if(interrupts!=0xFF)
486 printk(KERN_WARNING "%s: Too much work at interrupt, status %#2.2x\n",
487 dev->name, interrupts);
488 outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */
489 } else {
490 printk(KERN_WARNING "%s: unknown interrupt %#2x\n", dev->name, interrupts);
491 outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */
492 }
493 }
494 spin_unlock(&ei_local->page_lock);
495 return IRQ_RETVAL(nr_serviced > 0);
496} 21}
497 22
498#ifdef CONFIG_NET_POLL_CONTROLLER 23#ifdef CONFIG_NET_POLL_CONTROLLER
499void ei_poll(struct net_device *dev) 24void ei_poll(struct net_device *dev)
500{ 25{
501 disable_irq_lockdep(dev->irq); 26 __ei_poll(dev);
502 ei_interrupt(dev->irq, dev);
503 enable_irq_lockdep(dev->irq);
504} 27}
505#endif 28#endif
506 29
507/**
508 * ei_tx_err - handle transmitter error
509 * @dev: network device which threw the exception
510 *
511 * A transmitter error has happened. Most likely excess collisions (which
512 * is a fairly normal condition). If the error is one where the Tx will
513 * have been aborted, we try and send another one right away, instead of
514 * letting the failed packet sit and collect dust in the Tx buffer. This
515 * is a much better solution as it avoids kernel based Tx timeouts, and
516 * an unnecessary card reset.
517 *
518 * Called with lock held.
519 */
520
521static void ei_tx_err(struct net_device *dev)
522{
523 long e8390_base = dev->base_addr;
524 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
525 unsigned char txsr = inb_p(e8390_base+EN0_TSR);
526 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU);
527
528#ifdef VERBOSE_ERROR_DUMP
529 printk(KERN_DEBUG "%s: transmitter error (%#2x): ", dev->name, txsr);
530 if (txsr & ENTSR_ABT)
531 printk("excess-collisions ");
532 if (txsr & ENTSR_ND)
533 printk("non-deferral ");
534 if (txsr & ENTSR_CRS)
535 printk("lost-carrier ");
536 if (txsr & ENTSR_FU)
537 printk("FIFO-underrun ");
538 if (txsr & ENTSR_CDH)
539 printk("lost-heartbeat ");
540 printk("\n");
541#endif
542
543 outb_p(ENISR_TX_ERR, e8390_base + EN0_ISR); /* Ack intr. */
544
545 if (tx_was_aborted)
546 ei_tx_intr(dev);
547 else
548 {
549 ei_local->stat.tx_errors++;
550 if (txsr & ENTSR_CRS) ei_local->stat.tx_carrier_errors++;
551 if (txsr & ENTSR_CDH) ei_local->stat.tx_heartbeat_errors++;
552 if (txsr & ENTSR_OWC) ei_local->stat.tx_window_errors++;
553 }
554}
555
556/**
557 * ei_tx_intr - transmit interrupt handler
558 * @dev: network device for which tx intr is handled
559 *
560 * We have finished a transmit: check for errors and then trigger the next
561 * packet to be sent. Called with lock held.
562 */
563
564static void ei_tx_intr(struct net_device *dev)
565{
566 long e8390_base = dev->base_addr;
567 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
568 int status = inb(e8390_base + EN0_TSR);
569
570 outb_p(ENISR_TX, e8390_base + EN0_ISR); /* Ack intr. */
571
572 /*
573 * There are two Tx buffers, see which one finished, and trigger
574 * the send of another one if it exists.
575 */
576 ei_local->txqueue--;
577
578 if (ei_local->tx1 < 0)
579 {
580 if (ei_local->lasttx != 1 && ei_local->lasttx != -1)
581 printk(KERN_ERR "%s: bogus last_tx_buffer %d, tx1=%d.\n",
582 ei_local->name, ei_local->lasttx, ei_local->tx1);
583 ei_local->tx1 = 0;
584 if (ei_local->tx2 > 0)
585 {
586 ei_local->txing = 1;
587 NS8390_trigger_send(dev, ei_local->tx2, ei_local->tx_start_page + 6);
588 dev->trans_start = jiffies;
589 ei_local->tx2 = -1,
590 ei_local->lasttx = 2;
591 }
592 else ei_local->lasttx = 20, ei_local->txing = 0;
593 }
594 else if (ei_local->tx2 < 0)
595 {
596 if (ei_local->lasttx != 2 && ei_local->lasttx != -2)
597 printk("%s: bogus last_tx_buffer %d, tx2=%d.\n",
598 ei_local->name, ei_local->lasttx, ei_local->tx2);
599 ei_local->tx2 = 0;
600 if (ei_local->tx1 > 0)
601 {
602 ei_local->txing = 1;
603 NS8390_trigger_send(dev, ei_local->tx1, ei_local->tx_start_page);
604 dev->trans_start = jiffies;
605 ei_local->tx1 = -1;
606 ei_local->lasttx = 1;
607 }
608 else
609 ei_local->lasttx = 10, ei_local->txing = 0;
610 }
611// else printk(KERN_WARNING "%s: unexpected TX-done interrupt, lasttx=%d.\n",
612// dev->name, ei_local->lasttx);
613
614 /* Minimize Tx latency: update the statistics after we restart TXing. */
615 if (status & ENTSR_COL)
616 ei_local->stat.collisions++;
617 if (status & ENTSR_PTX)
618 ei_local->stat.tx_packets++;
619 else
620 {
621 ei_local->stat.tx_errors++;
622 if (status & ENTSR_ABT)
623 {
624 ei_local->stat.tx_aborted_errors++;
625 ei_local->stat.collisions += 16;
626 }
627 if (status & ENTSR_CRS)
628 ei_local->stat.tx_carrier_errors++;
629 if (status & ENTSR_FU)
630 ei_local->stat.tx_fifo_errors++;
631 if (status & ENTSR_CDH)
632 ei_local->stat.tx_heartbeat_errors++;
633 if (status & ENTSR_OWC)
634 ei_local->stat.tx_window_errors++;
635 }
636 netif_wake_queue(dev);
637}
638
639/**
640 * ei_receive - receive some packets
641 * @dev: network device with which receive will be run
642 *
643 * We have a good packet(s), get it/them out of the buffers.
644 * Called with lock held.
645 */
646
647static void ei_receive(struct net_device *dev)
648{
649 long e8390_base = dev->base_addr;
650 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
651 unsigned char rxing_page, this_frame, next_frame;
652 unsigned short current_offset;
653 int rx_pkt_count = 0;
654 struct e8390_pkt_hdr rx_frame;
655 int num_rx_pages = ei_local->stop_page-ei_local->rx_start_page;
656
657 while (++rx_pkt_count < 10)
658 {
659 int pkt_len, pkt_stat;
660
661 /* Get the rx page (incoming packet pointer). */
662 outb_p(E8390_NODMA+E8390_PAGE1, e8390_base + E8390_CMD);
663 rxing_page = inb_p(e8390_base + EN1_CURPAG);
664 outb_p(E8390_NODMA+E8390_PAGE0, e8390_base + E8390_CMD);
665
666 /* Remove one frame from the ring. Boundary is always a page behind. */
667 this_frame = inb_p(e8390_base + EN0_BOUNDARY) + 1;
668 if (this_frame >= ei_local->stop_page)
669 this_frame = ei_local->rx_start_page;
670
671 /* Someday we'll omit the previous, iff we never get this message.
672 (There is at least one clone claimed to have a problem.)
673
674 Keep quiet if it looks like a card removal. One problem here
675 is that some clones crash in roughly the same way.
676 */
677 if (ei_debug > 0 && this_frame != ei_local->current_page && (this_frame!=0x0 || rxing_page!=0xFF))
678 printk(KERN_ERR "%s: mismatched read page pointers %2x vs %2x.\n",
679 dev->name, this_frame, ei_local->current_page);
680
681 if (this_frame == rxing_page) /* Read all the frames? */
682 break; /* Done for now */
683
684 current_offset = this_frame << 8;
685 ei_get_8390_hdr(dev, &rx_frame, this_frame);
686
687 pkt_len = rx_frame.count - sizeof(struct e8390_pkt_hdr);
688 pkt_stat = rx_frame.status;
689
690 next_frame = this_frame + 1 + ((pkt_len+4)>>8);
691
692 /* Check for bogosity warned by 3c503 book: the status byte is never
693 written. This happened a lot during testing! This code should be
694 cleaned up someday. */
695 if (rx_frame.next != next_frame
696 && rx_frame.next != next_frame + 1
697 && rx_frame.next != next_frame - num_rx_pages
698 && rx_frame.next != next_frame + 1 - num_rx_pages) {
699 ei_local->current_page = rxing_page;
700 outb(ei_local->current_page-1, e8390_base+EN0_BOUNDARY);
701 ei_local->stat.rx_errors++;
702 continue;
703 }
704
705 if (pkt_len < 60 || pkt_len > 1518)
706 {
707 if (ei_debug)
708 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x nxpg=%#2x.\n",
709 dev->name, rx_frame.count, rx_frame.status,
710 rx_frame.next);
711 ei_local->stat.rx_errors++;
712 ei_local->stat.rx_length_errors++;
713 }
714 else if ((pkt_stat & 0x0F) == ENRSR_RXOK)
715 {
716 struct sk_buff *skb;
717
718 skb = dev_alloc_skb(pkt_len+2);
719 if (skb == NULL)
720 {
721 if (ei_debug > 1)
722 printk(KERN_DEBUG "%s: Couldn't allocate a sk_buff of size %d.\n",
723 dev->name, pkt_len);
724 ei_local->stat.rx_dropped++;
725 break;
726 }
727 else
728 {
729 skb_reserve(skb,2); /* IP headers on 16 byte boundaries */
730 skb->dev = dev;
731 skb_put(skb, pkt_len); /* Make room */
732 ei_block_input(dev, pkt_len, skb, current_offset + sizeof(rx_frame));
733 skb->protocol=eth_type_trans(skb,dev);
734 netif_rx(skb);
735 dev->last_rx = jiffies;
736 ei_local->stat.rx_packets++;
737 ei_local->stat.rx_bytes += pkt_len;
738 if (pkt_stat & ENRSR_PHY)
739 ei_local->stat.multicast++;
740 }
741 }
742 else
743 {
744 if (ei_debug)
745 printk(KERN_DEBUG "%s: bogus packet: status=%#2x nxpg=%#2x size=%d\n",
746 dev->name, rx_frame.status, rx_frame.next,
747 rx_frame.count);
748 ei_local->stat.rx_errors++;
749 /* NB: The NIC counts CRC, frame and missed errors. */
750 if (pkt_stat & ENRSR_FO)
751 ei_local->stat.rx_fifo_errors++;
752 }
753 next_frame = rx_frame.next;
754
755 /* This _should_ never happen: it's here for avoiding bad clones. */
756 if (next_frame >= ei_local->stop_page) {
757 printk("%s: next frame inconsistency, %#2x\n", dev->name,
758 next_frame);
759 next_frame = ei_local->rx_start_page;
760 }
761 ei_local->current_page = next_frame;
762 outb_p(next_frame-1, e8390_base+EN0_BOUNDARY);
763 }
764
765 /* We used to also ack ENISR_OVER here, but that would sometimes mask
766 a real overrun, leaving the 8390 in a stopped state with rec'vr off. */
767 outb_p(ENISR_RX+ENISR_RX_ERR, e8390_base+EN0_ISR);
768 return;
769}
770
771/**
772 * ei_rx_overrun - handle receiver overrun
773 * @dev: network device which threw exception
774 *
775 * We have a receiver overrun: we have to kick the 8390 to get it started
776 * again. Problem is that you have to kick it exactly as NS prescribes in
777 * the updated datasheets, or "the NIC may act in an unpredictable manner."
778 * This includes causing "the NIC to defer indefinitely when it is stopped
779 * on a busy network." Ugh.
780 * Called with lock held. Don't call this with the interrupts off or your
781 * computer will hate you - it takes 10ms or so.
782 */
783
784static void ei_rx_overrun(struct net_device *dev)
785{
786 long e8390_base = dev->base_addr;
787 unsigned char was_txing, must_resend = 0;
788 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
789
790 /*
791 * Record whether a Tx was in progress and then issue the
792 * stop command.
793 */
794 was_txing = inb_p(e8390_base+E8390_CMD) & E8390_TRANS;
795 outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD);
796
797 if (ei_debug > 1)
798 printk(KERN_DEBUG "%s: Receiver overrun.\n", dev->name);
799 ei_local->stat.rx_over_errors++;
800
801 /*
802 * Wait a full Tx time (1.2ms) + some guard time, NS says 1.6ms total.
803 * Early datasheets said to poll the reset bit, but now they say that
804 * it "is not a reliable indicator and subsequently should be ignored."
805 * We wait at least 10ms.
806 */
807
808 mdelay(10);
809
810 /*
811 * Reset RBCR[01] back to zero as per magic incantation.
812 */
813 outb_p(0x00, e8390_base+EN0_RCNTLO);
814 outb_p(0x00, e8390_base+EN0_RCNTHI);
815
816 /*
817 * See if any Tx was interrupted or not. According to NS, this
818 * step is vital, and skipping it will cause no end of havoc.
819 */
820
821 if (was_txing)
822 {
823 unsigned char tx_completed = inb_p(e8390_base+EN0_ISR) & (ENISR_TX+ENISR_TX_ERR);
824 if (!tx_completed)
825 must_resend = 1;
826 }
827
828 /*
829 * Have to enter loopback mode and then restart the NIC before
830 * you are allowed to slurp packets up off the ring.
831 */
832 outb_p(E8390_TXOFF, e8390_base + EN0_TXCR);
833 outb_p(E8390_NODMA + E8390_PAGE0 + E8390_START, e8390_base + E8390_CMD);
834
835 /*
836 * Clear the Rx ring of all the debris, and ack the interrupt.
837 */
838 ei_receive(dev);
839 outb_p(ENISR_OVER, e8390_base+EN0_ISR);
840
841 /*
842 * Leave loopback mode, and resend any packet that got stopped.
843 */
844 outb_p(E8390_TXCONFIG, e8390_base + EN0_TXCR);
845 if (must_resend)
846 outb_p(E8390_NODMA + E8390_PAGE0 + E8390_START + E8390_TRANS, e8390_base + E8390_CMD);
847}
848
849/*
850 * Collect the stats. This is called unlocked and from several contexts.
851 */
852
853static struct net_device_stats *get_stats(struct net_device *dev)
854{
855 long ioaddr = dev->base_addr;
856 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
857 unsigned long flags;
858
859 /* If the card is stopped, just return the present stats. */
860 if (!netif_running(dev))
861 return &ei_local->stat;
862
863 spin_lock_irqsave(&ei_local->page_lock,flags);
864 /* Read the counter registers, assuming we are in page 0. */
865 ei_local->stat.rx_frame_errors += inb_p(ioaddr + EN0_COUNTER0);
866 ei_local->stat.rx_crc_errors += inb_p(ioaddr + EN0_COUNTER1);
867 ei_local->stat.rx_missed_errors+= inb_p(ioaddr + EN0_COUNTER2);
868 spin_unlock_irqrestore(&ei_local->page_lock, flags);
869
870 return &ei_local->stat;
871}
872
873/*
874 * Form the 64 bit 8390 multicast table from the linked list of addresses
875 * associated with this dev structure.
876 */
877
878static inline void make_mc_bits(u8 *bits, struct net_device *dev)
879{
880 struct dev_mc_list *dmi;
881
882 for (dmi=dev->mc_list; dmi; dmi=dmi->next)
883 {
884 u32 crc;
885 if (dmi->dmi_addrlen != ETH_ALEN)
886 {
887 printk(KERN_INFO "%s: invalid multicast address length given.\n", dev->name);
888 continue;
889 }
890 crc = ether_crc(ETH_ALEN, dmi->dmi_addr);
891 /*
892 * The 8390 uses the 6 most significant bits of the
893 * CRC to index the multicast table.
894 */
895 bits[crc>>29] |= (1<<((crc>>26)&7));
896 }
897}
898
899/**
900 * do_set_multicast_list - set/clear multicast filter
901 * @dev: net device for which multicast filter is adjusted
902 *
903 * Set or clear the multicast filter for this adaptor. May be called
904 * from a BH in 2.1.x. Must be called with lock held.
905 */
906
907static void do_set_multicast_list(struct net_device *dev)
908{
909 long e8390_base = dev->base_addr;
910 int i;
911 struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
912
913 if (!(dev->flags&(IFF_PROMISC|IFF_ALLMULTI)))
914 {
915 memset(ei_local->mcfilter, 0, 8);
916 if (dev->mc_list)
917 make_mc_bits(ei_local->mcfilter, dev);
918 }
919 else
920 memset(ei_local->mcfilter, 0xFF, 8); /* mcast set to accept-all */
921
922 /*
923 * DP8390 manuals don't specify any magic sequence for altering
924 * the multicast regs on an already running card. To be safe, we
925 * ensure multicast mode is off prior to loading up the new hash
926 * table. If this proves to be not enough, we can always resort
927 * to stopping the NIC, loading the table and then restarting.
928 *
929 * Bug Alert! The MC regs on the SMC 83C690 (SMC Elite and SMC
930 * Elite16) appear to be write-only. The NS 8390 data sheet lists
931 * them as r/w so this is a bug. The SMC 83C790 (SMC Ultra and
932 * Ultra32 EISA) appears to have this bug fixed.
933 */
934
935 if (netif_running(dev))
936 outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR);
937 outb_p(E8390_NODMA + E8390_PAGE1, e8390_base + E8390_CMD);
938 for(i = 0; i < 8; i++)
939 {
940 outb_p(ei_local->mcfilter[i], e8390_base + EN1_MULT_SHIFT(i));
941#ifndef BUG_83C690
942 if(inb_p(e8390_base + EN1_MULT_SHIFT(i))!=ei_local->mcfilter[i])
943 printk(KERN_ERR "Multicast filter read/write mismap %d\n",i);
944#endif
945 }
946 outb_p(E8390_NODMA + E8390_PAGE0, e8390_base + E8390_CMD);
947
948 if(dev->flags&IFF_PROMISC)
949 outb_p(E8390_RXCONFIG | 0x18, e8390_base + EN0_RXCR);
950 else if(dev->flags&IFF_ALLMULTI || dev->mc_list)
951 outb_p(E8390_RXCONFIG | 0x08, e8390_base + EN0_RXCR);
952 else
953 outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR);
954 }
955
956/*
957 * Called without lock held. This is invoked from user context and may
958 * be parallel to just about everything else. Its also fairly quick and
959 * not called too often. Must protect against both bh and irq users
960 */
961
962static void set_multicast_list(struct net_device *dev)
963{
964 unsigned long flags;
965 struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
966
967 spin_lock_irqsave(&ei_local->page_lock, flags);
968 do_set_multicast_list(dev);
969 spin_unlock_irqrestore(&ei_local->page_lock, flags);
970}
971
972/**
973 * ethdev_setup - init rest of 8390 device struct
974 * @dev: network device structure to init
975 *
976 * Initialize the rest of the 8390 device structure. Do NOT __init
977 * this, as it is used by 8390 based modular drivers too.
978 */
979
980static void ethdev_setup(struct net_device *dev)
981{
982 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
983 if (ei_debug > 1)
984 printk(version);
985
986 dev->hard_start_xmit = &ei_start_xmit;
987 dev->get_stats = get_stats;
988 dev->set_multicast_list = &set_multicast_list;
989
990 ether_setup(dev);
991
992 spin_lock_init(&ei_local->page_lock);
993}
994
995/**
996 * alloc_ei_netdev - alloc_etherdev counterpart for 8390
997 * @size: extra bytes to allocate
998 *
999 * Allocate 8390-specific net_device.
1000 */
1001struct net_device *__alloc_ei_netdev(int size) 30struct net_device *__alloc_ei_netdev(int size)
1002{ 31{
1003 return alloc_netdev(sizeof(struct ei_device) + size, "eth%d", 32 return ____alloc_ei_netdev(size);
1004 ethdev_setup);
1005} 33}
1006 34
1007
1008
1009
1010/* This page of functions should be 8390 generic */
1011/* Follow National Semi's recommendations for initializing the "NIC". */
1012
1013/**
1014 * NS8390_init - initialize 8390 hardware
1015 * @dev: network device to initialize
1016 * @startp: boolean. non-zero value to initiate chip processing
1017 *
1018 * Must be called with lock held.
1019 */
1020
1021void NS8390_init(struct net_device *dev, int startp) 35void NS8390_init(struct net_device *dev, int startp)
1022{ 36{
1023 long e8390_base = dev->base_addr; 37 return __NS8390_init(dev, startp);
1024 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
1025 int i;
1026 int endcfg = ei_local->word16
1027 ? (0x48 | ENDCFG_WTS | (ei_local->bigendian ? ENDCFG_BOS : 0))
1028 : 0x48;
1029
1030 if(sizeof(struct e8390_pkt_hdr)!=4)
1031 panic("8390.c: header struct mispacked\n");
1032 /* Follow National Semi's recommendations for initing the DP83902. */
1033 outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD); /* 0x21 */
1034 outb_p(endcfg, e8390_base + EN0_DCFG); /* 0x48 or 0x49 */
1035 /* Clear the remote byte count registers. */
1036 outb_p(0x00, e8390_base + EN0_RCNTLO);
1037 outb_p(0x00, e8390_base + EN0_RCNTHI);
1038 /* Set to monitor and loopback mode -- this is vital!. */
1039 outb_p(E8390_RXOFF, e8390_base + EN0_RXCR); /* 0x20 */
1040 outb_p(E8390_TXOFF, e8390_base + EN0_TXCR); /* 0x02 */
1041 /* Set the transmit page and receive ring. */
1042 outb_p(ei_local->tx_start_page, e8390_base + EN0_TPSR);
1043 ei_local->tx1 = ei_local->tx2 = 0;
1044 outb_p(ei_local->rx_start_page, e8390_base + EN0_STARTPG);
1045 outb_p(ei_local->stop_page-1, e8390_base + EN0_BOUNDARY); /* 3c503 says 0x3f,NS0x26*/
1046 ei_local->current_page = ei_local->rx_start_page; /* assert boundary+1 */
1047 outb_p(ei_local->stop_page, e8390_base + EN0_STOPPG);
1048 /* Clear the pending interrupts and mask. */
1049 outb_p(0xFF, e8390_base + EN0_ISR);
1050 outb_p(0x00, e8390_base + EN0_IMR);
1051
1052 /* Copy the station address into the DS8390 registers. */
1053
1054 outb_p(E8390_NODMA + E8390_PAGE1 + E8390_STOP, e8390_base+E8390_CMD); /* 0x61 */
1055 for(i = 0; i < 6; i++)
1056 {
1057 outb_p(dev->dev_addr[i], e8390_base + EN1_PHYS_SHIFT(i));
1058 if (ei_debug > 1 && inb_p(e8390_base + EN1_PHYS_SHIFT(i))!=dev->dev_addr[i])
1059 printk(KERN_ERR "Hw. address read/write mismap %d\n",i);
1060 }
1061
1062 outb_p(ei_local->rx_start_page, e8390_base + EN1_CURPAG);
1063 outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD);
1064
1065 netif_start_queue(dev);
1066 ei_local->tx1 = ei_local->tx2 = 0;
1067 ei_local->txing = 0;
1068
1069 if (startp)
1070 {
1071 outb_p(0xff, e8390_base + EN0_ISR);
1072 outb_p(ENISR_ALL, e8390_base + EN0_IMR);
1073 outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, e8390_base+E8390_CMD);
1074 outb_p(E8390_TXCONFIG, e8390_base + EN0_TXCR); /* xmit on. */
1075 /* 3c503 TechMan says rxconfig only after the NIC is started. */
1076 outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR); /* rx on, */
1077 do_set_multicast_list(dev); /* (re)load the mcast table */
1078 }
1079}
1080
1081/* Trigger a transmit start, assuming the length is valid.
1082 Always called with the page lock held */
1083
1084static void NS8390_trigger_send(struct net_device *dev, unsigned int length,
1085 int start_page)
1086{
1087 long e8390_base = dev->base_addr;
1088 struct ei_device *ei_local __attribute((unused)) = (struct ei_device *) netdev_priv(dev);
1089
1090 outb_p(E8390_NODMA+E8390_PAGE0, e8390_base+E8390_CMD);
1091
1092 if (inb_p(e8390_base + E8390_CMD) & E8390_TRANS)
1093 {
1094 printk(KERN_WARNING "%s: trigger_send() called with the transmitter busy.\n",
1095 dev->name);
1096 return;
1097 }
1098 outb_p(length & 0xff, e8390_base + EN0_TCNTLO);
1099 outb_p(length >> 8, e8390_base + EN0_TCNTHI);
1100 outb_p(start_page, e8390_base + EN0_TPSR);
1101 outb_p(E8390_NODMA+E8390_TRANS+E8390_START, e8390_base+E8390_CMD);
1102} 38}
1103 39
1104EXPORT_SYMBOL(ei_open); 40EXPORT_SYMBOL(ei_open);
diff --git a/drivers/net/8390.h b/drivers/net/8390.h
index f44f1220b3a5..414de5bd228f 100644
--- a/drivers/net/8390.h
+++ b/drivers/net/8390.h
@@ -107,35 +107,14 @@ struct ei_device {
107 * - removed AMIGA_PCMCIA from this list, handled as ISA io now 107 * - removed AMIGA_PCMCIA from this list, handled as ISA io now
108 */ 108 */
109 109
110#if defined(CONFIG_MAC) || \ 110#ifndef ei_inb
111 defined(CONFIG_ZORRO8390) || defined(CONFIG_ZORRO8390_MODULE) || \ 111#define ei_inb(_p) inb(_p)
112 defined(CONFIG_HYDRA) || defined(CONFIG_HYDRA_MODULE) 112#define ei_outb(_v,_p) outb(_v,_p)
113#define EI_SHIFT(x) (ei_local->reg_offset[x]) 113#define ei_inb_p(_p) inb_p(_p)
114#undef inb 114#define ei_outb_p(_v,_p) outb_p(_v,_p)
115#undef inb_p 115#endif
116#undef outb 116
117#undef outb_p 117#ifndef EI_SHIFT
118
119#define inb(port) in_8(port)
120#define outb(val,port) out_8(port,val)
121#define inb_p(port) in_8(port)
122#define outb_p(val,port) out_8(port,val)
123
124#elif defined(CONFIG_ARM_ETHERH) || defined(CONFIG_ARM_ETHERH_MODULE)
125#define EI_SHIFT(x) (ei_local->reg_offset[x])
126#undef inb
127#undef inb_p
128#undef outb
129#undef outb_p
130
131#define inb(_p) readb(_p)
132#define outb(_v,_p) writeb(_v,_p)
133#define inb_p(_p) inb(_p)
134#define outb_p(_v,_p) outb(_v,_p)
135
136#elif defined(CONFIG_NE_H8300) || defined(CONFIG_NE_H8300_MODULE)
137#define EI_SHIFT(x) (ei_local->reg_offset[x])
138#else
139#define EI_SHIFT(x) (x) 118#define EI_SHIFT(x) (x)
140#endif 119#endif
141 120
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6e863aa9894c..9de0eed6755b 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -32,7 +32,7 @@ config IFB
32 tristate "Intermediate Functional Block support" 32 tristate "Intermediate Functional Block support"
33 depends on NET_CLS_ACT 33 depends on NET_CLS_ACT
34 ---help--- 34 ---help---
35 This is an intermidiate driver that allows sharing of 35 This is an intermediate driver that allows sharing of
36 resources. 36 resources.
37 To compile this driver as a module, choose M here: the module 37 To compile this driver as a module, choose M here: the module
38 will be called ifb. If you want to use more than one ifb 38 will be called ifb. If you want to use more than one ifb
@@ -188,6 +188,17 @@ config MII
188 or internal device. It is safe to say Y or M here even if your 188 or internal device. It is safe to say Y or M here even if your
189 ethernet card lack MII. 189 ethernet card lack MII.
190 190
191config MACB
192 tristate "Atmel MACB support"
193 depends on NET_ETHERNET && AVR32
194 select MII
195 help
196 The Atmel MACB ethernet interface is found on many AT32 and AT91
197 parts. Say Y to include support for the MACB chip.
198
199 To compile this driver as a module, choose M here: the module
200 will be called macb.
201
191source "drivers/net/arm/Kconfig" 202source "drivers/net/arm/Kconfig"
192 203
193config MACE 204config MACE
@@ -1769,8 +1780,8 @@ config VIA_RHINE_NAPI
1769 information. 1780 information.
1770 1781
1771config LAN_SAA9730 1782config LAN_SAA9730
1772 bool "Philips SAA9730 Ethernet support (EXPERIMENTAL)" 1783 bool "Philips SAA9730 Ethernet support"
1773 depends on NET_PCI && EXPERIMENTAL && MIPS 1784 depends on NET_PCI && PCI && MIPS_ATLAS
1774 help 1785 help
1775 The SAA9730 is a combined multimedia and peripheral controller used 1786 The SAA9730 is a combined multimedia and peripheral controller used
1776 in thin clients, Internet access terminals, and diskless 1787 in thin clients, Internet access terminals, and diskless
@@ -2136,7 +2147,7 @@ config SK98LIN
2136 This driver supports the original Yukon chipset. A cleaner driver is 2147 This driver supports the original Yukon chipset. A cleaner driver is
2137 also available (skge) which seems to work better than this one. 2148 also available (skge) which seems to work better than this one.
2138 2149
2139 This driver does not support the newer Yukon2 chipset. A seperate 2150 This driver does not support the newer Yukon2 chipset. A separate
2140 driver, sky2, is provided to support Yukon2-based adapters. 2151 driver, sky2, is provided to support Yukon2-based adapters.
2141 2152
2142 The following adapters are supported by this driver: 2153 The following adapters are supported by this driver:
@@ -2251,6 +2262,14 @@ config SPIDER_NET
2251 This driver supports the Gigabit Ethernet chips present on the 2262 This driver supports the Gigabit Ethernet chips present on the
2252 Cell Processor-Based Blades from IBM. 2263 Cell Processor-Based Blades from IBM.
2253 2264
2265config TSI108_ETH
2266 tristate "Tundra TSI108 gigabit Ethernet support"
2267 depends on TSI108_BRIDGE
2268 help
2269 This driver supports Tundra TSI108 gigabit Ethernet ports.
2270 To compile this driver as a module, choose M here: the module
2271 will be called tsi108_eth.
2272
2254config GIANFAR 2273config GIANFAR
2255 tristate "Gianfar Ethernet" 2274 tristate "Gianfar Ethernet"
2256 depends on 85xx || 83xx || PPC_86xx 2275 depends on 85xx || 83xx || PPC_86xx
@@ -2341,10 +2360,11 @@ menu "Ethernet (10000 Mbit)"
2341config CHELSIO_T1 2360config CHELSIO_T1
2342 tristate "Chelsio 10Gb Ethernet support" 2361 tristate "Chelsio 10Gb Ethernet support"
2343 depends on PCI 2362 depends on PCI
2363 select CRC32
2344 help 2364 help
2345 This driver supports Chelsio N110 and N210 models 10Gb Ethernet 2365 This driver supports Chelsio gigabit and 10-gigabit
2346 cards. More information about adapter features and performance 2366 Ethernet cards. More information about adapter features and
2347 tuning is in <file:Documentation/networking/cxgb.txt>. 2367 performance tuning is in <file:Documentation/networking/cxgb.txt>.
2348 2368
2349 For general information about Chelsio and our products, visit 2369 For general information about Chelsio and our products, visit
2350 our website at <http://www.chelsio.com>. 2370 our website at <http://www.chelsio.com>.
@@ -2357,6 +2377,13 @@ config CHELSIO_T1
2357 To compile this driver as a module, choose M here: the module 2377 To compile this driver as a module, choose M here: the module
2358 will be called cxgb. 2378 will be called cxgb.
2359 2379
2380config CHELSIO_T1_1G
2381 bool "Chelsio gigabit Ethernet support"
2382 depends on CHELSIO_T1
2383 help
2384 Enables support for Chelsio's gigabit Ethernet PCI cards. If you
2385 are using only 10G cards say 'N' here.
2386
2360config EHEA 2387config EHEA
2361 tristate "eHEA Ethernet support" 2388 tristate "eHEA Ethernet support"
2362 depends on IBMEBUS 2389 depends on IBMEBUS
@@ -2447,6 +2474,12 @@ config MYRI10GE
2447 <file:Documentation/networking/net-modules.txt>. The module 2474 <file:Documentation/networking/net-modules.txt>. The module
2448 will be called myri10ge. 2475 will be called myri10ge.
2449 2476
2477config NETXEN_NIC
2478 tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC"
2479 depends on PCI
2480 help
2481 This enables the support for NetXen's Gigabit Ethernet card.
2482
2450endmenu 2483endmenu
2451 2484
2452source "drivers/net/tokenring/Kconfig" 2485source "drivers/net/tokenring/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index f270bc49e571..4c0d4e5ce42b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -82,7 +82,7 @@ obj-$(CONFIG_HAMACHI) += hamachi.o
82obj-$(CONFIG_NET) += Space.o loopback.o 82obj-$(CONFIG_NET) += Space.o loopback.o
83obj-$(CONFIG_SEEQ8005) += seeq8005.o 83obj-$(CONFIG_SEEQ8005) += seeq8005.o
84obj-$(CONFIG_NET_SB1000) += sb1000.o 84obj-$(CONFIG_NET_SB1000) += sb1000.o
85obj-$(CONFIG_MAC8390) += mac8390.o 8390.o 85obj-$(CONFIG_MAC8390) += mac8390.o
86obj-$(CONFIG_APNE) += apne.o 8390.o 86obj-$(CONFIG_APNE) += apne.o 8390.o
87obj-$(CONFIG_PCMCIA_PCNET) += 8390.o 87obj-$(CONFIG_PCMCIA_PCNET) += 8390.o
88obj-$(CONFIG_SHAPER) += shaper.o 88obj-$(CONFIG_SHAPER) += shaper.o
@@ -90,7 +90,6 @@ obj-$(CONFIG_HP100) += hp100.o
90obj-$(CONFIG_SMC9194) += smc9194.o 90obj-$(CONFIG_SMC9194) += smc9194.o
91obj-$(CONFIG_FEC) += fec.o 91obj-$(CONFIG_FEC) += fec.o
92obj-$(CONFIG_68360_ENET) += 68360enet.o 92obj-$(CONFIG_68360_ENET) += 68360enet.o
93obj-$(CONFIG_ARM_ETHERH) += 8390.o
94obj-$(CONFIG_WD80x3) += wd.o 8390.o 93obj-$(CONFIG_WD80x3) += wd.o 8390.o
95obj-$(CONFIG_EL2) += 3c503.o 8390.o 94obj-$(CONFIG_EL2) += 3c503.o 8390.o
96obj-$(CONFIG_NE2000) += ne.o 8390.o 95obj-$(CONFIG_NE2000) += ne.o 8390.o
@@ -107,8 +106,9 @@ obj-$(CONFIG_NE3210) += ne3210.o 8390.o
107obj-$(CONFIG_NET_SB1250_MAC) += sb1250-mac.o 106obj-$(CONFIG_NET_SB1250_MAC) += sb1250-mac.o
108obj-$(CONFIG_B44) += b44.o 107obj-$(CONFIG_B44) += b44.o
109obj-$(CONFIG_FORCEDETH) += forcedeth.o 108obj-$(CONFIG_FORCEDETH) += forcedeth.o
110obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o 109obj-$(CONFIG_NE_H8300) += ne-h8300.o
111 110
111obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
112obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o 112obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
113obj-$(CONFIG_QLA3XXX) += qla3xxx.o 113obj-$(CONFIG_QLA3XXX) += qla3xxx.o
114 114
@@ -165,7 +165,7 @@ obj-$(CONFIG_BVME6000_NET) += 82596.o
165obj-$(CONFIG_LP486E) += lp486e.o 165obj-$(CONFIG_LP486E) += lp486e.o
166 166
167obj-$(CONFIG_ETH16I) += eth16i.o 167obj-$(CONFIG_ETH16I) += eth16i.o
168obj-$(CONFIG_ZORRO8390) += zorro8390.o 8390.o 168obj-$(CONFIG_ZORRO8390) += zorro8390.o
169obj-$(CONFIG_HPLANCE) += hplance.o 7990.o 169obj-$(CONFIG_HPLANCE) += hplance.o 7990.o
170obj-$(CONFIG_MVME147_NET) += mvme147.o 7990.o 170obj-$(CONFIG_MVME147_NET) += mvme147.o 7990.o
171obj-$(CONFIG_EQUALIZER) += eql.o 171obj-$(CONFIG_EQUALIZER) += eql.o
@@ -178,7 +178,7 @@ obj-$(CONFIG_ATARILANCE) += atarilance.o
178obj-$(CONFIG_ATARI_BIONET) += atari_bionet.o 178obj-$(CONFIG_ATARI_BIONET) += atari_bionet.o
179obj-$(CONFIG_ATARI_PAMSNET) += atari_pamsnet.o 179obj-$(CONFIG_ATARI_PAMSNET) += atari_pamsnet.o
180obj-$(CONFIG_A2065) += a2065.o 180obj-$(CONFIG_A2065) += a2065.o
181obj-$(CONFIG_HYDRA) += hydra.o 8390.o 181obj-$(CONFIG_HYDRA) += hydra.o
182obj-$(CONFIG_ARIADNE) += ariadne.o 182obj-$(CONFIG_ARIADNE) += ariadne.o
183obj-$(CONFIG_CS89x0) += cs89x0.o 183obj-$(CONFIG_CS89x0) += cs89x0.o
184obj-$(CONFIG_MACSONIC) += macsonic.o 184obj-$(CONFIG_MACSONIC) += macsonic.o
@@ -197,6 +197,8 @@ obj-$(CONFIG_SMC911X) += smc911x.o
197obj-$(CONFIG_DM9000) += dm9000.o 197obj-$(CONFIG_DM9000) += dm9000.o
198obj-$(CONFIG_FEC_8XX) += fec_8xx/ 198obj-$(CONFIG_FEC_8XX) += fec_8xx/
199 199
200obj-$(CONFIG_MACB) += macb.o
201
200obj-$(CONFIG_ARM) += arm/ 202obj-$(CONFIG_ARM) += arm/
201obj-$(CONFIG_DEV_APPLETALK) += appletalk/ 203obj-$(CONFIG_DEV_APPLETALK) += appletalk/
202obj-$(CONFIG_TR) += tokenring/ 204obj-$(CONFIG_TR) += tokenring/
@@ -214,3 +216,4 @@ obj-$(CONFIG_NETCONSOLE) += netconsole.o
214 216
215obj-$(CONFIG_FS_ENET) += fs_enet/ 217obj-$(CONFIG_FS_ENET) += fs_enet/
216 218
219obj-$(CONFIG_NETXEN_NIC) += netxen/
diff --git a/drivers/net/Space.c b/drivers/net/Space.c
index a67f5efc983f..602ed31a5dd9 100644
--- a/drivers/net/Space.c
+++ b/drivers/net/Space.c
@@ -33,7 +33,6 @@
33#include <linux/errno.h> 33#include <linux/errno.h>
34#include <linux/init.h> 34#include <linux/init.h>
35#include <linux/netlink.h> 35#include <linux/netlink.h>
36#include <linux/divert.h>
37 36
38/* A unified ethernet device probe. This is the easiest way to have every 37/* A unified ethernet device probe. This is the easiest way to have every
39 ethernet adaptor have the name "eth[0123...]". 38 ethernet adaptor have the name "eth[0123...]".
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c
index ef65e5917c8f..18896f24d407 100644
--- a/drivers/net/amd8111e.c
+++ b/drivers/net/amd8111e.c
@@ -1490,32 +1490,7 @@ static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1490 buf[12] = readl(mmio + STAT0); 1490 buf[12] = readl(mmio + STAT0);
1491} 1491}
1492 1492
1493/*
1494amd8111e crc generator implementation is different from the kernel
1495ether_crc() function.
1496*/
1497static int amd8111e_ether_crc(int len, char* mac_addr)
1498{
1499 int i,byte;
1500 unsigned char octet;
1501 u32 crc= INITCRC;
1502
1503 for(byte=0; byte < len; byte++){
1504 octet = mac_addr[byte];
1505 for( i=0;i < 8; i++){
1506 /*If the next bit form the input stream is 1,subtract the divisor (CRC32) from the dividend(crc).*/
1507 if( (octet & 0x1) ^ (crc & 0x1) ){
1508 crc >>= 1;
1509 crc ^= CRC32;
1510 }
1511 else
1512 crc >>= 1;
1513 1493
1514 octet >>= 1;
1515 }
1516 }
1517 return crc;
1518}
1519/* 1494/*
1520This function sets promiscuos mode, all-multi mode or the multicast address 1495This function sets promiscuos mode, all-multi mode or the multicast address
1521list to the device. 1496list to the device.
@@ -1556,7 +1531,7 @@ static void amd8111e_set_multicast_list(struct net_device *dev)
1556 mc_filter[1] = mc_filter[0] = 0; 1531 mc_filter[1] = mc_filter[0] = 0;
1557 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count; 1532 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1558 i++, mc_ptr = mc_ptr->next) { 1533 i++, mc_ptr = mc_ptr->next) {
1559 bit_num = ( amd8111e_ether_crc(ETH_ALEN,mc_ptr->dmi_addr) >> 26 ) & 0x3f; 1534 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1560 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31); 1535 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1561 } 1536 }
1562 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF); 1537 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
diff --git a/drivers/net/amd8111e.h b/drivers/net/amd8111e.h
index 7727d328f65e..2007510c4eb6 100644
--- a/drivers/net/amd8111e.h
+++ b/drivers/net/amd8111e.h
@@ -651,10 +651,6 @@ typedef enum {
651/* driver ioctl parameters */ 651/* driver ioctl parameters */
652#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32) 652#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
653 653
654/* crc generator constants */
655#define CRC32 0xedb88320
656#define INITCRC 0xFFFFFFFF
657
658/* amd8111e desriptor format */ 654/* amd8111e desriptor format */
659 655
660struct amd8111e_tx_dr{ 656struct amd8111e_tx_dr{
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c
index 4ae98970b282..f3faa4fe58e7 100644
--- a/drivers/net/arm/etherh.c
+++ b/drivers/net/arm/etherh.c
@@ -52,7 +52,12 @@
52#include <asm/ecard.h> 52#include <asm/ecard.h>
53#include <asm/io.h> 53#include <asm/io.h>
54 54
55#include "../8390.h" 55#define EI_SHIFT(x) (ei_local->reg_offset[x])
56
57#define ei_inb(_p) readb((void __iomem *)_p)
58#define ei_outb(_v,_p) writeb(_v,(void __iomem *)_p)
59#define ei_inb_p(_p) readb((void __iomem *)_p)
60#define ei_outb_p(_v,_p) writeb(_v,(void __iomem *)_p)
56 61
57#define NET_DEBUG 0 62#define NET_DEBUG 0
58#define DEBUG_INIT 2 63#define DEBUG_INIT 2
@@ -60,6 +65,11 @@
60#define DRV_NAME "etherh" 65#define DRV_NAME "etherh"
61#define DRV_VERSION "1.11" 66#define DRV_VERSION "1.11"
62 67
68static char version[] __initdata =
69 "EtherH/EtherM Driver (c) 2002-2004 Russell King " DRV_VERSION "\n";
70
71#include "../lib8390.c"
72
63static unsigned int net_debug = NET_DEBUG; 73static unsigned int net_debug = NET_DEBUG;
64 74
65struct etherh_priv { 75struct etherh_priv {
@@ -87,9 +97,6 @@ MODULE_AUTHOR("Russell King");
87MODULE_DESCRIPTION("EtherH/EtherM driver"); 97MODULE_DESCRIPTION("EtherH/EtherM driver");
88MODULE_LICENSE("GPL"); 98MODULE_LICENSE("GPL");
89 99
90static char version[] __initdata =
91 "EtherH/EtherM Driver (c) 2002-2004 Russell King " DRV_VERSION "\n";
92
93#define ETHERH500_DATAPORT 0x800 /* MEMC */ 100#define ETHERH500_DATAPORT 0x800 /* MEMC */
94#define ETHERH500_NS8390 0x000 /* MEMC */ 101#define ETHERH500_NS8390 0x000 /* MEMC */
95#define ETHERH500_CTRLPORT 0x800 /* IOC */ 102#define ETHERH500_CTRLPORT 0x800 /* IOC */
@@ -177,7 +184,7 @@ etherh_setif(struct net_device *dev)
177 switch (etherh_priv(dev)->id) { 184 switch (etherh_priv(dev)->id) {
178 case PROD_I3_ETHERLAN600: 185 case PROD_I3_ETHERLAN600:
179 case PROD_I3_ETHERLAN600A: 186 case PROD_I3_ETHERLAN600A:
180 addr = (void *)dev->base_addr + EN0_RCNTHI; 187 addr = (void __iomem *)dev->base_addr + EN0_RCNTHI;
181 188
182 switch (dev->if_port) { 189 switch (dev->if_port) {
183 case IF_PORT_10BASE2: 190 case IF_PORT_10BASE2:
@@ -218,7 +225,7 @@ etherh_getifstat(struct net_device *dev)
218 switch (etherh_priv(dev)->id) { 225 switch (etherh_priv(dev)->id) {
219 case PROD_I3_ETHERLAN600: 226 case PROD_I3_ETHERLAN600:
220 case PROD_I3_ETHERLAN600A: 227 case PROD_I3_ETHERLAN600A:
221 addr = (void *)dev->base_addr + EN0_RCNTHI; 228 addr = (void __iomem *)dev->base_addr + EN0_RCNTHI;
222 switch (dev->if_port) { 229 switch (dev->if_port) {
223 case IF_PORT_10BASE2: 230 case IF_PORT_10BASE2:
224 stat = 1; 231 stat = 1;
@@ -281,7 +288,7 @@ static void
281etherh_reset(struct net_device *dev) 288etherh_reset(struct net_device *dev)
282{ 289{
283 struct ei_device *ei_local = netdev_priv(dev); 290 struct ei_device *ei_local = netdev_priv(dev);
284 void __iomem *addr = (void *)dev->base_addr; 291 void __iomem *addr = (void __iomem *)dev->base_addr;
285 292
286 writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr); 293 writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr);
287 294
@@ -327,7 +334,7 @@ etherh_block_output (struct net_device *dev, int count, const unsigned char *buf
327 334
328 ei_local->dmaing = 1; 335 ei_local->dmaing = 1;
329 336
330 addr = (void *)dev->base_addr; 337 addr = (void __iomem *)dev->base_addr;
331 dma_base = etherh_priv(dev)->dma_base; 338 dma_base = etherh_priv(dev)->dma_base;
332 339
333 count = (count + 1) & ~1; 340 count = (count + 1) & ~1;
@@ -360,7 +367,7 @@ etherh_block_output (struct net_device *dev, int count, const unsigned char *buf
360 printk(KERN_ERR "%s: timeout waiting for TX RDC\n", 367 printk(KERN_ERR "%s: timeout waiting for TX RDC\n",
361 dev->name); 368 dev->name);
362 etherh_reset (dev); 369 etherh_reset (dev);
363 NS8390_init (dev, 1); 370 __NS8390_init (dev, 1);
364 break; 371 break;
365 } 372 }
366 373
@@ -387,7 +394,7 @@ etherh_block_input (struct net_device *dev, int count, struct sk_buff *skb, int
387 394
388 ei_local->dmaing = 1; 395 ei_local->dmaing = 1;
389 396
390 addr = (void *)dev->base_addr; 397 addr = (void __iomem *)dev->base_addr;
391 dma_base = etherh_priv(dev)->dma_base; 398 dma_base = etherh_priv(dev)->dma_base;
392 399
393 buf = skb->data; 400 buf = skb->data;
@@ -427,7 +434,7 @@ etherh_get_header (struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_p
427 434
428 ei_local->dmaing = 1; 435 ei_local->dmaing = 1;
429 436
430 addr = (void *)dev->base_addr; 437 addr = (void __iomem *)dev->base_addr;
431 dma_base = etherh_priv(dev)->dma_base; 438 dma_base = etherh_priv(dev)->dma_base;
432 439
433 writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD); 440 writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD);
@@ -465,7 +472,7 @@ etherh_open(struct net_device *dev)
465 return -EINVAL; 472 return -EINVAL;
466 } 473 }
467 474
468 if (request_irq(dev->irq, ei_interrupt, 0, dev->name, dev)) 475 if (request_irq(dev->irq, __ei_interrupt, 0, dev->name, dev))
469 return -EAGAIN; 476 return -EAGAIN;
470 477
471 /* 478 /*
@@ -491,7 +498,7 @@ etherh_open(struct net_device *dev)
491 etherh_setif(dev); 498 etherh_setif(dev);
492 499
493 etherh_reset(dev); 500 etherh_reset(dev);
494 ei_open(dev); 501 __ei_open(dev);
495 502
496 return 0; 503 return 0;
497} 504}
@@ -502,7 +509,7 @@ etherh_open(struct net_device *dev)
502static int 509static int
503etherh_close(struct net_device *dev) 510etherh_close(struct net_device *dev)
504{ 511{
505 ei_close (dev); 512 __ei_close (dev);
506 free_irq (dev->irq, dev); 513 free_irq (dev->irq, dev);
507 return 0; 514 return 0;
508} 515}
@@ -650,7 +657,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
650 if (ret) 657 if (ret)
651 goto out; 658 goto out;
652 659
653 dev = __alloc_ei_netdev(sizeof(struct etherh_priv)); 660 dev = ____alloc_ei_netdev(sizeof(struct etherh_priv));
654 if (!dev) { 661 if (!dev) {
655 ret = -ENOMEM; 662 ret = -ENOMEM;
656 goto release; 663 goto release;
@@ -736,7 +743,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
736 ei_local->interface_num = 0; 743 ei_local->interface_num = 0;
737 744
738 etherh_reset(dev); 745 etherh_reset(dev);
739 NS8390_init(dev, 0); 746 __NS8390_init(dev, 0);
740 747
741 ret = register_netdev(dev); 748 ret = register_netdev(dev);
742 if (ret) 749 if (ret)
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index 7db3c8af0894..f0b6879a1c7d 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -360,7 +360,8 @@ static int mii_probe (struct net_device *dev)
360 BUG_ON(!phydev); 360 BUG_ON(!phydev);
361 BUG_ON(phydev->attached_dev); 361 BUG_ON(phydev->attached_dev);
362 362
363 phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0); 363 phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0,
364 PHY_INTERFACE_MODE_MII);
364 365
365 if (IS_ERR(phydev)) { 366 if (IS_ERR(phydev)) {
366 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 367 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index b12cc4596b8d..5bacb7587df4 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -53,11 +53,12 @@
53 53
54#include "bnx2.h" 54#include "bnx2.h"
55#include "bnx2_fw.h" 55#include "bnx2_fw.h"
56#include "bnx2_fw2.h"
56 57
57#define DRV_MODULE_NAME "bnx2" 58#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": " 59#define PFX DRV_MODULE_NAME ": "
59#define DRV_MODULE_VERSION "1.4.45" 60#define DRV_MODULE_VERSION "1.5.1"
60#define DRV_MODULE_RELDATE "September 29, 2006" 61#define DRV_MODULE_RELDATE "November 15, 2006"
61 62
62#define RUN_AT(x) (jiffies + (x)) 63#define RUN_AT(x) (jiffies + (x))
63 64
@@ -85,6 +86,7 @@ typedef enum {
85 NC370F, 86 NC370F,
86 BCM5708, 87 BCM5708,
87 BCM5708S, 88 BCM5708S,
89 BCM5709,
88} board_t; 90} board_t;
89 91
90/* indexed by board_t, above */ 92/* indexed by board_t, above */
@@ -98,6 +100,7 @@ static const struct {
98 { "HP NC370F Multifunction Gigabit Server Adapter" }, 100 { "HP NC370F Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-T" }, 101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
100 { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
101 }; 104 };
102 105
103static struct pci_device_id bnx2_pci_tbl[] = { 106static struct pci_device_id bnx2_pci_tbl[] = {
@@ -115,6 +118,8 @@ static struct pci_device_id bnx2_pci_tbl[] = {
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, 118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, 119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, 120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
118 { 0, } 123 { 0, }
119}; 124};
120 125
@@ -236,8 +241,23 @@ static void
236bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) 241bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
237{ 242{
238 offset += cid_addr; 243 offset += cid_addr;
239 REG_WR(bp, BNX2_CTX_DATA_ADR, offset); 244 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
240 REG_WR(bp, BNX2_CTX_DATA, val); 245 int i;
246
247 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
248 REG_WR(bp, BNX2_CTX_CTX_CTRL,
249 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
250 for (i = 0; i < 5; i++) {
251 u32 val;
252 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
253 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
254 break;
255 udelay(5);
256 }
257 } else {
258 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
259 REG_WR(bp, BNX2_CTX_DATA, val);
260 }
241} 261}
242 262
243static int 263static int
@@ -403,6 +423,14 @@ bnx2_free_mem(struct bnx2 *bp)
403{ 423{
404 int i; 424 int i;
405 425
426 for (i = 0; i < bp->ctx_pages; i++) {
427 if (bp->ctx_blk[i]) {
428 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
429 bp->ctx_blk[i],
430 bp->ctx_blk_mapping[i]);
431 bp->ctx_blk[i] = NULL;
432 }
433 }
406 if (bp->status_blk) { 434 if (bp->status_blk) {
407 pci_free_consistent(bp->pdev, bp->status_stats_size, 435 pci_free_consistent(bp->pdev, bp->status_stats_size,
408 bp->status_blk, bp->status_blk_mapping); 436 bp->status_blk, bp->status_blk_mapping);
@@ -481,6 +509,18 @@ bnx2_alloc_mem(struct bnx2 *bp)
481 509
482 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; 510 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
483 511
512 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
513 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
514 if (bp->ctx_pages == 0)
515 bp->ctx_pages = 1;
516 for (i = 0; i < bp->ctx_pages; i++) {
517 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
518 BCM_PAGE_SIZE,
519 &bp->ctx_blk_mapping[i]);
520 if (bp->ctx_blk[i] == NULL)
521 goto alloc_mem_err;
522 }
523 }
484 return 0; 524 return 0;
485 525
486alloc_mem_err: 526alloc_mem_err:
@@ -803,13 +843,13 @@ bnx2_set_mac_link(struct bnx2 *bp)
803 843
804 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 844 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
805 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 845 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
806 BNX2_EMAC_MODE_25G); 846 BNX2_EMAC_MODE_25G_MODE);
807 847
808 if (bp->link_up) { 848 if (bp->link_up) {
809 switch (bp->line_speed) { 849 switch (bp->line_speed) {
810 case SPEED_10: 850 case SPEED_10:
811 if (CHIP_NUM(bp) == CHIP_NUM_5708) { 851 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
812 val |= BNX2_EMAC_MODE_PORT_MII_10; 852 val |= BNX2_EMAC_MODE_PORT_MII_10M;
813 break; 853 break;
814 } 854 }
815 /* fall through */ 855 /* fall through */
@@ -817,7 +857,7 @@ bnx2_set_mac_link(struct bnx2 *bp)
817 val |= BNX2_EMAC_MODE_PORT_MII; 857 val |= BNX2_EMAC_MODE_PORT_MII;
818 break; 858 break;
819 case SPEED_2500: 859 case SPEED_2500:
820 val |= BNX2_EMAC_MODE_25G; 860 val |= BNX2_EMAC_MODE_25G_MODE;
821 /* fall through */ 861 /* fall through */
822 case SPEED_1000: 862 case SPEED_1000:
823 val |= BNX2_EMAC_MODE_PORT_GMII; 863 val |= BNX2_EMAC_MODE_PORT_GMII;
@@ -860,7 +900,7 @@ bnx2_set_link(struct bnx2 *bp)
860 u32 bmsr; 900 u32 bmsr;
861 u8 link_up; 901 u8 link_up;
862 902
863 if (bp->loopback == MAC_LOOPBACK) { 903 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
864 bp->link_up = 1; 904 bp->link_up = 1;
865 return 0; 905 return 0;
866 } 906 }
@@ -902,6 +942,7 @@ bnx2_set_link(struct bnx2 *bp)
902 u32 bmcr; 942 u32 bmcr;
903 943
904 bnx2_read_phy(bp, MII_BMCR, &bmcr); 944 bnx2_read_phy(bp, MII_BMCR, &bmcr);
945 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
905 if (!(bmcr & BMCR_ANENABLE)) { 946 if (!(bmcr & BMCR_ANENABLE)) {
906 bnx2_write_phy(bp, MII_BMCR, bmcr | 947 bnx2_write_phy(bp, MII_BMCR, bmcr |
907 BMCR_ANENABLE); 948 BMCR_ANENABLE);
@@ -988,7 +1029,21 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
988 u32 new_bmcr; 1029 u32 new_bmcr;
989 int force_link_down = 0; 1030 int force_link_down = 0;
990 1031
991 if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1032 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1033 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1034
1035 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1036 new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500);
1037 new_bmcr |= BMCR_SPEED1000;
1038 if (bp->req_line_speed == SPEED_2500) {
1039 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1040 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1041 if (!(up1 & BCM5708S_UP1_2G5)) {
1042 up1 |= BCM5708S_UP1_2G5;
1043 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1044 force_link_down = 1;
1045 }
1046 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
992 bnx2_read_phy(bp, BCM5708S_UP1, &up1); 1047 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
993 if (up1 & BCM5708S_UP1_2G5) { 1048 if (up1 & BCM5708S_UP1_2G5) {
994 up1 &= ~BCM5708S_UP1_2G5; 1049 up1 &= ~BCM5708S_UP1_2G5;
@@ -997,12 +1052,6 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
997 } 1052 }
998 } 1053 }
999 1054
1000 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1001 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1002
1003 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1004 new_bmcr = bmcr & ~BMCR_ANENABLE;
1005 new_bmcr |= BMCR_SPEED1000;
1006 if (bp->req_duplex == DUPLEX_FULL) { 1055 if (bp->req_duplex == DUPLEX_FULL) {
1007 adv |= ADVERTISE_1000XFULL; 1056 adv |= ADVERTISE_1000XFULL;
1008 new_bmcr |= BMCR_FULLDPLX; 1057 new_bmcr |= BMCR_FULLDPLX;
@@ -1023,6 +1072,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
1023 bp->link_up = 0; 1072 bp->link_up = 0;
1024 netif_carrier_off(bp->dev); 1073 netif_carrier_off(bp->dev);
1025 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 1074 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1075 bnx2_report_link(bp);
1026 } 1076 }
1027 bnx2_write_phy(bp, MII_ADVERTISE, adv); 1077 bnx2_write_phy(bp, MII_ADVERTISE, adv);
1028 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 1078 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
@@ -1048,30 +1098,26 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
1048 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { 1098 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1049 /* Force a link down visible on the other side */ 1099 /* Force a link down visible on the other side */
1050 if (bp->link_up) { 1100 if (bp->link_up) {
1051 int i;
1052
1053 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); 1101 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1054 for (i = 0; i < 110; i++) { 1102 spin_unlock_bh(&bp->phy_lock);
1055 udelay(100); 1103 msleep(20);
1056 } 1104 spin_lock_bh(&bp->phy_lock);
1057 } 1105 }
1058 1106
1059 bnx2_write_phy(bp, MII_ADVERTISE, new_adv); 1107 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1060 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | 1108 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1061 BMCR_ANENABLE); 1109 BMCR_ANENABLE);
1062 if (CHIP_NUM(bp) == CHIP_NUM_5706) { 1110 /* Speed up link-up time when the link partner
1063 /* Speed up link-up time when the link partner 1111 * does not autonegotiate which is very common
1064 * does not autonegotiate which is very common 1112 * in blade servers. Some blade servers use
1065 * in blade servers. Some blade servers use 1113 * IPMI for kerboard input and it's important
1066 * IPMI for kerboard input and it's important 1114 * to minimize link disruptions. Autoneg. involves
1067 * to minimize link disruptions. Autoneg. involves 1115 * exchanging base pages plus 3 next pages and
1068 * exchanging base pages plus 3 next pages and 1116 * normally completes in about 120 msec.
1069 * normally completes in about 120 msec. 1117 */
1070 */ 1118 bp->current_interval = SERDES_AN_TIMEOUT;
1071 bp->current_interval = SERDES_AN_TIMEOUT; 1119 bp->serdes_an_pending = 1;
1072 bp->serdes_an_pending = 1; 1120 mod_timer(&bp->timer, jiffies + bp->current_interval);
1073 mod_timer(&bp->timer, jiffies + bp->current_interval);
1074 }
1075 } 1121 }
1076 1122
1077 return 0; 1123 return 0;
@@ -1153,7 +1199,6 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
1153 } 1199 }
1154 if (new_bmcr != bmcr) { 1200 if (new_bmcr != bmcr) {
1155 u32 bmsr; 1201 u32 bmsr;
1156 int i = 0;
1157 1202
1158 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1203 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1159 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1204 bnx2_read_phy(bp, MII_BMSR, &bmsr);
@@ -1161,12 +1206,12 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
1161 if (bmsr & BMSR_LSTATUS) { 1206 if (bmsr & BMSR_LSTATUS) {
1162 /* Force link down */ 1207 /* Force link down */
1163 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); 1208 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1164 do { 1209 spin_unlock_bh(&bp->phy_lock);
1165 udelay(100); 1210 msleep(50);
1166 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1211 spin_lock_bh(&bp->phy_lock);
1167 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1212
1168 i++; 1213 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1169 } while ((bmsr & BMSR_LSTATUS) && (i < 620)); 1214 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1170 } 1215 }
1171 1216
1172 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 1217 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
@@ -1258,9 +1303,8 @@ bnx2_init_5706s_phy(struct bnx2 *bp)
1258{ 1303{
1259 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; 1304 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1260 1305
1261 if (CHIP_NUM(bp) == CHIP_NUM_5706) { 1306 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1262 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300); 1307 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1263 }
1264 1308
1265 if (bp->dev->mtu > 1500) { 1309 if (bp->dev->mtu > 1500) {
1266 u32 val; 1310 u32 val;
@@ -1397,13 +1441,13 @@ bnx2_set_phy_loopback(struct bnx2 *bp)
1397 for (i = 0; i < 10; i++) { 1441 for (i = 0; i < 10; i++) {
1398 if (bnx2_test_link(bp) == 0) 1442 if (bnx2_test_link(bp) == 0)
1399 break; 1443 break;
1400 udelay(10); 1444 msleep(100);
1401 } 1445 }
1402 1446
1403 mac_mode = REG_RD(bp, BNX2_EMAC_MODE); 1447 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1404 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 1448 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1405 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 1449 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1406 BNX2_EMAC_MODE_25G); 1450 BNX2_EMAC_MODE_25G_MODE);
1407 1451
1408 mac_mode |= BNX2_EMAC_MODE_PORT_GMII; 1452 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1409 REG_WR(bp, BNX2_EMAC_MODE, mac_mode); 1453 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
@@ -1454,6 +1498,40 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1454 return 0; 1498 return 0;
1455} 1499}
1456 1500
1501static int
1502bnx2_init_5709_context(struct bnx2 *bp)
1503{
1504 int i, ret = 0;
1505 u32 val;
1506
1507 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
1508 val |= (BCM_PAGE_BITS - 8) << 16;
1509 REG_WR(bp, BNX2_CTX_COMMAND, val);
1510 for (i = 0; i < bp->ctx_pages; i++) {
1511 int j;
1512
1513 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
1514 (bp->ctx_blk_mapping[i] & 0xffffffff) |
1515 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
1516 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
1517 (u64) bp->ctx_blk_mapping[i] >> 32);
1518 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
1519 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
1520 for (j = 0; j < 10; j++) {
1521
1522 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
1523 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
1524 break;
1525 udelay(5);
1526 }
1527 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
1528 ret = -EBUSY;
1529 break;
1530 }
1531 }
1532 return ret;
1533}
1534
1457static void 1535static void
1458bnx2_init_context(struct bnx2 *bp) 1536bnx2_init_context(struct bnx2 *bp)
1459{ 1537{
@@ -1576,9 +1654,8 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1576 return -ENOMEM; 1654 return -ENOMEM;
1577 } 1655 }
1578 1656
1579 if (unlikely((align = (unsigned long) skb->data & 0x7))) { 1657 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
1580 skb_reserve(skb, 8 - align); 1658 skb_reserve(skb, BNX2_RX_ALIGN - align);
1581 }
1582 1659
1583 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, 1660 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1584 PCI_DMA_FROMDEVICE); 1661 PCI_DMA_FROMDEVICE);
@@ -2040,7 +2117,8 @@ bnx2_set_rx_mode(struct net_device *dev)
2040 if (dev->flags & IFF_PROMISC) { 2117 if (dev->flags & IFF_PROMISC) {
2041 /* Promiscuous mode. */ 2118 /* Promiscuous mode. */
2042 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 2119 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2043 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN; 2120 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2121 BNX2_RPM_SORT_USER0_PROM_VLAN;
2044 } 2122 }
2045 else if (dev->flags & IFF_ALLMULTI) { 2123 else if (dev->flags & IFF_ALLMULTI) {
2046 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 2124 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
@@ -2208,11 +2286,12 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2208 } 2286 }
2209} 2287}
2210 2288
2211static void 2289static int
2212load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) 2290load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2213{ 2291{
2214 u32 offset; 2292 u32 offset;
2215 u32 val; 2293 u32 val;
2294 int rc;
2216 2295
2217 /* Halt the CPU. */ 2296 /* Halt the CPU. */
2218 val = REG_RD_IND(bp, cpu_reg->mode); 2297 val = REG_RD_IND(bp, cpu_reg->mode);
@@ -2222,7 +2301,18 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2222 2301
2223 /* Load the Text area. */ 2302 /* Load the Text area. */
2224 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2303 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2225 if (fw->text) { 2304 if (fw->gz_text) {
2305 u32 text_len;
2306 void *text;
2307
2308 rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
2309 &text_len);
2310 if (rc)
2311 return rc;
2312
2313 fw->text = text;
2314 }
2315 if (fw->gz_text) {
2226 int j; 2316 int j;
2227 2317
2228 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 2318 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
@@ -2280,13 +2370,15 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2280 val &= ~cpu_reg->mode_value_halt; 2370 val &= ~cpu_reg->mode_value_halt;
2281 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); 2371 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2282 REG_WR_IND(bp, cpu_reg->mode, val); 2372 REG_WR_IND(bp, cpu_reg->mode, val);
2373
2374 return 0;
2283} 2375}
2284 2376
2285static int 2377static int
2286bnx2_init_cpus(struct bnx2 *bp) 2378bnx2_init_cpus(struct bnx2 *bp)
2287{ 2379{
2288 struct cpu_reg cpu_reg; 2380 struct cpu_reg cpu_reg;
2289 struct fw_info fw; 2381 struct fw_info *fw;
2290 int rc = 0; 2382 int rc = 0;
2291 void *text; 2383 void *text;
2292 u32 text_len; 2384 u32 text_len;
@@ -2323,44 +2415,15 @@ bnx2_init_cpus(struct bnx2 *bp)
2323 cpu_reg.spad_base = BNX2_RXP_SCRATCH; 2415 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2324 cpu_reg.mips_view_base = 0x8000000; 2416 cpu_reg.mips_view_base = 0x8000000;
2325 2417
2326 fw.ver_major = bnx2_RXP_b06FwReleaseMajor; 2418 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2327 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; 2419 fw = &bnx2_rxp_fw_09;
2328 fw.ver_fix = bnx2_RXP_b06FwReleaseFix; 2420 else
2329 fw.start_addr = bnx2_RXP_b06FwStartAddr; 2421 fw = &bnx2_rxp_fw_06;
2330
2331 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2332 fw.text_len = bnx2_RXP_b06FwTextLen;
2333 fw.text_index = 0;
2334 2422
2335 rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText), 2423 rc = load_cpu_fw(bp, &cpu_reg, fw);
2336 &text, &text_len);
2337 if (rc) 2424 if (rc)
2338 goto init_cpu_err; 2425 goto init_cpu_err;
2339 2426
2340 fw.text = text;
2341
2342 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2343 fw.data_len = bnx2_RXP_b06FwDataLen;
2344 fw.data_index = 0;
2345 fw.data = bnx2_RXP_b06FwData;
2346
2347 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2348 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2349 fw.sbss_index = 0;
2350 fw.sbss = bnx2_RXP_b06FwSbss;
2351
2352 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2353 fw.bss_len = bnx2_RXP_b06FwBssLen;
2354 fw.bss_index = 0;
2355 fw.bss = bnx2_RXP_b06FwBss;
2356
2357 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2358 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2359 fw.rodata_index = 0;
2360 fw.rodata = bnx2_RXP_b06FwRodata;
2361
2362 load_cpu_fw(bp, &cpu_reg, &fw);
2363
2364 /* Initialize the TX Processor. */ 2427 /* Initialize the TX Processor. */
2365 cpu_reg.mode = BNX2_TXP_CPU_MODE; 2428 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2366 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; 2429 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
@@ -2375,44 +2438,15 @@ bnx2_init_cpus(struct bnx2 *bp)
2375 cpu_reg.spad_base = BNX2_TXP_SCRATCH; 2438 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2376 cpu_reg.mips_view_base = 0x8000000; 2439 cpu_reg.mips_view_base = 0x8000000;
2377 2440
2378 fw.ver_major = bnx2_TXP_b06FwReleaseMajor; 2441 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2379 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; 2442 fw = &bnx2_txp_fw_09;
2380 fw.ver_fix = bnx2_TXP_b06FwReleaseFix; 2443 else
2381 fw.start_addr = bnx2_TXP_b06FwStartAddr; 2444 fw = &bnx2_txp_fw_06;
2382
2383 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2384 fw.text_len = bnx2_TXP_b06FwTextLen;
2385 fw.text_index = 0;
2386 2445
2387 rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText), 2446 rc = load_cpu_fw(bp, &cpu_reg, fw);
2388 &text, &text_len);
2389 if (rc) 2447 if (rc)
2390 goto init_cpu_err; 2448 goto init_cpu_err;
2391 2449
2392 fw.text = text;
2393
2394 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2395 fw.data_len = bnx2_TXP_b06FwDataLen;
2396 fw.data_index = 0;
2397 fw.data = bnx2_TXP_b06FwData;
2398
2399 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2400 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2401 fw.sbss_index = 0;
2402 fw.sbss = bnx2_TXP_b06FwSbss;
2403
2404 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2405 fw.bss_len = bnx2_TXP_b06FwBssLen;
2406 fw.bss_index = 0;
2407 fw.bss = bnx2_TXP_b06FwBss;
2408
2409 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2410 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2411 fw.rodata_index = 0;
2412 fw.rodata = bnx2_TXP_b06FwRodata;
2413
2414 load_cpu_fw(bp, &cpu_reg, &fw);
2415
2416 /* Initialize the TX Patch-up Processor. */ 2450 /* Initialize the TX Patch-up Processor. */
2417 cpu_reg.mode = BNX2_TPAT_CPU_MODE; 2451 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2418 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; 2452 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
@@ -2427,44 +2461,15 @@ bnx2_init_cpus(struct bnx2 *bp)
2427 cpu_reg.spad_base = BNX2_TPAT_SCRATCH; 2461 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2428 cpu_reg.mips_view_base = 0x8000000; 2462 cpu_reg.mips_view_base = 0x8000000;
2429 2463
2430 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; 2464 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2431 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; 2465 fw = &bnx2_tpat_fw_09;
2432 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; 2466 else
2433 fw.start_addr = bnx2_TPAT_b06FwStartAddr; 2467 fw = &bnx2_tpat_fw_06;
2434
2435 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2436 fw.text_len = bnx2_TPAT_b06FwTextLen;
2437 fw.text_index = 0;
2438 2468
2439 rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText), 2469 rc = load_cpu_fw(bp, &cpu_reg, fw);
2440 &text, &text_len);
2441 if (rc) 2470 if (rc)
2442 goto init_cpu_err; 2471 goto init_cpu_err;
2443 2472
2444 fw.text = text;
2445
2446 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2447 fw.data_len = bnx2_TPAT_b06FwDataLen;
2448 fw.data_index = 0;
2449 fw.data = bnx2_TPAT_b06FwData;
2450
2451 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2452 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2453 fw.sbss_index = 0;
2454 fw.sbss = bnx2_TPAT_b06FwSbss;
2455
2456 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2457 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2458 fw.bss_index = 0;
2459 fw.bss = bnx2_TPAT_b06FwBss;
2460
2461 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2462 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2463 fw.rodata_index = 0;
2464 fw.rodata = bnx2_TPAT_b06FwRodata;
2465
2466 load_cpu_fw(bp, &cpu_reg, &fw);
2467
2468 /* Initialize the Completion Processor. */ 2473 /* Initialize the Completion Processor. */
2469 cpu_reg.mode = BNX2_COM_CPU_MODE; 2474 cpu_reg.mode = BNX2_COM_CPU_MODE;
2470 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; 2475 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
@@ -2479,44 +2484,36 @@ bnx2_init_cpus(struct bnx2 *bp)
2479 cpu_reg.spad_base = BNX2_COM_SCRATCH; 2484 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2480 cpu_reg.mips_view_base = 0x8000000; 2485 cpu_reg.mips_view_base = 0x8000000;
2481 2486
2482 fw.ver_major = bnx2_COM_b06FwReleaseMajor; 2487 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2483 fw.ver_minor = bnx2_COM_b06FwReleaseMinor; 2488 fw = &bnx2_com_fw_09;
2484 fw.ver_fix = bnx2_COM_b06FwReleaseFix; 2489 else
2485 fw.start_addr = bnx2_COM_b06FwStartAddr; 2490 fw = &bnx2_com_fw_06;
2486
2487 fw.text_addr = bnx2_COM_b06FwTextAddr;
2488 fw.text_len = bnx2_COM_b06FwTextLen;
2489 fw.text_index = 0;
2490 2491
2491 rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText), 2492 rc = load_cpu_fw(bp, &cpu_reg, fw);
2492 &text, &text_len);
2493 if (rc) 2493 if (rc)
2494 goto init_cpu_err; 2494 goto init_cpu_err;
2495 2495
2496 fw.text = text; 2496 /* Initialize the Command Processor. */
2497 2497 cpu_reg.mode = BNX2_CP_CPU_MODE;
2498 fw.data_addr = bnx2_COM_b06FwDataAddr; 2498 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
2499 fw.data_len = bnx2_COM_b06FwDataLen; 2499 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
2500 fw.data_index = 0; 2500 cpu_reg.state = BNX2_CP_CPU_STATE;
2501 fw.data = bnx2_COM_b06FwData; 2501 cpu_reg.state_value_clear = 0xffffff;
2502 2502 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
2503 fw.sbss_addr = bnx2_COM_b06FwSbssAddr; 2503 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
2504 fw.sbss_len = bnx2_COM_b06FwSbssLen; 2504 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
2505 fw.sbss_index = 0; 2505 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
2506 fw.sbss = bnx2_COM_b06FwSbss; 2506 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
2507 2507 cpu_reg.spad_base = BNX2_CP_SCRATCH;
2508 fw.bss_addr = bnx2_COM_b06FwBssAddr; 2508 cpu_reg.mips_view_base = 0x8000000;
2509 fw.bss_len = bnx2_COM_b06FwBssLen;
2510 fw.bss_index = 0;
2511 fw.bss = bnx2_COM_b06FwBss;
2512
2513 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2514 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2515 fw.rodata_index = 0;
2516 fw.rodata = bnx2_COM_b06FwRodata;
2517 2509
2518 load_cpu_fw(bp, &cpu_reg, &fw); 2510 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2511 fw = &bnx2_cp_fw_09;
2519 2512
2513 load_cpu_fw(bp, &cpu_reg, fw);
2514 if (rc)
2515 goto init_cpu_err;
2516 }
2520init_cpu_err: 2517init_cpu_err:
2521 bnx2_gunzip_end(bp); 2518 bnx2_gunzip_end(bp);
2522 return rc; 2519 return rc;
@@ -3288,31 +3285,44 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3288 * before we issue a reset. */ 3285 * before we issue a reset. */
3289 val = REG_RD(bp, BNX2_MISC_ID); 3286 val = REG_RD(bp, BNX2_MISC_ID);
3290 3287
3291 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3288 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3292 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3289 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3293 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3290 REG_RD(bp, BNX2_MISC_COMMAND);
3291 udelay(5);
3294 3292
3295 /* Chip reset. */ 3293 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3296 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 3294 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3297 3295
3298 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 3296 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3299 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3300 msleep(15);
3301 3297
3302 /* Reset takes approximate 30 usec */ 3298 } else {
3303 for (i = 0; i < 10; i++) { 3299 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3304 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); 3300 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3305 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3301 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3306 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3302
3307 break; 3303 /* Chip reset. */
3304 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3305
3306 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3307 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3308 current->state = TASK_UNINTERRUPTIBLE;
3309 schedule_timeout(HZ / 50);
3308 } 3310 }
3309 udelay(10);
3310 }
3311 3311
3312 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3312 /* Reset takes approximate 30 usec */
3313 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3313 for (i = 0; i < 10; i++) {
3314 printk(KERN_ERR PFX "Chip reset did not complete\n"); 3314 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3315 return -EBUSY; 3315 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3316 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3317 break;
3318 udelay(10);
3319 }
3320
3321 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3322 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3323 printk(KERN_ERR PFX "Chip reset did not complete\n");
3324 return -EBUSY;
3325 }
3316 } 3326 }
3317 3327
3318 /* Make sure byte swapping is properly configured. */ 3328 /* Make sure byte swapping is properly configured. */
@@ -3390,7 +3400,10 @@ bnx2_init_chip(struct bnx2 *bp)
3390 3400
3391 /* Initialize context mapping and zero out the quick contexts. The 3401 /* Initialize context mapping and zero out the quick contexts. The
3392 * context block must have already been enabled. */ 3402 * context block must have already been enabled. */
3393 bnx2_init_context(bp); 3403 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3404 bnx2_init_5709_context(bp);
3405 else
3406 bnx2_init_context(bp);
3394 3407
3395 if ((rc = bnx2_init_cpus(bp)) != 0) 3408 if ((rc = bnx2_init_cpus(bp)) != 0)
3396 return rc; 3409 return rc;
@@ -3501,12 +3514,40 @@ bnx2_init_chip(struct bnx2 *bp)
3501 return rc; 3514 return rc;
3502} 3515}
3503 3516
3517static void
3518bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
3519{
3520 u32 val, offset0, offset1, offset2, offset3;
3521
3522 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3523 offset0 = BNX2_L2CTX_TYPE_XI;
3524 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3525 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3526 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3527 } else {
3528 offset0 = BNX2_L2CTX_TYPE;
3529 offset1 = BNX2_L2CTX_CMD_TYPE;
3530 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3531 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3532 }
3533 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3534 CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
3535
3536 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3537 CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
3538
3539 val = (u64) bp->tx_desc_mapping >> 32;
3540 CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
3541
3542 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3543 CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
3544}
3504 3545
3505static void 3546static void
3506bnx2_init_tx_ring(struct bnx2 *bp) 3547bnx2_init_tx_ring(struct bnx2 *bp)
3507{ 3548{
3508 struct tx_bd *txbd; 3549 struct tx_bd *txbd;
3509 u32 val; 3550 u32 cid;
3510 3551
3511 bp->tx_wake_thresh = bp->tx_ring_size / 2; 3552 bp->tx_wake_thresh = bp->tx_ring_size / 2;
3512 3553
@@ -3520,19 +3561,11 @@ bnx2_init_tx_ring(struct bnx2 *bp)
3520 bp->hw_tx_cons = 0; 3561 bp->hw_tx_cons = 0;
3521 bp->tx_prod_bseq = 0; 3562 bp->tx_prod_bseq = 0;
3522 3563
3523 val = BNX2_L2CTX_TYPE_TYPE_L2; 3564 cid = TX_CID;
3524 val |= BNX2_L2CTX_TYPE_SIZE_L2; 3565 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
3525 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val); 3566 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
3526 3567
3527 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2; 3568 bnx2_init_tx_context(bp, cid);
3528 val |= 8 << 16;
3529 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3530
3531 val = (u64) bp->tx_desc_mapping >> 32;
3532 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3533
3534 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3535 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3536} 3569}
3537 3570
3538static void 3571static void
@@ -3545,8 +3578,8 @@ bnx2_init_rx_ring(struct bnx2 *bp)
3545 3578
3546 /* 8 for CRC and VLAN */ 3579 /* 8 for CRC and VLAN */
3547 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; 3580 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3548 /* 8 for alignment */ 3581 /* hw alignment */
3549 bp->rx_buf_size = bp->rx_buf_use_size + 8; 3582 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
3550 3583
3551 ring_prod = prod = bp->rx_prod = 0; 3584 ring_prod = prod = bp->rx_prod = 0;
3552 bp->rx_cons = 0; 3585 bp->rx_cons = 0;
@@ -3712,7 +3745,9 @@ bnx2_init_nic(struct bnx2 *bp)
3712 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) 3745 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3713 return rc; 3746 return rc;
3714 3747
3748 spin_lock_bh(&bp->phy_lock);
3715 bnx2_init_phy(bp); 3749 bnx2_init_phy(bp);
3750 spin_unlock_bh(&bp->phy_lock);
3716 bnx2_set_link(bp); 3751 bnx2_set_link(bp);
3717 return 0; 3752 return 0;
3718} 3753}
@@ -3952,7 +3987,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3952 bnx2_set_mac_loopback(bp); 3987 bnx2_set_mac_loopback(bp);
3953 } 3988 }
3954 else if (loopback_mode == BNX2_PHY_LOOPBACK) { 3989 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3955 bp->loopback = 0; 3990 bp->loopback = PHY_LOOPBACK;
3956 bnx2_set_phy_loopback(bp); 3991 bnx2_set_phy_loopback(bp);
3957 } 3992 }
3958 else 3993 else
@@ -3992,8 +4027,8 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3992 bp->tx_prod = NEXT_TX_BD(bp->tx_prod); 4027 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3993 bp->tx_prod_bseq += pkt_size; 4028 bp->tx_prod_bseq += pkt_size;
3994 4029
3995 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod); 4030 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
3996 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); 4031 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
3997 4032
3998 udelay(100); 4033 udelay(100);
3999 4034
@@ -4162,80 +4197,117 @@ bnx2_test_intr(struct bnx2 *bp)
4162} 4197}
4163 4198
4164static void 4199static void
4165bnx2_timer(unsigned long data) 4200bnx2_5706_serdes_timer(struct bnx2 *bp)
4166{ 4201{
4167 struct bnx2 *bp = (struct bnx2 *) data; 4202 spin_lock(&bp->phy_lock);
4168 u32 msg; 4203 if (bp->serdes_an_pending)
4204 bp->serdes_an_pending--;
4205 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4206 u32 bmcr;
4169 4207
4170 if (!netif_running(bp->dev)) 4208 bp->current_interval = bp->timer_interval;
4171 return;
4172 4209
4173 if (atomic_read(&bp->intr_sem) != 0) 4210 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4174 goto bnx2_restart_timer;
4175 4211
4176 msg = (u32) ++bp->fw_drv_pulse_wr_seq; 4212 if (bmcr & BMCR_ANENABLE) {
4177 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg); 4213 u32 phy1, phy2;
4178 4214
4179 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); 4215 bnx2_write_phy(bp, 0x1c, 0x7c00);
4216 bnx2_read_phy(bp, 0x1c, &phy1);
4180 4217
4181 if ((bp->phy_flags & PHY_SERDES_FLAG) && 4218 bnx2_write_phy(bp, 0x17, 0x0f01);
4182 (CHIP_NUM(bp) == CHIP_NUM_5706)) { 4219 bnx2_read_phy(bp, 0x15, &phy2);
4220 bnx2_write_phy(bp, 0x17, 0x0f01);
4221 bnx2_read_phy(bp, 0x15, &phy2);
4183 4222
4184 spin_lock(&bp->phy_lock); 4223 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4185 if (bp->serdes_an_pending) { 4224 !(phy2 & 0x20)) { /* no CONFIG */
4186 bp->serdes_an_pending--; 4225
4226 bmcr &= ~BMCR_ANENABLE;
4227 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4228 bnx2_write_phy(bp, MII_BMCR, bmcr);
4229 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4230 }
4187 } 4231 }
4188 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 4232 }
4189 u32 bmcr; 4233 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4234 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4235 u32 phy2;
4190 4236
4191 bp->current_interval = bp->timer_interval; 4237 bnx2_write_phy(bp, 0x17, 0x0f01);
4238 bnx2_read_phy(bp, 0x15, &phy2);
4239 if (phy2 & 0x20) {
4240 u32 bmcr;
4192 4241
4193 bnx2_read_phy(bp, MII_BMCR, &bmcr); 4242 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4243 bmcr |= BMCR_ANENABLE;
4244 bnx2_write_phy(bp, MII_BMCR, bmcr);
4194 4245
4195 if (bmcr & BMCR_ANENABLE) { 4246 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4196 u32 phy1, phy2; 4247 }
4248 } else
4249 bp->current_interval = bp->timer_interval;
4197 4250
4198 bnx2_write_phy(bp, 0x1c, 0x7c00); 4251 spin_unlock(&bp->phy_lock);
4199 bnx2_read_phy(bp, 0x1c, &phy1); 4252}
4200 4253
4201 bnx2_write_phy(bp, 0x17, 0x0f01); 4254static void
4202 bnx2_read_phy(bp, 0x15, &phy2); 4255bnx2_5708_serdes_timer(struct bnx2 *bp)
4203 bnx2_write_phy(bp, 0x17, 0x0f01); 4256{
4204 bnx2_read_phy(bp, 0x15, &phy2); 4257 if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4258 bp->serdes_an_pending = 0;
4259 return;
4260 }
4205 4261
4206 if ((phy1 & 0x10) && /* SIGNAL DETECT */ 4262 spin_lock(&bp->phy_lock);
4207 !(phy2 & 0x20)) { /* no CONFIG */ 4263 if (bp->serdes_an_pending)
4264 bp->serdes_an_pending--;
4265 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4266 u32 bmcr;
4208 4267
4209 bmcr &= ~BMCR_ANENABLE; 4268 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4210 bmcr |= BMCR_SPEED1000 | 4269
4211 BMCR_FULLDPLX; 4270 if (bmcr & BMCR_ANENABLE) {
4212 bnx2_write_phy(bp, MII_BMCR, bmcr); 4271 bmcr &= ~BMCR_ANENABLE;
4213 bp->phy_flags |= 4272 bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500;
4214 PHY_PARALLEL_DETECT_FLAG; 4273 bnx2_write_phy(bp, MII_BMCR, bmcr);
4215 } 4274 bp->current_interval = SERDES_FORCED_TIMEOUT;
4216 } 4275 } else {
4276 bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500);
4277 bmcr |= BMCR_ANENABLE;
4278 bnx2_write_phy(bp, MII_BMCR, bmcr);
4279 bp->serdes_an_pending = 2;
4280 bp->current_interval = bp->timer_interval;
4217 } 4281 }
4218 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4219 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4220 u32 phy2;
4221 4282
4222 bnx2_write_phy(bp, 0x17, 0x0f01); 4283 } else
4223 bnx2_read_phy(bp, 0x15, &phy2); 4284 bp->current_interval = bp->timer_interval;
4224 if (phy2 & 0x20) {
4225 u32 bmcr;
4226 4285
4227 bnx2_read_phy(bp, MII_BMCR, &bmcr); 4286 spin_unlock(&bp->phy_lock);
4228 bmcr |= BMCR_ANENABLE; 4287}
4229 bnx2_write_phy(bp, MII_BMCR, bmcr); 4288
4289static void
4290bnx2_timer(unsigned long data)
4291{
4292 struct bnx2 *bp = (struct bnx2 *) data;
4293 u32 msg;
4230 4294
4231 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; 4295 if (!netif_running(bp->dev))
4296 return;
4232 4297
4233 } 4298 if (atomic_read(&bp->intr_sem) != 0)
4234 } 4299 goto bnx2_restart_timer;
4235 else
4236 bp->current_interval = bp->timer_interval;
4237 4300
4238 spin_unlock(&bp->phy_lock); 4301 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4302 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4303
4304 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4305
4306 if (bp->phy_flags & PHY_SERDES_FLAG) {
4307 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4308 bnx2_5706_serdes_timer(bp);
4309 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
4310 bnx2_5708_serdes_timer(bp);
4239 } 4311 }
4240 4312
4241bnx2_restart_timer: 4313bnx2_restart_timer:
@@ -4508,8 +4580,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4508 prod = NEXT_TX_BD(prod); 4580 prod = NEXT_TX_BD(prod);
4509 bp->tx_prod_bseq += skb->len; 4581 bp->tx_prod_bseq += skb->len;
4510 4582
4511 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); 4583 REG_WR16(bp, bp->tx_bidx_addr, prod);
4512 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); 4584 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4513 4585
4514 mmiowb(); 4586 mmiowb();
4515 4587
@@ -4743,10 +4815,14 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4743 } 4815 }
4744 else { 4816 else {
4745 if (bp->phy_flags & PHY_SERDES_FLAG) { 4817 if (bp->phy_flags & PHY_SERDES_FLAG) {
4746 if ((cmd->speed != SPEED_1000) || 4818 if ((cmd->speed != SPEED_1000 &&
4747 (cmd->duplex != DUPLEX_FULL)) { 4819 cmd->speed != SPEED_2500) ||
4820 (cmd->duplex != DUPLEX_FULL))
4821 return -EINVAL;
4822
4823 if (cmd->speed == SPEED_2500 &&
4824 !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
4748 return -EINVAL; 4825 return -EINVAL;
4749 }
4750 } 4826 }
4751 else if (cmd->speed == SPEED_1000) { 4827 else if (cmd->speed == SPEED_1000) {
4752 return -EINVAL; 4828 return -EINVAL;
@@ -4903,11 +4979,10 @@ bnx2_nway_reset(struct net_device *dev)
4903 msleep(20); 4979 msleep(20);
4904 4980
4905 spin_lock_bh(&bp->phy_lock); 4981 spin_lock_bh(&bp->phy_lock);
4906 if (CHIP_NUM(bp) == CHIP_NUM_5706) { 4982
4907 bp->current_interval = SERDES_AN_TIMEOUT; 4983 bp->current_interval = SERDES_AN_TIMEOUT;
4908 bp->serdes_an_pending = 1; 4984 bp->serdes_an_pending = 1;
4909 mod_timer(&bp->timer, jiffies + bp->current_interval); 4985 mod_timer(&bp->timer, jiffies + bp->current_interval);
4910 }
4911 } 4986 }
4912 4987
4913 bnx2_read_phy(bp, MII_BMCR, &bmcr); 4988 bnx2_read_phy(bp, MII_BMCR, &bmcr);
@@ -5288,6 +5363,8 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5288 5363
5289 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); 5364 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5290 if (etest->flags & ETH_TEST_FL_OFFLINE) { 5365 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5366 int i;
5367
5291 bnx2_netif_stop(bp); 5368 bnx2_netif_stop(bp);
5292 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); 5369 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5293 bnx2_free_skbs(bp); 5370 bnx2_free_skbs(bp);
@@ -5312,9 +5389,11 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5312 } 5389 }
5313 5390
5314 /* wait for link up */ 5391 /* wait for link up */
5315 msleep_interruptible(3000); 5392 for (i = 0; i < 7; i++) {
5316 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG)) 5393 if (bp->link_up)
5317 msleep_interruptible(4000); 5394 break;
5395 msleep_interruptible(1000);
5396 }
5318 } 5397 }
5319 5398
5320 if (bnx2_test_nvram(bp) != 0) { 5399 if (bnx2_test_nvram(bp) != 0) {
@@ -5604,13 +5683,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5604 goto err_out_release; 5683 goto err_out_release;
5605 } 5684 }
5606 5685
5607 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5608 if (bp->pcix_cap == 0) {
5609 dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
5610 rc = -EIO;
5611 goto err_out_release;
5612 }
5613
5614 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { 5686 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5615 bp->flags |= USING_DAC_FLAG; 5687 bp->flags |= USING_DAC_FLAG;
5616 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { 5688 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
@@ -5633,7 +5705,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5633 INIT_WORK(&bp->reset_task, bnx2_reset_task); 5705 INIT_WORK(&bp->reset_task, bnx2_reset_task);
5634 5706
5635 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); 5707 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5636 mem_len = MB_GET_CID_ADDR(17); 5708 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
5637 dev->mem_end = dev->mem_start + mem_len; 5709 dev->mem_end = dev->mem_start + mem_len;
5638 dev->irq = pdev->irq; 5710 dev->irq = pdev->irq;
5639 5711
@@ -5657,6 +5729,16 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5657 5729
5658 bp->chip_id = REG_RD(bp, BNX2_MISC_ID); 5730 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5659 5731
5732 if (CHIP_NUM(bp) != CHIP_NUM_5709) {
5733 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5734 if (bp->pcix_cap == 0) {
5735 dev_err(&pdev->dev,
5736 "Cannot find PCIX capability, aborting.\n");
5737 rc = -EIO;
5738 goto err_out_unmap;
5739 }
5740 }
5741
5660 /* Get bus information. */ 5742 /* Get bus information. */
5661 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); 5743 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5662 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { 5744 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
@@ -5776,10 +5858,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5776 bp->phy_addr = 1; 5858 bp->phy_addr = 1;
5777 5859
5778 /* Disable WOL support if we are running on a SERDES chip. */ 5860 /* Disable WOL support if we are running on a SERDES chip. */
5779 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) { 5861 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5862 if (CHIP_BOND_ID(bp) != BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
5863 bp->phy_flags |= PHY_SERDES_FLAG;
5864 } else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
5780 bp->phy_flags |= PHY_SERDES_FLAG; 5865 bp->phy_flags |= PHY_SERDES_FLAG;
5866
5867 if (bp->phy_flags & PHY_SERDES_FLAG) {
5781 bp->flags |= NO_WOL_FLAG; 5868 bp->flags |= NO_WOL_FLAG;
5782 if (CHIP_NUM(bp) == CHIP_NUM_5708) { 5869 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
5783 bp->phy_addr = 2; 5870 bp->phy_addr = 2;
5784 reg = REG_RD_IND(bp, bp->shmem_base + 5871 reg = REG_RD_IND(bp, bp->shmem_base +
5785 BNX2_SHARED_HW_CFG_CONFIG); 5872 BNX2_SHARED_HW_CFG_CONFIG);
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index ca31904893ea..13b6f9b11e01 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -56,6 +56,7 @@ struct rx_bd {
56 56
57}; 57};
58 58
59#define BNX2_RX_ALIGN 16
59 60
60/* 61/*
61 * status_block definition 62 * status_block definition
@@ -90,6 +91,7 @@ struct status_block {
90 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 91 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
91 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 92 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
92 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 93 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
94 #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30)
93 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 95 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
94 96
95 u32 status_attn_bits_ack; 97 u32 status_attn_bits_ack;
@@ -117,7 +119,8 @@ struct status_block {
117 u16 status_completion_producer_index; 119 u16 status_completion_producer_index;
118 u16 status_cmd_consumer_index; 120 u16 status_cmd_consumer_index;
119 u16 status_idx; 121 u16 status_idx;
120 u16 status_unused; 122 u8 status_unused;
123 u8 status_blk_num;
121#elif defined(__LITTLE_ENDIAN) 124#elif defined(__LITTLE_ENDIAN)
122 u16 status_tx_quick_consumer_index1; 125 u16 status_tx_quick_consumer_index1;
123 u16 status_tx_quick_consumer_index0; 126 u16 status_tx_quick_consumer_index0;
@@ -141,7 +144,8 @@ struct status_block {
141 u16 status_rx_quick_consumer_index14; 144 u16 status_rx_quick_consumer_index14;
142 u16 status_cmd_consumer_index; 145 u16 status_cmd_consumer_index;
143 u16 status_completion_producer_index; 146 u16 status_completion_producer_index;
144 u16 status_unused; 147 u8 status_blk_num;
148 u8 status_unused;
145 u16 status_idx; 149 u16 status_idx;
146#endif 150#endif
147}; 151};
@@ -301,6 +305,10 @@ struct l2_fhdr {
301#define BNX2_L2CTX_TXP_BIDX 0x000000a8 305#define BNX2_L2CTX_TXP_BIDX 0x000000a8
302#define BNX2_L2CTX_TXP_BSEQ 0x000000ac 306#define BNX2_L2CTX_TXP_BSEQ 0x000000ac
303 307
308#define BNX2_L2CTX_TYPE_XI 0x00000080
309#define BNX2_L2CTX_CMD_TYPE_XI 0x00000240
310#define BNX2_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
311#define BNX2_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
304 312
305/* 313/*
306 * l2_bd_chain_context definition 314 * l2_bd_chain_context definition
@@ -328,11 +336,15 @@ struct l2_fhdr {
328#define BNX2_PCICFG_MISC_CONFIG 0x00000068 336#define BNX2_PCICFG_MISC_CONFIG 0x00000068
329#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 337#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
330#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 338#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
339#define BNX2_PCICFG_MISC_CONFIG_RESERVED1 (1L<<4)
331#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 340#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
332#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 341#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
333#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 342#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
334#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 343#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
335#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 344#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
345#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1L<<10)
346#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1L<<11)
347#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1L<<12)
336#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 348#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
337#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 349#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
338#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 350#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
@@ -347,6 +359,7 @@ struct l2_fhdr {
347#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 359#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
348#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 360#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
349#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 361#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
362#define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1L<<8)
350 363
351#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 364#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
352#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 365#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
@@ -366,7 +379,7 @@ struct l2_fhdr {
366#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 379#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
367#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 380#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
368#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 381#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
369#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 382#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
370#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 383#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
371#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 384#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
372#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 385#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
@@ -374,18 +387,21 @@ struct l2_fhdr {
374#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 387#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
375#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 388#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
376#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 389#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
377#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 390#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1L<<17)
378#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 391#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
379#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 392#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1L<<19)
380#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 393#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
381 394
382#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 395#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
396#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffL<<2)
397
383#define BNX2_PCICFG_REG_WINDOW 0x00000080 398#define BNX2_PCICFG_REG_WINDOW 0x00000080
384#define BNX2_PCICFG_INT_ACK_CMD 0x00000084 399#define BNX2_PCICFG_INT_ACK_CMD 0x00000084
385#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 400#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
386#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 401#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
387#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 402#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
388#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 403#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
404#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfL<<24)
389 405
390#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088 406#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
391#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 407#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
@@ -398,9 +414,11 @@ struct l2_fhdr {
398 * offset: 0x400 414 * offset: 0x400
399 */ 415 */
400#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400 416#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
401#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 417#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13)
418#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31)
402 419
403#define BNX2_PCI_CONFIG_1 0x00000404 420#define BNX2_PCI_CONFIG_1 0x00000404
421#define BNX2_PCI_CONFIG_1_RESERVED0 (0xffL<<0)
404#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 422#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
405#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 423#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
406#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 424#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
@@ -419,6 +437,7 @@ struct l2_fhdr {
419#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 437#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
420#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 438#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
421#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 439#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
440#define BNX2_PCI_CONFIG_1_RESERVED1 (0x3ffffL<<14)
422 441
423#define BNX2_PCI_CONFIG_2 0x00000408 442#define BNX2_PCI_CONFIG_2 0x00000408
424#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 443#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
@@ -468,9 +487,13 @@ struct l2_fhdr {
468#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 487#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
469#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 488#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
470#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 489#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
490#define BNX2_PCI_CONFIG_2_RESERVED0 (0x3fL<<26)
491#define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI (1L<<16)
492#define BNX2_PCI_CONFIG_2_RESERVED0_XI (0x7fffL<<17)
471 493
472#define BNX2_PCI_CONFIG_3 0x0000040c 494#define BNX2_PCI_CONFIG_3 0x0000040c
473#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 495#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
496#define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE (0xffL<<8)
474#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24) 497#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
475#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25) 498#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
476#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) 499#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
@@ -501,8 +524,10 @@ struct l2_fhdr {
501#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0) 524#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
502 525
503#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c 526#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
504#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 527#define BNX2_PCI_VPD_ADDR_FLAG_MSK 0x0000ffff
505#define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15) 528#define BNX2_PCI_VPD_ADDR_FLAG_SL 0L
529#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fffL<<2)
530#define BNX2_PCI_VPD_ADDR_FLAG_WR (1L<<15)
506 531
507#define BNX2_PCI_VPD_DATA 0x00000430 532#define BNX2_PCI_VPD_DATA 0x00000430
508#define BNX2_PCI_ID_VAL1 0x00000434 533#define BNX2_PCI_ID_VAL1 0x00000434
@@ -535,19 +560,26 @@ struct l2_fhdr {
535#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 560#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
536#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 561#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
537#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 562#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
563#define BNX2_PCI_ID_VAL4_RESERVED0 (0x3L<<4)
538#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 564#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
539#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 565#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
540#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 566#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
541#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 567#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
542#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 568#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
569#define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP (1L<<8)
543#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 570#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
544#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 571#define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP (0x7L<<12)
545#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 572#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
546#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 573#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
547#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 574#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
548#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 575#define BNX2_PCI_ID_VAL4_RESERVED2 (0x7L<<18)
549#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 576#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21 (0x3L<<21)
550#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 577#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21 (0x3L<<23)
578#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0 (1L<<25)
579#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10 (0x3L<<26)
580#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0 (1L<<28)
581#define BNX2_PCI_ID_VAL4_RESERVED3 (0x7L<<29)
582#define BNX2_PCI_ID_VAL4_RESERVED3_XI (0xffffL<<16)
551 583
552#define BNX2_PCI_ID_VAL5 0x00000444 584#define BNX2_PCI_ID_VAL5 0x00000444
553#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 585#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
@@ -556,6 +588,10 @@ struct l2_fhdr {
556#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 588#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
557#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 589#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
558#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 590#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
591#define BNX2_PCI_ID_VAL5_RESERVED0_TE (0x3ffffffL<<6)
592#define BNX2_PCI_ID_VAL5_PM_VERSION_XI (0x7L<<6)
593#define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI (1L<<9)
594#define BNX2_PCI_ID_VAL5_RESERVED0_XI (0x3fffffL<<10)
559 595
560#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448 596#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
561#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 597#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
@@ -567,12 +603,91 @@ struct l2_fhdr {
567#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 603#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
568#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 604#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
569#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16) 605#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
606#define BNX2_PCI_ID_VAL6_RESERVED0 (0xffL<<24)
570 607
571#define BNX2_PCI_MSI_DATA 0x00000450 608#define BNX2_PCI_MSI_DATA 0x00000450
572#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 609#define BNX2_PCI_MSI_DATA_MSI_DATA (0xffffL<<0)
573 610
574#define BNX2_PCI_MSI_ADDR_H 0x00000454 611#define BNX2_PCI_MSI_ADDR_H 0x00000454
575#define BNX2_PCI_MSI_ADDR_L 0x00000458 612#define BNX2_PCI_MSI_ADDR_L 0x00000458
613#define BNX2_PCI_MSI_ADDR_L_VAL (0x3fffffffL<<2)
614
615#define BNX2_PCI_CFG_ACCESS_CMD 0x0000045c
616#define BNX2_PCI_CFG_ACCESS_CMD_ADR (0x3fL<<2)
617#define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ (1L<<27)
618#define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ (0xfL<<28)
619
620#define BNX2_PCI_CFG_ACCESS_DATA 0x00000460
621#define BNX2_PCI_MSI_MASK 0x00000464
622#define BNX2_PCI_MSI_MASK_MSI_MASK (0xffffffffL<<0)
623
624#define BNX2_PCI_MSI_PEND 0x00000468
625#define BNX2_PCI_MSI_PEND_MSI_PEND (0xffffffffL<<0)
626
627#define BNX2_PCI_PM_DATA_C 0x0000046c
628#define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG (0xffL<<0)
629#define BNX2_PCI_PM_DATA_C_RESERVED0 (0xffffffL<<8)
630
631#define BNX2_PCI_MSIX_CONTROL 0x000004c0
632#define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffL<<0)
633#define BNX2_PCI_MSIX_CONTROL_RESERVED0 (0x1fffffL<<11)
634
635#define BNX2_PCI_MSIX_TBL_OFF_BIR 0x000004c4
636#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7L<<0)
637#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffL<<3)
638
639#define BNX2_PCI_MSIX_PBA_OFF_BIT 0x000004c8
640#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7L<<0)
641#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffL<<3)
642
643#define BNX2_PCI_PCIE_CAPABILITY 0x000004d0
644#define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fL<<0)
645#define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1L<<5)
646
647#define BNX2_PCI_DEVICE_CAPABILITY 0x000004d4
648#define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7L<<0)
649#define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1L<<5)
650#define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7L<<6)
651#define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7L<<9)
652#define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1L<<15)
653
654#define BNX2_PCI_LINK_CAPABILITY 0x000004dc
655#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfL<<0)
656#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1L<<0)
657#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (1L<<0)
658#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fL<<4)
659#define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1L<<9)
660#define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3L<<10)
661#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7L<<12)
662#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5L<<12)
663#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6L<<12)
664#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7L<<15)
665#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1L<<15)
666#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2L<<15)
667#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7L<<18)
668#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5L<<18)
669#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6L<<18)
670#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7L<<21)
671#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1L<<21)
672#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2L<<21)
673#define BNX2_PCI_LINK_CAPABILITY_PORT_NUM (0xffL<<24)
674
675#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2 0x000004e4
676#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfL<<0)
677#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1L<<4)
678#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffL<<5)
679
680#define BNX2_PCI_PCIE_LINK_CAPABILITY_2 0x000004e8
681#define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffL<<0)
682
683#define BNX2_PCI_GRC_WINDOW1_ADDR 0x00000610
684#define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffL<<13)
685
686#define BNX2_PCI_GRC_WINDOW2_ADDR 0x00000614
687#define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffL<<13)
688
689#define BNX2_PCI_GRC_WINDOW3_ADDR 0x00000618
690#define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13)
576 691
577 692
578/* 693/*
@@ -582,13 +697,23 @@ struct l2_fhdr {
582#define BNX2_MISC_COMMAND 0x00000800 697#define BNX2_MISC_COMMAND 0x00000800
583#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0) 698#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
584#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1) 699#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
585#define BNX2_MISC_COMMAND_CORE_RESET (1L<<4) 700#define BNX2_MISC_COMMAND_SW_RESET (1L<<4)
586#define BNX2_MISC_COMMAND_HARD_RESET (1L<<5) 701#define BNX2_MISC_COMMAND_POR_RESET (1L<<5)
702#define BNX2_MISC_COMMAND_HD_RESET (1L<<6)
703#define BNX2_MISC_COMMAND_CMN_SW_RESET (1L<<7)
587#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8) 704#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
705#define BNX2_MISC_COMMAND_CS16_ERR (1L<<9)
706#define BNX2_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
588#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 707#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
708#define BNX2_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
709#define BNX2_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
710#define BNX2_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
711#define BNX2_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
712#define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
713#define BNX2_MISC_COMMAND_PCIE_DIS (1L<<28)
589 714
590#define BNX2_MISC_CFG 0x00000804 715#define BNX2_MISC_CFG 0x00000804
591#define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 716#define BNX2_MISC_CFG_GRC_TMOUT (1L<<0)
592#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1) 717#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
593#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 718#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
594#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 719#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
@@ -596,16 +721,45 @@ struct l2_fhdr {
596#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 721#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
597#define BNX2_MISC_CFG_BIST_EN (1L<<3) 722#define BNX2_MISC_CFG_BIST_EN (1L<<3)
598#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 723#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
599#define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5) 724#define BNX2_MISC_CFG_RESERVED5_TE (1L<<5)
600#define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6) 725#define BNX2_MISC_CFG_RESERVED6_TE (1L<<6)
601#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 726#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
602#define BNX2_MISC_CFG_LEDMODE (0x3L<<8) 727#define BNX2_MISC_CFG_LEDMODE (0x7L<<8)
603#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8) 728#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
604#define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 729#define BNX2_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
605#define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 730#define BNX2_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
731#define BNX2_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
732#define BNX2_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
733#define BNX2_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
734#define BNX2_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
735#define BNX2_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
736#define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
737#define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
738#define BNX2_MISC_CFG_LEDMODE_XI (0xfL<<8)
739#define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
740#define BNX2_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
741#define BNX2_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
742#define BNX2_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
743#define BNX2_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
744#define BNX2_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
745#define BNX2_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
746#define BNX2_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
747#define BNX2_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
748#define BNX2_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
749#define BNX2_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
750#define BNX2_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
751#define BNX2_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
752#define BNX2_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
753#define BNX2_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
754#define BNX2_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
755#define BNX2_MISC_CFG_PORT_SELECT_XI (1L<<13)
756#define BNX2_MISC_CFG_PARITY_MODE_XI (1L<<14)
606 757
607#define BNX2_MISC_ID 0x00000808 758#define BNX2_MISC_ID 0x00000808
608#define BNX2_MISC_ID_BOND_ID (0xfL<<0) 759#define BNX2_MISC_ID_BOND_ID (0xfL<<0)
760#define BNX2_MISC_ID_BOND_ID_X (0L<<0)
761#define BNX2_MISC_ID_BOND_ID_C (3L<<0)
762#define BNX2_MISC_ID_BOND_ID_S (12L<<0)
609#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4) 763#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
610#define BNX2_MISC_ID_CHIP_REV (0xfL<<12) 764#define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
611#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16) 765#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
@@ -639,6 +793,8 @@ struct l2_fhdr {
639#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 793#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
640#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 794#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
641#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 795#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
796#define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
797#define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
642 798
643#define BNX2_MISC_ENABLE_SET_BITS 0x00000810 799#define BNX2_MISC_ENABLE_SET_BITS 0x00000810
644#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 800#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
@@ -669,6 +825,8 @@ struct l2_fhdr {
669#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 825#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
670#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 826#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
671#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 827#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
828#define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
829#define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
672 830
673#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814 831#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
674#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 832#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
@@ -699,6 +857,8 @@ struct l2_fhdr {
699#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 857#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
700#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 858#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
701#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 859#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
860#define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
861#define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
702 862
703#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818 863#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
704#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 864#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
@@ -718,30 +878,41 @@ struct l2_fhdr {
718#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 878#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
719#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 879#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
720#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 880#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
721#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 881#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8)
882#define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
722#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 883#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
723#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 884#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
724#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 885#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
725#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 886#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
726#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 887#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
727#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 888#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
889#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12)
728#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 890#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
729#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 891#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
730#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 892#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
731#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 893#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
732#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 894#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20)
733 895#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
734#define BNX2_MISC_GPIO 0x0000081c 896#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18)
735#define BNX2_MISC_GPIO_VALUE (0xffL<<0) 897#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24)
736#define BNX2_MISC_GPIO_SET (0xffL<<8) 898#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
737#define BNX2_MISC_GPIO_CLR (0xffL<<16) 899#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28)
738#define BNX2_MISC_GPIO_FLOAT (0xffL<<24) 900
739 901#define BNX2_MISC_SPIO 0x0000081c
740#define BNX2_MISC_GPIO_INT 0x00000820 902#define BNX2_MISC_SPIO_VALUE (0xffL<<0)
741#define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0) 903#define BNX2_MISC_SPIO_SET (0xffL<<8)
742#define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 904#define BNX2_MISC_SPIO_CLR (0xffL<<16)
743#define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16) 905#define BNX2_MISC_SPIO_FLOAT (0xffL<<24)
744#define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 906
907#define BNX2_MISC_SPIO_INT 0x00000820
908#define BNX2_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0)
909#define BNX2_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8)
910#define BNX2_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16)
911#define BNX2_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24)
912#define BNX2_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0)
913#define BNX2_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8)
914#define BNX2_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16)
915#define BNX2_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24)
745 916
746#define BNX2_MISC_CONFIG_LFSR 0x00000824 917#define BNX2_MISC_CONFIG_LFSR 0x00000824
747#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 918#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
@@ -775,6 +946,8 @@ struct l2_fhdr {
775#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 946#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
776#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 947#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
777#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 948#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
949#define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
950#define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
778 951
779#define BNX2_MISC_ARB_REQ0 0x0000082c 952#define BNX2_MISC_ARB_REQ0 0x0000082c
780#define BNX2_MISC_ARB_REQ1 0x00000830 953#define BNX2_MISC_ARB_REQ1 0x00000830
@@ -831,22 +1004,12 @@ struct l2_fhdr {
831#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24) 1004#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
832#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28) 1005#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
833 1006
834#define BNX2_MISC_PRBS_CONTROL 0x00000878 1007#define BNX2_MISC_RESERVED1 0x00000878
835#define BNX2_MISC_PRBS_CONTROL_EN (1L<<0) 1008#define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0)
836#define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1) 1009
837#define BNX2_MISC_PRBS_CONTROL_INV (1L<<2) 1010#define BNX2_MISC_RESERVED2 0x0000087c
838#define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1011#define BNX2_MISC_RESERVED2_PCIE_DIS (1L<<0)
839#define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1012#define BNX2_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
840#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
841#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
842#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
843#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
844
845#define BNX2_MISC_PRBS_STATUS 0x0000087c
846#define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
847#define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
848#define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
849#define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
850 1013
851#define BNX2_MISC_SM_ASF_CONTROL 0x00000880 1014#define BNX2_MISC_SM_ASF_CONTROL 0x00000880
852#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1015#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
@@ -857,13 +1020,15 @@ struct l2_fhdr {
857#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1020#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
858#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1021#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
859#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1022#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
860#define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1023#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
1024#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
1025#define BNX2_MISC_SM_ASF_CONTROL_RES (0x3L<<10)
861#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1026#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
862#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1027#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
863#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1028#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
864#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1029#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
865#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1030#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16)
866#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1031#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23)
867#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1032#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
868#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1033#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
869 1034
@@ -891,13 +1056,13 @@ struct l2_fhdr {
891#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1056#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
892#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1057#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
893#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1058#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
894#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
895#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1059#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
896#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1060#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
897#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1061#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
898#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1062#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
1063#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
1064#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
899#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1065#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
900#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
901#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1066#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
902#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1067#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
903#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1068#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
@@ -955,6 +1120,38 @@ struct l2_fhdr {
955#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1120#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
956#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1121#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
957#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1122#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
1123#define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
1124#define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
1125#define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
1126#define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
1127#define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
1128#define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
1129#define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
1130#define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
1131#define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
1132#define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
1133#define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
1134#define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
1135#define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
1136#define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
1137#define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
1138#define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
1139#define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
1140#define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
1141#define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
1142#define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
1143#define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
1144#define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
1145#define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
1146#define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
1147#define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
1148#define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
1149#define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
1150#define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
1151#define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
1152#define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
1153#define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
1154#define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
958 1155
959#define BNX2_MISC_PERR_ENA1 0x000008a8 1156#define BNX2_MISC_PERR_ENA1 0x000008a8
960#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1157#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
@@ -989,6 +1186,35 @@ struct l2_fhdr {
989#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1186#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
990#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1187#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
991#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1188#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1189#define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
1190#define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
1191#define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
1192#define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
1193#define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
1194#define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
1195#define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
1196#define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
1197#define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
1198#define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
1199#define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
1200#define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
1201#define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
1202#define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
1203#define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
1204#define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
1205#define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
1206#define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
1207#define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
1208#define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
1209#define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
1210#define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
1211#define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
1212#define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
1213#define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
1214#define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
1215#define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
1216#define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
1217#define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
992 1218
993#define BNX2_MISC_PERR_ENA2 0x000008ac 1219#define BNX2_MISC_PERR_ENA2 0x000008ac
994#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1220#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
@@ -1000,19 +1226,498 @@ struct l2_fhdr {
1000#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1226#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1001#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1227#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1002#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1228#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1229#define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
1230#define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
1231#define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
1232#define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
1233#define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
1234#define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
1235#define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
1003 1236
1004#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0 1237#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
1005#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1238#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1006#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1239#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1240#define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15)
1007 1241
1008#define BNX2_MISC_VREG_CONTROL 0x000008b4 1242#define BNX2_MISC_VREG_CONTROL 0x000008b4
1009#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1243#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1244#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0)
1245#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
1246#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
1247#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
1248#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
1249#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
1250#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
1251#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
1252#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
1253#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
1254#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
1255#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
1256#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
1257#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
1258#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
1259#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
1260#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
1010#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1261#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1262#define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
1263#define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
1264#define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
1265#define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
1266#define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
1267#define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
1268#define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
1269#define BNX2_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
1270#define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
1271#define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
1272#define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
1273#define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
1274#define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
1275#define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
1276#define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
1277#define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
1278#define BNX2_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8)
1279#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
1280#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
1281#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
1282#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
1283#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
1284#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
1285#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
1286#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
1287#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
1288#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
1289#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
1290#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
1291#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
1292#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
1293#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
1294#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
1011 1295
1012#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1296#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1013#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1297#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1014 1298
1015#define BNX2_MISC_UNUSED0 0x000008bc 1299#define BNX2_MISC_GP_HW_CTL0 0x000008bc
1300#define BNX2_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
1301#define BNX2_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
1302#define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
1303#define BNX2_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
1304#define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
1305#define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
1306#define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
1307#define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4)
1308#define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
1309#define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
1310#define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
1311#define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
1312#define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8)
1313#define BNX2_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
1314#define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
1315#define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
1316#define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
1317#define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
1318#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16)
1319#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
1320#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
1321#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
1322#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
1323#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
1324#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
1325#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
1326#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
1327#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22)
1328#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
1329#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
1330#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
1331#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
1332#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24)
1333#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
1334#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
1335#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
1336#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
1337#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26)
1338#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
1339#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
1340#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
1341#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
1342#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28)
1343#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
1344#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
1345#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
1346#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
1347#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30)
1348#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
1349#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
1350#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
1351#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
1352
1353#define BNX2_MISC_GP_HW_CTL1 0x000008c0
1354#define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
1355#define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
1356#define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
1357#define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
1358#define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0)
1359#define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16)
1360
1361#define BNX2_MISC_NEW_HW_CTL 0x000008c4
1362#define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
1363#define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
1364#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
1365#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
1366#define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4)
1367#define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16)
1368
1369#define BNX2_MISC_NEW_CORE_CTL 0x000008c8
1370#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
1371#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
1372#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
1373#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
1374
1375#define BNX2_MISC_ECO_HW_CTL 0x000008cc
1376#define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
1377#define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1)
1378#define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16)
1379
1380#define BNX2_MISC_ECO_CORE_CTL 0x000008d0
1381#define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0)
1382#define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16)
1383
1384#define BNX2_MISC_PPIO 0x000008d4
1385#define BNX2_MISC_PPIO_VALUE (0xfL<<0)
1386#define BNX2_MISC_PPIO_SET (0xfL<<8)
1387#define BNX2_MISC_PPIO_CLR (0xfL<<16)
1388#define BNX2_MISC_PPIO_FLOAT (0xfL<<24)
1389
1390#define BNX2_MISC_PPIO_INT 0x000008d8
1391#define BNX2_MISC_PPIO_INT_INT_STATE (0xfL<<0)
1392#define BNX2_MISC_PPIO_INT_OLD_VALUE (0xfL<<8)
1393#define BNX2_MISC_PPIO_INT_OLD_SET (0xfL<<16)
1394#define BNX2_MISC_PPIO_INT_OLD_CLR (0xfL<<24)
1395
1396#define BNX2_MISC_RESET_NUMS 0x000008dc
1397#define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0)
1398#define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4)
1399#define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8)
1400#define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12)
1401#define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16)
1402
1403#define BNX2_MISC_CS16_ERR 0x000008e0
1404#define BNX2_MISC_CS16_ERR_ENA_PCI (1L<<0)
1405#define BNX2_MISC_CS16_ERR_ENA_RDMA (1L<<1)
1406#define BNX2_MISC_CS16_ERR_ENA_TDMA (1L<<2)
1407#define BNX2_MISC_CS16_ERR_ENA_EMAC (1L<<3)
1408#define BNX2_MISC_CS16_ERR_ENA_CTX (1L<<4)
1409#define BNX2_MISC_CS16_ERR_ENA_TBDR (1L<<5)
1410#define BNX2_MISC_CS16_ERR_ENA_RBDC (1L<<6)
1411#define BNX2_MISC_CS16_ERR_ENA_COM (1L<<7)
1412#define BNX2_MISC_CS16_ERR_ENA_CP (1L<<8)
1413#define BNX2_MISC_CS16_ERR_STA_PCI (1L<<16)
1414#define BNX2_MISC_CS16_ERR_STA_RDMA (1L<<17)
1415#define BNX2_MISC_CS16_ERR_STA_TDMA (1L<<18)
1416#define BNX2_MISC_CS16_ERR_STA_EMAC (1L<<19)
1417#define BNX2_MISC_CS16_ERR_STA_CTX (1L<<20)
1418#define BNX2_MISC_CS16_ERR_STA_TBDR (1L<<21)
1419#define BNX2_MISC_CS16_ERR_STA_RBDC (1L<<22)
1420#define BNX2_MISC_CS16_ERR_STA_COM (1L<<23)
1421#define BNX2_MISC_CS16_ERR_STA_CP (1L<<24)
1422
1423#define BNX2_MISC_SPIO_EVENT 0x000008e4
1424#define BNX2_MISC_SPIO_EVENT_ENABLE (0xffL<<0)
1425
1426#define BNX2_MISC_PPIO_EVENT 0x000008e8
1427#define BNX2_MISC_PPIO_EVENT_ENABLE (0xfL<<0)
1428
1429#define BNX2_MISC_DUAL_MEDIA_CTRL 0x000008ec
1430#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
1431#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
1432#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
1433#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
1434#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
1435#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
1436#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
1437#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
1438#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
1439#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
1440#define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
1441#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
1442#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
1443#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
1444#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
1445#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
1446#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
1447#define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
1448#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
1449#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
1450#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
1451#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
1452#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
1453
1454#define BNX2_MISC_OTP_CMD1 0x000008f0
1455#define BNX2_MISC_OTP_CMD1_FMODE (0x7L<<0)
1456#define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
1457#define BNX2_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
1458#define BNX2_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
1459#define BNX2_MISC_OTP_CMD1_FMODE_SET (3L<<0)
1460#define BNX2_MISC_OTP_CMD1_FMODE_RST (4L<<0)
1461#define BNX2_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
1462#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
1463#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
1464#define BNX2_MISC_OTP_CMD1_USEPINS (1L<<8)
1465#define BNX2_MISC_OTP_CMD1_PROGSEL (1L<<9)
1466#define BNX2_MISC_OTP_CMD1_PROGSTART (1L<<10)
1467#define BNX2_MISC_OTP_CMD1_PCOUNT (0x7L<<16)
1468#define BNX2_MISC_OTP_CMD1_PBYP (1L<<19)
1469#define BNX2_MISC_OTP_CMD1_VSEL (0xfL<<20)
1470#define BNX2_MISC_OTP_CMD1_TM (0x7L<<27)
1471#define BNX2_MISC_OTP_CMD1_SADBYP (1L<<30)
1472#define BNX2_MISC_OTP_CMD1_DEBUG (1L<<31)
1473
1474#define BNX2_MISC_OTP_CMD2 0x000008f4
1475#define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0)
1476#define BNX2_MISC_OTP_CMD2_DOSEL (0x7fL<<16)
1477#define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
1478#define BNX2_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
1479#define BNX2_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
1480
1481#define BNX2_MISC_OTP_STATUS 0x000008f8
1482#define BNX2_MISC_OTP_STATUS_DATA (0xffL<<0)
1483#define BNX2_MISC_OTP_STATUS_VALID (1L<<8)
1484#define BNX2_MISC_OTP_STATUS_BUSY (1L<<9)
1485#define BNX2_MISC_OTP_STATUS_BUSYSM (1L<<10)
1486#define BNX2_MISC_OTP_STATUS_DONE (1L<<11)
1487
1488#define BNX2_MISC_OTP_SHIFT1_CMD 0x000008fc
1489#define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
1490#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
1491#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
1492#define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
1493#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8)
1494
1495#define BNX2_MISC_OTP_SHIFT1_DATA 0x00000900
1496#define BNX2_MISC_OTP_SHIFT2_CMD 0x00000904
1497#define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
1498#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
1499#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
1500#define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
1501#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8)
1502
1503#define BNX2_MISC_OTP_SHIFT2_DATA 0x00000908
1504#define BNX2_MISC_BIST_CS0 0x0000090c
1505#define BNX2_MISC_BIST_CS0_MBIST_EN (1L<<0)
1506#define BNX2_MISC_BIST_CS0_BIST_SETUP (0x3L<<1)
1507#define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
1508#define BNX2_MISC_BIST_CS0_MBIST_DONE (1L<<8)
1509#define BNX2_MISC_BIST_CS0_MBIST_GO (1L<<9)
1510#define BNX2_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
1511
1512#define BNX2_MISC_BIST_MEMSTATUS0 0x00000910
1513#define BNX2_MISC_BIST_CS1 0x00000914
1514#define BNX2_MISC_BIST_CS1_MBIST_EN (1L<<0)
1515#define BNX2_MISC_BIST_CS1_BIST_SETUP (0x3L<<1)
1516#define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
1517#define BNX2_MISC_BIST_CS1_MBIST_DONE (1L<<8)
1518#define BNX2_MISC_BIST_CS1_MBIST_GO (1L<<9)
1519
1520#define BNX2_MISC_BIST_MEMSTATUS1 0x00000918
1521#define BNX2_MISC_BIST_CS2 0x0000091c
1522#define BNX2_MISC_BIST_CS2_MBIST_EN (1L<<0)
1523#define BNX2_MISC_BIST_CS2_BIST_SETUP (0x3L<<1)
1524#define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
1525#define BNX2_MISC_BIST_CS2_MBIST_DONE (1L<<8)
1526#define BNX2_MISC_BIST_CS2_MBIST_GO (1L<<9)
1527
1528#define BNX2_MISC_BIST_MEMSTATUS2 0x00000920
1529#define BNX2_MISC_BIST_CS3 0x00000924
1530#define BNX2_MISC_BIST_CS3_MBIST_EN (1L<<0)
1531#define BNX2_MISC_BIST_CS3_BIST_SETUP (0x3L<<1)
1532#define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
1533#define BNX2_MISC_BIST_CS3_MBIST_DONE (1L<<8)
1534#define BNX2_MISC_BIST_CS3_MBIST_GO (1L<<9)
1535
1536#define BNX2_MISC_BIST_MEMSTATUS3 0x00000928
1537#define BNX2_MISC_BIST_CS4 0x0000092c
1538#define BNX2_MISC_BIST_CS4_MBIST_EN (1L<<0)
1539#define BNX2_MISC_BIST_CS4_BIST_SETUP (0x3L<<1)
1540#define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
1541#define BNX2_MISC_BIST_CS4_MBIST_DONE (1L<<8)
1542#define BNX2_MISC_BIST_CS4_MBIST_GO (1L<<9)
1543
1544#define BNX2_MISC_BIST_MEMSTATUS4 0x00000930
1545#define BNX2_MISC_BIST_CS5 0x00000934
1546#define BNX2_MISC_BIST_CS5_MBIST_EN (1L<<0)
1547#define BNX2_MISC_BIST_CS5_BIST_SETUP (0x3L<<1)
1548#define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
1549#define BNX2_MISC_BIST_CS5_MBIST_DONE (1L<<8)
1550#define BNX2_MISC_BIST_CS5_MBIST_GO (1L<<9)
1551
1552#define BNX2_MISC_BIST_MEMSTATUS5 0x00000938
1553#define BNX2_MISC_MEM_TM0 0x0000093c
1554#define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0)
1555#define BNX2_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8)
1556#define BNX2_MISC_MEM_TM0_UMP_TM (0xffL<<16)
1557#define BNX2_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24)
1558
1559#define BNX2_MISC_USPLL_CTRL 0x00000940
1560#define BNX2_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
1561#define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
1562#define BNX2_MISC_USPLL_CTRL_LCPX (0x3fL<<2)
1563#define BNX2_MISC_USPLL_CTRL_RX (0x3L<<8)
1564#define BNX2_MISC_USPLL_CTRL_VC_EN (1L<<10)
1565#define BNX2_MISC_USPLL_CTRL_VCO_MG (0x3L<<11)
1566#define BNX2_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13)
1567#define BNX2_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16)
1568#define BNX2_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
1569#define BNX2_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20)
1570#define BNX2_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
1571#define BNX2_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24)
1572#define BNX2_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
1573#define BNX2_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
1574#define BNX2_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
1575#define BNX2_MISC_USPLL_CTRL_LOCK (1L<<29)
1576
1577#define BNX2_MISC_PERR_STATUS0 0x00000944
1578#define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
1579#define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
1580#define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
1581#define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
1582#define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
1583#define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
1584#define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
1585#define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
1586#define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
1587#define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
1588#define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
1589#define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
1590#define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
1591#define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
1592#define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
1593#define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
1594#define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
1595#define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
1596#define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
1597#define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
1598#define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
1599#define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
1600#define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
1601#define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
1602#define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
1603#define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
1604#define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
1605#define BNX2_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
1606#define BNX2_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
1607#define BNX2_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
1608#define BNX2_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
1609#define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
1610
1611#define BNX2_MISC_PERR_STATUS1 0x00000948
1612#define BNX2_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
1613#define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
1614#define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
1615#define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
1616#define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
1617#define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
1618#define BNX2_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
1619#define BNX2_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
1620#define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
1621#define BNX2_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
1622#define BNX2_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
1623#define BNX2_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
1624#define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
1625#define BNX2_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
1626#define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
1627#define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
1628#define BNX2_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
1629#define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
1630#define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
1631#define BNX2_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
1632#define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
1633#define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
1634#define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
1635#define BNX2_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
1636#define BNX2_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
1637#define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
1638#define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
1639#define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
1640#define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
1641
1642#define BNX2_MISC_PERR_STATUS2 0x0000094c
1643#define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
1644#define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
1645#define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
1646#define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
1647#define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
1648#define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
1649#define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
1650
1651#define BNX2_MISC_LCPLL_CTRL0 0x00000950
1652#define BNX2_MISC_LCPLL_CTRL0_OAC (0x7L<<0)
1653#define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
1654#define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
1655#define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
1656#define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
1657#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3)
1658#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
1659#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
1660#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
1661#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
1662#define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6)
1663#define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8)
1664#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11)
1665#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
1666#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
1667#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
1668#define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
1669#define BNX2_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
1670#define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
1671#define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
1672#define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
1673#define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
1674#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
1675#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
1676#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
1677#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
1678#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
1679#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
1680#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
1681#define BNX2_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
1682#define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
1683
1684#define BNX2_MISC_LCPLL_CTRL1 0x00000954
1685#define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0)
1686#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
1687#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
1688#define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
1689
1690#define BNX2_MISC_LCPLL_STATUS 0x00000958
1691#define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
1692#define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
1693#define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
1694#define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
1695#define BNX2_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4)
1696#define BNX2_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7)
1697#define BNX2_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10)
1698#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
1699#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
1700#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
1701
1702#define BNX2_MISC_OSCFUNDS_CTRL 0x0000095c
1703#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
1704#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
1705#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
1706#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6)
1707#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
1708#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
1709#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
1710#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
1711#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8)
1712#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
1713#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
1714#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
1715#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
1716#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10)
1717#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
1718#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
1719#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
1720#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
1016 1721
1017 1722
1018/* 1723/*
@@ -1031,11 +1736,35 @@ struct l2_fhdr {
1031#define BNX2_NVM_COMMAND_WRDI (1L<<17) 1736#define BNX2_NVM_COMMAND_WRDI (1L<<17)
1032#define BNX2_NVM_COMMAND_EWSR (1L<<18) 1737#define BNX2_NVM_COMMAND_EWSR (1L<<18)
1033#define BNX2_NVM_COMMAND_WRSR (1L<<19) 1738#define BNX2_NVM_COMMAND_WRSR (1L<<19)
1739#define BNX2_NVM_COMMAND_RD_ID (1L<<20)
1740#define BNX2_NVM_COMMAND_RD_STATUS (1L<<21)
1741#define BNX2_NVM_COMMAND_MODE_256 (1L<<22)
1034 1742
1035#define BNX2_NVM_STATUS 0x00006404 1743#define BNX2_NVM_STATUS 0x00006404
1036#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1744#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1037#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1745#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1038#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1746#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1747#define BNX2_NVM_STATUS_SPI_FSM_STATE_XI (0x1fL<<0)
1748#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0)
1749#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1L<<0)
1750#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2L<<0)
1751#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3L<<0)
1752#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4L<<0)
1753#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5L<<0)
1754#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6L<<0)
1755#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7L<<0)
1756#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8L<<0)
1757#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9L<<0)
1758#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10L<<0)
1759#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11L<<0)
1760#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12L<<0)
1761#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13L<<0)
1762#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14L<<0)
1763#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15L<<0)
1764#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16L<<0)
1765#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17L<<0)
1766#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18L<<0)
1767#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19L<<0)
1039 1768
1040#define BNX2_NVM_WRITE 0x00006408 1769#define BNX2_NVM_WRITE 0x00006408
1041#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1770#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
@@ -1046,6 +1775,10 @@ struct l2_fhdr {
1046#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1775#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1047#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1776#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1048#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1777#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1778#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1L<<0)
1779#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2L<<0)
1780#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4L<<0)
1781#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8L<<0)
1049 1782
1050#define BNX2_NVM_ADDR 0x0000640c 1783#define BNX2_NVM_ADDR 0x0000640c
1051#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1784#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
@@ -1056,6 +1789,10 @@ struct l2_fhdr {
1056#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1789#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1057#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1790#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1058#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1791#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1792#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1L<<0)
1793#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2L<<0)
1794#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4L<<0)
1795#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8L<<0)
1059 1796
1060#define BNX2_NVM_READ 0x00006410 1797#define BNX2_NVM_READ 0x00006410
1061#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1798#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
@@ -1066,6 +1803,10 @@ struct l2_fhdr {
1066#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1803#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1067#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1804#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1068#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1805#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1806#define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI (1L<<0)
1807#define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI (2L<<0)
1808#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI (4L<<0)
1809#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI (8L<<0)
1069 1810
1070#define BNX2_NVM_CFG1 0x00006414 1811#define BNX2_NVM_CFG1 0x00006414
1071#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0) 1812#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
@@ -1077,14 +1818,21 @@ struct l2_fhdr {
1077#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1818#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1078#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1819#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1079#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1820#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1821#define BNX2_NVM_CFG1_STRAP_CONTROL_0 (1L<<23)
1080#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24) 1822#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
1081#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25) 1823#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
1824#define BNX2_NVM_CFG1_FW_USTRAP_1 (1L<<26)
1825#define BNX2_NVM_CFG1_FW_USTRAP_0 (1L<<27)
1826#define BNX2_NVM_CFG1_FW_USTRAP_2 (1L<<28)
1827#define BNX2_NVM_CFG1_FW_USTRAP_3 (1L<<29)
1828#define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30)
1082#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1829#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1083 1830
1084#define BNX2_NVM_CFG2 0x00006418 1831#define BNX2_NVM_CFG2 0x00006418
1085#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) 1832#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
1086#define BNX2_NVM_CFG2_DUMMY (0xffL<<8) 1833#define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
1087#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16) 1834#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
1835#define BNX2_NVM_CFG2_READ_ID (0xffL<<24)
1088 1836
1089#define BNX2_NVM_CFG3 0x0000641c 1837#define BNX2_NVM_CFG3 0x0000641c
1090#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1838#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
@@ -1119,6 +1867,35 @@ struct l2_fhdr {
1119#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1867#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1120#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16) 1868#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
1121 1869
1870#define BNX2_NVM_CFG4 0x0000642c
1871#define BNX2_NVM_CFG4_FLASH_SIZE (0x7L<<0)
1872#define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
1873#define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
1874#define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
1875#define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
1876#define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
1877#define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
1878#define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
1879#define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
1880#define BNX2_NVM_CFG4_FLASH_VENDOR (1L<<3)
1881#define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
1882#define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3)
1883#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4)
1884#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
1885#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4)
1886#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4)
1887#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4)
1888#define BNX2_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6)
1889#define BNX2_NVM_CFG4_RESERVED (0x1ffffffL<<7)
1890
1891#define BNX2_NVM_RECONFIG 0x00006430
1892#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0)
1893#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
1894#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
1895#define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4)
1896#define BNX2_NVM_RECONFIG_RESERVED (0x7fffffL<<8)
1897#define BNX2_NVM_RECONFIG_RECONFIG_DONE (1L<<31)
1898
1122 1899
1123 1900
1124/* 1901/*
@@ -1140,6 +1917,8 @@ struct l2_fhdr {
1140#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1917#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1141#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1918#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1142#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1919#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1920#define BNX2_DMA_STATUS_GLOBAL_ERR_XI (1L<<0)
1921#define BNX2_DMA_STATUS_BME_XI (1L<<4)
1143 1922
1144#define BNX2_DMA_CONFIG 0x00000c08 1923#define BNX2_DMA_CONFIG 0x00000c08
1145#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1924#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
@@ -1161,85 +1940,315 @@ struct l2_fhdr {
1161#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1940#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1162#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1941#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1163#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1942#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1943#define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3L<<0)
1944#define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3L<<4)
1945#define BNX2_DMA_CONFIG_MAX_PL_XI (0x7L<<12)
1946#define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12)
1947#define BNX2_DMA_CONFIG_MAX_PL_256B_XI (1L<<12)
1948#define BNX2_DMA_CONFIG_MAX_PL_512B_XI (2L<<12)
1949#define BNX2_DMA_CONFIG_MAX_PL_EN_XI (1L<<15)
1950#define BNX2_DMA_CONFIG_MAX_RRS_XI (0x7L<<16)
1951#define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16)
1952#define BNX2_DMA_CONFIG_MAX_RRS_256B_XI (1L<<16)
1953#define BNX2_DMA_CONFIG_MAX_RRS_512B_XI (2L<<16)
1954#define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI (3L<<16)
1955#define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI (4L<<16)
1956#define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI (5L<<16)
1957#define BNX2_DMA_CONFIG_MAX_RRS_EN_XI (1L<<19)
1958#define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI (1L<<31)
1164 1959
1165#define BNX2_DMA_BLACKOUT 0x00000c0c 1960#define BNX2_DMA_BLACKOUT 0x00000c0c
1166#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1961#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1167#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1962#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1168#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1963#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1169 1964
1170#define BNX2_DMA_RCHAN_STAT 0x00000c30 1965#define BNX2_DMA_READ_MASTER_SETTING_0 0x00000c10
1171#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1966#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1L<<0)
1172#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1967#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1L<<1)
1173#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1968#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1L<<2)
1174#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1969#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7L<<4)
1175#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1970#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1L<<7)
1176#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1971#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1L<<8)
1177#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1972#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1L<<9)
1178#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1973#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1L<<10)
1179#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1974#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7L<<12)
1180#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1975#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1L<<15)
1181#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1976#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1L<<16)
1182#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1977#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1L<<17)
1183#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1978#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1L<<18)
1184#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1979#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7L<<20)
1185#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1980#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1L<<23)
1186#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1981#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
1187 1982#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
1188#define BNX2_DMA_WCHAN_STAT 0x00000c34 1983#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
1189#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1984#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
1190#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1985#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
1191#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1986
1192#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1987#define BNX2_DMA_READ_MASTER_SETTING_1 0x00000c14
1193#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1988#define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
1194#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1989#define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
1195#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1990#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
1196#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1991#define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
1197#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1992#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
1198#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1993#define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
1199#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1994#define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
1200#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1995#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
1201#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1996#define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
1202#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1997#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
1203#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1998
1204#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1999#define BNX2_DMA_WRITE_MASTER_SETTING_0 0x00000c18
1205 2000#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1L<<0)
1206#define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38 2001#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1L<<1)
1207#define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 2002#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1L<<2)
1208#define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 2003#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1L<<3)
1209#define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 2004#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7L<<4)
1210#define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 2005#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1L<<7)
1211#define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 2006#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1L<<8)
1212#define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 2007#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1L<<9)
1213#define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 2008#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1L<<10)
1214#define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 2009#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1L<<11)
1215 2010#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7L<<12)
1216#define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c 2011#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1L<<15)
1217#define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 2012#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
1218#define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 2013#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
1219#define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 2014#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
1220#define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 2015#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1L<<27)
1221#define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 2016#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
1222#define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 2017#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
1223#define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 2018
1224#define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 2019#define BNX2_DMA_WRITE_MASTER_SETTING_1 0x00000c1c
1225 2020#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
1226#define BNX2_DMA_RCHAN_STAT_00 0x00000c40 2021#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
1227#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2022#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
1228 2023#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1L<<3)
1229#define BNX2_DMA_RCHAN_STAT_01 0x00000c44 2024#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
1230#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2025#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
1231 2026#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
1232#define BNX2_DMA_RCHAN_STAT_02 0x00000c48 2027#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
1233#define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 2028#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
1234#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 2029#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1L<<11)
1235#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 2030#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
1236#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2031#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
1237 2032
1238#define BNX2_DMA_RCHAN_STAT_10 0x00000c4c 2033#define BNX2_DMA_ARBITER 0x00000c20
1239#define BNX2_DMA_RCHAN_STAT_11 0x00000c50 2034#define BNX2_DMA_ARBITER_NUM_READS (0x7L<<0)
1240#define BNX2_DMA_RCHAN_STAT_12 0x00000c54 2035#define BNX2_DMA_ARBITER_WR_ARB_MODE (1L<<4)
1241#define BNX2_DMA_RCHAN_STAT_20 0x00000c58 2036#define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4)
1242#define BNX2_DMA_RCHAN_STAT_21 0x00000c5c 2037#define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN (1L<<4)
2038#define BNX2_DMA_ARBITER_RD_ARB_MODE (0x3L<<5)
2039#define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5)
2040#define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN (1L<<5)
2041#define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2L<<5)
2042#define BNX2_DMA_ARBITER_ALT_MODE_EN (1L<<8)
2043#define BNX2_DMA_ARBITER_RR_MODE (1L<<9)
2044#define BNX2_DMA_ARBITER_TIMER_MODE (1L<<10)
2045#define BNX2_DMA_ARBITER_OUSTD_READ_REQ (0xfL<<12)
2046
2047#define BNX2_DMA_ARB_TIMERS 0x00000c24
2048#define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffL<<0)
2049#define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffL<<12)
2050#define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffL<<20)
2051
2052#define BNX2_DMA_DEBUG_VECT_PEEK 0x00000c2c
2053#define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2054#define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2055#define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2056#define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2057#define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2058#define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2059
2060#define BNX2_DMA_TAG_RAM_00 0x00000c30
2061#define BNX2_DMA_TAG_RAM_00_CHANNEL (0xfL<<0)
2062#define BNX2_DMA_TAG_RAM_00_MASTER (0x7L<<4)
2063#define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4)
2064#define BNX2_DMA_TAG_RAM_00_MASTER_RBDC (1L<<4)
2065#define BNX2_DMA_TAG_RAM_00_MASTER_TBDC (2L<<4)
2066#define BNX2_DMA_TAG_RAM_00_MASTER_COM (3L<<4)
2067#define BNX2_DMA_TAG_RAM_00_MASTER_CP (4L<<4)
2068#define BNX2_DMA_TAG_RAM_00_MASTER_TDMA (5L<<4)
2069#define BNX2_DMA_TAG_RAM_00_SWAP (0x3L<<7)
2070#define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7)
2071#define BNX2_DMA_TAG_RAM_00_SWAP_DATA (1L<<7)
2072#define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL (2L<<7)
2073#define BNX2_DMA_TAG_RAM_00_FUNCTION (1L<<9)
2074#define BNX2_DMA_TAG_RAM_00_VALID (1L<<10)
2075
2076#define BNX2_DMA_TAG_RAM_01 0x00000c34
2077#define BNX2_DMA_TAG_RAM_01_CHANNEL (0xfL<<0)
2078#define BNX2_DMA_TAG_RAM_01_MASTER (0x7L<<4)
2079#define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4)
2080#define BNX2_DMA_TAG_RAM_01_MASTER_RBDC (1L<<4)
2081#define BNX2_DMA_TAG_RAM_01_MASTER_TBDC (2L<<4)
2082#define BNX2_DMA_TAG_RAM_01_MASTER_COM (3L<<4)
2083#define BNX2_DMA_TAG_RAM_01_MASTER_CP (4L<<4)
2084#define BNX2_DMA_TAG_RAM_01_MASTER_TDMA (5L<<4)
2085#define BNX2_DMA_TAG_RAM_01_SWAP (0x3L<<7)
2086#define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7)
2087#define BNX2_DMA_TAG_RAM_01_SWAP_DATA (1L<<7)
2088#define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL (2L<<7)
2089#define BNX2_DMA_TAG_RAM_01_FUNCTION (1L<<9)
2090#define BNX2_DMA_TAG_RAM_01_VALID (1L<<10)
2091
2092#define BNX2_DMA_TAG_RAM_02 0x00000c38
2093#define BNX2_DMA_TAG_RAM_02_CHANNEL (0xfL<<0)
2094#define BNX2_DMA_TAG_RAM_02_MASTER (0x7L<<4)
2095#define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4)
2096#define BNX2_DMA_TAG_RAM_02_MASTER_RBDC (1L<<4)
2097#define BNX2_DMA_TAG_RAM_02_MASTER_TBDC (2L<<4)
2098#define BNX2_DMA_TAG_RAM_02_MASTER_COM (3L<<4)
2099#define BNX2_DMA_TAG_RAM_02_MASTER_CP (4L<<4)
2100#define BNX2_DMA_TAG_RAM_02_MASTER_TDMA (5L<<4)
2101#define BNX2_DMA_TAG_RAM_02_SWAP (0x3L<<7)
2102#define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7)
2103#define BNX2_DMA_TAG_RAM_02_SWAP_DATA (1L<<7)
2104#define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL (2L<<7)
2105#define BNX2_DMA_TAG_RAM_02_FUNCTION (1L<<9)
2106#define BNX2_DMA_TAG_RAM_02_VALID (1L<<10)
2107
2108#define BNX2_DMA_TAG_RAM_03 0x00000c3c
2109#define BNX2_DMA_TAG_RAM_03_CHANNEL (0xfL<<0)
2110#define BNX2_DMA_TAG_RAM_03_MASTER (0x7L<<4)
2111#define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4)
2112#define BNX2_DMA_TAG_RAM_03_MASTER_RBDC (1L<<4)
2113#define BNX2_DMA_TAG_RAM_03_MASTER_TBDC (2L<<4)
2114#define BNX2_DMA_TAG_RAM_03_MASTER_COM (3L<<4)
2115#define BNX2_DMA_TAG_RAM_03_MASTER_CP (4L<<4)
2116#define BNX2_DMA_TAG_RAM_03_MASTER_TDMA (5L<<4)
2117#define BNX2_DMA_TAG_RAM_03_SWAP (0x3L<<7)
2118#define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7)
2119#define BNX2_DMA_TAG_RAM_03_SWAP_DATA (1L<<7)
2120#define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL (2L<<7)
2121#define BNX2_DMA_TAG_RAM_03_FUNCTION (1L<<9)
2122#define BNX2_DMA_TAG_RAM_03_VALID (1L<<10)
2123
2124#define BNX2_DMA_TAG_RAM_04 0x00000c40
2125#define BNX2_DMA_TAG_RAM_04_CHANNEL (0xfL<<0)
2126#define BNX2_DMA_TAG_RAM_04_MASTER (0x7L<<4)
2127#define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4)
2128#define BNX2_DMA_TAG_RAM_04_MASTER_RBDC (1L<<4)
2129#define BNX2_DMA_TAG_RAM_04_MASTER_TBDC (2L<<4)
2130#define BNX2_DMA_TAG_RAM_04_MASTER_COM (3L<<4)
2131#define BNX2_DMA_TAG_RAM_04_MASTER_CP (4L<<4)
2132#define BNX2_DMA_TAG_RAM_04_MASTER_TDMA (5L<<4)
2133#define BNX2_DMA_TAG_RAM_04_SWAP (0x3L<<7)
2134#define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7)
2135#define BNX2_DMA_TAG_RAM_04_SWAP_DATA (1L<<7)
2136#define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL (2L<<7)
2137#define BNX2_DMA_TAG_RAM_04_FUNCTION (1L<<9)
2138#define BNX2_DMA_TAG_RAM_04_VALID (1L<<10)
2139
2140#define BNX2_DMA_TAG_RAM_05 0x00000c44
2141#define BNX2_DMA_TAG_RAM_05_CHANNEL (0xfL<<0)
2142#define BNX2_DMA_TAG_RAM_05_MASTER (0x7L<<4)
2143#define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4)
2144#define BNX2_DMA_TAG_RAM_05_MASTER_RBDC (1L<<4)
2145#define BNX2_DMA_TAG_RAM_05_MASTER_TBDC (2L<<4)
2146#define BNX2_DMA_TAG_RAM_05_MASTER_COM (3L<<4)
2147#define BNX2_DMA_TAG_RAM_05_MASTER_CP (4L<<4)
2148#define BNX2_DMA_TAG_RAM_05_MASTER_TDMA (5L<<4)
2149#define BNX2_DMA_TAG_RAM_05_SWAP (0x3L<<7)
2150#define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7)
2151#define BNX2_DMA_TAG_RAM_05_SWAP_DATA (1L<<7)
2152#define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL (2L<<7)
2153#define BNX2_DMA_TAG_RAM_05_FUNCTION (1L<<9)
2154#define BNX2_DMA_TAG_RAM_05_VALID (1L<<10)
2155
2156#define BNX2_DMA_TAG_RAM_06 0x00000c48
2157#define BNX2_DMA_TAG_RAM_06_CHANNEL (0xfL<<0)
2158#define BNX2_DMA_TAG_RAM_06_MASTER (0x7L<<4)
2159#define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4)
2160#define BNX2_DMA_TAG_RAM_06_MASTER_RBDC (1L<<4)
2161#define BNX2_DMA_TAG_RAM_06_MASTER_TBDC (2L<<4)
2162#define BNX2_DMA_TAG_RAM_06_MASTER_COM (3L<<4)
2163#define BNX2_DMA_TAG_RAM_06_MASTER_CP (4L<<4)
2164#define BNX2_DMA_TAG_RAM_06_MASTER_TDMA (5L<<4)
2165#define BNX2_DMA_TAG_RAM_06_SWAP (0x3L<<7)
2166#define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7)
2167#define BNX2_DMA_TAG_RAM_06_SWAP_DATA (1L<<7)
2168#define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL (2L<<7)
2169#define BNX2_DMA_TAG_RAM_06_FUNCTION (1L<<9)
2170#define BNX2_DMA_TAG_RAM_06_VALID (1L<<10)
2171
2172#define BNX2_DMA_TAG_RAM_07 0x00000c4c
2173#define BNX2_DMA_TAG_RAM_07_CHANNEL (0xfL<<0)
2174#define BNX2_DMA_TAG_RAM_07_MASTER (0x7L<<4)
2175#define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4)
2176#define BNX2_DMA_TAG_RAM_07_MASTER_RBDC (1L<<4)
2177#define BNX2_DMA_TAG_RAM_07_MASTER_TBDC (2L<<4)
2178#define BNX2_DMA_TAG_RAM_07_MASTER_COM (3L<<4)
2179#define BNX2_DMA_TAG_RAM_07_MASTER_CP (4L<<4)
2180#define BNX2_DMA_TAG_RAM_07_MASTER_TDMA (5L<<4)
2181#define BNX2_DMA_TAG_RAM_07_SWAP (0x3L<<7)
2182#define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7)
2183#define BNX2_DMA_TAG_RAM_07_SWAP_DATA (1L<<7)
2184#define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL (2L<<7)
2185#define BNX2_DMA_TAG_RAM_07_FUNCTION (1L<<9)
2186#define BNX2_DMA_TAG_RAM_07_VALID (1L<<10)
2187
2188#define BNX2_DMA_TAG_RAM_08 0x00000c50
2189#define BNX2_DMA_TAG_RAM_08_CHANNEL (0xfL<<0)
2190#define BNX2_DMA_TAG_RAM_08_MASTER (0x7L<<4)
2191#define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4)
2192#define BNX2_DMA_TAG_RAM_08_MASTER_RBDC (1L<<4)
2193#define BNX2_DMA_TAG_RAM_08_MASTER_TBDC (2L<<4)
2194#define BNX2_DMA_TAG_RAM_08_MASTER_COM (3L<<4)
2195#define BNX2_DMA_TAG_RAM_08_MASTER_CP (4L<<4)
2196#define BNX2_DMA_TAG_RAM_08_MASTER_TDMA (5L<<4)
2197#define BNX2_DMA_TAG_RAM_08_SWAP (0x3L<<7)
2198#define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7)
2199#define BNX2_DMA_TAG_RAM_08_SWAP_DATA (1L<<7)
2200#define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL (2L<<7)
2201#define BNX2_DMA_TAG_RAM_08_FUNCTION (1L<<9)
2202#define BNX2_DMA_TAG_RAM_08_VALID (1L<<10)
2203
2204#define BNX2_DMA_TAG_RAM_09 0x00000c54
2205#define BNX2_DMA_TAG_RAM_09_CHANNEL (0xfL<<0)
2206#define BNX2_DMA_TAG_RAM_09_MASTER (0x7L<<4)
2207#define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4)
2208#define BNX2_DMA_TAG_RAM_09_MASTER_RBDC (1L<<4)
2209#define BNX2_DMA_TAG_RAM_09_MASTER_TBDC (2L<<4)
2210#define BNX2_DMA_TAG_RAM_09_MASTER_COM (3L<<4)
2211#define BNX2_DMA_TAG_RAM_09_MASTER_CP (4L<<4)
2212#define BNX2_DMA_TAG_RAM_09_MASTER_TDMA (5L<<4)
2213#define BNX2_DMA_TAG_RAM_09_SWAP (0x3L<<7)
2214#define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7)
2215#define BNX2_DMA_TAG_RAM_09_SWAP_DATA (1L<<7)
2216#define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL (2L<<7)
2217#define BNX2_DMA_TAG_RAM_09_FUNCTION (1L<<9)
2218#define BNX2_DMA_TAG_RAM_09_VALID (1L<<10)
2219
2220#define BNX2_DMA_TAG_RAM_10 0x00000c58
2221#define BNX2_DMA_TAG_RAM_10_CHANNEL (0xfL<<0)
2222#define BNX2_DMA_TAG_RAM_10_MASTER (0x7L<<4)
2223#define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4)
2224#define BNX2_DMA_TAG_RAM_10_MASTER_RBDC (1L<<4)
2225#define BNX2_DMA_TAG_RAM_10_MASTER_TBDC (2L<<4)
2226#define BNX2_DMA_TAG_RAM_10_MASTER_COM (3L<<4)
2227#define BNX2_DMA_TAG_RAM_10_MASTER_CP (4L<<4)
2228#define BNX2_DMA_TAG_RAM_10_MASTER_TDMA (5L<<4)
2229#define BNX2_DMA_TAG_RAM_10_SWAP (0x3L<<7)
2230#define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7)
2231#define BNX2_DMA_TAG_RAM_10_SWAP_DATA (1L<<7)
2232#define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL (2L<<7)
2233#define BNX2_DMA_TAG_RAM_10_FUNCTION (1L<<9)
2234#define BNX2_DMA_TAG_RAM_10_VALID (1L<<10)
2235
2236#define BNX2_DMA_TAG_RAM_11 0x00000c5c
2237#define BNX2_DMA_TAG_RAM_11_CHANNEL (0xfL<<0)
2238#define BNX2_DMA_TAG_RAM_11_MASTER (0x7L<<4)
2239#define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4)
2240#define BNX2_DMA_TAG_RAM_11_MASTER_RBDC (1L<<4)
2241#define BNX2_DMA_TAG_RAM_11_MASTER_TBDC (2L<<4)
2242#define BNX2_DMA_TAG_RAM_11_MASTER_COM (3L<<4)
2243#define BNX2_DMA_TAG_RAM_11_MASTER_CP (4L<<4)
2244#define BNX2_DMA_TAG_RAM_11_MASTER_TDMA (5L<<4)
2245#define BNX2_DMA_TAG_RAM_11_SWAP (0x3L<<7)
2246#define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7)
2247#define BNX2_DMA_TAG_RAM_11_SWAP_DATA (1L<<7)
2248#define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL (2L<<7)
2249#define BNX2_DMA_TAG_RAM_11_FUNCTION (1L<<9)
2250#define BNX2_DMA_TAG_RAM_11_VALID (1L<<10)
2251
1243#define BNX2_DMA_RCHAN_STAT_22 0x00000c60 2252#define BNX2_DMA_RCHAN_STAT_22 0x00000c60
1244#define BNX2_DMA_RCHAN_STAT_30 0x00000c64 2253#define BNX2_DMA_RCHAN_STAT_30 0x00000c64
1245#define BNX2_DMA_RCHAN_STAT_31 0x00000c68 2254#define BNX2_DMA_RCHAN_STAT_31 0x00000c68
@@ -1336,6 +2345,25 @@ struct l2_fhdr {
1336 */ 2345 */
1337#define BNX2_CTX_COMMAND 0x00001000 2346#define BNX2_CTX_COMMAND 0x00001000
1338#define BNX2_CTX_COMMAND_ENABLED (1L<<0) 2347#define BNX2_CTX_COMMAND_ENABLED (1L<<0)
2348#define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
2349#define BNX2_CTX_COMMAND_DISABLE_PLRU (1L<<2)
2350#define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
2351#define BNX2_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
2352#define BNX2_CTX_COMMAND_MEM_INIT (1L<<13)
2353#define BNX2_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
2354#define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2355#define BNX2_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
2356#define BNX2_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
2357#define BNX2_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
2358#define BNX2_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
2359#define BNX2_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
2360#define BNX2_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
2361#define BNX2_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
2362#define BNX2_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
2363#define BNX2_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
2364#define BNX2_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
2365#define BNX2_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
2366#define BNX2_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
1339 2367
1340#define BNX2_CTX_STATUS 0x00001004 2368#define BNX2_CTX_STATUS 0x00001004
1341#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0) 2369#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
@@ -1343,6 +2371,13 @@ struct l2_fhdr {
1343#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17) 2371#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
1344#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2372#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
1345#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2373#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
2374#define BNX2_CTX_STATUS_EXT_READ_STAT (1L<<20)
2375#define BNX2_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
2376#define BNX2_CTX_STATUS_MISS_STAT (1L<<22)
2377#define BNX2_CTX_STATUS_HIT_STAT (1L<<23)
2378#define BNX2_CTX_STATUS_DEAD_LOCK (1L<<24)
2379#define BNX2_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
2380#define BNX2_CTX_STATUS_INVALID_PAGE (1L<<26)
1346 2381
1347#define BNX2_CTX_VIRT_ADDR 0x00001008 2382#define BNX2_CTX_VIRT_ADDR 0x00001008
1348#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2383#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
@@ -1357,10 +2392,15 @@ struct l2_fhdr {
1357#define BNX2_CTX_LOCK 0x00001018 2392#define BNX2_CTX_LOCK 0x00001018
1358#define BNX2_CTX_LOCK_TYPE (0x7L<<0) 2393#define BNX2_CTX_LOCK_TYPE (0x7L<<0)
1359#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2394#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
1360#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
1361#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2395#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
1362#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2396#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
1363#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2397#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
2398#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
2399#define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0)
2400#define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
2401#define BNX2_CTX_LOCK_TYPE_TX_XI (2L<<0)
2402#define BNX2_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
2403#define BNX2_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
1364#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2404#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
1365#define BNX2_CTX_LOCK_GRANTED (1L<<26) 2405#define BNX2_CTX_LOCK_GRANTED (1L<<26)
1366#define BNX2_CTX_LOCK_MODE (0x7L<<27) 2406#define BNX2_CTX_LOCK_MODE (0x7L<<27)
@@ -1370,21 +2410,89 @@ struct l2_fhdr {
1370#define BNX2_CTX_LOCK_STATUS (1L<<30) 2410#define BNX2_CTX_LOCK_STATUS (1L<<30)
1371#define BNX2_CTX_LOCK_REQ (1L<<31) 2411#define BNX2_CTX_LOCK_REQ (1L<<31)
1372 2412
2413#define BNX2_CTX_CTX_CTRL 0x0000101c
2414#define BNX2_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
2415#define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
2416#define BNX2_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
2417#define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
2418#define BNX2_CTX_CTX_CTRL_ATTR (1L<<26)
2419#define BNX2_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
2420#define BNX2_CTX_CTX_CTRL_READ_REQ (1L<<31)
2421
2422#define BNX2_CTX_CTX_DATA 0x00001020
1373#define BNX2_CTX_ACCESS_STATUS 0x00001040 2423#define BNX2_CTX_ACCESS_STATUS 0x00001040
1374#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2424#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
1375#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2425#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
1376#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2426#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
1377#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2427#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
1378#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2428#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
2429#define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
2430#define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
2431#define BNX2_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
1379 2432
1380#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044 2433#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
1381#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2434#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
1382#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2435#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
1383 2436
2437#define BNX2_CTX_CACHE_CTRL_STATUS 0x00001048
2438#define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
2439#define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
2440#define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
2441#define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7)
2442#define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13)
2443#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
2444#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
2445#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
2446#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
2447#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
2448#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
2449#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
2450#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
2451#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
2452#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
2453#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
2454
2455#define BNX2_CTX_CACHE_CTRL_SM_STATUS 0x0000104c
2456#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0)
2457#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3)
2458#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6)
2459#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9)
2460#define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16)
2461
2462#define BNX2_CTX_CACHE_STATUS 0x00001050
2463#define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0)
2464#define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16)
2465
2466#define BNX2_CTX_DMA_STATUS 0x00001054
2467#define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0)
2468#define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2)
2469#define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4)
2470#define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6)
2471#define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8)
2472#define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10)
2473#define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12)
2474#define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14)
2475#define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16)
2476#define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18)
2477#define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20)
2478
2479#define BNX2_CTX_REP_STATUS 0x00001058
2480#define BNX2_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0)
2481#define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10)
2482#define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
2483#define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
2484#define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
2485
2486#define BNX2_CTX_CKSUM_ERROR_STATUS 0x0000105c
2487#define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
2488#define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
2489
1384#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080 2490#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
1385#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2491#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
1386#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2492#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
1387#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2493#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
2494#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
2495#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15)
1388 2496
1389#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084 2497#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
1390#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088 2498#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
@@ -1394,6 +2502,26 @@ struct l2_fhdr {
1394#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098 2502#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
1395#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2503#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
1396#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2504#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
2505#define BNX2_CTX_CHNL_LOCK_STATUS_9 0x000010a4
2506
2507#define BNX2_CTX_CACHE_DATA 0x000010c4
2508#define BNX2_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
2509#define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
2510#define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
2511#define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
2512
2513#define BNX2_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
2514#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
2515#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
2516
2517#define BNX2_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
2518#define BNX2_CTX_CAM_CTRL 0x000010d4
2519#define BNX2_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0)
2520#define BNX2_CTX_CAM_CTRL_RESET (1L<<27)
2521#define BNX2_CTX_CAM_CTRL_INVALIDATE (1L<<28)
2522#define BNX2_CTX_CAM_CTRL_SEARCH (1L<<29)
2523#define BNX2_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
2524#define BNX2_CTX_CAM_CTRL_READ_REQ (1L<<31)
1397 2525
1398 2526
1399/* 2527/*
@@ -1407,14 +2535,16 @@ struct l2_fhdr {
1407#define BNX2_EMAC_MODE_PORT_NONE (0L<<2) 2535#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
1408#define BNX2_EMAC_MODE_PORT_MII (1L<<2) 2536#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
1409#define BNX2_EMAC_MODE_PORT_GMII (2L<<2) 2537#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
1410#define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2) 2538#define BNX2_EMAC_MODE_PORT_MII_10M (3L<<2)
1411#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4) 2539#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
1412#define BNX2_EMAC_MODE_25G (1L<<5) 2540#define BNX2_EMAC_MODE_25G_MODE (1L<<5)
1413#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2541#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
1414#define BNX2_EMAC_MODE_TX_BURST (1L<<8) 2542#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
1415#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2543#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
1416#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10) 2544#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
1417#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11) 2545#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
2546#define BNX2_EMAC_MODE_SERDES_MODE (1L<<12)
2547#define BNX2_EMAC_MODE_BOND_OVRD (1L<<13)
1418#define BNX2_EMAC_MODE_MPKT (1L<<18) 2548#define BNX2_EMAC_MODE_MPKT (1L<<18)
1419#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19) 2549#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
1420#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20) 2550#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
@@ -1422,6 +2552,11 @@ struct l2_fhdr {
1422#define BNX2_EMAC_STATUS 0x00001404 2552#define BNX2_EMAC_STATUS 0x00001404
1423#define BNX2_EMAC_STATUS_LINK (1L<<11) 2553#define BNX2_EMAC_STATUS_LINK (1L<<11)
1424#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12) 2554#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
2555#define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13)
2556#define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14)
2557#define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16)
2558#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17)
2559#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
1425#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) 2560#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
1426#define BNX2_EMAC_STATUS_MI_INT (1L<<23) 2561#define BNX2_EMAC_STATUS_MI_INT (1L<<23)
1427#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24) 2562#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
@@ -1429,6 +2564,9 @@ struct l2_fhdr {
1429 2564
1430#define BNX2_EMAC_ATTENTION_ENA 0x00001408 2565#define BNX2_EMAC_ATTENTION_ENA 0x00001408
1431#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) 2566#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
2567#define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14)
2568#define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16)
2569#define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
1432#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2570#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
1433#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2571#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
1434#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2572#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
@@ -1445,6 +2583,13 @@ struct l2_fhdr {
1445#define BNX2_EMAC_LED_100MB (1L<<8) 2583#define BNX2_EMAC_LED_100MB (1L<<8)
1446#define BNX2_EMAC_LED_10MB (1L<<9) 2584#define BNX2_EMAC_LED_10MB (1L<<9)
1447#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) 2585#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
2586#define BNX2_EMAC_LED_2500MB (1L<<11)
2587#define BNX2_EMAC_LED_2500MB_OVERRIDE (1L<<12)
2588#define BNX2_EMAC_LED_ACTIVITY_SEL (0x3L<<17)
2589#define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
2590#define BNX2_EMAC_LED_ACTIVITY_SEL_1 (1L<<17)
2591#define BNX2_EMAC_LED_ACTIVITY_SEL_2 (2L<<17)
2592#define BNX2_EMAC_LED_ACTIVITY_SEL_3 (3L<<17)
1448#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) 2593#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
1449#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2594#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
1450 2595
@@ -1515,9 +2660,15 @@ struct l2_fhdr {
1515#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2660#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
1516#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2661#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
1517#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2662#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2663#define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
1518#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2664#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
1519#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2665#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
2666#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1L<<26)
2667#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1L<<26)
2668#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI (2L<<26)
2669#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2L<<26)
1520#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2670#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
2671#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
1521#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28) 2672#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
1522#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2673#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
1523#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30) 2674#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
@@ -1534,13 +2685,17 @@ struct l2_fhdr {
1534#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2685#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
1535#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11) 2686#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
1536#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12) 2687#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
2688#define BNX2_EMAC_MDIO_MODE_EXT_MDINT (1L<<13)
1537#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2689#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
2690#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fL<<16)
2691#define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI (1L<<31)
1538 2692
1539#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8 2693#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
1540#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2694#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
1541 2695
1542#define BNX2_EMAC_TX_MODE 0x000014bc 2696#define BNX2_EMAC_TX_MODE 0x000014bc
1543#define BNX2_EMAC_TX_MODE_RESET (1L<<0) 2697#define BNX2_EMAC_TX_MODE_RESET (1L<<0)
2698#define BNX2_EMAC_TX_MODE_CS16_TEST (1L<<2)
1544#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2699#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1545#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4) 2700#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
1546#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2701#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
@@ -1553,6 +2708,7 @@ struct l2_fhdr {
1553#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2) 2708#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
1554#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3) 2709#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
1555#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2710#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
2711#define BNX2_EMAC_TX_STATUS_CS16_ERROR (1L<<5)
1556 2712
1557#define BNX2_EMAC_TX_LENGTHS 0x000014c4 2713#define BNX2_EMAC_TX_LENGTHS 0x000014c4
1558#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2714#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
@@ -1586,6 +2742,10 @@ struct l2_fhdr {
1586#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4 2742#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
1587#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8 2743#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
1588#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec 2744#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
2745#define BNX2_EMAC_CKSUM_ERROR_STATUS 0x000014f0
2746#define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
2747#define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
2748
1589#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2749#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
1590#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2750#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
1591#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2751#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
@@ -1608,7 +2768,7 @@ struct l2_fhdr {
1608#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2768#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
1609#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2769#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
1610#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2770#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
1611#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2771#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001558
1612#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c 2772#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
1613#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560 2773#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
1614#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2774#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
@@ -1661,9 +2821,9 @@ struct l2_fhdr {
1661#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2821#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
1662#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2822#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
1663#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2823#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
1664#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
1665#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2824#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
1666#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2825#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
2826#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
1667#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2827#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
1668#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2828#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
1669#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2829#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
@@ -1701,7 +2861,7 @@ struct l2_fhdr {
1701#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2861#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
1702#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2862#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
1703#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2863#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
1704#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2864#define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26)
1705#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2865#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
1706#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28) 2866#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
1707 2867
@@ -1733,6 +2893,7 @@ struct l2_fhdr {
1733#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2893#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
1734#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2894#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
1735 2895
2896#define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS 0x00001574
1736#define BNX2_EMAC_RX_STAT_AC0 0x00001580 2897#define BNX2_EMAC_RX_STAT_AC0 0x00001580
1737#define BNX2_EMAC_RX_STAT_AC1 0x00001584 2898#define BNX2_EMAC_RX_STAT_AC1 0x00001584
1738#define BNX2_EMAC_RX_STAT_AC2 0x00001588 2899#define BNX2_EMAC_RX_STAT_AC2 0x00001588
@@ -1757,6 +2918,7 @@ struct l2_fhdr {
1757#define BNX2_EMAC_RX_STAT_AC21 0x000015d4 2918#define BNX2_EMAC_RX_STAT_AC21 0x000015d4
1758#define BNX2_EMAC_RX_STAT_AC22 0x000015d8 2919#define BNX2_EMAC_RX_STAT_AC22 0x000015d8
1759#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2920#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
2921#define BNX2_EMAC_RX_STAT_AC_28 0x000015f4
1760#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2922#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
1761#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2923#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
1762#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2924#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
@@ -1777,7 +2939,7 @@ struct l2_fhdr {
1777#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2939#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
1778#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2940#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
1779#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2941#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
1780#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2942#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001650
1781#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2943#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
1782#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658 2944#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
1783#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c 2945#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
@@ -1843,16 +3005,16 @@ struct l2_fhdr {
1843#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 3005#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
1844#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 3006#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
1845#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 3007#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
3008#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
3009#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
1846#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 3010#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
1847#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 3011#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
1848#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
1849#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
1850#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
1851#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
1852#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
1853#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 3012#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
1854#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 3013#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
3014#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
3015#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
1855#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 3016#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
3017#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
1856#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 3018#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
1857#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 3019#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
1858#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 3020#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
@@ -1887,8 +3049,11 @@ struct l2_fhdr {
1887#define BNX2_EMAC_TX_STAT_AC18 0x000016c8 3049#define BNX2_EMAC_TX_STAT_AC18 0x000016c8
1888#define BNX2_EMAC_TX_STAT_AC19 0x000016cc 3050#define BNX2_EMAC_TX_STAT_AC19 0x000016cc
1889#define BNX2_EMAC_TX_STAT_AC20 0x000016d0 3051#define BNX2_EMAC_TX_STAT_AC20 0x000016d0
1890#define BNX2_EMAC_TX_STAT_AC21 0x000016d4
1891#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 3052#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
3053#define BNX2_EMAC_TX_RATE_LIMIT_CTRL 0x000016fc
3054#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0)
3055#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16)
3056#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31)
1892 3057
1893 3058
1894/* 3059/*
@@ -1909,8 +3074,15 @@ struct l2_fhdr {
1909#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2) 3074#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
1910#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3) 3075#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
1911#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 3076#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
3077#define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT (1L<<30)
1912#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31) 3078#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
1913 3079
3080#define BNX2_RPM_MGMT_PKT_CTRL 0x0000180c
3081#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT (0xfL<<0)
3082#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE (0xfL<<4)
3083#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30)
3084#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31)
3085
1914#define BNX2_RPM_VLAN_MATCH0 0x00001810 3086#define BNX2_RPM_VLAN_MATCH0 0x00001810
1915#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 3087#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
1916 3088
@@ -1931,6 +3103,7 @@ struct l2_fhdr {
1931#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19) 3103#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
1932#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 3104#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
1933#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24) 3105#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
3106#define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH (1L<<25)
1934#define BNX2_RPM_SORT_USER0_ENA (1L<<31) 3107#define BNX2_RPM_SORT_USER0_ENA (1L<<31)
1935 3108
1936#define BNX2_RPM_SORT_USER1 0x00001824 3109#define BNX2_RPM_SORT_USER1 0x00001824
@@ -1968,11 +3141,187 @@ struct l2_fhdr {
1968#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848 3141#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
1969#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c 3142#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
1970#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 3143#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
3144#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0 0x00001854
3145#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffL<<0)
3146#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffL<<16)
3147#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1L<<30)
3148#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1L<<31)
3149
3150#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1 0x00001858
3151#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffL<<0)
3152#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffL<<16)
3153#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1L<<30)
3154#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1L<<31)
3155
3156#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2 0x0000185c
3157#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffL<<0)
3158#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffL<<16)
3159#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1L<<30)
3160#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1L<<31)
3161
3162#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3 0x00001860
3163#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffL<<0)
3164#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffL<<16)
3165#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1L<<30)
3166#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1L<<31)
3167
3168#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4 0x00001864
3169#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffL<<0)
3170#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffL<<16)
3171#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1L<<30)
3172#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1L<<31)
3173
3174#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5 0x00001868
3175#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffL<<0)
3176#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffL<<16)
3177#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1L<<30)
3178#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1L<<31)
3179
3180#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6 0x0000186c
3181#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffL<<0)
3182#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffL<<16)
3183#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1L<<30)
3184#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1L<<31)
3185
3186#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7 0x00001870
3187#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffL<<0)
3188#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffL<<16)
3189#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1L<<30)
3190#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1L<<31)
3191
1971#define BNX2_RPM_STAT_AC0 0x00001880 3192#define BNX2_RPM_STAT_AC0 0x00001880
1972#define BNX2_RPM_STAT_AC1 0x00001884 3193#define BNX2_RPM_STAT_AC1 0x00001884
1973#define BNX2_RPM_STAT_AC2 0x00001888 3194#define BNX2_RPM_STAT_AC2 0x00001888
1974#define BNX2_RPM_STAT_AC3 0x0000188c 3195#define BNX2_RPM_STAT_AC3 0x0000188c
1975#define BNX2_RPM_STAT_AC4 0x00001890 3196#define BNX2_RPM_STAT_AC4 0x00001890
3197#define BNX2_RPM_RC_CNTL_16 0x000018e0
3198#define BNX2_RPM_RC_CNTL_16_OFFSET (0xffL<<0)
3199#define BNX2_RPM_RC_CNTL_16_CLASS (0x7L<<8)
3200#define BNX2_RPM_RC_CNTL_16_PRIORITY (1L<<11)
3201#define BNX2_RPM_RC_CNTL_16_P4 (1L<<12)
3202#define BNX2_RPM_RC_CNTL_16_HDR_TYPE (0x7L<<13)
3203#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START (0L<<13)
3204#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP (1L<<13)
3205#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP (2L<<13)
3206#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP (3L<<13)
3207#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA (4L<<13)
3208#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP (5L<<13)
3209#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 (6L<<13)
3210#define BNX2_RPM_RC_CNTL_16_COMP (0x3L<<16)
3211#define BNX2_RPM_RC_CNTL_16_COMP_EQUAL (0L<<16)
3212#define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL (1L<<16)
3213#define BNX2_RPM_RC_CNTL_16_COMP_GREATER (2L<<16)
3214#define BNX2_RPM_RC_CNTL_16_COMP_LESS (3L<<16)
3215#define BNX2_RPM_RC_CNTL_16_MAP (1L<<18)
3216#define BNX2_RPM_RC_CNTL_16_SBIT (1L<<19)
3217#define BNX2_RPM_RC_CNTL_16_CMDSEL (0x1fL<<20)
3218#define BNX2_RPM_RC_CNTL_16_DISCARD (1L<<25)
3219#define BNX2_RPM_RC_CNTL_16_MASK (1L<<26)
3220#define BNX2_RPM_RC_CNTL_16_P1 (1L<<27)
3221#define BNX2_RPM_RC_CNTL_16_P2 (1L<<28)
3222#define BNX2_RPM_RC_CNTL_16_P3 (1L<<29)
3223#define BNX2_RPM_RC_CNTL_16_NBIT (1L<<30)
3224
3225#define BNX2_RPM_RC_VALUE_MASK_16 0x000018e4
3226#define BNX2_RPM_RC_VALUE_MASK_16_VALUE (0xffffL<<0)
3227#define BNX2_RPM_RC_VALUE_MASK_16_MASK (0xffffL<<16)
3228
3229#define BNX2_RPM_RC_CNTL_17 0x000018e8
3230#define BNX2_RPM_RC_CNTL_17_OFFSET (0xffL<<0)
3231#define BNX2_RPM_RC_CNTL_17_CLASS (0x7L<<8)
3232#define BNX2_RPM_RC_CNTL_17_PRIORITY (1L<<11)
3233#define BNX2_RPM_RC_CNTL_17_P4 (1L<<12)
3234#define BNX2_RPM_RC_CNTL_17_HDR_TYPE (0x7L<<13)
3235#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START (0L<<13)
3236#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP (1L<<13)
3237#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP (2L<<13)
3238#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP (3L<<13)
3239#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA (4L<<13)
3240#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP (5L<<13)
3241#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 (6L<<13)
3242#define BNX2_RPM_RC_CNTL_17_COMP (0x3L<<16)
3243#define BNX2_RPM_RC_CNTL_17_COMP_EQUAL (0L<<16)
3244#define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL (1L<<16)
3245#define BNX2_RPM_RC_CNTL_17_COMP_GREATER (2L<<16)
3246#define BNX2_RPM_RC_CNTL_17_COMP_LESS (3L<<16)
3247#define BNX2_RPM_RC_CNTL_17_MAP (1L<<18)
3248#define BNX2_RPM_RC_CNTL_17_SBIT (1L<<19)
3249#define BNX2_RPM_RC_CNTL_17_CMDSEL (0x1fL<<20)
3250#define BNX2_RPM_RC_CNTL_17_DISCARD (1L<<25)
3251#define BNX2_RPM_RC_CNTL_17_MASK (1L<<26)
3252#define BNX2_RPM_RC_CNTL_17_P1 (1L<<27)
3253#define BNX2_RPM_RC_CNTL_17_P2 (1L<<28)
3254#define BNX2_RPM_RC_CNTL_17_P3 (1L<<29)
3255#define BNX2_RPM_RC_CNTL_17_NBIT (1L<<30)
3256
3257#define BNX2_RPM_RC_VALUE_MASK_17 0x000018ec
3258#define BNX2_RPM_RC_VALUE_MASK_17_VALUE (0xffffL<<0)
3259#define BNX2_RPM_RC_VALUE_MASK_17_MASK (0xffffL<<16)
3260
3261#define BNX2_RPM_RC_CNTL_18 0x000018f0
3262#define BNX2_RPM_RC_CNTL_18_OFFSET (0xffL<<0)
3263#define BNX2_RPM_RC_CNTL_18_CLASS (0x7L<<8)
3264#define BNX2_RPM_RC_CNTL_18_PRIORITY (1L<<11)
3265#define BNX2_RPM_RC_CNTL_18_P4 (1L<<12)
3266#define BNX2_RPM_RC_CNTL_18_HDR_TYPE (0x7L<<13)
3267#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START (0L<<13)
3268#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP (1L<<13)
3269#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP (2L<<13)
3270#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP (3L<<13)
3271#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA (4L<<13)
3272#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP (5L<<13)
3273#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 (6L<<13)
3274#define BNX2_RPM_RC_CNTL_18_COMP (0x3L<<16)
3275#define BNX2_RPM_RC_CNTL_18_COMP_EQUAL (0L<<16)
3276#define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL (1L<<16)
3277#define BNX2_RPM_RC_CNTL_18_COMP_GREATER (2L<<16)
3278#define BNX2_RPM_RC_CNTL_18_COMP_LESS (3L<<16)
3279#define BNX2_RPM_RC_CNTL_18_MAP (1L<<18)
3280#define BNX2_RPM_RC_CNTL_18_SBIT (1L<<19)
3281#define BNX2_RPM_RC_CNTL_18_CMDSEL (0x1fL<<20)
3282#define BNX2_RPM_RC_CNTL_18_DISCARD (1L<<25)
3283#define BNX2_RPM_RC_CNTL_18_MASK (1L<<26)
3284#define BNX2_RPM_RC_CNTL_18_P1 (1L<<27)
3285#define BNX2_RPM_RC_CNTL_18_P2 (1L<<28)
3286#define BNX2_RPM_RC_CNTL_18_P3 (1L<<29)
3287#define BNX2_RPM_RC_CNTL_18_NBIT (1L<<30)
3288
3289#define BNX2_RPM_RC_VALUE_MASK_18 0x000018f4
3290#define BNX2_RPM_RC_VALUE_MASK_18_VALUE (0xffffL<<0)
3291#define BNX2_RPM_RC_VALUE_MASK_18_MASK (0xffffL<<16)
3292
3293#define BNX2_RPM_RC_CNTL_19 0x000018f8
3294#define BNX2_RPM_RC_CNTL_19_OFFSET (0xffL<<0)
3295#define BNX2_RPM_RC_CNTL_19_CLASS (0x7L<<8)
3296#define BNX2_RPM_RC_CNTL_19_PRIORITY (1L<<11)
3297#define BNX2_RPM_RC_CNTL_19_P4 (1L<<12)
3298#define BNX2_RPM_RC_CNTL_19_HDR_TYPE (0x7L<<13)
3299#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START (0L<<13)
3300#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP (1L<<13)
3301#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP (2L<<13)
3302#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP (3L<<13)
3303#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA (4L<<13)
3304#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP (5L<<13)
3305#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 (6L<<13)
3306#define BNX2_RPM_RC_CNTL_19_COMP (0x3L<<16)
3307#define BNX2_RPM_RC_CNTL_19_COMP_EQUAL (0L<<16)
3308#define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL (1L<<16)
3309#define BNX2_RPM_RC_CNTL_19_COMP_GREATER (2L<<16)
3310#define BNX2_RPM_RC_CNTL_19_COMP_LESS (3L<<16)
3311#define BNX2_RPM_RC_CNTL_19_MAP (1L<<18)
3312#define BNX2_RPM_RC_CNTL_19_SBIT (1L<<19)
3313#define BNX2_RPM_RC_CNTL_19_CMDSEL (0x1fL<<20)
3314#define BNX2_RPM_RC_CNTL_19_DISCARD (1L<<25)
3315#define BNX2_RPM_RC_CNTL_19_MASK (1L<<26)
3316#define BNX2_RPM_RC_CNTL_19_P1 (1L<<27)
3317#define BNX2_RPM_RC_CNTL_19_P2 (1L<<28)
3318#define BNX2_RPM_RC_CNTL_19_P3 (1L<<29)
3319#define BNX2_RPM_RC_CNTL_19_NBIT (1L<<30)
3320
3321#define BNX2_RPM_RC_VALUE_MASK_19 0x000018fc
3322#define BNX2_RPM_RC_VALUE_MASK_19_VALUE (0xffffL<<0)
3323#define BNX2_RPM_RC_VALUE_MASK_19_MASK (0xffffL<<16)
3324
1976#define BNX2_RPM_RC_CNTL_0 0x00001900 3325#define BNX2_RPM_RC_CNTL_0 0x00001900
1977#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 3326#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
1978#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8) 3327#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
@@ -1984,14 +3333,18 @@ struct l2_fhdr {
1984#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 3333#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
1985#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 3334#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
1986#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 3335#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
3336#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP (5L<<13)
3337#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 (6L<<13)
1987#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16) 3338#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
1988#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 3339#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
1989#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 3340#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
1990#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 3341#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
1991#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 3342#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
3343#define BNX2_RPM_RC_CNTL_0_MAP_XI (1L<<18)
1992#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19) 3344#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
1993#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 3345#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
1994#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24) 3346#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
3347#define BNX2_RPM_RC_CNTL_0_CMDSEL_XI (0x1fL<<20)
1995#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25) 3348#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
1996#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26) 3349#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
1997#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27) 3350#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
@@ -2006,81 +3359,518 @@ struct l2_fhdr {
2006#define BNX2_RPM_RC_CNTL_1 0x00001908 3359#define BNX2_RPM_RC_CNTL_1 0x00001908
2007#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0) 3360#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2008#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19) 3361#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
3362#define BNX2_RPM_RC_CNTL_1_OFFSET_XI (0xffL<<0)
3363#define BNX2_RPM_RC_CNTL_1_CLASS_XI (0x7L<<8)
3364#define BNX2_RPM_RC_CNTL_1_PRIORITY_XI (1L<<11)
3365#define BNX2_RPM_RC_CNTL_1_P4_XI (1L<<12)
3366#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI (0x7L<<13)
3367#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI (0L<<13)
3368#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI (1L<<13)
3369#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI (2L<<13)
3370#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI (3L<<13)
3371#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI (4L<<13)
3372#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI (5L<<13)
3373#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI (6L<<13)
3374#define BNX2_RPM_RC_CNTL_1_COMP_XI (0x3L<<16)
3375#define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI (0L<<16)
3376#define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI (1L<<16)
3377#define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI (2L<<16)
3378#define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI (3L<<16)
3379#define BNX2_RPM_RC_CNTL_1_MAP_XI (1L<<18)
3380#define BNX2_RPM_RC_CNTL_1_SBIT_XI (1L<<19)
3381#define BNX2_RPM_RC_CNTL_1_CMDSEL_XI (0x1fL<<20)
3382#define BNX2_RPM_RC_CNTL_1_DISCARD_XI (1L<<25)
3383#define BNX2_RPM_RC_CNTL_1_MASK_XI (1L<<26)
3384#define BNX2_RPM_RC_CNTL_1_P1_XI (1L<<27)
3385#define BNX2_RPM_RC_CNTL_1_P2_XI (1L<<28)
3386#define BNX2_RPM_RC_CNTL_1_P3_XI (1L<<29)
3387#define BNX2_RPM_RC_CNTL_1_NBIT_XI (1L<<30)
2009 3388
2010#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c 3389#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
3390#define BNX2_RPM_RC_VALUE_MASK_1_VALUE (0xffffL<<0)
3391#define BNX2_RPM_RC_VALUE_MASK_1_MASK (0xffffL<<16)
3392
2011#define BNX2_RPM_RC_CNTL_2 0x00001910 3393#define BNX2_RPM_RC_CNTL_2 0x00001910
2012#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0) 3394#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2013#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19) 3395#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
3396#define BNX2_RPM_RC_CNTL_2_OFFSET_XI (0xffL<<0)
3397#define BNX2_RPM_RC_CNTL_2_CLASS_XI (0x7L<<8)
3398#define BNX2_RPM_RC_CNTL_2_PRIORITY_XI (1L<<11)
3399#define BNX2_RPM_RC_CNTL_2_P4_XI (1L<<12)
3400#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI (0x7L<<13)
3401#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI (0L<<13)
3402#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI (1L<<13)
3403#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI (2L<<13)
3404#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI (3L<<13)
3405#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI (4L<<13)
3406#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI (5L<<13)
3407#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI (6L<<13)
3408#define BNX2_RPM_RC_CNTL_2_COMP_XI (0x3L<<16)
3409#define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI (0L<<16)
3410#define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI (1L<<16)
3411#define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI (2L<<16)
3412#define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI (3L<<16)
3413#define BNX2_RPM_RC_CNTL_2_MAP_XI (1L<<18)
3414#define BNX2_RPM_RC_CNTL_2_SBIT_XI (1L<<19)
3415#define BNX2_RPM_RC_CNTL_2_CMDSEL_XI (0x1fL<<20)
3416#define BNX2_RPM_RC_CNTL_2_DISCARD_XI (1L<<25)
3417#define BNX2_RPM_RC_CNTL_2_MASK_XI (1L<<26)
3418#define BNX2_RPM_RC_CNTL_2_P1_XI (1L<<27)
3419#define BNX2_RPM_RC_CNTL_2_P2_XI (1L<<28)
3420#define BNX2_RPM_RC_CNTL_2_P3_XI (1L<<29)
3421#define BNX2_RPM_RC_CNTL_2_NBIT_XI (1L<<30)
2014 3422
2015#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914 3423#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
3424#define BNX2_RPM_RC_VALUE_MASK_2_VALUE (0xffffL<<0)
3425#define BNX2_RPM_RC_VALUE_MASK_2_MASK (0xffffL<<16)
3426
2016#define BNX2_RPM_RC_CNTL_3 0x00001918 3427#define BNX2_RPM_RC_CNTL_3 0x00001918
2017#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0) 3428#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2018#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19) 3429#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
3430#define BNX2_RPM_RC_CNTL_3_OFFSET_XI (0xffL<<0)
3431#define BNX2_RPM_RC_CNTL_3_CLASS_XI (0x7L<<8)
3432#define BNX2_RPM_RC_CNTL_3_PRIORITY_XI (1L<<11)
3433#define BNX2_RPM_RC_CNTL_3_P4_XI (1L<<12)
3434#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI (0x7L<<13)
3435#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI (0L<<13)
3436#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI (1L<<13)
3437#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI (2L<<13)
3438#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI (3L<<13)
3439#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI (4L<<13)
3440#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI (5L<<13)
3441#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI (6L<<13)
3442#define BNX2_RPM_RC_CNTL_3_COMP_XI (0x3L<<16)
3443#define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI (0L<<16)
3444#define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI (1L<<16)
3445#define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI (2L<<16)
3446#define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI (3L<<16)
3447#define BNX2_RPM_RC_CNTL_3_MAP_XI (1L<<18)
3448#define BNX2_RPM_RC_CNTL_3_SBIT_XI (1L<<19)
3449#define BNX2_RPM_RC_CNTL_3_CMDSEL_XI (0x1fL<<20)
3450#define BNX2_RPM_RC_CNTL_3_DISCARD_XI (1L<<25)
3451#define BNX2_RPM_RC_CNTL_3_MASK_XI (1L<<26)
3452#define BNX2_RPM_RC_CNTL_3_P1_XI (1L<<27)
3453#define BNX2_RPM_RC_CNTL_3_P2_XI (1L<<28)
3454#define BNX2_RPM_RC_CNTL_3_P3_XI (1L<<29)
3455#define BNX2_RPM_RC_CNTL_3_NBIT_XI (1L<<30)
2019 3456
2020#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c 3457#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
3458#define BNX2_RPM_RC_VALUE_MASK_3_VALUE (0xffffL<<0)
3459#define BNX2_RPM_RC_VALUE_MASK_3_MASK (0xffffL<<16)
3460
2021#define BNX2_RPM_RC_CNTL_4 0x00001920 3461#define BNX2_RPM_RC_CNTL_4 0x00001920
2022#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0) 3462#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2023#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19) 3463#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
3464#define BNX2_RPM_RC_CNTL_4_OFFSET_XI (0xffL<<0)
3465#define BNX2_RPM_RC_CNTL_4_CLASS_XI (0x7L<<8)
3466#define BNX2_RPM_RC_CNTL_4_PRIORITY_XI (1L<<11)
3467#define BNX2_RPM_RC_CNTL_4_P4_XI (1L<<12)
3468#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI (0x7L<<13)
3469#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI (0L<<13)
3470#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI (1L<<13)
3471#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI (2L<<13)
3472#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI (3L<<13)
3473#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI (4L<<13)
3474#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI (5L<<13)
3475#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI (6L<<13)
3476#define BNX2_RPM_RC_CNTL_4_COMP_XI (0x3L<<16)
3477#define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI (0L<<16)
3478#define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI (1L<<16)
3479#define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI (2L<<16)
3480#define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI (3L<<16)
3481#define BNX2_RPM_RC_CNTL_4_MAP_XI (1L<<18)
3482#define BNX2_RPM_RC_CNTL_4_SBIT_XI (1L<<19)
3483#define BNX2_RPM_RC_CNTL_4_CMDSEL_XI (0x1fL<<20)
3484#define BNX2_RPM_RC_CNTL_4_DISCARD_XI (1L<<25)
3485#define BNX2_RPM_RC_CNTL_4_MASK_XI (1L<<26)
3486#define BNX2_RPM_RC_CNTL_4_P1_XI (1L<<27)
3487#define BNX2_RPM_RC_CNTL_4_P2_XI (1L<<28)
3488#define BNX2_RPM_RC_CNTL_4_P3_XI (1L<<29)
3489#define BNX2_RPM_RC_CNTL_4_NBIT_XI (1L<<30)
2024 3490
2025#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924 3491#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
3492#define BNX2_RPM_RC_VALUE_MASK_4_VALUE (0xffffL<<0)
3493#define BNX2_RPM_RC_VALUE_MASK_4_MASK (0xffffL<<16)
3494
2026#define BNX2_RPM_RC_CNTL_5 0x00001928 3495#define BNX2_RPM_RC_CNTL_5 0x00001928
2027#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0) 3496#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2028#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19) 3497#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
3498#define BNX2_RPM_RC_CNTL_5_OFFSET_XI (0xffL<<0)
3499#define BNX2_RPM_RC_CNTL_5_CLASS_XI (0x7L<<8)
3500#define BNX2_RPM_RC_CNTL_5_PRIORITY_XI (1L<<11)
3501#define BNX2_RPM_RC_CNTL_5_P4_XI (1L<<12)
3502#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI (0x7L<<13)
3503#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI (0L<<13)
3504#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI (1L<<13)
3505#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI (2L<<13)
3506#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI (3L<<13)
3507#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI (4L<<13)
3508#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI (5L<<13)
3509#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI (6L<<13)
3510#define BNX2_RPM_RC_CNTL_5_COMP_XI (0x3L<<16)
3511#define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI (0L<<16)
3512#define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI (1L<<16)
3513#define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI (2L<<16)
3514#define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI (3L<<16)
3515#define BNX2_RPM_RC_CNTL_5_MAP_XI (1L<<18)
3516#define BNX2_RPM_RC_CNTL_5_SBIT_XI (1L<<19)
3517#define BNX2_RPM_RC_CNTL_5_CMDSEL_XI (0x1fL<<20)
3518#define BNX2_RPM_RC_CNTL_5_DISCARD_XI (1L<<25)
3519#define BNX2_RPM_RC_CNTL_5_MASK_XI (1L<<26)
3520#define BNX2_RPM_RC_CNTL_5_P1_XI (1L<<27)
3521#define BNX2_RPM_RC_CNTL_5_P2_XI (1L<<28)
3522#define BNX2_RPM_RC_CNTL_5_P3_XI (1L<<29)
3523#define BNX2_RPM_RC_CNTL_5_NBIT_XI (1L<<30)
2029 3524
2030#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c 3525#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
3526#define BNX2_RPM_RC_VALUE_MASK_5_VALUE (0xffffL<<0)
3527#define BNX2_RPM_RC_VALUE_MASK_5_MASK (0xffffL<<16)
3528
2031#define BNX2_RPM_RC_CNTL_6 0x00001930 3529#define BNX2_RPM_RC_CNTL_6 0x00001930
2032#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0) 3530#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2033#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19) 3531#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
3532#define BNX2_RPM_RC_CNTL_6_OFFSET_XI (0xffL<<0)
3533#define BNX2_RPM_RC_CNTL_6_CLASS_XI (0x7L<<8)
3534#define BNX2_RPM_RC_CNTL_6_PRIORITY_XI (1L<<11)
3535#define BNX2_RPM_RC_CNTL_6_P4_XI (1L<<12)
3536#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI (0x7L<<13)
3537#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI (0L<<13)
3538#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI (1L<<13)
3539#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI (2L<<13)
3540#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI (3L<<13)
3541#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI (4L<<13)
3542#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI (5L<<13)
3543#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI (6L<<13)
3544#define BNX2_RPM_RC_CNTL_6_COMP_XI (0x3L<<16)
3545#define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI (0L<<16)
3546#define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI (1L<<16)
3547#define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI (2L<<16)
3548#define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI (3L<<16)
3549#define BNX2_RPM_RC_CNTL_6_MAP_XI (1L<<18)
3550#define BNX2_RPM_RC_CNTL_6_SBIT_XI (1L<<19)
3551#define BNX2_RPM_RC_CNTL_6_CMDSEL_XI (0x1fL<<20)
3552#define BNX2_RPM_RC_CNTL_6_DISCARD_XI (1L<<25)
3553#define BNX2_RPM_RC_CNTL_6_MASK_XI (1L<<26)
3554#define BNX2_RPM_RC_CNTL_6_P1_XI (1L<<27)
3555#define BNX2_RPM_RC_CNTL_6_P2_XI (1L<<28)
3556#define BNX2_RPM_RC_CNTL_6_P3_XI (1L<<29)
3557#define BNX2_RPM_RC_CNTL_6_NBIT_XI (1L<<30)
2034 3558
2035#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934 3559#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
3560#define BNX2_RPM_RC_VALUE_MASK_6_VALUE (0xffffL<<0)
3561#define BNX2_RPM_RC_VALUE_MASK_6_MASK (0xffffL<<16)
3562
2036#define BNX2_RPM_RC_CNTL_7 0x00001938 3563#define BNX2_RPM_RC_CNTL_7 0x00001938
2037#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0) 3564#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2038#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19) 3565#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
3566#define BNX2_RPM_RC_CNTL_7_OFFSET_XI (0xffL<<0)
3567#define BNX2_RPM_RC_CNTL_7_CLASS_XI (0x7L<<8)
3568#define BNX2_RPM_RC_CNTL_7_PRIORITY_XI (1L<<11)
3569#define BNX2_RPM_RC_CNTL_7_P4_XI (1L<<12)
3570#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI (0x7L<<13)
3571#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI (0L<<13)
3572#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI (1L<<13)
3573#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI (2L<<13)
3574#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI (3L<<13)
3575#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI (4L<<13)
3576#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI (5L<<13)
3577#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI (6L<<13)
3578#define BNX2_RPM_RC_CNTL_7_COMP_XI (0x3L<<16)
3579#define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI (0L<<16)
3580#define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI (1L<<16)
3581#define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI (2L<<16)
3582#define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI (3L<<16)
3583#define BNX2_RPM_RC_CNTL_7_MAP_XI (1L<<18)
3584#define BNX2_RPM_RC_CNTL_7_SBIT_XI (1L<<19)
3585#define BNX2_RPM_RC_CNTL_7_CMDSEL_XI (0x1fL<<20)
3586#define BNX2_RPM_RC_CNTL_7_DISCARD_XI (1L<<25)
3587#define BNX2_RPM_RC_CNTL_7_MASK_XI (1L<<26)
3588#define BNX2_RPM_RC_CNTL_7_P1_XI (1L<<27)
3589#define BNX2_RPM_RC_CNTL_7_P2_XI (1L<<28)
3590#define BNX2_RPM_RC_CNTL_7_P3_XI (1L<<29)
3591#define BNX2_RPM_RC_CNTL_7_NBIT_XI (1L<<30)
2039 3592
2040#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c 3593#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
3594#define BNX2_RPM_RC_VALUE_MASK_7_VALUE (0xffffL<<0)
3595#define BNX2_RPM_RC_VALUE_MASK_7_MASK (0xffffL<<16)
3596
2041#define BNX2_RPM_RC_CNTL_8 0x00001940 3597#define BNX2_RPM_RC_CNTL_8 0x00001940
2042#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0) 3598#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2043#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19) 3599#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
3600#define BNX2_RPM_RC_CNTL_8_OFFSET_XI (0xffL<<0)
3601#define BNX2_RPM_RC_CNTL_8_CLASS_XI (0x7L<<8)
3602#define BNX2_RPM_RC_CNTL_8_PRIORITY_XI (1L<<11)
3603#define BNX2_RPM_RC_CNTL_8_P4_XI (1L<<12)
3604#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI (0x7L<<13)
3605#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI (0L<<13)
3606#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI (1L<<13)
3607#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI (2L<<13)
3608#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI (3L<<13)
3609#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI (4L<<13)
3610#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI (5L<<13)
3611#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI (6L<<13)
3612#define BNX2_RPM_RC_CNTL_8_COMP_XI (0x3L<<16)
3613#define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI (0L<<16)
3614#define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI (1L<<16)
3615#define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI (2L<<16)
3616#define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI (3L<<16)
3617#define BNX2_RPM_RC_CNTL_8_MAP_XI (1L<<18)
3618#define BNX2_RPM_RC_CNTL_8_SBIT_XI (1L<<19)
3619#define BNX2_RPM_RC_CNTL_8_CMDSEL_XI (0x1fL<<20)
3620#define BNX2_RPM_RC_CNTL_8_DISCARD_XI (1L<<25)
3621#define BNX2_RPM_RC_CNTL_8_MASK_XI (1L<<26)
3622#define BNX2_RPM_RC_CNTL_8_P1_XI (1L<<27)
3623#define BNX2_RPM_RC_CNTL_8_P2_XI (1L<<28)
3624#define BNX2_RPM_RC_CNTL_8_P3_XI (1L<<29)
3625#define BNX2_RPM_RC_CNTL_8_NBIT_XI (1L<<30)
2044 3626
2045#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944 3627#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
3628#define BNX2_RPM_RC_VALUE_MASK_8_VALUE (0xffffL<<0)
3629#define BNX2_RPM_RC_VALUE_MASK_8_MASK (0xffffL<<16)
3630
2046#define BNX2_RPM_RC_CNTL_9 0x00001948 3631#define BNX2_RPM_RC_CNTL_9 0x00001948
2047#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0) 3632#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2048#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19) 3633#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
3634#define BNX2_RPM_RC_CNTL_9_OFFSET_XI (0xffL<<0)
3635#define BNX2_RPM_RC_CNTL_9_CLASS_XI (0x7L<<8)
3636#define BNX2_RPM_RC_CNTL_9_PRIORITY_XI (1L<<11)
3637#define BNX2_RPM_RC_CNTL_9_P4_XI (1L<<12)
3638#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI (0x7L<<13)
3639#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI (0L<<13)
3640#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI (1L<<13)
3641#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI (2L<<13)
3642#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI (3L<<13)
3643#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI (4L<<13)
3644#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI (5L<<13)
3645#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI (6L<<13)
3646#define BNX2_RPM_RC_CNTL_9_COMP_XI (0x3L<<16)
3647#define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI (0L<<16)
3648#define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI (1L<<16)
3649#define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI (2L<<16)
3650#define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI (3L<<16)
3651#define BNX2_RPM_RC_CNTL_9_MAP_XI (1L<<18)
3652#define BNX2_RPM_RC_CNTL_9_SBIT_XI (1L<<19)
3653#define BNX2_RPM_RC_CNTL_9_CMDSEL_XI (0x1fL<<20)
3654#define BNX2_RPM_RC_CNTL_9_DISCARD_XI (1L<<25)
3655#define BNX2_RPM_RC_CNTL_9_MASK_XI (1L<<26)
3656#define BNX2_RPM_RC_CNTL_9_P1_XI (1L<<27)
3657#define BNX2_RPM_RC_CNTL_9_P2_XI (1L<<28)
3658#define BNX2_RPM_RC_CNTL_9_P3_XI (1L<<29)
3659#define BNX2_RPM_RC_CNTL_9_NBIT_XI (1L<<30)
2049 3660
2050#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c 3661#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
3662#define BNX2_RPM_RC_VALUE_MASK_9_VALUE (0xffffL<<0)
3663#define BNX2_RPM_RC_VALUE_MASK_9_MASK (0xffffL<<16)
3664
2051#define BNX2_RPM_RC_CNTL_10 0x00001950 3665#define BNX2_RPM_RC_CNTL_10 0x00001950
2052#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0) 3666#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2053#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19) 3667#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
3668#define BNX2_RPM_RC_CNTL_10_OFFSET_XI (0xffL<<0)
3669#define BNX2_RPM_RC_CNTL_10_CLASS_XI (0x7L<<8)
3670#define BNX2_RPM_RC_CNTL_10_PRIORITY_XI (1L<<11)
3671#define BNX2_RPM_RC_CNTL_10_P4_XI (1L<<12)
3672#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI (0x7L<<13)
3673#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI (0L<<13)
3674#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI (1L<<13)
3675#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI (2L<<13)
3676#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI (3L<<13)
3677#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI (4L<<13)
3678#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI (5L<<13)
3679#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI (6L<<13)
3680#define BNX2_RPM_RC_CNTL_10_COMP_XI (0x3L<<16)
3681#define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI (0L<<16)
3682#define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI (1L<<16)
3683#define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI (2L<<16)
3684#define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI (3L<<16)
3685#define BNX2_RPM_RC_CNTL_10_MAP_XI (1L<<18)
3686#define BNX2_RPM_RC_CNTL_10_SBIT_XI (1L<<19)
3687#define BNX2_RPM_RC_CNTL_10_CMDSEL_XI (0x1fL<<20)
3688#define BNX2_RPM_RC_CNTL_10_DISCARD_XI (1L<<25)
3689#define BNX2_RPM_RC_CNTL_10_MASK_XI (1L<<26)
3690#define BNX2_RPM_RC_CNTL_10_P1_XI (1L<<27)
3691#define BNX2_RPM_RC_CNTL_10_P2_XI (1L<<28)
3692#define BNX2_RPM_RC_CNTL_10_P3_XI (1L<<29)
3693#define BNX2_RPM_RC_CNTL_10_NBIT_XI (1L<<30)
2054 3694
2055#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954 3695#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
3696#define BNX2_RPM_RC_VALUE_MASK_10_VALUE (0xffffL<<0)
3697#define BNX2_RPM_RC_VALUE_MASK_10_MASK (0xffffL<<16)
3698
2056#define BNX2_RPM_RC_CNTL_11 0x00001958 3699#define BNX2_RPM_RC_CNTL_11 0x00001958
2057#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0) 3700#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2058#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19) 3701#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
3702#define BNX2_RPM_RC_CNTL_11_OFFSET_XI (0xffL<<0)
3703#define BNX2_RPM_RC_CNTL_11_CLASS_XI (0x7L<<8)
3704#define BNX2_RPM_RC_CNTL_11_PRIORITY_XI (1L<<11)
3705#define BNX2_RPM_RC_CNTL_11_P4_XI (1L<<12)
3706#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI (0x7L<<13)
3707#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI (0L<<13)
3708#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI (1L<<13)
3709#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI (2L<<13)
3710#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI (3L<<13)
3711#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI (4L<<13)
3712#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI (5L<<13)
3713#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI (6L<<13)
3714#define BNX2_RPM_RC_CNTL_11_COMP_XI (0x3L<<16)
3715#define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI (0L<<16)
3716#define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI (1L<<16)
3717#define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI (2L<<16)
3718#define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI (3L<<16)
3719#define BNX2_RPM_RC_CNTL_11_MAP_XI (1L<<18)
3720#define BNX2_RPM_RC_CNTL_11_SBIT_XI (1L<<19)
3721#define BNX2_RPM_RC_CNTL_11_CMDSEL_XI (0x1fL<<20)
3722#define BNX2_RPM_RC_CNTL_11_DISCARD_XI (1L<<25)
3723#define BNX2_RPM_RC_CNTL_11_MASK_XI (1L<<26)
3724#define BNX2_RPM_RC_CNTL_11_P1_XI (1L<<27)
3725#define BNX2_RPM_RC_CNTL_11_P2_XI (1L<<28)
3726#define BNX2_RPM_RC_CNTL_11_P3_XI (1L<<29)
3727#define BNX2_RPM_RC_CNTL_11_NBIT_XI (1L<<30)
2059 3728
2060#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c 3729#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
3730#define BNX2_RPM_RC_VALUE_MASK_11_VALUE (0xffffL<<0)
3731#define BNX2_RPM_RC_VALUE_MASK_11_MASK (0xffffL<<16)
3732
2061#define BNX2_RPM_RC_CNTL_12 0x00001960 3733#define BNX2_RPM_RC_CNTL_12 0x00001960
2062#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0) 3734#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2063#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19) 3735#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
3736#define BNX2_RPM_RC_CNTL_12_OFFSET_XI (0xffL<<0)
3737#define BNX2_RPM_RC_CNTL_12_CLASS_XI (0x7L<<8)
3738#define BNX2_RPM_RC_CNTL_12_PRIORITY_XI (1L<<11)
3739#define BNX2_RPM_RC_CNTL_12_P4_XI (1L<<12)
3740#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI (0x7L<<13)
3741#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI (0L<<13)
3742#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI (1L<<13)
3743#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI (2L<<13)
3744#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI (3L<<13)
3745#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI (4L<<13)
3746#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI (5L<<13)
3747#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI (6L<<13)
3748#define BNX2_RPM_RC_CNTL_12_COMP_XI (0x3L<<16)
3749#define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI (0L<<16)
3750#define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI (1L<<16)
3751#define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI (2L<<16)
3752#define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI (3L<<16)
3753#define BNX2_RPM_RC_CNTL_12_MAP_XI (1L<<18)
3754#define BNX2_RPM_RC_CNTL_12_SBIT_XI (1L<<19)
3755#define BNX2_RPM_RC_CNTL_12_CMDSEL_XI (0x1fL<<20)
3756#define BNX2_RPM_RC_CNTL_12_DISCARD_XI (1L<<25)
3757#define BNX2_RPM_RC_CNTL_12_MASK_XI (1L<<26)
3758#define BNX2_RPM_RC_CNTL_12_P1_XI (1L<<27)
3759#define BNX2_RPM_RC_CNTL_12_P2_XI (1L<<28)
3760#define BNX2_RPM_RC_CNTL_12_P3_XI (1L<<29)
3761#define BNX2_RPM_RC_CNTL_12_NBIT_XI (1L<<30)
2064 3762
2065#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964 3763#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
3764#define BNX2_RPM_RC_VALUE_MASK_12_VALUE (0xffffL<<0)
3765#define BNX2_RPM_RC_VALUE_MASK_12_MASK (0xffffL<<16)
3766
2066#define BNX2_RPM_RC_CNTL_13 0x00001968 3767#define BNX2_RPM_RC_CNTL_13 0x00001968
2067#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0) 3768#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2068#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19) 3769#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
3770#define BNX2_RPM_RC_CNTL_13_OFFSET_XI (0xffL<<0)
3771#define BNX2_RPM_RC_CNTL_13_CLASS_XI (0x7L<<8)
3772#define BNX2_RPM_RC_CNTL_13_PRIORITY_XI (1L<<11)
3773#define BNX2_RPM_RC_CNTL_13_P4_XI (1L<<12)
3774#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI (0x7L<<13)
3775#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI (0L<<13)
3776#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI (1L<<13)
3777#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI (2L<<13)
3778#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI (3L<<13)
3779#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI (4L<<13)
3780#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI (5L<<13)
3781#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI (6L<<13)
3782#define BNX2_RPM_RC_CNTL_13_COMP_XI (0x3L<<16)
3783#define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI (0L<<16)
3784#define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI (1L<<16)
3785#define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI (2L<<16)
3786#define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI (3L<<16)
3787#define BNX2_RPM_RC_CNTL_13_MAP_XI (1L<<18)
3788#define BNX2_RPM_RC_CNTL_13_SBIT_XI (1L<<19)
3789#define BNX2_RPM_RC_CNTL_13_CMDSEL_XI (0x1fL<<20)
3790#define BNX2_RPM_RC_CNTL_13_DISCARD_XI (1L<<25)
3791#define BNX2_RPM_RC_CNTL_13_MASK_XI (1L<<26)
3792#define BNX2_RPM_RC_CNTL_13_P1_XI (1L<<27)
3793#define BNX2_RPM_RC_CNTL_13_P2_XI (1L<<28)
3794#define BNX2_RPM_RC_CNTL_13_P3_XI (1L<<29)
3795#define BNX2_RPM_RC_CNTL_13_NBIT_XI (1L<<30)
2069 3796
2070#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c 3797#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
3798#define BNX2_RPM_RC_VALUE_MASK_13_VALUE (0xffffL<<0)
3799#define BNX2_RPM_RC_VALUE_MASK_13_MASK (0xffffL<<16)
3800
2071#define BNX2_RPM_RC_CNTL_14 0x00001970 3801#define BNX2_RPM_RC_CNTL_14 0x00001970
2072#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0) 3802#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2073#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19) 3803#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
3804#define BNX2_RPM_RC_CNTL_14_OFFSET_XI (0xffL<<0)
3805#define BNX2_RPM_RC_CNTL_14_CLASS_XI (0x7L<<8)
3806#define BNX2_RPM_RC_CNTL_14_PRIORITY_XI (1L<<11)
3807#define BNX2_RPM_RC_CNTL_14_P4_XI (1L<<12)
3808#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI (0x7L<<13)
3809#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI (0L<<13)
3810#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI (1L<<13)
3811#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI (2L<<13)
3812#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI (3L<<13)
3813#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI (4L<<13)
3814#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI (5L<<13)
3815#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI (6L<<13)
3816#define BNX2_RPM_RC_CNTL_14_COMP_XI (0x3L<<16)
3817#define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI (0L<<16)
3818#define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI (1L<<16)
3819#define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI (2L<<16)
3820#define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI (3L<<16)
3821#define BNX2_RPM_RC_CNTL_14_MAP_XI (1L<<18)
3822#define BNX2_RPM_RC_CNTL_14_SBIT_XI (1L<<19)
3823#define BNX2_RPM_RC_CNTL_14_CMDSEL_XI (0x1fL<<20)
3824#define BNX2_RPM_RC_CNTL_14_DISCARD_XI (1L<<25)
3825#define BNX2_RPM_RC_CNTL_14_MASK_XI (1L<<26)
3826#define BNX2_RPM_RC_CNTL_14_P1_XI (1L<<27)
3827#define BNX2_RPM_RC_CNTL_14_P2_XI (1L<<28)
3828#define BNX2_RPM_RC_CNTL_14_P3_XI (1L<<29)
3829#define BNX2_RPM_RC_CNTL_14_NBIT_XI (1L<<30)
2074 3830
2075#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974 3831#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
3832#define BNX2_RPM_RC_VALUE_MASK_14_VALUE (0xffffL<<0)
3833#define BNX2_RPM_RC_VALUE_MASK_14_MASK (0xffffL<<16)
3834
2076#define BNX2_RPM_RC_CNTL_15 0x00001978 3835#define BNX2_RPM_RC_CNTL_15 0x00001978
2077#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0) 3836#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2078#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19) 3837#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
3838#define BNX2_RPM_RC_CNTL_15_OFFSET_XI (0xffL<<0)
3839#define BNX2_RPM_RC_CNTL_15_CLASS_XI (0x7L<<8)
3840#define BNX2_RPM_RC_CNTL_15_PRIORITY_XI (1L<<11)
3841#define BNX2_RPM_RC_CNTL_15_P4_XI (1L<<12)
3842#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI (0x7L<<13)
3843#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI (0L<<13)
3844#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI (1L<<13)
3845#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI (2L<<13)
3846#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI (3L<<13)
3847#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI (4L<<13)
3848#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI (5L<<13)
3849#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI (6L<<13)
3850#define BNX2_RPM_RC_CNTL_15_COMP_XI (0x3L<<16)
3851#define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI (0L<<16)
3852#define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI (1L<<16)
3853#define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI (2L<<16)
3854#define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI (3L<<16)
3855#define BNX2_RPM_RC_CNTL_15_MAP_XI (1L<<18)
3856#define BNX2_RPM_RC_CNTL_15_SBIT_XI (1L<<19)
3857#define BNX2_RPM_RC_CNTL_15_CMDSEL_XI (0x1fL<<20)
3858#define BNX2_RPM_RC_CNTL_15_DISCARD_XI (1L<<25)
3859#define BNX2_RPM_RC_CNTL_15_MASK_XI (1L<<26)
3860#define BNX2_RPM_RC_CNTL_15_P1_XI (1L<<27)
3861#define BNX2_RPM_RC_CNTL_15_P2_XI (1L<<28)
3862#define BNX2_RPM_RC_CNTL_15_P3_XI (1L<<29)
3863#define BNX2_RPM_RC_CNTL_15_NBIT_XI (1L<<30)
2079 3864
2080#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c 3865#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
3866#define BNX2_RPM_RC_VALUE_MASK_15_VALUE (0xffffL<<0)
3867#define BNX2_RPM_RC_VALUE_MASK_15_MASK (0xffffL<<16)
3868
2081#define BNX2_RPM_RC_CONFIG 0x00001980 3869#define BNX2_RPM_RC_CONFIG 0x00001980
2082#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 3870#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
3871#define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI (0xfffffL<<0)
2083#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 3872#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
3873#define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE (1L<<31)
2084 3874
2085#define BNX2_RPM_DEBUG0 0x00001984 3875#define BNX2_RPM_DEBUG0 0x00001984
2086#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 3876#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
@@ -2236,6 +4026,16 @@ struct l2_fhdr {
2236#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 4026#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2237#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 4027#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2238#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 4028#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
4029#define BNX2_RPM_DEBUG9_BEMEM_R_XI (0x1fL<<0)
4030#define BNX2_RPM_DEBUG9_EO_XI (1L<<5)
4031#define BNX2_RPM_DEBUG9_AEOF_DE_XI (1L<<6)
4032#define BNX2_RPM_DEBUG9_SO_XI (1L<<7)
4033#define BNX2_RPM_DEBUG9_WD64_CT_XI (0x1fL<<8)
4034#define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI (0x7L<<13)
4035#define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI (0xfL<<16)
4036#define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI (0x3ffL<<20)
4037#define BNX2_RPM_DEBUG9_DATA_IN_VL_XI (1L<<30)
4038#define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI (1L<<31)
2239 4039
2240#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0 4040#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
2241#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4 4041#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
@@ -2253,6 +4053,56 @@ struct l2_fhdr {
2253#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4 4053#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
2254#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8 4054#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
2255#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc 4055#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
4056#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL 0x00001a00
4057#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS (0xffffL<<0)
4058#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD (1L<<28)
4059#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE (1L<<29)
4060#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT (1L<<30)
4061#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR (1L<<31)
4062
4063#define BNX2_RPM_ACPI_PATTERN_CTRL 0x00001a04
4064#define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID (0xfL<<0)
4065#define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR (1L<<30)
4066#define BNX2_RPM_ACPI_PATTERN_CTRL_WR (1L<<31)
4067
4068#define BNX2_RPM_ACPI_DATA 0x00001a08
4069#define BNX2_RPM_ACPI_DATA_PATTERN_BE (0xffffffffL<<0)
4070
4071#define BNX2_RPM_ACPI_PATTERN_LEN0 0x00001a0c
4072#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 (0xffL<<0)
4073#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 (0xffL<<8)
4074#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 (0xffL<<16)
4075#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 (0xffL<<24)
4076
4077#define BNX2_RPM_ACPI_PATTERN_LEN1 0x00001a10
4078#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 (0xffL<<0)
4079#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 (0xffL<<8)
4080#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 (0xffL<<16)
4081#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 (0xffL<<24)
4082
4083#define BNX2_RPM_ACPI_PATTERN_CRC0 0x00001a18
4084#define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 (0xffffffffL<<0)
4085
4086#define BNX2_RPM_ACPI_PATTERN_CRC1 0x00001a1c
4087#define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 (0xffffffffL<<0)
4088
4089#define BNX2_RPM_ACPI_PATTERN_CRC2 0x00001a20
4090#define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 (0xffffffffL<<0)
4091
4092#define BNX2_RPM_ACPI_PATTERN_CRC3 0x00001a24
4093#define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 (0xffffffffL<<0)
4094
4095#define BNX2_RPM_ACPI_PATTERN_CRC4 0x00001a28
4096#define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 (0xffffffffL<<0)
4097
4098#define BNX2_RPM_ACPI_PATTERN_CRC5 0x00001a2c
4099#define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 (0xffffffffL<<0)
4100
4101#define BNX2_RPM_ACPI_PATTERN_CRC6 0x00001a30
4102#define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 (0xffffffffL<<0)
4103
4104#define BNX2_RPM_ACPI_PATTERN_CRC7 0x00001a34
4105#define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 (0xffffffffL<<0)
2256 4106
2257 4107
2258/* 4108/*
@@ -2263,15 +4113,20 @@ struct l2_fhdr {
2263#define BNX2_RBUF_COMMAND_ENABLED (1L<<0) 4113#define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
2264#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1) 4114#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
2265#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2) 4115#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
4116#define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL (1L<<3)
2266#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4) 4117#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
2267#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5) 4118#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
4119#define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE (1L<<6)
4120#define BNX2_RBUF_COMMAND_CU_ISOLATE_XI (1L<<5)
4121#define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI (1L<<6)
4122#define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI (1L<<7)
2268 4123
2269#define BNX2_RBUF_STATUS1 0x00200004 4124#define BNX2_RBUF_STATUS1 0x00200004
2270#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 4125#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2271 4126
2272#define BNX2_RBUF_STATUS2 0x00200008 4127#define BNX2_RBUF_STATUS2 0x00200008
2273#define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 4128#define BNX2_RBUF_STATUS2_FREE_TAIL (0x1ffL<<0)
2274#define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 4129#define BNX2_RBUF_STATUS2_FREE_HEAD (0x1ffL<<16)
2275 4130
2276#define BNX2_RBUF_CONFIG 0x0020000c 4131#define BNX2_RBUF_CONFIG 0x0020000c
2277#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 4132#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
@@ -2279,16 +4134,21 @@ struct l2_fhdr {
2279 4134
2280#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010 4135#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
2281#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 4136#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
4137#define BNX2_RBUF_FW_BUF_ALLOC_TYPE (1L<<16)
4138#define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ (1L<<31)
2282 4139
2283#define BNX2_RBUF_FW_BUF_FREE 0x00200014 4140#define BNX2_RBUF_FW_BUF_FREE 0x00200014
2284#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 4141#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2285#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 4142#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2286#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 4143#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
4144#define BNX2_RBUF_FW_BUF_FREE_TYPE (1L<<25)
4145#define BNX2_RBUF_FW_BUF_FREE_FREE_REQ (1L<<31)
2287 4146
2288#define BNX2_RBUF_FW_BUF_SEL 0x00200018 4147#define BNX2_RBUF_FW_BUF_SEL 0x00200018
2289#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 4148#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2290#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 4149#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2291#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 4150#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
4151#define BNX2_RBUF_FW_BUF_SEL_SEL_REQ (1L<<31)
2292 4152
2293#define BNX2_RBUF_CONFIG2 0x0020001c 4153#define BNX2_RBUF_CONFIG2 0x0020001c
2294#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 4154#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
@@ -2376,6 +4236,8 @@ struct l2_fhdr {
2376#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 4236#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
2377 4237
2378#define BNX2_RV2P_INSTR_LOW 0x00002834 4238#define BNX2_RV2P_INSTR_LOW 0x00002834
4239#define BNX2_RV2P_INSTR_LOW_LOW (0xffffffffL<<0)
4240
2379#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838 4241#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
2380#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 4242#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
2381#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 4243#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
@@ -2395,7 +4257,29 @@ struct l2_fhdr {
2395#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4257#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2396#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4258#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2397 4259
2398#define BNX2_RV2P_PFTQ_DATA 0x00002b40 4260#define BNX2_RV2P_MPFE_PFE_CTL 0x00002afc
4261#define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
4262#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE (0xfL<<4)
4263#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
4264#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
4265#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
4266#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
4267#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
4268#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
4269#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
4270#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
4271#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
4272#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
4273#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
4274#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
4275#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
4276#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
4277#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
4278#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
4279#define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT (0xfL<<12)
4280#define BNX2_RV2P_MPFE_PFE_CTL_OFFSET (0x1ffL<<16)
4281
4282#define BNX2_RV2P_RV2PPQ 0x00002b40
2399#define BNX2_RV2P_PFTQ_CMD 0x00002b78 4283#define BNX2_RV2P_PFTQ_CMD 0x00002b78
2400#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 4284#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
2401#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 4285#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
@@ -2416,7 +4300,7 @@ struct l2_fhdr {
2416#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4300#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2417#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4301#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2418 4302
2419#define BNX2_RV2P_TFTQ_DATA 0x00002b80 4303#define BNX2_RV2P_RV2PTQ 0x00002b80
2420#define BNX2_RV2P_TFTQ_CMD 0x00002bb8 4304#define BNX2_RV2P_TFTQ_CMD 0x00002bb8
2421#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 4305#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
2422#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 4306#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
@@ -2437,7 +4321,7 @@ struct l2_fhdr {
2437#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4321#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2438#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4322#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2439 4323
2440#define BNX2_RV2P_MFTQ_DATA 0x00002bc0 4324#define BNX2_RV2P_RV2PMQ 0x00002bc0
2441#define BNX2_RV2P_MFTQ_CMD 0x00002bf8 4325#define BNX2_RV2P_MFTQ_CMD 0x00002bf8
2442#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 4326#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
2443#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 4327#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
@@ -2466,18 +4350,26 @@ struct l2_fhdr {
2466 */ 4350 */
2467#define BNX2_MQ_COMMAND 0x00003c00 4351#define BNX2_MQ_COMMAND 0x00003c00
2468#define BNX2_MQ_COMMAND_ENABLED (1L<<0) 4352#define BNX2_MQ_COMMAND_ENABLED (1L<<0)
4353#define BNX2_MQ_COMMAND_INIT (1L<<1)
2469#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4) 4354#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
2470#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5) 4355#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
2471#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6) 4356#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
4357#define BNX2_MQ_COMMAND_IDB_CFG_ERROR (1L<<7)
4358#define BNX2_MQ_COMMAND_IDB_OVERFLOW (1L<<10)
4359#define BNX2_MQ_COMMAND_NO_BIN_ERROR (1L<<11)
4360#define BNX2_MQ_COMMAND_NO_MAP_ERROR (1L<<12)
2472 4361
2473#define BNX2_MQ_STATUS 0x00003c04 4362#define BNX2_MQ_STATUS 0x00003c04
2474#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 4363#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
2475#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 4364#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
2476#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18) 4365#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
4366#define BNX2_MQ_STATUS_IDB_OFLOW_STAT (1L<<19)
2477 4367
2478#define BNX2_MQ_CONFIG 0x00003c08 4368#define BNX2_MQ_CONFIG 0x00003c08
2479#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 4369#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
2480#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1) 4370#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
4371#define BNX2_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
4372#define BNX2_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
2481#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 4373#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
2482#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 4374#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
2483#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 4375#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
@@ -2533,6 +4425,7 @@ struct l2_fhdr {
2533 4425
2534#define BNX2_MQ_MEM_WR_DATA2 0x00003c80 4426#define BNX2_MQ_MEM_WR_DATA2 0x00003c80
2535#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 4427#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
4428#define BNX2_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0)
2536 4429
2537#define BNX2_MQ_MEM_RD_ADDR 0x00003c84 4430#define BNX2_MQ_MEM_RD_ADDR 0x00003c84
2538#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 4431#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
@@ -2545,6 +4438,16 @@ struct l2_fhdr {
2545 4438
2546#define BNX2_MQ_MEM_RD_DATA2 0x00003c90 4439#define BNX2_MQ_MEM_RD_DATA2 0x00003c90
2547#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 4440#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
4441#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
4442
4443
4444/*
4445 * tsch_reg definition
4446 * offset: 0x4c00
4447 */
4448#define BNX2_TSCH_TSS_CFG 0x00004c1c
4449#define BNX2_TSCH_TSS_CFG_TSS_START_CID (0x7ffL<<8)
4450#define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfL<<24)
2548 4451
2549 4452
2550 4453
@@ -2594,7 +4497,11 @@ struct l2_fhdr {
2594#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4497#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2595#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4498#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2596 4499
2597#define BNX2_TBDR_FTQ_DATA 0x000053c0 4500#define BNX2_TBDR_CKSUM_ERROR_STATUS 0x00005010
4501#define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
4502#define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
4503
4504#define BNX2_TBDR_TBDRQ 0x000053c0
2598#define BNX2_TBDR_FTQ_CMD 0x000053f8 4505#define BNX2_TBDR_FTQ_CMD 0x000053f8
2599#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 4506#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
2600#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10) 4507#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
@@ -2624,7 +4531,15 @@ struct l2_fhdr {
2624#define BNX2_TDMA_COMMAND 0x00005c00 4531#define BNX2_TDMA_COMMAND 0x00005c00
2625#define BNX2_TDMA_COMMAND_ENABLED (1L<<0) 4532#define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
2626#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4) 4533#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
4534#define BNX2_TDMA_COMMAND_CS16_ERR (1L<<5)
2627#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 4535#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
4536#define BNX2_TDMA_COMMAND_MASK_CS1 (1L<<20)
4537#define BNX2_TDMA_COMMAND_MASK_CS2 (1L<<21)
4538#define BNX2_TDMA_COMMAND_MASK_CS3 (1L<<22)
4539#define BNX2_TDMA_COMMAND_MASK_CS4 (1L<<23)
4540#define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR (1L<<24)
4541#define BNX2_TDMA_COMMAND_OFIFO_CLR (1L<<30)
4542#define BNX2_TDMA_COMMAND_IFIFO_CLR (1L<<31)
2628 4543
2629#define BNX2_TDMA_STATUS 0x00005c04 4544#define BNX2_TDMA_STATUS 0x00005c04
2630#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0) 4545#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
@@ -2633,10 +4548,18 @@ struct l2_fhdr {
2633#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3) 4548#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
2634#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 4549#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
2635#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17) 4550#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
4551#define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH (0x3fL<<20)
4552#define BNX2_TDMA_STATUS_OFIFO_OVERFLOW (1L<<30)
4553#define BNX2_TDMA_STATUS_IFIFO_OVERFLOW (1L<<31)
2636 4554
2637#define BNX2_TDMA_CONFIG 0x00005c08 4555#define BNX2_TDMA_CONFIG 0x00005c08
2638#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0) 4556#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
2639#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1) 4557#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
4558#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN (0x3L<<2)
4559#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 (0L<<2)
4560#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1 (1L<<2)
4561#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2 (2L<<2)
4562#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3 (3L<<2)
2640#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 4563#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
2641#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 4564#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
2642#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 4565#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
@@ -2649,7 +4572,35 @@ struct l2_fhdr {
2649#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 4572#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
2650#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15) 4573#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
2651#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16) 4574#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
4575#define BNX2_TDMA_CONFIG_CMPL_ENTRY (1L<<17)
4576#define BNX2_TDMA_CONFIG_OFIFO_CMP (1L<<19)
4577#define BNX2_TDMA_CONFIG_OFIFO_CMP_3 (0L<<19)
4578#define BNX2_TDMA_CONFIG_OFIFO_CMP_2 (1L<<19)
2652#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 4579#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
4580#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI (0x7L<<20)
4581#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI (0L<<20)
4582#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI (1L<<20)
4583#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI (2L<<20)
4584#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI (3L<<20)
4585#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI (4L<<20)
4586#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI (5L<<20)
4587#define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI (1L<<23)
4588#define BNX2_TDMA_CONFIG_BYTES_OST_XI (0x7L<<24)
4589#define BNX2_TDMA_CONFIG_BYTES_OST_512_XI (0L<<24)
4590#define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI (1L<<24)
4591#define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI (2L<<24)
4592#define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI (3L<<24)
4593#define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI (4L<<24)
4594#define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI (5L<<24)
4595#define BNX2_TDMA_CONFIG_HC_BYPASS_XI (1L<<27)
4596#define BNX2_TDMA_CONFIG_LCL_MRRS_XI (0x7L<<28)
4597#define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI (0L<<28)
4598#define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI (1L<<28)
4599#define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI (2L<<28)
4600#define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI (3L<<28)
4601#define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI (4L<<28)
4602#define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI (5L<<28)
4603#define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI (1L<<31)
2653 4604
2654#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c 4605#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
2655#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 4606#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
@@ -2685,7 +4636,22 @@ struct l2_fhdr {
2685#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 4636#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
2686#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 4637#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
2687 4638
2688#define BNX2_TDMA_FTQ_DATA 0x00005fc0 4639#define BNX2_TDMA_PUSH_FSM 0x00005c90
4640#define BNX2_TDMA_BD_IF_DEBUG 0x00005c94
4641#define BNX2_TDMA_DMAD_IF_DEBUG 0x00005c98
4642#define BNX2_TDMA_CTX_IF_DEBUG 0x00005c9c
4643#define BNX2_TDMA_TPBUF_IF_DEBUG 0x00005ca0
4644#define BNX2_TDMA_DR_IF_DEBUG 0x00005ca4
4645#define BNX2_TDMA_TPATQ_IF_DEBUG 0x00005ca8
4646#define BNX2_TDMA_TDMA_ILOCK_CKSUM 0x00005cac
4647#define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED (0xffffL<<0)
4648#define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED (0xffffL<<16)
4649
4650#define BNX2_TDMA_TDMA_PCIE_CKSUM 0x00005cb0
4651#define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED (0xffffL<<0)
4652#define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED (0xffffL<<16)
4653
4654#define BNX2_TDMA_TDMAQ 0x00005fc0
2689#define BNX2_TDMA_FTQ_CMD 0x00005ff8 4655#define BNX2_TDMA_FTQ_CMD 0x00005ff8
2690#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 4656#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
2691#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10) 4657#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
@@ -2724,6 +4690,8 @@ struct l2_fhdr {
2724#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19) 4690#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
2725#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19) 4691#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
2726#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21) 4692#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
4693#define BNX2_HC_COMMAND_MAIN_PWR_INT (1L<<22)
4694#define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27)
2727 4695
2728#define BNX2_HC_STATUS 0x00006804 4696#define BNX2_HC_STATUS 0x00006804
2729#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0) 4697#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
@@ -2746,6 +4714,23 @@ struct l2_fhdr {
2746#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 4714#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
2747#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6) 4715#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
2748#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 4716#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
4717#define BNX2_HC_CONFIG_PER_MODE (1L<<16)
4718#define BNX2_HC_CONFIG_ONE_SHOT (1L<<17)
4719#define BNX2_HC_CONFIG_USE_INT_PARAM (1L<<18)
4720#define BNX2_HC_CONFIG_SET_MASK_AT_RD (1L<<19)
4721#define BNX2_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20)
4722#define BNX2_HC_CONFIG_SB_ADDR_INC (0x7L<<24)
4723#define BNX2_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
4724#define BNX2_HC_CONFIG_SB_ADDR_INC_128B (1L<<24)
4725#define BNX2_HC_CONFIG_SB_ADDR_INC_256B (2L<<24)
4726#define BNX2_HC_CONFIG_SB_ADDR_INC_512B (3L<<24)
4727#define BNX2_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24)
4728#define BNX2_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24)
4729#define BNX2_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24)
4730#define BNX2_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24)
4731#define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29)
4732#define BNX2_HC_CONFIG_UNMASK_ALL (1L<<30)
4733#define BNX2_HC_CONFIG_TX_SEL (1L<<31)
2749 4734
2750#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c 4735#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
2751#define BNX2_HC_STATUS_ADDR_L 0x00006810 4736#define BNX2_HC_STATUS_ADDR_L 0x00006810
@@ -2782,6 +4767,7 @@ struct l2_fhdr {
2782 4767
2783#define BNX2_HC_PERIODIC_TICKS 0x0000683c 4768#define BNX2_HC_PERIODIC_TICKS 0x0000683c
2784#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 4769#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
4770#define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16)
2785 4771
2786#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840 4772#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
2787#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 4773#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
@@ -2789,6 +4775,10 @@ struct l2_fhdr {
2789#define BNX2_HC_STATS_TICKS 0x00006844 4775#define BNX2_HC_STATS_TICKS 0x00006844
2790#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 4776#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
2791 4777
4778#define BNX2_HC_STATS_INTERRUPT_STATUS 0x00006848
4779#define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0)
4780#define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16)
4781
2792#define BNX2_HC_STAT_MEM_DATA 0x0000684c 4782#define BNX2_HC_STAT_MEM_DATA 0x0000684c
2793#define BNX2_HC_STAT_GEN_SEL_0 0x00006850 4783#define BNX2_HC_STAT_GEN_SEL_0 0x00006850
2794#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 4784#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
@@ -2917,24 +4907,108 @@ struct l2_fhdr {
2917#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 4907#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
2918#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 4908#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
2919#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 4909#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
4910#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0)
4911#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
4912#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
4913#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
4914#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
4915#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
4916#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
4917#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
4918#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
4919#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
4920#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
4921#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
4922#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
4923#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
4924#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
4925#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
4926#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
4927#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
4928#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
4929#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
4930#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
4931#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
4932#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
4933#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
4934#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
4935#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
4936#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
4937#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
4938#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
4939#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
4940#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
4941#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
4942#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
4943#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
4944#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
4945#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
4946#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
4947#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
4948#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
4949#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
4950#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
4951#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
4952#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
4953#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
4954#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
4955#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
4956#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
4957#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
4958#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
4959#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
4960#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
4961#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
4962#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
4963#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
4964#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
4965#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
4966#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
4967#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
4968#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
4969#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
4970#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
4971#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
4972#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
4973#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
4974#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
4975#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
4976#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
4977#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
4978#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
4979#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8)
4980#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16)
4981#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24)
2920 4982
2921#define BNX2_HC_STAT_GEN_SEL_1 0x00006854 4983#define BNX2_HC_STAT_GEN_SEL_1 0x00006854
2922#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 4984#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
2923#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 4985#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
2924#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 4986#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
2925#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 4987#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
4988#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0)
4989#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8)
4990#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16)
4991#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24)
2926 4992
2927#define BNX2_HC_STAT_GEN_SEL_2 0x00006858 4993#define BNX2_HC_STAT_GEN_SEL_2 0x00006858
2928#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 4994#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
2929#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 4995#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
2930#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 4996#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
2931#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 4997#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
4998#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0)
4999#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8)
5000#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16)
5001#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24)
2932 5002
2933#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c 5003#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
2934#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 5004#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
2935#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 5005#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
2936#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 5006#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
2937#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 5007#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
5008#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0)
5009#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8)
5010#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16)
5011#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24)
2938 5012
2939#define BNX2_HC_STAT_GEN_STAT0 0x00006888 5013#define BNX2_HC_STAT_GEN_STAT0 0x00006888
2940#define BNX2_HC_STAT_GEN_STAT1 0x0000688c 5014#define BNX2_HC_STAT_GEN_STAT1 0x0000688c
@@ -2968,6 +5042,7 @@ struct l2_fhdr {
2968#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc 5042#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
2969#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900 5043#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
2970#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904 5044#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
5045#define BNX2_HC_STAT_GEN_STAT_AC 0x000068c8
2971#define BNX2_HC_VIS 0x00006908 5046#define BNX2_HC_VIS 0x00006908
2972#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 5047#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
2973#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 5048#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
@@ -3038,6 +5113,349 @@ struct l2_fhdr {
3038#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 5113#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3039#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 5114#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3040 5115
5116#define BNX2_HC_COALESCE_NOW 0x00006914
5117#define BNX2_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1)
5118#define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11)
5119#define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21)
5120
5121#define BNX2_HC_MSIX_BIT_VECTOR 0x00006918
5122#define BNX2_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0)
5123
5124#define BNX2_HC_SB_CONFIG_1 0x00006a00
5125#define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1)
5126#define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2)
5127#define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3)
5128#define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4)
5129#define BNX2_HC_SB_CONFIG_1_PER_MODE (1L<<16)
5130#define BNX2_HC_SB_CONFIG_1_ONE_SHOT (1L<<17)
5131#define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18)
5132#define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20)
5133
5134#define BNX2_HC_TX_QUICK_CONS_TRIP_1 0x00006a04
5135#define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
5136#define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
5137
5138#define BNX2_HC_COMP_PROD_TRIP_1 0x00006a08
5139#define BNX2_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0)
5140#define BNX2_HC_COMP_PROD_TRIP_1_INT (0xffL<<16)
5141
5142#define BNX2_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c
5143#define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
5144#define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
5145
5146#define BNX2_HC_RX_TICKS_1 0x00006a10
5147#define BNX2_HC_RX_TICKS_1_VALUE (0x3ffL<<0)
5148#define BNX2_HC_RX_TICKS_1_INT (0x3ffL<<16)
5149
5150#define BNX2_HC_TX_TICKS_1 0x00006a14
5151#define BNX2_HC_TX_TICKS_1_VALUE (0x3ffL<<0)
5152#define BNX2_HC_TX_TICKS_1_INT (0x3ffL<<16)
5153
5154#define BNX2_HC_COM_TICKS_1 0x00006a18
5155#define BNX2_HC_COM_TICKS_1_VALUE (0x3ffL<<0)
5156#define BNX2_HC_COM_TICKS_1_INT (0x3ffL<<16)
5157
5158#define BNX2_HC_CMD_TICKS_1 0x00006a1c
5159#define BNX2_HC_CMD_TICKS_1_VALUE (0x3ffL<<0)
5160#define BNX2_HC_CMD_TICKS_1_INT (0x3ffL<<16)
5161
5162#define BNX2_HC_PERIODIC_TICKS_1 0x00006a20
5163#define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0)
5164#define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5165
5166#define BNX2_HC_SB_CONFIG_2 0x00006a24
5167#define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1)
5168#define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2)
5169#define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3)
5170#define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4)
5171#define BNX2_HC_SB_CONFIG_2_PER_MODE (1L<<16)
5172#define BNX2_HC_SB_CONFIG_2_ONE_SHOT (1L<<17)
5173#define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18)
5174#define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20)
5175
5176#define BNX2_HC_TX_QUICK_CONS_TRIP_2 0x00006a28
5177#define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
5178#define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
5179
5180#define BNX2_HC_COMP_PROD_TRIP_2 0x00006a2c
5181#define BNX2_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0)
5182#define BNX2_HC_COMP_PROD_TRIP_2_INT (0xffL<<16)
5183
5184#define BNX2_HC_RX_QUICK_CONS_TRIP_2 0x00006a30
5185#define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
5186#define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
5187
5188#define BNX2_HC_RX_TICKS_2 0x00006a34
5189#define BNX2_HC_RX_TICKS_2_VALUE (0x3ffL<<0)
5190#define BNX2_HC_RX_TICKS_2_INT (0x3ffL<<16)
5191
5192#define BNX2_HC_TX_TICKS_2 0x00006a38
5193#define BNX2_HC_TX_TICKS_2_VALUE (0x3ffL<<0)
5194#define BNX2_HC_TX_TICKS_2_INT (0x3ffL<<16)
5195
5196#define BNX2_HC_COM_TICKS_2 0x00006a3c
5197#define BNX2_HC_COM_TICKS_2_VALUE (0x3ffL<<0)
5198#define BNX2_HC_COM_TICKS_2_INT (0x3ffL<<16)
5199
5200#define BNX2_HC_CMD_TICKS_2 0x00006a40
5201#define BNX2_HC_CMD_TICKS_2_VALUE (0x3ffL<<0)
5202#define BNX2_HC_CMD_TICKS_2_INT (0x3ffL<<16)
5203
5204#define BNX2_HC_PERIODIC_TICKS_2 0x00006a44
5205#define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0)
5206#define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5207
5208#define BNX2_HC_SB_CONFIG_3 0x00006a48
5209#define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1)
5210#define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2)
5211#define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3)
5212#define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4)
5213#define BNX2_HC_SB_CONFIG_3_PER_MODE (1L<<16)
5214#define BNX2_HC_SB_CONFIG_3_ONE_SHOT (1L<<17)
5215#define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18)
5216#define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20)
5217
5218#define BNX2_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c
5219#define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
5220#define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
5221
5222#define BNX2_HC_COMP_PROD_TRIP_3 0x00006a50
5223#define BNX2_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0)
5224#define BNX2_HC_COMP_PROD_TRIP_3_INT (0xffL<<16)
5225
5226#define BNX2_HC_RX_QUICK_CONS_TRIP_3 0x00006a54
5227#define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
5228#define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
5229
5230#define BNX2_HC_RX_TICKS_3 0x00006a58
5231#define BNX2_HC_RX_TICKS_3_VALUE (0x3ffL<<0)
5232#define BNX2_HC_RX_TICKS_3_INT (0x3ffL<<16)
5233
5234#define BNX2_HC_TX_TICKS_3 0x00006a5c
5235#define BNX2_HC_TX_TICKS_3_VALUE (0x3ffL<<0)
5236#define BNX2_HC_TX_TICKS_3_INT (0x3ffL<<16)
5237
5238#define BNX2_HC_COM_TICKS_3 0x00006a60
5239#define BNX2_HC_COM_TICKS_3_VALUE (0x3ffL<<0)
5240#define BNX2_HC_COM_TICKS_3_INT (0x3ffL<<16)
5241
5242#define BNX2_HC_CMD_TICKS_3 0x00006a64
5243#define BNX2_HC_CMD_TICKS_3_VALUE (0x3ffL<<0)
5244#define BNX2_HC_CMD_TICKS_3_INT (0x3ffL<<16)
5245
5246#define BNX2_HC_PERIODIC_TICKS_3 0x00006a68
5247#define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0)
5248#define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5249
5250#define BNX2_HC_SB_CONFIG_4 0x00006a6c
5251#define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1)
5252#define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2)
5253#define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3)
5254#define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4)
5255#define BNX2_HC_SB_CONFIG_4_PER_MODE (1L<<16)
5256#define BNX2_HC_SB_CONFIG_4_ONE_SHOT (1L<<17)
5257#define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18)
5258#define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20)
5259
5260#define BNX2_HC_TX_QUICK_CONS_TRIP_4 0x00006a70
5261#define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
5262#define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
5263
5264#define BNX2_HC_COMP_PROD_TRIP_4 0x00006a74
5265#define BNX2_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0)
5266#define BNX2_HC_COMP_PROD_TRIP_4_INT (0xffL<<16)
5267
5268#define BNX2_HC_RX_QUICK_CONS_TRIP_4 0x00006a78
5269#define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
5270#define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
5271
5272#define BNX2_HC_RX_TICKS_4 0x00006a7c
5273#define BNX2_HC_RX_TICKS_4_VALUE (0x3ffL<<0)
5274#define BNX2_HC_RX_TICKS_4_INT (0x3ffL<<16)
5275
5276#define BNX2_HC_TX_TICKS_4 0x00006a80
5277#define BNX2_HC_TX_TICKS_4_VALUE (0x3ffL<<0)
5278#define BNX2_HC_TX_TICKS_4_INT (0x3ffL<<16)
5279
5280#define BNX2_HC_COM_TICKS_4 0x00006a84
5281#define BNX2_HC_COM_TICKS_4_VALUE (0x3ffL<<0)
5282#define BNX2_HC_COM_TICKS_4_INT (0x3ffL<<16)
5283
5284#define BNX2_HC_CMD_TICKS_4 0x00006a88
5285#define BNX2_HC_CMD_TICKS_4_VALUE (0x3ffL<<0)
5286#define BNX2_HC_CMD_TICKS_4_INT (0x3ffL<<16)
5287
5288#define BNX2_HC_PERIODIC_TICKS_4 0x00006a8c
5289#define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0)
5290#define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5291
5292#define BNX2_HC_SB_CONFIG_5 0x00006a90
5293#define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1)
5294#define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2)
5295#define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3)
5296#define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4)
5297#define BNX2_HC_SB_CONFIG_5_PER_MODE (1L<<16)
5298#define BNX2_HC_SB_CONFIG_5_ONE_SHOT (1L<<17)
5299#define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18)
5300#define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20)
5301
5302#define BNX2_HC_TX_QUICK_CONS_TRIP_5 0x00006a94
5303#define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
5304#define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
5305
5306#define BNX2_HC_COMP_PROD_TRIP_5 0x00006a98
5307#define BNX2_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0)
5308#define BNX2_HC_COMP_PROD_TRIP_5_INT (0xffL<<16)
5309
5310#define BNX2_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c
5311#define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
5312#define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
5313
5314#define BNX2_HC_RX_TICKS_5 0x00006aa0
5315#define BNX2_HC_RX_TICKS_5_VALUE (0x3ffL<<0)
5316#define BNX2_HC_RX_TICKS_5_INT (0x3ffL<<16)
5317
5318#define BNX2_HC_TX_TICKS_5 0x00006aa4
5319#define BNX2_HC_TX_TICKS_5_VALUE (0x3ffL<<0)
5320#define BNX2_HC_TX_TICKS_5_INT (0x3ffL<<16)
5321
5322#define BNX2_HC_COM_TICKS_5 0x00006aa8
5323#define BNX2_HC_COM_TICKS_5_VALUE (0x3ffL<<0)
5324#define BNX2_HC_COM_TICKS_5_INT (0x3ffL<<16)
5325
5326#define BNX2_HC_CMD_TICKS_5 0x00006aac
5327#define BNX2_HC_CMD_TICKS_5_VALUE (0x3ffL<<0)
5328#define BNX2_HC_CMD_TICKS_5_INT (0x3ffL<<16)
5329
5330#define BNX2_HC_PERIODIC_TICKS_5 0x00006ab0
5331#define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0)
5332#define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5333
5334#define BNX2_HC_SB_CONFIG_6 0x00006ab4
5335#define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1)
5336#define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2)
5337#define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3)
5338#define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4)
5339#define BNX2_HC_SB_CONFIG_6_PER_MODE (1L<<16)
5340#define BNX2_HC_SB_CONFIG_6_ONE_SHOT (1L<<17)
5341#define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18)
5342#define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20)
5343
5344#define BNX2_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8
5345#define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
5346#define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
5347
5348#define BNX2_HC_COMP_PROD_TRIP_6 0x00006abc
5349#define BNX2_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0)
5350#define BNX2_HC_COMP_PROD_TRIP_6_INT (0xffL<<16)
5351
5352#define BNX2_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0
5353#define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
5354#define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
5355
5356#define BNX2_HC_RX_TICKS_6 0x00006ac4
5357#define BNX2_HC_RX_TICKS_6_VALUE (0x3ffL<<0)
5358#define BNX2_HC_RX_TICKS_6_INT (0x3ffL<<16)
5359
5360#define BNX2_HC_TX_TICKS_6 0x00006ac8
5361#define BNX2_HC_TX_TICKS_6_VALUE (0x3ffL<<0)
5362#define BNX2_HC_TX_TICKS_6_INT (0x3ffL<<16)
5363
5364#define BNX2_HC_COM_TICKS_6 0x00006acc
5365#define BNX2_HC_COM_TICKS_6_VALUE (0x3ffL<<0)
5366#define BNX2_HC_COM_TICKS_6_INT (0x3ffL<<16)
5367
5368#define BNX2_HC_CMD_TICKS_6 0x00006ad0
5369#define BNX2_HC_CMD_TICKS_6_VALUE (0x3ffL<<0)
5370#define BNX2_HC_CMD_TICKS_6_INT (0x3ffL<<16)
5371
5372#define BNX2_HC_PERIODIC_TICKS_6 0x00006ad4
5373#define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0)
5374#define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5375
5376#define BNX2_HC_SB_CONFIG_7 0x00006ad8
5377#define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1)
5378#define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2)
5379#define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3)
5380#define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4)
5381#define BNX2_HC_SB_CONFIG_7_PER_MODE (1L<<16)
5382#define BNX2_HC_SB_CONFIG_7_ONE_SHOT (1L<<17)
5383#define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18)
5384#define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20)
5385
5386#define BNX2_HC_TX_QUICK_CONS_TRIP_7 0x00006adc
5387#define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
5388#define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
5389
5390#define BNX2_HC_COMP_PROD_TRIP_7 0x00006ae0
5391#define BNX2_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0)
5392#define BNX2_HC_COMP_PROD_TRIP_7_INT (0xffL<<16)
5393
5394#define BNX2_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4
5395#define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
5396#define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
5397
5398#define BNX2_HC_RX_TICKS_7 0x00006ae8
5399#define BNX2_HC_RX_TICKS_7_VALUE (0x3ffL<<0)
5400#define BNX2_HC_RX_TICKS_7_INT (0x3ffL<<16)
5401
5402#define BNX2_HC_TX_TICKS_7 0x00006aec
5403#define BNX2_HC_TX_TICKS_7_VALUE (0x3ffL<<0)
5404#define BNX2_HC_TX_TICKS_7_INT (0x3ffL<<16)
5405
5406#define BNX2_HC_COM_TICKS_7 0x00006af0
5407#define BNX2_HC_COM_TICKS_7_VALUE (0x3ffL<<0)
5408#define BNX2_HC_COM_TICKS_7_INT (0x3ffL<<16)
5409
5410#define BNX2_HC_CMD_TICKS_7 0x00006af4
5411#define BNX2_HC_CMD_TICKS_7_VALUE (0x3ffL<<0)
5412#define BNX2_HC_CMD_TICKS_7_INT (0x3ffL<<16)
5413
5414#define BNX2_HC_PERIODIC_TICKS_7 0x00006af8
5415#define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0)
5416#define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5417
5418#define BNX2_HC_SB_CONFIG_8 0x00006afc
5419#define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1)
5420#define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2)
5421#define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3)
5422#define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4)
5423#define BNX2_HC_SB_CONFIG_8_PER_MODE (1L<<16)
5424#define BNX2_HC_SB_CONFIG_8_ONE_SHOT (1L<<17)
5425#define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18)
5426#define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20)
5427
5428#define BNX2_HC_TX_QUICK_CONS_TRIP_8 0x00006b00
5429#define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
5430#define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
5431
5432#define BNX2_HC_COMP_PROD_TRIP_8 0x00006b04
5433#define BNX2_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0)
5434#define BNX2_HC_COMP_PROD_TRIP_8_INT (0xffL<<16)
5435
5436#define BNX2_HC_RX_QUICK_CONS_TRIP_8 0x00006b08
5437#define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
5438#define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
5439
5440#define BNX2_HC_RX_TICKS_8 0x00006b0c
5441#define BNX2_HC_RX_TICKS_8_VALUE (0x3ffL<<0)
5442#define BNX2_HC_RX_TICKS_8_INT (0x3ffL<<16)
5443
5444#define BNX2_HC_TX_TICKS_8 0x00006b10
5445#define BNX2_HC_TX_TICKS_8_VALUE (0x3ffL<<0)
5446#define BNX2_HC_TX_TICKS_8_INT (0x3ffL<<16)
5447
5448#define BNX2_HC_COM_TICKS_8 0x00006b14
5449#define BNX2_HC_COM_TICKS_8_VALUE (0x3ffL<<0)
5450#define BNX2_HC_COM_TICKS_8_INT (0x3ffL<<16)
5451
5452#define BNX2_HC_CMD_TICKS_8 0x00006b18
5453#define BNX2_HC_CMD_TICKS_8_VALUE (0x3ffL<<0)
5454#define BNX2_HC_CMD_TICKS_8_INT (0x3ffL<<16)
5455
5456#define BNX2_HC_PERIODIC_TICKS_8 0x00006b1c
5457#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
5458#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
3041 5459
3042 5460
3043/* 5461/*
@@ -3063,7 +5481,7 @@ struct l2_fhdr {
3063#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5481#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3064#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5482#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3065#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5483#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3066#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5484#define BNX2_TXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
3067#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 5485#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3068#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5486#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3069#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 5487#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
@@ -3111,7 +5529,7 @@ struct l2_fhdr {
3111#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 5529#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3112 5530
3113#define BNX2_TXP_CPU_REG_FILE 0x00045200 5531#define BNX2_TXP_CPU_REG_FILE 0x00045200
3114#define BNX2_TXP_FTQ_DATA 0x000453c0 5532#define BNX2_TXP_TXPQ 0x000453c0
3115#define BNX2_TXP_FTQ_CMD 0x000453f8 5533#define BNX2_TXP_FTQ_CMD 0x000453f8
3116#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 5534#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3117#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10) 5535#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
@@ -3158,7 +5576,7 @@ struct l2_fhdr {
3158#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5576#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3159#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5577#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3160#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5578#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3161#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 5579#define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED (1L<<6)
3162#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 5580#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3163#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5581#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3164#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 5582#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
@@ -3206,7 +5624,7 @@ struct l2_fhdr {
3206#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 5624#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3207 5625
3208#define BNX2_TPAT_CPU_REG_FILE 0x00085200 5626#define BNX2_TPAT_CPU_REG_FILE 0x00085200
3209#define BNX2_TPAT_FTQ_DATA 0x000853c0 5627#define BNX2_TPAT_TPATQ 0x000853c0
3210#define BNX2_TPAT_FTQ_CMD 0x000853f8 5628#define BNX2_TPAT_FTQ_CMD 0x000853f8
3211#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 5629#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3212#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10) 5630#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
@@ -3253,7 +5671,7 @@ struct l2_fhdr {
3253#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5671#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3254#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5672#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3255#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5673#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3256#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5674#define BNX2_RXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
3257#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 5675#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3258#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5676#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3259#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 5677#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
@@ -3301,7 +5719,29 @@ struct l2_fhdr {
3301#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 5719#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3302 5720
3303#define BNX2_RXP_CPU_REG_FILE 0x000c5200 5721#define BNX2_RXP_CPU_REG_FILE 0x000c5200
3304#define BNX2_RXP_CFTQ_DATA 0x000c5380 5722#define BNX2_RXP_PFE_PFE_CTL 0x000c537c
5723#define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
5724#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
5725#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
5726#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
5727#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
5728#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
5729#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
5730#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
5731#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
5732#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
5733#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
5734#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
5735#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
5736#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
5737#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
5738#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
5739#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
5740#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
5741#define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
5742#define BNX2_RXP_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
5743
5744#define BNX2_RXP_RXPCQ 0x000c5380
3305#define BNX2_RXP_CFTQ_CMD 0x000c53b8 5745#define BNX2_RXP_CFTQ_CMD 0x000c53b8
3306#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 5746#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3307#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10) 5747#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
@@ -3322,7 +5762,7 @@ struct l2_fhdr {
3322#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5762#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3323#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5763#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3324 5764
3325#define BNX2_RXP_FTQ_DATA 0x000c53c0 5765#define BNX2_RXP_RXPQ 0x000c53c0
3326#define BNX2_RXP_FTQ_CMD 0x000c53f8 5766#define BNX2_RXP_FTQ_CMD 0x000c53f8
3327#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 5767#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3328#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10) 5768#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
@@ -3350,6 +5790,10 @@ struct l2_fhdr {
3350 * com_reg definition 5790 * com_reg definition
3351 * offset: 0x100000 5791 * offset: 0x100000
3352 */ 5792 */
5793#define BNX2_COM_CKSUM_ERROR_STATUS 0x00100000
5794#define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
5795#define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
5796
3353#define BNX2_COM_CPU_MODE 0x00105000 5797#define BNX2_COM_CPU_MODE 0x00105000
3354#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0) 5798#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
3355#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1) 5799#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
@@ -3369,7 +5813,7 @@ struct l2_fhdr {
3369#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5813#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3370#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5814#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3371#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5815#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3372#define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 5816#define BNX2_COM_CPU_STATE_BAD_PC_HALTED (1L<<6)
3373#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 5817#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
3374#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5818#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3375#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10) 5819#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
@@ -3417,7 +5861,29 @@ struct l2_fhdr {
3417#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 5861#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3418 5862
3419#define BNX2_COM_CPU_REG_FILE 0x00105200 5863#define BNX2_COM_CPU_REG_FILE 0x00105200
3420#define BNX2_COM_COMXQ_FTQ_DATA 0x00105340 5864#define BNX2_COM_COMTQ_PFE_PFE_CTL 0x001052bc
5865#define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
5866#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
5867#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
5868#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
5869#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
5870#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
5871#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
5872#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
5873#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
5874#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
5875#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
5876#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
5877#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
5878#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
5879#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
5880#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
5881#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
5882#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
5883#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
5884#define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
5885
5886#define BNX2_COM_COMXQ 0x00105340
3421#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378 5887#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
3422#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5888#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3423#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 5889#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
@@ -3438,7 +5904,7 @@ struct l2_fhdr {
3438#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5904#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3439#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5905#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3440 5906
3441#define BNX2_COM_COMTQ_FTQ_DATA 0x00105380 5907#define BNX2_COM_COMTQ 0x00105380
3442#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8 5908#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
3443#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5909#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3444#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 5910#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
@@ -3459,7 +5925,7 @@ struct l2_fhdr {
3459#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5925#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3460#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5926#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3461 5927
3462#define BNX2_COM_COMQ_FTQ_DATA 0x001053c0 5928#define BNX2_COM_COMQ 0x001053c0
3463#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8 5929#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
3464#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5930#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3465#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 5931#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
@@ -3489,6 +5955,10 @@ struct l2_fhdr {
3489 * cp_reg definition 5955 * cp_reg definition
3490 * offset: 0x180000 5956 * offset: 0x180000
3491 */ 5957 */
5958#define BNX2_CP_CKSUM_ERROR_STATUS 0x00180000
5959#define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
5960#define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
5961
3492#define BNX2_CP_CPU_MODE 0x00185000 5962#define BNX2_CP_CPU_MODE 0x00185000
3493#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0) 5963#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
3494#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1) 5964#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
@@ -3508,7 +5978,7 @@ struct l2_fhdr {
3508#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5978#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3509#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5979#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3510#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5980#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3511#define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5981#define BNX2_CP_CPU_STATE_BAD_PC_HALTED (1L<<6)
3512#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 5982#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
3513#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5983#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3514#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10) 5984#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
@@ -3556,7 +6026,29 @@ struct l2_fhdr {
3556#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 6026#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3557 6027
3558#define BNX2_CP_CPU_REG_FILE 0x00185200 6028#define BNX2_CP_CPU_REG_FILE 0x00185200
3559#define BNX2_CP_CPQ_FTQ_DATA 0x001853c0 6029#define BNX2_CP_CPQ_PFE_PFE_CTL 0x001853bc
6030#define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
6031#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
6032#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6033#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
6034#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
6035#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
6036#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
6037#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
6038#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
6039#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
6040#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
6041#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
6042#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
6043#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
6044#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
6045#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
6046#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
6047#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
6048#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
6049#define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
6050
6051#define BNX2_CP_CPQ 0x001853c0
3560#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8 6052#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
3561#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 6053#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3562#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 6054#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
@@ -3584,6 +6076,59 @@ struct l2_fhdr {
3584 * mcp_reg definition 6076 * mcp_reg definition
3585 * offset: 0x140000 6077 * offset: 0x140000
3586 */ 6078 */
6079#define BNX2_MCP_MCP_CONTROL 0x00140080
6080#define BNX2_MCP_MCP_CONTROL_SMBUS_SEL (1L<<30)
6081#define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE (1L<<31)
6082
6083#define BNX2_MCP_MCP_ATTENTION_STATUS 0x00140084
6084#define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL (1L<<29)
6085#define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1L<<30)
6086#define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT (1L<<31)
6087
6088#define BNX2_MCP_MCP_HEARTBEAT_CONTROL 0x00140088
6089#define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1L<<31)
6090
6091#define BNX2_MCP_MCP_HEARTBEAT_STATUS 0x0014008c
6092#define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffL<<0)
6093#define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID (1L<<31)
6094
6095#define BNX2_MCP_MCP_HEARTBEAT 0x00140090
6096#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffL<<0)
6097#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1L<<30)
6098#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1L<<31)
6099
6100#define BNX2_MCP_WATCHDOG_RESET 0x00140094
6101#define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET (1L<<31)
6102
6103#define BNX2_MCP_WATCHDOG_CONTROL 0x00140098
6104#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffL<<0)
6105#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN (1L<<29)
6106#define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE (1L<<30)
6107#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1L<<31)
6108
6109#define BNX2_MCP_ACCESS_LOCK 0x0014009c
6110#define BNX2_MCP_ACCESS_LOCK_LOCK (1L<<31)
6111
6112#define BNX2_MCP_TOE_ID 0x001400a0
6113#define BNX2_MCP_TOE_ID_FUNCTION_ID (1L<<31)
6114
6115#define BNX2_MCP_MAILBOX_CFG 0x001400a4
6116#define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffL<<0)
6117#define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE (0xfffL<<20)
6118
6119#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC 0x001400a8
6120#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffL<<0)
6121#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffL<<20)
6122
6123#define BNX2_MCP_MCP_DOORBELL 0x001400ac
6124#define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL (1L<<31)
6125
6126#define BNX2_MCP_DRIVER_DOORBELL 0x001400b0
6127#define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL (1L<<31)
6128
6129#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC 0x001400b4
6130#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1L<<31)
6131
3587#define BNX2_MCP_CPU_MODE 0x00145000 6132#define BNX2_MCP_CPU_MODE 0x00145000
3588#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0) 6133#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
3589#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1) 6134#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
@@ -3603,7 +6148,7 @@ struct l2_fhdr {
3603#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 6148#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3604#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 6149#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3605#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 6150#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3606#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 6151#define BNX2_MCP_CPU_STATE_BAD_PC_HALTED (1L<<6)
3607#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 6152#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
3608#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 6153#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3609#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 6154#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
@@ -3651,7 +6196,7 @@ struct l2_fhdr {
3651#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 6196#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3652 6197
3653#define BNX2_MCP_CPU_REG_FILE 0x00145200 6198#define BNX2_MCP_CPU_REG_FILE 0x00145200
3654#define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0 6199#define BNX2_MCP_MCPQ 0x001453c0
3655#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8 6200#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
3656#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 6201#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3657#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 6202#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
@@ -3696,6 +6241,8 @@ struct l2_fhdr {
3696 6241
3697/* 5708 Serdes PHY registers */ 6242/* 5708 Serdes PHY registers */
3698 6243
6244#define BCM5708S_BMCR_FORCE_2500 0x20
6245
3699#define BCM5708S_UP1 0xb 6246#define BCM5708S_UP1 0xb
3700 6247
3701#define BCM5708S_UP1_2G5 0x1 6248#define BCM5708S_UP1_2G5 0x1
@@ -3804,6 +6351,7 @@ struct l2_fhdr {
3804#define INVALID_CID_ADDR 0xffffffff 6351#define INVALID_CID_ADDR 0xffffffff
3805 6352
3806#define TX_CID 16 6353#define TX_CID 16
6354#define TX_TSS_CID 32
3807#define RX_CID 0 6355#define RX_CID 0
3808 6356
3809#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 6357#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
@@ -3889,6 +6437,8 @@ struct bnx2 {
3889 6437
3890 u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES))); 6438 u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
3891 u16 tx_prod; 6439 u16 tx_prod;
6440 u32 tx_bidx_addr;
6441 u32 tx_bseq_addr;
3892 6442
3893 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES))); 6443 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
3894 u16 hw_tx_cons; 6444 u16 hw_tx_cons;
@@ -3945,6 +6495,7 @@ struct bnx2 {
3945#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 6495#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
3946#define CHIP_NUM_5706 0x57060000 6496#define CHIP_NUM_5706 0x57060000
3947#define CHIP_NUM_5708 0x57080000 6497#define CHIP_NUM_5708 0x57080000
6498#define CHIP_NUM_5709 0x57090000
3948 6499
3949#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) 6500#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
3950#define CHIP_REV_Ax 0x00000000 6501#define CHIP_REV_Ax 0x00000000
@@ -4007,6 +6558,10 @@ struct bnx2 {
4007 struct statistics_block *stats_blk; 6558 struct statistics_block *stats_blk;
4008 dma_addr_t stats_blk_mapping; 6559 dma_addr_t stats_blk_mapping;
4009 6560
6561 int ctx_pages;
6562 void *ctx_blk[4];
6563 dma_addr_t ctx_blk_mapping[4];
6564
4010 u32 hc_cmd; 6565 u32 hc_cmd;
4011 u32 rx_mode; 6566 u32 rx_mode;
4012 6567
@@ -4038,6 +6593,7 @@ struct bnx2 {
4038 6593
4039 u8 serdes_an_pending; 6594 u8 serdes_an_pending;
4040#define SERDES_AN_TIMEOUT (HZ / 3) 6595#define SERDES_AN_TIMEOUT (HZ / 3)
6596#define SERDES_FORCED_TIMEOUT (HZ / 10)
4041 6597
4042 u8 mac_addr[8]; 6598 u8 mac_addr[8];
4043 6599
@@ -4104,41 +6660,43 @@ struct cpu_reg {
4104}; 6660};
4105 6661
4106struct fw_info { 6662struct fw_info {
4107 u32 ver_major; 6663 const u32 ver_major;
4108 u32 ver_minor; 6664 const u32 ver_minor;
4109 u32 ver_fix; 6665 const u32 ver_fix;
4110 6666
4111 u32 start_addr; 6667 const u32 start_addr;
4112 6668
4113 /* Text section. */ 6669 /* Text section. */
4114 u32 text_addr; 6670 const u32 text_addr;
4115 u32 text_len; 6671 const u32 text_len;
4116 u32 text_index; 6672 const u32 text_index;
4117 u32 *text; 6673 u32 *text;
6674 u8 *gz_text;
6675 const u32 gz_text_len;
4118 6676
4119 /* Data section. */ 6677 /* Data section. */
4120 u32 data_addr; 6678 const u32 data_addr;
4121 u32 data_len; 6679 const u32 data_len;
4122 u32 data_index; 6680 const u32 data_index;
4123 u32 *data; 6681 const u32 *data;
4124 6682
4125 /* SBSS section. */ 6683 /* SBSS section. */
4126 u32 sbss_addr; 6684 const u32 sbss_addr;
4127 u32 sbss_len; 6685 const u32 sbss_len;
4128 u32 sbss_index; 6686 const u32 sbss_index;
4129 u32 *sbss; 6687 const u32 *sbss;
4130 6688
4131 /* BSS section. */ 6689 /* BSS section. */
4132 u32 bss_addr; 6690 const u32 bss_addr;
4133 u32 bss_len; 6691 const u32 bss_len;
4134 u32 bss_index; 6692 const u32 bss_index;
4135 u32 *bss; 6693 const u32 *bss;
4136 6694
4137 /* Read-only section. */ 6695 /* Read-only section. */
4138 u32 rodata_addr; 6696 const u32 rodata_addr;
4139 u32 rodata_len; 6697 const u32 rodata_len;
4140 u32 rodata_index; 6698 const u32 rodata_index;
4141 u32 *rodata; 6699 const u32 *rodata;
4142}; 6700};
4143 6701
4144#define RV2P_PROC1 0 6702#define RV2P_PROC1 0
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h
index 2d753dca0d75..21d368ff424d 100644
--- a/drivers/net/bnx2_fw.h
+++ b/drivers/net/bnx2_fw.h
@@ -14,20 +14,6 @@
14 * accompanying it. 14 * accompanying it.
15 */ 15 */
16 16
17static const int bnx2_COM_b06FwReleaseMajor = 0x1;
18static const int bnx2_COM_b06FwReleaseMinor = 0x0;
19static const int bnx2_COM_b06FwReleaseFix = 0x0;
20static const u32 bnx2_COM_b06FwStartAddr = 0x080008b4;
21static const u32 bnx2_COM_b06FwTextAddr = 0x08000000;
22static const int bnx2_COM_b06FwTextLen = 0x57bc;
23static const u32 bnx2_COM_b06FwDataAddr = 0x08005840;
24static const int bnx2_COM_b06FwDataLen = 0x0;
25static const u32 bnx2_COM_b06FwRodataAddr = 0x080057c0;
26static const int bnx2_COM_b06FwRodataLen = 0x58;
27static const u32 bnx2_COM_b06FwBssAddr = 0x08005860;
28static const int bnx2_COM_b06FwBssLen = 0x88;
29static const u32 bnx2_COM_b06FwSbssAddr = 0x08005840;
30static const int bnx2_COM_b06FwSbssLen = 0x1c;
31static u8 bnx2_COM_b06FwText[] = { 17static u8 bnx2_COM_b06FwText[] = {
32 0x1f, 0x8b, 0x08, 0x08, 0x09, 0x83, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, 18 0x1f, 0x8b, 0x08, 0x08, 0x09, 0x83, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
33 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5b, 0x7d, 0x6c, 19 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5b, 0x7d, 0x6c,
@@ -673,389 +659,752 @@ static u32 bnx2_COM_b06FwRodata[(0x58/4) + 1] = {
673static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 }; 659static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 };
674static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; 660static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
675 661
676static int bnx2_RXP_b06FwReleaseMajor = 0x1; 662static struct fw_info bnx2_com_fw_06 = {
677static int bnx2_RXP_b06FwReleaseMinor = 0x0; 663 .ver_major = 0x1,
678static int bnx2_RXP_b06FwReleaseFix = 0x0; 664 .ver_minor = 0x0,
679static u32 bnx2_RXP_b06FwStartAddr = 0x08003184; 665 .ver_fix = 0x0,
680static u32 bnx2_RXP_b06FwTextAddr = 0x08000000; 666
681static int bnx2_RXP_b06FwTextLen = 0x588c; 667 .start_addr = 0x080008b4,
682static u32 bnx2_RXP_b06FwDataAddr = 0x080058e0; 668
683static int bnx2_RXP_b06FwDataLen = 0x0; 669 .text_addr = 0x08000000,
684static u32 bnx2_RXP_b06FwRodataAddr = 0x08005890; 670 .text_len = 0x57bc,
685static int bnx2_RXP_b06FwRodataLen = 0x28; 671 .text_index = 0x0,
686static u32 bnx2_RXP_b06FwBssAddr = 0x08005900; 672 .gz_text = bnx2_COM_b06FwText,
687static int bnx2_RXP_b06FwBssLen = 0x13a4; 673 .gz_text_len = sizeof(bnx2_COM_b06FwText),
688static u32 bnx2_RXP_b06FwSbssAddr = 0x080058e0; 674
689static int bnx2_RXP_b06FwSbssLen = 0x1c; 675 .data_addr = 0x08005840,
676 .data_len = 0x0,
677 .data_index = 0x0,
678 .data = bnx2_COM_b06FwData,
679
680 .sbss_addr = 0x08005840,
681 .sbss_len = 0x1c,
682 .sbss_index = 0x0,
683 .sbss = bnx2_COM_b06FwSbss,
684
685 .bss_addr = 0x08005860,
686 .bss_len = 0x88,
687 .bss_index = 0x0,
688 .bss = bnx2_COM_b06FwBss,
689
690 .rodata_addr = 0x080057c0,
691 .rodata_len = 0x58,
692 .rodata_index = 0x0,
693 .rodata = bnx2_COM_b06FwRodata,
694};
695
690static u8 bnx2_RXP_b06FwText[] = { 696static u8 bnx2_RXP_b06FwText[] = {
691 0x1f, 0x8b, 0x08, 0x08, 0x07, 0x87, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, 697 0x1f, 0x8b, 0x08, 0x08, 0xcb, 0xa3, 0x46, 0x45, 0x00, 0x03, 0x74, 0x65,
692 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x5d, 0x6c, 698 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5c, 0x6f, 0x6c,
693 0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x43, 0x71, 0x49, 0x91, 0xd4, 0x70, 0xb9, 699 0x1c, 0xc7, 0x75, 0x7f, 0x3b, 0xbb, 0xa4, 0x4e, 0xd4, 0x91, 0x5c, 0x1e,
694 0x62, 0x57, 0x12, 0x65, 0xed, 0x8a, 0x43, 0x71, 0x6d, 0x31, 0xce, 0x50, 700 0x4f, 0xf4, 0x49, 0x66, 0x94, 0x5d, 0x71, 0x25, 0x5e, 0x2d, 0xc6, 0x5d,
695 0x58, 0xdb, 0x82, 0xb1, 0x48, 0xc7, 0xb3, 0xa4, 0xc8, 0x24, 0x02, 0x42, 701 0x31, 0x57, 0x9b, 0x08, 0xce, 0xf1, 0x79, 0xef, 0x64, 0xb1, 0x86, 0x0a,
696 0x1b, 0x42, 0xab, 0xa4, 0xa9, 0xc1, 0x90, 0x72, 0x91, 0x22, 0x2c, 0xa0, 702 0x51, 0x0d, 0x1d, 0x1b, 0x85, 0x6b, 0xb0, 0x47, 0x39, 0xae, 0xdb, 0x7e,
697 0x1a, 0x79, 0xf0, 0x43, 0x10, 0x2f, 0x56, 0x3f, 0xa6, 0xd1, 0x8d, 0x96, 703 0x90, 0x65, 0x1b, 0x30, 0xda, 0x10, 0xbe, 0x1c, 0xe9, 0x46, 0x75, 0x2f,
698 0xb6, 0x1c, 0x53, 0x08, 0x82, 0x82, 0xe5, 0x52, 0x52, 0x0b, 0x2c, 0xb4, 704 0xdc, 0x8b, 0xc4, 0x98, 0x06, 0xfa, 0x07, 0x57, 0x92, 0xfa, 0x83, 0xe0,
699 0x96, 0xed, 0x36, 0x7e, 0xa8, 0x23, 0x9a, 0x92, 0x8d, 0xa6, 0x68, 0x81, 705 0xa0, 0x93, 0xe2, 0x26, 0xf5, 0x17, 0x57, 0x84, 0x2a, 0xc7, 0xf9, 0xe0,
700 0x22, 0xad, 0xd1, 0xf4, 0x4d, 0x95, 0x9a, 0x4a, 0x75, 0x5f, 0xd4, 0xa2, 706 0x02, 0x4e, 0x63, 0x20, 0x06, 0xea, 0x16, 0xaa, 0xec, 0xd8, 0x46, 0x81,
701 0x48, 0xda, 0x46, 0xcd, 0xf4, 0xfb, 0xee, 0xcc, 0x88, 0xd4, 0x9a, 0xb2, 707 0xa2, 0x42, 0x1c, 0xd8, 0x46, 0xfc, 0x67, 0xfb, 0x7b, 0x33, 0xbb, 0xd4,
702 0x2c, 0x3b, 0x0d, 0x62, 0x74, 0x0e, 0x30, 0xd8, 0xb9, 0x7f, 0xe7, 0xef, 708 0x91, 0x96, 0x6d, 0xa0, 0x1f, 0xfa, 0xa5, 0x3b, 0xc0, 0x61, 0x67, 0x66,
703 0x9e, 0x73, 0xee, 0x39, 0x77, 0x28, 0x7d, 0xa5, 0x43, 0xda, 0x25, 0x84, 709 0xe7, 0xbd, 0x79, 0xf3, 0xfe, 0xbf, 0x59, 0x4a, 0x7f, 0x90, 0xa4, 0x2e,
704 0x4e, 0x3c, 0x99, 0xc3, 0xcf, 0x3c, 0xfd, 0xe0, 0xc3, 0x0f, 0xee, 0xc1, 710 0x0a, 0x5b, 0x37, 0x7e, 0xd6, 0x91, 0xc7, 0x8f, 0xde, 0x3c, 0x76, 0xf3,
705 0xeb, 0xb0, 0xa1, 0x6d, 0xd0, 0xa3, 0xfe, 0x18, 0x62, 0x88, 0x21, 0x86, 711 0x28, 0xd1, 0x97, 0x47, 0xf5, 0x1b, 0x12, 0x22, 0x9a, 0x8f, 0x5b, 0xdc,
706 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 712 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2,
707 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 713 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16,
708 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 714 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7,
709 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 715 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8,
710 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0xff, 0xef, 0x60, 0x88, 0x58, 716 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5,
711 0xfc, 0xed, 0x0c, 0x1f, 0x49, 0xe8, 0x85, 0xcb, 0x07, 0x3d, 0x5b, 0x12, 717 0x2d, 0x6e, 0x71, 0xfb, 0xff, 0xde, 0x74, 0x22, 0x93, 0x9f, 0xdd, 0xe1,
712 0x46, 0x61, 0x69, 0x66, 0xda, 0x16, 0x71, 0xeb, 0xbb, 0x33, 0x45, 0xf9, 718 0x8f, 0x12, 0x22, 0xbf, 0xfa, 0x90, 0xe7, 0x50, 0x42, 0xcf, 0xbf, 0x34,
713 0x1f, 0xbf, 0x94, 0x32, 0x85, 0xfd, 0xdb, 0x0b, 0x37, 0x9f, 0x7d, 0xf3, 719 0x33, 0xed, 0x10, 0x15, 0x9a, 0x7b, 0xac, 0x22, 0x7d, 0x14, 0x54, 0xd2,
714 0x91, 0xec, 0x8d, 0x05, 0x43, 0x12, 0x56, 0xe1, 0xe8, 0xb0, 0xb5, 0x4b, 720 0x06, 0xf1, 0xfc, 0x17, 0xf2, 0x1f, 0x3e, 0xf1, 0xfc, 0xad, 0xf6, 0xd5,
715 0x12, 0x7d, 0x58, 0xf3, 0xdd, 0xc1, 0xcf, 0x59, 0xd2, 0x15, 0xe1, 0xba, 721 0x86, 0x4e, 0x09, 0x33, 0x3f, 0xb7, 0xd7, 0xdc, 0x4d, 0x89, 0x41, 0xc0,
716 0xee, 0xbf, 0x39, 0x68, 0xc9, 0x2b, 0x8d, 0x94, 0x5c, 0x68, 0x6c, 0xdf, 722 0xfc, 0xf5, 0xf0, 0x7f, 0xf4, 0x50, 0x0f, 0x5d, 0xc3, 0xe3, 0x24, 0xe8,
717 0x24, 0x5d, 0xd9, 0x52, 0x09, 0xfd, 0x6e, 0x8a, 0xe3, 0x96, 0x94, 0xab, 723 0xb2, 0xfe, 0x9c, 0xe6, 0xb5, 0x82, 0xe0, 0xa4, 0x1b, 0x04, 0x3f, 0xc6,
718 0x2d, 0xe2, 0x2a, 0xba, 0x7d, 0x5a, 0x71, 0xfe, 0x3e, 0xcd, 0x9b, 0x7f, 724 0xef, 0x2d, 0x17, 0x63, 0xff, 0xe3, 0xa0, 0x60, 0xe8, 0x24, 0x9c, 0xbf,
719 0x9e, 0xff, 0x1e, 0x24, 0xa5, 0xcb, 0x7d, 0x68, 0xf7, 0xa1, 0xcd, 0xf7, 725 0xd4, 0xbc, 0xe5, 0x2e, 0xaa, 0x2e, 0x1a, 0x34, 0xeb, 0xa7, 0xe9, 0x98,
720 0x81, 0xf4, 0x94, 0x98, 0x72, 0xa4, 0x91, 0x90, 0xa3, 0xd5, 0x8c, 0xe8, 726 0x5f, 0xd1, 0x4a, 0xad, 0x9a, 0xb6, 0xef, 0xf4, 0xbc, 0x76, 0xe7, 0xe9,
721 0x05, 0x71, 0xbd, 0xbc, 0x9d, 0x2e, 0xa3, 0x6f, 0xea, 0x00, 0xdb, 0x29, 727 0x63, 0xda, 0xfe, 0xd3, 0x75, 0xcd, 0x3b, 0x4d, 0x15, 0xb1, 0x37, 0x49,
722 0xe0, 0xf9, 0x0e, 0xd7, 0x59, 0x5e, 0x5e, 0x4a, 0xb7, 0xc6, 0x14, 0x0d, 728 0x05, 0xf3, 0x8c, 0x56, 0x6c, 0x0d, 0x68, 0xde, 0x89, 0x0f, 0xc9, 0x73,
723 0x8e, 0xb1, 0x0f, 0xbf, 0x58, 0x5f, 0xae, 0x76, 0x00, 0x6f, 0xd6, 0x71, 729 0x6d, 0xf3, 0xf7, 0xc8, 0x28, 0x80, 0x16, 0xf2, 0x6a, 0x41, 0xe0, 0xb9,
724 0x41, 0xdc, 0x73, 0x2c, 0xd0, 0xf6, 0xfd, 0xdf, 0x75, 0x32, 0xb2, 0xe2, 730 0x06, 0x15, 0xd2, 0x41, 0x20, 0xf2, 0xc1, 0x13, 0x5e, 0xce, 0x31, 0x85,
725 0x74, 0x81, 0xa7, 0x16, 0x69, 0xb5, 0xc5, 0xd2, 0x0b, 0xb6, 0xb5, 0x22, 731 0x96, 0xa6, 0x6a, 0x6b, 0x00, 0x78, 0x93, 0x5a, 0x71, 0xd1, 0xd0, 0x4a,
726 0x6d, 0x1c, 0xeb, 0x34, 0x0a, 0xbe, 0x3f, 0x9d, 0x97, 0xae, 0xa0, 0x6f, 732 0x7e, 0x70, 0xc1, 0x73, 0x69, 0x50, 0xa7, 0x20, 0x98, 0x73, 0x77, 0x65,
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877 0x5d, 0x97, 0xd7, 0x7d, 0xf7, 0x00, 0xe5, 0x89, 0x72, 0x8b, 0x39, 0x9f, 883 0x24, 0x65, 0xb0, 0x4e, 0x9e, 0x94, 0x30, 0xf2, 0xf5, 0x99, 0x39, 0x87,
878 0xb1, 0xd8, 0x28, 0xcc, 0xc0, 0x8e, 0xbf, 0x2a, 0xdf, 0x6f, 0x1c, 0x92, 884 0xe5, 0x0a, 0xff, 0x56, 0x8b, 0xe4, 0xca, 0x32, 0xea, 0xa4, 0x6a, 0xfd,
879 0xef, 0x35, 0x26, 0xe5, 0xcf, 0x1a, 0x5f, 0x96, 0x3f, 0x6d, 0x1c, 0x94, 885 0x29, 0xc8, 0x55, 0x84, 0xf5, 0x01, 0xec, 0x7b, 0x81, 0xe5, 0x8b, 0xba,
880 0xd7, 0x1b, 0x07, 0xe4, 0xb5, 0xc6, 0x84, 0xbc, 0xda, 0xd8, 0x0f, 0x1b, 886 0xb1, 0x8e, 0xbc, 0xa7, 0x4e, 0x29, 0x55, 0xdf, 0x1c, 0x47, 0x5d, 0x00,
881 0x1f, 0x87, 0x8d, 0x9f, 0x9a, 0x99, 0xac, 0xf7, 0xcb, 0xd4, 0x49, 0xc4, 887 0xf9, 0xd5, 0x16, 0x80, 0x03, 0x36, 0x5a, 0x5b, 0xc1, 0x13, 0xb5, 0x48,
882 0x20, 0xe7, 0x1b, 0xba, 0xba, 0xe3, 0xb3, 0xe9, 0xe7, 0x2d, 0x32, 0xad, 888 0xed, 0x0c, 0x9e, 0x83, 0x78, 0x36, 0x59, 0x37, 0xc3, 0x3c, 0xe3, 0x13,
883 0xee, 0xaf, 0x34, 0xe4, 0x89, 0x2d, 0xbc, 0x2b, 0x7c, 0xc5, 0x33, 0x2e, 889 0xf4, 0xc0, 0x9e, 0x4a, 0x6c, 0x4f, 0xf4, 0x8f, 0xad, 0x3c, 0xfd, 0x43,
884 0x87, 0xf1, 0xe8, 0xe1, 0x94, 0xb4, 0x03, 0xbf, 0xca, 0x4b, 0x4d, 0x9e, 890 0x6b, 0x8c, 0x7e, 0xd4, 0xca, 0xd1, 0x0f, 0x5b, 0x2e, 0xfd, 0x7d, 0x6b,
885 0xdb, 0x62, 0x86, 0xf7, 0x9c, 0x87, 0x24, 0xc9, 0xfb, 0xb0, 0x9c, 0x67, 891 0x84, 0x9e, 0x6d, 0x65, 0xb9, 0x96, 0x43, 0xce, 0x64, 0x71, 0xce, 0x44,
886 0xa0, 0xde, 0x5e, 0xd7, 0x27, 0x73, 0xb4, 0x65, 0xe8, 0xc6, 0x95, 0x43, 892 0x0f, 0xfa, 0xb7, 0xc3, 0xde, 0x59, 0xfe, 0xe7, 0x66, 0x0a, 0xcd, 0x21,
887 0xb0, 0x53, 0xc3, 0x7e, 0xcb, 0xa5, 0x1e, 0x16, 0x97, 0x28, 0xf7, 0x46, 893 0x2a, 0x9f, 0x80, 0x6f, 0x76, 0x6f, 0xe3, 0x1a, 0x94, 0x1e, 0x73, 0xb9,
888 0x59, 0x5c, 0xa0, 0x6f, 0xff, 0x1b, 0x64, 0x6c, 0x97, 0xda, 0x82, 0x89, 894 0x86, 0xe8, 0xe0, 0xf7, 0xa8, 0x23, 0xe0, 0xbb, 0xe1, 0xcb, 0xa6, 0xd2,
889 0xb9, 0x6e, 0x98, 0xab, 0x6c, 0xa7, 0x3d, 0x00, 0x1f, 0xf1, 0x7e, 0x10, 895 0xf6, 0x39, 0x4f, 0x1f, 0x08, 0x7d, 0xc0, 0x5d, 0x29, 0xea, 0xc2, 0x5e,
890 0x4e, 0xab, 0x09, 0x27, 0xf1, 0x24, 0x54, 0x0c, 0x08, 0x70, 0x5b, 0x52, 896 0xf0, 0x7f, 0x17, 0x9f, 0x86, 0x0d, 0xc8, 0x1a, 0x28, 0x01, 0x5f, 0xc3,
891 0x5b, 0x4a, 0xca, 0xc2, 0x42, 0x0f, 0x9e, 0x94, 0x2c, 0xd4, 0x6d, 0x3c, 897 0x79, 0x80, 0xc1, 0x76, 0xcc, 0xf5, 0x87, 0xe5, 0xe9, 0x5c, 0x17, 0xb2,
892 0x39, 0x3c, 0x43, 0x78, 0xd2, 0xb0, 0x53, 0xca, 0xc8, 0xd8, 0x12, 0xc9, 898 0x3d, 0xeb, 0x08, 0x1a, 0x0c, 0x37, 0x69, 0xb2, 0xdc, 0x0c, 0x87, 0x7d,
893 0x88, 0x78, 0x5c, 0xed, 0x0d, 0x6b, 0x2a, 0xf2, 0xa3, 0x85, 0xfc, 0x74, 899 0x6a, 0x21, 0xf4, 0x6f, 0x89, 0x50, 0x2f, 0x4d, 0xcc, 0x3f, 0x15, 0xfa,
894 0x87, 0x7d, 0x1d, 0x52, 0xab, 0x38, 0x32, 0x55, 0xfd, 0x94, 0x3e, 0xa5, 900 0xe3, 0x8d, 0xfb, 0x20, 0x56, 0x20, 0x97, 0x54, 0xeb, 0x18, 0x56, 0x0b,
895 0x74, 0x07, 0xfc, 0x95, 0x21, 0xb4, 0xef, 0x0f, 0xdb, 0x8f, 0xca, 0xf4, 901 0x61, 0xfb, 0xc3, 0xb9, 0x24, 0xf8, 0xed, 0x52, 0xd9, 0x7f, 0x43, 0xe3,
896 0xbc, 0xc8, 0xca, 0xcb, 0x03, 0x7a, 0x51, 0xb5, 0xf7, 0xa2, 0xad, 0xa3, 902 0x1c, 0x5b, 0x38, 0xcc, 0xff, 0x11, 0x8c, 0x2f, 0x87, 0xe3, 0xaf, 0xd0,
897 0x9d, 0x0d, 0xdb, 0xcc, 0x8f, 0x0e, 0xe0, 0x71, 0xd5, 0xf3, 0xf5, 0xea, 903 0xf4, 0x22, 0x81, 0xd6, 0xd7, 0xb4, 0xa2, 0x1c, 0x8f, 0x61, 0x2c, 0x30,
898 0xb8, 0x3c, 0x55, 0xed, 0x77, 0x5e, 0x87, 0xcd, 0xbd, 0x65, 0x46, 0xf7, 904 0xd6, 0xb9, 0x6e, 0xe0, 0x0c, 0x23, 0xc5, 0xba, 0x2e, 0x9c, 0x71, 0xf0,
899 0xd2, 0x04, 0x24, 0x79, 0xf6, 0x56, 0x75, 0xf7, 0xf1, 0x04, 0xe2, 0xad, 905 0x71, 0x12, 0xbf, 0x82, 0xfc, 0x3d, 0xe2, 0x0f, 0x15, 0xde, 0x41, 0xbc,
900 0x9b, 0x34, 0xe5, 0x6f, 0x4f, 0x64, 0xad, 0xa7, 0xf5, 0x5c, 0x52, 0xda, 906 0xd0, 0x3a, 0xa2, 0xdc, 0x67, 0x3b, 0x6a, 0xcf, 0x20, 0x38, 0x84, 0x5a,
901 0x7d, 0xff, 0x71, 0x3b, 0x3b, 0x3b, 0xa9, 0x77, 0xca, 0xdf, 0xbf, 0x98, 907 0xdd, 0x4a, 0x19, 0xf4, 0x2f, 0xf3, 0xb6, 0x79, 0x48, 0xcc, 0xe1, 0x4c,
902 0x91, 0x85, 0xb3, 0x5b, 0x65, 0xa1, 0x06, 0x99, 0x1a, 0xbf, 0x8e, 0x7d, 908 0x41, 0x30, 0xe1, 0xd8, 0x95, 0x82, 0xe8, 0xa6, 0x9f, 0x1f, 0xe7, 0xb8,
903 0x35, 0xe5, 0xea, 0x9e, 0x47, 0xb1, 0x27, 0x8c, 0x5d, 0x49, 0xe4, 0x6c, 909 0x5b, 0x9f, 0x79, 0x01, 0xba, 0xd7, 0x58, 0xe9, 0xa4, 0x46, 0xc3, 0xa0,
904 0x1b, 0xc4, 0xec, 0x25, 0x5d, 0x49, 0x98, 0x85, 0x9c, 0x1c, 0x81, 0xdf, 910 0x2b, 0xa3, 0x43, 0xa0, 0xd3, 0xa4, 0x46, 0x33, 0x85, 0x5c, 0x6e, 0x33,
905 0x4f, 0xdb, 0xb9, 0x1e, 0x69, 0xc7, 0x7b, 0x7d, 0x04, 0x7c, 0x5b, 0x32, 911 0xa1, 0x3c, 0x94, 0x0e, 0x43, 0xcf, 0x67, 0xa5, 0x8f, 0xf6, 0x1c, 0x3c,
906 0xd5, 0x6b, 0xc9, 0x99, 0xc1, 0x68, 0xff, 0xb6, 0x62, 0x6e, 0x46, 0x16, 912 0x9b, 0x1f, 0xf4, 0xae, 0x3f, 0x73, 0x09, 0xf4, 0xf7, 0xa0, 0x0a, 0xd9,
907 0xcf, 0x66, 0xf0, 0x9b, 0x83, 0xfd, 0xec, 0x94, 0x57, 0x6a, 0xfd, 0xb2, 913 0x2e, 0xe5, 0x5c, 0xf6, 0x87, 0x4c, 0x4f, 0x20, 0x6e, 0x19, 0x43, 0xe6,
908 0x54, 0xdb, 0x2a, 0x8b, 0xb5, 0xe6, 0x7d, 0xe8, 0xec, 0x09, 0xe2, 0x1d, 914 0x7e, 0xf1, 0xab, 0xe0, 0x0e, 0x83, 0x65, 0xf7, 0xaa, 0xac, 0x77, 0x64,
909 0xf1, 0xf4, 0x5b, 0x53, 0xfa, 0x56, 0x71, 0xcd, 0x7e, 0xeb, 0x29, 0xfd, 915 0x9c, 0xc3, 0x7e, 0x4b, 0x2b, 0xaf, 0x81, 0x16, 0x93, 0x9e, 0x6d, 0x6e,
910 0x1f, 0xe4, 0x31, 0x33, 0xa0, 0xa9, 0x17, 0x7e, 0xa4, 0xee, 0x84, 0x26, 916 0x0f, 0xc7, 0x96, 0xe4, 0xc5, 0xb3, 0xcd, 0x2e, 0xfa, 0x61, 0x63, 0x0b,
911 0x79, 0xf6, 0x2a, 0xbc, 0x4f, 0x26, 0x49, 0xfb, 0xf5, 0xc6, 0x07, 0xd1, 917 0x2d, 0x37, 0xf8, 0x7d, 0x27, 0x2d, 0x35, 0x86, 0xae, 0x1e, 0x15, 0x03,
912 0x59, 0xcb, 0xcf, 0x9d, 0x68, 0x52, 0x06, 0xe2, 0xec, 0xbf, 0x71, 0x52, 918 0xb4, 0x7a, 0xe3, 0x4d, 0xe6, 0x57, 0x05, 0xf2, 0x82, 0xc9, 0x8f, 0xe9,
913 0xef, 0x95, 0xe5, 0x6d, 0x0f, 0x58, 0x4f, 0xea, 0xad, 0x88, 0x01, 0x3f, 919 0xbd, 0xd1, 0x5e, 0xfa, 0xe9, 0x3d, 0x76, 0xfd, 0x7e, 0x01, 0x1b, 0x18,
914 0x97, 0x9f, 0xee, 0xd9, 0x24, 0x3f, 0xfc, 0xcd, 0xec, 0xa9, 0x6f, 0x22, 920 0x4d, 0xb2, 0x6d, 0xa3, 0xcf, 0xf3, 0xf6, 0x55, 0x4b, 0xb0, 0x6e, 0xff,
915 0xd9, 0xbf, 0xb2, 0xa7, 0x83, 0x71, 0x01, 0xef, 0xec, 0xcf, 0xde, 0x70, 921 0x04, 0x3c, 0xb5, 0x8f, 0x29, 0x3b, 0x60, 0xdc, 0x8c, 0x17, 0xba, 0xe1,
916 0x75, 0xea, 0xe1, 0x2f, 0xa0, 0x87, 0xec, 0x9c, 0xba, 0x9b, 0x56, 0x3c, 922 0xbc, 0x08, 0x9c, 0x78, 0xd7, 0x1c, 0x02, 0xae, 0x17, 0x25, 0x2f, 0x0e,
917 0x90, 0x3e, 0xf5, 0x52, 0x06, 0x6f, 0x18, 0xab, 0xf7, 0x03, 0x57, 0x59, 923 0xb9, 0xf6, 0x55, 0x42, 0x0e, 0x79, 0xc5, 0x19, 0xca, 0x0a, 0xb1, 0x9d,
918 0xe9, 0xf9, 0x09, 0x27, 0x7b, 0x03, 0xe9, 0xb0, 0xbf, 0x68, 0xf7, 0xa7, 924 0x1a, 0x99, 0x9b, 0xcc, 0xf3, 0xf0, 0xff, 0xa8, 0xab, 0x2a, 0x97, 0xa9,
919 0x77, 0xea, 0x3b, 0x64, 0x32, 0xfd, 0x80, 0xf5, 0xb4, 0x6c, 0x21, 0xce, 925 0x3e, 0x73, 0xc9, 0x61, 0xfd, 0x67, 0xbf, 0xf1, 0x12, 0xf2, 0x4e, 0x93,
920 0xd9, 0x05, 0xc1, 0xda, 0x79, 0xe2, 0xfb, 0x2b, 0xe0, 0x0b, 0x70, 0x28, 926 0x4e, 0x34, 0xd9, 0x5f, 0x32, 0x2e, 0xce, 0xfd, 0x77, 0x9b, 0x5f, 0x13,
921 0xff, 0x51, 0x38, 0x77, 0x59, 0x5f, 0xd7, 0x79, 0xc6, 0x63, 0x0c, 0x71, 927 0x9c, 0x23, 0xe0, 0x1d, 0xe6, 0xf5, 0x2f, 0xb1, 0x9c, 0x3b, 0x18, 0x36,
922 0xe1, 0xe2, 0x10, 0x65, 0x40, 0x82, 0x95, 0xca, 0xa6, 0x5d, 0xfd, 0xc3, 928 0x6b, 0x89, 0x60, 0x03, 0x8f, 0x86, 0xcc, 0x5d, 0x82, 0xf7, 0xfb, 0x6f,
923 0xc8, 0x47, 0xfc, 0xfd, 0x56, 0x51, 0x27, 0x0f, 0xe7, 0xc0, 0xcb, 0x4f, 929 0xec, 0xfb, 0x2e, 0x68, 0x1d, 0x02, 0x2c, 0xe2, 0x65, 0xa6, 0x7d, 0x8f,
924 0xc0, 0x7f, 0x3f, 0x70, 0xa2, 0xf6, 0x48, 0x47, 0x74, 0xff, 0x4e, 0xd1, 930 0x57, 0xe4, 0x1e, 0xc7, 0x9b, 0xc8, 0xf3, 0xd6, 0xf6, 0xc0, 0x5c, 0x53,
925 0x7d, 0xad, 0x21, 0xe6, 0x2a, 0x5d, 0xf4, 0xd5, 0x75, 0xc8, 0xdd, 0x07, 931 0xe0, 0x9c, 0x86, 0x94, 0xcb, 0x95, 0x51, 0xe6, 0xef, 0x6d, 0x7d, 0x9c,
926 0x7b, 0xb5, 0xf0, 0xcb, 0xbd, 0xe9, 0x0c, 0xf7, 0x98, 0xeb, 0x22, 0xba, 932 0x63, 0xea, 0xf9, 0xbf, 0x09, 0xa2, 0x5a, 0xf3, 0x95, 0xf9, 0x49, 0xf8,
927 0x11, 0xbf, 0x5c, 0x73, 0x27, 0x1e, 0xee, 0x75, 0x3e, 0xea, 0xd4, 0x03, 933 0xe7, 0x20, 0xa8, 0xee, 0x1e, 0x52, 0x71, 0x68, 0x90, 0xdf, 0x1f, 0x90,
928 0x09, 0x79, 0xf7, 0x44, 0xb4, 0x37, 0x07, 0x64, 0xba, 0x0a, 0xdd, 0xed, 934 0xb2, 0xa8, 0x8a, 0x4e, 0xba, 0xc3, 0xb0, 0x00, 0xcb, 0x73, 0x2f, 0x87,
929 0xea, 0x0f, 0xfc, 0x27, 0x1d, 0xf1, 0x40, 0xde, 0xff, 0x06, 0xbc, 0x07, 935 0x72, 0x84, 0x11, 0x75, 0xa1, 0xdf, 0x8c, 0xf4, 0x32, 0x05, 0x1d, 0xdb,
930 0xb8, 0x5b, 0x0b, 0xcd, 0xba, 0xc3, 0x58, 0x3d, 0xa0, 0x31, 0xb6, 0x0e, 936 0x63, 0x1e, 0x0a, 0x63, 0x32, 0xc7, 0xb4, 0x9f, 0x42, 0xe7, 0xac, 0x14,
931 0x4f, 0x57, 0xf6, 0x44, 0xbe, 0x98, 0x84, 0x5f, 0xed, 0xb6, 0x9e, 0x10, 937 0xeb, 0x4d, 0xaa, 0xef, 0x9a, 0xde, 0xf0, 0xbb, 0xfa, 0x8c, 0x07, 0xda,
932 0xd6, 0x63, 0xc4, 0x9b, 0x94, 0x1f, 0xbe, 0x0c, 0x1e, 0x92, 0xf4, 0x93, 938 0x8a, 0x0b, 0x9d, 0x54, 0xaa, 0x27, 0x90, 0x03, 0x19, 0x34, 0x97, 0xc3,
933 0x7f, 0x5f, 0xe3, 0x27, 0x1c, 0xdb, 0x2a, 0x35, 0xd4, 0xd4, 0x5e, 0xde, 939 0x18, 0x3a, 0x54, 0x6a, 0xb0, 0xce, 0x57, 0x42, 0x9d, 0x4f, 0x86, 0xb8,
934 0x94, 0x69, 0x25, 0x03, 0xda, 0x35, 0xfa, 0x77, 0x29, 0xf4, 0xef, 0x47, 940 0x4f, 0x82, 0x17, 0xb6, 0xb5, 0x2a, 0xb8, 0x76, 0xda, 0x26, 0xeb, 0x5f,
935 0x80, 0xa3, 0x5d, 0x8c, 0x47, 0x1f, 0xc7, 0x59, 0x9d, 0xcd, 0x2c, 0xeb, 941 0x1d, 0xb6, 0x5c, 0xae, 0x71, 0xed, 0x89, 0xfc, 0xdb, 0x3c, 0x37, 0x33,
936 0xcc, 0x03, 0x76, 0x4b, 0x51, 0xdd, 0x4f, 0xdf, 0x8b, 0xee, 0xa2, 0xd8, 942 0xed, 0x18, 0xa0, 0x6b, 0x44, 0x2b, 0xb7, 0x1c, 0xad, 0xec, 0x33, 0x7d,
937 0x94, 0x96, 0x8b, 0x95, 0x28, 0x2e, 0xa5, 0x71, 0x9e, 0xb4, 0xcb, 0xa5, 943 0xbb, 0x41, 0xb7, 0x26, 0x6b, 0xdc, 0xa5, 0xd6, 0x7b, 0xc1, 0xd2, 0xee,
938 0xb9, 0x28, 0xe6, 0xb5, 0xcb, 0x12, 0xf2, 0x9a, 0x95, 0x97, 0x2c, 0x8c, 944 0x4d, 0xe8, 0x43, 0xe7, 0x27, 0x58, 0xae, 0x5f, 0x60, 0xba, 0xac, 0x82,
939 0x25, 0xe5, 0xe2, 0x5c, 0x12, 0x31, 0xab, 0x47, 0x56, 0xe6, 0x7a, 0x30, 945 0x60, 0x3e, 0xa7, 0xe9, 0xd4, 0xf0, 0xdf, 0xf5, 0x72, 0x3e, 0x75, 0x7a,
940 0x96, 0xc2, 0xba, 0x14, 0xe6, 0xdb, 0xb2, 0x52, 0xb1, 0x81, 0x27, 0x87, 946 0x98, 0xf1, 0x83, 0x8e, 0x74, 0x9a, 0x96, 0x7d, 0xde, 0xa3, 0x3e, 0xc3,
941 0x76, 0x0e, 0xed, 0x21, 0xb9, 0xa4, 0xbe, 0x17, 0x30, 0x2f, 0x18, 0x42, 947 0x3c, 0x2c, 0x2f, 0x98, 0xf4, 0x88, 0x94, 0xdb, 0x6b, 0xd2, 0xa6, 0xcb,
942 0xdc, 0x62, 0x5e, 0x30, 0x82, 0x18, 0x32, 0x81, 0x27, 0x8a, 0x5d, 0xa7, 948 0x2b, 0xb0, 0xa5, 0xd4, 0x90, 0x79, 0x94, 0xec, 0xab, 0x17, 0x75, 0xbb,
943 0x66, 0xa6, 0x2a, 0xbc, 0x73, 0x84, 0x0e, 0xac, 0x53, 0x33, 0xd3, 0xb6, 949 0x3e, 0x05, 0x7b, 0x5e, 0x5a, 0xd4, 0x69, 0xa7, 0xac, 0xb1, 0x58, 0x36,
944 0x89, 0xba, 0xed, 0x1b, 0xda, 0x54, 0x83, 0x72, 0x41, 0xb7, 0x43, 0x1d, 950 0xf6, 0x31, 0x58, 0x7c, 0x78, 0xf6, 0x43, 0x6d, 0x67, 0xef, 0xa1, 0x4b,
945 0xa2, 0x3f, 0x4a, 0x9b, 0xe4, 0x79, 0x67, 0x20, 0xc6, 0x77, 0x01, 0x9f, 951 0x4f, 0xff, 0x16, 0x7c, 0x0d, 0xf3, 0xd5, 0xb0, 0x0e, 0x23, 0x9f, 0x58,
946 0x23, 0xfa, 0x6f, 0xd0, 0x17, 0xa0, 0xc3, 0x27, 0xba, 0xe4, 0xd2, 0xcb, 952 0x40, 0xee, 0x51, 0x45, 0x6e, 0x5c, 0xc8, 0x30, 0x6c, 0xc4, 0xef, 0xad,
947 0x8c, 0x35, 0xae, 0xbc, 0x7a, 0x96, 0x3a, 0x2c, 0xf6, 0xac, 0xea, 0x90, 953 0x92, 0xff, 0x42, 0xf2, 0x7f, 0x07, 0x55, 0xa5, 0x0d, 0x65, 0xe4, 0x3b,
948 0x63, 0x0f, 0xe1, 0x8c, 0xd8, 0x0f, 0x7b, 0x32, 0x33, 0x87, 0x90, 0xcb, 954 0x01, 0x1c, 0xea, 0x1d, 0x8f, 0x91, 0x2b, 0xc9, 0x77, 0xf7, 0x2a, 0x38,
949 0x7c, 0x1b, 0xf6, 0x59, 0x66, 0xcd, 0x9d, 0x0e, 0x6a, 0x84, 0x20, 0x06, 955 0xf6, 0x11, 0x19, 0x7e, 0x77, 0x14, 0x7b, 0x32, 0x8f, 0xa3, 0xf9, 0x6e,
950 0xa0, 0xdd, 0x47, 0x5d, 0xb1, 0xdd, 0x07, 0xbb, 0xe3, 0x58, 0x9f, 0x1a, 956 0x52, 0x36, 0x14, 0xf1, 0x1d, 0x89, 0x44, 0x33, 0x4d, 0xbf, 0x8b, 0x9a,
951 0x5b, 0x04, 0x8e, 0x60, 0x8c, 0xed, 0xcd, 0xb2, 0xa8, 0xc6, 0x0e, 0xaa, 957 0x67, 0xb2, 0x39, 0x48, 0xa5, 0xa6, 0x05, 0x19, 0xcc, 0xf4, 0xf1, 0xd9,
952 0xb1, 0xb2, 0xb2, 0x0f, 0x8e, 0x1d, 0x52, 0xb1, 0xe9, 0x7c, 0x23, 0xea, 958 0x8a, 0x2b, 0x38, 0x8f, 0x60, 0x5a, 0xef, 0xa5, 0xc3, 0x7e, 0x44, 0x4f,
953 0xdf, 0x88, 0x58, 0xc2, 0x7e, 0xf6, 0xe5, 0x61, 0xeb, 0x7b, 0x71, 0xae, 959 0x32, 0xa4, 0x6f, 0x32, 0x1c, 0x27, 0x42, 0x1a, 0xda, 0xf1, 0x25, 0x81,
954 0x15, 0x64, 0xa9, 0x81, 0x3a, 0x30, 0xff, 0x7b, 0x98, 0xcb, 0x3d, 0xc8, 960 0x0b, 0x31, 0x3e, 0xf7, 0x57, 0x21, 0x1e, 0xf6, 0x1f, 0xa0, 0x75, 0x32,
955 0x9e, 0x2a, 0xe9, 0xe4, 0xf1, 0x20, 0xce, 0x83, 0xfd, 0x21, 0xad, 0xb6, 961 0x43, 0x2b, 0x3e, 0xd3, 0xb1, 0x85, 0xaa, 0x69, 0xee, 0x1f, 0x80, 0x9e,
956 0x90, 0xaf, 0x03, 0x61, 0xbb, 0x25, 0xa4, 0x4d, 0x3c, 0x36, 0x70, 0x1c, 962 0x31, 0x9e, 0x4d, 0x9c, 0xc7, 0xac, 0xe3, 0xf1, 0x91, 0x66, 0x05, 0x3c,
957 0xc3, 0x5a, 0x17, 0x38, 0x18, 0x63, 0x11, 0x23, 0x52, 0x29, 0xe8, 0x82, 963 0x66, 0xfe, 0xf2, 0xba, 0x24, 0x2d, 0x7d, 0x85, 0xe5, 0xb7, 0x07, 0xf9,
958 0x34, 0xdb, 0xa4, 0xac, 0xde, 0xf7, 0xc3, 0x76, 0xb9, 0x16, 0x3a, 0xb4, 964 0x3b, 0xeb, 0xc2, 0x96, 0x50, 0xaf, 0xd4, 0x9e, 0xa5, 0x85, 0x1e, 0xc8,
959 0xa2, 0x75, 0xa5, 0x70, 0xcf, 0x53, 0xea, 0x9c, 0xd1, 0x93, 0x9b, 0xc3, 965 0x8a, 0xf7, 0xed, 0xa2, 0xbb, 0x61, 0xef, 0xc5, 0x06, 0xef, 0x3f, 0x09,
960 0x9c, 0x10, 0x7a, 0x45, 0x9c, 0xd5, 0x93, 0x8c, 0x37, 0xef, 0x84, 0x76, 966 0x3d, 0x7a, 0x59, 0xee, 0x5f, 0x5a, 0x19, 0x08, 0xe1, 0x19, 0xb6, 0x67,
961 0xda, 0x8b, 0xbe, 0x87, 0x44, 0xef, 0x65, 0xdf, 0x51, 0xe0, 0x61, 0xed, 967 0x03, 0x6c, 0x27, 0xed, 0xab, 0x9b, 0xd7, 0x81, 0xff, 0x7d, 0xc0, 0x0b,
962 0x3c, 0x0c, 0x99, 0xd9, 0xe6, 0xfa, 0x6c, 0xd3, 0xfa, 0xc4, 0x3a, 0xeb, 968 0x3a, 0x99, 0x63, 0x78, 0xc6, 0x83, 0x75, 0x8d, 0xf4, 0x67, 0xe0, 0x49,
963 0x3b, 0x9a, 0xfa, 0x32, 0x52, 0x9b, 0xef, 0x52, 0xf1, 0xf2, 0x7c, 0x18, 969 0xc9, 0x5a, 0xbe, 0xd8, 0xe8, 0xa4, 0x62, 0x3d, 0xc2, 0xc5, 0x78, 0x3e,
964 0x2f, 0x17, 0x6b, 0x94, 0x05, 0x7e, 0x96, 0x7f, 0x5b, 0xe9, 0xa2, 0x76, 970 0x46, 0xad, 0x7b, 0x9f, 0xc4, 0x35, 0x2d, 0x71, 0xe1, 0x7d, 0x83, 0x7d,
965 0x36, 0xb0, 0xf5, 0xa5, 0x93, 0x3c, 0x17, 0x57, 0xe7, 0xd5, 0xd4, 0xbc, 971 0xcd, 0xad, 0x80, 0x47, 0xbd, 0xee, 0x80, 0xb6, 0x54, 0x37, 0x2d, 0xc9,
966 0xdf, 0x06, 0xff, 0xba, 0x1c, 0x55, 0x32, 0x70, 0x3e, 0xe6, 0xd5, 0x02, 972 0x7a, 0xbd, 0x4b, 0xf9, 0x98, 0xd4, 0x66, 0xbc, 0xdf, 0x02, 0x5b, 0xdf,
967 0xbf, 0x31, 0x6c, 0xce, 0xa1, 0x8f, 0x44, 0x6b, 0x38, 0xff, 0xe7, 0xa8, 973 0x83, 0x3c, 0xa6, 0x07, 0x73, 0xd6, 0x86, 0xb9, 0x8d, 0xf4, 0x27, 0x36,
968 0x55, 0xbe, 0xac, 0xd6, 0xac, 0xfa, 0x0c, 0xf9, 0x71, 0x42, 0x9e, 0x7b, 974 0xd0, 0xdf, 0x89, 0x75, 0xfd, 0xd8, 0x53, 0xad, 0x2b, 0x61, 0xdd, 0xec,
969 0xc0, 0x5f, 0x67, 0x28, 0x43, 0x7b, 0x28, 0x03, 0xf1, 0xfd, 0x27, 0x70, 975 0x02, 0x6c, 0x82, 0x73, 0xf3, 0x34, 0xc7, 0xe4, 0x1b, 0x25, 0x2d, 0xb3,
970 0xb7, 0x61, 0x1e, 0x79, 0xdd, 0x86, 0x3e, 0xbe, 0xff, 0x17, 0xfa, 0x76, 976 0x2b, 0xef, 0xe1, 0x5c, 0x03, 0x80, 0x8d, 0xc6, 0x8a, 0x0f, 0x75, 0xe0,
971 0x23, 0xff, 0x23, 0x6f, 0x89, 0x26, 0xde, 0xfe, 0x03, 0x63, 0x3d, 0x4a, 977 0xf9, 0x5e, 0x43, 0xde, 0x4b, 0x40, 0x06, 0x9b, 0x53, 0x7c, 0xf6, 0x6a,
972 0xb7, 0x35, 0xd4, 0x26, 0x53, 0xbc, 0xef, 0x48, 0xe1, 0x1c, 0x38, 0xb9, 978 0xe3, 0xf3, 0x78, 0x76, 0x63, 0x1b, 0xbf, 0x98, 0x57, 0x4c, 0x2f, 0xd3,
973 0x4d, 0xd1, 0xad, 0x9d, 0xbd, 0x86, 0xf1, 0x5e, 0xac, 0x89, 0xda, 0xcd, 979 0x0a, 0x3d, 0x25, 0xd8, 0x9b, 0x8b, 0x9a, 0x2f, 0xa5, 0x53, 0x29, 0x87,
974 0xb2, 0xe9, 0x58, 0xfb, 0x53, 0x25, 0xcf, 0x62, 0xed, 0x4e, 0xf2, 0x6f, 980 0x78, 0xee, 0xf3, 0x5d, 0x2d, 0xdb, 0xe5, 0xa0, 0xaa, 0x0b, 0x1c, 0x8e,
975 0x5b, 0x23, 0x3b, 0xe5, 0x26, 0x4f, 0xe4, 0xa7, 0x1f, 0x4f, 0x2b, 0x72, 981 0xeb, 0x86, 0x3c, 0xfb, 0xe1, 0x15, 0xbe, 0xaf, 0xb5, 0x10, 0x4f, 0xed,
976 0x21, 0xd8, 0x6d, 0xd2, 0x90, 0xd1, 0x7c, 0x9a, 0xdf, 0xf9, 0x12, 0xbc, 982 0x2c, 0xe1, 0xec, 0x0f, 0xaf, 0x38, 0xf4, 0x68, 0x33, 0x4b, 0x47, 0x9b,
977 0x17, 0x1d, 0x19, 0xe4, 0x9e, 0xa1, 0xdd, 0x60, 0x4e, 0x47, 0x7f, 0x4b, 983 0xb6, 0x79, 0x3f, 0x7c, 0x40, 0x79, 0xed, 0x1e, 0x77, 0x57, 0x8a, 0xfd,
978 0xc8, 0x31, 0xd4, 0x24, 0xe5, 0x85, 0x8c, 0x56, 0x3c, 0x99, 0x45, 0x16, 984 0x96, 0x81, 0x9c, 0xb3, 0xc3, 0x51, 0x39, 0x48, 0x95, 0xeb, 0xb1, 0x05,
979 0xad, 0xbe, 0xd5, 0xc9, 0x8b, 0x4b, 0xb6, 0x7c, 0x1b, 0x7e, 0x7a, 0xb2, 985 0x9b, 0xef, 0x68, 0xcc, 0x06, 0x6d, 0xcc, 0x53, 0xfe, 0x2f, 0x73, 0x14,
980 0x9e, 0x4d, 0x7f, 0x13, 0xf9, 0xc1, 0x91, 0x25, 0xe6, 0x13, 0x3d, 0x29, 986 0xde, 0x9f, 0xfd, 0x34, 0x72, 0x12, 0x1f, 0x39, 0x89, 0x8f, 0x9c, 0xc4,
981 0x65, 0x9b, 0xf3, 0x9a, 0x6c, 0x60, 0x4c, 0x9b, 0x47, 0x7e, 0x6a, 0xdd, 987 0x47, 0x4e, 0xe2, 0x23, 0x27, 0xf1, 0x91, 0x93, 0xf8, 0xc8, 0x49, 0x7c,
982 0x2d, 0x47, 0x82, 0x9f, 0x57, 0xd7, 0xc6, 0x0c, 0xca, 0xb1, 0x36, 0x66, 988 0xe4, 0x24, 0xc8, 0xff, 0x55, 0x5d, 0x30, 0x8e, 0x5c, 0x1b, 0xfe, 0xcb,
983 0x10, 0x0f, 0x63, 0xc6, 0x4e, 0xec, 0x13, 0x63, 0x06, 0xf6, 0xff, 0x24, 989 0xff, 0x6a, 0x98, 0x53, 0x44, 0x31, 0x99, 0xe7, 0x56, 0x37, 0x79, 0x6e,
984 0x63, 0x86, 0x8d, 0x75, 0x8c, 0x19, 0x79, 0x59, 0xac, 0x32, 0x66, 0xec, 990 0x74, 0x4f, 0x7c, 0x00, 0x73, 0x13, 0x61, 0xee, 0xc3, 0x6b, 0xa2, 0x98,
985 0x45, 0x9b, 0x31, 0xa3, 0x80, 0x76, 0x10, 0x2f, 0x16, 0x55, 0xbc, 0xc8, 991 0xcd, 0xeb, 0x68, 0xcc, 0x43, 0xbd, 0x59, 0x98, 0xe4, 0xdc, 0x48, 0xc5,
986 0x5a, 0xcb, 0xc2, 0x38, 0x81, 0x3c, 0xb1, 0x8a, 0x3c, 0xb1, 0x8a, 0x3c, 992 0x2a, 0x95, 0x97, 0xbf, 0x8a, 0xfc, 0xc8, 0x42, 0x7e, 0x34, 0x88, 0x5c,
987 0xb1, 0x8a, 0x3c, 0xb1, 0x8a, 0x3c, 0x11, 0xb6, 0xfe, 0x5a, 0x15, 0x79, 993 0x88, 0xef, 0xb5, 0xa3, 0xfb, 0xa3, 0x82, 0x76, 0xc8, 0x1f, 0xd7, 0xbe,
988 0x22, 0xfc, 0xe7, 0x3c, 0x72, 0x92, 0xa0, 0xa6, 0x38, 0x8c, 0x9a, 0xc2, 994 0xe6, 0x73, 0xde, 0xee, 0x58, 0x65, 0x21, 0x16, 0xfa, 0x29, 0xa0, 0xe2,
989 0xd5, 0xc6, 0xaa, 0xe3, 0xda, 0xbe, 0x2a, 0x6a, 0x43, 0xf5, 0x9d, 0x58, 995 0xe8, 0xb7, 0x90, 0x23, 0x7f, 0x4f, 0xde, 0x95, 0x4d, 0x0c, 0xb3, 0xcc,
990 0x1f, 0xda, 0x80, 0xba, 0xa8, 0xe6, 0x6c, 0x01, 0x5f, 0xd7, 0xe0, 0x1b, 996 0x27, 0x3e, 0x25, 0x4f, 0x8e, 0xf8, 0xab, 0xee, 0xf8, 0xc4, 0x12, 0xf3,
991 0xd4, 0xd3, 0x56, 0x99, 0xca, 0xed, 0x80, 0x7c, 0xd8, 0x7f, 0xfb, 0xfb, 997 0x8f, 0xa8, 0xef, 0x2c, 0x18, 0x7e, 0x36, 0x41, 0xa9, 0x53, 0x5b, 0x30,
992 0xe8, 0x43, 0x3e, 0x9f, 0x63, 0x0d, 0xc2, 0x78, 0xb5, 0x0f, 0x6d, 0x1d, 998 0x67, 0x52, 0xbf, 0xbc, 0x27, 0x82, 0x28, 0xcf, 0xfe, 0x1a, 0xf2, 0x72,
993 0x6d, 0xec, 0xe9, 0x04, 0x7c, 0xc4, 0x7e, 0x90, 0xf9, 0x62, 0x7a, 0x41, 999 0x48, 0x9c, 0xe5, 0xdb, 0x04, 0xc6, 0xcb, 0xfe, 0xb5, 0x32, 0x53, 0x6c,
994 0x9e, 0xdc, 0x1c, 0xd8, 0xf4, 0x6f, 0x31, 0x27, 0x5e, 0xd3, 0xde, 0x88, 1000 0x54, 0xa4, 0x4e, 0x1d, 0x6a, 0x96, 0x90, 0x3f, 0xf5, 0xf6, 0x53, 0x97,
995 0x39, 0xf0, 0x17, 0xd8, 0x97, 0x5a, 0x03, 0x5c, 0xba, 0xfd, 0xe7, 0xc4, 1001 0x81, 0x1a, 0x2a, 0xc2, 0xcd, 0x38, 0x7f, 0x99, 0x92, 0xb5, 0xcd, 0xd9,
996 0xd1, 0xb7, 0xe1, 0xd6, 0x1c, 0xda, 0xd5, 0xf7, 0x9a, 0xfa, 0xb2, 0x98, 1002 0x35, 0x79, 0x42, 0xd6, 0xbc, 0x4f, 0x65, 0xa6, 0x5a, 0xb7, 0x33, 0x5c,
997 0xcf, 0xef, 0xe2, 0x3b, 0xf0, 0xfb, 0x16, 0x7e, 0x61, 0x77, 0xf6, 0x05, 1003 0xd7, 0x82, 0xd6, 0x99, 0x27, 0x81, 0x63, 0x19, 0x39, 0x81, 0x2e, 0xf7,
998 0xcc, 0xe9, 0xc3, 0xef, 0x77, 0x9a, 0xe6, 0x42, 0x0a, 0xfb, 0x2f, 0xd1, 1004 0xae, 0xcc, 0xcc, 0xd6, 0xd5, 0x5d, 0x95, 0xa2, 0x01, 0xf1, 0x2f, 0xd7,
999 0x77, 0x31, 0xa4, 0xc1, 0x6f, 0x89, 0x5f, 0x6a, 0xe2, 0xe3, 0x07, 0xe8, 1005 0x45, 0xfa, 0x92, 0xba, 0xb3, 0x12, 0x12, 0x96, 0xe1, 0x18, 0xde, 0x00,
1000 0xfb, 0x6b, 0xf4, 0xf9, 0xfe, 0xdb, 0x4e, 0xd4, 0x27, 0xa5, 0x96, 0x70, 1006 0x1c, 0xcb, 0x2d, 0x0b, 0x58, 0x96, 0x1d, 0xd3, 0x50, 0x99, 0xa9, 0x34,
1001 0xef, 0x46, 0xd5, 0xde, 0x69, 0xca, 0xe6, 0x8f, 0x2c, 0xe9, 0xaa, 0x0e, 1007 0xda, 0x69, 0x60, 0x3c, 0x8c, 0x37, 0x3a, 0x0f, 0x9f, 0x25, 0x45, 0xe2,
1002 0x7a, 0xae, 0x8e, 0xea, 0x08, 0x71, 0xbe, 0xbc, 0x10, 0xd4, 0xad, 0xc7, 1008 0x54, 0x10, 0x94, 0x47, 0x07, 0xc3, 0x3a, 0x12, 0xf5, 0xe3, 0x09, 0x43,
1003 0x51, 0x73, 0x16, 0xab, 0xb4, 0x91, 0x1c, 0xfa, 0x6d, 0x9c, 0x69, 0x32, 1009 0xea, 0xb9, 0x1a, 0x7f, 0x53, 0xc6, 0x29, 0x4b, 0xf0, 0x3c, 0x3f, 0xf1,
1004 0x69, 0xdc, 0xaa, 0x63, 0x13, 0x89, 0xc9, 0x7a, 0x9b, 0x48, 0x37, 0x69, 1010 0x2e, 0xf7, 0x24, 0xe6, 0x30, 0x5e, 0x8e, 0xd6, 0x8a, 0x70, 0x6d, 0x77,
1005 0x32, 0x4f, 0x22, 0x8e, 0xd9, 0x99, 0xe2, 0xc2, 0xec, 0x8c, 0x07, 0x9c, 1011 0x1b, 0x3f, 0x3b, 0xc2, 0xfd, 0x98, 0x26, 0x3e, 0xe7, 0x65, 0xec, 0xc5,
1006 0x63, 0x75, 0xae, 0xe5, 0x3c, 0x93, 0xf7, 0x63, 0x4d, 0x74, 0x69, 0x13, 1012 0x74, 0xf1, 0x1a, 0x13, 0xb4, 0x41, 0x96, 0xfe, 0xff, 0x96, 0xf7, 0xed,
1007 0x60, 0x06, 0xf4, 0x9e, 0xab, 0x93, 0x7e, 0x40, 0xb3, 0xac, 0x68, 0xda, 1013 0x67, 0x62, 0x9e, 0x1a, 0x80, 0xe1, 0xf5, 0x8c, 0x23, 0x82, 0xc1, 0x8b,
1008 0xe8, 0x8f, 0xea, 0xc7, 0x1c, 0x6a, 0x5d, 0x99, 0x64, 0xed, 0x5c, 0x0c, 1014 0xb3, 0x0a, 0x4e, 0xac, 0xdd, 0xed, 0x7d, 0xd6, 0xbe, 0xed, 0xb4, 0x46,
1009 0x69, 0xba, 0x75, 0x49, 0x24, 0x0a, 0xcd, 0xf8, 0x82, 0x8c, 0xf3, 0xb9, 1015 0xfb, 0x47, 0x78, 0xb2, 0x4a, 0x6e, 0x6b, 0xf0, 0xf2, 0xff, 0x0a, 0xc3,
1010 0xfa, 0xec, 0x8c, 0xfe, 0x42, 0x36, 0xc7, 0x3b, 0x11, 0xd7, 0x9a, 0x9d, 1016 0x13, 0xba, 0xf8, 0x89, 0x3b, 0xd2, 0x6c, 0x5b, 0x6d, 0x1c, 0xdd, 0x35,
1011 0x69, 0x1d, 0x48, 0xc8, 0x8f, 0x91, 0xbb, 0x1d, 0x53, 0x34, 0x66, 0x67, 1017 0x70, 0xcd, 0xcf, 0x35, 0x3c, 0x7f, 0x47, 0x68, 0xaf, 0x4b, 0x4b, 0x61,
1012 0x8c, 0x17, 0x02, 0x5b, 0x0c, 0xe8, 0xe0, 0x3c, 0xc9, 0xb7, 0x43, 0x4e, 1018 0x2c, 0x83, 0x2e, 0xaa, 0xbb, 0xd4, 0x70, 0x6c, 0x70, 0x6c, 0x43, 0xe3,
1013 0xd2, 0x62, 0x4d, 0x1d, 0x8c, 0x4f, 0xaa, 0x7a, 0xd1, 0x94, 0x2b, 0x15, 1019 0x1c, 0x3f, 0xb2, 0x91, 0xf6, 0x7b, 0x42, 0x95, 0x9b, 0x9c, 0x59, 0x8c,
1014 0x45, 0x3b, 0xac, 0xdb, 0xc9, 0xc3, 0xec, 0x8c, 0xfc, 0xd1, 0x2d, 0x1e, 1020 0x7c, 0x0e, 0xfc, 0xc1, 0xb0, 0x11, 0xfa, 0xed, 0x24, 0xfc, 0x56, 0x0f,
1015 0xd6, 0x91, 0x87, 0x78, 0x49, 0x27, 0xd0, 0x5b, 0xc0, 0x7f, 0x12, 0xf5, 1021 0xed, 0x83, 0xbf, 0xb9, 0x13, 0xfe, 0x66, 0x3f, 0xea, 0xca, 0xf1, 0x95,
1016 0x7b, 0x54, 0xab, 0xfb, 0xfe, 0x8a, 0x93, 0x43, 0x5c, 0xe0, 0x3e, 0xb6, 1022 0xf6, 0xfb, 0x57, 0xae, 0x65, 0xab, 0x74, 0x58, 0xca, 0xae, 0x12, 0xe8,
1017 0xa8, 0x3c, 0xd7, 0x73, 0x32, 0xbc, 0xef, 0x9b, 0xe3, 0xdf, 0x39, 0x78, 1023 0xce, 0xc7, 0x90, 0xdf, 0x2e, 0x99, 0xa3, 0x29, 0x79, 0xc2, 0x57, 0xba,
1018 0xf9, 0x01, 0xd4, 0x4d, 0xbc, 0x1b, 0xa4, 0x7f, 0xe1, 0xf7, 0x36, 0xff, 1024 0xfc, 0x2d, 0x62, 0xe3, 0x3d, 0x6f, 0x16, 0x7a, 0xdd, 0x55, 0x10, 0x32,
1019 0xe2, 0x7c, 0xf6, 0x93, 0xe7, 0x81, 0xf4, 0x55, 0xf0, 0xe7, 0xe5, 0xd1, 1025 0xff, 0x52, 0x7c, 0xab, 0x36, 0x14, 0xdf, 0xe0, 0x53, 0x81, 0xdf, 0xa0,
1020 0x87, 0x58, 0x51, 0x6c, 0x44, 0xb8, 0x78, 0xc7, 0xce, 0x39, 0x2a, 0xff, 1026 0x4a, 0xd3, 0xa4, 0x0a, 0xf6, 0xad, 0x60, 0xdf, 0x0a, 0xea, 0xc1, 0xd9,
1021 0x6e, 0xf2, 0xd1, 0x96, 0xf0, 0xdc, 0xa5, 0x8e, 0xc8, 0x27, 0xf9, 0xe9, 1027 0x66, 0xfb, 0x77, 0xaa, 0xee, 0xb0, 0xc6, 0x66, 0xd8, 0xa8, 0x6f, 0x86,
1022 0x84, 0x4d, 0x90, 0x17, 0xce, 0x8f, 0xee, 0x25, 0xd8, 0xfe, 0xb8, 0x36, 1028 0xe7, 0xd2, 0xda, 0x9e, 0xc7, 0xc0, 0xbb, 0x47, 0xc1, 0xbb, 0x23, 0xa8,
1023 0x12, 0xdd, 0xa9, 0x7d, 0x9c, 0x3d, 0x8f, 0x74, 0x76, 0x37, 0x7e, 0x88, 1029 0x83, 0xfe, 0x04, 0x75, 0xd0, 0x1f, 0xa2, 0x0e, 0x3a, 0x8c, 0x3a, 0x68,
1024 0x83, 0xb4, 0x23, 0xbe, 0x22, 0x9e, 0x88, 0x8f, 0xfc, 0x44, 0xbc, 0x28, 1030 0x0a, 0x75, 0xd0, 0x7d, 0xb0, 0xfd, 0x7b, 0x61, 0xfb, 0x93, 0xb0, 0xfd,
1025 0x1b, 0x5d, 0x97, 0x9f, 0x60, 0x5d, 0xc0, 0x4f, 0x69, 0x21, 0x0d, 0x9d, 1031 0x09, 0x79, 0xc7, 0x73, 0xc8, 0xdf, 0x78, 0xef, 0x11, 0xed, 0xc5, 0xed,
1026 0x90, 0xa7, 0x11, 0x6d, 0xa4, 0xba, 0xde, 0x1d, 0xc7, 0x0f, 0x5c, 0xc6, 1032 0x4d, 0x22, 0x88, 0xaf, 0x7c, 0x62, 0x9c, 0x1a, 0x2d, 0xae, 0x87, 0x5c,
1027 0xd5, 0xb1, 0x06, 0xef, 0xa1, 0x48, 0x97, 0x7f, 0x3b, 0xb2, 0xa4, 0x8d, 1033 0x79, 0x7f, 0x35, 0xed, 0x4e, 0x6a, 0x53, 0xc8, 0xb9, 0xef, 0x1f, 0xe1,
1028 0x34, 0xf8, 0x9d, 0xa9, 0xae, 0xb9, 0x8d, 0x88, 0xde, 0x5a, 0x9d, 0x46, 1034 0x3a, 0x29, 0xa5, 0xee, 0x2b, 0x73, 0xf6, 0x73, 0x1e, 0xd2, 0x2e, 0xe4,
1029 0xbf, 0xbc, 0x2b, 0xff, 0x0c, 0xf6, 0xa9, 0x3b, 0xf8, 0xbb, 0x14, 0x55, 1035 0x6d, 0x38, 0xb3, 0x7d, 0xa6, 0xa8, 0x47, 0x35, 0x4a, 0xdf, 0x5a, 0x8d,
1030 0x47, 0xb1, 0x6f, 0xb9, 0xd5, 0x73, 0xa2, 0xbf, 0xd3, 0xd9, 0x1f, 0xe6, 1036 0xb2, 0x3c, 0xcf, 0x35, 0xca, 0xab, 0x6b, 0x35, 0xca, 0xf2, 0x3c, 0xd7,
1031 0x43, 0x51, 0x6d, 0x1c, 0xd5, 0x59, 0xea, 0x9e, 0x7d, 0xaf, 0xe7, 0x68, 1037 0x28, 0xaf, 0xac, 0xab, 0x51, 0xae, 0x3c, 0xfd, 0xf2, 0xba, 0x1a, 0xe5,
1032 0xc8, 0x4f, 0x99, 0x33, 0x05, 0x3a, 0x08, 0xf1, 0xde, 0x91, 0xcf, 0x91, 1038 0xca, 0xd3, 0x2f, 0x85, 0x63, 0xa6, 0x03, 0x7e, 0xc9, 0x0d, 0x69, 0x35,
1033 0x26, 0x3e, 0x47, 0xc1, 0xe7, 0x3e, 0xf0, 0x39, 0x76, 0x8b, 0xcf, 0x5b, 1039 0x5d, 0x3c, 0x7b, 0xc3, 0x7c, 0xe1, 0xfb, 0xfd, 0xeb, 0xff, 0x1f, 0x3a,
1034 0xb6, 0x97, 0x29, 0xc3, 0xf6, 0x46, 0xd6, 0xb5, 0xbd, 0x55, 0x3a, 0xab, 1040 0x6e, 0x9d, 0x1a, 0x39, 0xdf, 0xd8, 0xaa, 0xea, 0x9a, 0xf6, 0xf9, 0xde,
1035 0x73, 0x83, 0xfb, 0x9a, 0x91, 0x86, 0x2f, 0xc7, 0x9d, 0x8f, 0x53, 0x37, 1041 0xb6, 0xf9, 0x55, 0xf9, 0x6d, 0xb4, 0x5c, 0xdb, 0xfc, 0x3e, 0xbc, 0x27,
1036 0xb7, 0xcb, 0x99, 0x85, 0xbb, 0xd5, 0xb7, 0x11, 0xaf, 0x2a, 0x77, 0x94, 1042 0xad, 0x0c, 0xdb, 0xf5, 0x02, 0x7d, 0x1c, 0xf0, 0xf7, 0x3d, 0x4f, 0x74,
1037 0x4b, 0xf5, 0x80, 0x9f, 0x1f, 0x2f, 0xb1, 0x3d, 0x12, 0xea, 0x8a, 0x3a, 1043 0xc9, 0xef, 0x6a, 0x9e, 0xcc, 0x91, 0x61, 0xa3, 0xa3, 0x47, 0xb7, 0x2a,
1038 0xcb, 0x3a, 0x25, 0xb9, 0x1b, 0x2f, 0xbf, 0xf8, 0x9c, 0x76, 0xa5, 0x12, 1044 0x3b, 0xe6, 0x7e, 0x5a, 0x53, 0xbe, 0xf9, 0x41, 0xe0, 0x01, 0xaf, 0x7d,
1039 0x9d, 0x4f, 0x5a, 0x78, 0xc6, 0xae, 0xe5, 0x29, 0xfa, 0x6e, 0x32, 0x66, 1045 0x43, 0xde, 0xe1, 0xa8, 0xf3, 0xaa, 0xbb, 0x6c, 0x23, 0xbf, 0x8a, 0x38,
1040 0x45, 0xf7, 0x67, 0x22, 0xfc, 0xfe, 0xc0, 0xef, 0x75, 0x6b, 0xbf, 0x13, 1046 0x03, 0x59, 0x4b, 0xdc, 0x5c, 0xf3, 0x71, 0x9d, 0x18, 0xf9, 0xef, 0x08,
1041 0xf0, 0x7c, 0x8a, 0x78, 0xd7, 0x53, 0x3c, 0x9f, 0xc6, 0x9c, 0x66, 0x19, 1047 0xd7, 0xcf, 0xd2, 0x8a, 0xee, 0xdb, 0x50, 0xef, 0xf1, 0x9a, 0x68, 0xdc,
1042 0x5c, 0xd8, 0xa4, 0x9e, 0xe4, 0x98, 0xe7, 0xd0, 0x2f, 0x4c, 0xd0, 0x0c, 1048 0x5e, 0x1f, 0x26, 0xc3, 0xfb, 0xac, 0x55, 0x95, 0x13, 0x49, 0x7c, 0x46,
1043 0xee, 0xdd, 0x6a, 0x4b, 0xbe, 0x5c, 0x74, 0x36, 0x06, 0xe7, 0x28, 0x64, 1049 0x88, 0xef, 0xbf, 0x02, 0xe5, 0x37, 0x18, 0xde, 0x6c, 0x83, 0x1f, 0x47,
1044 0xba, 0x6c, 0xf1, 0xfe, 0x0a, 0x31, 0x8c, 0x67, 0x83, 0xb2, 0xb5, 0x16, 1050 0x9e, 0xc6, 0x77, 0x2b, 0x9c, 0x6f, 0x19, 0xf4, 0xee, 0x7c, 0x37, 0xbd,
1045 0xf5, 0x5c, 0x39, 0xd0, 0x0e, 0x1d, 0xb3, 0xdd, 0xd6, 0xcb, 0xfb, 0x0a, 1051 0x73, 0x1c, 0xf9, 0xa6, 0x6b, 0x67, 0x5f, 0x46, 0xbd, 0x70, 0x8a, 0xf3,
1046 0xca, 0xbc, 0xa0, 0xf6, 0x21, 0xd2, 0x71, 0xf4, 0x7d, 0xae, 0x55, 0x96, 1052 0xe2, 0x51, 0xa6, 0x73, 0xc8, 0x9a, 0x25, 0xab, 0x5f, 0xe5, 0xd1, 0x47,
1047 0xc3, 0xbb, 0xad, 0xc5, 0x8a, 0xef, 0xbf, 0x83, 0x3c, 0xfc, 0x34, 0x74, 1053 0xb4, 0x4f, 0xd2, 0x2d, 0xc2, 0x7d, 0x7e, 0xd6, 0xb6, 0x8f, 0xd5, 0xb6,
1048 0x5f, 0xae, 0xff, 0xcc, 0x5f, 0x4e, 0xf1, 0x6f, 0xa5, 0x22, 0x9b, 0xd8, 1054 0x4f, 0x81, 0xed, 0xad, 0xf1, 0x75, 0x9c, 0xb9, 0xb2, 0xfd, 0x26, 0x33,
1049 0xd1, 0xcb, 0x7b, 0x20, 0xf8, 0x96, 0x1c, 0xaf, 0x87, 0x65, 0xbf, 0x70, 1055 0x1d, 0xd6, 0x52, 0x8f, 0x8c, 0x6e, 0xa6, 0xfa, 0x80, 0x7d, 0xee, 0x15,
1050 0x9c, 0x7d, 0xff, 0x0d, 0xbe, 0x7d, 0xff, 0xf4, 0xaa, 0x9d, 0x02, 0xfe, 1056 0xe4, 0xda, 0xe5, 0x51, 0xcc, 0xa5, 0x87, 0xf0, 0x8e, 0xe7, 0xed, 0x06,
1051 0x17, 0x33, 0xe1, 0x9b, 0xdd, 0x90, 0x58, 0x00, 0x00, 0x00 }; 1057 0x09, 0xfb, 0x5c, 0x83, 0x90, 0x4c, 0x77, 0xd9, 0x15, 0xbe, 0x63, 0x4b,
1058 0x0b, 0xee, 0x4b, 0xda, 0x1a, 0xa1, 0xfd, 0x66, 0x2e, 0xe2, 0xcc, 0x53,
1059 0xa8, 0x99, 0x8e, 0xa8, 0xbb, 0xaf, 0x70, 0x9f, 0x5b, 0xb4, 0x8b, 0x32,
1060 0xaf, 0xcd, 0x69, 0x95, 0xb4, 0x3a, 0xe3, 0x37, 0x60, 0xeb, 0xba, 0x60,
1061 0xd8, 0x77, 0x81, 0x5b, 0xa3, 0xa5, 0xe3, 0xba, 0xbc, 0xeb, 0x2c, 0x8f,
1062 0xb2, 0xac, 0xf9, 0x79, 0x3d, 0xde, 0x45, 0x67, 0xfa, 0xdb, 0xf0, 0x4c,
1063 0x5f, 0x0a, 0x6b, 0xed, 0xe8, 0x4c, 0x09, 0x7a, 0x63, 0xde, 0x04, 0xec,
1064 0x08, 0xf8, 0x51, 0xa2, 0x95, 0x96, 0xf5, 0x39, 0x78, 0x6a, 0x6d, 0xbc,
1065 0x31, 0x36, 0xc8, 0x30, 0xaa, 0x59, 0xc0, 0x83, 0x89, 0x0c, 0xec, 0x70,
1066 0xba, 0x3f, 0xba, 0x83, 0xd5, 0x1d, 0xa1, 0xa9, 0xda, 0x9b, 0xe7, 0x07,
1067 0x61, 0x8b, 0x16, 0xec, 0x93, 0xf3, 0x9d, 0x12, 0xd7, 0x19, 0xe1, 0xf7,
1068 0x4b, 0xdb, 0x9c, 0xa4, 0x2c, 0x6a, 0x15, 0x3e, 0x7f, 0x9e, 0x96, 0x5b,
1069 0x11, 0x0d, 0x39, 0xd8, 0xe3, 0x18, 0x7e, 0x23, 0x78, 0xe7, 0xe2, 0xc7,
1070 0x75, 0x4e, 0x81, 0x1e, 0x93, 0x79, 0x34, 0xf2, 0xe4, 0x61, 0xa6, 0xef,
1071 0x00, 0xd6, 0xb3, 0x3e, 0xb3, 0x9e, 0x1e, 0x20, 0x6f, 0x80, 0x7d, 0x45,
1072 0x06, 0xb8, 0x01, 0xe3, 0xbf, 0x0e, 0x5b, 0x1f, 0xc4, 0xd3, 0x36, 0xcb,
1073 0xcc, 0x5b, 0x89, 0x3f, 0x08, 0xf4, 0x1c, 0x7f, 0x3b, 0x18, 0x0f, 0xc7,
1074 0x43, 0xe6, 0xdd, 0xac, 0x7b, 0x99, 0x1d, 0x74, 0x6e, 0x31, 0x8a, 0x61,
1075 0x33, 0xb0, 0x41, 0xbe, 0x53, 0x1d, 0x07, 0x5f, 0x78, 0xac, 0x85, 0xb1,
1076 0x0c, 0xf3, 0xcb, 0x0b, 0x38, 0x77, 0x9e, 0x4e, 0xa1, 0x66, 0xa7, 0x01,
1077 0x7e, 0x22, 0x57, 0xf5, 0xb7, 0x84, 0xfa, 0xbe, 0x1e, 0x5e, 0x77, 0xb8,
1078 0x3f, 0x0e, 0xfa, 0x8c, 0x36, 0x78, 0x86, 0x51, 0xb5, 0xc5, 0x45, 0x42,
1079 0x2c, 0xcd, 0x04, 0xb7, 0x8b, 0xfc, 0x7d, 0xf4, 0x80, 0x3c, 0x53, 0x9e,
1080 0x0e, 0x2f, 0x06, 0x81, 0x97, 0x1b, 0xca, 0x2e, 0x93, 0x9d, 0x7d, 0x92,
1081 0xf6, 0x98, 0xfb, 0x48, 0x97, 0xdf, 0xe0, 0x50, 0x13, 0xdf, 0xde, 0x91,
1082 0x0f, 0x82, 0x93, 0xa0, 0xfd, 0x05, 0xb9, 0xcf, 0x7d, 0xa0, 0x1f, 0xbc,
1083 0x92, 0xf5, 0x04, 0xd3, 0x0a, 0xde, 0xa4, 0x99, 0xde, 0x24, 0x1d, 0x6e,
1084 0x9d, 0x0f, 0x65, 0xf3, 0x28, 0x79, 0xfe, 0xdb, 0x3a, 0xdf, 0x47, 0x97,
1085 0x5b, 0x4f, 0x86, 0xb4, 0xe5, 0x41, 0x2f, 0xf6, 0x6f, 0xbd, 0x90, 0x66,
1086 0xdf, 0xc0, 0x32, 0xf7, 0x90, 0xf1, 0x79, 0xa3, 0xcf, 0x40, 0x07, 0x3f,
1087 0xcd, 0x0f, 0xa4, 0x68, 0xbd, 0x1f, 0x60, 0xb8, 0xd4, 0x75, 0x74, 0x85,
1088 0xe9, 0x20, 0xe9, 0x3f, 0x85, 0xb3, 0x19, 0xf4, 0x30, 0x3e, 0x7d, 0x83,
1089 0x2f, 0xa8, 0xc8, 0xe7, 0xaa, 0xce, 0xbe, 0x89, 0xe3, 0x14, 0xeb, 0x70,
1090 0x0f, 0xfc, 0x1f, 0x74, 0x10, 0x76, 0x5c, 0x5c, 0xe4, 0x3b, 0x85, 0x61,
1091 0xbe, 0x87, 0x3a, 0x53, 0x82, 0x6c, 0x97, 0xf8, 0xbb, 0x60, 0x5a, 0xe5,
1092 0x82, 0xaa, 0x76, 0xb2, 0xd8, 0x17, 0x32, 0xaf, 0xa5, 0x9f, 0x2c, 0xc9,
1093 0xef, 0x80, 0x29, 0xac, 0x09, 0xf0, 0x6c, 0xff, 0x9b, 0x88, 0x9f, 0x14,
1094 0xd4, 0xdf, 0x44, 0x84, 0xdf, 0x64, 0x1b, 0x2a, 0x07, 0x78, 0xb8, 0x69,
1095 0xd0, 0x54, 0x33, 0xfa, 0x1b, 0x09, 0x96, 0x83, 0x83, 0x3a, 0x3e, 0x8a,
1096 0xfb, 0x81, 0x8c, 0x2f, 0xd5, 0x75, 0xb2, 0xfc, 0x66, 0x98, 0xcf, 0x70,
1097 0xfe, 0xce, 0x3c, 0xc4, 0x78, 0x59, 0xc9, 0x6f, 0x49, 0xec, 0x84, 0xfc,
1098 0xc0, 0x73, 0xdf, 0x80, 0x2d, 0x65, 0xc2, 0x98, 0x6c, 0x72, 0x7d, 0x18,
1099 0xd6, 0xac, 0xdb, 0xa9, 0x3a, 0xc9, 0xef, 0x13, 0xf4, 0xfa, 0xfc, 0xa0,
1100 0x7c, 0x5f, 0xa6, 0x44, 0xf8, 0x9e, 0xc7, 0x29, 0x2a, 0xcb, 0xf7, 0xf7,
1101 0x86, 0xf8, 0x50, 0x63, 0xdd, 0x1b, 0x8d, 0x33, 0x90, 0xa3, 0x82, 0x9b,
1102 0x46, 0x2c, 0x7b, 0x0c, 0x71, 0x6c, 0x1a, 0x7c, 0x2f, 0x4e, 0x54, 0x68,
1103 0x87, 0xc3, 0x3a, 0x0e, 0x99, 0xa5, 0x58, 0xc7, 0x58, 0xbf, 0x18, 0xa6,
1104 0x17, 0x79, 0x26, 0xce, 0x3b, 0x4a, 0x53, 0x7a, 0xfe, 0xfd, 0x83, 0xe5,
1105 0x9a, 0x6d, 0x16, 0xe8, 0xa3, 0xc0, 0x33, 0x78, 0xbc, 0x7a, 0xf0, 0x61,
1106 0x75, 0x4f, 0x2f, 0x44, 0xfe, 0xd2, 0xc1, 0xb2, 0xea, 0xe3, 0xcc, 0xef,
1107 0x87, 0x7d, 0x86, 0xd3, 0xe5, 0xf7, 0xd3, 0x7f, 0xbf, 0xd5, 0xa0, 0x8b,
1108 0xb7, 0x06, 0xc1, 0xfd, 0xfc, 0x0d, 0x27, 0xac, 0x41, 0xd5, 0x77, 0x71,
1109 0x8e, 0x13, 0xa8, 0x37, 0x46, 0x2d, 0xad, 0x04, 0xdb, 0x3d, 0xe5, 0xa3,
1110 0x5e, 0x11, 0xf6, 0xd8, 0xaa, 0x30, 0x11, 0x7f, 0xb9, 0x96, 0xff, 0xcd,
1111 0x7e, 0xfe, 0x26, 0x3c, 0xe7, 0xf2, 0x9a, 0x6d, 0xea, 0xae, 0xea, 0xe6,
1112 0xdb, 0xa4, 0xcf, 0x25, 0x0a, 0xe3, 0xd0, 0xcd, 0xed, 0xf6, 0xd1, 0x9e,
1113 0x23, 0xb2, 0x5d, 0xd0, 0x94, 0x01, 0x7a, 0xaa, 0xb5, 0x28, 0xdf, 0xe2,
1114 0xef, 0xfd, 0xab, 0x07, 0xbf, 0xdb, 0xbc, 0x74, 0x70, 0x16, 0xf2, 0xe1,
1115 0x33, 0xcd, 0x36, 0x23, 0xfd, 0x8b, 0x72, 0x7e, 0xee, 0x23, 0xfe, 0xfb,
1116 0x88, 0xff, 0x3e, 0xe2, 0xbf, 0x8f, 0xf8, 0xef, 0x23, 0xfe, 0xfb, 0x88,
1117 0xff, 0xe0, 0xe1, 0x0f, 0xa0, 0x2f, 0xe7, 0xfd, 0x89, 0x30, 0xdf, 0x7a,
1118 0x7c, 0x2d, 0xdf, 0x3a, 0xd7, 0xe2, 0x6f, 0x3f, 0x92, 0x96, 0x4a, 0x85,
1119 0x54, 0xbe, 0x4a, 0x82, 0xf3, 0x9b, 0x28, 0x5f, 0xbd, 0xfe, 0x37, 0x0c,
1120 0x05, 0xc7, 0xb9, 0x1a, 0xc3, 0x55, 0x34, 0xe1, 0x30, 0x9c, 0xca, 0xd7,
1121 0xb8, 0x46, 0x5a, 0x0f, 0xc3, 0xdf, 0xc9, 0xd8, 0xb7, 0xa9, 0x6f, 0x34,
1122 0xea, 0x7b, 0xd0, 0xe3, 0x5f, 0xf7, 0x10, 0x8b, 0xcb, 0x4d, 0x19, 0x8f,
1123 0x31, 0x7e, 0x06, 0x63, 0x83, 0xf5, 0x8f, 0xdf, 0xdd, 0xc3, 0x75, 0x41,
1124 0xb9, 0x89, 0xbc, 0x68, 0x39, 0xca, 0x85, 0x00, 0xe7, 0xbf, 0xa9, 0x95,
1125 0xea, 0x2c, 0x67, 0x41, 0xb3, 0x69, 0x30, 0xc5, 0x69, 0xaf, 0x75, 0x5e,
1126 0x96, 0xb5, 0x8e, 0xfa, 0x9b, 0x9e, 0x11, 0xd0, 0x16, 0xdd, 0xfd, 0x12,
1127 0xe9, 0xf3, 0x69, 0xf9, 0x77, 0x00, 0x29, 0x67, 0x58, 0xfe, 0x3d, 0x42,
1128 0x1f, 0xf6, 0x11, 0xf3, 0x3b, 0xdb, 0xee, 0x56, 0xa9, 0xa0, 0x7c, 0x76,
1129 0xa7, 0xfa, 0x3b, 0x08, 0x91, 0x86, 0xed, 0xde, 0xb6, 0x0d, 0x67, 0x83,
1130 0x5c, 0x5f, 0xdd, 0x2a, 0xf3, 0x67, 0xf8, 0xd1, 0x93, 0xc3, 0x7d, 0x03,
1131 0xd4, 0xb3, 0x9d, 0x4e, 0x0d, 0x73, 0xad, 0xb5, 0x19, 0xf8, 0x78, 0xad,
1132 0x9d, 0x2d, 0x88, 0xed, 0x74, 0x7a, 0x11, 0x7e, 0x76, 0xd1, 0x76, 0x59,
1133 0x97, 0x97, 0x86, 0xd3, 0xf0, 0xcf, 0x63, 0x03, 0x1c, 0x9f, 0x97, 0x5b,
1134 0xac, 0x2b, 0x7d, 0x80, 0x1f, 0x84, 0x5e, 0x6e, 0x82, 0x3d, 0x09, 0xec,
1135 0x1f, 0xe1, 0xfe, 0xb9, 0xc4, 0xdd, 0xe7, 0xec, 0xd9, 0x26, 0x75, 0x43,
1136 0xd8, 0xa6, 0x25, 0x40, 0xfb, 0x27, 0x6a, 0x44, 0x97, 0xf8, 0x6c, 0xb3,
1137 0x7e, 0xfb, 0xb7, 0xba, 0x37, 0xb5, 0x72, 0x9d, 0xff, 0x0e, 0x61, 0x98,
1138 0xf6, 0x41, 0xbf, 0x4c, 0xe7, 0x4d, 0xed, 0x81, 0xc6, 0xff, 0x14, 0x6e,
1139 0x75, 0xb1, 0x71, 0x5c, 0x55, 0xf8, 0xdc, 0x59, 0xaf, 0xed, 0x38, 0x6b,
1140 0x67, 0xe2, 0x6c, 0xec, 0xb5, 0x15, 0xc4, 0xce, 0x7a, 0x12, 0x4f, 0xb5,
1141 0x8e, 0x3a, 0xb6, 0x12, 0xb4, 0x42, 0x96, 0x58, 0xed, 0x7a, 0x5d, 0x87,
1142 0x92, 0xb2, 0x85, 0x50, 0x05, 0x09, 0x55, 0x96, 0x9d, 0xd2, 0x54, 0x80,
1143 0x90, 0xfa, 0x80, 0x78, 0xcb, 0x6a, 0x6d, 0x87, 0xa4, 0xec, 0x76, 0x6d,
1144 0x62, 0xd7, 0x2f, 0x3c, 0x2c, 0xeb, 0x75, 0x6a, 0xbb, 0x9b, 0xac, 0x42,
1145 0xfb, 0x50, 0x9e, 0x62, 0x99, 0x92, 0xc2, 0x4b, 0x85, 0xc4, 0x03, 0x02,
1146 0x54, 0xa9, 0x4a, 0xda, 0x34, 0x0f, 0x25, 0x11, 0xbc, 0x50, 0x0a, 0xd2,
1147 0xf0, 0x7d, 0x77, 0x66, 0x1d, 0x27, 0x50, 0x61, 0x69, 0x35, 0x77, 0xee,
1148 0xdc, 0x3b, 0x73, 0x7f, 0xce, 0xf9, 0xce, 0x77, 0xce, 0x3d, 0x66, 0x1b,
1149 0x1b, 0x65, 0xfa, 0xd3, 0xab, 0x6a, 0xa6, 0xda, 0x2b, 0x0b, 0x90, 0xe3,
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1168 0xc8, 0xe4, 0xba, 0x73, 0xbe, 0xcf, 0x71, 0x6c, 0xa8, 0xa3, 0x2f, 0xda,
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1173 0x2d, 0xd6, 0xfd, 0xb0, 0xcf, 0xaf, 0x8b, 0x07, 0xbe, 0x13, 0x7d, 0xac,
1174 0x2a, 0xe6, 0xf6, 0xb2, 0x34, 0x57, 0x7f, 0x2c, 0x6f, 0x57, 0x7e, 0x24,
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1176 0x9e, 0x77, 0xc3, 0x3d, 0x03, 0x5f, 0xc1, 0xf3, 0xfe, 0xe0, 0x6e, 0x4b,
1177 0x62, 0xec, 0x3b, 0x98, 0x73, 0x1e, 0x3a, 0x44, 0x2c, 0x9c, 0x82, 0xbc,
1178 0x25, 0xfb, 0xa5, 0x2b, 0xa2, 0xe5, 0x64, 0x68, 0x2c, 0x8c, 0x39, 0x18,
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1180 0x3f, 0x0c, 0xbd, 0xd8, 0x8f, 0x9f, 0x92, 0x7b, 0xa3, 0x18, 0xeb, 0x28,
1181 0x65, 0x2f, 0x2c, 0x89, 0x27, 0x31, 0x8f, 0x7c, 0x9b, 0xdc, 0x2f, 0x5d,
1182 0xe9, 0x63, 0x5c, 0xee, 0x7e, 0x89, 0x65, 0xe3, 0x4b, 0x3d, 0xe2, 0x49,
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1186 0x22, 0xd9, 0x12, 0x73, 0xb0, 0x98, 0x0f, 0x85, 0x31, 0x9e, 0x21, 0x6e,
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1199 0x12, 0xdf, 0x84, 0xbd, 0x2c, 0xb5, 0xea, 0x23, 0xf2, 0x49, 0xe9, 0xb3,
1200 0x3e, 0x9e, 0x93, 0xfc, 0xb5, 0x64, 0xca, 0x47, 0x25, 0x7d, 0x7e, 0x3a,
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1202 0xf4, 0xfc, 0xba, 0xea, 0x44, 0xdb, 0x08, 0xda, 0x71, 0x1c, 0xa6, 0xe4,
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1222 0x9f, 0x5c, 0x9b, 0xb8, 0x9a, 0xbc, 0xc2, 0xf1, 0x0c, 0x4a, 0x6e, 0x19,
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1233 0xfe, 0xc7, 0x56, 0x25, 0x23, 0x1b, 0xab, 0x93, 0xb2, 0xb9, 0xea, 0xe7,
1234 0x1c, 0xbf, 0xcb, 0x3c, 0xad, 0x51, 0xee, 0x93, 0x03, 0x1c, 0xda, 0x27,
1235 0x89, 0xe3, 0xc4, 0x8f, 0x4e, 0x59, 0x2b, 0xaf, 0x69, 0x1c, 0x5a, 0x2b,
1236 0xb3, 0x1c, 0x12, 0x9d, 0xf3, 0x75, 0x66, 0x5b, 0x6a, 0xee, 0x16, 0xea,
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1243 0xb1, 0x77, 0xad, 0xf9, 0x27, 0xbc, 0xc7, 0x3a, 0x9b, 0x96, 0x3f, 0xf6,
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1251 0xf3, 0xfe, 0xe9, 0xce, 0xc8, 0xdb, 0xab, 0x9e, 0x9c, 0x76, 0x8d, 0x81,
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1254 0xc4, 0x9c, 0x8c, 0x6d, 0x9f, 0xaf, 0x29, 0x05, 0x7c, 0x3b, 0xe0, 0xf3,
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1257 0x1c, 0x79, 0xac, 0x6c, 0xe2, 0xea, 0x18, 0xc5, 0xf2, 0x7d, 0x6f, 0x48,
1258 0xc7, 0xfe, 0xc1, 0x49, 0x4c, 0xcf, 0x9b, 0x75, 0xf9, 0xbd, 0x03, 0x8c,
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1263 0x7d, 0xad, 0x18, 0xf3, 0xf7, 0x1c, 0x7a, 0x9c, 0xe7, 0xf9, 0x40, 0xaf,
1264 0x64, 0xd7, 0xcf, 0x40, 0x27, 0x62, 0x58, 0xdb, 0xb0, 0xd6, 0x87, 0x1d,
1265 0xd8, 0xef, 0x1d, 0x27, 0x1c, 0x60, 0x6a, 0x27, 0xee, 0xd9, 0x6e, 0x12,
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1267 0x48, 0x0e, 0xe5, 0x10, 0xea, 0xe2, 0x41, 0x99, 0xdc, 0x6b, 0x1a, 0xe5,
1268 0x36, 0x5c, 0xd9, 0xe6, 0x28, 0x78, 0x05, 0xae, 0xbf, 0xc0, 0xfb, 0x46,
1269 0x31, 0xe6, 0xbc, 0x29, 0xef, 0x9d, 0xa4, 0x2d, 0x71, 0x0c, 0xe6, 0x1a,
1270 0xcf, 0xda, 0xb8, 0x36, 0xca, 0x2a, 0xbb, 0xc8, 0x32, 0xae, 0x55, 0xff,
1271 0xf9, 0x23, 0x98, 0x84, 0x3e, 0x99, 0x15, 0x1f, 0x93, 0xde, 0xdb, 0xc5,
1272 0x24, 0xd6, 0x75, 0xc8, 0xc4, 0x52, 0x5c, 0x9d, 0xba, 0x62, 0x42, 0xde,
1273 0xba, 0x24, 0xbb, 0x12, 0xd5, 0x7c, 0xb4, 0x06, 0x59, 0x5c, 0x87, 0x5c,
1274 0xad, 0x41, 0xa6, 0x32, 0x65, 0x2b, 0x35, 0xad, 0xe2, 0x3a, 0x2e, 0x30,
1275 0x05, 0x79, 0x0d, 0xbf, 0x4a, 0x2e, 0x4a, 0xfd, 0x75, 0xd0, 0x46, 0x68,
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1277 0x51, 0x1a, 0x57, 0x53, 0x77, 0x24, 0xe9, 0xdc, 0x11, 0xcb, 0xdd, 0xc1,
1278 0xef, 0x37, 0xe2, 0xca, 0x55, 0xe8, 0xfb, 0xeb, 0xf8, 0x4e, 0xf8, 0x35,
1279 0x43, 0x8e, 0x0d, 0x6b, 0x9d, 0x4e, 0x49, 0xc8, 0x72, 0x36, 0xc5, 0xd7,
1280 0xf1, 0x75, 0xad, 0xe3, 0x90, 0x37, 0x60, 0x90, 0xaf, 0xd3, 0xe9, 0x40,
1281 0x46, 0xbf, 0x01, 0xfd, 0xb5, 0xe0, 0x95, 0xc5, 0x65, 0x1e, 0xfa, 0x7f,
1282 0x15, 0xcf, 0x6f, 0x36, 0x3f, 0x56, 0x73, 0x8b, 0x2a, 0xc8, 0x3f, 0x79,
1283 0x0e, 0x3c, 0xf9, 0xf7, 0x58, 0xbb, 0x1e, 0xcd, 0xdd, 0x13, 0xa3, 0x3c,
1284 0x07, 0xfb, 0xb7, 0xba, 0x64, 0x1f, 0x97, 0xdb, 0x23, 0x27, 0x50, 0xee,
1285 0xc6, 0xd5, 0xc0, 0x3a, 0x44, 0xf4, 0xf9, 0xf5, 0x5a, 0x69, 0xc4, 0x28,
1286 0xea, 0x33, 0xe6, 0x31, 0xf4, 0x25, 0x96, 0x1d, 0xc6, 0x73, 0xc6, 0x65,
1287 0x38, 0x37, 0x70, 0x26, 0x15, 0xd3, 0x39, 0xa1, 0x35, 0x70, 0x89, 0x75,
1288 0xbc, 0xef, 0x16, 0xe3, 0x7a, 0x0d, 0xe8, 0xf0, 0xc8, 0x67, 0x5e, 0x3a,
1289 0xca, 0xbc, 0xf3, 0xf7, 0x63, 0xbe, 0xfd, 0xfb, 0xc4, 0xbb, 0x6d, 0xcf,
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1295 0xcf, 0xb9, 0x70, 0x0e, 0xf0, 0x6d, 0x4c, 0x53, 0xcb, 0xe8, 0x4e, 0xc3,
1296 0x18, 0xf0, 0x65, 0xb4, 0x35, 0x8f, 0xe8, 0xff, 0x99, 0x07, 0xe5, 0x64,
1297 0xc4, 0xf0, 0xcf, 0xdb, 0x71, 0x6d, 0x70, 0x3d, 0x3f, 0x06, 0xbf, 0xdf,
1298 0x2b, 0x3f, 0xad, 0x38, 0xa3, 0x2f, 0x3f, 0x4f, 0xec, 0xca, 0x0f, 0x7d,
1299 0xd4, 0x2e, 0xc9, 0xad, 0xd8, 0x32, 0x59, 0xd6, 0xfb, 0x0d, 0xae, 0xc9,
1300 0xf8, 0xd1, 0x09, 0xc8, 0x0d, 0x65, 0x9d, 0xba, 0x65, 0x4a, 0x15, 0x72,
1301 0x54, 0x05, 0x3e, 0x55, 0x21, 0x53, 0xe4, 0x40, 0x55, 0xe0, 0x5b, 0xb5,
1302 0x69, 0x39, 0x75, 0xcc, 0x99, 0x36, 0x7b, 0x1d, 0x72, 0x74, 0xb5, 0xc9,
1303 0xfd, 0xd7, 0x63, 0x36, 0x69, 0x07, 0x6f, 0xee, 0xee, 0xfd, 0xa7, 0xd8,
1304 0xfb, 0x23, 0x72, 0x0d, 0x7e, 0xcb, 0xf5, 0xca, 0x08, 0x30, 0x49, 0x80,
1305 0x51, 0x2e, 0x64, 0x23, 0x25, 0x1b, 0x95, 0x71, 0xd9, 0x84, 0x7d, 0xda,
1306 0x5a, 0x4d, 0x80, 0x4f, 0x03, 0x47, 0xaf, 0x1c, 0x93, 0x37, 0x56, 0x95,
1307 0xcc, 0xd8, 0xb0, 0x33, 0x6b, 0x8c, 0xc1, 0x43, 0x9e, 0xab, 0x5d, 0xfa,
1308 0xbc, 0x7d, 0xa2, 0xee, 0xc7, 0xe2, 0x73, 0xf5, 0x1e, 0x99, 0xac, 0x9b,
1309 0xf2, 0x54, 0xbd, 0x57, 0xbe, 0x5a, 0x8f, 0xca, 0xe9, 0x46, 0x4c, 0xbe,
1310 0x56, 0x1f, 0x94, 0xa7, 0xeb, 0x47, 0xe4, 0x99, 0x46, 0x5c, 0xbe, 0x0e,
1311 0xbf, 0x30, 0xdf, 0x70, 0x64, 0xaa, 0x31, 0x22, 0xa7, 0x1a, 0x8c, 0xb1,
1312 0xe3, 0x7b, 0xf8, 0x65, 0x77, 0x63, 0x17, 0x1c, 0x57, 0x27, 0xc6, 0xe5,
1313 0xa8, 0x9c, 0x3e, 0x6f, 0x94, 0xbc, 0x1f, 0xff, 0x10, 0x79, 0x01, 0x7d,
1314 0x17, 0xae, 0x28, 0xa9, 0xe9, 0xef, 0xb7, 0xfe, 0x47, 0x24, 0xa2, 0x7d,
1315 0xa3, 0x17, 0xaa, 0x83, 0x68, 0x63, 0xd3, 0x27, 0x09, 0xe2, 0x20, 0xad,
1316 0xf8, 0x7f, 0xcb, 0xf7, 0x32, 0x74, 0x0c, 0xfb, 0x26, 0x7d, 0x2f, 0xbd,
1317 0xf6, 0xc4, 0x0f, 0xfa, 0x39, 0xf4, 0xb5, 0xf6, 0x9e, 0x51, 0xb4, 0xbe,
1318 0xbb, 0x90, 0x7f, 0xf4, 0x7f, 0x51, 0xfc, 0xb3, 0xa6, 0x73, 0x8d, 0x41,
1319 0xfe, 0x4f, 0x0a, 0xc6, 0xf2, 0xf9, 0xf9, 0xdd, 0x93, 0x95, 0x09, 0xf5,
1320 0x54, 0x85, 0x8c, 0xc6, 0x93, 0x85, 0xdd, 0x3c, 0xba, 0xaf, 0xc8, 0x9a,
1321 0x1b, 0xd1, 0x63, 0xf0, 0xe3, 0xf6, 0x69, 0x9d, 0x53, 0x37, 0x31, 0x4c,
1322 0xf9, 0xe3, 0x19, 0x5a, 0x4f, 0x70, 0xb6, 0x00, 0x6e, 0xeb, 0x9a, 0x72,
1323 0xb1, 0xee, 0xc7, 0xaf, 0xe6, 0xb4, 0xbc, 0x5c, 0x87, 0xcc, 0xf1, 0xfc,
1324 0xc1, 0xbf, 0x16, 0xaa, 0x7e, 0xdf, 0xec, 0xb0, 0x43, 0x7f, 0x1c, 0xf3,
1325 0x35, 0x7a, 0xf9, 0x2d, 0xfe, 0x4f, 0x0e, 0xca, 0xc1, 0x78, 0x99, 0x0f,
1326 0x6c, 0x6b, 0x59, 0xf4, 0xcf, 0x67, 0x1d, 0x79, 0x11, 0x7b, 0x51, 0x33,
1327 0x39, 0xfe, 0x4e, 0xa9, 0x39, 0xf4, 0x6d, 0x89, 0xdf, 0xc3, 0x52, 0xc5,
1328 0x77, 0x6a, 0x4e, 0x2b, 0x36, 0xe6, 0xe3, 0x6c, 0xcd, 0x7c, 0xf8, 0xdd,
1329 0xe9, 0xea, 0x41, 0xdc, 0xa3, 0xce, 0x01, 0x67, 0x3a, 0xc3, 0xfb, 0x05,
1330 0x94, 0x19, 0x1b, 0x99, 0xc3, 0x35, 0x16, 0xd4, 0xfd, 0x7c, 0x40, 0x73,
1331 0xf5, 0xf1, 0x87, 0xfd, 0x66, 0xaa, 0x56, 0x21, 0x13, 0xba, 0xab, 0x8c,
1332 0x9f, 0xad, 0x0f, 0x10, 0x73, 0x0f, 0xda, 0xfc, 0x45, 0xe4, 0x6f, 0xa6,
1333 0x8e, 0x29, 0x04, 0xcf, 0xf6, 0xc9, 0xb3, 0x26, 0x73, 0xcd, 0xd3, 0x6a,
1334 0xa2, 0xf2, 0x72, 0x90, 0x57, 0x7b, 0x57, 0x1d, 0xac, 0x35, 0x07, 0xfc,
1335 0xbc, 0x74, 0xbe, 0x7b, 0x6f, 0x2e, 0xfa, 0x5e, 0x39, 0x61, 0x4e, 0x7a,
1336 0x07, 0x78, 0xab, 0x36, 0x62, 0xd0, 0x41, 0xe0, 0x9d, 0xdd, 0xa6, 0xf5,
1337 0xb1, 0xd8, 0xf8, 0x97, 0xb7, 0xad, 0xf5, 0xb9, 0x15, 0x63, 0xb8, 0x35,
1338 0x40, 0xdf, 0x96, 0xb8, 0x71, 0xd1, 0x8f, 0x1b, 0x69, 0x1f, 0x1a, 0x58,
1339 0x81, 0x3a, 0xea, 0x2a, 0xf4, 0x64, 0xb7, 0x2d, 0xff, 0xfe, 0x03, 0x7d,
1340 0xe7, 0x95, 0xf0, 0x2c, 0x67, 0x00, 0x00, 0x00 };
1052 1341
1053static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; 1342static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x0 };
1054static u32 bnx2_RXP_b06FwRodata[(0x28/4) + 1] = { 1343static u32 bnx2_RXP_b06FwRodata[(0x278/4) + 1] = {
1055 0x0800468c, 0x0800458c, 0x08004630, 0x08004648, 0x08004660, 0x08004680, 1344 0x08003fdc, 0x08003edc, 0x08003f80, 0x08003f98, 0x08003fb0, 0x08003fd0,
1056 0x0800468c, 0x0800468c, 0x08004594, 0x00000000, 0x00000000 }; 1345 0x08003fdc, 0x08003fdc, 0x08003ee4, 0x00000000, 0x08004a04, 0x08004a3c,
1057static u32 bnx2_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 }; 1346 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004a74, 0x08004c38,
1058static u32 bnx2_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; 1347 0x08004b80, 0x08004bb8, 0x08004c38, 0x08004b08, 0x08004c38, 0x08004c38,
1348 0x08004bb8, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1349 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004bf8,
1350 0x08004c38, 0x08004bf8, 0x08004b80, 0x08004c38, 0x08004c38, 0x08004bf8,
1351 0x08004bf8, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1352 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1353 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1354 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1355 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1356 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1357 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1358 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1359 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1360 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1361 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1362 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1363 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1364 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1365 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1366 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38,
1367 0x08004ae4, 0x00000000, 0x08006018, 0x08006030, 0x08006030, 0x08006030,
1368 0x08006018, 0x08006030, 0x08006030, 0x08006030, 0x08006018, 0x08006030,
1369 0x08006030, 0x08006030, 0x08006018, 0x08006030, 0x08006030, 0x08006030,
1370 0x08006024, 0x00000000, 0x00000000 };
1371
1372static u32 bnx2_RXP_b06FwBss[(0x13dc/4) + 1] = { 0x0 };
1373static u32 bnx2_RXP_b06FwSbss[(0x2c/4) + 1] = { 0x0 };
1374
1375static struct fw_info bnx2_rxp_fw_06 = {
1376 .ver_major = 0x2,
1377 .ver_minor = 0x8,
1378 .ver_fix = 0x17,
1379
1380 .start_addr = 0x08003184,
1381
1382 .text_addr = 0x08000000,
1383 .text_len = 0x6728,
1384 .text_index = 0x0,
1385 .gz_text = bnx2_RXP_b06FwText,
1386 .gz_text_len = sizeof(bnx2_RXP_b06FwText),
1387
1388 .data_addr = 0x080069c0,
1389 .data_len = 0x0,
1390 .data_index = 0x0,
1391 .data = bnx2_RXP_b06FwData,
1392
1393 .sbss_addr = 0x080069c0,
1394 .sbss_len = 0x2c,
1395 .sbss_index = 0x0,
1396 .sbss = bnx2_RXP_b06FwSbss,
1397
1398 .bss_addr = 0x080069f0,
1399 .bss_len = 0x13dc,
1400 .bss_index = 0x0,
1401 .bss = bnx2_RXP_b06FwBss,
1402
1403 .rodata_addr = 0x08006728,
1404 .rodata_len = 0x278,
1405 .rodata_index = 0x0,
1406 .rodata = bnx2_RXP_b06FwRodata,
1407};
1059 1408
1060static u8 bnx2_rv2p_proc1[] = { 1409static u8 bnx2_rv2p_proc1[] = {
1061 0x1f, 0x8b, 0x08, 0x08, 0x5e, 0xd0, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, 1410 0x1f, 0x8b, 0x08, 0x08, 0x5e, 0xd0, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
@@ -1316,20 +1665,6 @@ static u8 bnx2_rv2p_proc2[] = {
1316 0x63, 0xd6, 0x11, 0x8f, 0x47, 0xd5, 0x5f, 0x3f, 0x97, 0x8f, 0x31, 0xd8, 1665 0x63, 0xd6, 0x11, 0x8f, 0x47, 0xd5, 0x5f, 0x3f, 0x97, 0x8f, 0x31, 0xd8,
1317 0x17, 0x00, 0x00, 0x00 }; 1666 0x17, 0x00, 0x00, 0x00 };
1318 1667
1319static const int bnx2_TPAT_b06FwReleaseMajor = 0x1;
1320static const int bnx2_TPAT_b06FwReleaseMinor = 0x0;
1321static const int bnx2_TPAT_b06FwReleaseFix = 0x0;
1322static const u32 bnx2_TPAT_b06FwStartAddr = 0x08000860;
1323static const u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
1324static const int bnx2_TPAT_b06FwTextLen = 0x122c;
1325static const u32 bnx2_TPAT_b06FwDataAddr = 0x08001a60;
1326static const int bnx2_TPAT_b06FwDataLen = 0x0;
1327static const u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
1328static const int bnx2_TPAT_b06FwRodataLen = 0x0;
1329static const u32 bnx2_TPAT_b06FwBssAddr = 0x08001aa0;
1330static const int bnx2_TPAT_b06FwBssLen = 0x250;
1331static const u32 bnx2_TPAT_b06FwSbssAddr = 0x08001a60;
1332static const int bnx2_TPAT_b06FwSbssLen = 0x34;
1333static u8 bnx2_TPAT_b06FwText[] = { 1668static u8 bnx2_TPAT_b06FwText[] = {
1334 0x1f, 0x8b, 0x08, 0x08, 0x47, 0xd2, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, 1669 0x1f, 0x8b, 0x08, 0x08, 0x47, 0xd2, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
1335 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x57, 0x4d, 0x68, 1670 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x57, 0x4d, 0x68,
@@ -1529,20 +1864,40 @@ static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
1529static u32 bnx2_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 }; 1864static u32 bnx2_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
1530static u32 bnx2_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 }; 1865static u32 bnx2_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
1531 1866
1532static const int bnx2_TXP_b06FwReleaseMajor = 0x1; 1867static struct fw_info bnx2_tpat_fw_06 = {
1533static const int bnx2_TXP_b06FwReleaseMinor = 0x0; 1868 .ver_major = 0x1,
1534static const int bnx2_TXP_b06FwReleaseFix = 0x0; 1869 .ver_minor = 0x0,
1535static const u32 bnx2_TXP_b06FwStartAddr = 0x080034b0; 1870 .ver_fix = 0x0,
1536static const u32 bnx2_TXP_b06FwTextAddr = 0x08000000; 1871
1537static const int bnx2_TXP_b06FwTextLen = 0x5748; 1872 .start_addr = 0x08000860,
1538static const u32 bnx2_TXP_b06FwDataAddr = 0x08005760; 1873
1539static const int bnx2_TXP_b06FwDataLen = 0x0; 1874 .text_addr = 0x08000800,
1540static const u32 bnx2_TXP_b06FwRodataAddr = 0x00000000; 1875 .text_len = 0x122c,
1541static const int bnx2_TXP_b06FwRodataLen = 0x0; 1876 .text_index = 0x0,
1542static const u32 bnx2_TXP_b06FwBssAddr = 0x080057a0; 1877 .gz_text = bnx2_TPAT_b06FwText,
1543static const int bnx2_TXP_b06FwBssLen = 0x1c4; 1878 .gz_text_len = sizeof(bnx2_TPAT_b06FwText),
1544static const u32 bnx2_TXP_b06FwSbssAddr = 0x08005760; 1879
1545static const int bnx2_TXP_b06FwSbssLen = 0x38; 1880 .data_addr = 0x08001a60,
1881 .data_len = 0x0,
1882 .data_index = 0x0,
1883 .data = bnx2_TPAT_b06FwData,
1884
1885 .sbss_addr = 0x08001a60,
1886 .sbss_len = 0x34,
1887 .sbss_index = 0x0,
1888 .sbss = bnx2_TPAT_b06FwSbss,
1889
1890 .bss_addr = 0x08001aa0,
1891 .bss_len = 0x250,
1892 .bss_index = 0x0,
1893 .bss = bnx2_TPAT_b06FwBss,
1894
1895 .rodata_addr = 0x00000000,
1896 .rodata_len = 0x0,
1897 .rodata_index = 0x0,
1898 .rodata = bnx2_TPAT_b06FwRodata,
1899};
1900
1546static u8 bnx2_TXP_b06FwText[] = { 1901static u8 bnx2_TXP_b06FwText[] = {
1547 0x1f, 0x8b, 0x08, 0x08, 0x21, 0xd3, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, 1902 0x1f, 0x8b, 0x08, 0x08, 0x21, 0xd3, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
1548 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x6d, 0x6c, 1903 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x6d, 0x6c,
@@ -1964,3 +2319,38 @@ static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };
1964static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 }; 2319static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };
1965static u32 bnx2_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 }; 2320static u32 bnx2_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 };
1966static u32 bnx2_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 }; 2321static u32 bnx2_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 };
2322
2323static struct fw_info bnx2_txp_fw_06 = {
2324 .ver_major = 0x1,
2325 .ver_minor = 0x0,
2326 .ver_fix = 0x0,
2327
2328 .start_addr = 0x080034b0,
2329
2330 .text_addr = 0x08000000,
2331 .text_len = 0x5748,
2332 .text_index = 0x0,
2333 .gz_text = bnx2_TXP_b06FwText,
2334 .gz_text_len = sizeof(bnx2_TXP_b06FwText),
2335
2336 .data_addr = 0x08005760,
2337 .data_len = 0x0,
2338 .data_index = 0x0,
2339 .data = bnx2_TXP_b06FwData,
2340
2341 .sbss_addr = 0x08005760,
2342 .sbss_len = 0x38,
2343 .sbss_index = 0x0,
2344 .sbss = bnx2_TXP_b06FwSbss,
2345
2346 .bss_addr = 0x080057a0,
2347 .bss_len = 0x1c4,
2348 .bss_index = 0x0,
2349 .bss = bnx2_TXP_b06FwBss,
2350
2351 .rodata_addr = 0x00000000,
2352 .rodata_len = 0x0,
2353 .rodata_index = 0x0,
2354 .rodata = bnx2_TXP_b06FwRodata,
2355};
2356
diff --git a/drivers/net/bnx2_fw2.h b/drivers/net/bnx2_fw2.h
new file mode 100644
index 000000000000..680c769a3fc0
--- /dev/null
+++ b/drivers/net/bnx2_fw2.h
@@ -0,0 +1,4086 @@
1/* bnx2_fw2.h: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2006 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, except as noted below.
8 *
9 * This file contains firmware data derived from proprietary unpublished
10 * source code, Copyright (c) 2006 Broadcom Corporation.
11 *
12 * Permission is hereby granted for the distribution of this firmware data
13 * in hexadecimal or equivalent format, provided this copyright notice is
14 * accompanying it.
15 */
16
17static u8 bnx2_COM_b09FwText[] = {
18 0x1f, 0x8b, 0x08, 0x08, 0xac, 0xfb, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
19 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xdc, 0x5b, 0x6b, 0x70,
20 0x1b, 0xd7, 0x75, 0x3e, 0xfb, 0x00, 0x09, 0x91, 0x10, 0xb5, 0xa4, 0x60,
21 0x1a, 0x96, 0x68, 0x07, 0x20, 0x57, 0x22, 0x6a, 0xb1, 0x29, 0x4c, 0x33,
22 0x16, 0x9b, 0xc2, 0x12, 0x02, 0x50, 0xae, 0x26, 0xc3, 0x3a, 0x94, 0xcd,
23 0xd8, 0x4a, 0xaa, 0xc9, 0x30, 0x00, 0xa5, 0xf4, 0x61, 0xb7, 0x92, 0xab,
24 0xa9, 0x5d, 0xd7, 0xaa, 0x21, 0x92, 0x6a, 0xf5, 0x83, 0xe5, 0x2a, 0x16,
25 0x43, 0xa9, 0xd3, 0x74, 0xc2, 0x12, 0x56, 0xac, 0x4e, 0x31, 0x85, 0xfc,
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228 0xa6, 0x95, 0xef, 0xe8, 0xeb, 0x96, 0xf7, 0xdd, 0xb8, 0xbe, 0x61, 0x0c,
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259 0xdb, 0x3c, 0x7f, 0xcb, 0x1c, 0x80, 0xf1, 0xb7, 0xab, 0xb3, 0xd9, 0xd4,
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772 0xe5, 0xfe, 0x62, 0xe9, 0xe6, 0x5c, 0xd8, 0xfd, 0x3c, 0x32, 0x92, 0xe1,
773 0x4e, 0xa1, 0x23, 0xad, 0xac, 0xfa, 0xf8, 0xd9, 0x11, 0x2b, 0x39, 0xc5,
774 0x73, 0xcc, 0xb9, 0xe7, 0x5d, 0xba, 0x19, 0x0b, 0x63, 0x9c, 0xbf, 0x66,
775 0x1c, 0xdb, 0xca, 0x53, 0x72, 0x3d, 0x85, 0x5c, 0xe9, 0xe7, 0xd1, 0xb0,
776 0x5e, 0x9f, 0xfb, 0x5a, 0xac, 0x03, 0xf4, 0xc4, 0x9f, 0x2b, 0x5d, 0xbe,
777 0x2b, 0x59, 0xd8, 0xdf, 0x06, 0xe3, 0x39, 0x66, 0x34, 0x44, 0xa9, 0x15,
778 0xa6, 0xef, 0x8b, 0x1d, 0xbe, 0x8d, 0xec, 0x95, 0x52, 0xb2, 0x2a, 0x97,
779 0xa5, 0xda, 0xef, 0x2e, 0x6d, 0xae, 0x21, 0x72, 0x96, 0x20, 0x33, 0x21,
780 0x2f, 0x53, 0x25, 0xbf, 0x03, 0xfd, 0x0e, 0xb6, 0xd0, 0x59, 0xe6, 0x57,
781 0x32, 0x1f, 0x89, 0x79, 0x27, 0xf3, 0x2c, 0x49, 0x2f, 0xf1, 0xaa, 0xd7,
782 0x0d, 0x48, 0x9c, 0x1d, 0xa9, 0xe4, 0x41, 0xba, 0xe2, 0xe9, 0x01, 0x57,
783 0x3c, 0xdd, 0x74, 0xe5, 0x41, 0x06, 0x85, 0x3e, 0x56, 0xd1, 0xa1, 0x82,
784 0x4a, 0x87, 0x82, 0xae, 0x25, 0x79, 0x59, 0xa1, 0xcc, 0xcb, 0x76, 0x6f,
785 0xc1, 0xcb, 0xbc, 0x6c, 0xd3, 0x75, 0xc5, 0x37, 0xec, 0x30, 0xe4, 0xfc,
786 0xe5, 0xe2, 0x34, 0xbd, 0xcd, 0x3c, 0xe2, 0xad, 0x62, 0x98, 0xf9, 0xc6,
787 0x24, 0xf3, 0x8d, 0x09, 0xe6, 0x1b, 0x0e, 0xc3, 0xc0, 0xe2, 0xb5, 0x5f,
788 0xf3, 0x5d, 0x59, 0x84, 0xbc, 0x98, 0xa2, 0xe7, 0x8b, 0xe0, 0xc1, 0x93,
789 0xac, 0xf3, 0x5c, 0xf3, 0x6d, 0x2c, 0x76, 0x31, 0xbe, 0x4a, 0x3d, 0xa7,
790 0xda, 0x8e, 0x41, 0xaf, 0x15, 0xf8, 0x87, 0xaf, 0x82, 0xcf, 0xbc, 0x91,
791 0xa2, 0x4e, 0x86, 0x3d, 0xe0, 0xbc, 0x8e, 0xde, 0x14, 0xaf, 0x81, 0x96,
792 0xd1, 0x13, 0xf8, 0xbb, 0xe3, 0x53, 0x3c, 0xf7, 0x4e, 0xdf, 0x02, 0xef,
793 0xcb, 0xd3, 0xe1, 0x94, 0xd9, 0xcb, 0x38, 0x7f, 0xac, 0x82, 0xf3, 0xa9,
794 0x34, 0xaf, 0xa0, 0x67, 0xb9, 0x9b, 0xc6, 0x0e, 0x44, 0xf7, 0xf6, 0x30,
795 0x9d, 0x22, 0x37, 0xa2, 0xd2, 0xa7, 0xc7, 0x4f, 0x27, 0x83, 0x6d, 0xaa,
796 0xbf, 0x8f, 0xc5, 0xf2, 0xf1, 0x03, 0xbe, 0xcf, 0x2d, 0x5f, 0x3a, 0xfb,
797 0x2a, 0x3f, 0x03, 0xc7, 0x5f, 0x85, 0xff, 0x93, 0xed, 0x83, 0x56, 0xe1,
798 0x3f, 0x2a, 0x88, 0xb1, 0x38, 0xb6, 0x27, 0x98, 0x97, 0x85, 0xd7, 0x0d,
799 0x7b, 0x3a, 0x62, 0x30, 0xd1, 0x75, 0x99, 0xbc, 0xde, 0xd2, 0xa0, 0x8c,
800 0xc1, 0xed, 0xdd, 0x2b, 0xf9, 0x06, 0xe3, 0x66, 0x30, 0x22, 0x6c, 0xb4,
801 0xa6, 0x25, 0x29, 0x27, 0x0b, 0xbc, 0xcf, 0x2b, 0xe1, 0x09, 0xde, 0xe7,
802 0x0e, 0x25, 0x23, 0x53, 0xfc, 0xbb, 0x90, 0xbf, 0x2c, 0x2b, 0x87, 0xd0,
803 0xb3, 0xda, 0x14, 0xfd, 0x20, 0x66, 0xd1, 0x6f, 0xa7, 0x83, 0xef, 0x6b,
804 0x33, 0xd6, 0x82, 0x4f, 0x7c, 0xe0, 0x4b, 0x66, 0xf1, 0x5c, 0xe0, 0x21,
805 0x7f, 0xcf, 0x4f, 0xd1, 0x85, 0x8c, 0x9e, 0xc3, 0x80, 0x61, 0xbc, 0x84,
806 0x79, 0xf8, 0x68, 0xb7, 0xf3, 0x43, 0x86, 0x17, 0x1f, 0xff, 0x71, 0xed,
807 0x9c, 0x86, 0xd5, 0x9c, 0xd0, 0xd3, 0xb2, 0x05, 0x3d, 0x7c, 0x08, 0xbd,
808 0x8f, 0x0a, 0xa2, 0xe7, 0x64, 0xb3, 0xb0, 0x4d, 0x0b, 0xc2, 0xc6, 0x28,
809 0x85, 0x2a, 0x7d, 0x30, 0xef, 0xa9, 0x39, 0xf7, 0x13, 0x5f, 0x7a, 0xf1,
810 0xa0, 0xd0, 0xc5, 0x46, 0x0e, 0xec, 0x55, 0xf5, 0xa7, 0x5d, 0xe2, 0xbe,
811 0xc6, 0x32, 0x7e, 0x7b, 0x50, 0xfd, 0xf6, 0x49, 0xa1, 0x03, 0x23, 0x2f,
812 0x2e, 0xb0, 0x24, 0xf0, 0x9c, 0xf7, 0xd7, 0x99, 0x60, 0x3c, 0x0f, 0xad,
813 0xc0, 0x77, 0x2f, 0xe0, 0xa9, 0xe1, 0x01, 0x58, 0x00, 0xf7, 0x3b, 0x14,
814 0xde, 0xdb, 0x56, 0xdc, 0xaf, 0xd7, 0xdd, 0x08, 0xce, 0xac, 0xd3, 0x64,
815 0xb0, 0x56, 0xac, 0x69, 0x8f, 0x2f, 0x92, 0xb7, 0x8c, 0xf4, 0x22, 0x6c,
816 0x1a, 0xd4, 0xb5, 0xdc, 0x85, 0xbc, 0x29, 0x9e, 0xc3, 0x1e, 0x8a, 0x24,
817 0x30, 0x2f, 0x8c, 0xd3, 0x30, 0xf8, 0xb7, 0x1a, 0x58, 0xb8, 0xaf, 0xeb,
818 0x56, 0xd7, 0xb5, 0x8a, 0xbd, 0x20, 0x03, 0xcf, 0xd1, 0xcf, 0xc6, 0x73,
819 0xf1, 0x7c, 0x5c, 0x87, 0xfb, 0xc9, 0xfb, 0xf6, 0x31, 0x7f, 0x8e, 0x4e,
820 0xc9, 0x7b, 0x19, 0x97, 0xe4, 0x6f, 0x7d, 0x8e, 0xf7, 0x7c, 0xe5, 0xfe,
821 0xf9, 0x54, 0xbf, 0x1e, 0xec, 0x5f, 0x37, 0xe5, 0x85, 0x8f, 0x13, 0xbf,
822 0x75, 0x8a, 0xdf, 0xa2, 0x4e, 0xa7, 0xd8, 0xd7, 0xf3, 0x7c, 0x3c, 0x9f,
823 0xed, 0xf2, 0xc1, 0x36, 0x4f, 0x27, 0x3a, 0x7d, 0xf9, 0x3c, 0xd6, 0xdb,
824 0xe9, 0x8b, 0x33, 0xee, 0xc7, 0xb2, 0xf1, 0xd2, 0x82, 0xe0, 0x31, 0xac,
825 0xd3, 0xf6, 0xda, 0xe6, 0x49, 0xe3, 0x4f, 0x86, 0x64, 0x6f, 0x5b, 0x7c,
826 0x67, 0xfa, 0xcb, 0x30, 0xfd, 0x65, 0x98, 0xfe, 0x32, 0x4c, 0x7f, 0x19,
827 0xa6, 0x3f, 0xb6, 0x4b, 0xdf, 0x64, 0x99, 0xf1, 0x6d, 0x96, 0x19, 0x92,
828 0x66, 0x23, 0xca, 0x8f, 0xa9, 0x69, 0xb6, 0xb6, 0x3e, 0x53, 0xd3, 0x28,
829 0xe4, 0x34, 0xf9, 0x0e, 0x8f, 0x57, 0xd3, 0xea, 0x55, 0xa6, 0xd5, 0xa6,
830 0x99, 0x7e, 0xba, 0x91, 0xc3, 0x9e, 0xd9, 0xd6, 0x79, 0xe6, 0xd1, 0x71,
831 0x3f, 0x74, 0xaa, 0x00, 0xd3, 0x13, 0x74, 0x4a, 0x9b, 0xe1, 0xde, 0x4f,
832 0x37, 0x99, 0x4f, 0xdf, 0xc8, 0x81, 0x76, 0xef, 0x52, 0xc7, 0x19, 0xa6,
833 0x5d, 0xc8, 0xb9, 0x25, 0xdf, 0xd5, 0xac, 0xc1, 0xba, 0x57, 0xc0, 0x4c,
834 0x12, 0xf8, 0xa8, 0xd0, 0xc7, 0x78, 0xdf, 0xd7, 0x99, 0xdf, 0xc3, 0x57,
835 0x87, 0xbe, 0x5f, 0x79, 0x1f, 0xcb, 0x89, 0xd0, 0x15, 0xe6, 0xa3, 0xa7,
836 0x73, 0x4b, 0x4c, 0xef, 0xbd, 0xf4, 0x85, 0x1c, 0xe4, 0x31, 0x60, 0xc4,
837 0xc7, 0x79, 0x12, 0x3e, 0x30, 0x63, 0x06, 0x6b, 0x1f, 0x4b, 0x19, 0x02,
838 0x4f, 0x9e, 0x01, 0x1c, 0x18, 0xf6, 0x67, 0xf6, 0xa2, 0x67, 0x7d, 0xc4,
839 0x68, 0x56, 0x3e, 0x45, 0x7c, 0xc7, 0x78, 0x8c, 0x05, 0xdc, 0x70, 0xdc,
840 0x28, 0xfe, 0x88, 0xf7, 0x42, 0x84, 0x19, 0x1e, 0xb5, 0x7c, 0xeb, 0x02,
841 0x7a, 0x91, 0x02, 0x5e, 0xd3, 0x51, 0x3f, 0x6a, 0xc5, 0xe9, 0x39, 0xbc,
842 0xff, 0xe0, 0x85, 0x22, 0xe6, 0xbd, 0x48, 0x0b, 0x41, 0xf0, 0x21, 0x3b,
843 0x7c, 0x9d, 0x24, 0xec, 0x5a, 0x59, 0xbf, 0xfc, 0xbc, 0x37, 0x6f, 0xb3,
844 0xa2, 0x42, 0x1f, 0x6e, 0x61, 0xfb, 0x06, 0xb0, 0x79, 0x8b, 0x71, 0x2d,
845 0x0c, 0x9b, 0x5f, 0xf1, 0xb5, 0x37, 0x99, 0xe7, 0x60, 0xcf, 0x3a, 0x85,
846 0x8c, 0xf1, 0xe2, 0x65, 0x1b, 0x8a, 0x97, 0x39, 0x2e, 0x5e, 0x96, 0x2e,
847 0xf3, 0x32, 0xc6, 0x09, 0xc1, 0xc3, 0xc0, 0xa3, 0x66, 0x59, 0x4f, 0x94,
848 0xdf, 0xa1, 0xff, 0xed, 0x16, 0x3c, 0x8b, 0x79, 0x3d, 0xdb, 0x0d, 0x85,
849 0x62, 0xca, 0x77, 0x48, 0xf0, 0x0e, 0x8d, 0xd7, 0xff, 0xa3, 0xe8, 0xa1,
850 0x55, 0xf0, 0x81, 0xf4, 0x2c, 0xf8, 0x95, 0xd7, 0xf8, 0xff, 0x02, 0x6c,
851 0x79, 0xbc, 0x13, 0x7a, 0x8d, 0xf9, 0x58, 0x21, 0x0c, 0x9b, 0xb5, 0x43,
852 0xd9, 0x36, 0xe8, 0xbb, 0xb5, 0x07, 0xb9, 0x96, 0x56, 0xb4, 0xcc, 0xc7,
853 0x76, 0x2b, 0xbf, 0x05, 0xfc, 0x8c, 0xd8, 0xeb, 0x3a, 0x5d, 0xc0, 0x82,
854 0x2e, 0xc0, 0x63, 0x03, 0x0c, 0x1f, 0xd1, 0x1b, 0x9c, 0xe8, 0x16, 0xc3,
855 0x01, 0xfb, 0x7c, 0x0b, 0xfb, 0xcc, 0xba, 0x2c, 0x05, 0xe6, 0xa6, 0x02,
856 0x03, 0x98, 0xdf, 0xc2, 0x6a, 0x85, 0x1f, 0x9e, 0xcf, 0x0c, 0x18, 0x85,
857 0xac, 0x9c, 0xe3, 0xca, 0xb8, 0xe4, 0x79, 0x85, 0x3c, 0x7a, 0x7b, 0x89,
858 0xb9, 0xf2, 0x1c, 0xf5, 0xfa, 0x04, 0xff, 0x52, 0x74, 0xbf, 0x1d, 0x5a,
859 0x4b, 0x30, 0x5d, 0x61, 0x4f, 0x52, 0x2e, 0x9c, 0x79, 0x94, 0x9f, 0x8f,
860 0x73, 0x8d, 0xd7, 0x71, 0xb3, 0xbc, 0x8e, 0x08, 0xaf, 0x03, 0x63, 0x6f,
861 0xf9, 0x6e, 0xa8, 0x75, 0xdc, 0x28, 0xaf, 0x63, 0x56, 0xad, 0x83, 0xd2,
862 0xc6, 0xcc, 0x6e, 0xa5, 0xc7, 0x6f, 0x79, 0xcf, 0xd6, 0x28, 0xeb, 0x27,
863 0xe9, 0x55, 0xc0, 0xf3, 0x1e, 0x85, 0x2f, 0x6e, 0x7f, 0xa8, 0x7b, 0x6e,
864 0xf6, 0xc4, 0x75, 0xfa, 0x5d, 0xba, 0x29, 0xf4, 0x93, 0x61, 0xd6, 0x4f,
865 0x70, 0x9e, 0x16, 0xc0, 0x87, 0xd3, 0x41, 0xf4, 0x9b, 0x1d, 0x64, 0x98,
866 0xb1, 0x5d, 0x35, 0xc5, 0x9f, 0xc2, 0x4f, 0x86, 0xfb, 0xe8, 0xeb, 0xbf,
867 0x48, 0x37, 0x17, 0xc1, 0xab, 0xa1, 0x8f, 0xca, 0x9e, 0xb4, 0x37, 0xd7,
868 0xa4, 0x9f, 0x36, 0xee, 0xe9, 0xa7, 0x85, 0x8f, 0x36, 0x0c, 0x7d, 0xdd,
869 0x84, 0x3f, 0x37, 0x26, 0xde, 0x67, 0xc1, 0xc7, 0x45, 0xdc, 0xcb, 0x8b,
870 0xef, 0x4c, 0xbb, 0x72, 0xdc, 0x90, 0x73, 0x92, 0x62, 0x3e, 0xe2, 0x98,
871 0x4d, 0x86, 0xac, 0x9d, 0xb9, 0x5c, 0xd4, 0x3a, 0x51, 0x9c, 0xf7, 0xc8,
872 0x09, 0x1b, 0x46, 0x44, 0xf8, 0x0c, 0x5a, 0x9d, 0x0e, 0x6a, 0x61, 0x39,
873 0x79, 0x8a, 0xd0, 0x13, 0xcd, 0xb6, 0xe0, 0xcb, 0xbf, 0xc0, 0xb8, 0xb7,
874 0x10, 0xb6, 0x43, 0x9f, 0x13, 0xf6, 0x25, 0xe4, 0x07, 0xde, 0xa7, 0x02,
875 0x18, 0x63, 0x0e, 0xfc, 0x7d, 0x15, 0xfd, 0x30, 0xc3, 0xbc, 0x7e, 0xf8,
876 0x81, 0x47, 0xad, 0x77, 0x58, 0xee, 0x5c, 0x10, 0xfe, 0x95, 0xb3, 0x94,
877 0x66, 0x3a, 0x3c, 0x2c, 0xe8, 0xd0, 0x18, 0x66, 0x6a, 0x61, 0xfa, 0x41,
878 0x8e, 0xc1, 0x98, 0xe8, 0xbf, 0x23, 0x6d, 0x16, 0x5e, 0xe5, 0x9a, 0xea,
879 0x6b, 0x90, 0x00, 0x6f, 0xd8, 0xbe, 0x6f, 0x21, 0xf1, 0x91, 0x7d, 0x2a,
880 0x6e, 0x5d, 0xab, 0xd6, 0x87, 0x0d, 0xfb, 0xcc, 0x12, 0x7d, 0x1f, 0x01,
881 0x3b, 0xe1, 0x17, 0x34, 0x26, 0x19, 0x6e, 0xfa, 0xdd, 0x35, 0x6e, 0xfb,
882 0xff, 0x29, 0x51, 0x9f, 0xff, 0x46, 0x51, 0xca, 0xd8, 0x34, 0xdb, 0xe6,
883 0x0b, 0x07, 0xdc, 0x3a, 0x87, 0x9d, 0x8d, 0x09, 0x9f, 0xcc, 0x00, 0x45,
884 0x97, 0x27, 0xe9, 0xb1, 0x0c, 0x78, 0x14, 0x5d, 0x8f, 0x3a, 0x78, 0xc3,
885 0x06, 0x68, 0x79, 0x92, 0xe2, 0x45, 0xc0, 0xc8, 0x47, 0x0b, 0x2c, 0x05,
886 0xd2, 0x59, 0xc4, 0xee, 0xf9, 0x7b, 0x1e, 0xef, 0x57, 0xf9, 0x15, 0xe5,
887 0xf7, 0x1e, 0xa2, 0xd8, 0x32, 0xa5, 0x92, 0xe1, 0x87, 0x45, 0xcf, 0xea,
888 0x64, 0x78, 0x5c, 0xf9, 0x68, 0x42, 0x7c, 0x1e, 0x7e, 0x2f, 0x8b, 0x1e,
889 0xcd, 0xd8, 0xa9, 0x24, 0x49, 0xdf, 0x03, 0xf1, 0x1c, 0x0c, 0x96, 0xad,
890 0xbb, 0x99, 0x57, 0x1c, 0x17, 0xfe, 0x07, 0xd6, 0x44, 0x16, 0x31, 0x1e,
891 0xbe, 0x83, 0x5e, 0x82, 0xbd, 0x95, 0xcc, 0x3e, 0xa0, 0xc6, 0x96, 0xc8,
892 0x64, 0x5c, 0x30, 0x7f, 0xc9, 0x49, 0x85, 0x8d, 0xca, 0xf5, 0xf0, 0x5d,
893 0x1c, 0x17, 0xfa, 0xe1, 0x30, 0xdb, 0x30, 0x62, 0x5c, 0x69, 0x4e, 0xf8,
894 0x21, 0xf8, 0x38, 0xff, 0xd3, 0x01, 0xfd, 0x6e, 0x03, 0x9c, 0x97, 0xfe,
895 0x09, 0xbe, 0x67, 0x9e, 0xe7, 0x51, 0x95, 0x17, 0x3f, 0x44, 0x91, 0x1d,
896 0xf8, 0x8b, 0x66, 0xef, 0xa8, 0xbf, 0x88, 0x61, 0xcd, 0xb2, 0xe5, 0x32,
897 0xd3, 0xc6, 0xdb, 0x5b, 0xda, 0x71, 0xef, 0x6b, 0x19, 0xcd, 0xb0, 0x32,
898 0xc5, 0xfb, 0x2f, 0xd0, 0xeb, 0x73, 0xa1, 0xf8, 0x29, 0xbc, 0x47, 0xc6,
899 0x97, 0x10, 0x3a, 0x6f, 0x88, 0x75, 0x17, 0xe8, 0x30, 0xa3, 0x22, 0xbe,
900 0x15, 0x79, 0xc2, 0x32, 0x16, 0xd6, 0xfa, 0xc9, 0x0f, 0xbf, 0x9a, 0xa3,
901 0x73, 0x22, 0x5a, 0x45, 0xfe, 0xba, 0x8c, 0x2b, 0x42, 0xfe, 0x82, 0x07,
902 0xfe, 0xc4, 0x97, 0x5c, 0xf3, 0xf7, 0xe9, 0x7c, 0xb7, 0x48, 0xb0, 0x9c,
903 0x4f, 0xa3, 0x78, 0x8a, 0xc6, 0x3d, 0x1d, 0xb3, 0x70, 0xbf, 0xd7, 0x0a,
904 0xb4, 0xeb, 0xd6, 0x19, 0xe0, 0x67, 0x12, 0x7b, 0x74, 0x01, 0x71, 0x5c,
905 0xa3, 0x2a, 0x1e, 0xd1, 0xc2, 0xfb, 0x04, 0x3b, 0x0f, 0xfe, 0xbb, 0xcf,
906 0xf2, 0x27, 0xe2, 0x0a, 0x27, 0x07, 0xa1, 0x27, 0xf5, 0x38, 0x8c, 0x33,
907 0x53, 0x38, 0xee, 0x67, 0xbb, 0x4b, 0xeb, 0xb5, 0xd2, 0xa7, 0xc4, 0xb6,
908 0x98, 0xda, 0x2f, 0xf8, 0x93, 0x46, 0x54, 0xbf, 0x01, 0x9b, 0xac, 0x5e,
909 0xc0, 0xe9, 0xe3, 0xa2, 0xc7, 0xad, 0x62, 0x10, 0xdb, 0xc9, 0x59, 0xc2,
910 0x3b, 0xb7, 0xd0, 0x77, 0xf3, 0x6e, 0xc0, 0x9e, 0xf7, 0xc8, 0x1d, 0xa3,
911 0xf8, 0x94, 0x7a, 0xff, 0xcf, 0x9d, 0xda, 0xb7, 0x5d, 0x1e, 0xfb, 0xf6,
912 0xbd, 0x41, 0x19, 0x03, 0xbb, 0x4b, 0x8d, 0xf1, 0xca, 0x53, 0xfd, 0xfb,
913 0xa7, 0xe1, 0x4f, 0xaa, 0xd4, 0x51, 0x5c, 0x13, 0x7c, 0xa5, 0xde, 0xa7,
914 0x1d, 0x62, 0x7e, 0x2a, 0xe9, 0xf8, 0xb8, 0x07, 0x1d, 0xf7, 0xce, 0x40,
915 0x2f, 0xb9, 0x7d, 0x3a, 0x3e, 0xd6, 0x90, 0x8e, 0xff, 0x75, 0x50, 0xfa,
916 0x54, 0xeb, 0xe9, 0x18, 0xb5, 0x3c, 0xc7, 0x8b, 0x8d, 0xfc, 0x57, 0xd8,
917 0x07, 0xd4, 0xa4, 0xc3, 0xe7, 0x01, 0x58, 0x69, 0xbf, 0x07, 0xe2, 0x7e,
918 0xc0, 0x47, 0xc4, 0x4e, 0xfe, 0x90, 0xe2, 0x8b, 0xb5, 0xb1, 0xd0, 0xcd,
919 0xae, 0xf9, 0x96, 0xc7, 0x35, 0xd0, 0xc5, 0x41, 0x0b, 0x76, 0x48, 0xda,
920 0xf4, 0x1a, 0x5e, 0xef, 0xf9, 0x0e, 0xe5, 0xec, 0x54, 0x9e, 0xe0, 0xa3,
921 0x0e, 0xd2, 0x53, 0x88, 0x2b, 0x2b, 0x1f, 0xf0, 0xd1, 0x8c, 0x5c, 0xb7,
922 0x79, 0x40, 0xe0, 0x03, 0xf4, 0xd5, 0x50, 0xc2, 0x9f, 0xe0, 0x3d, 0x95,
923 0xfe, 0xdf, 0xe4, 0x6a, 0x48, 0xed, 0x13, 0x8f, 0xc5, 0xfd, 0x3c, 0xeb,
924 0xfc, 0xb0, 0x3f, 0xf6, 0xd7, 0xd7, 0xcb, 0x79, 0xc5, 0x90, 0x05, 0x25,
925 0xfa, 0x0f, 0x96, 0x73, 0xfe, 0x03, 0xa6, 0xe8, 0xb9, 0x70, 0xb9, 0x78,
926 0x80, 0xf5, 0x47, 0xec, 0x21, 0x7c, 0x87, 0xda, 0xb7, 0xfb, 0xf6, 0x30,
927 0x75, 0xed, 0x67, 0xa9, 0x6f, 0x90, 0xc3, 0x7a, 0xa3, 0x71, 0x00, 0xf9,
928 0xe1, 0x16, 0x5f, 0x83, 0x5e, 0x51, 0x63, 0x56, 0x9c, 0x3a, 0xe0, 0x4f,
929 0x40, 0x0f, 0x68, 0x2b, 0x5d, 0x45, 0x53, 0xb3, 0x82, 0xa6, 0xe2, 0x6b,
930 0xb3, 0x8a, 0xa6, 0x66, 0x95, 0xff, 0x7c, 0x56, 0xd1, 0xd4, 0xac, 0xa2,
931 0xa9, 0x59, 0x45, 0x53, 0xb3, 0x8c, 0xd7, 0xa3, 0xac, 0xaf, 0x42, 0xf7,
932 0xd0, 0xfe, 0xcb, 0x2e, 0x4a, 0xe6, 0x70, 0x1e, 0xf2, 0xb8, 0x96, 0xae,
933 0x7e, 0x6d, 0x58, 0xfb, 0x47, 0x0b, 0x32, 0xcf, 0x8e, 0x9f, 0x85, 0x3d,
934 0x78, 0x98, 0xe1, 0x77, 0xcd, 0x37, 0xbf, 0x88, 0xb9, 0xfa, 0x28, 0x26,
935 0x7a, 0xc0, 0x36, 0x51, 0xd4, 0xad, 0xe3, 0x9a, 0xa8, 0xeb, 0x92, 0xb6,
936 0x5c, 0xaa, 0x61, 0x8d, 0x97, 0xc6, 0x8b, 0x69, 0xb5, 0x5f, 0xb5, 0x76,
937 0x4e, 0x0b, 0x25, 0xb2, 0x80, 0x2b, 0x72, 0x21, 0x2d, 0xde, 0x1b, 0x01,
938 0xa7, 0x94, 0xe9, 0x01, 0x83, 0xa3, 0x0a, 0x06, 0x4f, 0x8b, 0x35, 0x22,
939 0x97, 0x10, 0x3e, 0xc8, 0xc6, 0x70, 0x48, 0x67, 0x46, 0xf9, 0x3e, 0x8c,
940 0xfb, 0x07, 0x42, 0xcc, 0x83, 0xb6, 0x0b, 0x07, 0xf7, 0xda, 0x1b, 0xf1,
941 0x9a, 0xed, 0xd6, 0xd3, 0x5c, 0x77, 0xc9, 0x8e, 0x90, 0x92, 0x1b, 0x52,
942 0xef, 0xdd, 0xe5, 0xd8, 0x89, 0x14, 0xcf, 0xed, 0x2f, 0xc2, 0x7f, 0x39,
943 0x44, 0x6d, 0x25, 0x3a, 0x12, 0x06, 0x3e, 0x77, 0xb1, 0x5d, 0xc9, 0x73,
944 0x18, 0x2b, 0xd1, 0x85, 0xf0, 0x3e, 0xb6, 0x5d, 0xf6, 0xb3, 0x0e, 0x3a,
945 0xca, 0xff, 0x4e, 0xc4, 0xef, 0xc3, 0xbc, 0x3a, 0xf8, 0xda, 0x7e, 0x32,
946 0x7a, 0x52, 0x66, 0x2b, 0xeb, 0x07, 0x47, 0x2a, 0xf6, 0x88, 0x05, 0xff,
947 0x1c, 0xeb, 0xb6, 0xc6, 0x5c, 0xb8, 0x5b, 0xd5, 0x9c, 0xc1, 0x87, 0x8d,
948 0xf8, 0xd6, 0x3f, 0x97, 0x64, 0xaf, 0x80, 0x21, 0x75, 0xfc, 0xe3, 0x52,
949 0x64, 0x08, 0xc7, 0x78, 0xe7, 0x90, 0x3d, 0x11, 0xf1, 0xfd, 0x58, 0xea,
950 0xf2, 0x3e, 0xfb, 0x88, 0x7c, 0x3f, 0x80, 0x6d, 0x5a, 0x3e, 0x2f, 0xbc,
951 0x97, 0x3a, 0x4f, 0x25, 0x5f, 0x15, 0x74, 0x50, 0xa2, 0x7f, 0x67, 0x9a,
952 0x35, 0x09, 0xb1, 0x8c, 0x29, 0x51, 0x0b, 0x8d, 0x7c, 0xe5, 0xf9, 0x45,
953 0x3d, 0x2f, 0x47, 0xed, 0xf5, 0xfd, 0xc8, 0x37, 0xcb, 0x16, 0x68, 0x73,
954 0x99, 0x01, 0x3f, 0xda, 0xe8, 0xf2, 0x46, 0x4f, 0x50, 0xd4, 0x66, 0x77,
955 0xb3, 0x8e, 0xa3, 0xf3, 0x92, 0xc7, 0xf8, 0xfe, 0x01, 0xf1, 0xbe, 0xb9,
956 0xd8, 0x12, 0xc6, 0x35, 0xd3, 0xc8, 0x72, 0xe9, 0x21, 0xfe, 0x5d, 0xc4,
957 0x11, 0x93, 0xd4, 0xaa, 0x62, 0x04, 0x1d, 0x2a, 0xae, 0x14, 0x62, 0x5a,
958 0xaa, 0xd4, 0x1c, 0x8f, 0x94, 0x7d, 0x6d, 0xc0, 0xf1, 0x5a, 0x5f, 0xdb,
959 0x73, 0x5b, 0xc8, 0x9b, 0xad, 0xf0, 0x1a, 0x39, 0xa5, 0x2d, 0xa4, 0x7c,
960 0x88, 0xd6, 0x02, 0x6d, 0xb7, 0xb6, 0x6e, 0xc7, 0xd7, 0xb4, 0x36, 0xcf,
961 0xac, 0x9f, 0x79, 0xc7, 0x69, 0x53, 0xf8, 0xd4, 0x4c, 0xf3, 0xb9, 0x36,
962 0x96, 0xd9, 0xa8, 0x97, 0x02, 0xbc, 0xfc, 0x43, 0xa8, 0x37, 0x79, 0x32,
963 0xd0, 0x4c, 0xab, 0xab, 0xc8, 0x79, 0x78, 0xfc, 0x2e, 0x99, 0xe7, 0xfb,
964 0x08, 0xc3, 0x65, 0x3f, 0xcb, 0x37, 0x43, 0xc5, 0x70, 0x70, 0x0e, 0xbc,
965 0x41, 0xf4, 0xfd, 0x0c, 0x3c, 0x3c, 0xde, 0xc6, 0x7a, 0xbd, 0x8c, 0x01,
966 0x1c, 0xe4, 0x7b, 0x7f, 0x33, 0xf7, 0x08, 0xfc, 0x59, 0xe6, 0x61, 0xbe,
967 0x7f, 0x8c, 0xf5, 0x81, 0x08, 0x35, 0xd3, 0xca, 0x6a, 0x33, 0xeb, 0xf5,
968 0xcd, 0xac, 0x0f, 0x8c, 0x9a, 0x23, 0x3e, 0xf1, 0x2c, 0x51, 0xdb, 0xf2,
969 0xe9, 0xc0, 0x7e, 0xc6, 0x41, 0x3c, 0xeb, 0x8b, 0xea, 0x59, 0xb5, 0xcf,
970 0xb8, 0x55, 0xc2, 0xf1, 0x61, 0xff, 0xfa, 0x99, 0xab, 0x78, 0x2f, 0xd4,
971 0xe2, 0x34, 0xeb, 0xbe, 0x41, 0xf1, 0x6e, 0x46, 0x63, 0x66, 0x86, 0xed,
972 0x80, 0x30, 0x1f, 0x1f, 0xa1, 0x54, 0x31, 0x41, 0xbf, 0x57, 0x74, 0xfb,
973 0x6a, 0x8f, 0xf0, 0x9c, 0x65, 0x6d, 0x7d, 0x0b, 0xcf, 0xeb, 0x7d, 0xa7,
974 0x96, 0x67, 0xb4, 0x91, 0xff, 0x6b, 0x41, 0x6a, 0x7e, 0x11, 0xbe, 0x91,
975 0x12, 0x65, 0xc3, 0xf6, 0x85, 0xeb, 0xe2, 0xbd, 0x1b, 0x16, 0xbd, 0x22,
976 0xf2, 0x5b, 0xf9, 0x7a, 0xbe, 0xe7, 0x79, 0x8c, 0x7b, 0xc5, 0xa2, 0x2b,
977 0x8e, 0x84, 0xf7, 0x9f, 0x05, 0x82, 0xe4, 0x7f, 0x1d, 0x39, 0x48, 0xd0,
978 0xb5, 0xd6, 0xcf, 0x38, 0xfb, 0x98, 0x5f, 0xbf, 0x88, 0xeb, 0xf8, 0xf3,
979 0x75, 0x1c, 0xb7, 0xf1, 0x3a, 0x21, 0x6f, 0x91, 0x77, 0x02, 0x3e, 0xb7,
980 0x3f, 0x64, 0x0a, 0xfc, 0x3b, 0xc2, 0x38, 0xd5, 0x24, 0x7c, 0x81, 0xbd,
981 0x18, 0xeb, 0x0c, 0xb2, 0x6e, 0xb0, 0x7e, 0x66, 0x7c, 0x1f, 0x8e, 0x23,
982 0x3d, 0x7e, 0x86, 0x91, 0xc4, 0xa1, 0xb0, 0x78, 0xff, 0xa1, 0xeb, 0x2f,
983 0x70, 0x70, 0x9c, 0x78, 0x3f, 0xa1, 0x3f, 0xf0, 0x7e, 0x9a, 0xe8, 0xb3,
984 0xd4, 0x46, 0x71, 0x7e, 0x46, 0x2c, 0x27, 0xd7, 0x7d, 0xbe, 0xe8, 0x27,
985 0xe9, 0x47, 0x6a, 0x1e, 0xd6, 0xef, 0x29, 0xa4, 0x7e, 0xdc, 0x5b, 0xd3,
986 0x0a, 0xbe, 0x77, 0xd1, 0x8d, 0x5c, 0x07, 0xdd, 0x54, 0xb1, 0xa5, 0x1b,
987 0xc2, 0xae, 0x62, 0x9e, 0x9c, 0xe8, 0xa2, 0xeb, 0xab, 0x4d, 0x44, 0xbd,
988 0x6d, 0x22, 0xf6, 0x7b, 0x23, 0x97, 0xc7, 0xf3, 0x87, 0xa5, 0xdf, 0xa5,
989 0x82, 0x23, 0x37, 0x3c, 0x70, 0xe4, 0x3d, 0x81, 0x23, 0xef, 0x6d, 0x81,
990 0x23, 0x7b, 0x95, 0x2d, 0xd1, 0x46, 0xcd, 0x0a, 0x3f, 0x5e, 0x63, 0xfc,
991 0x78, 0x81, 0xf1, 0xe3, 0x50, 0x03, 0xfc, 0x30, 0x6a, 0xf0, 0xe3, 0xb0,
992 0xc0, 0x8f, 0x9f, 0x6d, 0x8a, 0x1f, 0x87, 0xfc, 0x9b, 0xf9, 0x82, 0x34,
993 0x6e, 0x0e, 0xd0, 0x4a, 0xce, 0xa1, 0xd5, 0x45, 0x9b, 0x2d, 0x7b, 0xd8,
994 0xe6, 0x88, 0x19, 0xce, 0x88, 0x7a, 0x97, 0x82, 0xc0, 0x2b, 0x96, 0xe3,
995 0x33, 0xa8, 0x69, 0xaa, 0xdb, 0x03, 0x12, 0xef, 0xa5, 0x14, 0xf0, 0x97,
996 0x7b, 0x12, 0xcb, 0xac, 0x9f, 0xf9, 0x73, 0xde, 0xc7, 0x2b, 0x6b, 0x81,
997 0x00, 0x7e, 0xf3, 0xcf, 0x04, 0x69, 0x63, 0x8d, 0xed, 0x54, 0xc6, 0xb1,
998 0xab, 0xb9, 0x21, 0xba, 0x92, 0x1b, 0xa0, 0x8d, 0xdc, 0x30, 0xbd, 0x93,
999 0xc3, 0x33, 0x00, 0x73, 0x3e, 0x16, 0x30, 0x37, 0xe8, 0x60, 0x90, 0xc7,
1000 0xac, 0x0e, 0xd0, 0xfa, 0xaa, 0xc6, 0x57, 0xe0, 0x2a, 0xf6, 0x3f, 0xd2,
1001 0x23, 0xeb, 0xd0, 0xea, 0x71, 0x20, 0x56, 0x85, 0x03, 0xf2, 0x1a, 0xec,
1002 0xfd, 0x42, 0x7d, 0x0d, 0x6d, 0xab, 0x39, 0x83, 0x1c, 0xb8, 0x36, 0xb6,
1003 0xc9, 0x6d, 0xe1, 0x73, 0x3d, 0xe8, 0x87, 0x4e, 0x6b, 0xdc, 0x4d, 0x5d,
1004 0xbc, 0x07, 0x0e, 0xf2, 0x87, 0x86, 0x59, 0x3f, 0xed, 0x16, 0xfa, 0x68,
1005 0xd4, 0x09, 0x84, 0x62, 0x54, 0x3a, 0x6b, 0x38, 0xe8, 0x93, 0xf8, 0x08,
1006 0xdf, 0xcf, 0x50, 0x7e, 0x9e, 0x4e, 0x17, 0x3e, 0xd5, 0xea, 0x9e, 0x88,
1007 0xd1, 0x9e, 0xe0, 0x39, 0x43, 0x4e, 0x56, 0xe2, 0x22, 0x54, 0x8e, 0x8b,
1008 0xb4, 0xf2, 0xba, 0x25, 0x2d, 0xcd, 0x39, 0x3c, 0xae, 0xc8, 0xe3, 0x8a,
1009 0x88, 0xa9, 0xf1, 0xf9, 0x55, 0xc4, 0x73, 0x87, 0x68, 0x63, 0x11, 0x34,
1010 0x07, 0xff, 0x44, 0x25, 0x86, 0xba, 0xb1, 0x86, 0xf3, 0xf0, 0x51, 0x54,
1011 0x62, 0xa8, 0x1b, 0x2a, 0x86, 0xba, 0xb1, 0x36, 0x2d, 0xf8, 0xf0, 0x42,
1012 0x8e, 0x79, 0x40, 0xce, 0xaf, 0xf2, 0x07, 0xf7, 0xa9, 0x77, 0xf6, 0x9c,
1013 0x10, 0x3e, 0xe4, 0x1e, 0x67, 0x73, 0x18, 0x1e, 0xac, 0x83, 0xe1, 0xb4,
1014 0xd0, 0x83, 0xe2, 0x7c, 0xcf, 0x58, 0xee, 0x04, 0xc3, 0x73, 0x96, 0x69,
1015 0x69, 0xb7, 0xa2, 0x25, 0x1d, 0x93, 0xed, 0x26, 0xf5, 0xfe, 0x1f, 0xa1,
1016 0xeb, 0x4b, 0xfe, 0x33, 0x54, 0xc3, 0x7f, 0x28, 0x10, 0x1d, 0x97, 0xd7,
1017 0xa7, 0x8b, 0xaf, 0x0c, 0x6b, 0xff, 0x5b, 0x9a, 0xef, 0xbb, 0x90, 0xdb,
1018 0x49, 0x4c, 0x97, 0xe5, 0xa6, 0x67, 0xce, 0xe0, 0x76, 0x9f, 0xad, 0x71,
1019 0xe1, 0xc4, 0x6d, 0xe0, 0x93, 0xbc, 0x47, 0x05, 0x9f, 0xfe, 0x77, 0x16,
1020 0xc0, 0xb2, 0x93, 0x05, 0x98, 0x57, 0x84, 0x80, 0xf5, 0x03, 0x03, 0xb4,
1021 0x8e, 0x39, 0x00, 0x1e, 0x53, 0x68, 0x02, 0xe6, 0x19, 0xa7, 0xf5, 0x40,
1022 0xfb, 0xfb, 0x95, 0xc1, 0xeb, 0x5d, 0x1b, 0xa0, 0x67, 0x4f, 0x2d, 0xea,
1023 0x79, 0x2c, 0x07, 0xca, 0xa3, 0x4e, 0x2a, 0x0c, 0x24, 0xe6, 0x27, 0x90,
1024 0xff, 0x80, 0xfe, 0x00, 0xf9, 0x11, 0x98, 0x9f, 0x9c, 0x81, 0x72, 0xa0,
1025 0x35, 0x53, 0xcd, 0x6b, 0x40, 0xfa, 0x40, 0x61, 0x08, 0x2a, 0x53, 0x41,
1026 0x63, 0x1d, 0x40, 0xf6, 0x12, 0x21, 0x68, 0xd8, 0x01, 0x69, 0x20, 0xbb,
1027 0x79, 0x8a, 0x08, 0x98, 0x9f, 0x14, 0x20, 0xc4, 0xd0, 0x00, 0xcf, 0x4f,
1028 0xec, 0x40, 0x97, 0xc2, 0xdc, 0xf4, 0xff, 0xff, 0x31, 0x15, 0x16, 0x60,
1029 0xda, 0x03, 0xad, 0xf9, 0xfc, 0xfd, 0xff, 0x80, 0x08, 0x0b, 0x43, 0x0b,
1030 0x7c, 0xed, 0x9e, 0xb0, 0x3c, 0xa8, 0x9c, 0x5b, 0x00, 0x64, 0xb5, 0xc1,
1031 0xeb, 0x6d, 0x16, 0xf0, 0x7d, 0xc4, 0x0b, 0x18, 0x7e, 0x01, 0xcb, 0x95,
1032 0xff, 0xff, 0x97, 0xc2, 0xd5, 0x82, 0x00, 0x00, 0xd4, 0xc2, 0xcb, 0x42,
1033 0x60, 0x7c, 0x00, 0x00, 0x00 };
1034static u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 };
1035static u32 bnx2_COM_b09FwRodata[(0x88/4) + 1] = {
1036 0x08001ad8, 0x08001b14, 0x08001b14, 0x08001b14, 0x08001b14, 0x08001b14,
1037 0x08001a24, 0x08001b14, 0x08001a98, 0x08001b14, 0x080019ac, 0x08001b14,
1038 0x08001b14, 0x08001b14, 0x080019b8, 0x0, 0x08002a2c, 0x08002a7c,
1039 0x08002aac, 0x08002adc, 0x08002b0c, 0x0, 0x08005fac, 0x08005fac,
1040 0x08005fac, 0x08005fac, 0x08005fac, 0x08005fd8, 0x08005fd8, 0x08006018,
1041 0x08006024, 0x08006024, 0x08005fac, 0x0, 0x0 };
1042static u32 bnx2_COM_b09FwBss[(0x88/4) + 1] = { 0x0 };
1043static u32 bnx2_COM_b09FwSbss[(0x5c/4) + 1] = { 0x0 };
1044
1045static struct fw_info bnx2_com_fw_09 = {
1046 .ver_major = 0x1,
1047 .ver_minor = 0x0,
1048 .ver_fix = 0x0,
1049
1050 .start_addr = 0x080000b0,
1051
1052 .text_addr = 0x08000000,
1053 .text_len = 0x7c5c,
1054 .text_index = 0x0,
1055 .gz_text = bnx2_COM_b09FwText,
1056 .gz_text_len = sizeof(bnx2_COM_b09FwText),
1057
1058 .data_addr = 0x08007d00,
1059 .data_len = 0x0,
1060 .data_index = 0x0,
1061 .data = bnx2_COM_b09FwData,
1062
1063 .sbss_addr = 0x08007d00,
1064 .sbss_len = 0x5c,
1065 .sbss_index = 0x0,
1066 .sbss = bnx2_COM_b09FwSbss,
1067
1068 .bss_addr = 0x08007d60,
1069 .bss_len = 0x88,
1070 .bss_index = 0x0,
1071 .bss = bnx2_COM_b09FwBss,
1072
1073 .rodata_addr = 0x08007c60,
1074 .rodata_len = 0x88,
1075 .rodata_index = 0x0,
1076 .rodata = bnx2_COM_b09FwRodata,
1077};
1078
1079static u8 bnx2_CP_b09FwText[] = {
1080 0x1f, 0x8b, 0x08, 0x08, 0x8e, 0xfc, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
1081 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xbd, 0x7d, 0x0d, 0x74,
1082 0x5c, 0x57, 0x7d, 0xe7, 0xff, 0xdd, 0x79, 0x92, 0xc6, 0xb2, 0x2c, 0x3f,
1083 0xcb, 0x63, 0x65, 0x22, 0x0b, 0x7b, 0x46, 0x7a, 0xb2, 0x95, 0x58, 0x64,
1084 0xc7, 0xae, 0x00, 0x6d, 0x3b, 0x85, 0xe9, 0x48, 0xb2, 0x9d, 0x0f, 0x8a,
1085 0x4c, 0x44, 0x4f, 0x5a, 0xe8, 0x22, 0xc6, 0x76, 0x48, 0x80, 0xb2, 0x4e,
1086 0x09, 0x69, 0x80, 0x04, 0x0f, 0x23, 0xf9, 0x83, 0x74, 0xec, 0x51, 0x12,
1087 0xc5, 0x76, 0x4f, 0x73, 0x58, 0x55, 0x92, 0x1d, 0x43, 0xa7, 0x1e, 0x27,
1088 0x71, 0x68, 0xf6, 0x6c, 0x68, 0xb4, 0x4a, 0xe2, 0xa6, 0x3d, 0xd9, 0xd6,
1089 0xf4, 0x84, 0x6e, 0xda, 0x43, 0x77, 0x85, 0x71, 0x88, 0x4b, 0xb3, 0x4b,
1090 0xf8, 0x68, 0x61, 0xa1, 0xe5, 0xed, 0xef, 0x77, 0xef, 0x7d, 0xd2, 0xe8,
1091 0xc3, 0x09, 0xa1, 0xbb, 0xf5, 0x39, 0xcf, 0x6f, 0xde, 0xfd, 0xfc, 0xdf,
1092 0xff, 0xfd, 0x7f, 0xdf, 0x0f, 0xad, 0x17, 0xa9, 0x17, 0xfb, 0x6f, 0x15,
1093 0x9e, 0x6d, 0x89, 0x7d, 0xbb, 0xb7, 0x5e, 0xd7, 0x73, 0x1d, 0x7e, 0x6e,
1094 0x75, 0x57, 0x46, 0x95, 0xbc, 0x89, 0x7f, 0x89, 0x9f, 0xa1, 0x4c, 0x44,
1095 0xc4, 0x0b, 0xfb, 0xe2, 0x23, 0x51, 0x95, 0x1e, 0xfc, 0x64, 0xd6, 0x97,
1096 0x68, 0x24, 0x7d, 0xf6, 0xb3, 0xbb, 0x7d, 0x91, 0x4c, 0x79, 0x4b, 0xa2,
1097 0x57, 0xfe, 0x25, 0xc8, 0xc7, 0x5c, 0x61, 0xfa, 0x5b, 0xd2, 0xff, 0xfc,
1098 0x9f, 0xbe, 0xf2, 0x8e, 0xe4, 0x6b, 0xe3, 0x11, 0x89, 0x7a, 0xe9, 0x8f,
1099 0x89, 0xb7, 0x49, 0xa2, 0xad, 0xe9, 0x81, 0x4f, 0x3e, 0xbc, 0xf9, 0x6f,
1100 0x44, 0x1a, 0xc3, 0xb6, 0x2e, 0x07, 0x5f, 0xd9, 0x2c, 0xf9, 0x96, 0x74,
1101 0x7c, 0xc8, 0x4d, 0x7b, 0xf2, 0x74, 0x45, 0x06, 0x0a, 0xc5, 0xa8, 0x44,
1102 0xd2, 0x1d, 0x2f, 0xf5, 0x46, 0xf6, 0x07, 0x11, 0xdf, 0xf7, 0x7a, 0xa5,
1103 0xa1, 0x27, 0xdb, 0x8d, 0xf4, 0xf2, 0x56, 0x51, 0x7e, 0x54, 0xb2, 0x15,
1104 0x69, 0x50, 0xbe, 0x8f, 0x77, 0xbd, 0xa8, 0x74, 0xd2, 0xcb, 0x46, 0x5c,
1105 0x29, 0x54, 0x2e, 0xac, 0x30, 0x6d, 0x96, 0xec, 0xfb, 0x6f, 0xa2, 0xe6,
1106 0x8d, 0x36, 0x4b, 0x51, 0x99, 0x8d, 0xc4, 0x05, 0xfd, 0x00, 0xe6, 0x06,
1107 0x19, 0x2e, 0x25, 0x24, 0x5b, 0x64, 0xbf, 0xae, 0xe4, 0x3c, 0xf6, 0xd9,
1108 0x80, 0xfa, 0x2b, 0x9d, 0xe5, 0xcb, 0xb3, 0xec, 0x4b, 0x28, 0x9b, 0x40,
1109 0xb9, 0x56, 0x79, 0xbc, 0x12, 0x97, 0xc7, 0x2a, 0x31, 0x79, 0xb4, 0x72,
1110 0x87, 0x64, 0x50, 0xf7, 0x6c, 0x05, 0x7d, 0x97, 0x6a, 0xa5, 0x77, 0xac,
1111 0x5e, 0xb2, 0x63, 0xed, 0xf1, 0x9c, 0x04, 0xc1, 0x27, 0x52, 0x1f, 0x95,
1112 0xa1, 0x26, 0x94, 0x2f, 0x31, 0x2f, 0xbe, 0x20, 0x2f, 0x97, 0xda, 0xe2,
1113 0xe5, 0x94, 0x23, 0x99, 0xc1, 0x64, 0x7c, 0x48, 0xf1, 0xbb, 0x46, 0xb2,
1114 0x5d, 0xf8, 0x1e, 0x70, 0x25, 0xe2, 0x07, 0xc1, 0x1d, 0xa9, 0x26, 0xc0,
1115 0x91, 0x4c, 0x24, 0x14, 0xeb, 0xb2, 0x5e, 0x32, 0x9f, 0x50, 0x51, 0xc9,
1116 0x57, 0xae, 0x93, 0x44, 0x53, 0x10, 0xbc, 0x37, 0xe5, 0x21, 0x5d, 0xa4,
1117 0xb7, 0x28, 0xfb, 0x54, 0xda, 0x47, 0x9b, 0x92, 0x52, 0xe9, 0xb5, 0x18,
1118 0xc7, 0x16, 0xe0, 0xa9, 0x56, 0x32, 0x31, 0xc9, 0xa8, 0xb4, 0x24, 0x54,
1119 0x7a, 0x05, 0xd2, 0x1c, 0xa9, 0xf1, 0xa7, 0x2c, 0x9d, 0xac, 0xc6, 0xb7,
1120 0x0c, 0xa8, 0x74, 0xd3, 0xa2, 0xf4, 0x64, 0x42, 0xd4, 0x8f, 0xea, 0xd0,
1121 0x67, 0x67, 0x46, 0x31, 0x0d, 0x6f, 0x9d, 0x76, 0xfd, 0x32, 0x69, 0x1f,
1122 0x74, 0x16, 0xa6, 0x3d, 0xb5, 0x8a, 0xb0, 0x8a, 0xe2, 0xef, 0x28, 0xe0,
1123 0x6a, 0x41, 0xff, 0xed, 0x5e, 0x0d, 0xc6, 0x35, 0x90, 0x4a, 0x7a, 0xfd,
1124 0xea, 0xc5, 0x40, 0x9a, 0x09, 0x33, 0xf3, 0x14, 0xf2, 0x50, 0x34, 0x9d,
1125 0xc2, 0xbc, 0xb9, 0x72, 0x08, 0x63, 0xbb, 0x38, 0x96, 0xf4, 0xda, 0x14,
1126 0xde, 0x53, 0xfc, 0xdd, 0x34, 0x14, 0x49, 0x07, 0x41, 0x36, 0x35, 0x2e,
1127 0xb9, 0x72, 0xd2, 0x9b, 0x05, 0x70, 0xbd, 0x63, 0x71, 0x8c, 0x1f, 0xe3,
1128 0x88, 0x65, 0x92, 0x6b, 0xa4, 0xcb, 0xce, 0xcf, 0x5f, 0xa2, 0xef, 0x76,
1129 0xef, 0x0e, 0xd5, 0xee, 0xa5, 0x54, 0xd2, 0x9b, 0x90, 0x3f, 0xc4, 0x77,
1130 0x10, 0xec, 0x4a, 0x25, 0xe3, 0x79, 0xcc, 0xdd, 0xa5, 0x62, 0x4c, 0x5e,
1131 0x2e, 0x26, 0x41, 0xa9, 0xc9, 0xce, 0x49, 0xd9, 0x92, 0x9a, 0x04, 0xdc,
1132 0x05, 0x3c, 0x07, 0x99, 0x57, 0x46, 0x5e, 0x99, 0x75, 0x83, 0xe0, 0xe6,
1133 0xd4, 0x89, 0x60, 0xa8, 0xd9, 0xd0, 0xfe, 0xd3, 0x25, 0xcc, 0x2b, 0xe6,
1134 0xe9, 0xb1, 0x12, 0xe6, 0xb5, 0x84, 0x39, 0xd5, 0xf3, 0xdf, 0x89, 0xf9,
1135 0x27, 0x8d, 0x90, 0x3e, 0xb6, 0x59, 0x7a, 0x7d, 0xb7, 0x7d, 0x8b, 0x64,
1136 0x4b, 0x8e, 0x64, 0x53, 0x3f, 0x09, 0x32, 0x9a, 0x27, 0xc4, 0xe9, 0x2d,
1137 0x91, 0x26, 0x6b, 0x00, 0x2b, 0x3f, 0x7f, 0xdd, 0x96, 0x8b, 0x3a, 0x18,
1138 0x06, 0xe7, 0x83, 0xf9, 0x51, 0xe5, 0xd7, 0xd9, 0xfc, 0x90, 0xf6, 0xf9,
1139 0x0f, 0x74, 0xe7, 0xcf, 0x97, 0xcb, 0x92, 0x36, 0x2b, 0x22, 0xb9, 0x07,
1140 0x03, 0xe9, 0x4d, 0x01, 0x5f, 0x6c, 0xd3, 0x4b, 0x89, 0xae, 0xeb, 0xb1,
1141 0x8c, 0x2e, 0x8b, 0x7f, 0x3f, 0xae, 0x41, 0x1f, 0x4e, 0x5f, 0x69, 0xbe,
1142 0x6e, 0x5f, 0xe9, 0x85, 0x98, 0x85, 0x0f, 0xdf, 0x3d, 0x4e, 0xb6, 0xf2,
1143 0x77, 0x76, 0x8e, 0xc3, 0x71, 0x74, 0x2d, 0x43, 0xe3, 0x2e, 0xf8, 0xc1,
1144 0x93, 0x5c, 0xb1, 0x07, 0xfd, 0xc6, 0xf0, 0x0e, 0x82, 0x91, 0x54, 0x26,
1145 0xe9, 0x4a, 0x1a, 0xdf, 0x03, 0x98, 0xaf, 0x0e, 0xe0, 0x4f, 0xdc, 0xec,
1146 0xe6, 0x94, 0xf4, 0x55, 0x40, 0x7b, 0x95, 0x37, 0x96, 0x14, 0x7a, 0x0c,
1147 0xa9, 0x7f, 0xb1, 0xb8, 0x61, 0x3f, 0x7c, 0xbb, 0x32, 0x02, 0xfa, 0x28,
1148 0x8c, 0xf9, 0x32, 0x5c, 0x9c, 0xf6, 0x94, 0x24, 0x41, 0xbb, 0x69, 0xe9,
1149 0xad, 0xf8, 0x52, 0x28, 0xe2, 0x5d, 0x6a, 0x07, 0xfd, 0xba, 0x92, 0x89,
1150 0x9b, 0x39, 0x29, 0x14, 0x7f, 0x09, 0xe3, 0x02, 0x8e, 0x7d, 0xfe, 0xee,
1151 0xb1, 0xb0, 0x80, 0xf7, 0xbb, 0x53, 0x1a, 0x3f, 0x6f, 0x0e, 0x06, 0xf6,
1152 0x8d, 0x31, 0x60, 0x9c, 0x85, 0xb2, 0x8b, 0x77, 0x0c, 0xef, 0x90, 0x16,
1153 0xe3, 0x80, 0xa9, 0x55, 0x86, 0x41, 0x8b, 0xbd, 0x82, 0xdf, 0x53, 0x84,
1154 0x91, 0xfd, 0xb6, 0xe8, 0xdf, 0xc3, 0x63, 0x1b, 0xf4, 0x77, 0x6e, 0xa0,
1155 0x45, 0xf2, 0x53, 0xe1, 0x58, 0x28, 0x0f, 0x28, 0x03, 0x92, 0x87, 0x45,
1156 0x28, 0x13, 0x82, 0xe0, 0xc1, 0x14, 0xe5, 0x42, 0x10, 0x3c, 0x96, 0xa2,
1157 0x9c, 0x38, 0x07, 0xfe, 0xa7, 0x6c, 0x20, 0xaf, 0xae, 0x55, 0x9c, 0x83,
1158 0x6c, 0x11, 0x7d, 0x40, 0x4e, 0xe4, 0xba, 0x4e, 0x40, 0x6e, 0x50, 0xae,
1159 0x5c, 0xf8, 0x44, 0xd6, 0xcf, 0xc7, 0x23, 0x1a, 0x0f, 0x98, 0x6f, 0xc8,
1160 0xbc, 0x8c, 0x86, 0xbc, 0x4d, 0x0a, 0x5d, 0xa3, 0xb6, 0xcc, 0x65, 0x5d,
1161 0xc6, 0x5d, 0x52, 0xe6, 0x76, 0x65, 0xf8, 0xae, 0x15, 0xf3, 0xb1, 0x42,
1162 0x11, 0x4f, 0x6d, 0x9b, 0xf8, 0x2d, 0xd1, 0x9a, 0xf4, 0x97, 0x90, 0x37,
1163 0x7d, 0xd7, 0x49, 0x7f, 0xb9, 0xbc, 0x59, 0x77, 0x69, 0xde, 0x88, 0xb8,
1164 0x7e, 0xb2, 0x73, 0x97, 0x9a, 0x01, 0x3d, 0x05, 0xc1, 0xc9, 0x54, 0x98,
1165 0xfe, 0x8f, 0xee, 0xd2, 0x3e, 0x12, 0x35, 0x4b, 0xd3, 0xee, 0x5d, 0x26,
1166 0xed, 0xc4, 0x32, 0x69, 0x1b, 0x6a, 0x97, 0xa6, 0xbd, 0x7f, 0x99, 0xb4,
1167 0xfb, 0x97, 0x49, 0xfb, 0x5f, 0xcb, 0xa4, 0x7d, 0x67, 0x99, 0xb4, 0xef,
1168 0x2d, 0x93, 0xd6, 0x52, 0xb7, 0x34, 0xcd, 0x05, 0x3f, 0x6d, 0x92, 0x42,
1169 0xec, 0x73, 0x1c, 0xbb, 0xc5, 0xcd, 0xfe, 0xc8, 0x52, 0xdc, 0xd4, 0xa0,
1170 0x5c, 0xeb, 0xa2, 0x72, 0x53, 0xcb, 0x94, 0xab, 0x45, 0xb9, 0xa6, 0x45,
1171 0xe5, 0x92, 0xcb, 0xe0, 0xba, 0x4e, 0xeb, 0xaf, 0x85, 0xe5, 0x0a, 0xcb,
1172 0x94, 0x63, 0xfa, 0x1e, 0xdb, 0xcf, 0x16, 0x68, 0x99, 0xd7, 0x9b, 0xaf,
1173 0x5a, 0x91, 0x66, 0xa6, 0xb7, 0x42, 0x47, 0xac, 0x50, 0x86, 0xdf, 0x29,
1174 0x5b, 0x98, 0xe6, 0x81, 0xee, 0xa3, 0xa0, 0x3b, 0xca, 0x47, 0xf0, 0x91,
1175 0x4f, 0xfe, 0x5d, 0x25, 0x43, 0xb1, 0x2d, 0xde, 0x2f, 0xa8, 0x06, 0xd0,
1176 0x58, 0xd2, 0x4b, 0x28, 0xf2, 0x97, 0xe4, 0x23, 0x69, 0x3f, 0xdf, 0x2b,
1177 0x2a, 0xa6, 0x24, 0x90, 0xbe, 0x94, 0x6a, 0x52, 0xb2, 0x1f, 0xfc, 0x93,
1178 0x81, 0x4e, 0xda, 0x15, 0xf4, 0x6a, 0x1e, 0x32, 0x65, 0xaf, 0x2c, 0x2b,
1179 0x7d, 0x39, 0x48, 0x19, 0x97, 0xce, 0xdc, 0x95, 0xf5, 0xa7, 0x7b, 0x6a,
1180 0x41, 0xb3, 0x17, 0x51, 0x67, 0x07, 0x6a, 0xee, 0x2d, 0xbb, 0xd2, 0x57,
1181 0xee, 0x04, 0x2f, 0x38, 0x72, 0xde, 0x5f, 0x2d, 0xe7, 0x53, 0x28, 0x5b,
1182 0x89, 0xc8, 0x4c, 0xcc, 0x91, 0x19, 0x7c, 0x67, 0x53, 0xc8, 0xab, 0x84,
1183 0xbc, 0xd5, 0x29, 0x07, 0x4a, 0xbe, 0x1c, 0x2e, 0xfd, 0x92, 0x0a, 0xf5,
1184 0x56, 0x7f, 0x6a, 0xa5, 0x9c, 0xf6, 0x4c, 0xdb, 0x3b, 0xfc, 0x69, 0x68,
1185 0x4c, 0x57, 0x2e, 0xfa, 0xc9, 0xf8, 0x8c, 0xe6, 0x89, 0x1f, 0x06, 0x7d,
1186 0x68, 0x67, 0xc2, 0x4f, 0x7a, 0x7f, 0x8a, 0xef, 0xa1, 0x32, 0xed, 0x90,
1187 0xf9, 0xb6, 0x86, 0xd1, 0xd6, 0xa1, 0xd2, 0x2a, 0xf9, 0xb0, 0xad, 0xbf,
1188 0xdd, 0x9f, 0xee, 0x04, 0xcf, 0x79, 0xa7, 0x28, 0x23, 0x8a, 0x80, 0x6b,
1189 0x10, 0xbc, 0x8d, 0xba, 0xcf, 0x69, 0x39, 0x05, 0xbb, 0xa5, 0xb8, 0x1a,
1190 0x72, 0xf7, 0x1f, 0x83, 0x0f, 0xc7, 0x58, 0x9e, 0x69, 0xd4, 0x25, 0x32,
1191 0xaa, 0xd2, 0x90, 0x09, 0xdd, 0x94, 0x85, 0x09, 0xc8, 0x41, 0xc8, 0x96,
1192 0xd2, 0x4f, 0x83, 0x8c, 0x5b, 0x2d, 0xdf, 0x24, 0x3f, 0x5f, 0x86, 0x69,
1193 0x09, 0x23, 0x2f, 0x4b, 0xb3, 0x73, 0xb2, 0x22, 0x0f, 0xf9, 0xf2, 0x74,
1194 0x85, 0x72, 0xe1, 0x7a, 0xf0, 0x68, 0xab, 0xf4, 0x15, 0x93, 0xf9, 0x8c,
1195 0x6c, 0xc2, 0xfc, 0x7d, 0x1e, 0x73, 0xea, 0xe2, 0xb9, 0xaf, 0x5e, 0x1a,
1196 0x53, 0xd0, 0xcd, 0x4c, 0x47, 0xa3, 0xcd, 0x51, 0xc8, 0xa8, 0xdf, 0x03,
1197 0x1e, 0x86, 0x39, 0xe7, 0xf1, 0x6c, 0xc4, 0x19, 0xa0, 0x3d, 0x32, 0x40,
1198 0xfd, 0x50, 0x66, 0xdb, 0x84, 0x37, 0x6e, 0x7f, 0x47, 0xb5, 0x8c, 0x31,
1199 0xbf, 0x1b, 0xf0, 0x3b, 0x61, 0x7f, 0x7b, 0xf8, 0xed, 0xdb, 0xdf, 0x31,
1200 0xfc, 0xee, 0xb4, 0xbf, 0xa1, 0x5b, 0x8b, 0x5d, 0xfa, 0xf7, 0x48, 0x69,
1201 0xfb, 0x76, 0xe5, 0x5f, 0x27, 0xb9, 0xa9, 0x56, 0x39, 0x50, 0xf4, 0xad,
1202 0x6c, 0xc1, 0x23, 0x4f, 0x3a, 0x66, 0x9c, 0x80, 0x9b, 0xb2, 0xb3, 0x94,
1203 0x77, 0x06, 0x08, 0x3f, 0x68, 0xa0, 0xb7, 0xb8, 0xc5, 0x5b, 0x23, 0xa4,
1204 0x81, 0x11, 0xa7, 0xb7, 0xe2, 0x64, 0x60, 0xaf, 0xc5, 0x87, 0xe5, 0x30,
1205 0x7e, 0x8b, 0x17, 0x49, 0x3f, 0x89, 0xb7, 0xc1, 0x01, 0xf5, 0xce, 0x70,
1206 0x89, 0xf2, 0xd2, 0xc7, 0xd8, 0x13, 0x72, 0x6e, 0x81, 0x0d, 0x45, 0x5c,
1207 0x28, 0xc9, 0x8d, 0x25, 0x4f, 0xe4, 0x25, 0x99, 0x1f, 0x07, 0x43, 0xec,
1208 0x4a, 0xb9, 0xf2, 0xde, 0x14, 0x68, 0xf7, 0x3a, 0x47, 0xb6, 0x5f, 0xe7,
1209 0xc2, 0xe6, 0xf1, 0xc7, 0xb7, 0x83, 0xfe, 0x31, 0xcf, 0x9a, 0x1e, 0xd4,
1210 0x19, 0x81, 0x9d, 0x08, 0x6c, 0x9f, 0xe9, 0xea, 0x1b, 0x2e, 0xe6, 0x3e,
1211 0xa6, 0xd2, 0xfb, 0x3e, 0x95, 0xed, 0xbe, 0x46, 0x72, 0x83, 0x0a, 0x38,
1212 0x6a, 0x1e, 0x82, 0x1e, 0xc4, 0xb8, 0x82, 0x00, 0xf4, 0x0c, 0x79, 0x7e,
1213 0xf3, 0xcd, 0x91, 0x74, 0x8d, 0xf4, 0x0e, 0x36, 0xa3, 0x0e, 0xf3, 0x88,
1214 0xaf, 0xaf, 0xa2, 0x9d, 0x64, 0xa2, 0x4f, 0xe4, 0x9e, 0x91, 0xee, 0x59,
1215 0x67, 0x78, 0xf4, 0x37, 0xc0, 0x93, 0x5b, 0x51, 0xff, 0x01, 0xd4, 0x7f,
1216 0xcd, 0x29, 0x8c, 0xfd, 0xc8, 0x19, 0x1e, 0xfb, 0x9e, 0x33, 0x32, 0xb6,
1217 0x61, 0x43, 0x7f, 0xcf, 0x86, 0x0d, 0xbb, 0x7b, 0x5c, 0x99, 0x00, 0x8f,
1218 0x65, 0xbc, 0x0d, 0x1b, 0x46, 0x7a, 0xba, 0x80, 0x83, 0x2d, 0x5e, 0x9f,
1219 0xf8, 0xde, 0x76, 0x01, 0xff, 0xc4, 0xd8, 0x67, 0x14, 0xf9, 0x49, 0xe4,
1220 0xb3, 0x7e, 0x5c, 0xe7, 0xf7, 0xca, 0x96, 0x78, 0x93, 0xb0, 0xff, 0x88,
1221 0x2d, 0x53, 0x13, 0x91, 0xfa, 0x07, 0xec, 0xfc, 0x66, 0x9c, 0x1a, 0x9f,
1222 0xe9, 0x1c, 0x0b, 0xd3, 0x39, 0xb7, 0x7f, 0x67, 0x6d, 0xd5, 0xd5, 0x48,
1223 0xe7, 0x37, 0x71, 0x46, 0xbc, 0xd0, 0xc6, 0xa8, 0xd1, 0xb6, 0x61, 0xae,
1224 0x48, 0x9a, 0x71, 0x65, 0x4f, 0xd1, 0x41, 0x1d, 0xd0, 0xc5, 0x19, 0xfb,
1225 0x1c, 0x05, 0x6c, 0x83, 0x68, 0xeb, 0xe8, 0x21, 0xd4, 0xa3, 0xcc, 0x48,
1226 0x76, 0x8a, 0xfa, 0x00, 0xca, 0x6c, 0xf1, 0xd6, 0x0a, 0x6d, 0x89, 0x3b,
1227 0x25, 0x57, 0x22, 0x7f, 0x77, 0x00, 0x9e, 0xa8, 0x24, 0x9a, 0xf1, 0x5d,
1228 0x81, 0x4d, 0xf1, 0x60, 0x8d, 0x58, 0xdb, 0x45, 0xe6, 0x6d, 0x91, 0x3b,
1229 0x94, 0xc0, 0xde, 0x18, 0x9a, 0x5c, 0x8f, 0x72, 0x0e, 0xf0, 0x42, 0xfb,
1230 0x03, 0xb4, 0x36, 0x99, 0x91, 0xec, 0x26, 0xf0, 0xc9, 0xa4, 0x87, 0x6f,
1231 0xc0, 0x35, 0xf9, 0x16, 0xbc, 0x23, 0xfa, 0xdb, 0xc0, 0x09, 0xbc, 0xa6,
1232 0x22, 0x56, 0x67, 0x75, 0xa1, 0xef, 0xf7, 0x48, 0x76, 0x34, 0x4e, 0x5b,
1233 0x62, 0x75, 0xd6, 0xcf, 0x40, 0xd7, 0x2b, 0x28, 0x41, 0x8c, 0x61, 0xd2,
1234 0x81, 0x3c, 0xa9, 0x95, 0xdd, 0x8f, 0xe0, 0xf7, 0x83, 0xc6, 0xe6, 0xdd,
1235 0x3d, 0xc9, 0x7e, 0x1a, 0x00, 0x13, 0x6c, 0x90, 0x47, 0x60, 0x9b, 0x3e,
1236 0x02, 0x1b, 0xe4, 0x91, 0x66, 0x3c, 0x1c, 0x1b, 0xdb, 0x9f, 0x59, 0x03,
1237 0x31, 0xa9, 0xbf, 0x73, 0xa4, 0x57, 0xd8, 0xea, 0xb9, 0x62, 0xca, 0x94,
1238 0x2f, 0x76, 0xeb, 0xb7, 0xa1, 0xeb, 0x1e, 0xfb, 0x3b, 0xae, 0xf9, 0x3a,
1239 0xdf, 0x04, 0x9a, 0xaf, 0x74, 0x69, 0x99, 0x93, 0xf5, 0xf1, 0x86, 0xcd,
1240 0x99, 0x69, 0xe2, 0x18, 0xe3, 0x36, 0x2d, 0xae, 0xd3, 0x12, 0x4d, 0xd6,
1241 0xde, 0x28, 0x59, 0x5b, 0x03, 0xb8, 0x19, 0x6a, 0x06, 0xc4, 0x94, 0xcf,
1242 0x12, 0xe2, 0x93, 0x32, 0x00, 0xf4, 0x0b, 0x9b, 0xe2, 0xdc, 0x15, 0xe5,
1243 0xdf, 0xac, 0xb6, 0xb1, 0xce, 0x56, 0x48, 0xc7, 0xa4, 0xed, 0x20, 0xb8,
1244 0x3f, 0x55, 0x87, 0xf6, 0xc9, 0xf3, 0xb0, 0x40, 0x8e, 0x02, 0x26, 0x60,
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1397 0x38, 0xe6, 0x8c, 0x17, 0xb1, 0xe5, 0xaa, 0xd3, 0xa7, 0xea, 0x42, 0x5b,
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1514 0xd2, 0xe0, 0xf5, 0xeb, 0xdf, 0x2c, 0xd3, 0xe0, 0x81, 0x4f, 0x17, 0x95,
1515 0x61, 0x1a, 0xf3, 0x0a, 0x6b, 0x94, 0xde, 0xab, 0xa4, 0xf7, 0x28, 0xc9,
1516 0x83, 0xa9, 0x64, 0x62, 0x48, 0x25, 0xbd, 0x71, 0xd9, 0x0f, 0xb9, 0x43,
1517 0x39, 0x39, 0x73, 0x7f, 0x44, 0xb8, 0x9f, 0xef, 0x5d, 0x92, 0xf5, 0x29,
1518 0x3f, 0x0b, 0x9f, 0x57, 0x94, 0x75, 0x95, 0x97, 0x1a, 0xcc, 0xd8, 0xb8,
1519 0x0f, 0x01, 0x70, 0x36, 0xd1, 0x86, 0xbb, 0xb5, 0x81, 0x3c, 0x94, 0x50,
1520 0x11, 0xd9, 0x45, 0x3f, 0x5f, 0x7d, 0xb1, 0x5e, 0xea, 0xa7, 0xd7, 0x78,
1521 0x52, 0xd1, 0xe9, 0x66, 0x7f, 0x60, 0xb2, 0x73, 0x48, 0x89, 0x1e, 0x7b,
1522 0x46, 0xbd, 0x91, 0xcc, 0x9e, 0xb5, 0xfa, 0x23, 0x90, 0xc7, 0xb4, 0xbe,
1523 0x98, 0xf9, 0xbc, 0x2b, 0x17, 0x82, 0xb6, 0x4d, 0x17, 0xda, 0xb3, 0x5d,
1524 0xb4, 0x73, 0x57, 0xd9, 0xfd, 0x95, 0x8c, 0x63, 0xbd, 0x4b, 0x9e, 0xf3,
1525 0x0b, 0x18, 0xf7, 0x7e, 0xb9, 0xe0, 0xb3, 0xbf, 0x99, 0xcf, 0x79, 0xc2,
1526 0x74, 0xc2, 0x6e, 0xfa, 0x13, 0xf5, 0xa7, 0x80, 0x87, 0x7d, 0x52, 0x07,
1527 0x5f, 0xc9, 0xee, 0x4b, 0x0e, 0xe4, 0x45, 0xcf, 0x4b, 0x8f, 0xa0, 0xad,
1528 0x15, 0x3e, 0xf8, 0x10, 0x76, 0x73, 0xcd, 0x91, 0xab, 0x21, 0x77, 0x1d,
1529 0xbd, 0xc7, 0x02, 0x93, 0xe1, 0x4d, 0x61, 0xde, 0x33, 0x03, 0x2c, 0x57,
1530 0x2f, 0xd3, 0x31, 0xf2, 0xba, 0xe6, 0x97, 0x4f, 0x65, 0xfd, 0x76, 0x4f,
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1533 0x7b, 0xc0, 0x91, 0x81, 0x4c, 0xe0, 0xf3, 0x6a, 0x90, 0x8f, 0x31, 0xa6,
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1537 0x93, 0xf2, 0xed, 0x41, 0xe6, 0xb1, 0xdd, 0xec, 0xd5, 0xae, 0xd6, 0x0b,
1538 0x21, 0x2c, 0xc9, 0xce, 0x1c, 0xf2, 0x47, 0xb4, 0x1d, 0xef, 0xc9, 0xac,
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1832 0xbb, 0xac, 0x53, 0xcf, 0xd9, 0x0c, 0x6c, 0x59, 0x3b, 0x67, 0xda, 0x9e,
1833 0x2d, 0x84, 0x73, 0x36, 0x00, 0x8d, 0x53, 0xbe, 0x41, 0xcf, 0x99, 0x07,
1834 0xba, 0xc9, 0x03, 0xef, 0x79, 0xcc, 0x53, 0x1e, 0x73, 0x94, 0x2f, 0xb7,
1835 0xc8, 0xc4, 0x71, 0xd5, 0x5a, 0x23, 0x92, 0xd8, 0xed, 0xb7, 0xc8, 0xf0,
1836 0x14, 0x63, 0x05, 0x1b, 0x60, 0x83, 0x6d, 0xc4, 0xd3, 0x8a, 0x6f, 0xd6,
1837 0xe3, 0x1d, 0x1f, 0x0a, 0x75, 0xeb, 0x96, 0xd8, 0x59, 0x67, 0xd1, 0xf7,
1838 0xd3, 0xc0, 0xc3, 0xa3, 0xc0, 0xc3, 0x3c, 0xef, 0xbc, 0x50, 0x15, 0x5f,
1839 0xe2, 0x58, 0xb5, 0x0e, 0xc5, 0x78, 0x63, 0x7a, 0x3e, 0x75, 0x9c, 0xa9,
1840 0x54, 0xfb, 0x66, 0xec, 0xa9, 0x38, 0xed, 0xa9, 0xdc, 0xa8, 0x67, 0xce,
1841 0x60, 0x0d, 0xc0, 0x77, 0xf2, 0xf7, 0x69, 0x5a, 0x1f, 0x1a, 0x27, 0x5c,
1842 0xd1, 0x10, 0xae, 0x05, 0x73, 0xc6, 0x33, 0xb3, 0x4b, 0xe3, 0x18, 0x2f,
1843 0xcc, 0xed, 0x11, 0x87, 0x2e, 0x97, 0xd1, 0x14, 0xe3, 0x24, 0xad, 0xcb,
1844 0xc0, 0xf4, 0x94, 0xb6, 0x61, 0x45, 0x9d, 0x96, 0x03, 0x25, 0x9e, 0xb7,
1845 0xe5, 0x1a, 0xcc, 0xef, 0x31, 0x7e, 0xd4, 0x39, 0x21, 0xc7, 0xd0, 0x37,
1846 0xd7, 0xc5, 0x95, 0x8d, 0xcf, 0xac, 0xb2, 0x7b, 0xf2, 0xaa, 0x63, 0x34,
1847 0x66, 0xdd, 0x7c, 0xe1, 0xd9, 0x93, 0xe4, 0xc0, 0xac, 0x5e, 0x77, 0xe5,
1848 0x9a, 0xa1, 0x8c, 0x46, 0xa0, 0xfd, 0x76, 0x77, 0x27, 0x7b, 0xcc, 0x59,
1849 0xc3, 0x84, 0xf4, 0x97, 0xcc, 0xf8, 0x2f, 0xea, 0x7d, 0x93, 0x66, 0x7f,
1850 0xb8, 0xd9, 0x53, 0xb9, 0x5f, 0x2e, 0xa6, 0xa2, 0x55, 0x73, 0x5b, 0x27,
1851 0xc3, 0xc0, 0x85, 0x5e, 0xcb, 0x84, 0x5d, 0x9c, 0xeb, 0x7e, 0xbc, 0x89,
1852 0x67, 0xd1, 0xa2, 0x98, 0x9f, 0xc2, 0x38, 0xcf, 0xa7, 0xb3, 0xdd, 0x2b,
1853 0xb5, 0x45, 0x31, 0xcb, 0xb3, 0x4e, 0x90, 0x95, 0x6f, 0xdd, 0x12, 0xaf,
1854 0xd7, 0xf9, 0x2b, 0xec, 0x99, 0x16, 0xd8, 0x0d, 0xbb, 0x02, 0xf9, 0x33,
1855 0xe8, 0xc9, 0xd3, 0x76, 0x4c, 0x09, 0x1d, 0x93, 0x92, 0xe0, 0x7c, 0x2a,
1856 0x6e, 0xe3, 0xce, 0x1c, 0xcb, 0x98, 0xa5, 0x6f, 0x63, 0xff, 0xcc, 0xdb,
1857 0xd0, 0x5d, 0x9a, 0xd6, 0x1f, 0xd7, 0xb2, 0xb0, 0xcb, 0xda, 0xce, 0x3a,
1858 0x8e, 0x73, 0x42, 0xf4, 0x1e, 0xac, 0xd0, 0x37, 0xea, 0xa8, 0xf2, 0x0b,
1859 0x8c, 0x2f, 0x57, 0x18, 0x5b, 0x4e, 0x46, 0xcd, 0xfb, 0x84, 0xf4, 0xe5,
1860 0xf6, 0x6c, 0xe2, 0xdd, 0x30, 0xa1, 0x2f, 0xd7, 0x65, 0x7d, 0xb9, 0x46,
1861 0xed, 0xcb, 0x99, 0xd8, 0x43, 0xe3, 0x9c, 0x2f, 0x57, 0x18, 0xcb, 0x83,
1862 0x56, 0x6a, 0xed, 0x59, 0x09, 0x63, 0x0b, 0x0d, 0x17, 0x5d, 0xbd, 0x6f,
1863 0x24, 0x37, 0xa0, 0xe0, 0x37, 0x18, 0x1f, 0x8b, 0xb1, 0x0a, 0xa5, 0xfe,
1864 0xce, 0xfa, 0x17, 0x1b, 0x24, 0xd3, 0xbc, 0x02, 0xe3, 0x7e, 0x4a, 0xcf,
1865 0xb9, 0x59, 0xc3, 0x82, 0x5c, 0x1b, 0x64, 0xcc, 0x87, 0x67, 0x47, 0x35,
1866 0x7f, 0x25, 0x7a, 0x23, 0x9d, 0xc6, 0x9e, 0xf5, 0x13, 0x6b, 0xa5, 0xfe,
1867 0xb8, 0x53, 0x18, 0x8f, 0xda, 0x7e, 0x13, 0x80, 0xa9, 0x06, 0x73, 0xf3,
1868 0x4e, 0x2b, 0x93, 0xd9, 0xf7, 0x3b, 0xea, 0x18, 0x1b, 0x98, 0x2a, 0x9a,
1869 0x18, 0x60, 0x5f, 0x31, 0x12, 0x9e, 0x5b, 0x57, 0x5c, 0x47, 0xce, 0x0c,
1870 0xae, 0x00, 0x2c, 0x2b, 0x96, 0xb5, 0x59, 0x1f, 0x7b, 0x43, 0x1d, 0x45,
1871 0x9a, 0x7a, 0x4a, 0xef, 0x2f, 0x5c, 0xd9, 0x9d, 0xdc, 0xa9, 0xcf, 0x23,
1872 0xe9, 0x58, 0x62, 0x5e, 0xb8, 0x7f, 0xf7, 0x9b, 0xf2, 0x36, 0x2d, 0xfb,
1873 0x0f, 0xa4, 0xa8, 0xc7, 0xb6, 0xe9, 0xdf, 0xb5, 0xe9, 0x20, 0x38, 0xdf,
1874 0xfd, 0x2c, 0x6c, 0x16, 0xdf, 0xfb, 0x96, 0xb4, 0xc7, 0x7b, 0xb5, 0x0d,
1875 0x85, 0xb9, 0x1a, 0xac, 0x97, 0x15, 0xfe, 0xb8, 0xdd, 0xab, 0x68, 0xd6,
1876 0x03, 0x0b, 0xc2, 0xfb, 0x17, 0x3a, 0x6c, 0x5e, 0x3e, 0xa8, 0x07, 0x3d,
1877 0x7d, 0x44, 0x8c, 0xac, 0xc9, 0xcd, 0xcb, 0x1a, 0xee, 0xa7, 0xcb, 0x90,
1878 0xa0, 0xdd, 0x23, 0x92, 0xe4, 0xdd, 0x49, 0xec, 0xbb, 0x20, 0x57, 0x41,
1879 0x3f, 0xb3, 0x1e, 0x6d, 0x56, 0x7e, 0x73, 0x0f, 0x8a, 0xef, 0x1d, 0x84,
1880 0x8e, 0xb9, 0x61, 0xa9, 0x8e, 0x89, 0xd3, 0xbf, 0xcf, 0x8d, 0xd2, 0x47,
1881 0x5c, 0x89, 0x3a, 0x2d, 0xf2, 0xd1, 0xb1, 0xdf, 0x5a, 0x4b, 0x1e, 0x1b,
1882 0x82, 0x7c, 0x57, 0xf7, 0x87, 0xe7, 0x2e, 0x99, 0xc6, 0x7c, 0xb6, 0x5b,
1883 0x27, 0x89, 0xf7, 0x79, 0xf2, 0xc5, 0x4a, 0x32, 0x31, 0x0b, 0x1d, 0x35,
1884 0xe4, 0x0c, 0xb7, 0x9a, 0xd8, 0xe9, 0xa7, 0xd6, 0x9a, 0x73, 0x5a, 0xf5,
1885 0xc0, 0x69, 0x18, 0x4f, 0xad, 0xa6, 0xdd, 0x59, 0x2b, 0x97, 0x83, 0xa0,
1886 0xbe, 0x5b, 0xcb, 0xe2, 0x9d, 0x94, 0xc5, 0x07, 0x52, 0x1d, 0x86, 0x07,
1887 0xb4, 0xef, 0xc4, 0x3d, 0x00, 0xc0, 0x43, 0xb7, 0xcb, 0xbd, 0xd0, 0x96,
1888 0x4f, 0xfd, 0xcc, 0x8c, 0x95, 0x4f, 0xca, 0x59, 0xca, 0x9f, 0x6a, 0x6b,
1889 0x74, 0x81, 0xec, 0x3d, 0x34, 0x46, 0xbd, 0x9c, 0x9a, 0xfe, 0x26, 0xe4,
1890 0x55, 0x4e, 0xe3, 0xa1, 0x45, 0xee, 0x1b, 0x93, 0xcc, 0x45, 0xe8, 0xac,
1891 0xc2, 0xd4, 0x42, 0x1e, 0x5d, 0xda, 0x1e, 0xc7, 0x7a, 0x7a, 0xad, 0xf1,
1892 0x71, 0x17, 0x8e, 0x75, 0x9a, 0x7b, 0x8c, 0xf4, 0x58, 0xb9, 0x37, 0xff,
1893 0x9c, 0x1d, 0xeb, 0xca, 0x70, 0xac, 0x3d, 0x0b, 0xc7, 0x1a, 0xfa, 0xf8,
1894 0xa1, 0xfc, 0x4d, 0xe8, 0xb3, 0x49, 0xfa, 0x4c, 0xcc, 0xd8, 0x4a, 0xe9,
1895 0x1d, 0x6d, 0xb4, 0x72, 0xd3, 0x83, 0x0e, 0xe2, 0x79, 0xa1, 0xe9, 0xcf,
1896 0x79, 0x62, 0x71, 0xa6, 0x88, 0x07, 0xca, 0xdc, 0x26, 0x7d, 0x9e, 0x71,
1897 0x02, 0x7e, 0xd6, 0x87, 0x8b, 0x2c, 0x1b, 0xe6, 0x5f, 0x29, 0x46, 0x1c,
1898 0xfa, 0xd6, 0xf4, 0x9f, 0x3a, 0x97, 0xc4, 0x16, 0x4c, 0x1c, 0x98, 0xf1,
1899 0x5f, 0x73, 0xcf, 0x02, 0xf7, 0x7d, 0xdf, 0x01, 0xde, 0xfa, 0xed, 0x62,
1900 0xb2, 0x27, 0x1b, 0xa1, 0x3c, 0x9d, 0x95, 0x43, 0x95, 0x3e, 0x69, 0xd3,
1901 0x67, 0xed, 0xdf, 0x30, 0x46, 0x9c, 0xa9, 0x8e, 0x11, 0x8b, 0x63, 0x62,
1902 0xc4, 0x3b, 0x7f, 0x8e, 0x18, 0xb1, 0x38, 0x26, 0x46, 0xbc, 0x9c, 0x9f,
1903 0x35, 0x52, 0x9a, 0xc5, 0xb8, 0xea, 0x21, 0x53, 0x94, 0x93, 0x9b, 0x6a,
1904 0xc0, 0xbb, 0x16, 0x6f, 0xc0, 0x32, 0x56, 0xc0, 0xdb, 0xc3, 0xfb, 0x20,
1905 0xde, 0x31, 0x19, 0x99, 0xd3, 0x1d, 0xb3, 0x90, 0x1f, 0xd4, 0x69, 0xac,
1906 0x6b, 0xfc, 0x82, 0xc9, 0x72, 0x33, 0xca, 0x5d, 0x72, 0x26, 0x58, 0xaf,
1907 0xd4, 0x28, 0xc3, 0x63, 0x94, 0xdd, 0x4d, 0x32, 0x3a, 0x16, 0xda, 0xb8,
1908 0x9f, 0x5d, 0xcf, 0xb5, 0x81, 0x21, 0x09, 0x6d, 0xd8, 0x67, 0xd6, 0x9b,
1909 0xb5, 0xdb, 0x2d, 0x31, 0xa9, 0x5f, 0x8d, 0x39, 0x38, 0xee, 0x5c, 0x1c,
1910 0x5f, 0xbd, 0xc0, 0x96, 0x4d, 0xd8, 0xd8, 0xe0, 0xb8, 0xd5, 0xc1, 0xcb,
1911 0xcb, 0x88, 0xea, 0xf9, 0x8f, 0xdb, 0x73, 0xbc, 0x51, 0x7b, 0xd7, 0x5f,
1912 0x42, 0xcf, 0xcf, 0x40, 0x65, 0x16, 0xfd, 0xad, 0x57, 0x99, 0x71, 0x8e,
1913 0x73, 0xee, 0x7e, 0x1e, 0xc8, 0xc5, 0x56, 0x35, 0x34, 0xbe, 0x80, 0x2e,
1914 0x41, 0xb7, 0x1c, 0x9b, 0x03, 0xda, 0xbd, 0x57, 0x26, 0x46, 0x09, 0x5f,
1915 0x47, 0x3c, 0xa2, 0xcf, 0xf5, 0xe2, 0x7b, 0xdc, 0x9c, 0x27, 0xea, 0xad,
1916 0x84, 0x67, 0x7a, 0xd7, 0x00, 0xde, 0xc5, 0xe7, 0x7a, 0xad, 0x9e, 0xd6,
1917 0x36, 0x04, 0xcf, 0xf7, 0x86, 0x63, 0x58, 0x8e, 0x9e, 0x02, 0x19, 0xd6,
1918 0xfb, 0x7d, 0xd7, 0xca, 0xe9, 0x07, 0xe7, 0xce, 0x17, 0x34, 0xc1, 0x56,
1919 0x69, 0x85, 0xa9, 0x3c, 0xe0, 0xa6, 0xb9, 0xef, 0x82, 0xfb, 0x0b, 0x3a,
1920 0xe2, 0xb7, 0xe9, 0x73, 0x1f, 0xf3, 0x67, 0xac, 0xe7, 0xcf, 0x7e, 0x84,
1921 0x67, 0x5a, 0xe3, 0xd2, 0x07, 0x3a, 0xec, 0xd7, 0xe9, 0x31, 0x8c, 0x87,
1922 0x6b, 0xbe, 0x1a, 0x0f, 0x90, 0x3d, 0x5c, 0xfb, 0xc5, 0xd8, 0x2b, 0x2d,
1923 0x2a, 0xa7, 0xcf, 0x58, 0x47, 0x2d, 0x8d, 0x5d, 0x76, 0xf6, 0x94, 0x13,
1924 0x6a, 0x4f, 0xd9, 0x57, 0x7b, 0xcb, 0x36, 0xaf, 0xfb, 0x01, 0xcc, 0x07,
1925 0x7e, 0x8f, 0x17, 0x9d, 0x21, 0xe0, 0xab, 0x50, 0x3a, 0xe2, 0x64, 0xf4,
1926 0xfb, 0xa8, 0x7d, 0x43, 0x0e, 0x60, 0xae, 0x7a, 0xc7, 0xa3, 0x5a, 0xde,
1927 0xcf, 0xdf, 0xd3, 0x17, 0xce, 0xeb, 0x0b, 0x7a, 0x0d, 0x68, 0x5a, 0x88,
1928 0x6b, 0xcf, 0xda, 0x10, 0xc7, 0x9d, 0x9c, 0xc6, 0x3d, 0xcb, 0x7c, 0x4b,
1929 0xff, 0x06, 0x9d, 0x2b, 0xd3, 0x5e, 0x2b, 0xde, 0x8b, 0xf7, 0x4d, 0x86,
1930 0xfa, 0x86, 0x70, 0xdf, 0x09, 0xbd, 0x16, 0xec, 0x37, 0xf2, 0x6a, 0x56,
1931 0x46, 0x2a, 0x5c, 0xc3, 0x64, 0x3b, 0x48, 0x2f, 0xd7, 0xc0, 0x1e, 0x58,
1932 0x78, 0xbe, 0xba, 0x7f, 0x7e, 0x1e, 0x12, 0xe3, 0x42, 0x58, 0xee, 0xd6,
1933 0x67, 0x17, 0xab, 0xef, 0x1e, 0xb9, 0xf2, 0xbf, 0x70, 0xfd, 0xd0, 0xc8,
1934 0x50, 0x0b, 0x47, 0x86, 0xf2, 0xce, 0xc8, 0x95, 0xaf, 0xcb, 0x41, 0xe0,
1935 0xf1, 0x30, 0x60, 0x52, 0xf7, 0xf3, 0xce, 0xab, 0x57, 0xa5, 0x30, 0x59,
1936 0x2f, 0xea, 0xa1, 0x82, 0xe3, 0x3e, 0x54, 0x2b, 0x91, 0x87, 0x94, 0x53,
1937 0xf3, 0x50, 0xbb, 0xf6, 0xcf, 0x77, 0xa4, 0xda, 0xe3, 0x7b, 0xe5, 0xb8,
1938 0xe3, 0xde, 0xaf, 0xf4, 0x59, 0xdb, 0x82, 0xc7, 0x58, 0xdf, 0x71, 0x27,
1939 0x72, 0x7f, 0xd4, 0x9e, 0xd3, 0x37, 0xf1, 0xbd, 0x59, 0xcd, 0xf7, 0xdf,
1940 0x58, 0x47, 0x9c, 0xcd, 0x0a, 0xf1, 0xf1, 0x59, 0xc8, 0xad, 0x4f, 0x4b,
1941 0x76, 0x34, 0x31, 0x57, 0xc6, 0xec, 0xb3, 0xdf, 0xb0, 0xce, 0xf0, 0x0b,
1942 0xcb, 0xbc, 0xe2, 0xf0, 0xce, 0x1c, 0xa3, 0x33, 0x3e, 0xdf, 0x12, 0xee,
1943 0xb9, 0x37, 0x73, 0xca, 0xfc, 0xc6, 0x75, 0x52, 0xff, 0x0a, 0xe6, 0x8b,
1944 0xfd, 0x11, 0x57, 0xab, 0xf4, 0x3d, 0x05, 0x9e, 0x6c, 0x89, 0xd7, 0xcd,
1945 0xd9, 0x43, 0x46, 0xf6, 0xd6, 0x01, 0x6e, 0xc0, 0x6f, 0xec, 0x3b, 0x21,
1946 0x9d, 0x0a, 0x24, 0x37, 0x69, 0xb6, 0xa3, 0x67, 0x87, 0x98, 0x39, 0x33,
1947 0x34, 0xb3, 0xc2, 0xd8, 0x91, 0xf8, 0x36, 0x74, 0xa1, 0x64, 0xfb, 0xd8,
1948 0x4b, 0x4e, 0x3f, 0xcf, 0x3c, 0x8a, 0xb6, 0x1b, 0x97, 0xb3, 0x09, 0xc1,
1949 0x4b, 0xcf, 0x5b, 0xff, 0x32, 0x08, 0xc6, 0x52, 0x29, 0xde, 0x2b, 0xb8,
1950 0x8c, 0x4f, 0xb9, 0xca, 0x99, 0x1c, 0x6d, 0x70, 0x26, 0x46, 0x03, 0xd9,
1951 0x93, 0xe2, 0x9d, 0x49, 0xdc, 0x93, 0xa0, 0xe3, 0xe3, 0x48, 0x6b, 0x87,
1952 0x6e, 0x7d, 0xc7, 0x3a, 0xee, 0x71, 0xbb, 0xd9, 0x6f, 0xb4, 0xe5, 0x88,
1953 0x63, 0xfa, 0xca, 0xed, 0x27, 0x72, 0xc2, 0xbb, 0x8b, 0xb6, 0xc4, 0x63,
1954 0x7a, 0x7f, 0xe2, 0x17, 0x50, 0x0f, 0x7d, 0x94, 0xd8, 0xaf, 0xeb, 0x4c,
1955 0x40, 0x9e, 0x4d, 0x8e, 0xf1, 0xbe, 0x14, 0x9e, 0x63, 0x88, 0xb4, 0x2a,
1956 0xb9, 0xd6, 0x1b, 0xb6, 0xf7, 0x69, 0xe6, 0xe1, 0x0a, 0x45, 0x74, 0xda,
1957 0x16, 0x6f, 0xf7, 0xdc, 0x1d, 0x9b, 0x61, 0x5a, 0x78, 0xd7, 0xa6, 0xd2,
1958 0x67, 0x56, 0xe0, 0xd3, 0x9e, 0x1e, 0x92, 0xb8, 0x33, 0x55, 0x6c, 0x75,
1959 0x4e, 0x16, 0x33, 0x5b, 0xd7, 0x81, 0x3e, 0xce, 0xa7, 0x3e, 0x46, 0xf9,
1960 0x05, 0xdb, 0xef, 0x45, 0xc9, 0x57, 0x3e, 0x24, 0xe3, 0x2d, 0xed, 0xde,
1961 0xfd, 0x7a, 0x6e, 0x2e, 0x03, 0x67, 0x2d, 0x2a, 0x3b, 0xfa, 0xc4, 0x3a,
1962 0xea, 0xb7, 0xdd, 0x45, 0x05, 0x5e, 0x56, 0xbf, 0x88, 0x07, 0x36, 0x6e,
1963 0xad, 0xb6, 0x51, 0xf6, 0xa6, 0x58, 0xae, 0xc1, 0xe9, 0x1d, 0x5d, 0x85,
1964 0x79, 0xdc, 0x05, 0xfd, 0xe9, 0xc0, 0x46, 0x22, 0xae, 0x1b, 0x9c, 0x3d,
1965 0xa3, 0x79, 0xf4, 0xc8, 0x7d, 0xd6, 0xbc, 0xf7, 0xf0, 0x30, 0xc6, 0xa8,
1966 0xe5, 0x2b, 0x78, 0xf7, 0x12, 0xd7, 0xdb, 0x83, 0x49, 0xd8, 0x06, 0xb9,
1967 0xae, 0x7f, 0x67, 0xd7, 0xab, 0xa7, 0xaf, 0xb0, 0x5e, 0xed, 0xc9, 0x23,
1968 0x15, 0x7d, 0x6f, 0x48, 0xe7, 0xb8, 0xe2, 0x3a, 0x6e, 0xf3, 0x55, 0x7a,
1969 0x7e, 0x54, 0x87, 0xdd, 0x1b, 0x78, 0x72, 0x9d, 0xbd, 0xd3, 0x06, 0x70,
1970 0x5c, 0x05, 0x18, 0x36, 0x62, 0xfc, 0x84, 0xc1, 0xd4, 0x11, 0x75, 0x4b,
1971 0x9c, 0x3a, 0x70, 0x56, 0x4e, 0xaf, 0x0b, 0xf7, 0x7b, 0xa0, 0x1d, 0xc8,
1972 0xb5, 0x47, 0xe3, 0x46, 0x37, 0xae, 0x5d, 0xa6, 0x9d, 0x70, 0x3c, 0x8e,
1973 0x1d, 0x0f, 0x69, 0x75, 0x43, 0x0b, 0xfd, 0x89, 0x59, 0xa9, 0x5b, 0x54,
1974 0x9e, 0xf1, 0xfc, 0x5d, 0xad, 0x66, 0xdf, 0x11, 0xcb, 0x7a, 0xb0, 0x4b,
1975 0x69, 0xe3, 0x12, 0x77, 0x7a, 0xae, 0x8a, 0xdc, 0x5b, 0x9c, 0xf3, 0x2f,
1976 0x43, 0x9e, 0x5c, 0xeb, 0xbd, 0x4d, 0x91, 0xf6, 0x42, 0xfc, 0x12, 0xb7,
1977 0x09, 0xe0, 0x95, 0x71, 0x95, 0xd3, 0x41, 0x66, 0x80, 0x7c, 0xc5, 0x36,
1978 0x98, 0xff, 0xa2, 0x8e, 0xe5, 0x0e, 0xa6, 0x18, 0x27, 0x6a, 0x3f, 0x71,
1979 0x87, 0x0a, 0x65, 0xd3, 0x2c, 0xd7, 0x10, 0x1c, 0xde, 0x21, 0xba, 0x0b,
1980 0x1d, 0x5e, 0x9c, 0x52, 0xce, 0x37, 0xc7, 0x5c, 0x7c, 0xd7, 0xd8, 0xfb,
1981 0x42, 0x8d, 0x6e, 0x12, 0xf9, 0xeb, 0x70, 0xbc, 0xf1, 0x3c, 0xe6, 0xfb,
1982 0x12, 0xe6, 0x7b, 0xf9, 0xfb, 0x41, 0x91, 0x57, 0x46, 0x5e, 0xf9, 0x43,
1983 0x41, 0xa6, 0x89, 0xf4, 0x47, 0x9a, 0x7b, 0x3d, 0x9f, 0x59, 0xef, 0x63,
1984 0x02, 0x6c, 0x67, 0xc1, 0x0b, 0x19, 0xae, 0x25, 0x07, 0xc7, 0x52, 0x37,
1985 0x81, 0x17, 0x76, 0xca, 0x9f, 0xc0, 0x16, 0xf8, 0xe3, 0x4a, 0x1a, 0x3c,
1986 0xd1, 0x03, 0x1e, 0xe9, 0x06, 0x5f, 0xa4, 0xb4, 0x5d, 0xfc, 0x28, 0x74,
1987 0xde, 0xd9, 0x4a, 0xc9, 0xd9, 0x3b, 0x5a, 0x74, 0x72, 0xa3, 0x47, 0x41,
1988 0x17, 0xdc, 0x03, 0xab, 0xae, 0xa9, 0x11, 0x37, 0x3e, 0x29, 0xa4, 0xff,
1989 0x76, 0xee, 0xed, 0x68, 0x06, 0xae, 0xce, 0x10, 0x57, 0x93, 0x95, 0x2d,
1990 0xde, 0x3a, 0xf0, 0x41, 0xb3, 0xe6, 0x83, 0x46, 0x27, 0xe3, 0xdd, 0x64,
1991 0xf9, 0x60, 0x04, 0x7c, 0x50, 0x58, 0xc2, 0x07, 0xcf, 0x58, 0x9a, 0x9f,
1992 0xae, 0xe2, 0x83, 0x49, 0x9b, 0x36, 0x7e, 0x05, 0x3e, 0xb8, 0xca, 0x4f,
1993 0x3e, 0x39, 0x24, 0x27, 0xc0, 0x07, 0x0f, 0x6b, 0x3e, 0xb8, 0x4a, 0xf3,
1994 0x01, 0xe3, 0x46, 0xe4, 0x85, 0x56, 0xc8, 0x0e, 0xf2, 0xc2, 0xb3, 0x32,
1995 0x0b, 0x5e, 0x78, 0x51, 0xb1, 0xef, 0xcb, 0xb4, 0x0f, 0x46, 0xe9, 0x8f,
1996 0x9d, 0x2a, 0x15, 0xc1, 0xbb, 0x4a, 0xbe, 0x30, 0x16, 0x04, 0x33, 0xf0,
1997 0xd1, 0x1f, 0x84, 0x0d, 0xef, 0xea, 0x3b, 0x69, 0xa7, 0x61, 0xbb, 0x10,
1998 0x36, 0xda, 0xe4, 0xe3, 0x0e, 0xe8, 0xfd, 0xf0, 0x04, 0xc6, 0xb0, 0x47,
1999 0xfd, 0x3e, 0xfc, 0x60, 0x0f, 0xf3, 0x4a, 0xdb, 0xfe, 0xb8, 0xe6, 0x9b,
2000 0x1a, 0xe8, 0x80, 0x93, 0xdd, 0x8c, 0x33, 0xf9, 0xde, 0x5e, 0xd5, 0x9e,
2001 0xef, 0x03, 0xcc, 0x11, 0x75, 0xbf, 0x30, 0xc6, 0xd1, 0xb4, 0xc8, 0xb6,
2002 0xa7, 0x5c, 0x18, 0x90, 0xfb, 0x6c, 0x5e, 0x3e, 0xa8, 0x83, 0x1d, 0x5a,
2003 0xa7, 0x8c, 0x5d, 0xae, 0xb6, 0x25, 0xbd, 0xdf, 0x80, 0xd0, 0xac, 0x4d,
2004 0x9b, 0x3d, 0x81, 0x7d, 0xc5, 0x6a, 0xbb, 0xfe, 0x5e, 0xd8, 0xf5, 0xac,
2005 0x23, 0xae, 0xb1, 0xeb, 0xef, 0xb2, 0xbc, 0xc6, 0xdf, 0x9e, 0xb6, 0xf1,
2006 0x0f, 0x00, 0xbe, 0x1d, 0x73, 0x36, 0x3e, 0xdb, 0xa0, 0xad, 0x21, 0x72,
2007 0x03, 0xec, 0xbc, 0x1b, 0xc1, 0x83, 0x37, 0xc1, 0x8f, 0x7a, 0x77, 0xd1,
2008 0x93, 0x9d, 0xc5, 0x66, 0xf8, 0xdb, 0xad, 0xf2, 0xab, 0x63, 0x1b, 0xa5,
2009 0x7f, 0xf4, 0x77, 0x9a, 0xa1, 0x57, 0x61, 0x97, 0xbe, 0x08, 0x38, 0x23,
2010 0x56, 0x56, 0x47, 0xc1, 0x03, 0xed, 0x89, 0x1f, 0xa8, 0x44, 0xab, 0x91,
2011 0xed, 0x3c, 0x4b, 0xbe, 0x5c, 0x3b, 0x31, 0xd4, 0x67, 0x1c, 0xa5, 0x45,
2012 0xce, 0x1c, 0xa7, 0xe7, 0x95, 0x80, 0x2d, 0x9e, 0x82, 0x1d, 0xb2, 0x01,
2013 0xed, 0x31, 0x96, 0xbc, 0x5a, 0x9e, 0xd9, 0xea, 0xde, 0x9d, 0xd3, 0x7c,
2014 0x78, 0xc9, 0xc9, 0x8e, 0xdd, 0x24, 0x85, 0xc1, 0x28, 0xc6, 0xa0, 0x9a,
2015 0xd7, 0xca, 0xf5, 0xd2, 0xaf, 0xc7, 0x73, 0x59, 0x0e, 0x42, 0x1f, 0xff,
2016 0x69, 0xb1, 0x5f, 0x66, 0x07, 0x9a, 0xf0, 0x1d, 0x95, 0x67, 0x8a, 0x5b,
2017 0xe0, 0xef, 0xfc, 0x0a, 0x70, 0x54, 0x8b, 0xef, 0x5a, 0xe9, 0x5d, 0x47,
2018 0x5e, 0x6d, 0x90, 0x19, 0xa4, 0xdf, 0x28, 0xbf, 0x64, 0xd3, 0x99, 0x46,
2019 0xde, 0x68, 0x40, 0xdd, 0xa8, 0x9c, 0x2f, 0xd2, 0x96, 0xd4, 0x3c, 0xd1,
2020 0xf3, 0xb2, 0x6c, 0xc9, 0xbc, 0x0c, 0xdb, 0xf4, 0x59, 0x3c, 0xcf, 0x4b,
2021 0x72, 0xe7, 0x6e, 0x67, 0x4b, 0xa2, 0xdd, 0x81, 0xbe, 0xc4, 0xe3, 0x3a,
2022 0x5b, 0xbc, 0x5a, 0xe7, 0x5a, 0xdb, 0x46, 0x8d, 0x3c, 0x3f, 0xa8, 0xe2,
2023 0x0d, 0x98, 0x93, 0xcd, 0x4e, 0x87, 0x4d, 0xe3, 0xb7, 0xbe, 0x2f, 0x51,
2024 0xda, 0xcf, 0xa8, 0x0d, 0xab, 0x44, 0xda, 0x1a, 0x60, 0xe7, 0xec, 0x11,
2025 0xd5, 0xdc, 0x20, 0xae, 0xb4, 0x4f, 0xa8, 0x56, 0xa4, 0xf9, 0x36, 0x2d,
2026 0xd6, 0x00, 0x9d, 0x80, 0xb4, 0x16, 0xa4, 0x6d, 0xb2, 0x69, 0x4d, 0x0d,
2027 0x52, 0x8b, 0xb4, 0xcb, 0x9a, 0xe7, 0x2f, 0x76, 0xf8, 0x5e, 0xce, 0xa9,
2028 0x97, 0xb6, 0x53, 0x0d, 0x90, 0x0d, 0xab, 0x65, 0x66, 0x6b, 0x9d, 0xb4,
2029 0x21, 0x8f, 0x31, 0xee, 0xd4, 0xa9, 0xa8, 0xbc, 0xf3, 0x54, 0x7b, 0xfc,
2030 0xa3, 0x18, 0x43, 0xfb, 0x19, 0xc6, 0xbc, 0xff, 0xac, 0x99, 0x31, 0x9f,
2031 0xb6, 0x33, 0x7c, 0xd7, 0x69, 0xf9, 0x43, 0x7c, 0x98, 0x3b, 0xdf, 0x60,
2032 0x63, 0x94, 0x8e, 0x3b, 0xc3, 0xa3, 0xd4, 0xdb, 0xed, 0xf6, 0x7e, 0xa2,
2033 0xff, 0xd9, 0x4c, 0x5f, 0x6d, 0x82, 0x36, 0x54, 0x89, 0xfc, 0x48, 0xdd,
2034 0x83, 0xf7, 0xb8, 0x23, 0x85, 0x79, 0x99, 0x35, 0x45, 0xbe, 0x3a, 0xae,
2035 0xb8, 0x4f, 0x05, 0x69, 0x95, 0x77, 0x05, 0x66, 0x8e, 0xc9, 0x0b, 0x46,
2036 0x2e, 0xfd, 0x9a, 0x91, 0x4b, 0xa7, 0xcf, 0x2d, 0x90, 0x4b, 0x05, 0x2d,
2037 0x97, 0x06, 0x05, 0xef, 0xa9, 0x02, 0xe4, 0xd2, 0x08, 0xbe, 0x3d, 0x2d,
2038 0x97, 0x62, 0x62, 0x6d, 0x64, 0x89, 0x5e, 0xc5, 0xfe, 0x27, 0x4b, 0xae,
2039 0xb6, 0xa5, 0x0a, 0xe3, 0xb0, 0x43, 0x4a, 0x23, 0x56, 0x67, 0x4b, 0xba,
2040 0x49, 0x3a, 0x7a, 0x7e, 0x2a, 0xa1, 0x9d, 0x39, 0xdb, 0xcc, 0x3b, 0x8f,
2041 0x5f, 0x54, 0x94, 0x61, 0x27, 0x20, 0xc3, 0x1e, 0xbe, 0x82, 0x0c, 0x43,
2042 0x5e, 0x19, 0x79, 0x65, 0xb6, 0xfb, 0xdd, 0x9f, 0x0e, 0x79, 0x94, 0x1f,
2043 0x94, 0x19, 0x90, 0x49, 0x25, 0xc8, 0xa4, 0x12, 0xe4, 0x54, 0x09, 0x72,
2044 0xa9, 0x04, 0xb9, 0x54, 0x82, 0x5c, 0x2a, 0x41, 0x2e, 0x41, 0xc6, 0x3d,
2045 0x0a, 0x19, 0x67, 0x64, 0xda, 0x00, 0xed, 0x35, 0xb9, 0xcf, 0xea, 0x77,
2046 0x13, 0x27, 0xe9, 0xb2, 0x7e, 0x91, 0xd9, 0xb3, 0x7a, 0xae, 0x2a, 0x2e,
2047 0xb8, 0xeb, 0x88, 0xe6, 0x77, 0xcf, 0x57, 0xd7, 0x3a, 0xdc, 0x1f, 0xf3,
2048 0x03, 0xed, 0xb3, 0x6f, 0xe6, 0x6f, 0xa9, 0x03, 0x5f, 0xbf, 0x62, 0xf9,
2049 0x7a, 0xf3, 0x1c, 0x5f, 0x27, 0x1d, 0xc6, 0x89, 0x97, 0xe7, 0xeb, 0x16,
2050 0x9b, 0x97, 0x0f, 0x56, 0x80, 0xaf, 0x57, 0x2c, 0xe2, 0xeb, 0x28, 0xf8,
2051 0x7a, 0xe7, 0x12, 0xbe, 0x5e, 0xe5, 0xf4, 0xea, 0x3a, 0x3c, 0x83, 0xc6,
2052 0xef, 0x5a, 0x67, 0x9e, 0xaf, 0xf7, 0x6b, 0xbe, 0x3e, 0x04, 0xbe, 0xbe,
2053 0xbe, 0x8a, 0xaf, 0x77, 0x4a, 0xf2, 0x96, 0x6c, 0x64, 0xa3, 0xec, 0xbe,
2054 0x5f, 0x35, 0xaf, 0x91, 0x7f, 0x11, 0x53, 0xdf, 0xf0, 0x58, 0xef, 0x58,
2055 0xb3, 0xe4, 0x1e, 0xfa, 0x11, 0xd7, 0x06, 0xc8, 0x23, 0x43, 0x19, 0xc7,
2056 0x93, 0x83, 0x47, 0x7e, 0x20, 0xd3, 0x9a, 0xb7, 0x44, 0xf6, 0x1c, 0x89,
2057 0xca, 0xf0, 0x11, 0xc6, 0x1e, 0xbe, 0x63, 0xe9, 0xbd, 0x4e, 0x86, 0x07,
2058 0xb9, 0x5f, 0xd2, 0x95, 0xdd, 0x47, 0xe0, 0x63, 0x1d, 0x61, 0xec, 0xe1,
2059 0xf2, 0x1c, 0x8f, 0x4d, 0x43, 0xb6, 0xec, 0x3e, 0xa2, 0xe7, 0x1a, 0xed,
2060 0x34, 0xc8, 0xa1, 0x23, 0x22, 0xb7, 0x1d, 0x71, 0xe5, 0xf6, 0x23, 0x73,
2061 0xbc, 0x36, 0x10, 0xf2, 0xda, 0x9f, 0x83, 0xd7, 0xda, 0x2d, 0xaf, 0xa9,
2062 0x39, 0x5e, 0xfb, 0x5a, 0x15, 0xaf, 0xb1, 0x3e, 0x79, 0xed, 0x82, 0x4d,
2063 0xe3, 0xb7, 0x2b, 0x7b, 0x8f, 0xb4, 0xca, 0xee, 0x87, 0xde, 0x22, 0x7b,
2064 0xee, 0x27, 0xac, 0xe6, 0x9e, 0x3c, 0xda, 0x5f, 0xe3, 0x95, 0x76, 0xb4,
2065 0x1f, 0xee, 0x0f, 0xd2, 0x77, 0x65, 0x75, 0x4e, 0x48, 0x32, 0xcf, 0xfe,
2066 0x6a, 0xe1, 0x3b, 0x9f, 0x82, 0x4f, 0xb1, 0x17, 0x30, 0xdd, 0x7a, 0x44,
2067 0x92, 0xae, 0xbc, 0x26, 0x23, 0xa9, 0x47, 0x5b, 0x8d, 0x3d, 0x71, 0x09,
2068 0xbc, 0x42, 0xfa, 0xcf, 0x48, 0xee, 0xed, 0x81, 0xf6, 0x2b, 0x46, 0xcb,
2069 0x42, 0xff, 0x9f, 0x31, 0x73, 0xc7, 0xdc, 0x77, 0xc7, 0xf3, 0xbe, 0x35,
2070 0xfa, 0xbc, 0x9b, 0x8e, 0xd7, 0x76, 0x33, 0xbf, 0x46, 0xef, 0x37, 0xcd,
2071 0xe9, 0xb3, 0xdc, 0xac, 0xcf, 0x76, 0x62, 0x3a, 0x9e, 0x5e, 0x28, 0xf3,
2072 0x8e, 0x30, 0xde, 0xbd, 0xcc, 0xbb, 0x06, 0xff, 0xf8, 0x2a, 0x13, 0x9b,
2073 0x25, 0xdf, 0x7d, 0xdd, 0xc9, 0x15, 0x2f, 0xe9, 0x7d, 0x85, 0x59, 0x1f,
2074 0xbf, 0xcb, 0xfc, 0x66, 0xf9, 0x4b, 0x8c, 0x71, 0x24, 0x12, 0xea, 0x81,
2075 0x56, 0xee, 0x3b, 0x18, 0x9c, 0x32, 0x76, 0x94, 0xe1, 0xd1, 0x06, 0xed,
2076 0x6b, 0x8c, 0xe0, 0x7b, 0xf7, 0x68, 0xa3, 0x53, 0xa0, 0x6d, 0x32, 0xd0,
2077 0xe0, 0xe4, 0xc7, 0xf7, 0xb4, 0x1a, 0x9b, 0x79, 0x20, 0xce, 0x3d, 0x85,
2078 0x19, 0xb5, 0x54, 0x26, 0x9f, 0x92, 0x50, 0x26, 0x27, 0x6f, 0xc9, 0xc0,
2079 0xb6, 0xce, 0x1d, 0xd1, 0xf7, 0xf7, 0x25, 0xda, 0x15, 0xc7, 0xf4, 0x09,
2080 0xc8, 0xd7, 0x90, 0x16, 0xe2, 0xf2, 0xf1, 0x23, 0xa4, 0x07, 0x15, 0x6b,
2081 0x94, 0xdf, 0xb2, 0xf4, 0x70, 0x59, 0x8a, 0x90, 0x3b, 0x47, 0x8e, 0xdc,
2082 0x2e, 0xe3, 0xbb, 0x16, 0xd3, 0xc3, 0x9e, 0x79, 0x7a, 0x88, 0xc1, 0x3e,
2083 0x73, 0xaa, 0xe9, 0xe1, 0x37, 0xe7, 0xe8, 0x61, 0xdc, 0xf9, 0xd7, 0xd2,
2084 0xc3, 0x0d, 0x0b, 0xe8, 0x61, 0x44, 0xd3, 0x43, 0xff, 0x1c, 0x3d, 0x8c,
2085 0x1c, 0x61, 0xbf, 0x7a, 0x5d, 0xd4, 0x9b, 0x71, 0x38, 0xe7, 0x73, 0xb4,
2086 0x90, 0x18, 0xd6, 0xfb, 0x44, 0x93, 0x79, 0x9e, 0x25, 0x5d, 0xa5, 0x18,
2087 0x1b, 0x99, 0x9f, 0xff, 0xc6, 0x7f, 0xd3, 0xf9, 0x7f, 0x47, 0xfc, 0xff,
2088 0xef, 0xfc, 0x5f, 0x8f, 0xf6, 0x29, 0x8b, 0x43, 0x79, 0x1c, 0xd2, 0xc3,
2089 0x7b, 0xe2, 0x46, 0x2f, 0x70, 0x8e, 0xf9, 0x6d, 0xf6, 0xac, 0x9f, 0x83,
2090 0xfc, 0x7b, 0x1c, 0xf2, 0xef, 0xb1, 0x05, 0xeb, 0x01, 0x3d, 0x36, 0x06,
2091 0x11, 0xc8, 0xc1, 0xd4, 0x3c, 0x3e, 0x66, 0xba, 0x89, 0x0f, 0xb3, 0xf7,
2092 0xe4, 0x6c, 0x65, 0x31, 0x4e, 0x5c, 0xbd, 0xdf, 0xe8, 0x64, 0xaa, 0x1a,
2093 0x27, 0x84, 0x7b, 0xb6, 0x6a, 0x8c, 0xf8, 0x5d, 0xe6, 0xf7, 0x65, 0xbd,
2094 0x87, 0xa4, 0xa0, 0xd7, 0x9f, 0x88, 0x17, 0xae, 0x3f, 0x11, 0x27, 0xae,
2095 0xb6, 0xf7, 0x0b, 0xe5, 0x3a, 0xbd, 0x2f, 0xfc, 0xc0, 0x54, 0x4c, 0x66,
2096 0x62, 0x8c, 0xeb, 0xf1, 0xde, 0x57, 0xfa, 0xca, 0x7e, 0xbc, 0x20, 0x79,
2097 0x7b, 0xd6, 0x67, 0x95, 0xa5, 0x6d, 0xc6, 0x03, 0x79, 0x27, 0x42, 0xb8,
2098 0x0e, 0xd1, 0x69, 0x65, 0x5d, 0x43, 0x55, 0x9c, 0x12, 0x78, 0x1f, 0x93,
2099 0x44, 0xb6, 0x1b, 0xef, 0x29, 0xf6, 0xfd, 0xa4, 0x8c, 0x3c, 0x58, 0x86,
2100 0x2d, 0xf7, 0x30, 0x74, 0x8e, 0x23, 0x10, 0x93, 0xfa, 0x2e, 0x14, 0xc2,
2101 0x30, 0xa1, 0xef, 0xf5, 0xa3, 0xdf, 0x47, 0x7a, 0x88, 0xe3, 0xfb, 0xb2,
2102 0x8d, 0x25, 0xc5, 0xa5, 0x50, 0xfc, 0x01, 0xe0, 0xe7, 0x1d, 0x94, 0x3f,
2103 0xc2, 0xfb, 0x8d, 0xe6, 0xc3, 0xf8, 0x21, 0x03, 0xfa, 0xcd, 0xb9, 0x79,
2104 0xcd, 0xc9, 0x94, 0xcd, 0xfe, 0x96, 0xaa, 0xfb, 0xf5, 0xe5, 0xb0, 0xb6,
2105 0x9f, 0xd3, 0x76, 0x5f, 0x0b, 0xcf, 0xe7, 0x19, 0x1b, 0xfa, 0xcb, 0xb0,
2106 0xa1, 0x9f, 0xa8, 0x64, 0xf4, 0x1a, 0xd6, 0x63, 0xb0, 0xa1, 0x1f, 0x85,
2107 0xee, 0xa1, 0xce, 0x89, 0x59, 0x9d, 0x33, 0xa2, 0x76, 0x69, 0x9d, 0xf3,
2108 0xd7, 0x5a, 0xe7, 0xfc, 0xea, 0x12, 0x9d, 0x73, 0x48, 0xb5, 0x8f, 0x52,
2109 0xe7, 0xf4, 0xaa, 0x9d, 0x0e, 0xed, 0xc5, 0xb5, 0xcb, 0xe8, 0x9c, 0xf7,
2110 0xca, 0xaf, 0xd8, 0xbc, 0xfd, 0xf2, 0xbe, 0x6d, 0x7a, 0xdd, 0xc6, 0x9b,
2111 0x50, 0xbc, 0xcb, 0xce, 0xe8, 0xa0, 0xeb, 0x55, 0xa7, 0x5e, 0xef, 0xfd,
2112 0x6a, 0x95, 0xce, 0x69, 0x53, 0xdd, 0x4e, 0xaf, 0xae, 0xc3, 0x78, 0x04,
2113 0xbf, 0x53, 0x4e, 0x66, 0xa0, 0x0e, 0xdf, 0x71, 0x89, 0x1c, 0xc1, 0xd8,
2114 0xcd, 0x7d, 0x7b, 0xca, 0xe4, 0x5d, 0x63, 0xf3, 0x54, 0x98, 0xee, 0x9a,
2115 0xf4, 0x76, 0x9b, 0x6e, 0x74, 0x55, 0x9b, 0x6a, 0xd5, 0xba, 0x6a, 0x33,
2116 0x18, 0x6a, 0x02, 0xfa, 0x75, 0xa2, 0x14, 0xea, 0x2c, 0xfe, 0x66, 0xbc,
2117 0x99, 0x71, 0x89, 0x30, 0x6e, 0x9d, 0x40, 0x19, 0x3c, 0xa5, 0xd0, 0xa6,
2118 0xe4, 0x6f, 0xf8, 0x0a, 0x78, 0xa6, 0x80, 0xd7, 0x5b, 0xc0, 0x3f, 0xbf,
2119 0x5e, 0x64, 0xdc, 0xb3, 0x59, 0x8e, 0x8e, 0x55, 0xe7, 0xb5, 0xca, 0xbb,
2120 0xc7, 0x36, 0xc8, 0xbe, 0x51, 0xff, 0x6a, 0xa9, 0xdf, 0x28, 0x23, 0xa3,
2121 0x2f, 0xea, 0xfb, 0x40, 0xd6, 0xe8, 0x7b, 0x92, 0x78, 0x7f, 0x98, 0x91,
2122 0x91, 0xfd, 0x8e, 0x91, 0x91, 0x19, 0x35, 0x6f, 0xb3, 0x86, 0x6d, 0xf2,
2123 0x6e, 0xa6, 0xbe, 0xd1, 0xb8, 0xbe, 0x43, 0x7a, 0xa2, 0x72, 0xad, 0xfc,
2124 0xd1, 0x71, 0x75, 0xa7, 0x9a, 0xbf, 0x4b, 0x41, 0xdb, 0xac, 0x93, 0x0b,
2125 0x6c, 0xd6, 0xbf, 0x97, 0x99, 0xf7, 0x45, 0x31, 0x4e, 0xd0, 0xf0, 0x75,
2126 0x2f, 0x73, 0x1d, 0xb4, 0x39, 0x26, 0x97, 0xa4, 0x4f, 0xe3, 0x8f, 0xf2,
2127 0xb4, 0x01, 0x72, 0x70, 0x56, 0xeb, 0xd7, 0xb5, 0xbc, 0xf3, 0xf8, 0x08,
2128 0x6d, 0xd7, 0xaf, 0x6b, 0x79, 0xb6, 0xd6, 0xda, 0xae, 0xd3, 0x90, 0xd3,
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2143 0xf9, 0x1b, 0x3a, 0x36, 0x5f, 0x7b, 0x4b, 0x1f, 0x7c, 0x76, 0xf1, 0x92,
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2160 0x4b, 0xea, 0x11, 0x2e, 0xae, 0x55, 0x2e, 0x94, 0xb1, 0x4a, 0x9f, 0x13,
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2187 0xee, 0x84, 0x7f, 0xab, 0x69, 0x12, 0xf2, 0x67, 0x8f, 0x5c, 0x6b, 0xe3,
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2274 0xf4, 0x97, 0x5b, 0x65, 0x7b, 0xb9, 0x41, 0x76, 0x40, 0x2f, 0xec, 0x28,
2275 0xfb, 0x78, 0xa2, 0x72, 0x63, 0xd9, 0xcc, 0xd3, 0x47, 0xca, 0x9c, 0xef,
2276 0x6d, 0x32, 0x71, 0xbc, 0x9a, 0x66, 0xa7, 0xed, 0xde, 0x31, 0xd2, 0x0f,
2277 0x9e, 0x52, 0x32, 0x3f, 0xad, 0xc7, 0xce, 0x5d, 0xac, 0xc9, 0xc3, 0xb3,
2278 0xc2, 0xbd, 0xf8, 0xfc, 0x1b, 0x74, 0xdf, 0x68, 0xe5, 0x19, 0x77, 0xde,
2279 0x8f, 0xd8, 0x5f, 0x09, 0xf7, 0x86, 0xbf, 0xfe, 0x19, 0x10, 0xfd, 0x77,
2280 0x5d, 0xf4, 0xde, 0x70, 0x4d, 0x7b, 0xd2, 0x76, 0x26, 0xa6, 0x75, 0x84,
2281 0xa1, 0xf1, 0xf9, 0xbf, 0xe7, 0x22, 0xf2, 0x7f, 0x01, 0x95, 0xf6, 0x2d,
2282 0x58, 0xd0, 0x73, 0x00, 0x00, 0x00 };
2283static u32 bnx2_CP_b09FwData[(0x50/4) + 1] = {
2284 0x00010030, 0x00000030, 0x00000000, 0x00000001, 0x00010fd0, 0x00000fd0,
2285 0x00001430, 0x0000007f, 0x00030400, 0x00001000, 0x00000030, 0x00000020,
2286 0x00050200, 0x00001000, 0x00000030, 0x00000010, 0x00010400, 0x00000400,
2287 0x00001030, 0x00000020, 0x00000000 };
2288static u32 bnx2_CP_b09FwRodata[(0x118/4) + 1] = {
2289 0x080005d8, 0x080007f8, 0x0800073c, 0x08000764, 0x0800078c, 0x080007b4,
2290 0x08000610, 0x080005fc, 0x08000820, 0x08000820, 0x0800062c, 0x08000648,
2291 0x08000648, 0x08000820, 0x08000660, 0x08000674, 0x08000820, 0x08000688,
2292 0x08000820, 0x08000820, 0x0800069c, 0x08000820, 0x08000820, 0x08000820,
2293 0x08000820, 0x08000820, 0x08000820, 0x08000820, 0x08000820, 0x08000820,
2294 0x08000820, 0x080006b0, 0x08000820, 0x080006c4, 0x080006d8, 0x080006ec,
2295 0x08000820, 0x08000700, 0x08000714, 0x08000728, 0x08003740, 0x08003758,
2296 0x08003768, 0x08003778, 0x08003790, 0x080037a8, 0x080037b8, 0x080037c8,
2297 0x080037e8, 0x080037f8, 0x08003808, 0x08003898, 0x080037d8, 0x08003818,
2298 0x08003828, 0x08003840, 0x08003860, 0x08003898, 0x08003878, 0x08003878,
2299 0x080055f0, 0x080055f0, 0x080055f0, 0x080055f0, 0x080055f0, 0x08005618,
2300 0x08005618, 0x08005640, 0x08005690, 0x08005660, 0x00000000 };
2301static u32 bnx2_CP_b09FwBss[(0x870/4) + 1] = { 0x0 };
2302static u32 bnx2_CP_b09FwSbss[(0xe9/4) + 1] = { 0x0 };
2303
2304static struct fw_info bnx2_cp_fw_09 = {
2305 .ver_major = 0x1,
2306 .ver_minor = 0x0,
2307 .ver_fix = 0x0,
2308
2309 .start_addr = 0x0800006c,
2310
2311 .text_addr = 0x08000000,
2312 .text_len = 0x73cc,
2313 .text_index = 0x0,
2314 .gz_text = bnx2_CP_b09FwText,
2315 .gz_text_len = sizeof(bnx2_CP_b09FwText),
2316
2317 .data_addr = 0x08007500,
2318 .data_len = 0x50,
2319 .data_index = 0x0,
2320 .data = bnx2_CP_b09FwData,
2321
2322 .sbss_addr = 0x08007554,
2323 .sbss_len = 0xe9,
2324 .sbss_index = 0x0,
2325 .sbss = bnx2_CP_b09FwSbss,
2326
2327 .bss_addr = 0x08007640,
2328 .bss_len = 0x870,
2329 .bss_index = 0x0,
2330 .bss = bnx2_CP_b09FwBss,
2331
2332 .rodata_addr = 0x080073d0,
2333 .rodata_len = 0x118,
2334 .rodata_index = 0x0,
2335 .rodata = bnx2_CP_b09FwRodata,
2336};
2337
2338static u8 bnx2_RXP_b09FwText[] = {
2339 0x1f, 0x8b, 0x08, 0x08, 0x19, 0xfd, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
2340 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5c, 0x6b, 0x6c,
2341 0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x20, 0xb5, 0xa2, 0xf8, 0x18, 0x2e, 0x57,
2342 0xcc, 0x4a, 0x66, 0xec, 0x5d, 0x71, 0x24, 0xb2, 0x16, 0x6b, 0x8c, 0xd8,
2343 0xad, 0x4d, 0x04, 0x6b, 0x7b, 0x33, 0xbb, 0x92, 0x98, 0x54, 0x85, 0x29,
2344 0x87, 0x75, 0x0c, 0xc3, 0x75, 0xd9, 0xa5, 0x1a, 0xbb, 0xae, 0x51, 0xc8,
2345 0x8f, 0xc4, 0x06, 0x6a, 0xd6, 0x9b, 0x25, 0xdd, 0xa8, 0xe9, 0x82, 0x43,
2346 0x4b, 0xaa, 0xe9, 0x02, 0x69, 0xbb, 0x20, 0xa9, 0xc7, 0x8f, 0x85, 0x56,
2347 0x76, 0x52, 0xc7, 0xf9, 0xe1, 0x48, 0x50, 0x95, 0x20, 0x28, 0x0c, 0x43,
2348 0x48, 0x8d, 0xd6, 0x3f, 0xda, 0x40, 0x95, 0x9f, 0x68, 0x92, 0x42, 0x41,
2349 0x0b, 0xc7, 0x68, 0x6c, 0x4f, 0xbf, 0xef, 0xce, 0x0c, 0xb9, 0xa4, 0x5f,
2350 0x40, 0x7f, 0xf4, 0x4f, 0xe7, 0x02, 0x8b, 0xb9, 0xf7, 0xce, 0x3d, 0xe7,
2351 0x9e, 0x7b, 0xde, 0xe7, 0x0e, 0xa5, 0xdf, 0xef, 0x94, 0x0e, 0x09, 0x5b,
2352 0x17, 0x7e, 0x99, 0xc3, 0x8f, 0x3d, 0x74, 0xc3, 0xd8, 0x0d, 0xa3, 0x22,
2353 0x7b, 0xf6, 0x18, 0x5b, 0x12, 0x7a, 0x34, 0x1f, 0xb7, 0xb8, 0xc5, 0x2d,
2354 0x6e, 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e,
2355 0x71, 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71,
2356 0x8b, 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b,
2357 0x5b, 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b,
2358 0xdc, 0xe2, 0x16, 0xb7, 0xb8, 0xc5, 0x2d, 0x6e, 0x71, 0x8b, 0x5b, 0xdc,
2359 0xe2, 0xf6, 0xff, 0xbd, 0x19, 0x22, 0x16, 0x9f, 0x5d, 0xe1, 0x4f, 0x12,
2360 0x7a, 0xfe, 0xf2, 0x1f, 0xba, 0xb6, 0x24, 0x8c, 0xfc, 0xcf, 0x66, 0xa6,
2361 0x6d, 0x91, 0x42, 0x63, 0x77, 0xa6, 0x28, 0xef, 0xfb, 0x95, 0x94, 0x29,
2362 0x9c, 0xff, 0x6c, 0xfe, 0xbd, 0xbf, 0x7d, 0xf1, 0xa6, 0xec, 0xd5, 0xba,
2363 0x21, 0x09, 0x2b, 0x3f, 0xb7, 0xc7, 0xda, 0x25, 0x89, 0x01, 0xc0, 0x7c,
2364 0x6b, 0xe8, 0xc7, 0xdd, 0xd2, 0x2d, 0x6b, 0x78, 0xec, 0x84, 0x5c, 0x36,
2365 0x5e, 0xd0, 0xdc, 0xa6, 0xef, 0x9f, 0x70, 0x7c, 0xff, 0x87, 0xf8, 0xbd,
2366 0xe5, 0x60, 0xec, 0x7d, 0xe0, 0x17, 0x4c, 0x43, 0x74, 0xfb, 0x2f, 0x34,
2367 0x77, 0xb9, 0x43, 0xaa, 0x8b, 0xa6, 0xcc, 0x7a, 0x29, 0x39, 0xe2, 0x55,
2368 0xb4, 0x52, 0xb3, 0xa6, 0xed, 0x3d, 0x35, 0xaf, 0xed, 0x3b, 0x75, 0x44,
2369 0xdb, 0x7f, 0x6a, 0x41, 0x73, 0x4f, 0x49, 0x45, 0xdf, 0xd3, 0x29, 0x05,
2370 0xeb, 0xb4, 0x56, 0x6c, 0xf6, 0x6b, 0xee, 0xe2, 0x7b, 0xbe, 0xeb, 0x64,
2371 0xad, 0xbb, 0xc4, 0x2c, 0x80, 0x16, 0x71, 0x6b, 0x3e, 0xc6, 0xa6, 0x14,
2372 0x52, 0xbe, 0xaf, 0xe7, 0xfd, 0x27, 0xdc, 0x9c, 0x6d, 0xe9, 0x5a, 0x4a,
2373 0xaa, 0xcd, 0x7e, 0xe0, 0xed, 0xd4, 0x8a, 0x8b, 0xa6, 0x56, 0xf2, 0xfc,
2374 0x73, 0xae, 0x23, 0x03, 0x86, 0xf8, 0xfe, 0x9c, 0xb3, 0x33, 0x7d, 0x48,
2375 0x4e, 0x02, 0x6f, 0x03, 0xf8, 0xc4, 0xd2, 0xf3, 0xa4, 0x8f, 0x74, 0x92,
2376 0xe4, 0x8a, 0x56, 0x1c, 0x8a, 0xe8, 0x93, 0x0c, 0xe9, 0x2f, 0xaf, 0xe8,
2377 0xa0, 0x73, 0x8b, 0x94, 0xeb, 0x96, 0x4c, 0xad, 0x6c, 0x5c, 0x7f, 0xd9,
2378 0x7f, 0x71, 0x28, 0x25, 0xcf, 0x36, 0xb3, 0x47, 0x2a, 0x92, 0x90, 0x39,
2379 0x2f, 0x23, 0x7a, 0x5e, 0x0a, 0x6e, 0x6e, 0x40, 0xce, 0x35, 0xd3, 0xf2,
2380 0x5c, 0xd3, 0x4e, 0x57, 0x65, 0x93, 0x94, 0x53, 0x96, 0x9c, 0x6d, 0xa6,
2381 0x70, 0x46, 0xff, 0x9c, 0x6e, 0xdb, 0x56, 0x15, 0x6b, 0xab, 0xcd, 0x97,
2382 0xf8, 0xef, 0x5f, 0xac, 0xe9, 0x9c, 0x82, 0xa9, 0x80, 0xee, 0x70, 0x2d,
2383 0xcf, 0xa1, 0xd6, 0xaa, 0xb3, 0x04, 0x6b, 0xa5, 0x32, 0x9d, 0xc3, 0x5c,
2384 0x73, 0x34, 0xe4, 0xef, 0x16, 0x9c, 0x97, 0x4f, 0x4b, 0xaa, 0x9e, 0x01,
2385 0xde, 0xb0, 0xff, 0xcf, 0xc0, 0x37, 0x80, 0xf3, 0x5e, 0xab, 0x7e, 0xee,
2386 0xa2, 0xa4, 0x74, 0xd9, 0x99, 0x2e, 0x0b, 0x78, 0xdb, 0xec, 0xc4, 0x98,
2387 0xf4, 0xf9, 0xfe, 0x7e, 0x47, 0xac, 0xaa, 0xd3, 0x03, 0x98, 0x8c, 0x54,
2388 0x9d, 0x6e, 0xe0, 0x69, 0x13, 0xcb, 0xe6, 0xb9, 0xb8, 0xd7, 0x66, 0xcc,
2389 0xfb, 0x5d, 0x46, 0xde, 0xf7, 0xa7, 0x73, 0xd2, 0x1d, 0xcc, 0xed, 0x56,
2390 0x38, 0xa6, 0x26, 0x34, 0xac, 0xfb, 0x05, 0x69, 0x4e, 0x24, 0xf3, 0xec,
2391 0xf3, 0x99, 0x13, 0x77, 0xfe, 0xda, 0x90, 0x96, 0x34, 0x68, 0xb9, 0x26,
2392 0xec, 0x83, 0xff, 0x1e, 0xf8, 0xe0, 0x7c, 0x06, 0x63, 0xed, 0x3a, 0xe0,
2393 0x19, 0xae, 0x0a, 0xf7, 0xe8, 0x93, 0xa5, 0x94, 0xe8, 0x57, 0x9c, 0xde,
2394 0x70, 0x5d, 0x37, 0x68, 0x8d, 0xf4, 0xa0, 0x5f, 0xe6, 0x16, 0xc9, 0xeb,
2395 0x1a, 0x64, 0x83, 0xe7, 0x8d, 0x15, 0xad, 0xd0, 0x3c, 0x82, 0xbe, 0x29,
2396 0xd3, 0xb6, 0x7f, 0x6e, 0xce, 0x99, 0xd7, 0x8a, 0xa7, 0x4e, 0x6a, 0xa5,
2397 0x53, 0x2f, 0x68, 0x7b, 0x9b, 0x2f, 0x74, 0x49, 0x47, 0x16, 0xa7, 0x4e,
2398 0xc8, 0x93, 0x9e, 0x26, 0xa4, 0x73, 0x09, 0xbc, 0x2b, 0x58, 0x15, 0x31,
2399 0xed, 0x6e, 0x6d, 0x1f, 0xf0, 0xb4, 0xd9, 0x7f, 0xd2, 0x29, 0xdd, 0x86,
2400 0x6c, 0xb2, 0xa3, 0xb5, 0x29, 0xf9, 0x33, 0xd0, 0x74, 0xc1, 0x49, 0x91,
2401 0x5f, 0x3d, 0x01, 0x4c, 0x44, 0x07, 0xf5, 0x8a, 0x3a, 0xa5, 0x17, 0x4a,
2402 0xc7, 0xff, 0xbc, 0xaf, 0x3a, 0xb2, 0x85, 0x6b, 0xa0, 0xff, 0xd6, 0xfd,
2403 0xd3, 0xb6, 0xdb, 0x6b, 0x4a, 0xc5, 0xd2, 0x25, 0x6b, 0x15, 0xe5, 0x3a,
2404 0x99, 0x73, 0x44, 0x8a, 0x35, 0xec, 0x69, 0x9b, 0xe0, 0x8d, 0x0d, 0xde,
2405 0xec, 0x3c, 0x32, 0xa8, 0xff, 0x96, 0x64, 0xfa, 0x2b, 0x9a, 0x19, 0xf2,
2406 0x71, 0x49, 0x6e, 0x51, 0xf0, 0x7a, 0xde, 0x81, 0x7e, 0x76, 0xb0, 0x8f,
2407 0x7d, 0x13, 0x6a, 0x5f, 0x23, 0x6f, 0xa7, 0x97, 0x45, 0x34, 0x3d, 0xbf,
2408 0x1b, 0xf8, 0xa8, 0xb7, 0x5c, 0xf7, 0x04, 0x68, 0x24, 0xed, 0xec, 0xdb,
2409 0x80, 0x49, 0x88, 0xeb, 0x74, 0xb5, 0xd0, 0x49, 0x79, 0x93, 0xd7, 0xe4,
2410 0x9d, 0x3a, 0xa7, 0xb6, 0x76, 0xce, 0x5f, 0xf9, 0x9b, 0x46, 0x4d, 0xf9,
2411 0xa1, 0x3a, 0x2f, 0x6d, 0x8c, 0xeb, 0x52, 0xa1, 0x4e, 0x24, 0xa0, 0x47,
2412 0xa2, 0x95, 0x1d, 0x6b, 0x15, 0x57, 0x59, 0x44, 0x37, 0xf2, 0x9d, 0x52,
2413 0x54, 0xf4, 0x8d, 0x61, 0x2f, 0xda, 0x1e, 0x6c, 0xc8, 0xe6, 0x59, 0x38,
2414 0x97, 0x87, 0x8d, 0x67, 0xd9, 0x97, 0xf2, 0x02, 0xed, 0x9d, 0xb4, 0x9d,
2415 0xcf, 0xaa, 0x7f, 0x8e, 0x45, 0x5d, 0x3c, 0xd6, 0x03, 0xda, 0x38, 0x86,
2416 0x1d, 0xda, 0x78, 0x3f, 0xa2, 0x89, 0x3b, 0x36, 0x08, 0xfe, 0x70, 0x9d,
2417 0x9d, 0x81, 0x9c, 0x0b, 0x2e, 0xf6, 0x74, 0x9d, 0xdf, 0x50, 0x3c, 0xe8,
2418 0xc5, 0x79, 0x06, 0xe7, 0xc9, 0xaf, 0x0e, 0xe8, 0xb6, 0x26, 0x65, 0x27,
2419 0x9b, 0xa1, 0xdc, 0x03, 0xda, 0x75, 0xd9, 0x74, 0x63, 0x2b, 0xed, 0x91,
2420 0xac, 0xa8, 0x87, 0xa6, 0x24, 0x47, 0xb9, 0x96, 0xeb, 0xb8, 0x3e, 0x3b,
2421 0x26, 0xfa, 0xaf, 0x7c, 0x6b, 0xdd, 0x59, 0x6d, 0xd9, 0x31, 0x0f, 0x1a,
2422 0x02, 0xde, 0x82, 0x27, 0x9f, 0xb6, 0x96, 0x7c, 0xdd, 0xc8, 0x3f, 0xae,
2423 0x6d, 0x5d, 0x07, 0x9d, 0xe8, 0x27, 0x0d, 0x27, 0x3a, 0x03, 0x5b, 0x8b,
2424 0x68, 0x8a, 0x64, 0xa3, 0x85, 0x38, 0x3e, 0xe9, 0x1c, 0x5c, 0x0f, 0x1f,
2425 0xe0, 0xc1, 0x07, 0xc0, 0xaf, 0x3d, 0xeb, 0xc1, 0xfe, 0x3d, 0xfa, 0x8c,
2426 0x8c, 0xbc, 0x38, 0x04, 0x1f, 0xb7, 0xe6, 0x63, 0xd0, 0xc6, 0xd1, 0xd7,
2427 0xc5, 0x80, 0x8f, 0x99, 0xad, 0xeb, 0xb0, 0x59, 0xf0, 0x78, 0x85, 0x73,
2428 0xb0, 0xed, 0x95, 0x12, 0x9e, 0xb6, 0x54, 0x1b, 0xd4, 0xab, 0xc8, 0x97,
2429 0xd2, 0xe7, 0xa4, 0xe1, 0x5f, 0xe8, 0x77, 0xe8, 0x57, 0xb8, 0xd6, 0xf7,
2430 0x4b, 0x0e, 0x61, 0x7d, 0x99, 0x70, 0x68, 0x43, 0x9d, 0xa2, 0x27, 0x2b,
2431 0xda, 0xc1, 0x21, 0xd8, 0xd6, 0xf5, 0x6d, 0xa0, 0x95, 0x36, 0x76, 0x8d,
2432 0x48, 0x3b, 0xf7, 0xfb, 0x69, 0x57, 0xf0, 0xef, 0xee, 0x36, 0x61, 0x0d,
2433 0x9f, 0xef, 0x86, 0x63, 0x2d, 0xf4, 0x2d, 0x7c, 0x9f, 0xcd, 0x14, 0xa4,
2434 0x3f, 0x1c, 0xb3, 0xbf, 0x4a, 0xaf, 0xa3, 0xdf, 0x98, 0x90, 0x1d, 0x27,
2435 0x03, 0x9f, 0xb8, 0x63, 0xc9, 0x12, 0xfb, 0x64, 0x40, 0xe3, 0x8e, 0x33,
2436 0x91, 0x6f, 0x7c, 0x1f, 0xf0, 0xa0, 0xcf, 0x5b, 0x8d, 0x03, 0x68, 0x3f,
2437 0xd3, 0x60, 0x2a, 0x98, 0xdb, 0xc8, 0x0b, 0xfa, 0x63, 0xda, 0x9b, 0xd5,
2438 0x6a, 0x6f, 0x7b, 0x60, 0x6f, 0x4e, 0xbb, 0x64, 0x9d, 0xbf, 0x87, 0xbd,
2439 0x7d, 0xc3, 0xd1, 0xc0, 0x1b, 0x91, 0x8b, 0xb5, 0x34, 0x6c, 0xdd, 0x4c,
2440 0xbf, 0x26, 0x3b, 0x33, 0xb3, 0xa2, 0xc9, 0x09, 0xce, 0x35, 0x30, 0xa7,
2441 0x7c, 0x71, 0xe0, 0x0b, 0x2e, 0x1b, 0x4f, 0x81, 0x2e, 0xdf, 0x9f, 0x05,
2442 0xce, 0xf2, 0x88, 0x11, 0xda, 0x56, 0x34, 0x6f, 0xdd, 0xef, 0xda, 0xee,
2443 0xaf, 0x19, 0x52, 0x19, 0x6e, 0x93, 0xec, 0xf0, 0x12, 0x70, 0x4f, 0x3b,
2444 0x81, 0x1d, 0x53, 0xd7, 0x97, 0x81, 0x7f, 0xce, 0x1b, 0x82, 0x1e, 0xd3,
2445 0x0e, 0x40, 0x17, 0xf0, 0x2f, 0x03, 0xff, 0x5c, 0xb3, 0x4d, 0xbe, 0x6e,
2446 0x46, 0xb1, 0x32, 0x3a, 0x4f, 0x37, 0x96, 0x45, 0xfb, 0x1e, 0x96, 0x2f,
2447 0x7a, 0x49, 0xcd, 0x3d, 0x46, 0xff, 0x5a, 0x1d, 0x86, 0x9d, 0x68, 0x55,
2448 0x87, 0x7b, 0x1b, 0xb2, 0xbc, 0xba, 0x46, 0x0a, 0xd5, 0xc0, 0x06, 0x0b,
2449 0xee, 0x50, 0x25, 0x6d, 0x28, 0x5f, 0x22, 0xb2, 0x0f, 0xb6, 0xb7, 0x6c,
2450 0x73, 0xcc, 0xf9, 0x60, 0x6e, 0xbc, 0xd6, 0x0f, 0x9f, 0xc8, 0xf1, 0x7b,
2451 0xfe, 0xb4, 0x13, 0xcc, 0x7d, 0xa1, 0x76, 0x57, 0x37, 0xfd, 0x2e, 0xe2,
2452 0x44, 0xa6, 0xea, 0xfc, 0xbb, 0x0f, 0xfd, 0x5d, 0x07, 0xf3, 0xd1, 0x78,
2453 0xb2, 0xe3, 0x81, 0xce, 0x8a, 0xb6, 0xdf, 0xd6, 0xfb, 0xdb, 0x43, 0x1f,
2454 0xb6, 0x1f, 0x93, 0x7b, 0x6b, 0xd5, 0xbe, 0x76, 0x79, 0xcf, 0x60, 0x1c,
2455 0xbd, 0x22, 0x62, 0xba, 0xb5, 0x5d, 0xe0, 0x47, 0xb5, 0xb7, 0x65, 0x2e,
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2895 0x01, 0xd9, 0xbc, 0x7e, 0xc0, 0xf7, 0x1f, 0x19, 0x19, 0x11, 0xe7, 0x00,
2896 0x31, 0xca, 0x70, 0x82, 0x39, 0xae, 0x94, 0x39, 0x19, 0xdb, 0x3e, 0x5f,
2897 0x51, 0x0a, 0xf2, 0xad, 0x3b, 0xc0, 0x2f, 0x8f, 0xee, 0x0b, 0xe3, 0x26,
2898 0x3f, 0x7c, 0x9e, 0x7e, 0xe5, 0xc4, 0xe7, 0xfc, 0xca, 0xa6, 0x9c, 0x2d,
2899 0xf6, 0xa2, 0x7f, 0x4c, 0x7e, 0x50, 0x8c, 0xee, 0x2a, 0x9b, 0x78, 0x3a,
2900 0x46, 0xa1, 0x78, 0xcf, 0x1f, 0xd4, 0xf1, 0x03, 0x60, 0x12, 0xd3, 0xf7,
2901 0x67, 0x5d, 0xce, 0xd7, 0x8d, 0xf9, 0x36, 0xcc, 0x7d, 0xd0, 0xff, 0xa7,
2902 0xb5, 0x7e, 0x2e, 0x2b, 0xd8, 0xc1, 0xe0, 0xef, 0x98, 0x8c, 0x15, 0xa1,
2903 0xe3, 0x15, 0xf3, 0x4c, 0x89, 0x15, 0xac, 0xc4, 0x2c, 0x64, 0xc7, 0x0c,
2904 0xe4, 0xcd, 0x29, 0x1d, 0x67, 0xed, 0xd5, 0xb2, 0x67, 0x8e, 0xe5, 0x9c,
2905 0xa4, 0x2b, 0x6e, 0x8f, 0x3e, 0xbf, 0xcd, 0x1b, 0x2f, 0x26, 0x82, 0x3b,
2906 0x07, 0x1f, 0xe7, 0x94, 0xb4, 0xc1, 0x1e, 0xca, 0xae, 0x4c, 0x81, 0x27,
2907 0x12, 0x38, 0xdb, 0x56, 0xcd, 0x0f, 0x0d, 0xe8, 0xef, 0x86, 0xf6, 0x29,
2908 0x06, 0xb1, 0x8b, 0x86, 0xc9, 0x76, 0xa7, 0xd0, 0xaf, 0x5d, 0x32, 0x57,
2909 0xdb, 0xb4, 0x5c, 0x7d, 0xb8, 0x2e, 0x0d, 0x1c, 0xf2, 0x04, 0xca, 0x11,
2910 0xd4, 0x25, 0xc3, 0xb2, 0x81, 0xf2, 0x34, 0xca, 0x2d, 0x78, 0xb2, 0xcd,
2911 0x61, 0xe0, 0x0a, 0x3c, 0x5f, 0xc3, 0x78, 0x23, 0x58, 0x73, 0xce, 0x94,
2912 0x8f, 0x4e, 0x50, 0x97, 0x38, 0x06, 0x73, 0x91, 0x67, 0x6d, 0x3c, 0x6b,
2913 0x45, 0x95, 0x5d, 0x60, 0x19, 0xcf, 0x72, 0xf0, 0xfd, 0x21, 0x99, 0x84,
2914 0x3e, 0x99, 0x6b, 0x81, 0x4c, 0xfa, 0x68, 0x5b, 0x26, 0xb1, 0xae, 0x5d,
2915 0xc6, 0xae, 0x92, 0xd7, 0x4d, 0xd0, 0x5b, 0xa7, 0x64, 0xaf, 0xc5, 0x34,
2916 0x1e, 0xad, 0x80, 0x16, 0xaf, 0x83, 0xae, 0x96, 0x41, 0x53, 0x99, 0xa2,
2917 0x35, 0x3a, 0xad, 0x92, 0xda, 0x2f, 0xf0, 0x38, 0xe8, 0xb5, 0xe3, 0x0a,
2918 0xb1, 0x28, 0x79, 0xd9, 0x01, 0xed, 0x89, 0xdf, 0x61, 0xdb, 0x93, 0x8e,
2919 0xb2, 0x41, 0x83, 0xa0, 0xcb, 0x62, 0xc0, 0xd3, 0xef, 0x29, 0x2d, 0x57,
2920 0x47, 0xef, 0x48, 0x2a, 0x7d, 0x47, 0x2c, 0xc8, 0x02, 0xcb, 0xfd, 0x50,
2921 0x5c, 0x8c, 0x79, 0x5c, 0x5e, 0xc7, 0x3c, 0x06, 0xf8, 0xfb, 0xc8, 0x90,
2922 0xe6, 0xef, 0x51, 0x89, 0xec, 0xe6, 0x71, 0xd0, 0x1b, 0x64, 0x50, 0xc0,
2923 0xd3, 0xe9, 0x90, 0x46, 0x9f, 0x06, 0xff, 0x5a, 0xb0, 0xca, 0x92, 0x32,
2924 0x0f, 0xfe, 0xbf, 0x8e, 0xef, 0xb7, 0xea, 0x9f, 0xaa, 0xb9, 0x05, 0x15,
2925 0xe6, 0xb2, 0x7c, 0x1b, 0x38, 0xf9, 0xf7, 0x38, 0xbb, 0x2e, 0x8d, 0xdd,
2926 0x07, 0x46, 0x18, 0x4b, 0xfb, 0xb7, 0xba, 0x6c, 0x1f, 0x95, 0xcd, 0xe1,
2927 0xe3, 0x28, 0xef, 0xc3, 0xd3, 0xc0, 0x39, 0x44, 0x75, 0x2c, 0x7c, 0xd9,
2928 0x1b, 0x36, 0x0a, 0x3a, 0xef, 0xe0, 0x98, 0xce, 0xcf, 0x37, 0xec, 0x03,
2929 0xf8, 0x4e, 0xbf, 0x0c, 0xf7, 0x06, 0xcc, 0xa4, 0x12, 0x3a, 0xc7, 0xb4,
2930 0x02, 0x2c, 0xb1, 0x82, 0xf1, 0xde, 0xa7, 0x5f, 0xaf, 0x06, 0x1e, 0x1e,
2931 0xfe, 0xa7, 0x9f, 0x8e, 0x31, 0x27, 0x7d, 0x33, 0x11, 0xe8, 0xbf, 0xcf,
2932 0xfc, 0x4d, 0x7b, 0x6e, 0xd4, 0xc0, 0xcb, 0x6d, 0x33, 0x86, 0xb6, 0xd0,
2933 0x65, 0xd0, 0x45, 0x65, 0x4d, 0xbf, 0x6c, 0x17, 0xf4, 0x2d, 0xd4, 0x52,
2934 0xe6, 0x07, 0x12, 0xf4, 0x9d, 0xb7, 0xa9, 0x77, 0xda, 0x21, 0x5f, 0x92,
2935 0x1a, 0x57, 0xbe, 0x6f, 0xe7, 0x21, 0x15, 0xac, 0xe4, 0x24, 0x68, 0xb4,
2936 0x4d, 0x2c, 0x67, 0x5c, 0x1e, 0xcc, 0x3b, 0xab, 0xfb, 0xb2, 0x6d, 0xb3,
2937 0x6f, 0x73, 0x5e, 0xae, 0x9f, 0x7b, 0xe1, 0x1e, 0xe8, 0xa7, 0x36, 0x35,
2938 0x8d, 0x36, 0x6a, 0xed, 0xfd, 0x01, 0x8d, 0x36, 0xf7, 0x11, 0xfb, 0x3f,
2939 0xfb, 0x20, 0x9d, 0x0c, 0x1b, 0x41, 0x0e, 0x06, 0x9e, 0x35, 0x9e, 0xe7,
2940 0xa7, 0xc0, 0xf7, 0x3b, 0xe9, 0xa7, 0xe9, 0x67, 0x0c, 0xe8, 0xe7, 0x91,
2941 0x6d, 0xfa, 0x21, 0xdd, 0x74, 0xca, 0xd8, 0x35, 0x5b, 0x26, 0x8a, 0xfa,
2942 0xbe, 0x81, 0x35, 0xe9, 0x3f, 0x3a, 0x0e, 0xba, 0x21, 0xad, 0x93, 0xb7,
2943 0x4c, 0x29, 0x83, 0x8e, 0xca, 0x90, 0x4f, 0x65, 0xd0, 0x14, 0x31, 0x50,
2944 0x19, 0xf2, 0xad, 0x5c, 0xb7, 0x9c, 0x2a, 0xf6, 0x4c, 0x9d, 0xbd, 0x02,
2945 0x3a, 0xba, 0x5e, 0xe7, 0xfd, 0xeb, 0x35, 0x9b, 0xd4, 0x83, 0xb7, 0xb6,
2946 0xef, 0xfe, 0xef, 0xb8, 0xfb, 0x43, 0x72, 0x03, 0x76, 0xcb, 0x9b, 0xa5,
2947 0x61, 0xc8, 0x24, 0x21, 0x5e, 0x04, 0x6d, 0x8c, 0xca, 0x6a, 0xe9, 0xa4,
2948 0xac, 0x41, 0x3f, 0xad, 0x2f, 0x0d, 0x00, 0x4f, 0x43, 0x8e, 0xbe, 0x72,
2949 0x44, 0xde, 0x58, 0x52, 0x32, 0x63, 0x43, 0xbf, 0x2c, 0xd3, 0x07, 0x0f,
2950 0x7a, 0x2e, 0x77, 0xea, 0x98, 0xfd, 0x58, 0x35, 0xf0, 0xc5, 0x8f, 0x57,
2951 0xbb, 0x64, 0xa2, 0x6a, 0xca, 0x63, 0xd5, 0x1e, 0x79, 0xa2, 0x1a, 0x93,
2952 0xd3, 0xb5, 0x84, 0x7c, 0xa3, 0x7a, 0x50, 0x4e, 0x55, 0x0f, 0xc9, 0x93,
2953 0xb5, 0xa4, 0x7c, 0x13, 0x76, 0x61, 0xae, 0xe6, 0xc8, 0x64, 0x6d, 0x58,
2954 0x1e, 0xaf, 0xd1, 0xc7, 0x8e, 0xf9, 0xf0, 0xcb, 0x6e, 0xfb, 0x2e, 0xb8,
2955 0xae, 0x0e, 0xac, 0xcb, 0x51, 0xe3, 0x3a, 0x66, 0x29, 0xb9, 0xc0, 0xff,
2956 0x21, 0x72, 0x0e, 0x7d, 0x2f, 0xbe, 0xa2, 0xa4, 0xa2, 0xe7, 0x6f, 0xfe,
2957 0xdf, 0x48, 0x54, 0xdb, 0x46, 0xe7, 0xca, 0x07, 0xd1, 0xc6, 0xa6, 0x4d,
2958 0x12, 0xfa, 0x41, 0x9a, 0xfe, 0xff, 0xa6, 0xed, 0x65, 0x68, 0x1f, 0xf6,
2959 0x2d, 0xda, 0x5e, 0xfa, 0xec, 0x29, 0x3f, 0x68, 0xe7, 0xd0, 0xd6, 0xda,
2960 0x19, 0xe7, 0x68, 0xce, 0x7b, 0x31, 0xf7, 0xf0, 0xff, 0xa7, 0x04, 0xf1,
2961 0xaa, 0xb3, 0xb5, 0x83, 0xfc, 0x3f, 0x15, 0xac, 0xe5, 0x8b, 0xf3, 0xc5,
2962 0x27, 0x4a, 0x63, 0xea, 0xb1, 0x12, 0x11, 0x8d, 0x2f, 0x17, 0xb7, 0x73,
2963 0xf2, 0xbe, 0x2e, 0xcb, 0x6e, 0x54, 0xaf, 0x21, 0xf0, 0xdb, 0xa7, 0x75,
2964 0x7e, 0xde, 0xd8, 0x10, 0xe9, 0x8f, 0x71, 0xb8, 0xae, 0x30, 0xb6, 0x00,
2965 0x6c, 0xeb, 0x9a, 0x72, 0xa9, 0x1a, 0xf8, 0xaf, 0xe6, 0x34, 0xbd, 0xbc,
2966 0x05, 0x9a, 0x63, 0xfc, 0x21, 0x78, 0xe6, 0xcb, 0x41, 0xdf, 0xec, 0x90,
2967 0x43, 0x7b, 0x1c, 0xfb, 0x35, 0x7a, 0x38, 0x17, 0xff, 0x4f, 0x07, 0xe5,
2968 0x70, 0xbd, 0xcc, 0x2f, 0xb6, 0x35, 0x2d, 0x06, 0x31, 0x5e, 0x47, 0x9e,
2969 0xc3, 0x5d, 0x54, 0x4c, 0xae, 0xbf, 0x43, 0x2a, 0x0e, 0x6d, 0x5b, 0xca,
2970 0xef, 0x21, 0x29, 0x63, 0x9e, 0x8a, 0xd3, 0xf4, 0x8d, 0x05, 0x72, 0xb6,
2971 0x62, 0x3e, 0x98, 0x77, 0xba, 0xbc, 0x1f, 0xef, 0xa8, 0x73, 0x80, 0x99,
2972 0xa6, 0xf8, 0x7e, 0x11, 0x65, 0xfa, 0x46, 0xe6, 0xf0, 0x4c, 0x84, 0x75,
2973 0xaf, 0xf5, 0x6b, 0xac, 0x7e, 0xf2, 0x41, 0xbf, 0x99, 0xb2, 0x95, 0xcf,
2974 0x44, 0xb6, 0x94, 0xf1, 0x8b, 0xf5, 0x7e, 0xca, 0xdc, 0xfd, 0x36, 0x7f,
2975 0x51, 0xf9, 0x8b, 0xa9, 0x7d, 0x0a, 0xe1, 0xb7, 0x3d, 0xf2, 0x94, 0xc9,
2976 0xdc, 0xf5, 0xb4, 0x1a, 0x2b, 0xfd, 0x34, 0xcc, 0xd3, 0xdd, 0x52, 0xfb,
2977 0x2b, 0x6f, 0xf7, 0x07, 0x79, 0xee, 0x1c, 0x7b, 0x67, 0x6e, 0xfb, 0x4e,
2978 0x3a, 0x61, 0x8e, 0x7b, 0x3b, 0x70, 0xab, 0x56, 0x62, 0xe0, 0x41, 0xc8,
2979 0x3b, 0xbb, 0x45, 0xf3, 0x63, 0xa1, 0xf6, 0x2f, 0x7f, 0x43, 0xf3, 0x73,
2980 0xd3, 0xc7, 0xf0, 0xdb, 0x7e, 0xda, 0xb6, 0x94, 0x1b, 0x97, 0x02, 0xbf,
2981 0x91, 0xb6, 0xa1, 0x21, 0x2b, 0x50, 0x47, 0x5e, 0x05, 0x9f, 0x6c, 0xb7,
2982 0xe5, 0xdf, 0x7f, 0x01, 0x99, 0xe7, 0xd3, 0x46, 0x40, 0x67, 0x00, 0x00,
2983 0x00 };
2984static u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 };
2985static u32 bnx2_RXP_b09FwRodata[(0x278/4) + 1] = {
2986 0x08003fa4, 0x08003ea4, 0x08003f48, 0x08003f60, 0x08003f78, 0x08003f98,
2987 0x08003fa4, 0x08003fa4, 0x08003eac, 0x00000000, 0x080049d4, 0x08004a0c,
2988 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004a44, 0x08004c08,
2989 0x08004b50, 0x08004b88, 0x08004c08, 0x08004ad8, 0x08004c08, 0x08004c08,
2990 0x08004b88, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2991 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004bc8,
2992 0x08004c08, 0x08004bc8, 0x08004b50, 0x08004c08, 0x08004c08, 0x08004bc8,
2993 0x08004bc8, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2994 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2995 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2996 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2997 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2998 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
2999 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3000 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3001 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3002 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3003 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3004 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3005 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3006 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3007 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3008 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08,
3009 0x08004ab4, 0x00000000, 0x0800602c, 0x08006044, 0x08006044, 0x08006044,
3010 0x0800602c, 0x08006044, 0x08006044, 0x08006044, 0x0800602c, 0x08006044,
3011 0x08006044, 0x08006044, 0x0800602c, 0x08006044, 0x08006044, 0x08006044,
3012 0x08006038, 0x00000000, 0x00000000 };
3013static u32 bnx2_RXP_b09FwBss[(0x13dc/4) + 1] = { 0x0 };
3014static u32 bnx2_RXP_b09FwSbss[(0x2c/4) + 1] = { 0x0 };
3015
3016static struct fw_info bnx2_rxp_fw_09 = {
3017 .ver_major = 0x1,
3018 .ver_minor = 0x0,
3019 .ver_fix = 0x0,
3020
3021 .start_addr = 0x08003184,
3022
3023 .text_addr = 0x08000000,
3024 .text_len = 0x673c,
3025 .text_index = 0x0,
3026 .gz_text = bnx2_RXP_b09FwText,
3027 .gz_text_len = sizeof(bnx2_RXP_b09FwText),
3028
3029 .data_addr = 0x080069e0,
3030 .data_len = 0x0,
3031 .data_index = 0x0,
3032 .data = bnx2_RXP_b09FwData,
3033
3034 .sbss_addr = 0x080069e0,
3035 .sbss_len = 0x2c,
3036 .sbss_index = 0x0,
3037 .sbss = bnx2_RXP_b09FwSbss,
3038
3039 .bss_addr = 0x08006a10,
3040 .bss_len = 0x13dc,
3041 .bss_index = 0x0,
3042 .bss = bnx2_RXP_b09FwBss,
3043
3044 .rodata_addr = 0x08006740,
3045 .rodata_len = 0x278,
3046 .rodata_index = 0x0,
3047 .rodata = bnx2_RXP_b09FwRodata,
3048};
3049
3050static u8 bnx2_TPAT_b09FwText[] = {
3051 0x1f, 0x8b, 0x08, 0x08, 0xdb, 0xfd, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
3052 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x58, 0x5d, 0x6c,
3053 0x1c, 0x57, 0x15, 0x3e, 0xf3, 0xbb, 0x13, 0x77, 0xed, 0xbd, 0x49, 0x97,
3054 0x6a, 0x13, 0xb9, 0x74, 0xc6, 0x1e, 0x3b, 0x8b, 0x1c, 0x35, 0x93, 0xb0,
3055 0x24, 0x16, 0x5a, 0xd1, 0xc9, 0xcc, 0xae, 0x6b, 0xe5, 0x29, 0x86, 0xbc,
3056 0xf1, 0xb2, 0xac, 0xed, 0x46, 0x54, 0x48, 0x4d, 0x51, 0x84, 0x22, 0x81,
3057 0x94, 0x65, 0x76, 0x53, 0x40, 0x5a, 0x65, 0xc1, 0xa0, 0x04, 0x21, 0x84,
3058 0x22, 0x9b, 0x66, 0x91, 0x58, 0x3c, 0x4d, 0xe9, 0x6b, 0x94, 0xbc, 0x90,
3059 0x96, 0x17, 0x9e, 0x4b, 0x9e, 0xac, 0x02, 0x12, 0x0f, 0xa8, 0x8a, 0x78,
3060 0x40, 0x15, 0x0d, 0x1e, 0xbe, 0x33, 0x3f, 0x9b, 0x5d, 0xd7, 0x29, 0x79,
3061 0xa8, 0x84, 0xa5, 0xf1, 0xcc, 0xfd, 0x39, 0xf7, 0xe7, 0x7c, 0xdf, 0x77,
3062 0xee, 0xb9, 0x5b, 0x92, 0x69, 0x82, 0xd2, 0xbf, 0x49, 0x3c, 0x97, 0xbe,
3063 0x71, 0xf1, 0xd2, 0xe2, 0x8b, 0x27, 0x4d, 0x3a, 0x71, 0xe2, 0x45, 0xe9,
3064 0x19, 0x43, 0xa6, 0xcf, 0xe0, 0x4f, 0x21, 0x12, 0xd9, 0xf8, 0xfc, 0x90,
3065 0x21, 0x57, 0x6f, 0x4e, 0x7b, 0x36, 0x19, 0x4a, 0xd5, 0x79, 0x61, 0xd5,
3066 0x26, 0x72, 0x07, 0x0b, 0xa6, 0x4f, 0xff, 0x89, 0x5a, 0x45, 0x95, 0xb8,
3067 0xfe, 0xf9, 0xea, 0xa3, 0xe3, 0x77, 0x4e, 0x5b, 0x0f, 0x6f, 0x2a, 0x64,
3068 0x88, 0x6a, 0xc3, 0x10, 0xf3, 0x64, 0x4c, 0xc3, 0xe6, 0x97, 0x47, 0x57,
3069 0x34, 0x9a, 0xca, 0xc6, 0x12, 0x14, 0xf4, 0x0c, 0xaa, 0x77, 0x31, 0x8e,
3070 0x7d, 0x59, 0xf2, 0x43, 0x55, 0xf2, 0x6f, 0x18, 0x24, 0x57, 0x5d, 0xc9,
3071 0x0b, 0x6d, 0xb4, 0x49, 0xe4, 0x39, 0x39, 0x72, 0x45, 0x14, 0x7d, 0xd3,
3072 0x91, 0x49, 0xb6, 0x77, 0xa3, 0xd9, 0xb9, 0x25, 0xc9, 0xeb, 0x2f, 0x4b,
3073 0x7e, 0xdf, 0xe3, 0x7d, 0x63, 0x1d, 0x4b, 0x92, 0xdb, 0xe7, 0x77, 0xd5,
3074 0xf0, 0xbb, 0x53, 0xd4, 0x28, 0x52, 0x41, 0xb6, 0xd9, 0xd6, 0x24, 0xdf,
3075 0x59, 0x28, 0x29, 0x34, 0x8b, 0xe7, 0x00, 0xad, 0x3b, 0x94, 0xf7, 0x1c,
3076 0x52, 0x15, 0x5b, 0x26, 0xbf, 0x28, 0xd1, 0xaf, 0x2b, 0x1a, 0x9e, 0xb3,
3077 0x52, 0xad, 0xbf, 0x96, 0x8e, 0x53, 0xa4, 0x36, 0xd6, 0xd2, 0x2c, 0xf2,
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3223 0x55, 0x90, 0xc6, 0x8f, 0x00, 0xf1, 0xa3, 0xc6, 0xf9, 0x4f, 0x1c, 0x0b,
3224 0x12, 0xfd, 0xac, 0x41, 0x3f, 0x35, 0x85, 0xf3, 0x23, 0xd6, 0x0e, 0xdb,
3225 0xb1, 0x7e, 0xd8, 0xae, 0x90, 0xda, 0x8d, 0xc7, 0x91, 0x76, 0xcf, 0x32,
3226 0xb3, 0x38, 0xd2, 0x86, 0x76, 0x3a, 0xa9, 0x8e, 0xda, 0xa9, 0x8e, 0xd0,
3227 0xa7, 0xa5, 0x54, 0xf8, 0x4c, 0xb0, 0x4c, 0x1f, 0xf1, 0xa3, 0x13, 0x8f,
3228 0xd9, 0xa2, 0xe4, 0x2e, 0xc3, 0xda, 0xe6, 0xb8, 0x3b, 0x12, 0x6f, 0xd3,
3229 0x7b, 0x6e, 0x23, 0xbe, 0xe7, 0x7e, 0x45, 0x1f, 0x8f, 0xb7, 0x38, 0x6b,
3230 0xe2, 0x7b, 0xee, 0x29, 0x9d, 0xef, 0xb9, 0x01, 0x7d, 0x49, 0x1f, 0xbd,
3231 0xe7, 0x06, 0x63, 0xf7, 0xdc, 0xcc, 0x96, 0xeb, 0xf7, 0x8b, 0xbb, 0x99,
3232 0x4f, 0x38, 0xf6, 0x32, 0x9f, 0xf6, 0xcb, 0x15, 0xb3, 0x3e, 0x1c, 0x93,
3233 0x58, 0xef, 0x1c, 0xcb, 0x92, 0xdc, 0xec, 0x6e, 0x98, 0xe9, 0xe2, 0x55,
3234 0xcc, 0x83, 0x72, 0x6f, 0x3f, 0x5d, 0x18, 0xa9, 0x2e, 0x26, 0x13, 0x9b,
3235 0xde, 0xa8, 0x36, 0x5e, 0xd5, 0xc7, 0xb5, 0x91, 0x8d, 0x93, 0x69, 0x23,
3236 0x19, 0x73, 0x47, 0x29, 0xe1, 0x0c, 0x2c, 0x23, 0x1e, 0x09, 0xbe, 0xa3,
3237 0x21, 0x5e, 0x54, 0xf3, 0xb8, 0xa7, 0x14, 0x78, 0xec, 0x76, 0xf8, 0x2c,
3238 0x35, 0x8a, 0x8c, 0x0b, 0xaf, 0xff, 0x61, 0x7c, 0x7f, 0xc0, 0xba, 0x0b,
3239 0x01, 0xff, 0xfe, 0xf1, 0x09, 0x3e, 0xbe, 0x06, 0x3e, 0x66, 0xfb, 0x19,
3240 0xad, 0xbf, 0x34, 0x52, 0x5f, 0x4e, 0x31, 0x4f, 0x7c, 0x7e, 0x2f, 0xd5,
3241 0xc8, 0x26, 0x72, 0xb7, 0xfb, 0xc8, 0x8b, 0xde, 0x44, 0xfc, 0x0e, 0x06,
3242 0x1f, 0x47, 0xf7, 0x8a, 0x2a, 0x75, 0x86, 0x36, 0xbf, 0xc0, 0xba, 0x2d,
3243 0x71, 0x13, 0x5f, 0x6f, 0x0c, 0xb2, 0xb1, 0xb9, 0x9d, 0xeb, 0xfe, 0x8d,
3244 0xf3, 0x19, 0x79, 0xdf, 0xb0, 0xef, 0xfb, 0x11, 0xe7, 0xbb, 0x77, 0x81,
3245 0xc5, 0x3b, 0xe1, 0x34, 0xfd, 0x1e, 0x1c, 0x7b, 0x3b, 0xce, 0x79, 0x93,
3246 0x5c, 0x17, 0xfe, 0xc3, 0x99, 0xc7, 0x67, 0xbd, 0xf7, 0x39, 0x99, 0x2e,
3247 0xd3, 0x57, 0x1d, 0xae, 0x93, 0xa9, 0x7e, 0x2a, 0x8a, 0x2e, 0xe2, 0xdc,
3248 0x5f, 0x19, 0x3b, 0xf7, 0x71, 0x07, 0x3c, 0xc9, 0xf9, 0x7f, 0x96, 0xf3,
3249 0xef, 0x46, 0x33, 0xf3, 0xd6, 0x4d, 0x97, 0x5c, 0xa9, 0xde, 0xe7, 0x7c,
3250 0x6c, 0x98, 0x8b, 0x11, 0x1d, 0x7a, 0x14, 0xc9, 0xf3, 0x7c, 0x36, 0xbd,
3251 0x9b, 0xfa, 0x1c, 0x6d, 0x37, 0x1e, 0xe1, 0x1e, 0x53, 0x8b, 0x7f, 0x17,
3252 0x72, 0xfb, 0x3c, 0x0f, 0x97, 0xf1, 0x0e, 0x39, 0x47, 0x78, 0xd2, 0x6f,
3253 0x35, 0x2a, 0xf0, 0xb5, 0xcc, 0x75, 0x85, 0xe2, 0x7b, 0x21, 0xee, 0x6e,
3254 0x3f, 0x6f, 0x53, 0x12, 0x3b, 0x6a, 0xce, 0x39, 0xac, 0x05, 0x98, 0x88,
3255 0x06, 0x30, 0x9e, 0x47, 0xac, 0xb2, 0xcc, 0x93, 0x72, 0xf2, 0x5b, 0xd5,
3256 0x1a, 0xc6, 0x56, 0x4e, 0x72, 0x2e, 0xf9, 0x51, 0xb4, 0x36, 0x88, 0xcf,
3257 0x44, 0x87, 0xb9, 0xe6, 0x87, 0x07, 0x65, 0x7e, 0xbb, 0x21, 0x7f, 0xeb,
3258 0x98, 0xc7, 0x7c, 0x02, 0x0f, 0x8b, 0xa2, 0x76, 0xc3, 0x14, 0xf5, 0x9e,
3259 0x29, 0x96, 0x7a, 0x32, 0x54, 0x52, 0xc8, 0xd1, 0x14, 0xe7, 0x08, 0x3a,
3260 0xd1, 0x73, 0x58, 0xcb, 0x2d, 0x53, 0xf8, 0xc8, 0xa3, 0xbe, 0xad, 0x58,
3261 0x62, 0x85, 0x76, 0xb1, 0xc7, 0x47, 0x51, 0x72, 0xa7, 0x35, 0x45, 0x6d,
3262 0x38, 0xf7, 0x23, 0xcc, 0xcd, 0x6b, 0x62, 0x2d, 0xf3, 0x79, 0xb6, 0x2c,
3263 0x9d, 0x83, 0x8f, 0xce, 0xf7, 0x77, 0x11, 0x43, 0xf9, 0x3c, 0xcb, 0x23,
3264 0xe6, 0x59, 0x26, 0x5f, 0xf6, 0xef, 0x62, 0xff, 0xef, 0xf4, 0x80, 0x0f,
3265 0x72, 0xc7, 0xb7, 0x87, 0x79, 0x1a, 0x63, 0x58, 0x06, 0x17, 0xd9, 0x3e,
3266 0x8a, 0x82, 0xc5, 0x38, 0x47, 0xc1, 0x5a, 0xe6, 0xca, 0xb7, 0x90, 0xa7,
3267 0xd7, 0x69, 0xa1, 0x5c, 0x8f, 0xdf, 0x11, 0x72, 0x12, 0xfe, 0x5d, 0xc0,
3268 0x12, 0x4d, 0x7c, 0xd7, 0xd2, 0xef, 0x80, 0x73, 0xf8, 0x45, 0x1e, 0x83,
3269 0x73, 0x79, 0xd6, 0xe1, 0x7f, 0x01, 0x17, 0xc6, 0xf1, 0xb2, 0x84, 0x14,
3270 0x00, 0x00, 0x00 };
3271static u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 };
3272static u32 bnx2_TPAT_b09FwRodata[(0x0/4) + 1] = { 0x0 };
3273static u32 bnx2_TPAT_b09FwBss[(0x250/4) + 1] = { 0x0 };
3274static u32 bnx2_TPAT_b09FwSbss[(0x34/4) + 1] = { 0x0 };
3275
3276static struct fw_info bnx2_tpat_fw_09 = {
3277 .ver_major = 0x1,
3278 .ver_minor = 0x0,
3279 .ver_fix = 0x0,
3280
3281 .start_addr = 0x08000860,
3282
3283 .text_addr = 0x08000800,
3284 .text_len = 0x1480,
3285 .text_index = 0x0,
3286 .gz_text = bnx2_TPAT_b09FwText,
3287 .gz_text_len = sizeof(bnx2_TPAT_b09FwText),
3288
3289 .data_addr = 0x08001ca0,
3290 .data_len = 0x0,
3291 .data_index = 0x0,
3292 .data = bnx2_TPAT_b09FwData,
3293
3294 .sbss_addr = 0x08001ca0,
3295 .sbss_len = 0x34,
3296 .sbss_index = 0x0,
3297 .sbss = bnx2_TPAT_b09FwSbss,
3298
3299 .bss_addr = 0x08001ce0,
3300 .bss_len = 0x250,
3301 .bss_index = 0x0,
3302 .bss = bnx2_TPAT_b09FwBss,
3303
3304 .rodata_addr = 0x00000000,
3305 .rodata_len = 0x0,
3306 .rodata_index = 0x0,
3307 .rodata = bnx2_TPAT_b09FwRodata,
3308};
3309
3310static u8 bnx2_TXP_b09FwText[] = {
3311 0x1f, 0x8b, 0x08, 0x08, 0x51, 0xfe, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65,
3312 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xcd, 0x7b, 0x7f, 0x70,
3313 0x1b, 0xe7, 0x99, 0xde, 0xbb, 0x0b, 0x80, 0x04, 0x29, 0x8a, 0x5a, 0x31,
3314 0x30, 0x83, 0x38, 0xb4, 0x8d, 0x15, 0x17, 0x34, 0x6d, 0xf2, 0x1c, 0x58,
3315 0xe5, 0xf9, 0xd8, 0x06, 0xb5, 0xd7, 0xc0, 0x92, 0xa2, 0x63, 0x26, 0x47,
3316 0xbb, 0xcc, 0x9d, 0x92, 0x51, 0x7d, 0x28, 0x48, 0x29, 0x6e, 0xe3, 0xb4,
3317 0xaa, 0xe3, 0x3f, 0x34, 0x4d, 0x5b, 0xc3, 0x00, 0x25, 0xcb, 0x2e, 0x44,
3318 0xd0, 0x16, 0x63, 0xa5, 0x33, 0x37, 0x53, 0x18, 0x80, 0x28, 0xe7, 0xba,
3319 0x24, 0xdc, 0xe4, 0x2e, 0xe9, 0x1f, 0xc9, 0x99, 0xa5, 0x6c, 0xc5, 0x6d,
3320 0xae, 0x33, 0xbe, 0x3f, 0xda, 0xa6, 0x37, 0xd7, 0x19, 0x8d, 0xfc, 0x23,
3321 0xce, 0x8f, 0xb9, 0xb8, 0x69, 0x7a, 0x56, 0x5b, 0xd9, 0xe8, 0xf3, 0x7c,
3322 0xbb, 0x4b, 0x82, 0x32, 0x15, 0x5b, 0xd7, 0x76, 0xa6, 0x9c, 0xc1, 0x10,
3323 0xfb, 0xed, 0xb7, 0xdf, 0xf7, 0xfe, 0x7e, 0xdf, 0xe7, 0xfd, 0x16, 0x71,
3324 0x91, 0x6e, 0xf1, 0xff, 0x76, 0xe3, 0x93, 0x38, 0x7a, 0xec, 0xb1, 0x3b,
3325 0xc6, 0xef, 0xd8, 0x2f, 0x72, 0xe7, 0x9d, 0xb2, 0x2b, 0xaa, 0xf3, 0xe6,
3326 0xdb, 0x21, 0x91, 0xdc, 0x4f, 0xe5, 0xaf, 0xfc, 0x87, 0xc7, 0x8d, 0x60,
3327 0x7d, 0x7e, 0x24, 0xaa, 0xa7, 0x5f, 0xcc, 0x64, 0x2c, 0x89, 0x86, 0xd2,
3328 0x33, 0x9f, 0x9d, 0xb3, 0x44, 0x6c, 0x77, 0x24, 0x91, 0x95, 0xf7, 0x5a,
3329 0x85, 0x58, 0x58, 0x38, 0x7e, 0x53, 0xfa, 0xca, 0xe3, 0xdf, 0xff, 0x2d,
3330 0xf3, 0x9d, 0x6a, 0x48, 0xa2, 0x46, 0x3a, 0x27, 0xc6, 0x90, 0x44, 0x07,
3331 0xf0, 0xcc, 0xef, 0xdf, 0x3a, 0xa5, 0x4b, 0x6f, 0xb0, 0x56, 0x5c, 0x16,
3332 0x2a, 0x6f, 0xb7, 0xbe, 0x7f, 0x6b, 0x4c, 0xfe, 0x55, 0xd3, 0x90, 0x17,
3333 0x9b, 0x61, 0x6d, 0xb2, 0xd2, 0x23, 0xa5, 0x8a, 0x2b, 0xc7, 0xcb, 0x05,
3334 0xc9, 0x36, 0x5f, 0x90, 0xe2, 0xb2, 0xd1, 0x9b, 0x39, 0xf7, 0x07, 0x52,
3335 0x5a, 0xee, 0xeb, 0xcd, 0x9e, 0x73, 0xa5, 0x58, 0x8e, 0xf7, 0x66, 0x9a,
3336 0x46, 0x6f, 0xf6, 0x4c, 0x0c, 0xd7, 0x7d, 0xbd, 0x99, 0x33, 0x66, 0x41,
3337 0xa4, 0x1f, 0x73, 0xe2, 0xbd, 0xd9, 0x8a, 0x99, 0x13, 0x19, 0x4c, 0xbd,
3338 0x22, 0x03, 0xbd, 0xd9, 0x66, 0x4d, 0x5b, 0x37, 0x34, 0x29, 0xfe, 0x86,
3339 0x18, 0xbd, 0xe9, 0xcb, 0xad, 0x4f, 0x58, 0x86, 0xec, 0xb5, 0x64, 0xcf,
3340 0x1e, 0x4b, 0x9e, 0x88, 0xa7, 0xa3, 0x92, 0x3f, 0xdd, 0x25, 0xb6, 0xe2,
3341 0xc9, 0x90, 0xfc, 0x99, 0x11, 0x63, 0x43, 0x22, 0x62, 0xc7, 0x82, 0xeb,
3342 0x56, 0x2b, 0x93, 0xfa, 0x02, 0xe5, 0x8a, 0xbd, 0xa4, 0x77, 0xb2, 0x29,
3343 0x92, 0xa9, 0x44, 0x25, 0x93, 0x7a, 0xaf, 0xe5, 0x3d, 0x13, 0xc5, 0xbe,
3344 0xe1, 0xde, 0x89, 0x4a, 0xab, 0xe5, 0xa4, 0xb0, 0x47, 0x2a, 0x78, 0x36,
3345 0x22, 0xd5, 0x98, 0x5d, 0x2d, 0xa5, 0x4c, 0xdd, 0xd3, 0x09, 0x79, 0xe4,
3346 0xb5, 0x2d, 0xba, 0xf5, 0xdb, 0x92, 0x8f, 0x49, 0xb5, 0x98, 0xba, 0x4b,
3347 0x9e, 0x4e, 0x19, 0x72, 0x12, 0xeb, 0x3d, 0x95, 0x82, 0x1c, 0xad, 0x63,
3348 0x5a, 0xa6, 0x69, 0xc6, 0x45, 0x7b, 0x5a, 0x32, 0x67, 0x06, 0x8d, 0xac,
3349 0x60, 0x6f, 0xab, 0x75, 0x4b, 0x26, 0x85, 0xfd, 0x46, 0xff, 0x67, 0xcb,
3350 0x8e, 0x99, 0xb9, 0xaa, 0x0c, 0x48, 0xb1, 0x32, 0x98, 0xfa, 0x13, 0xd1,
3351 0xa4, 0xd3, 0xa2, 0x7c, 0x5a, 0x72, 0x3f, 0xf6, 0xcd, 0x58, 0x18, 0x6f,
3352 0x8a, 0xad, 0x27, 0x23, 0xf2, 0x0f, 0x0c, 0x33, 0x91, 0x09, 0xf5, 0x4b,
3353 0xf1, 0x74, 0x27, 0xe8, 0xb4, 0xfb, 0x74, 0xcc, 0x3d, 0x30, 0x26, 0xb1,
3354 0x5d, 0x22, 0x5a, 0x28, 0x9d, 0xc4, 0xba, 0x22, 0x45, 0x77, 0x00, 0xcf,
3355 0x26, 0xc7, 0x7f, 0x2a, 0x7b, 0x24, 0xb1, 0x37, 0x2c, 0x25, 0xb7, 0x1b,
3356 0x72, 0x34, 0xa0, 0x83, 0xe4, 0xf8, 0x5f, 0x40, 0x29, 0xba, 0x95, 0x8c,
3357 0x1f, 0x93, 0x9c, 0x96, 0x6d, 0x76, 0x48, 0x29, 0x19, 0x95, 0x05, 0xd0,
3358 0xb1, 0x90, 0xfa, 0xa2, 0x96, 0x39, 0x77, 0x50, 0xcb, 0x9e, 0xc3, 0xbc,
3359 0x66, 0xdd, 0xb7, 0x35, 0x03, 0xeb, 0xe8, 0x52, 0x4c, 0x1e, 0xc4, 0xbd,
3360 0xa8, 0xcc, 0x61, 0xde, 0x1c, 0x78, 0x2a, 0x35, 0xf7, 0xc8, 0xfa, 0x6c,
3361 0xac, 0x37, 0x03, 0x1d, 0x16, 0x71, 0xff, 0xb7, 0x67, 0x34, 0x31, 0x2c,
3362 0x5b, 0x7e, 0x3c, 0x06, 0x1d, 0x9e, 0x81, 0xfe, 0xce, 0xc4, 0xe5, 0x78,
3363 0x45, 0x62, 0xba, 0x24, 0xe3, 0x79, 0x79, 0x41, 0xea, 0x2e, 0xf5, 0x0f,
3364 0x7d, 0x42, 0xdf, 0x45, 0x97, 0xcf, 0x41, 0x6f, 0x15, 0x07, 0xf2, 0x98,
3365 0x02, 0x0d, 0x0f, 0x6a, 0xf7, 0xd7, 0x67, 0xb5, 0x03, 0xcd, 0x1f, 0x6b,
3366 0xd2, 0x7d, 0x4c, 0xfb, 0x5c, 0xf3, 0x88, 0xe6, 0xcb, 0x1e, 0xba, 0x8b,
3367 0x8a, 0x3d, 0x13, 0x95, 0x95, 0xa6, 0xa7, 0xbb, 0x1a, 0xec, 0xd3, 0x36,
3368 0x6c, 0xe8, 0xe1, 0x6f, 0x6f, 0xce, 0x59, 0x69, 0xc6, 0x64, 0x01, 0xb4,
3369 0x1d, 0x6f, 0x72, 0xfe, 0xef, 0x41, 0x3f, 0x51, 0x71, 0x6f, 0xed, 0x91,
3370 0x1c, 0xc6, 0x8b, 0x67, 0xc4, 0xce, 0xa4, 0x74, 0x3c, 0xd3, 0x2b, 0x21,
3371 0xab, 0x1f, 0x9f, 0x6e, 0x99, 0xab, 0x77, 0xda, 0x21, 0x2b, 0x26, 0x73,
3372 0x4d, 0xca, 0x10, 0xff, 0x2b, 0x81, 0x1c, 0x49, 0x2b, 0xc7, 0xf9, 0x1c,
3373 0xc7, 0x0d, 0x8c, 0xb7, 0x8f, 0xd1, 0x2e, 0x7a, 0x41, 0x8f, 0x39, 0x2c,
3374 0x18, 0xcb, 0x57, 0x92, 0xc6, 0xe7, 0xf8, 0xbf, 0x49, 0xd9, 0x06, 0x32,
3375 0x0d, 0x63, 0xae, 0x2e, 0xf9, 0x3a, 0xf6, 0x39, 0x7d, 0xa5, 0x15, 0x19,
3376 0xc3, 0xb5, 0xf5, 0x4b, 0xc8, 0x92, 0xfb, 0x86, 0x41, 0x93, 0x2e, 0xb9,
3377 0x3a, 0xd7, 0xe2, 0x7d, 0x81, 0xee, 0x8b, 0x7b, 0x75, 0x19, 0x86, 0x7e,
3378 0x4d, 0xec, 0xd3, 0x85, 0x39, 0x3d, 0x90, 0x1f, 0x78, 0x3d, 0x87, 0xef,
3379 0xe0, 0x5d, 0xb7, 0x74, 0x3c, 0xdf, 0x29, 0x73, 0x29, 0xda, 0x0b, 0xe9,
3380 0xdc, 0x85, 0xb5, 0xbb, 0x64, 0xfe, 0x34, 0xe5, 0x01, 0xbb, 0xaa, 0xc4,
3381 0xa4, 0x74, 0xc6, 0x34, 0x1c, 0x31, 0x21, 0x1b, 0x1b, 0xf3, 0x3a, 0x25,
3382 0x67, 0xb4, 0x5a, 0x13, 0xa9, 0x11, 0xe3, 0x9b, 0xca, 0xce, 0x47, 0x8c,
3383 0xa4, 0x26, 0x85, 0x8e, 0xf4, 0x10, 0x64, 0x6b, 0x1e, 0x14, 0xe1, 0xf5,
3384 0x0f, 0xc4, 0x9e, 0xa5, 0xff, 0xc4, 0xb8, 0x17, 0xfc, 0xa9, 0x1f, 0xf4,
3385 0xd3, 0xe7, 0x06, 0xa0, 0x97, 0xb8, 0xf2, 0x83, 0x89, 0x1d, 0xfd, 0xc0,
3386 0x9c, 0xaa, 0x82, 0xdf, 0xe2, 0xb9, 0x30, 0xfd, 0x2f, 0x05, 0x73, 0x93,
3387 0x5d, 0x56, 0x14, 0xb6, 0x40, 0x5a, 0xc6, 0xb1, 0x7e, 0xab, 0xf5, 0xd9,
3388 0x94, 0x47, 0x53, 0xf1, 0x8c, 0x8d, 0x67, 0xc3, 0x90, 0xbb, 0xf9, 0x70,
3389 0x42, 0xed, 0x3f, 0xee, 0xef, 0x6f, 0xc8, 0x1c, 0xe8, 0x2e, 0x56, 0x42,
3390 0x92, 0x35, 0xb8, 0xc6, 0x9f, 0x71, 0x3c, 0xe7, 0xad, 0x05, 0xbb, 0x3d,
3391 0x35, 0x68, 0xdc, 0x07, 0x5f, 0xa2, 0x8f, 0x15, 0x57, 0x29, 0x63, 0xac,
3392 0x33, 0x46, 0x19, 0x1b, 0x8a, 0xc6, 0xcc, 0x19, 0xda, 0x91, 0x0c, 0x84,
3393 0x84, 0x76, 0x8e, 0x98, 0x01, 0xbb, 0x2a, 0xf9, 0x76, 0x95, 0x77, 0xa9,
3394 0xff, 0xbb, 0x7d, 0xff, 0xd4, 0x65, 0x28, 0x49, 0x7b, 0x7f, 0x5a, 0xb2,
3395 0xf0, 0xf1, 0x39, 0xec, 0x54, 0x07, 0x4f, 0xb5, 0xca, 0x20, 0x64, 0x15,
3396 0xf8, 0x1d, 0xf4, 0x3b, 0xfa, 0x6e, 0x2b, 0x88, 0x05, 0xc5, 0x0a, 0x7d,
3397 0xa6, 0x68, 0xe8, 0x52, 0xc0, 0x07, 0x76, 0x63, 0x99, 0xc3, 0x99, 0x90,
3398 0x39, 0x93, 0x03, 0x6d, 0xb0, 0x7b, 0xc9, 0xdc, 0x49, 0x7b, 0xc6, 0x9c,
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3400 0x29, 0x8c, 0x31, 0xae, 0x13, 0x85, 0xcd, 0x07, 0x36, 0x43, 0xfb, 0x33,
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3987 0x53, 0xe2, 0x9f, 0xd9, 0xf2, 0xf7, 0x7a, 0x57, 0xf5, 0x6b, 0x94, 0x0d,
3988 0x4c, 0x58, 0x3c, 0x9b, 0x99, 0xd1, 0xb2, 0xf5, 0x3c, 0x72, 0xd5, 0x8d,
3989 0xc4, 0x43, 0x29, 0x1b, 0xb9, 0x92, 0xe7, 0x3c, 0x8d, 0x72, 0x81, 0xef,
3990 0x3d, 0xc3, 0x2e, 0xde, 0x21, 0x5e, 0xbe, 0x31, 0xa4, 0xde, 0x43, 0x70,
3991 0xfc, 0x73, 0x20, 0x31, 0x32, 0x63, 0x7c, 0xf7, 0xe0, 0x6e, 0xa9, 0x2f,
3992 0x7f, 0x11, 0x63, 0x19, 0xe4, 0xc5, 0x43, 0x5a, 0xe6, 0xdc, 0x24, 0xae,
3993 0x1f, 0xc2, 0x35, 0xe2, 0xf0, 0x72, 0x0e, 0xf7, 0x1f, 0xc2, 0xf5, 0xbc,
3994 0x96, 0x6d, 0xe6, 0x70, 0xfd, 0x30, 0xae, 0x27, 0x48, 0x9b, 0xf3, 0x8a,
3995 0x35, 0xa5, 0xd9, 0x58, 0xcb, 0x3e, 0x37, 0x89, 0x4f, 0xfb, 0x7a, 0xbc,
3996 0x07, 0x3d, 0x95, 0x79, 0x3e, 0x96, 0x04, 0x4d, 0x0f, 0x6a, 0x4e, 0xbd,
3997 0x1b, 0x6b, 0x0c, 0xe1, 0x79, 0xda, 0x54, 0xfb, 0x39, 0xd4, 0x6d, 0xaa,
3998 0x67, 0x14, 0x4a, 0xa7, 0x81, 0x77, 0x1f, 0x41, 0xde, 0xd7, 0xc4, 0xb1,
3999 0x1e, 0x97, 0x62, 0x2a, 0x2d, 0x0b, 0xf5, 0x90, 0x64, 0x63, 0x05, 0x7c,
4000 0x2f, 0x48, 0x66, 0x1c, 0xf7, 0xeb, 0xb4, 0x05, 0xce, 0x2b, 0x49, 0xb1,
4001 0x4a, 0xfc, 0xce, 0x7e, 0xd1, 0x57, 0xc0, 0x37, 0xfb, 0x44, 0x79, 0xc8,
4002 0x20, 0x46, 0xfb, 0xdd, 0xa1, 0xa7, 0xe5, 0xbd, 0xd3, 0x8c, 0x7c, 0xac,
4003 0x65, 0xea, 0xfe, 0x59, 0x9d, 0xc5, 0xdf, 0x2b, 0xb1, 0x47, 0x25, 0xc5,
4004 0x50, 0x9a, 0x7d, 0x0e, 0xd5, 0x17, 0x4f, 0x79, 0x67, 0x7a, 0xed, 0xef,
4005 0x90, 0x04, 0xfe, 0xc2, 0x7d, 0xbf, 0x82, 0xe7, 0xbd, 0xbe, 0x54, 0xb6,
4006 0xf9, 0x41, 0x5d, 0xf0, 0x5d, 0xfd, 0x15, 0xe8, 0xe2, 0xfc, 0x87, 0xf6,
4007 0xb9, 0xd8, 0xe3, 0x9a, 0x47, 0x2c, 0x62, 0x7f, 0x2c, 0x90, 0xdf, 0xd5,
4008 0x34, 0x92, 0xbe, 0xc3, 0x58, 0x4b, 0x52, 0x8c, 0xb3, 0xb9, 0x58, 0x42,
4009 0xd5, 0xbe, 0x1b, 0x4b, 0xf2, 0xc4, 0x16, 0xbd, 0xa4, 0x95, 0x72, 0x78,
4010 0x04, 0xf5, 0x1a, 0x7f, 0xff, 0xf0, 0xb8, 0xe4, 0x53, 0xec, 0xd1, 0x84,
4011 0x90, 0x0b, 0x0b, 0xf8, 0xbe, 0x25, 0xb7, 0x92, 0x2f, 0xb7, 0x7c, 0xf5,
4012 0x5b, 0x4a, 0x77, 0x35, 0x8b, 0xfb, 0x05, 0xbd, 0x8b, 0x69, 0xa5, 0xb3,
4013 0x9a, 0x7a, 0xcf, 0x36, 0xe0, 0x3d, 0xe8, 0xbf, 0xed, 0x6c, 0x73, 0x93,
4014 0x16, 0x69, 0xfb, 0x38, 0xdf, 0x5b, 0x18, 0xb6, 0x85, 0xf4, 0x93, 0x0f,
4015 0xe6, 0xac, 0xe0, 0x5c, 0x34, 0xe0, 0x21, 0xe0, 0xf3, 0xa3, 0xca, 0x85,
4016 0x74, 0xee, 0x31, 0xa4, 0x7b, 0xca, 0x08, 0x59, 0xcc, 0x01, 0x9f, 0xf6,
4017 0xfb, 0xf8, 0xff, 0x37, 0xe5, 0xea, 0xf1, 0x1e, 0x86, 0xa8, 0xfc, 0xdf,
4018 0x8b, 0xee, 0xa0, 0xf7, 0xab, 0xcf, 0x80, 0x0d, 0xe7, 0xac, 0xb5, 0xc5,
4019 0x67, 0x6d, 0x07, 0x3e, 0x6b, 0x3e, 0x9f, 0x1f, 0x7e, 0x4e, 0xea, 0xd1,
4020 0x59, 0x5b, 0xb2, 0xc1, 0x23, 0x6d, 0x6a, 0x27, 0x7b, 0xe3, 0x6f, 0x9c,
4021 0xd4, 0xef, 0xad, 0xa2, 0xb6, 0x7b, 0xad, 0x5e, 0x27, 0xeb, 0x64, 0xcf,
4022 0xee, 0xce, 0x22, 0xd7, 0x55, 0xab, 0x5e, 0xcd, 0x5c, 0x75, 0xd9, 0x6b,
4023 0xde, 0x69, 0x6f, 0x0d, 0x34, 0xff, 0x8e, 0x7a, 0xef, 0xa4, 0xe4, 0x7a,
4024 0x7d, 0xa9, 0x6a, 0xb5, 0x3d, 0x57, 0xde, 0xc0, 0x3c, 0x39, 0x5c, 0x90,
4025 0x19, 0xe8, 0x31, 0x89, 0xeb, 0x9b, 0xe5, 0xe5, 0x65, 0x75, 0x86, 0xe4,
4026 0x9f, 0xd5, 0xf0, 0x0c, 0x46, 0x9d, 0x43, 0x23, 0x5e, 0xcd, 0xaa, 0x78,
4027 0xbd, 0xb1, 0xac, 0xee, 0xa9, 0xdf, 0x3c, 0xd4, 0xdd, 0x19, 0xc4, 0x73,
4028 0xd4, 0x06, 0xd6, 0x6e, 0x29, 0xa2, 0x86, 0x3e, 0x6b, 0xcd, 0x18, 0xc4,
4029 0x29, 0x5c, 0x6b, 0x03, 0x6b, 0x9d, 0x5f, 0x96, 0xbd, 0x7c, 0xa7, 0xa3,
4030 0xaa, 0xce, 0xbd, 0xbc, 0x7e, 0xf5, 0xbc, 0x04, 0xbf, 0xd7, 0x8d, 0xfa,
4031 0x39, 0x8e, 0xef, 0x95, 0xf0, 0xb7, 0xa7, 0x8c, 0x01, 0xa8, 0x6b, 0x66,
4032 0x0a, 0x58, 0xaf, 0xd5, 0xf2, 0xfa, 0xd9, 0x2d, 0xd8, 0x7d, 0x84, 0xbf,
4033 0x65, 0xc0, 0xdf, 0x23, 0xb0, 0x13, 0xf8, 0xc1, 0xe6, 0x38, 0xaf, 0x59,
4034 0x4b, 0x04, 0xd7, 0x4c, 0x58, 0xff, 0x1b, 0xed, 0xcc, 0xfa, 0xa1, 0x98,
4035 0x41, 0x00, 0x00, 0x00 };
4036static u32 bnx2_TXP_b09FwData[(0xd0/4) + 1] = {
4037 0x00000000, 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000010,
4038 0x00000030, 0x00000030, 0x00000000, 0x00000000, 0x00000000, 0x00000010,
4039 0x00008000, 0x00000000, 0x00000000, 0x00000000, 0x00008002, 0x00000000,
4040 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
4041 0x00000000, 0x00000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4042 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000006,
4043 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000,
4044 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4045 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
4046static u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = {
4047 0x08003be8, 0x08003c14, 0x08003c5c, 0x08003c5c, 0x08003ae8, 0x08003b14,
4048 0x08003b14, 0x08003c5c, 0x08003c5c, 0x08003c5c, 0x08003b7c, 0x00000000,
4049 0x00000000 };
4050static u32 bnx2_TXP_b09FwBss[(0xa20/4) + 1] = { 0x0 };
4051static u32 bnx2_TXP_b09FwSbss[(0x80/4) + 1] = { 0x0 };
4052
4053static struct fw_info bnx2_txp_fw_09 = {
4054 .ver_major = 0x1,
4055 .ver_minor = 0x0,
4056 .ver_fix = 0x0,
4057
4058 .start_addr = 0x08000060,
4059
4060 .text_addr = 0x08000000,
4061 .text_len = 0x4194,
4062 .text_index = 0x0,
4063 .gz_text = bnx2_TXP_b09FwText,
4064 .gz_text_len = sizeof(bnx2_TXP_b09FwText),
4065
4066 .data_addr = 0x080041e0,
4067 .data_len = 0xd0,
4068 .data_index = 0x0,
4069 .data = bnx2_TXP_b09FwData,
4070
4071 .sbss_addr = 0x080042b0,
4072 .sbss_len = 0x80,
4073 .sbss_index = 0x0,
4074 .sbss = bnx2_TXP_b09FwSbss,
4075
4076 .bss_addr = 0x08004330,
4077 .bss_len = 0xa20,
4078 .bss_index = 0x0,
4079 .bss = bnx2_TXP_b09FwBss,
4080
4081 .rodata_addr = 0x08004198,
4082 .rodata_len = 0x30,
4083 .rodata_index = 0x0,
4084 .rodata = bnx2_TXP_b09FwRodata,
4085};
4086
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 17a461152d39..488d8ed9e740 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -1336,6 +1336,13 @@ int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
1336 goto err_undo_flags; 1336 goto err_undo_flags;
1337 } 1337 }
1338 1338
1339 if (slave_dev->get_stats == NULL) {
1340 printk(KERN_NOTICE DRV_NAME
1341 ": %s: the driver for slave device %s does not provide "
1342 "get_stats function, network statistics will be "
1343 "inaccurate.\n", bond_dev->name, slave_dev->name);
1344 }
1345
1339 new_slave = kmalloc(sizeof(struct slave), GFP_KERNEL); 1346 new_slave = kmalloc(sizeof(struct slave), GFP_KERNEL);
1340 if (!new_slave) { 1347 if (!new_slave) {
1341 res = -ENOMEM; 1348 res = -ENOMEM;
@@ -3605,33 +3612,35 @@ static struct net_device_stats *bond_get_stats(struct net_device *bond_dev)
3605 read_lock_bh(&bond->lock); 3612 read_lock_bh(&bond->lock);
3606 3613
3607 bond_for_each_slave(bond, slave, i) { 3614 bond_for_each_slave(bond, slave, i) {
3608 sstats = slave->dev->get_stats(slave->dev); 3615 if (slave->dev->get_stats) {
3609 3616 sstats = slave->dev->get_stats(slave->dev);
3610 stats->rx_packets += sstats->rx_packets; 3617
3611 stats->rx_bytes += sstats->rx_bytes; 3618 stats->rx_packets += sstats->rx_packets;
3612 stats->rx_errors += sstats->rx_errors; 3619 stats->rx_bytes += sstats->rx_bytes;
3613 stats->rx_dropped += sstats->rx_dropped; 3620 stats->rx_errors += sstats->rx_errors;
3614 3621 stats->rx_dropped += sstats->rx_dropped;
3615 stats->tx_packets += sstats->tx_packets; 3622
3616 stats->tx_bytes += sstats->tx_bytes; 3623 stats->tx_packets += sstats->tx_packets;
3617 stats->tx_errors += sstats->tx_errors; 3624 stats->tx_bytes += sstats->tx_bytes;
3618 stats->tx_dropped += sstats->tx_dropped; 3625 stats->tx_errors += sstats->tx_errors;
3619 3626 stats->tx_dropped += sstats->tx_dropped;
3620 stats->multicast += sstats->multicast; 3627
3621 stats->collisions += sstats->collisions; 3628 stats->multicast += sstats->multicast;
3622 3629 stats->collisions += sstats->collisions;
3623 stats->rx_length_errors += sstats->rx_length_errors; 3630
3624 stats->rx_over_errors += sstats->rx_over_errors; 3631 stats->rx_length_errors += sstats->rx_length_errors;
3625 stats->rx_crc_errors += sstats->rx_crc_errors; 3632 stats->rx_over_errors += sstats->rx_over_errors;
3626 stats->rx_frame_errors += sstats->rx_frame_errors; 3633 stats->rx_crc_errors += sstats->rx_crc_errors;
3627 stats->rx_fifo_errors += sstats->rx_fifo_errors; 3634 stats->rx_frame_errors += sstats->rx_frame_errors;
3628 stats->rx_missed_errors += sstats->rx_missed_errors; 3635 stats->rx_fifo_errors += sstats->rx_fifo_errors;
3629 3636 stats->rx_missed_errors += sstats->rx_missed_errors;
3630 stats->tx_aborted_errors += sstats->tx_aborted_errors; 3637
3631 stats->tx_carrier_errors += sstats->tx_carrier_errors; 3638 stats->tx_aborted_errors += sstats->tx_aborted_errors;
3632 stats->tx_fifo_errors += sstats->tx_fifo_errors; 3639 stats->tx_carrier_errors += sstats->tx_carrier_errors;
3633 stats->tx_heartbeat_errors += sstats->tx_heartbeat_errors; 3640 stats->tx_fifo_errors += sstats->tx_fifo_errors;
3634 stats->tx_window_errors += sstats->tx_window_errors; 3641 stats->tx_heartbeat_errors += sstats->tx_heartbeat_errors;
3642 stats->tx_window_errors += sstats->tx_window_errors;
3643 }
3635 } 3644 }
3636 3645
3637 read_unlock_bh(&bond->lock); 3646 read_unlock_bh(&bond->lock);
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index fe08f3845491..c8126484c2be 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -2825,7 +2825,7 @@ static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2825 u64 csum_start_off, csum_stuff_off; 2825 u64 csum_start_off, csum_stuff_off;
2826 2826
2827 csum_start_off = (u64) (skb->h.raw - skb->data); 2827 csum_start_off = (u64) (skb->h.raw - skb->data);
2828 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data); 2828 csum_stuff_off = csum_start_off + skb->csum_offset;
2829 2829
2830 ctrl = TX_DESC_CSUM_EN | 2830 ctrl = TX_DESC_CSUM_EN |
2831 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) | 2831 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
diff --git a/drivers/net/chelsio/Makefile b/drivers/net/chelsio/Makefile
index 54c78d94f48b..382d23f810ab 100644
--- a/drivers/net/chelsio/Makefile
+++ b/drivers/net/chelsio/Makefile
@@ -1,11 +1,11 @@
1# 1#
2# Chelsio 10Gb NIC driver for Linux. 2# Chelsio T1 driver
3# 3#
4 4
5obj-$(CONFIG_CHELSIO_T1) += cxgb.o 5obj-$(CONFIG_CHELSIO_T1) += cxgb.o
6 6
7EXTRA_CFLAGS += -Idrivers/net/chelsio $(DEBUG_FLAGS) 7cxgb-$(CONFIG_CHELSIO_T1_1G) += ixf1010.o mac.o mv88e1xxx.o vsc7326.o vsc8244.o
8cxgb-objs := cxgb2.o espi.o tp.o pm3393.o sge.o subr.o \
9 mv88x201x.o my3126.o $(cxgb-y)
8 10
9 11
10cxgb-objs := cxgb2.o espi.o pm3393.o sge.o subr.o mv88x201x.o
11
diff --git a/drivers/net/chelsio/common.h b/drivers/net/chelsio/common.h
index 8b1bedbce0d5..74758d2c7af8 100644
--- a/drivers/net/chelsio/common.h
+++ b/drivers/net/chelsio/common.h
@@ -45,6 +45,7 @@
45#include <linux/delay.h> 45#include <linux/delay.h>
46#include <linux/pci.h> 46#include <linux/pci.h>
47#include <linux/ethtool.h> 47#include <linux/ethtool.h>
48#include <linux/if_vlan.h>
48#include <linux/mii.h> 49#include <linux/mii.h>
49#include <linux/crc32.h> 50#include <linux/crc32.h>
50#include <linux/init.h> 51#include <linux/init.h>
@@ -53,13 +54,30 @@
53 54
54#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver" 55#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
55#define DRV_NAME "cxgb" 56#define DRV_NAME "cxgb"
56#define DRV_VERSION "2.1.1" 57#define DRV_VERSION "2.2"
57#define PFX DRV_NAME ": " 58#define PFX DRV_NAME ": "
58 59
59#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__) 60#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
60#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__) 61#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
61#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__) 62#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)
62 63
64/*
65 * More powerful macro that selectively prints messages based on msg_enable.
66 * For info and debugging messages.
67 */
68#define CH_MSG(adapter, level, category, fmt, ...) do { \
69 if ((adapter)->msg_enable & NETIF_MSG_##category) \
70 printk(KERN_##level PFX "%s: " fmt, (adapter)->name, \
71 ## __VA_ARGS__); \
72} while (0)
73
74#ifdef DEBUG
75# define CH_DBG(adapter, category, fmt, ...) \
76 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
77#else
78# define CH_DBG(fmt, ...)
79#endif
80
63#define CH_DEVICE(devid, ssid, idx) \ 81#define CH_DEVICE(devid, ssid, idx) \
64 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx } 82 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
65 83
@@ -71,10 +89,6 @@
71 89
72typedef struct adapter adapter_t; 90typedef struct adapter adapter_t;
73 91
74void t1_elmer0_ext_intr(adapter_t *adapter);
75void t1_link_changed(adapter_t *adapter, int port_id, int link_status,
76 int speed, int duplex, int fc);
77
78struct t1_rx_mode { 92struct t1_rx_mode {
79 struct net_device *dev; 93 struct net_device *dev;
80 u32 idx; 94 u32 idx;
@@ -97,26 +111,53 @@ static inline u8 *t1_get_next_mcaddr(struct t1_rx_mode *rm)
97} 111}
98 112
99#define MAX_NPORTS 4 113#define MAX_NPORTS 4
114#define PORT_MASK ((1 << MAX_NPORTS) - 1)
115#define NMTUS 8
116#define TCB_SIZE 128
100 117
101#define SPEED_INVALID 0xffff 118#define SPEED_INVALID 0xffff
102#define DUPLEX_INVALID 0xff 119#define DUPLEX_INVALID 0xff
103 120
104enum { 121enum {
105 CHBT_BOARD_N110, 122 CHBT_BOARD_N110,
106 CHBT_BOARD_N210 123 CHBT_BOARD_N210,
124 CHBT_BOARD_7500,
125 CHBT_BOARD_8000,
126 CHBT_BOARD_CHT101,
127 CHBT_BOARD_CHT110,
128 CHBT_BOARD_CHT210,
129 CHBT_BOARD_CHT204,
130 CHBT_BOARD_CHT204V,
131 CHBT_BOARD_CHT204E,
132 CHBT_BOARD_CHN204,
133 CHBT_BOARD_COUGAR,
134 CHBT_BOARD_6800,
135 CHBT_BOARD_SIMUL,
107}; 136};
108 137
109enum { 138enum {
139 CHBT_TERM_FPGA,
110 CHBT_TERM_T1, 140 CHBT_TERM_T1,
111 CHBT_TERM_T2 141 CHBT_TERM_T2,
142 CHBT_TERM_T3
112}; 143};
113 144
114enum { 145enum {
146 CHBT_MAC_CHELSIO_A,
147 CHBT_MAC_IXF1010,
115 CHBT_MAC_PM3393, 148 CHBT_MAC_PM3393,
149 CHBT_MAC_VSC7321,
150 CHBT_MAC_DUMMY
116}; 151};
117 152
118enum { 153enum {
154 CHBT_PHY_88E1041,
155 CHBT_PHY_88E1111,
119 CHBT_PHY_88X2010, 156 CHBT_PHY_88X2010,
157 CHBT_PHY_XPAK,
158 CHBT_PHY_MY3126,
159 CHBT_PHY_8244,
160 CHBT_PHY_DUMMY
120}; 161};
121 162
122enum { 163enum {
@@ -150,16 +191,44 @@ struct chelsio_pci_params {
150 unsigned char is_pcix; 191 unsigned char is_pcix;
151}; 192};
152 193
194struct tp_params {
195 unsigned int pm_size;
196 unsigned int cm_size;
197 unsigned int pm_rx_base;
198 unsigned int pm_tx_base;
199 unsigned int pm_rx_pg_size;
200 unsigned int pm_tx_pg_size;
201 unsigned int pm_rx_num_pgs;
202 unsigned int pm_tx_num_pgs;
203 unsigned int rx_coalescing_size;
204 unsigned int use_5tuple_mode;
205};
206
207struct mc5_params {
208 unsigned int mode; /* selects MC5 width */
209 unsigned int nservers; /* size of server region */
210 unsigned int nroutes; /* size of routing region */
211};
212
213/* Default MC5 region sizes */
214#define DEFAULT_SERVER_REGION_LEN 256
215#define DEFAULT_RT_REGION_LEN 1024
216
153struct adapter_params { 217struct adapter_params {
154 struct sge_params sge; 218 struct sge_params sge;
219 struct mc5_params mc5;
220 struct tp_params tp;
155 struct chelsio_pci_params pci; 221 struct chelsio_pci_params pci;
156 222
157 const struct board_info *brd_info; 223 const struct board_info *brd_info;
158 224
225 unsigned short mtus[NMTUS];
159 unsigned int nports; /* # of ethernet ports */ 226 unsigned int nports; /* # of ethernet ports */
160 unsigned int stats_update_period; 227 unsigned int stats_update_period;
161 unsigned short chip_revision; 228 unsigned short chip_revision;
162 unsigned char chip_version; 229 unsigned char chip_version;
230 unsigned char is_asic;
231 unsigned char has_msi;
163}; 232};
164 233
165struct link_config { 234struct link_config {
@@ -207,17 +276,20 @@ struct adapter {
207 /* Terminator modules. */ 276 /* Terminator modules. */
208 struct sge *sge; 277 struct sge *sge;
209 struct peespi *espi; 278 struct peespi *espi;
279 struct petp *tp;
210 280
211 struct port_info port[MAX_NPORTS]; 281 struct port_info port[MAX_NPORTS];
212 struct delayed_work stats_update_task; 282 struct delayed_work stats_update_task;
213 struct timer_list stats_update_timer; 283 struct timer_list stats_update_timer;
214 284
215 struct semaphore mib_mutex;
216 spinlock_t tpi_lock; 285 spinlock_t tpi_lock;
217 spinlock_t work_lock; 286 spinlock_t work_lock;
287 spinlock_t mac_lock;
288
218 /* guards async operations */ 289 /* guards async operations */
219 spinlock_t async_lock ____cacheline_aligned; 290 spinlock_t async_lock ____cacheline_aligned;
220 u32 slow_intr_mask; 291 u32 slow_intr_mask;
292 int t1powersave;
221}; 293};
222 294
223enum { /* adapter flags */ 295enum { /* adapter flags */
@@ -256,6 +328,11 @@ struct board_info {
256 const char *desc; 328 const char *desc;
257}; 329};
258 330
331static inline int t1_is_asic(const adapter_t *adapter)
332{
333 return adapter->params.is_asic;
334}
335
259extern struct pci_device_id t1_pci_tbl[]; 336extern struct pci_device_id t1_pci_tbl[];
260 337
261static inline int adapter_matches_type(const adapter_t *adapter, 338static inline int adapter_matches_type(const adapter_t *adapter,
@@ -285,13 +362,15 @@ static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
285 return board_info(adap)->clock_core / 1000000; 362 return board_info(adap)->clock_core / 1000000;
286} 363}
287 364
365extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
366extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
288extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); 367extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
289extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value); 368extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
290 369
291extern void t1_interrupts_enable(adapter_t *adapter); 370extern void t1_interrupts_enable(adapter_t *adapter);
292extern void t1_interrupts_disable(adapter_t *adapter); 371extern void t1_interrupts_disable(adapter_t *adapter);
293extern void t1_interrupts_clear(adapter_t *adapter); 372extern void t1_interrupts_clear(adapter_t *adapter);
294extern int elmer0_ext_intr_handler(adapter_t *adapter); 373extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
295extern int t1_slow_intr_handler(adapter_t *adapter); 374extern int t1_slow_intr_handler(adapter_t *adapter);
296 375
297extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 376extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
@@ -305,9 +384,7 @@ extern int t1_init_hw_modules(adapter_t *adapter);
305extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi); 384extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
306extern void t1_free_sw_modules(adapter_t *adapter); 385extern void t1_free_sw_modules(adapter_t *adapter);
307extern void t1_fatal_err(adapter_t *adapter); 386extern void t1_fatal_err(adapter_t *adapter);
308 387extern void t1_link_changed(adapter_t *adapter, int port_id);
309extern void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable); 388extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
310extern void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable); 389 int speed, int duplex, int pause);
311extern void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable);
312
313#endif /* _CXGB_COMMON_H_ */ 390#endif /* _CXGB_COMMON_H_ */
diff --git a/drivers/net/chelsio/cphy.h b/drivers/net/chelsio/cphy.h
index 3412342f7345..60901f25014e 100644
--- a/drivers/net/chelsio/cphy.h
+++ b/drivers/net/chelsio/cphy.h
@@ -52,7 +52,14 @@ struct mdio_ops {
52/* PHY interrupt types */ 52/* PHY interrupt types */
53enum { 53enum {
54 cphy_cause_link_change = 0x1, 54 cphy_cause_link_change = 0x1,
55 cphy_cause_error = 0x2 55 cphy_cause_error = 0x2,
56 cphy_cause_fifo_error = 0x3
57};
58
59enum {
60 PHY_LINK_UP = 0x1,
61 PHY_AUTONEG_RDY = 0x2,
62 PHY_AUTONEG_EN = 0x4
56}; 63};
57 64
58struct cphy; 65struct cphy;
@@ -81,7 +88,18 @@ struct cphy_ops {
81/* A PHY instance */ 88/* A PHY instance */
82struct cphy { 89struct cphy {
83 int addr; /* PHY address */ 90 int addr; /* PHY address */
91 int state; /* Link status state machine */
84 adapter_t *adapter; /* associated adapter */ 92 adapter_t *adapter; /* associated adapter */
93
94 struct work_struct phy_update;
95
96 u16 bmsr;
97 int count;
98 int act_count;
99 int act_on;
100
101 u32 elmer_gpo;
102
85 struct cphy_ops *ops; /* PHY operations */ 103 struct cphy_ops *ops; /* PHY operations */
86 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 104 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
87 int reg_addr, unsigned int *val); 105 int reg_addr, unsigned int *val);
@@ -142,6 +160,10 @@ struct gphy {
142 int (*reset)(adapter_t *adapter); 160 int (*reset)(adapter_t *adapter);
143}; 161};
144 162
163extern struct gphy t1_my3126_ops;
164extern struct gphy t1_mv88e1xxx_ops;
165extern struct gphy t1_vsc8244_ops;
166extern struct gphy t1_xpak_ops;
145extern struct gphy t1_mv88x201x_ops; 167extern struct gphy t1_mv88x201x_ops;
146extern struct gphy t1_dummy_phy_ops; 168extern struct gphy t1_dummy_phy_ops;
147 169
diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h
index 5b357d9e88d6..35f565be4fd3 100644
--- a/drivers/net/chelsio/cpl5_cmd.h
+++ b/drivers/net/chelsio/cpl5_cmd.h
@@ -46,24 +46,385 @@
46#endif 46#endif
47 47
48enum CPL_opcode { 48enum CPL_opcode {
49 CPL_PASS_OPEN_REQ = 0x1,
50 CPL_PASS_OPEN_RPL = 0x2,
51 CPL_PASS_ESTABLISH = 0x3,
52 CPL_PASS_ACCEPT_REQ = 0xE,
53 CPL_PASS_ACCEPT_RPL = 0x4,
54 CPL_ACT_OPEN_REQ = 0x5,
55 CPL_ACT_OPEN_RPL = 0x6,
56 CPL_CLOSE_CON_REQ = 0x7,
57 CPL_CLOSE_CON_RPL = 0x8,
58 CPL_CLOSE_LISTSRV_REQ = 0x9,
59 CPL_CLOSE_LISTSRV_RPL = 0xA,
60 CPL_ABORT_REQ = 0xB,
61 CPL_ABORT_RPL = 0xC,
62 CPL_PEER_CLOSE = 0xD,
63 CPL_ACT_ESTABLISH = 0x17,
64
65 CPL_GET_TCB = 0x24,
66 CPL_GET_TCB_RPL = 0x25,
67 CPL_SET_TCB = 0x26,
68 CPL_SET_TCB_FIELD = 0x27,
69 CPL_SET_TCB_RPL = 0x28,
70 CPL_PCMD = 0x29,
71
72 CPL_PCMD_READ = 0x31,
73 CPL_PCMD_READ_RPL = 0x32,
74
75
76 CPL_RX_DATA = 0xA0,
77 CPL_RX_DATA_DDP = 0xA1,
78 CPL_RX_DATA_ACK = 0xA3,
49 CPL_RX_PKT = 0xAD, 79 CPL_RX_PKT = 0xAD,
80 CPL_RX_ISCSI_HDR = 0xAF,
81 CPL_TX_DATA_ACK = 0xB0,
82 CPL_TX_DATA = 0xB1,
50 CPL_TX_PKT = 0xB2, 83 CPL_TX_PKT = 0xB2,
51 CPL_TX_PKT_LSO = 0xB6, 84 CPL_TX_PKT_LSO = 0xB6,
85
86 CPL_RTE_DELETE_REQ = 0xC0,
87 CPL_RTE_DELETE_RPL = 0xC1,
88 CPL_RTE_WRITE_REQ = 0xC2,
89 CPL_RTE_WRITE_RPL = 0xD3,
90 CPL_RTE_READ_REQ = 0xC3,
91 CPL_RTE_READ_RPL = 0xC4,
92 CPL_L2T_WRITE_REQ = 0xC5,
93 CPL_L2T_WRITE_RPL = 0xD4,
94 CPL_L2T_READ_REQ = 0xC6,
95 CPL_L2T_READ_RPL = 0xC7,
96 CPL_SMT_WRITE_REQ = 0xC8,
97 CPL_SMT_WRITE_RPL = 0xD5,
98 CPL_SMT_READ_REQ = 0xC9,
99 CPL_SMT_READ_RPL = 0xCA,
100 CPL_ARP_MISS_REQ = 0xCD,
101 CPL_ARP_MISS_RPL = 0xCE,
102 CPL_MIGRATE_C2T_REQ = 0xDC,
103 CPL_MIGRATE_C2T_RPL = 0xDD,
104 CPL_ERROR = 0xD7,
105
106 /* internal: driver -> TOM */
107 CPL_MSS_CHANGE = 0xE1
52}; 108};
53 109
54enum { /* TX_PKT_LSO ethernet types */ 110#define NUM_CPL_CMDS 256
111
112enum CPL_error {
113 CPL_ERR_NONE = 0,
114 CPL_ERR_TCAM_PARITY = 1,
115 CPL_ERR_TCAM_FULL = 3,
116 CPL_ERR_CONN_RESET = 20,
117 CPL_ERR_CONN_EXIST = 22,
118 CPL_ERR_ARP_MISS = 23,
119 CPL_ERR_BAD_SYN = 24,
120 CPL_ERR_CONN_TIMEDOUT = 30,
121 CPL_ERR_XMIT_TIMEDOUT = 31,
122 CPL_ERR_PERSIST_TIMEDOUT = 32,
123 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
124 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
125 CPL_ERR_ABORT_FAILED = 42,
126 CPL_ERR_GENERAL = 99
127};
128
129enum {
130 CPL_CONN_POLICY_AUTO = 0,
131 CPL_CONN_POLICY_ASK = 1,
132 CPL_CONN_POLICY_DENY = 3
133};
134
135enum {
136 ULP_MODE_NONE = 0,
137 ULP_MODE_TCPDDP = 1,
138 ULP_MODE_ISCSI = 2,
139 ULP_MODE_IWARP = 3,
140 ULP_MODE_SSL = 4
141};
142
143enum {
144 CPL_PASS_OPEN_ACCEPT,
145 CPL_PASS_OPEN_REJECT
146};
147
148enum {
149 CPL_ABORT_SEND_RST = 0,
150 CPL_ABORT_NO_RST,
151 CPL_ABORT_POST_CLOSE_REQ = 2
152};
153
154enum { // TX_PKT_LSO ethernet types
55 CPL_ETH_II, 155 CPL_ETH_II,
56 CPL_ETH_II_VLAN, 156 CPL_ETH_II_VLAN,
57 CPL_ETH_802_3, 157 CPL_ETH_802_3,
58 CPL_ETH_802_3_VLAN 158 CPL_ETH_802_3_VLAN
59}; 159};
60 160
61struct cpl_rx_data { 161union opcode_tid {
162 u32 opcode_tid;
163 u8 opcode;
164};
165
166#define S_OPCODE 24
167#define V_OPCODE(x) ((x) << S_OPCODE)
168#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
169#define G_TID(x) ((x) & 0xFFFFFF)
170
171/* tid is assumed to be 24-bits */
172#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
173
174#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
175
176/* extract the TID from a CPL command */
177#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
178
179struct tcp_options {
180 u16 mss;
181 u8 wsf;
182#if defined(__LITTLE_ENDIAN_BITFIELD)
183 u8 rsvd:4;
184 u8 ecn:1;
185 u8 sack:1;
186 u8 tstamp:1;
187#else
188 u8 tstamp:1;
189 u8 sack:1;
190 u8 ecn:1;
191 u8 rsvd:4;
192#endif
193};
194
195struct cpl_pass_open_req {
196 union opcode_tid ot;
197 u16 local_port;
198 u16 peer_port;
199 u32 local_ip;
200 u32 peer_ip;
201 u32 opt0h;
202 u32 opt0l;
203 u32 peer_netmask;
204 u32 opt1;
205};
206
207struct cpl_pass_open_rpl {
208 union opcode_tid ot;
209 u16 local_port;
210 u16 peer_port;
211 u32 local_ip;
212 u32 peer_ip;
213 u8 resvd[7];
214 u8 status;
215};
216
217struct cpl_pass_establish {
218 union opcode_tid ot;
219 u16 local_port;
220 u16 peer_port;
221 u32 local_ip;
222 u32 peer_ip;
223 u32 tos_tid;
224 u8 l2t_idx;
225 u8 rsvd[3];
226 u32 snd_isn;
227 u32 rcv_isn;
228};
229
230struct cpl_pass_accept_req {
231 union opcode_tid ot;
232 u16 local_port;
233 u16 peer_port;
234 u32 local_ip;
235 u32 peer_ip;
236 u32 tos_tid;
237 struct tcp_options tcp_options;
238 u8 dst_mac[6];
239 u16 vlan_tag;
240 u8 src_mac[6];
241 u8 rsvd[2];
242 u32 rcv_isn;
243 u32 unknown_tcp_options;
244};
245
246struct cpl_pass_accept_rpl {
247 union opcode_tid ot;
248 u32 rsvd0;
249 u32 rsvd1;
250 u32 peer_ip;
251 u32 opt0h;
252 union {
253 u32 opt0l;
254 struct {
255 u8 rsvd[3];
256 u8 status;
257 };
258 };
259};
260
261struct cpl_act_open_req {
262 union opcode_tid ot;
263 u16 local_port;
264 u16 peer_port;
265 u32 local_ip;
266 u32 peer_ip;
267 u32 opt0h;
268 u32 opt0l;
269 u32 iff_vlantag;
270 u32 rsvd;
271};
272
273struct cpl_act_open_rpl {
274 union opcode_tid ot;
275 u16 local_port;
276 u16 peer_port;
277 u32 local_ip;
278 u32 peer_ip;
279 u32 new_tid;
280 u8 rsvd[3];
281 u8 status;
282};
283
284struct cpl_act_establish {
285 union opcode_tid ot;
286 u16 local_port;
287 u16 peer_port;
288 u32 local_ip;
289 u32 peer_ip;
290 u32 tos_tid;
291 u32 rsvd;
292 u32 snd_isn;
293 u32 rcv_isn;
294};
295
296struct cpl_get_tcb {
297 union opcode_tid ot;
298 u32 rsvd;
299};
300
301struct cpl_get_tcb_rpl {
302 union opcode_tid ot;
303 u16 len;
304 u8 rsvd;
305 u8 status;
306};
307
308struct cpl_set_tcb {
309 union opcode_tid ot;
310 u16 len;
311 u16 rsvd;
312};
313
314struct cpl_set_tcb_field {
315 union opcode_tid ot;
316 u8 rsvd[3];
317 u8 offset;
318 u32 mask;
319 u32 val;
320};
321
322struct cpl_set_tcb_rpl {
323 union opcode_tid ot;
324 u8 rsvd[3];
325 u8 status;
326};
327
328struct cpl_pcmd {
329 union opcode_tid ot;
330 u16 dlen_in;
331 u16 dlen_out;
332 u32 pcmd_parm[2];
333};
334
335struct cpl_pcmd_read {
336 union opcode_tid ot;
337 u32 rsvd1;
338 u16 rsvd2;
339 u32 addr;
340 u16 len;
341};
342
343struct cpl_pcmd_read_rpl {
344 union opcode_tid ot;
345 u16 len;
346};
347
348struct cpl_close_con_req {
349 union opcode_tid ot;
350 u32 rsvd;
351};
352
353struct cpl_close_con_rpl {
354 union opcode_tid ot;
355 u8 rsvd[3];
356 u8 status;
357 u32 snd_nxt;
358 u32 rcv_nxt;
359};
360
361struct cpl_close_listserv_req {
362 union opcode_tid ot;
363 u32 rsvd;
364};
365
366struct cpl_close_listserv_rpl {
367 union opcode_tid ot;
368 u8 rsvd[3];
369 u8 status;
370};
371
372struct cpl_abort_req {
373 union opcode_tid ot;
62 u32 rsvd0; 374 u32 rsvd0;
375 u8 rsvd1;
376 u8 cmd;
377 u8 rsvd2[6];
378};
379
380struct cpl_abort_rpl {
381 union opcode_tid ot;
382 u32 rsvd0;
383 u8 rsvd1;
384 u8 status;
385 u8 rsvd2[6];
386};
387
388struct cpl_peer_close {
389 union opcode_tid ot;
390 u32 rsvd;
391};
392
393struct cpl_tx_data {
394 union opcode_tid ot;
395 u32 len;
396 u32 rsvd0;
397 u16 urg;
398 u16 flags;
399};
400
401struct cpl_tx_data_ack {
402 union opcode_tid ot;
403 u32 ack_seq;
404};
405
406struct cpl_rx_data {
407 union opcode_tid ot;
63 u32 len; 408 u32 len;
64 u32 seq; 409 u32 seq;
65 u16 urg; 410 u16 urg;
66 u8 rsvd1; 411 u8 rsvd;
412 u8 status;
413};
414
415struct cpl_rx_data_ack {
416 union opcode_tid ot;
417 u32 credit;
418};
419
420struct cpl_rx_data_ddp {
421 union opcode_tid ot;
422 u32 len;
423 u32 seq;
424 u32 nxt_seq;
425 u32 ulp_crc;
426 u16 ddp_status;
427 u8 rsvd;
67 u8 status; 428 u8 status;
68}; 429};
69 430
@@ -99,9 +460,9 @@ struct cpl_tx_pkt_lso {
99 u8 ip_csum_dis:1; 460 u8 ip_csum_dis:1;
100 u8 l4_csum_dis:1; 461 u8 l4_csum_dis:1;
101 u8 vlan_valid:1; 462 u8 vlan_valid:1;
102 u8 rsvd:1; 463 u8 :1;
103#else 464#else
104 u8 rsvd:1; 465 u8 :1;
105 u8 vlan_valid:1; 466 u8 vlan_valid:1;
106 u8 l4_csum_dis:1; 467 u8 l4_csum_dis:1;
107 u8 ip_csum_dis:1; 468 u8 ip_csum_dis:1;
@@ -110,8 +471,7 @@ struct cpl_tx_pkt_lso {
110 u16 vlan; 471 u16 vlan;
111 __be32 len; 472 __be32 len;
112 473
113 u32 rsvd2; 474 u8 rsvd[5];
114 u8 rsvd3;
115#if defined(__LITTLE_ENDIAN_BITFIELD) 475#if defined(__LITTLE_ENDIAN_BITFIELD)
116 u8 tcp_hdr_words:4; 476 u8 tcp_hdr_words:4;
117 u8 ip_hdr_words:4; 477 u8 ip_hdr_words:4;
@@ -138,8 +498,142 @@ struct cpl_rx_pkt {
138 u8 iff:4; 498 u8 iff:4;
139#endif 499#endif
140 u16 csum; 500 u16 csum;
141 __be16 vlan; 501 u16 vlan;
142 u16 len; 502 u16 len;
143}; 503};
144 504
505struct cpl_l2t_write_req {
506 union opcode_tid ot;
507 u32 params;
508 u8 rsvd1[2];
509 u8 dst_mac[6];
510};
511
512struct cpl_l2t_write_rpl {
513 union opcode_tid ot;
514 u8 status;
515 u8 rsvd[3];
516};
517
518struct cpl_l2t_read_req {
519 union opcode_tid ot;
520 u8 rsvd[3];
521 u8 l2t_idx;
522};
523
524struct cpl_l2t_read_rpl {
525 union opcode_tid ot;
526 u32 params;
527 u8 rsvd1[2];
528 u8 dst_mac[6];
529};
530
531struct cpl_smt_write_req {
532 union opcode_tid ot;
533 u8 rsvd0;
534#if defined(__LITTLE_ENDIAN_BITFIELD)
535 u8 rsvd1:1;
536 u8 mtu_idx:3;
537 u8 iff:4;
538#else
539 u8 iff:4;
540 u8 mtu_idx:3;
541 u8 rsvd1:1;
542#endif
543 u16 rsvd2;
544 u16 rsvd3;
545 u8 src_mac1[6];
546 u16 rsvd4;
547 u8 src_mac0[6];
548};
549
550struct cpl_smt_write_rpl {
551 union opcode_tid ot;
552 u8 status;
553 u8 rsvd[3];
554};
555
556struct cpl_smt_read_req {
557 union opcode_tid ot;
558 u8 rsvd0;
559#if defined(__LITTLE_ENDIAN_BITFIELD)
560 u8 rsvd1:4;
561 u8 iff:4;
562#else
563 u8 iff:4;
564 u8 rsvd1:4;
565#endif
566 u16 rsvd2;
567};
568
569struct cpl_smt_read_rpl {
570 union opcode_tid ot;
571 u8 status;
572#if defined(__LITTLE_ENDIAN_BITFIELD)
573 u8 rsvd1:1;
574 u8 mtu_idx:3;
575 u8 rsvd0:4;
576#else
577 u8 rsvd0:4;
578 u8 mtu_idx:3;
579 u8 rsvd1:1;
580#endif
581 u16 rsvd2;
582 u16 rsvd3;
583 u8 src_mac1[6];
584 u16 rsvd4;
585 u8 src_mac0[6];
586};
587
588struct cpl_rte_delete_req {
589 union opcode_tid ot;
590 u32 params;
591};
592
593struct cpl_rte_delete_rpl {
594 union opcode_tid ot;
595 u8 status;
596 u8 rsvd[3];
597};
598
599struct cpl_rte_write_req {
600 union opcode_tid ot;
601 u32 params;
602 u32 netmask;
603 u32 faddr;
604};
605
606struct cpl_rte_write_rpl {
607 union opcode_tid ot;
608 u8 status;
609 u8 rsvd[3];
610};
611
612struct cpl_rte_read_req {
613 union opcode_tid ot;
614 u32 params;
615};
616
617struct cpl_rte_read_rpl {
618 union opcode_tid ot;
619 u8 status;
620 u8 rsvd0[2];
621 u8 l2t_idx;
622#if defined(__LITTLE_ENDIAN_BITFIELD)
623 u8 rsvd1:7;
624 u8 select:1;
625#else
626 u8 select:1;
627 u8 rsvd1:7;
628#endif
629 u8 rsvd2[3];
630 u32 addr;
631};
632
633struct cpl_mss_change {
634 union opcode_tid ot;
635 u32 mss;
636};
637
145#endif /* _CXGB_CPL5_CMD_H_ */ 638#endif /* _CXGB_CPL5_CMD_H_ */
639
diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c
index f607cc6a276b..de48eadddbc4 100644
--- a/drivers/net/chelsio/cxgb2.c
+++ b/drivers/net/chelsio/cxgb2.c
@@ -45,7 +45,6 @@
45#include <linux/if_vlan.h> 45#include <linux/if_vlan.h>
46#include <linux/mii.h> 46#include <linux/mii.h>
47#include <linux/sockios.h> 47#include <linux/sockios.h>
48#include <linux/proc_fs.h>
49#include <linux/dma-mapping.h> 48#include <linux/dma-mapping.h>
50#include <asm/uaccess.h> 49#include <asm/uaccess.h>
51 50
@@ -54,36 +53,10 @@
54#include "gmac.h" 53#include "gmac.h"
55#include "cphy.h" 54#include "cphy.h"
56#include "sge.h" 55#include "sge.h"
56#include "tp.h"
57#include "espi.h" 57#include "espi.h"
58#include "elmer0.h"
58 59
59#ifdef work_struct
60#include <linux/tqueue.h>
61#define INIT_WORK INIT_TQUEUE
62#define schedule_work schedule_task
63#define flush_scheduled_work flush_scheduled_tasks
64
65static inline void schedule_mac_stats_update(struct adapter *ap, int secs)
66{
67 mod_timer(&ap->stats_update_timer, jiffies + secs * HZ);
68}
69
70static inline void cancel_mac_stats_update(struct adapter *ap)
71{
72 del_timer_sync(&ap->stats_update_timer);
73 flush_scheduled_tasks();
74}
75
76/*
77 * Stats update timer for 2.4. It schedules a task to do the actual update as
78 * we need to access MAC statistics in process context.
79 */
80static void mac_stats_timer(unsigned long data)
81{
82 struct adapter *ap = (struct adapter *)data;
83
84 schedule_task(&ap->stats_update_task);
85}
86#else
87#include <linux/workqueue.h> 60#include <linux/workqueue.h>
88 61
89static inline void schedule_mac_stats_update(struct adapter *ap, int secs) 62static inline void schedule_mac_stats_update(struct adapter *ap, int secs)
@@ -95,7 +68,6 @@ static inline void cancel_mac_stats_update(struct adapter *ap)
95{ 68{
96 cancel_delayed_work(&ap->stats_update_task); 69 cancel_delayed_work(&ap->stats_update_task);
97} 70}
98#endif
99 71
100#define MAX_CMDQ_ENTRIES 16384 72#define MAX_CMDQ_ENTRIES 16384
101#define MAX_CMDQ1_ENTRIES 1024 73#define MAX_CMDQ1_ENTRIES 1024
@@ -103,10 +75,9 @@ static inline void cancel_mac_stats_update(struct adapter *ap)
103#define MAX_RX_JUMBO_BUFFERS 16384 75#define MAX_RX_JUMBO_BUFFERS 16384
104#define MAX_TX_BUFFERS_HIGH 16384U 76#define MAX_TX_BUFFERS_HIGH 16384U
105#define MAX_TX_BUFFERS_LOW 1536U 77#define MAX_TX_BUFFERS_LOW 1536U
78#define MAX_TX_BUFFERS 1460U
106#define MIN_FL_ENTRIES 32 79#define MIN_FL_ENTRIES 32
107 80
108#define PORT_MASK ((1 << MAX_NPORTS) - 1)
109
110#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 81#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
111 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 82 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
112 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 83 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
@@ -124,8 +95,21 @@ MODULE_LICENSE("GPL");
124static int dflt_msg_enable = DFLT_MSG_ENABLE; 95static int dflt_msg_enable = DFLT_MSG_ENABLE;
125 96
126module_param(dflt_msg_enable, int, 0); 97module_param(dflt_msg_enable, int, 0);
127MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 message enable bitmap"); 98MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 default message enable bitmap");
99
100#define HCLOCK 0x0
101#define LCLOCK 0x1
102
103/* T1 cards powersave mode */
104static int t1_clock(struct adapter *adapter, int mode);
105static int t1powersave = 1; /* HW default is powersave mode. */
128 106
107module_param(t1powersave, int, 0);
108MODULE_PARM_DESC(t1powersave, "Enable/Disable T1 powersaving mode");
109
110static int disable_msi = 0;
111module_param(disable_msi, int, 0);
112MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
129 113
130static const char pci_speed[][4] = { 114static const char pci_speed[][4] = {
131 "33", "66", "100", "133" 115 "33", "66", "100", "133"
@@ -149,7 +133,7 @@ static void t1_set_rxmode(struct net_device *dev)
149static void link_report(struct port_info *p) 133static void link_report(struct port_info *p)
150{ 134{
151 if (!netif_carrier_ok(p->dev)) 135 if (!netif_carrier_ok(p->dev))
152 printk(KERN_INFO "%s: link down\n", p->dev->name); 136 printk(KERN_INFO "%s: link down\n", p->dev->name);
153 else { 137 else {
154 const char *s = "10Mbps"; 138 const char *s = "10Mbps";
155 139
@@ -159,13 +143,13 @@ static void link_report(struct port_info *p)
159 case SPEED_100: s = "100Mbps"; break; 143 case SPEED_100: s = "100Mbps"; break;
160 } 144 }
161 145
162 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", 146 printk(KERN_INFO "%s: link up, %s, %s-duplex\n",
163 p->dev->name, s, 147 p->dev->name, s,
164 p->link_config.duplex == DUPLEX_FULL ? "full" : "half"); 148 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
165 } 149 }
166} 150}
167 151
168void t1_link_changed(struct adapter *adapter, int port_id, int link_stat, 152void t1_link_negotiated(struct adapter *adapter, int port_id, int link_stat,
169 int speed, int duplex, int pause) 153 int speed, int duplex, int pause)
170{ 154{
171 struct port_info *p = &adapter->port[port_id]; 155 struct port_info *p = &adapter->port[port_id];
@@ -177,6 +161,22 @@ void t1_link_changed(struct adapter *adapter, int port_id, int link_stat,
177 netif_carrier_off(p->dev); 161 netif_carrier_off(p->dev);
178 link_report(p); 162 link_report(p);
179 163
164 /* multi-ports: inform toe */
165 if ((speed > 0) && (adapter->params.nports > 1)) {
166 unsigned int sched_speed = 10;
167 switch (speed) {
168 case SPEED_1000:
169 sched_speed = 1000;
170 break;
171 case SPEED_100:
172 sched_speed = 100;
173 break;
174 case SPEED_10:
175 sched_speed = 10;
176 break;
177 }
178 t1_sched_update_parms(adapter->sge, port_id, 0, sched_speed);
179 }
180 } 180 }
181} 181}
182 182
@@ -195,8 +195,10 @@ static void link_start(struct port_info *p)
195static void enable_hw_csum(struct adapter *adapter) 195static void enable_hw_csum(struct adapter *adapter)
196{ 196{
197 if (adapter->flags & TSO_CAPABLE) 197 if (adapter->flags & TSO_CAPABLE)
198 t1_tp_set_ip_checksum_offload(adapter, 1); /* for TSO only */ 198 t1_tp_set_ip_checksum_offload(adapter->tp, 1); /* for TSO only */
199 t1_tp_set_tcp_checksum_offload(adapter, 1); 199 if (adapter->flags & UDP_CSUM_CAPABLE)
200 t1_tp_set_udp_checksum_offload(adapter->tp, 1);
201 t1_tp_set_tcp_checksum_offload(adapter->tp, 1);
200} 202}
201 203
202/* 204/*
@@ -217,11 +219,19 @@ static int cxgb_up(struct adapter *adapter)
217 } 219 }
218 220
219 t1_interrupts_clear(adapter); 221 t1_interrupts_clear(adapter);
220 if ((err = request_irq(adapter->pdev->irq, 222
221 t1_select_intr_handler(adapter), IRQF_SHARED, 223 adapter->params.has_msi = !disable_msi && pci_enable_msi(adapter->pdev) == 0;
222 adapter->name, adapter))) { 224 err = request_irq(adapter->pdev->irq,
225 t1_select_intr_handler(adapter),
226 adapter->params.has_msi ? 0 : IRQF_SHARED,
227 adapter->name, adapter);
228 if (err) {
229 if (adapter->params.has_msi)
230 pci_disable_msi(adapter->pdev);
231
223 goto out_err; 232 goto out_err;
224 } 233 }
234
225 t1_sge_start(adapter->sge); 235 t1_sge_start(adapter->sge);
226 t1_interrupts_enable(adapter); 236 t1_interrupts_enable(adapter);
227 out_err: 237 out_err:
@@ -236,6 +246,8 @@ static void cxgb_down(struct adapter *adapter)
236 t1_sge_stop(adapter->sge); 246 t1_sge_stop(adapter->sge);
237 t1_interrupts_disable(adapter); 247 t1_interrupts_disable(adapter);
238 free_irq(adapter->pdev->irq, adapter); 248 free_irq(adapter->pdev->irq, adapter);
249 if (adapter->params.has_msi)
250 pci_disable_msi(adapter->pdev);
239} 251}
240 252
241static int cxgb_open(struct net_device *dev) 253static int cxgb_open(struct net_device *dev)
@@ -290,7 +302,7 @@ static struct net_device_stats *t1_get_stats(struct net_device *dev)
290 302
291 /* Do a full update of the MAC stats */ 303 /* Do a full update of the MAC stats */
292 pstats = p->mac->ops->statistics_update(p->mac, 304 pstats = p->mac->ops->statistics_update(p->mac,
293 MAC_STATS_UPDATE_FULL); 305 MAC_STATS_UPDATE_FULL);
294 306
295 ns->tx_packets = pstats->TxUnicastFramesOK + 307 ns->tx_packets = pstats->TxUnicastFramesOK +
296 pstats->TxMulticastFramesOK + pstats->TxBroadcastFramesOK; 308 pstats->TxMulticastFramesOK + pstats->TxBroadcastFramesOK;
@@ -344,47 +356,53 @@ static void set_msglevel(struct net_device *dev, u32 val)
344} 356}
345 357
346static char stats_strings[][ETH_GSTRING_LEN] = { 358static char stats_strings[][ETH_GSTRING_LEN] = {
347 "TxOctetsOK", 359 "TxOctetsOK",
348 "TxOctetsBad", 360 "TxOctetsBad",
349 "TxUnicastFramesOK", 361 "TxUnicastFramesOK",
350 "TxMulticastFramesOK", 362 "TxMulticastFramesOK",
351 "TxBroadcastFramesOK", 363 "TxBroadcastFramesOK",
352 "TxPauseFrames", 364 "TxPauseFrames",
353 "TxFramesWithDeferredXmissions", 365 "TxFramesWithDeferredXmissions",
354 "TxLateCollisions", 366 "TxLateCollisions",
355 "TxTotalCollisions", 367 "TxTotalCollisions",
356 "TxFramesAbortedDueToXSCollisions", 368 "TxFramesAbortedDueToXSCollisions",
357 "TxUnderrun", 369 "TxUnderrun",
358 "TxLengthErrors", 370 "TxLengthErrors",
359 "TxInternalMACXmitError", 371 "TxInternalMACXmitError",
360 "TxFramesWithExcessiveDeferral", 372 "TxFramesWithExcessiveDeferral",
361 "TxFCSErrors", 373 "TxFCSErrors",
362 374
363 "RxOctetsOK", 375 "RxOctetsOK",
364 "RxOctetsBad", 376 "RxOctetsBad",
365 "RxUnicastFramesOK", 377 "RxUnicastFramesOK",
366 "RxMulticastFramesOK", 378 "RxMulticastFramesOK",
367 "RxBroadcastFramesOK", 379 "RxBroadcastFramesOK",
368 "RxPauseFrames", 380 "RxPauseFrames",
369 "RxFCSErrors", 381 "RxFCSErrors",
370 "RxAlignErrors", 382 "RxAlignErrors",
371 "RxSymbolErrors", 383 "RxSymbolErrors",
372 "RxDataErrors", 384 "RxDataErrors",
373 "RxSequenceErrors", 385 "RxSequenceErrors",
374 "RxRuntErrors", 386 "RxRuntErrors",
375 "RxJabberErrors", 387 "RxJabberErrors",
376 "RxInternalMACRcvError", 388 "RxInternalMACRcvError",
377 "RxInRangeLengthErrors", 389 "RxInRangeLengthErrors",
378 "RxOutOfRangeLengthField", 390 "RxOutOfRangeLengthField",
379 "RxFrameTooLongErrors", 391 "RxFrameTooLongErrors",
380 392
381 "TSO", 393 /* Port stats */
382 "VLANextractions", 394 "RxPackets",
383 "VLANinsertions",
384 "RxCsumGood", 395 "RxCsumGood",
396 "TxPackets",
385 "TxCsumOffload", 397 "TxCsumOffload",
386 "RxDrops" 398 "TxTso",
387 399 "RxVlan",
400 "TxVlan",
401
402 /* Interrupt stats */
403 "rx drops",
404 "pure_rsps",
405 "unhandled irqs",
388 "respQ_empty", 406 "respQ_empty",
389 "respQ_overflow", 407 "respQ_overflow",
390 "freelistQ_empty", 408 "freelistQ_empty",
@@ -392,11 +410,7 @@ static char stats_strings[][ETH_GSTRING_LEN] = {
392 "pkt_mismatch", 410 "pkt_mismatch",
393 "cmdQ_full0", 411 "cmdQ_full0",
394 "cmdQ_full1", 412 "cmdQ_full1",
395 "tx_ipfrags", 413
396 "tx_reg_pkts",
397 "tx_lso_pkts",
398 "tx_do_cksum",
399
400 "espi_DIP2ParityErr", 414 "espi_DIP2ParityErr",
401 "espi_DIP4Err", 415 "espi_DIP4Err",
402 "espi_RxDrops", 416 "espi_RxDrops",
@@ -404,7 +418,7 @@ static char stats_strings[][ETH_GSTRING_LEN] = {
404 "espi_RxOvfl", 418 "espi_RxOvfl",
405 "espi_ParityErr" 419 "espi_ParityErr"
406}; 420};
407 421
408#define T2_REGMAP_SIZE (3 * 1024) 422#define T2_REGMAP_SIZE (3 * 1024)
409 423
410static int get_regs_len(struct net_device *dev) 424static int get_regs_len(struct net_device *dev)
@@ -439,65 +453,77 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
439 struct adapter *adapter = dev->priv; 453 struct adapter *adapter = dev->priv;
440 struct cmac *mac = adapter->port[dev->if_port].mac; 454 struct cmac *mac = adapter->port[dev->if_port].mac;
441 const struct cmac_statistics *s; 455 const struct cmac_statistics *s;
442 const struct sge_port_stats *ss;
443 const struct sge_intr_counts *t; 456 const struct sge_intr_counts *t;
457 struct sge_port_stats ss;
444 458
445 s = mac->ops->statistics_update(mac, MAC_STATS_UPDATE_FULL); 459 s = mac->ops->statistics_update(mac, MAC_STATS_UPDATE_FULL);
446 ss = t1_sge_get_port_stats(adapter->sge, dev->if_port);
447 t = t1_sge_get_intr_counts(adapter->sge);
448 460
449 *data++ = s->TxOctetsOK; 461 *data++ = s->TxOctetsOK;
450 *data++ = s->TxOctetsBad; 462 *data++ = s->TxOctetsBad;
451 *data++ = s->TxUnicastFramesOK; 463 *data++ = s->TxUnicastFramesOK;
452 *data++ = s->TxMulticastFramesOK; 464 *data++ = s->TxMulticastFramesOK;
453 *data++ = s->TxBroadcastFramesOK; 465 *data++ = s->TxBroadcastFramesOK;
454 *data++ = s->TxPauseFrames; 466 *data++ = s->TxPauseFrames;
455 *data++ = s->TxFramesWithDeferredXmissions; 467 *data++ = s->TxFramesWithDeferredXmissions;
456 *data++ = s->TxLateCollisions; 468 *data++ = s->TxLateCollisions;
457 *data++ = s->TxTotalCollisions; 469 *data++ = s->TxTotalCollisions;
458 *data++ = s->TxFramesAbortedDueToXSCollisions; 470 *data++ = s->TxFramesAbortedDueToXSCollisions;
459 *data++ = s->TxUnderrun; 471 *data++ = s->TxUnderrun;
460 *data++ = s->TxLengthErrors; 472 *data++ = s->TxLengthErrors;
461 *data++ = s->TxInternalMACXmitError; 473 *data++ = s->TxInternalMACXmitError;
462 *data++ = s->TxFramesWithExcessiveDeferral; 474 *data++ = s->TxFramesWithExcessiveDeferral;
463 *data++ = s->TxFCSErrors; 475 *data++ = s->TxFCSErrors;
464 476
465 *data++ = s->RxOctetsOK; 477 *data++ = s->RxOctetsOK;
466 *data++ = s->RxOctetsBad; 478 *data++ = s->RxOctetsBad;
467 *data++ = s->RxUnicastFramesOK; 479 *data++ = s->RxUnicastFramesOK;
468 *data++ = s->RxMulticastFramesOK; 480 *data++ = s->RxMulticastFramesOK;
469 *data++ = s->RxBroadcastFramesOK; 481 *data++ = s->RxBroadcastFramesOK;
470 *data++ = s->RxPauseFrames; 482 *data++ = s->RxPauseFrames;
471 *data++ = s->RxFCSErrors; 483 *data++ = s->RxFCSErrors;
472 *data++ = s->RxAlignErrors; 484 *data++ = s->RxAlignErrors;
473 *data++ = s->RxSymbolErrors; 485 *data++ = s->RxSymbolErrors;
474 *data++ = s->RxDataErrors; 486 *data++ = s->RxDataErrors;
475 *data++ = s->RxSequenceErrors; 487 *data++ = s->RxSequenceErrors;
476 *data++ = s->RxRuntErrors; 488 *data++ = s->RxRuntErrors;
477 *data++ = s->RxJabberErrors; 489 *data++ = s->RxJabberErrors;
478 *data++ = s->RxInternalMACRcvError; 490 *data++ = s->RxInternalMACRcvError;
479 *data++ = s->RxInRangeLengthErrors; 491 *data++ = s->RxInRangeLengthErrors;
480 *data++ = s->RxOutOfRangeLengthField; 492 *data++ = s->RxOutOfRangeLengthField;
481 *data++ = s->RxFrameTooLongErrors; 493 *data++ = s->RxFrameTooLongErrors;
482 494
483 *data++ = ss->tso; 495 t1_sge_get_port_stats(adapter->sge, dev->if_port, &ss);
484 *data++ = ss->vlan_xtract; 496 *data++ = ss.rx_packets;
485 *data++ = ss->vlan_insert; 497 *data++ = ss.rx_cso_good;
486 *data++ = ss->rx_cso_good; 498 *data++ = ss.tx_packets;
487 *data++ = ss->tx_cso; 499 *data++ = ss.tx_cso;
488 *data++ = ss->rx_drops; 500 *data++ = ss.tx_tso;
489 501 *data++ = ss.vlan_xtract;
490 *data++ = (u64)t->respQ_empty; 502 *data++ = ss.vlan_insert;
491 *data++ = (u64)t->respQ_overflow; 503
492 *data++ = (u64)t->freelistQ_empty; 504 t = t1_sge_get_intr_counts(adapter->sge);
493 *data++ = (u64)t->pkt_too_big; 505 *data++ = t->rx_drops;
494 *data++ = (u64)t->pkt_mismatch; 506 *data++ = t->pure_rsps;
495 *data++ = (u64)t->cmdQ_full[0]; 507 *data++ = t->unhandled_irqs;
496 *data++ = (u64)t->cmdQ_full[1]; 508 *data++ = t->respQ_empty;
497 *data++ = (u64)t->tx_ipfrags; 509 *data++ = t->respQ_overflow;
498 *data++ = (u64)t->tx_reg_pkts; 510 *data++ = t->freelistQ_empty;
499 *data++ = (u64)t->tx_lso_pkts; 511 *data++ = t->pkt_too_big;
500 *data++ = (u64)t->tx_do_cksum; 512 *data++ = t->pkt_mismatch;
513 *data++ = t->cmdQ_full[0];
514 *data++ = t->cmdQ_full[1];
515
516 if (adapter->espi) {
517 const struct espi_intr_counts *e;
518
519 e = t1_espi_get_intr_counts(adapter->espi);
520 *data++ = e->DIP2_parity_err;
521 *data++ = e->DIP4_err;
522 *data++ = e->rx_drops;
523 *data++ = e->tx_drops;
524 *data++ = e->rx_ovflw;
525 *data++ = e->parity_err;
526 }
501} 527}
502 528
503static inline void reg_block_dump(struct adapter *ap, void *buf, 529static inline void reg_block_dump(struct adapter *ap, void *buf,
@@ -521,6 +547,15 @@ static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
521 547
522 memset(buf, 0, T2_REGMAP_SIZE); 548 memset(buf, 0, T2_REGMAP_SIZE);
523 reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER); 549 reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER);
550 reg_block_dump(ap, buf, A_MC3_CFG, A_MC4_INT_CAUSE);
551 reg_block_dump(ap, buf, A_TPI_ADDR, A_TPI_PAR);
552 reg_block_dump(ap, buf, A_TP_IN_CONFIG, A_TP_TX_DROP_COUNT);
553 reg_block_dump(ap, buf, A_RAT_ROUTE_CONTROL, A_RAT_INTR_CAUSE);
554 reg_block_dump(ap, buf, A_CSPI_RX_AE_WM, A_CSPI_INTR_ENABLE);
555 reg_block_dump(ap, buf, A_ESPI_SCH_TOKEN0, A_ESPI_GOSTAT);
556 reg_block_dump(ap, buf, A_ULP_ULIMIT, A_ULP_PIO_CTRL);
557 reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE);
558 reg_block_dump(ap, buf, A_MC5_CONFIG, A_MC5_MASK_WRITE_CMD);
524} 559}
525 560
526static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 561static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
@@ -539,12 +574,12 @@ static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
539 cmd->duplex = -1; 574 cmd->duplex = -1;
540 } 575 }
541 576
542 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE; 577 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
543 cmd->phy_address = p->phy->addr; 578 cmd->phy_address = p->phy->addr;
544 cmd->transceiver = XCVR_EXTERNAL; 579 cmd->transceiver = XCVR_EXTERNAL;
545 cmd->autoneg = p->link_config.autoneg; 580 cmd->autoneg = p->link_config.autoneg;
546 cmd->maxtxpkt = 0; 581 cmd->maxtxpkt = 0;
547 cmd->maxrxpkt = 0; 582 cmd->maxrxpkt = 0;
548 return 0; 583 return 0;
549} 584}
550 585
@@ -715,7 +750,7 @@ static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
715 return -EINVAL; 750 return -EINVAL;
716 751
717 if (adapter->flags & FULL_INIT_DONE) 752 if (adapter->flags & FULL_INIT_DONE)
718 return -EBUSY; 753 return -EBUSY;
719 754
720 adapter->params.sge.freelQ_size[!jumbo_fl] = e->rx_pending; 755 adapter->params.sge.freelQ_size[!jumbo_fl] = e->rx_pending;
721 adapter->params.sge.freelQ_size[jumbo_fl] = e->rx_jumbo_pending; 756 adapter->params.sge.freelQ_size[jumbo_fl] = e->rx_jumbo_pending;
@@ -759,7 +794,9 @@ static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
759 794
760static int get_eeprom_len(struct net_device *dev) 795static int get_eeprom_len(struct net_device *dev)
761{ 796{
762 return EEPROM_SIZE; 797 struct adapter *adapter = dev->priv;
798
799 return t1_is_asic(adapter) ? EEPROM_SIZE : 0;
763} 800}
764 801
765#define EEPROM_MAGIC(ap) \ 802#define EEPROM_MAGIC(ap) \
@@ -809,47 +846,36 @@ static const struct ethtool_ops t1_ethtool_ops = {
809 .set_tso = set_tso, 846 .set_tso = set_tso,
810}; 847};
811 848
812static void cxgb_proc_cleanup(struct adapter *adapter,
813 struct proc_dir_entry *dir)
814{
815 const char *name;
816 name = adapter->name;
817 remove_proc_entry(name, dir);
818}
819//#define chtoe_setup_toedev(adapter) NULL
820#define update_mtu_tab(adapter)
821#define write_smt_entry(adapter, idx)
822
823static int t1_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 849static int t1_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
824{ 850{
825 struct adapter *adapter = dev->priv; 851 struct adapter *adapter = dev->priv;
826 struct mii_ioctl_data *data = if_mii(req); 852 struct mii_ioctl_data *data = if_mii(req);
827 853
828 switch (cmd) { 854 switch (cmd) {
829 case SIOCGMIIPHY: 855 case SIOCGMIIPHY:
830 data->phy_id = adapter->port[dev->if_port].phy->addr; 856 data->phy_id = adapter->port[dev->if_port].phy->addr;
831 /* FALLTHRU */ 857 /* FALLTHRU */
832 case SIOCGMIIREG: { 858 case SIOCGMIIREG: {
833 struct cphy *phy = adapter->port[dev->if_port].phy; 859 struct cphy *phy = adapter->port[dev->if_port].phy;
834 u32 val; 860 u32 val;
835 861
836 if (!phy->mdio_read) 862 if (!phy->mdio_read)
837 return -EOPNOTSUPP; 863 return -EOPNOTSUPP;
838 phy->mdio_read(adapter, data->phy_id, 0, data->reg_num & 0x1f, 864 phy->mdio_read(adapter, data->phy_id, 0, data->reg_num & 0x1f,
839 &val); 865 &val);
840 data->val_out = val; 866 data->val_out = val;
841 break; 867 break;
842 } 868 }
843 case SIOCSMIIREG: { 869 case SIOCSMIIREG: {
844 struct cphy *phy = adapter->port[dev->if_port].phy; 870 struct cphy *phy = adapter->port[dev->if_port].phy;
845 871
846 if (!capable(CAP_NET_ADMIN)) 872 if (!capable(CAP_NET_ADMIN))
847 return -EPERM; 873 return -EPERM;
848 if (!phy->mdio_write) 874 if (!phy->mdio_write)
849 return -EOPNOTSUPP; 875 return -EOPNOTSUPP;
850 phy->mdio_write(adapter, data->phy_id, 0, data->reg_num & 0x1f, 876 phy->mdio_write(adapter, data->phy_id, 0, data->reg_num & 0x1f,
851 data->val_in); 877 data->val_in);
852 break; 878 break;
853 } 879 }
854 880
855 default: 881 default:
@@ -865,9 +891,9 @@ static int t1_change_mtu(struct net_device *dev, int new_mtu)
865 struct cmac *mac = adapter->port[dev->if_port].mac; 891 struct cmac *mac = adapter->port[dev->if_port].mac;
866 892
867 if (!mac->ops->set_mtu) 893 if (!mac->ops->set_mtu)
868 return -EOPNOTSUPP; 894 return -EOPNOTSUPP;
869 if (new_mtu < 68) 895 if (new_mtu < 68)
870 return -EINVAL; 896 return -EINVAL;
871 if ((ret = mac->ops->set_mtu(mac, new_mtu))) 897 if ((ret = mac->ops->set_mtu(mac, new_mtu)))
872 return ret; 898 return ret;
873 dev->mtu = new_mtu; 899 dev->mtu = new_mtu;
@@ -918,7 +944,7 @@ static void t1_netpoll(struct net_device *dev)
918 struct adapter *adapter = dev->priv; 944 struct adapter *adapter = dev->priv;
919 945
920 local_irq_save(flags); 946 local_irq_save(flags);
921 t1_select_intr_handler(adapter)(adapter->pdev->irq, adapter); 947 t1_select_intr_handler(adapter)(adapter->pdev->irq, adapter);
922 local_irq_restore(flags); 948 local_irq_restore(flags);
923} 949}
924#endif 950#endif
@@ -957,14 +983,14 @@ static void ext_intr_task(struct work_struct *work)
957 struct adapter *adapter = 983 struct adapter *adapter =
958 container_of(work, struct adapter, ext_intr_handler_task); 984 container_of(work, struct adapter, ext_intr_handler_task);
959 985
960 elmer0_ext_intr_handler(adapter); 986 t1_elmer0_ext_intr_handler(adapter);
961 987
962 /* Now reenable external interrupts */ 988 /* Now reenable external interrupts */
963 spin_lock_irq(&adapter->async_lock); 989 spin_lock_irq(&adapter->async_lock);
964 adapter->slow_intr_mask |= F_PL_INTR_EXT; 990 adapter->slow_intr_mask |= F_PL_INTR_EXT;
965 writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE); 991 writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE);
966 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, 992 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
967 adapter->regs + A_PL_ENABLE); 993 adapter->regs + A_PL_ENABLE);
968 spin_unlock_irq(&adapter->async_lock); 994 spin_unlock_irq(&adapter->async_lock);
969} 995}
970 996
@@ -980,7 +1006,7 @@ void t1_elmer0_ext_intr(struct adapter *adapter)
980 */ 1006 */
981 adapter->slow_intr_mask &= ~F_PL_INTR_EXT; 1007 adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
982 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, 1008 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
983 adapter->regs + A_PL_ENABLE); 1009 adapter->regs + A_PL_ENABLE);
984 schedule_work(&adapter->ext_intr_handler_task); 1010 schedule_work(&adapter->ext_intr_handler_task);
985} 1011}
986 1012
@@ -1013,7 +1039,7 @@ static int __devinit init_one(struct pci_dev *pdev,
1013 1039
1014 err = pci_enable_device(pdev); 1040 err = pci_enable_device(pdev);
1015 if (err) 1041 if (err)
1016 return err; 1042 return err;
1017 1043
1018 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 1044 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1019 CH_ERR("%s: cannot find PCI device memory base address\n", 1045 CH_ERR("%s: cannot find PCI device memory base address\n",
@@ -1045,7 +1071,7 @@ static int __devinit init_one(struct pci_dev *pdev,
1045 1071
1046 pci_set_master(pdev); 1072 pci_set_master(pdev);
1047 1073
1048 mmio_start = pci_resource_start(pdev, 0); 1074 mmio_start = pci_resource_start(pdev, 0);
1049 mmio_len = pci_resource_len(pdev, 0); 1075 mmio_len = pci_resource_len(pdev, 0);
1050 bi = t1_get_board_info(ent->driver_data); 1076 bi = t1_get_board_info(ent->driver_data);
1051 1077
@@ -1083,21 +1109,15 @@ static int __devinit init_one(struct pci_dev *pdev,
1083 adapter->msg_enable = dflt_msg_enable; 1109 adapter->msg_enable = dflt_msg_enable;
1084 adapter->mmio_len = mmio_len; 1110 adapter->mmio_len = mmio_len;
1085 1111
1086 init_MUTEX(&adapter->mib_mutex);
1087 spin_lock_init(&adapter->tpi_lock); 1112 spin_lock_init(&adapter->tpi_lock);
1088 spin_lock_init(&adapter->work_lock); 1113 spin_lock_init(&adapter->work_lock);
1089 spin_lock_init(&adapter->async_lock); 1114 spin_lock_init(&adapter->async_lock);
1115 spin_lock_init(&adapter->mac_lock);
1090 1116
1091 INIT_WORK(&adapter->ext_intr_handler_task, 1117 INIT_WORK(&adapter->ext_intr_handler_task,
1092 ext_intr_task); 1118 ext_intr_task);
1093 INIT_DELAYED_WORK(&adapter->stats_update_task, 1119 INIT_DELAYED_WORK(&adapter->stats_update_task,
1094 mac_stats_task); 1120 mac_stats_task);
1095#ifdef work_struct
1096 init_timer(&adapter->stats_update_timer);
1097 adapter->stats_update_timer.function = mac_stats_timer;
1098 adapter->stats_update_timer.data =
1099 (unsigned long)adapter;
1100#endif
1101 1121
1102 pci_set_drvdata(pdev, netdev); 1122 pci_set_drvdata(pdev, netdev);
1103 } 1123 }
@@ -1124,16 +1144,19 @@ static int __devinit init_one(struct pci_dev *pdev,
1124 netdev->vlan_rx_register = vlan_rx_register; 1144 netdev->vlan_rx_register = vlan_rx_register;
1125 netdev->vlan_rx_kill_vid = vlan_rx_kill_vid; 1145 netdev->vlan_rx_kill_vid = vlan_rx_kill_vid;
1126#endif 1146#endif
1127 adapter->flags |= TSO_CAPABLE; 1147
1128 netdev->features |= NETIF_F_TSO; 1148 /* T204: disable TSO */
1149 if (!(is_T2(adapter)) || bi->port_number != 4) {
1150 adapter->flags |= TSO_CAPABLE;
1151 netdev->features |= NETIF_F_TSO;
1152 }
1129 } 1153 }
1130 1154
1131 netdev->open = cxgb_open; 1155 netdev->open = cxgb_open;
1132 netdev->stop = cxgb_close; 1156 netdev->stop = cxgb_close;
1133 netdev->hard_start_xmit = t1_start_xmit; 1157 netdev->hard_start_xmit = t1_start_xmit;
1134 netdev->hard_header_len += (adapter->flags & TSO_CAPABLE) ? 1158 netdev->hard_header_len += (adapter->flags & TSO_CAPABLE) ?
1135 sizeof(struct cpl_tx_pkt_lso) : 1159 sizeof(struct cpl_tx_pkt_lso) : sizeof(struct cpl_tx_pkt);
1136 sizeof(struct cpl_tx_pkt);
1137 netdev->get_stats = t1_get_stats; 1160 netdev->get_stats = t1_get_stats;
1138 netdev->set_multicast_list = t1_set_rxmode; 1161 netdev->set_multicast_list = t1_set_rxmode;
1139 netdev->do_ioctl = t1_ioctl; 1162 netdev->do_ioctl = t1_ioctl;
@@ -1144,7 +1167,7 @@ static int __devinit init_one(struct pci_dev *pdev,
1144#endif 1167#endif
1145 netdev->weight = 64; 1168 netdev->weight = 64;
1146 1169
1147 SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops); 1170 SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops);
1148 } 1171 }
1149 1172
1150 if (t1_init_sw_modules(adapter, bi) < 0) { 1173 if (t1_init_sw_modules(adapter, bi) < 0) {
@@ -1171,7 +1194,7 @@ static int __devinit init_one(struct pci_dev *pdev,
1171 if (!adapter->registered_device_map) 1194 if (!adapter->registered_device_map)
1172 adapter->name = adapter->port[i].dev->name; 1195 adapter->name = adapter->port[i].dev->name;
1173 1196
1174 __set_bit(i, &adapter->registered_device_map); 1197 __set_bit(i, &adapter->registered_device_map);
1175 } 1198 }
1176 } 1199 }
1177 if (!adapter->registered_device_map) { 1200 if (!adapter->registered_device_map) {
@@ -1184,18 +1207,28 @@ static int __devinit init_one(struct pci_dev *pdev,
1184 bi->desc, adapter->params.chip_revision, 1207 bi->desc, adapter->params.chip_revision,
1185 adapter->params.pci.is_pcix ? "PCIX" : "PCI", 1208 adapter->params.pci.is_pcix ? "PCIX" : "PCI",
1186 adapter->params.pci.speed, adapter->params.pci.width); 1209 adapter->params.pci.speed, adapter->params.pci.width);
1210
1211 /*
1212 * Set the T1B ASIC and memory clocks.
1213 */
1214 if (t1powersave)
1215 adapter->t1powersave = LCLOCK; /* HW default is powersave mode. */
1216 else
1217 adapter->t1powersave = HCLOCK;
1218 if (t1_is_T1B(adapter))
1219 t1_clock(adapter, t1powersave);
1220
1187 return 0; 1221 return 0;
1188 1222
1189 out_release_adapter_res: 1223 out_release_adapter_res:
1190 t1_free_sw_modules(adapter); 1224 t1_free_sw_modules(adapter);
1191 out_free_dev: 1225 out_free_dev:
1192 if (adapter) { 1226 if (adapter) {
1193 if (adapter->regs) iounmap(adapter->regs); 1227 if (adapter->regs)
1228 iounmap(adapter->regs);
1194 for (i = bi->port_number - 1; i >= 0; --i) 1229 for (i = bi->port_number - 1; i >= 0; --i)
1195 if (adapter->port[i].dev) { 1230 if (adapter->port[i].dev)
1196 cxgb_proc_cleanup(adapter, proc_root_driver); 1231 free_netdev(adapter->port[i].dev);
1197 kfree(adapter->port[i].dev);
1198 }
1199 } 1232 }
1200 pci_release_regions(pdev); 1233 pci_release_regions(pdev);
1201 out_disable_pdev: 1234 out_disable_pdev:
@@ -1204,6 +1237,155 @@ static int __devinit init_one(struct pci_dev *pdev,
1204 return err; 1237 return err;
1205} 1238}
1206 1239
1240static void bit_bang(struct adapter *adapter, int bitdata, int nbits)
1241{
1242 int data;
1243 int i;
1244 u32 val;
1245
1246 enum {
1247 S_CLOCK = 1 << 3,
1248 S_DATA = 1 << 4
1249 };
1250
1251 for (i = (nbits - 1); i > -1; i--) {
1252
1253 udelay(50);
1254
1255 data = ((bitdata >> i) & 0x1);
1256 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1257
1258 if (data)
1259 val |= S_DATA;
1260 else
1261 val &= ~S_DATA;
1262
1263 udelay(50);
1264
1265 /* Set SCLOCK low */
1266 val &= ~S_CLOCK;
1267 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1268
1269 udelay(50);
1270
1271 /* Write SCLOCK high */
1272 val |= S_CLOCK;
1273 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1274
1275 }
1276}
1277
1278static int t1_clock(struct adapter *adapter, int mode)
1279{
1280 u32 val;
1281 int M_CORE_VAL;
1282 int M_MEM_VAL;
1283
1284 enum {
1285 M_CORE_BITS = 9,
1286 T_CORE_VAL = 0,
1287 T_CORE_BITS = 2,
1288 N_CORE_VAL = 0,
1289 N_CORE_BITS = 2,
1290 M_MEM_BITS = 9,
1291 T_MEM_VAL = 0,
1292 T_MEM_BITS = 2,
1293 N_MEM_VAL = 0,
1294 N_MEM_BITS = 2,
1295 NP_LOAD = 1 << 17,
1296 S_LOAD_MEM = 1 << 5,
1297 S_LOAD_CORE = 1 << 6,
1298 S_CLOCK = 1 << 3
1299 };
1300
1301 if (!t1_is_T1B(adapter))
1302 return -ENODEV; /* Can't re-clock this chip. */
1303
1304 if (mode & 2) {
1305 return 0; /* show current mode. */
1306 }
1307
1308 if ((adapter->t1powersave & 1) == (mode & 1))
1309 return -EALREADY; /* ASIC already running in mode. */
1310
1311 if ((mode & 1) == HCLOCK) {
1312 M_CORE_VAL = 0x14;
1313 M_MEM_VAL = 0x18;
1314 adapter->t1powersave = HCLOCK; /* overclock */
1315 } else {
1316 M_CORE_VAL = 0xe;
1317 M_MEM_VAL = 0x10;
1318 adapter->t1powersave = LCLOCK; /* underclock */
1319 }
1320
1321 /* Don't interrupt this serial stream! */
1322 spin_lock(&adapter->tpi_lock);
1323
1324 /* Initialize for ASIC core */
1325 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1326 val |= NP_LOAD;
1327 udelay(50);
1328 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1329 udelay(50);
1330 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1331 val &= ~S_LOAD_CORE;
1332 val &= ~S_CLOCK;
1333 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1334 udelay(50);
1335
1336 /* Serial program the ASIC clock synthesizer */
1337 bit_bang(adapter, T_CORE_VAL, T_CORE_BITS);
1338 bit_bang(adapter, N_CORE_VAL, N_CORE_BITS);
1339 bit_bang(adapter, M_CORE_VAL, M_CORE_BITS);
1340 udelay(50);
1341
1342 /* Finish ASIC core */
1343 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1344 val |= S_LOAD_CORE;
1345 udelay(50);
1346 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1347 udelay(50);
1348 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1349 val &= ~S_LOAD_CORE;
1350 udelay(50);
1351 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1352 udelay(50);
1353
1354 /* Initialize for memory */
1355 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1356 val |= NP_LOAD;
1357 udelay(50);
1358 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1359 udelay(50);
1360 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1361 val &= ~S_LOAD_MEM;
1362 val &= ~S_CLOCK;
1363 udelay(50);
1364 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1365 udelay(50);
1366
1367 /* Serial program the memory clock synthesizer */
1368 bit_bang(adapter, T_MEM_VAL, T_MEM_BITS);
1369 bit_bang(adapter, N_MEM_VAL, N_MEM_BITS);
1370 bit_bang(adapter, M_MEM_VAL, M_MEM_BITS);
1371 udelay(50);
1372
1373 /* Finish memory */
1374 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1375 val |= S_LOAD_MEM;
1376 udelay(50);
1377 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1378 udelay(50);
1379 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1380 val &= ~S_LOAD_MEM;
1381 udelay(50);
1382 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1383
1384 spin_unlock(&adapter->tpi_lock);
1385
1386 return 0;
1387}
1388
1207static inline void t1_sw_reset(struct pci_dev *pdev) 1389static inline void t1_sw_reset(struct pci_dev *pdev)
1208{ 1390{
1209 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3); 1391 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3);
@@ -1225,10 +1407,9 @@ static void __devexit remove_one(struct pci_dev *pdev)
1225 t1_free_sw_modules(adapter); 1407 t1_free_sw_modules(adapter);
1226 iounmap(adapter->regs); 1408 iounmap(adapter->regs);
1227 while (--i >= 0) 1409 while (--i >= 0)
1228 if (adapter->port[i].dev) { 1410 if (adapter->port[i].dev)
1229 cxgb_proc_cleanup(adapter, proc_root_driver); 1411 free_netdev(adapter->port[i].dev);
1230 kfree(adapter->port[i].dev); 1412
1231 }
1232 pci_release_regions(pdev); 1413 pci_release_regions(pdev);
1233 pci_disable_device(pdev); 1414 pci_disable_device(pdev);
1234 pci_set_drvdata(pdev, NULL); 1415 pci_set_drvdata(pdev, NULL);
diff --git a/drivers/net/chelsio/elmer0.h b/drivers/net/chelsio/elmer0.h
index 5590cb2dac19..9ebecaa97d31 100644
--- a/drivers/net/chelsio/elmer0.h
+++ b/drivers/net/chelsio/elmer0.h
@@ -39,6 +39,12 @@
39#ifndef _CXGB_ELMER0_H_ 39#ifndef _CXGB_ELMER0_H_
40#define _CXGB_ELMER0_H_ 40#define _CXGB_ELMER0_H_
41 41
42/* ELMER0 flavors */
43enum {
44 ELMER0_XC2S300E_6FT256_C,
45 ELMER0_XC2S100E_6TQ144_C
46};
47
42/* ELMER0 registers */ 48/* ELMER0 registers */
43#define A_ELMER0_VERSION 0x100000 49#define A_ELMER0_VERSION 0x100000
44#define A_ELMER0_PHY_CFG 0x100004 50#define A_ELMER0_PHY_CFG 0x100004
@@ -149,3 +155,4 @@
149#define MI1_OP_INDIRECT_READ 3 155#define MI1_OP_INDIRECT_READ 3
150 156
151#endif /* _CXGB_ELMER0_H_ */ 157#endif /* _CXGB_ELMER0_H_ */
158
diff --git a/drivers/net/chelsio/espi.c b/drivers/net/chelsio/espi.c
index 542e5e065c6f..4192f0f5b3ee 100644
--- a/drivers/net/chelsio/espi.c
+++ b/drivers/net/chelsio/espi.c
@@ -81,46 +81,36 @@ static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
81 return busy; 81 return busy;
82} 82}
83 83
84/* 1. Deassert rx_reset_core. */
85/* 2. Program TRICN_CNFG registers. */
86/* 3. Deassert rx_reset_link */
87static int tricn_init(adapter_t *adapter) 84static int tricn_init(adapter_t *adapter)
88{ 85{
89 int i = 0; 86 int i, sme = 1;
90 int stat = 0;
91 int timeout = 0;
92 int is_ready = 0;
93 87
94 /* 1 */ 88 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
95 timeout=1000; 89 CH_ERR("%s: ESPI clock not ready\n", adapter->name);
96 do { 90 return -1;
97 stat = readl(adapter->regs + A_ESPI_RX_RESET);
98 is_ready = (stat & 0x4);
99 timeout--;
100 udelay(5);
101 } while (!is_ready || (timeout==0));
102 writel(0x2, adapter->regs + A_ESPI_RX_RESET);
103 if (timeout==0)
104 {
105 CH_ERR("ESPI : ERROR : Timeout tricn_init() \n");
106 t1_fatal_err(adapter);
107 } 91 }
108 92
109 /* 2 */ 93 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
110 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); 94
111 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); 95 if (sme) {
112 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); 96 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
113 for (i=1; i<= 8; i++) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); 97 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
114 for (i=1; i<= 2; i++) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); 98 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
115 for (i=1; i<= 3; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); 99 }
116 for (i=4; i<= 4; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1); 100 for (i = 1; i <= 8; i++)
117 for (i=5; i<= 5; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); 101 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
118 for (i=6; i<= 6; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1); 102 for (i = 1; i <= 2; i++)
119 for (i=7; i<= 7; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0x80); 103 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
120 for (i=8; i<= 8; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1); 104 for (i = 1; i <= 3; i++)
121 105 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
122 /* 3 */ 106 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
123 writel(0x3, adapter->regs + A_ESPI_RX_RESET); 107 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
108 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
109 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
110 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
111
112 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST,
113 adapter->regs + A_ESPI_RX_RESET);
124 114
125 return 0; 115 return 0;
126} 116}
@@ -143,6 +133,7 @@ void t1_espi_intr_enable(struct peespi *espi)
143 133
144void t1_espi_intr_clear(struct peespi *espi) 134void t1_espi_intr_clear(struct peespi *espi)
145{ 135{
136 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
146 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); 137 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
147 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); 138 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
148} 139}
@@ -157,7 +148,6 @@ void t1_espi_intr_disable(struct peespi *espi)
157 148
158int t1_espi_intr_handler(struct peespi *espi) 149int t1_espi_intr_handler(struct peespi *espi)
159{ 150{
160 u32 cnt;
161 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); 151 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
162 152
163 if (status & F_DIP4ERR) 153 if (status & F_DIP4ERR)
@@ -177,7 +167,7 @@ int t1_espi_intr_handler(struct peespi *espi)
177 * Must read the error count to clear the interrupt 167 * Must read the error count to clear the interrupt
178 * that it causes. 168 * that it causes.
179 */ 169 */
180 cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); 170 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
181 } 171 }
182 172
183 /* 173 /*
@@ -192,7 +182,7 @@ int t1_espi_intr_handler(struct peespi *espi)
192 182
193const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi) 183const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
194{ 184{
195 return &espi->intr_cnt; 185 return &espi->intr_cnt;
196} 186}
197 187
198static void espi_setup_for_pm3393(adapter_t *adapter) 188static void espi_setup_for_pm3393(adapter_t *adapter)
@@ -210,17 +200,45 @@ static void espi_setup_for_pm3393(adapter_t *adapter)
210 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); 200 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
211} 201}
212 202
213/* T2 Init part -- */ 203static void espi_setup_for_vsc7321(adapter_t *adapter)
214/* 1. Set T_ESPI_MISCCTRL_ADDR */ 204{
215/* 2. Init ESPI registers. */ 205 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
216/* 3. Init TriCN Hard Macro */ 206 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
217int t1_espi_init(struct peespi *espi, int mac_type, int nports) 207 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
208 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
209 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
210 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
211 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
212
213 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
214}
215
216/*
217 * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
218 */
219static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
218{ 220{
219 u32 cnt; 221 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
222 if (nports == 4) {
223 if (is_T2(adapter)) {
224 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
225 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
226 } else {
227 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
228 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
229 }
230 } else {
231 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
232 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
233 }
234 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
220 235
236}
237
238int t1_espi_init(struct peespi *espi, int mac_type, int nports)
239{
221 u32 status_enable_extra = 0; 240 u32 status_enable_extra = 0;
222 adapter_t *adapter = espi->adapter; 241 adapter_t *adapter = espi->adapter;
223 u32 status, burstval = 0x800100;
224 242
225 /* Disable ESPI training. MACs that can handle it enable it below. */ 243 /* Disable ESPI training. MACs that can handle it enable it below. */
226 writel(0, adapter->regs + A_ESPI_TRAIN); 244 writel(0, adapter->regs + A_ESPI_TRAIN);
@@ -229,38 +247,20 @@ int t1_espi_init(struct peespi *espi, int mac_type, int nports)
229 writel(V_OUT_OF_SYNC_COUNT(4) | 247 writel(V_OUT_OF_SYNC_COUNT(4) |
230 V_DIP2_PARITY_ERR_THRES(3) | 248 V_DIP2_PARITY_ERR_THRES(3) |
231 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); 249 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
232 if (nports == 4) { 250 writel(nports == 4 ? 0x200040 : 0x1000080,
233 /* T204: maxburst1 = 0x40, maxburst2 = 0x20 */ 251 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
234 burstval = 0x200040; 252 } else
235 } 253 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
236 }
237 writel(burstval, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
238 254
239 switch (mac_type) { 255 if (mac_type == CHBT_MAC_PM3393)
240 case CHBT_MAC_PM3393:
241 espi_setup_for_pm3393(adapter); 256 espi_setup_for_pm3393(adapter);
242 break; 257 else if (mac_type == CHBT_MAC_VSC7321)
243 default: 258 espi_setup_for_vsc7321(adapter);
259 else if (mac_type == CHBT_MAC_IXF1010) {
260 status_enable_extra = F_INTEL1010MODE;
261 espi_setup_for_ixf1010(adapter, nports);
262 } else
244 return -1; 263 return -1;
245 }
246
247 /*
248 * Make sure any pending interrupts from the SPI are
249 * Cleared before enabling the interrupt.
250 */
251 writel(ESPI_INTR_MASK, espi->adapter->regs + A_ESPI_INTR_ENABLE);
252 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
253 if (status & F_DIP2PARITYERR) {
254 cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
255 }
256
257 /*
258 * For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
259 * write the status as is.
260 */
261 if (status && t1_is_T1B(espi->adapter))
262 status = 1;
263 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
264 264
265 writel(status_enable_extra | F_RXSTATUSENABLE, 265 writel(status_enable_extra | F_RXSTATUSENABLE,
266 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); 266 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
@@ -271,9 +271,11 @@ int t1_espi_init(struct peespi *espi, int mac_type, int nports)
271 * Always position the control at the 1st port egress IN 271 * Always position the control at the 1st port egress IN
272 * (sop,eop) counter to reduce PIOs for T/N210 workaround. 272 * (sop,eop) counter to reduce PIOs for T/N210 workaround.
273 */ 273 */
274 espi->misc_ctrl = (readl(adapter->regs + A_ESPI_MISC_CONTROL) 274 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL);
275 & ~MON_MASK) | (F_MONITORED_DIRECTION 275 espi->misc_ctrl &= ~MON_MASK;
276 | F_MONITORED_INTERFACE); 276 espi->misc_ctrl |= F_MONITORED_DIRECTION;
277 if (adapter->params.nports == 1)
278 espi->misc_ctrl |= F_MONITORED_INTERFACE;
277 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); 279 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
278 spin_lock_init(&espi->lock); 280 spin_lock_init(&espi->lock);
279 } 281 }
@@ -299,8 +301,7 @@ void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
299{ 301{
300 struct peespi *espi = adapter->espi; 302 struct peespi *espi = adapter->espi;
301 303
302 if (!is_T2(adapter)) 304 if (!is_T2(adapter)) return;
303 return;
304 spin_lock(&espi->lock); 305 spin_lock(&espi->lock);
305 espi->misc_ctrl = (val & ~MON_MASK) | 306 espi->misc_ctrl = (val & ~MON_MASK) |
306 (espi->misc_ctrl & MON_MASK); 307 (espi->misc_ctrl & MON_MASK);
@@ -310,27 +311,61 @@ void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
310 311
311u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) 312u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
312{ 313{
313 u32 sel;
314
315 struct peespi *espi = adapter->espi; 314 struct peespi *espi = adapter->espi;
315 u32 sel;
316 316
317 if (!is_T2(adapter)) 317 if (!is_T2(adapter))
318 return 0; 318 return 0;
319
319 sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2); 320 sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
320 if (!wait) { 321 if (!wait) {
321 if (!spin_trylock(&espi->lock)) 322 if (!spin_trylock(&espi->lock))
322 return 0; 323 return 0;
323 } 324 } else
324 else
325 spin_lock(&espi->lock); 325 spin_lock(&espi->lock);
326
326 if ((sel != (espi->misc_ctrl & MON_MASK))) { 327 if ((sel != (espi->misc_ctrl & MON_MASK))) {
327 writel(((espi->misc_ctrl & ~MON_MASK) | sel), 328 writel(((espi->misc_ctrl & ~MON_MASK) | sel),
328 adapter->regs + A_ESPI_MISC_CONTROL); 329 adapter->regs + A_ESPI_MISC_CONTROL);
329 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); 330 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
330 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); 331 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
331 } 332 } else
332 else
333 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); 333 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
334 spin_unlock(&espi->lock); 334 spin_unlock(&espi->lock);
335 return sel; 335 return sel;
336} 336}
337
338/*
339 * This function is for T204 only.
340 * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
341 * one shot, since there is no per port counter on the out side.
342 */
343int
344t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
345{
346 struct peespi *espi = adapter->espi;
347 u8 i, nport = (u8)adapter->params.nports;
348
349 if (!wait) {
350 if (!spin_trylock(&espi->lock))
351 return -1;
352 } else
353 spin_lock(&espi->lock);
354
355 if ( (espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION ) {
356 espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) |
357 F_MONITORED_DIRECTION;
358 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
359 }
360 for (i = 0 ; i < nport; i++, valp++) {
361 if (i) {
362 writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i),
363 adapter->regs + A_ESPI_MISC_CONTROL);
364 }
365 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
366 }
367
368 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
369 spin_unlock(&espi->lock);
370 return 0;
371}
diff --git a/drivers/net/chelsio/espi.h b/drivers/net/chelsio/espi.h
index c90e37f8457c..84f2c98bc4cc 100644
--- a/drivers/net/chelsio/espi.h
+++ b/drivers/net/chelsio/espi.h
@@ -64,5 +64,6 @@ const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi);
64 64
65void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val); 65void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val);
66u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait); 66u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait);
67int t1_espi_get_mon_t204(adapter_t *, u32 *, u8);
67 68
68#endif /* _CXGB_ESPI_H_ */ 69#endif /* _CXGB_ESPI_H_ */
diff --git a/drivers/net/chelsio/fpga_defs.h b/drivers/net/chelsio/fpga_defs.h
new file mode 100644
index 000000000000..17a3c2ba36a3
--- /dev/null
+++ b/drivers/net/chelsio/fpga_defs.h
@@ -0,0 +1,232 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */
2
3/*
4 * FPGA specific definitions
5 */
6
7#ifndef __CHELSIO_FPGA_DEFS_H__
8#define __CHELSIO_FPGA_DEFS_H__
9
10#define FPGA_PCIX_ADDR_VERSION 0xA08
11#define FPGA_PCIX_ADDR_STAT 0xA0C
12
13/* FPGA master interrupt Cause/Enable bits */
14#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1
15#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2
16#define FPGA_PCIX_INTERRUPT_TP 0x4
17#define FPGA_PCIX_INTERRUPT_MC3 0x8
18#define FPGA_PCIX_INTERRUPT_GMAC 0x10
19#define FPGA_PCIX_INTERRUPT_PCIX 0x20
20
21/* TP interrupt register addresses */
22#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10
23#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14
24#define FPGA_TP_ADDR_VERSION 0xA18
25
26/* TP interrupt Cause/Enable bits */
27#define FPGA_TP_INTERRUPT_MC4 0x1
28#define FPGA_TP_INTERRUPT_MC5 0x2
29
30/*
31 * PM interrupt register addresses
32 */
33#define FPGA_MC3_REG_INTRENABLE 0xA20
34#define FPGA_MC3_REG_INTRCAUSE 0xA24
35#define FPGA_MC3_REG_VERSION 0xA28
36
37/*
38 * GMAC interrupt register addresses
39 */
40#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30
41#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34
42#define FPGA_GMAC_ADDR_VERSION 0xA38
43
44/* GMAC Cause/Enable bits */
45#define FPGA_GMAC_INTERRUPT_PORT0 0x1
46#define FPGA_GMAC_INTERRUPT_PORT1 0x2
47#define FPGA_GMAC_INTERRUPT_PORT2 0x4
48#define FPGA_GMAC_INTERRUPT_PORT3 0x8
49
50/* MI0 registers */
51#define A_MI0_CLK 0xb00
52
53#define S_MI0_CLK_DIV 0
54#define M_MI0_CLK_DIV 0xff
55#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
56#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
57
58#define S_MI0_CLK_CNT 8
59#define M_MI0_CLK_CNT 0xff
60#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
61#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
62
63#define A_MI0_CSR 0xb04
64
65#define S_MI0_CSR_POLL 0
66#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
67#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)
68
69#define S_MI0_PREAMBLE 1
70#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
71#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)
72
73#define S_MI0_INTR_ENABLE 2
74#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
75#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)
76
77#define S_MI0_BUSY 3
78#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
79#define F_MI0_BUSY V_MI0_BUSY(1U)
80
81#define S_MI0_MDIO 4
82#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
83#define F_MI0_MDIO V_MI0_MDIO(1U)
84
85#define A_MI0_ADDR 0xb08
86
87#define S_MI0_PHY_REG_ADDR 0
88#define M_MI0_PHY_REG_ADDR 0x1f
89#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
90#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
91
92#define S_MI0_PHY_ADDR 5
93#define M_MI0_PHY_ADDR 0x1f
94#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
95#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
96
97#define A_MI0_DATA_EXT 0xb0c
98#define A_MI0_DATA_INT 0xb10
99
100/* GMAC registers */
101#define A_GMAC_MACID_LO 0x28
102#define A_GMAC_MACID_HI 0x2c
103#define A_GMAC_CSR 0x30
104
105#define S_INTERFACE 0
106#define M_INTERFACE 0x3
107#define V_INTERFACE(x) ((x) << S_INTERFACE)
108#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
109
110#define S_MAC_TX_ENABLE 2
111#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
112#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)
113
114#define S_MAC_RX_ENABLE 3
115#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
116#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)
117
118#define S_MAC_LB_ENABLE 4
119#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
120#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)
121
122#define S_MAC_SPEED 5
123#define M_MAC_SPEED 0x3
124#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
125#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
126
127#define S_MAC_HD_FC_ENABLE 7
128#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
129#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)
130
131#define S_MAC_HALF_DUPLEX 8
132#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
133#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)
134
135#define S_MAC_PROMISC 9
136#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
137#define F_MAC_PROMISC V_MAC_PROMISC(1U)
138
139#define S_MAC_MC_ENABLE 10
140#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
141#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)
142
143#define S_MAC_RESET 11
144#define V_MAC_RESET(x) ((x) << S_MAC_RESET)
145#define F_MAC_RESET V_MAC_RESET(1U)
146
147#define S_MAC_RX_PAUSE_ENABLE 12
148#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
149#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)
150
151#define S_MAC_TX_PAUSE_ENABLE 13
152#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
153#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)
154
155#define S_MAC_LWM_ENABLE 14
156#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
157#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)
158
159#define S_MAC_MAGIC_PKT_ENABLE 15
160#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
161#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)
162
163#define S_MAC_ISL_ENABLE 16
164#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
165#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)
166
167#define S_MAC_JUMBO_ENABLE 17
168#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
169#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)
170
171#define S_MAC_RX_PAD_ENABLE 18
172#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
173#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)
174
175#define S_MAC_RX_CRC_ENABLE 19
176#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
177#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)
178
179#define A_GMAC_IFS 0x34
180
181#define S_MAC_IFS2 0
182#define M_MAC_IFS2 0x3f
183#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
184#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
185
186#define S_MAC_IFS1 8
187#define M_MAC_IFS1 0x7f
188#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
189#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
190
191#define A_GMAC_JUMBO_FRAME_LEN 0x38
192#define A_GMAC_LNK_DLY 0x3c
193#define A_GMAC_PAUSETIME 0x40
194#define A_GMAC_MCAST_LO 0x44
195#define A_GMAC_MCAST_HI 0x48
196#define A_GMAC_MCAST_MASK_LO 0x4c
197#define A_GMAC_MCAST_MASK_HI 0x50
198#define A_GMAC_RMT_CNT 0x54
199#define A_GMAC_RMT_DATA 0x58
200#define A_GMAC_BACKOFF_SEED 0x5c
201#define A_GMAC_TXF_THRES 0x60
202
203#define S_TXF_READ_THRESHOLD 0
204#define M_TXF_READ_THRESHOLD 0xff
205#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
206#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
207
208#define S_TXF_WRITE_THRESHOLD 16
209#define M_TXF_WRITE_THRESHOLD 0xff
210#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
211#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
212
213#define MAC_REG_BASE 0x600
214#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
215
216#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
217#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
218#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)
219#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)
220#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
221#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
222#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
223#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
224#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
225#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
226#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
227#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
228#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
229#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
230#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
231
232#endif
diff --git a/drivers/net/chelsio/gmac.h b/drivers/net/chelsio/gmac.h
index 746b0eeea964..a2b8ad9b5535 100644
--- a/drivers/net/chelsio/gmac.h
+++ b/drivers/net/chelsio/gmac.h
@@ -62,6 +62,8 @@ struct cmac_statistics {
62 u64 TxInternalMACXmitError; 62 u64 TxInternalMACXmitError;
63 u64 TxFramesWithExcessiveDeferral; 63 u64 TxFramesWithExcessiveDeferral;
64 u64 TxFCSErrors; 64 u64 TxFCSErrors;
65 u64 TxJumboFramesOK;
66 u64 TxJumboOctetsOK;
65 67
66 /* Receive */ 68 /* Receive */
67 u64 RxOctetsOK; 69 u64 RxOctetsOK;
@@ -81,6 +83,8 @@ struct cmac_statistics {
81 u64 RxInRangeLengthErrors; 83 u64 RxInRangeLengthErrors;
82 u64 RxOutOfRangeLengthField; 84 u64 RxOutOfRangeLengthField;
83 u64 RxFrameTooLongErrors; 85 u64 RxFrameTooLongErrors;
86 u64 RxJumboFramesOK;
87 u64 RxJumboOctetsOK;
84}; 88};
85 89
86struct cmac_ops { 90struct cmac_ops {
@@ -128,6 +132,7 @@ struct gmac {
128extern struct gmac t1_pm3393_ops; 132extern struct gmac t1_pm3393_ops;
129extern struct gmac t1_chelsio_mac_ops; 133extern struct gmac t1_chelsio_mac_ops;
130extern struct gmac t1_vsc7321_ops; 134extern struct gmac t1_vsc7321_ops;
135extern struct gmac t1_vsc7326_ops;
131extern struct gmac t1_ixf1010_ops; 136extern struct gmac t1_ixf1010_ops;
132extern struct gmac t1_dummy_mac_ops; 137extern struct gmac t1_dummy_mac_ops;
133 138
diff --git a/drivers/net/chelsio/ixf1010.c b/drivers/net/chelsio/ixf1010.c
new file mode 100644
index 000000000000..5b8f144e83d4
--- /dev/null
+++ b/drivers/net/chelsio/ixf1010.c
@@ -0,0 +1,485 @@
1/* $Date: 2005/11/12 02:13:49 $ $RCSfile: ixf1010.c,v $ $Revision: 1.36 $ */
2#include "gmac.h"
3#include "elmer0.h"
4
5/* Update fast changing statistics every 15 seconds */
6#define STATS_TICK_SECS 15
7/* 30 minutes for full statistics update */
8#define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS)
9
10/*
11 * The IXF1010 can handle frames up to 16383 bytes but it's optimized for
12 * frames up to 9831 (0x2667) bytes, so we limit jumbo frame size to this.
13 * This length includes ethernet header and FCS.
14 */
15#define MAX_FRAME_SIZE 0x2667
16
17/* MAC registers */
18enum {
19 /* Per-port registers */
20 REG_MACADDR_LOW = 0,
21 REG_MACADDR_HIGH = 0x4,
22 REG_FDFC_TYPE = 0xC,
23 REG_FC_TX_TIMER_VALUE = 0x1c,
24 REG_IPG_RX_TIME1 = 0x28,
25 REG_IPG_RX_TIME2 = 0x2c,
26 REG_IPG_TX_TIME = 0x30,
27 REG_PAUSE_THRES = 0x38,
28 REG_MAX_FRAME_SIZE = 0x3c,
29 REG_RGMII_SPEED = 0x40,
30 REG_FC_ENABLE = 0x48,
31 REG_DISCARD_CTRL_FRAMES = 0x54,
32 REG_DIVERSE_CONFIG = 0x60,
33 REG_RX_FILTER = 0x64,
34 REG_MC_ADDR_LOW = 0x68,
35 REG_MC_ADDR_HIGH = 0x6c,
36
37 REG_RX_OCTETS_OK = 0x80,
38 REG_RX_OCTETS_BAD = 0x84,
39 REG_RX_UC_PKTS = 0x88,
40 REG_RX_MC_PKTS = 0x8c,
41 REG_RX_BC_PKTS = 0x90,
42 REG_RX_FCS_ERR = 0xb0,
43 REG_RX_TAGGED = 0xb4,
44 REG_RX_DATA_ERR = 0xb8,
45 REG_RX_ALIGN_ERR = 0xbc,
46 REG_RX_LONG_ERR = 0xc0,
47 REG_RX_JABBER_ERR = 0xc4,
48 REG_RX_PAUSE_FRAMES = 0xc8,
49 REG_RX_UNKNOWN_CTRL_FRAMES = 0xcc,
50 REG_RX_VERY_LONG_ERR = 0xd0,
51 REG_RX_RUNT_ERR = 0xd4,
52 REG_RX_SHORT_ERR = 0xd8,
53 REG_RX_SYMBOL_ERR = 0xe4,
54
55 REG_TX_OCTETS_OK = 0x100,
56 REG_TX_OCTETS_BAD = 0x104,
57 REG_TX_UC_PKTS = 0x108,
58 REG_TX_MC_PKTS = 0x10c,
59 REG_TX_BC_PKTS = 0x110,
60 REG_TX_EXCESSIVE_LEN_DROP = 0x14c,
61 REG_TX_UNDERRUN = 0x150,
62 REG_TX_TAGGED = 0x154,
63 REG_TX_PAUSE_FRAMES = 0x15C,
64
65 /* Global registers */
66 REG_PORT_ENABLE = 0x1400,
67
68 REG_JTAG_ID = 0x1430,
69
70 RX_FIFO_HIGH_WATERMARK_BASE = 0x1600,
71 RX_FIFO_LOW_WATERMARK_BASE = 0x1628,
72 RX_FIFO_FRAMES_REMOVED_BASE = 0x1650,
73
74 REG_RX_ERR_DROP = 0x167c,
75 REG_RX_FIFO_OVERFLOW_EVENT = 0x1680,
76
77 TX_FIFO_HIGH_WATERMARK_BASE = 0x1800,
78 TX_FIFO_LOW_WATERMARK_BASE = 0x1828,
79 TX_FIFO_XFER_THRES_BASE = 0x1850,
80
81 REG_TX_FIFO_OVERFLOW_EVENT = 0x1878,
82 REG_TX_FIFO_OOS_EVENT = 0x1884,
83
84 TX_FIFO_FRAMES_REMOVED_BASE = 0x1888,
85
86 REG_SPI_RX_BURST = 0x1c00,
87 REG_SPI_RX_TRAINING = 0x1c04,
88 REG_SPI_RX_CALENDAR = 0x1c08,
89 REG_SPI_TX_SYNC = 0x1c0c
90};
91
92enum { /* RMON registers */
93 REG_RxOctetsTotalOK = 0x80,
94 REG_RxOctetsBad = 0x84,
95 REG_RxUCPkts = 0x88,
96 REG_RxMCPkts = 0x8c,
97 REG_RxBCPkts = 0x90,
98 REG_RxJumboPkts = 0xac,
99 REG_RxFCSErrors = 0xb0,
100 REG_RxDataErrors = 0xb8,
101 REG_RxAlignErrors = 0xbc,
102 REG_RxLongErrors = 0xc0,
103 REG_RxJabberErrors = 0xc4,
104 REG_RxPauseMacControlCounter = 0xc8,
105 REG_RxVeryLongErrors = 0xd0,
106 REG_RxRuntErrors = 0xd4,
107 REG_RxShortErrors = 0xd8,
108 REG_RxSequenceErrors = 0xe0,
109 REG_RxSymbolErrors = 0xe4,
110
111 REG_TxOctetsTotalOK = 0x100,
112 REG_TxOctetsBad = 0x104,
113 REG_TxUCPkts = 0x108,
114 REG_TxMCPkts = 0x10c,
115 REG_TxBCPkts = 0x110,
116 REG_TxJumboPkts = 0x12C,
117 REG_TxTotalCollisions = 0x134,
118 REG_TxExcessiveLengthDrop = 0x14c,
119 REG_TxUnderrun = 0x150,
120 REG_TxCRCErrors = 0x158,
121 REG_TxPauseFrames = 0x15c
122};
123
124enum {
125 DIVERSE_CONFIG_PAD_ENABLE = 0x80,
126 DIVERSE_CONFIG_CRC_ADD = 0x40
127};
128
129#define MACREG_BASE 0
130#define MACREG(mac, mac_reg) ((mac)->instance->mac_base + (mac_reg))
131
132struct _cmac_instance {
133 u32 mac_base;
134 u32 index;
135 u32 version;
136 u32 ticks;
137};
138
139static void disable_port(struct cmac *mac)
140{
141 u32 val;
142
143 t1_tpi_read(mac->adapter, REG_PORT_ENABLE, &val);
144 val &= ~(1 << mac->instance->index);
145 t1_tpi_write(mac->adapter, REG_PORT_ENABLE, val);
146}
147
148#define RMON_UPDATE(mac, name, stat_name) \
149 t1_tpi_read((mac)->adapter, MACREG(mac, REG_##name), &val); \
150 (mac)->stats.stat_name += val;
151
152/*
153 * Read the current values of the RMON counters and add them to the cumulative
154 * port statistics. The HW RMON counters are cleared by this operation.
155 */
156static void port_stats_update(struct cmac *mac)
157{
158 u32 val;
159
160 /* Rx stats */
161 RMON_UPDATE(mac, RxOctetsTotalOK, RxOctetsOK);
162 RMON_UPDATE(mac, RxOctetsBad, RxOctetsBad);
163 RMON_UPDATE(mac, RxUCPkts, RxUnicastFramesOK);
164 RMON_UPDATE(mac, RxMCPkts, RxMulticastFramesOK);
165 RMON_UPDATE(mac, RxBCPkts, RxBroadcastFramesOK);
166 RMON_UPDATE(mac, RxJumboPkts, RxJumboFramesOK);
167 RMON_UPDATE(mac, RxFCSErrors, RxFCSErrors);
168 RMON_UPDATE(mac, RxAlignErrors, RxAlignErrors);
169 RMON_UPDATE(mac, RxLongErrors, RxFrameTooLongErrors);
170 RMON_UPDATE(mac, RxVeryLongErrors, RxFrameTooLongErrors);
171 RMON_UPDATE(mac, RxPauseMacControlCounter, RxPauseFrames);
172 RMON_UPDATE(mac, RxDataErrors, RxDataErrors);
173 RMON_UPDATE(mac, RxJabberErrors, RxJabberErrors);
174 RMON_UPDATE(mac, RxRuntErrors, RxRuntErrors);
175 RMON_UPDATE(mac, RxShortErrors, RxRuntErrors);
176 RMON_UPDATE(mac, RxSequenceErrors, RxSequenceErrors);
177 RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
178
179 /* Tx stats (skip collision stats as we are full-duplex only) */
180 RMON_UPDATE(mac, TxOctetsTotalOK, TxOctetsOK);
181 RMON_UPDATE(mac, TxOctetsBad, TxOctetsBad);
182 RMON_UPDATE(mac, TxUCPkts, TxUnicastFramesOK);
183 RMON_UPDATE(mac, TxMCPkts, TxMulticastFramesOK);
184 RMON_UPDATE(mac, TxBCPkts, TxBroadcastFramesOK);
185 RMON_UPDATE(mac, TxJumboPkts, TxJumboFramesOK);
186 RMON_UPDATE(mac, TxPauseFrames, TxPauseFrames);
187 RMON_UPDATE(mac, TxExcessiveLengthDrop, TxLengthErrors);
188 RMON_UPDATE(mac, TxUnderrun, TxUnderrun);
189 RMON_UPDATE(mac, TxCRCErrors, TxFCSErrors);
190}
191
192/* No-op interrupt operation as this MAC does not support interrupts */
193static int mac_intr_op(struct cmac *mac)
194{
195 return 0;
196}
197
198/* Expect MAC address to be in network byte order. */
199static int mac_set_address(struct cmac *mac, u8 addr[6])
200{
201 u32 addr_lo, addr_hi;
202
203 addr_lo = addr[2];
204 addr_lo = (addr_lo << 8) | addr[3];
205 addr_lo = (addr_lo << 8) | addr[4];
206 addr_lo = (addr_lo << 8) | addr[5];
207
208 addr_hi = addr[0];
209 addr_hi = (addr_hi << 8) | addr[1];
210
211 t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo);
212 t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi);
213 return 0;
214}
215
216static int mac_get_address(struct cmac *mac, u8 addr[6])
217{
218 u32 addr_lo, addr_hi;
219
220 t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_LOW), &addr_lo);
221 t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), &addr_hi);
222
223 addr[0] = (u8) (addr_hi >> 8);
224 addr[1] = (u8) addr_hi;
225 addr[2] = (u8) (addr_lo >> 24);
226 addr[3] = (u8) (addr_lo >> 16);
227 addr[4] = (u8) (addr_lo >> 8);
228 addr[5] = (u8) addr_lo;
229 return 0;
230}
231
232/* This is intended to reset a port, not the whole MAC */
233static int mac_reset(struct cmac *mac)
234{
235 return 0;
236}
237
238static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
239{
240 u32 val, new_mode;
241 adapter_t *adapter = mac->adapter;
242 u32 addr_lo, addr_hi;
243 u8 *addr;
244
245 t1_tpi_read(adapter, MACREG(mac, REG_RX_FILTER), &val);
246 new_mode = val & ~7;
247 if (!t1_rx_mode_promisc(rm) && mac->instance->version > 0)
248 new_mode |= 1; /* only set if version > 0 due to erratum */
249 if (!t1_rx_mode_promisc(rm) && !t1_rx_mode_allmulti(rm)
250 && t1_rx_mode_mc_cnt(rm) <= 1)
251 new_mode |= 2;
252 if (new_mode != val)
253 t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode);
254 switch (t1_rx_mode_mc_cnt(rm)) {
255 case 0:
256 t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), 0);
257 t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), 0);
258 break;
259 case 1:
260 addr = t1_get_next_mcaddr(rm);
261 addr_lo = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
262 addr[5];
263 addr_hi = (addr[0] << 8) | addr[1];
264 t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), addr_lo);
265 t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), addr_hi);
266 break;
267 default:
268 break;
269 }
270 return 0;
271}
272
273static int mac_set_mtu(struct cmac *mac, int mtu)
274{
275 /* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't */
276 if (mtu > (MAX_FRAME_SIZE - 14 - 4)) return -EINVAL;
277 t1_tpi_write(mac->adapter, MACREG(mac, REG_MAX_FRAME_SIZE),
278 mtu + 14 + 4);
279 return 0;
280}
281
282static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
283 int fc)
284{
285 u32 val;
286
287 if (speed >= 0 && speed != SPEED_100 && speed != SPEED_1000)
288 return -1;
289 if (duplex >= 0 && duplex != DUPLEX_FULL)
290 return -1;
291
292 if (speed >= 0) {
293 val = speed == SPEED_100 ? 1 : 2;
294 t1_tpi_write(mac->adapter, MACREG(mac, REG_RGMII_SPEED), val);
295 }
296
297 t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val);
298 val &= ~3;
299 if (fc & PAUSE_RX)
300 val |= 1;
301 if (fc & PAUSE_TX)
302 val |= 2;
303 t1_tpi_write(mac->adapter, MACREG(mac, REG_FC_ENABLE), val);
304 return 0;
305}
306
307static int mac_get_speed_duplex_fc(struct cmac *mac, int *speed, int *duplex,
308 int *fc)
309{
310 u32 val;
311
312 if (duplex)
313 *duplex = DUPLEX_FULL;
314 if (speed) {
315 t1_tpi_read(mac->adapter, MACREG(mac, REG_RGMII_SPEED),
316 &val);
317 *speed = (val & 2) ? SPEED_1000 : SPEED_100;
318 }
319 if (fc) {
320 t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val);
321 *fc = 0;
322 if (val & 1)
323 *fc |= PAUSE_RX;
324 if (val & 2)
325 *fc |= PAUSE_TX;
326 }
327 return 0;
328}
329
330static void enable_port(struct cmac *mac)
331{
332 u32 val;
333 u32 index = mac->instance->index;
334 adapter_t *adapter = mac->adapter;
335
336 t1_tpi_read(adapter, MACREG(mac, REG_DIVERSE_CONFIG), &val);
337 val |= DIVERSE_CONFIG_CRC_ADD | DIVERSE_CONFIG_PAD_ENABLE;
338 t1_tpi_write(adapter, MACREG(mac, REG_DIVERSE_CONFIG), val);
339 if (mac->instance->version > 0)
340 t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 3);
341 else /* Don't enable unicast address filtering due to IXF1010 bug */
342 t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 2);
343
344 t1_tpi_read(adapter, REG_RX_ERR_DROP, &val);
345 val |= (1 << index);
346 t1_tpi_write(adapter, REG_RX_ERR_DROP, val);
347
348 /*
349 * Clear the port RMON registers by adding their current values to the
350 * cumulatice port stats and then clearing the stats. Really.
351 */
352 port_stats_update(mac);
353 memset(&mac->stats, 0, sizeof(struct cmac_statistics));
354 mac->instance->ticks = 0;
355
356 t1_tpi_read(adapter, REG_PORT_ENABLE, &val);
357 val |= (1 << index);
358 t1_tpi_write(adapter, REG_PORT_ENABLE, val);
359
360 index <<= 2;
361 if (is_T2(adapter)) {
362 /* T204: set the Fifo water level & threshold */
363 t1_tpi_write(adapter, RX_FIFO_HIGH_WATERMARK_BASE + index, 0x740);
364 t1_tpi_write(adapter, RX_FIFO_LOW_WATERMARK_BASE + index, 0x730);
365 t1_tpi_write(adapter, TX_FIFO_HIGH_WATERMARK_BASE + index, 0x600);
366 t1_tpi_write(adapter, TX_FIFO_LOW_WATERMARK_BASE + index, 0x1d0);
367 t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x1100);
368 } else {
369 /*
370 * Set the TX Fifo Threshold to 0x400 instead of 0x100 to work around
371 * Underrun problem. Intel has blessed this solution.
372 */
373 t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x400);
374 }
375}
376
377/* IXF1010 ports do not have separate enables for TX and RX */
378static int mac_enable(struct cmac *mac, int which)
379{
380 if (which & (MAC_DIRECTION_RX | MAC_DIRECTION_TX))
381 enable_port(mac);
382 return 0;
383}
384
385static int mac_disable(struct cmac *mac, int which)
386{
387 if (which & (MAC_DIRECTION_RX | MAC_DIRECTION_TX))
388 disable_port(mac);
389 return 0;
390}
391
392/*
393 * This function is called periodically to accumulate the current values of the
394 * RMON counters into the port statistics. Since the counters are only 32 bits
395 * some of them can overflow in less than a minute at GigE speeds, so this
396 * function should be called every 30 seconds or so.
397 *
398 * To cut down on reading costs we update only the octet counters at each tick
399 * and do a full update at major ticks, which can be every 30 minutes or more.
400 */
401static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
402 int flag)
403{
404 if (flag == MAC_STATS_UPDATE_FULL ||
405 MAJOR_UPDATE_TICKS <= mac->instance->ticks) {
406 port_stats_update(mac);
407 mac->instance->ticks = 0;
408 } else {
409 u32 val;
410
411 RMON_UPDATE(mac, RxOctetsTotalOK, RxOctetsOK);
412 RMON_UPDATE(mac, TxOctetsTotalOK, TxOctetsOK);
413 mac->instance->ticks++;
414 }
415 return &mac->stats;
416}
417
418static void mac_destroy(struct cmac *mac)
419{
420 kfree(mac);
421}
422
423static struct cmac_ops ixf1010_ops = {
424 .destroy = mac_destroy,
425 .reset = mac_reset,
426 .interrupt_enable = mac_intr_op,
427 .interrupt_disable = mac_intr_op,
428 .interrupt_clear = mac_intr_op,
429 .enable = mac_enable,
430 .disable = mac_disable,
431 .set_mtu = mac_set_mtu,
432 .set_rx_mode = mac_set_rx_mode,
433 .set_speed_duplex_fc = mac_set_speed_duplex_fc,
434 .get_speed_duplex_fc = mac_get_speed_duplex_fc,
435 .statistics_update = mac_update_statistics,
436 .macaddress_get = mac_get_address,
437 .macaddress_set = mac_set_address,
438};
439
440static int ixf1010_mac_reset(adapter_t *adapter)
441{
442 u32 val;
443
444 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
445 if ((val & 1) != 0) {
446 val &= ~1;
447 t1_tpi_write(adapter, A_ELMER0_GPO, val);
448 udelay(2);
449 }
450 val |= 1;
451 t1_tpi_write(adapter, A_ELMER0_GPO, val);
452 udelay(2);
453
454 t1_tpi_write(adapter, REG_PORT_ENABLE, 0);
455 return 0;
456}
457
458static struct cmac *ixf1010_mac_create(adapter_t *adapter, int index)
459{
460 struct cmac *mac;
461 u32 val;
462
463 if (index > 9) return NULL;
464
465 mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
466 if (!mac) return NULL;
467
468 mac->ops = &ixf1010_ops;
469 mac->instance = (cmac_instance *)(mac + 1);
470
471 mac->instance->mac_base = MACREG_BASE + (index * 0x200);
472 mac->instance->index = index;
473 mac->adapter = adapter;
474 mac->instance->ticks = 0;
475
476 t1_tpi_read(adapter, REG_JTAG_ID, &val);
477 mac->instance->version = val >> 28;
478 return mac;
479}
480
481struct gmac t1_ixf1010_ops = {
482 STATS_TICK_SECS,
483 ixf1010_mac_create,
484 ixf1010_mac_reset
485};
diff --git a/drivers/net/chelsio/mac.c b/drivers/net/chelsio/mac.c
new file mode 100644
index 000000000000..6af39dc70459
--- /dev/null
+++ b/drivers/net/chelsio/mac.c
@@ -0,0 +1,368 @@
1/* $Date: 2005/10/22 00:42:59 $ $RCSfile: mac.c,v $ $Revision: 1.32 $ */
2#include "gmac.h"
3#include "regs.h"
4#include "fpga_defs.h"
5
6#define MAC_CSR_INTERFACE_GMII 0x0
7#define MAC_CSR_INTERFACE_TBI 0x1
8#define MAC_CSR_INTERFACE_MII 0x2
9#define MAC_CSR_INTERFACE_RMII 0x3
10
11/* Chelsio's MAC statistics. */
12struct mac_statistics {
13
14 /* Transmit */
15 u32 TxFramesTransmittedOK;
16 u32 TxReserved1;
17 u32 TxReserved2;
18 u32 TxOctetsTransmittedOK;
19 u32 TxFramesWithDeferredXmissions;
20 u32 TxLateCollisions;
21 u32 TxFramesAbortedDueToXSCollisions;
22 u32 TxFramesLostDueToIntMACXmitError;
23 u32 TxReserved3;
24 u32 TxMulticastFrameXmittedOK;
25 u32 TxBroadcastFramesXmittedOK;
26 u32 TxFramesWithExcessiveDeferral;
27 u32 TxPAUSEMACCtrlFramesTransmitted;
28
29 /* Receive */
30 u32 RxFramesReceivedOK;
31 u32 RxFrameCheckSequenceErrors;
32 u32 RxAlignmentErrors;
33 u32 RxOctetsReceivedOK;
34 u32 RxFramesLostDueToIntMACRcvError;
35 u32 RxMulticastFramesReceivedOK;
36 u32 RxBroadcastFramesReceivedOK;
37 u32 RxInRangeLengthErrors;
38 u32 RxTxOutOfRangeLengthField;
39 u32 RxFrameTooLongErrors;
40 u32 RxPAUSEMACCtrlFramesReceived;
41};
42
43static int static_aPorts[] = {
44 FPGA_GMAC_INTERRUPT_PORT0,
45 FPGA_GMAC_INTERRUPT_PORT1,
46 FPGA_GMAC_INTERRUPT_PORT2,
47 FPGA_GMAC_INTERRUPT_PORT3
48};
49
50struct _cmac_instance {
51 u32 index;
52};
53
54static int mac_intr_enable(struct cmac *mac)
55{
56 u32 mac_intr;
57
58 if (t1_is_asic(mac->adapter)) {
59 /* ASIC */
60
61 /* We don't use the on chip MAC for ASIC products. */
62 } else {
63 /* FPGA */
64
65 /* Set parent gmac interrupt. */
66 mac_intr = readl(mac->adapter->regs + A_PL_ENABLE);
67 mac_intr |= FPGA_PCIX_INTERRUPT_GMAC;
68 writel(mac_intr, mac->adapter->regs + A_PL_ENABLE);
69
70 mac_intr = readl(mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
71 mac_intr |= static_aPorts[mac->instance->index];
72 writel(mac_intr,
73 mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
74 }
75
76 return 0;
77}
78
79static int mac_intr_disable(struct cmac *mac)
80{
81 u32 mac_intr;
82
83 if (t1_is_asic(mac->adapter)) {
84 /* ASIC */
85
86 /* We don't use the on chip MAC for ASIC products. */
87 } else {
88 /* FPGA */
89
90 /* Set parent gmac interrupt. */
91 mac_intr = readl(mac->adapter->regs + A_PL_ENABLE);
92 mac_intr &= ~FPGA_PCIX_INTERRUPT_GMAC;
93 writel(mac_intr, mac->adapter->regs + A_PL_ENABLE);
94
95 mac_intr = readl(mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
96 mac_intr &= ~(static_aPorts[mac->instance->index]);
97 writel(mac_intr,
98 mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
99 }
100
101 return 0;
102}
103
104static int mac_intr_clear(struct cmac *mac)
105{
106 u32 mac_intr;
107
108 if (t1_is_asic(mac->adapter)) {
109 /* ASIC */
110
111 /* We don't use the on chip MAC for ASIC products. */
112 } else {
113 /* FPGA */
114
115 /* Set parent gmac interrupt. */
116 writel(FPGA_PCIX_INTERRUPT_GMAC,
117 mac->adapter->regs + A_PL_CAUSE);
118 mac_intr = readl(mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
119 mac_intr |= (static_aPorts[mac->instance->index]);
120 writel(mac_intr,
121 mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
122 }
123
124 return 0;
125}
126
127static int mac_get_address(struct cmac *mac, u8 addr[6])
128{
129 u32 data32_lo, data32_hi;
130
131 data32_lo = readl(mac->adapter->regs
132 + MAC_REG_IDLO(mac->instance->index));
133 data32_hi = readl(mac->adapter->regs
134 + MAC_REG_IDHI(mac->instance->index));
135
136 addr[0] = (u8) ((data32_hi >> 8) & 0xFF);
137 addr[1] = (u8) ((data32_hi) & 0xFF);
138 addr[2] = (u8) ((data32_lo >> 24) & 0xFF);
139 addr[3] = (u8) ((data32_lo >> 16) & 0xFF);
140 addr[4] = (u8) ((data32_lo >> 8) & 0xFF);
141 addr[5] = (u8) ((data32_lo) & 0xFF);
142 return 0;
143}
144
145static int mac_reset(struct cmac *mac)
146{
147 u32 data32;
148 int mac_in_reset, time_out = 100;
149 int idx = mac->instance->index;
150
151 data32 = readl(mac->adapter->regs + MAC_REG_CSR(idx));
152 writel(data32 | F_MAC_RESET,
153 mac->adapter->regs + MAC_REG_CSR(idx));
154
155 do {
156 data32 = readl(mac->adapter->regs + MAC_REG_CSR(idx));
157
158 mac_in_reset = data32 & F_MAC_RESET;
159 if (mac_in_reset)
160 udelay(1);
161 } while (mac_in_reset && --time_out);
162
163 if (mac_in_reset) {
164 CH_ERR("%s: MAC %d reset timed out\n",
165 mac->adapter->name, idx);
166 return 2;
167 }
168
169 return 0;
170}
171
172static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
173{
174 u32 val;
175
176 val = readl(mac->adapter->regs
177 + MAC_REG_CSR(mac->instance->index));
178 val &= ~(F_MAC_PROMISC | F_MAC_MC_ENABLE);
179 val |= V_MAC_PROMISC(t1_rx_mode_promisc(rm) != 0);
180 val |= V_MAC_MC_ENABLE(t1_rx_mode_allmulti(rm) != 0);
181 writel(val,
182 mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
183
184 return 0;
185}
186
187static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
188 int fc)
189{
190 u32 data32;
191
192 data32 = readl(mac->adapter->regs
193 + MAC_REG_CSR(mac->instance->index));
194 data32 &= ~(F_MAC_HALF_DUPLEX | V_MAC_SPEED(M_MAC_SPEED) |
195 V_INTERFACE(M_INTERFACE) | F_MAC_TX_PAUSE_ENABLE |
196 F_MAC_RX_PAUSE_ENABLE);
197
198 switch (speed) {
199 case SPEED_10:
200 case SPEED_100:
201 data32 |= V_INTERFACE(MAC_CSR_INTERFACE_MII);
202 data32 |= V_MAC_SPEED(speed == SPEED_10 ? 0 : 1);
203 break;
204 case SPEED_1000:
205 data32 |= V_INTERFACE(MAC_CSR_INTERFACE_GMII);
206 data32 |= V_MAC_SPEED(2);
207 break;
208 }
209
210 if (duplex >= 0)
211 data32 |= V_MAC_HALF_DUPLEX(duplex == DUPLEX_HALF);
212
213 if (fc >= 0) {
214 data32 |= V_MAC_RX_PAUSE_ENABLE((fc & PAUSE_RX) != 0);
215 data32 |= V_MAC_TX_PAUSE_ENABLE((fc & PAUSE_TX) != 0);
216 }
217
218 writel(data32,
219 mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
220 return 0;
221}
222
223static int mac_enable(struct cmac *mac, int which)
224{
225 u32 val;
226
227 val = readl(mac->adapter->regs
228 + MAC_REG_CSR(mac->instance->index));
229 if (which & MAC_DIRECTION_RX)
230 val |= F_MAC_RX_ENABLE;
231 if (which & MAC_DIRECTION_TX)
232 val |= F_MAC_TX_ENABLE;
233 writel(val,
234 mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
235 return 0;
236}
237
238static int mac_disable(struct cmac *mac, int which)
239{
240 u32 val;
241
242 val = readl(mac->adapter->regs
243 + MAC_REG_CSR(mac->instance->index));
244 if (which & MAC_DIRECTION_RX)
245 val &= ~F_MAC_RX_ENABLE;
246 if (which & MAC_DIRECTION_TX)
247 val &= ~F_MAC_TX_ENABLE;
248 writel(val,
249 mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
250 return 0;
251}
252
253#if 0
254static int mac_set_ifs(struct cmac *mac, u32 mode)
255{
256 t1_write_reg_4(mac->adapter,
257 MAC_REG_IFS(mac->instance->index),
258 mode);
259 return 0;
260}
261
262static int mac_enable_isl(struct cmac *mac)
263{
264 u32 data32 = readl(mac->adapter->regs
265 + MAC_REG_CSR(mac->instance->index));
266 data32 |= F_MAC_RX_ENABLE | F_MAC_TX_ENABLE;
267 t1_write_reg_4(mac->adapter,
268 MAC_REG_CSR(mac->instance->index),
269 data32);
270 return 0;
271}
272#endif
273
274static int mac_set_mtu(struct cmac *mac, int mtu)
275{
276 if (mtu > 9600)
277 return -EINVAL;
278 writel(mtu + ETH_HLEN + VLAN_HLEN,
279 mac->adapter->regs + MAC_REG_LARGEFRAMELENGTH(mac->instance->index));
280
281 return 0;
282}
283
284static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
285 int flag)
286{
287 struct mac_statistics st;
288 u32 *p = (u32 *) & st, i;
289
290 writel(0,
291 mac->adapter->regs + MAC_REG_RMCNT(mac->instance->index));
292
293 for (i = 0; i < sizeof(st) / sizeof(u32); i++)
294 *p++ = readl(mac->adapter->regs
295 + MAC_REG_RMDATA(mac->instance->index));
296
297 /* XXX convert stats */
298 return &mac->stats;
299}
300
301static void mac_destroy(struct cmac *mac)
302{
303 kfree(mac);
304}
305
306static struct cmac_ops chelsio_mac_ops = {
307 .destroy = mac_destroy,
308 .reset = mac_reset,
309 .interrupt_enable = mac_intr_enable,
310 .interrupt_disable = mac_intr_disable,
311 .interrupt_clear = mac_intr_clear,
312 .enable = mac_enable,
313 .disable = mac_disable,
314 .set_mtu = mac_set_mtu,
315 .set_rx_mode = mac_set_rx_mode,
316 .set_speed_duplex_fc = mac_set_speed_duplex_fc,
317 .macaddress_get = mac_get_address,
318 .statistics_update = mac_update_statistics,
319};
320
321static struct cmac *mac_create(adapter_t *adapter, int index)
322{
323 struct cmac *mac;
324 u32 data32;
325
326 if (index >= 4)
327 return NULL;
328
329 mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
330 if (!mac)
331 return NULL;
332
333 mac->ops = &chelsio_mac_ops;
334 mac->instance = (cmac_instance *) (mac + 1);
335
336 mac->instance->index = index;
337 mac->adapter = adapter;
338
339 data32 = readl(adapter->regs + MAC_REG_CSR(mac->instance->index));
340 data32 &= ~(F_MAC_RESET | F_MAC_PROMISC | F_MAC_PROMISC |
341 F_MAC_LB_ENABLE | F_MAC_RX_ENABLE | F_MAC_TX_ENABLE);
342 data32 |= F_MAC_JUMBO_ENABLE;
343 writel(data32, adapter->regs + MAC_REG_CSR(mac->instance->index));
344
345 /* Initialize the random backoff seed. */
346 data32 = 0x55aa + (3 * index);
347 writel(data32,
348 adapter->regs + MAC_REG_GMRANDBACKOFFSEED(mac->instance->index));
349
350 /* Check to see if the mac address needs to be set manually. */
351 data32 = readl(adapter->regs + MAC_REG_IDLO(mac->instance->index));
352 if (data32 == 0 || data32 == 0xffffffff) {
353 /*
354 * Add a default MAC address if we can't read one.
355 */
356 writel(0x43FFFFFF - index,
357 adapter->regs + MAC_REG_IDLO(mac->instance->index));
358 writel(0x0007,
359 adapter->regs + MAC_REG_IDHI(mac->instance->index));
360 }
361
362 (void) mac_set_mtu(mac, 1500);
363 return mac;
364}
365
366struct gmac t1_chelsio_mac_ops = {
367 .create = mac_create
368};
diff --git a/drivers/net/chelsio/mv88e1xxx.c b/drivers/net/chelsio/mv88e1xxx.c
new file mode 100644
index 000000000000..28ac93ff7c4f
--- /dev/null
+++ b/drivers/net/chelsio/mv88e1xxx.c
@@ -0,0 +1,397 @@
1/* $Date: 2005/10/24 23:18:13 $ $RCSfile: mv88e1xxx.c,v $ $Revision: 1.49 $ */
2#include "common.h"
3#include "mv88e1xxx.h"
4#include "cphy.h"
5#include "elmer0.h"
6
7/* MV88E1XXX MDI crossover register values */
8#define CROSSOVER_MDI 0
9#define CROSSOVER_MDIX 1
10#define CROSSOVER_AUTO 3
11
12#define INTR_ENABLE_MASK 0x6CA0
13
14/*
15 * Set the bits given by 'bitval' in PHY register 'reg'.
16 */
17static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
18{
19 u32 val;
20
21 (void) simple_mdio_read(cphy, reg, &val);
22 (void) simple_mdio_write(cphy, reg, val | bitval);
23}
24
25/*
26 * Clear the bits given by 'bitval' in PHY register 'reg'.
27 */
28static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
29{
30 u32 val;
31
32 (void) simple_mdio_read(cphy, reg, &val);
33 (void) simple_mdio_write(cphy, reg, val & ~bitval);
34}
35
36/*
37 * NAME: phy_reset
38 *
39 * DESC: Reset the given PHY's port. NOTE: This is not a global
40 * chip reset.
41 *
42 * PARAMS: cphy - Pointer to PHY instance data.
43 *
44 * RETURN: 0 - Successfull reset.
45 * -1 - Timeout.
46 */
47static int mv88e1xxx_reset(struct cphy *cphy, int wait)
48{
49 u32 ctl;
50 int time_out = 1000;
51
52 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
53
54 do {
55 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
56 ctl &= BMCR_RESET;
57 if (ctl)
58 udelay(1);
59 } while (ctl && --time_out);
60
61 return ctl ? -1 : 0;
62}
63
64static int mv88e1xxx_interrupt_enable(struct cphy *cphy)
65{
66 /* Enable PHY interrupts. */
67 (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER,
68 INTR_ENABLE_MASK);
69
70 /* Enable Marvell interrupts through Elmer0. */
71 if (t1_is_asic(cphy->adapter)) {
72 u32 elmer;
73
74 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
75 elmer |= ELMER0_GP_BIT1;
76 if (is_T2(cphy->adapter)) {
77 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
78 }
79 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
80 }
81 return 0;
82}
83
84static int mv88e1xxx_interrupt_disable(struct cphy *cphy)
85{
86 /* Disable all phy interrupts. */
87 (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0);
88
89 /* Disable Marvell interrupts through Elmer0. */
90 if (t1_is_asic(cphy->adapter)) {
91 u32 elmer;
92
93 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
94 elmer &= ~ELMER0_GP_BIT1;
95 if (is_T2(cphy->adapter)) {
96 elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
97 }
98 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
99 }
100 return 0;
101}
102
103static int mv88e1xxx_interrupt_clear(struct cphy *cphy)
104{
105 u32 elmer;
106
107 /* Clear PHY interrupts by reading the register. */
108 (void) simple_mdio_read(cphy,
109 MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer);
110
111 /* Clear Marvell interrupts through Elmer0. */
112 if (t1_is_asic(cphy->adapter)) {
113 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
114 elmer |= ELMER0_GP_BIT1;
115 if (is_T2(cphy->adapter)) {
116 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
117 }
118 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
119 }
120 return 0;
121}
122
123/*
124 * Set the PHY speed and duplex. This also disables auto-negotiation, except
125 * for 1Gb/s, where auto-negotiation is mandatory.
126 */
127static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)
128{
129 u32 ctl;
130
131 (void) simple_mdio_read(phy, MII_BMCR, &ctl);
132 if (speed >= 0) {
133 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
134 if (speed == SPEED_100)
135 ctl |= BMCR_SPEED100;
136 else if (speed == SPEED_1000)
137 ctl |= BMCR_SPEED1000;
138 }
139 if (duplex >= 0) {
140 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
141 if (duplex == DUPLEX_FULL)
142 ctl |= BMCR_FULLDPLX;
143 }
144 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */
145 ctl |= BMCR_ANENABLE;
146 (void) simple_mdio_write(phy, MII_BMCR, ctl);
147 return 0;
148}
149
150static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
151{
152 u32 data32;
153
154 (void) simple_mdio_read(cphy,
155 MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32);
156 data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE);
157 data32 |= V_PSCR_MDI_XOVER_MODE(crossover);
158 (void) simple_mdio_write(cphy,
159 MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32);
160 return 0;
161}
162
163static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
164{
165 u32 ctl;
166
167 (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
168
169 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
170 /* restart autoneg for change to take effect */
171 ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
172 (void) simple_mdio_write(cphy, MII_BMCR, ctl);
173 return 0;
174}
175
176static int mv88e1xxx_autoneg_disable(struct cphy *cphy)
177{
178 u32 ctl;
179
180 /*
181 * Crossover *must* be set to manual in order to disable auto-neg.
182 * The Alaska FAQs document highlights this point.
183 */
184 (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI);
185
186 /*
187 * Must include autoneg reset when disabling auto-neg. This
188 * is described in the Alaska FAQ document.
189 */
190 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
191 ctl &= ~BMCR_ANENABLE;
192 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
193 return 0;
194}
195
196static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
197{
198 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
199 return 0;
200}
201
202static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map)
203{
204 u32 val = 0;
205
206 if (advertise_map &
207 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
208 (void) simple_mdio_read(phy, MII_GBCR, &val);
209 val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL);
210 if (advertise_map & ADVERTISED_1000baseT_Half)
211 val |= GBCR_ADV_1000HALF;
212 if (advertise_map & ADVERTISED_1000baseT_Full)
213 val |= GBCR_ADV_1000FULL;
214 }
215 (void) simple_mdio_write(phy, MII_GBCR, val);
216
217 val = 1;
218 if (advertise_map & ADVERTISED_10baseT_Half)
219 val |= ADVERTISE_10HALF;
220 if (advertise_map & ADVERTISED_10baseT_Full)
221 val |= ADVERTISE_10FULL;
222 if (advertise_map & ADVERTISED_100baseT_Half)
223 val |= ADVERTISE_100HALF;
224 if (advertise_map & ADVERTISED_100baseT_Full)
225 val |= ADVERTISE_100FULL;
226 if (advertise_map & ADVERTISED_PAUSE)
227 val |= ADVERTISE_PAUSE;
228 if (advertise_map & ADVERTISED_ASYM_PAUSE)
229 val |= ADVERTISE_PAUSE_ASYM;
230 (void) simple_mdio_write(phy, MII_ADVERTISE, val);
231 return 0;
232}
233
234static int mv88e1xxx_set_loopback(struct cphy *cphy, int on)
235{
236 if (on)
237 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
238 else
239 mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
240 return 0;
241}
242
243static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
244 int *speed, int *duplex, int *fc)
245{
246 u32 status;
247 int sp = -1, dplx = -1, pause = 0;
248
249 (void) simple_mdio_read(cphy,
250 MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
251 if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
252 if (status & V_PSSR_RX_PAUSE)
253 pause |= PAUSE_RX;
254 if (status & V_PSSR_TX_PAUSE)
255 pause |= PAUSE_TX;
256 dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
257 sp = G_PSSR_SPEED(status);
258 if (sp == 0)
259 sp = SPEED_10;
260 else if (sp == 1)
261 sp = SPEED_100;
262 else
263 sp = SPEED_1000;
264 }
265 if (link_ok)
266 *link_ok = (status & V_PSSR_LINK) != 0;
267 if (speed)
268 *speed = sp;
269 if (duplex)
270 *duplex = dplx;
271 if (fc)
272 *fc = pause;
273 return 0;
274}
275
276static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
277{
278 u32 val;
279
280 (void) simple_mdio_read(cphy,
281 MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val);
282
283 /*
284 * Set the downshift counter to 2 so we try to establish Gb link
285 * twice before downshifting.
286 */
287 val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT));
288
289 if (downshift_enable)
290 val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2);
291 (void) simple_mdio_write(cphy,
292 MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val);
293 return 0;
294}
295
296static int mv88e1xxx_interrupt_handler(struct cphy *cphy)
297{
298 int cphy_cause = 0;
299 u32 status;
300
301 /*
302 * Loop until cause reads zero. Need to handle bouncing interrupts.
303 */
304 while (1) {
305 u32 cause;
306
307 (void) simple_mdio_read(cphy,
308 MV88E1XXX_INTERRUPT_STATUS_REGISTER,
309 &cause);
310 cause &= INTR_ENABLE_MASK;
311 if (!cause) break;
312
313 if (cause & MV88E1XXX_INTR_LINK_CHNG) {
314 (void) simple_mdio_read(cphy,
315 MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
316
317 if (status & MV88E1XXX_INTR_LINK_CHNG) {
318 cphy->state |= PHY_LINK_UP;
319 } else {
320 cphy->state &= ~PHY_LINK_UP;
321 if (cphy->state & PHY_AUTONEG_EN)
322 cphy->state &= ~PHY_AUTONEG_RDY;
323 cphy_cause |= cphy_cause_link_change;
324 }
325 }
326
327 if (cause & MV88E1XXX_INTR_AUTONEG_DONE)
328 cphy->state |= PHY_AUTONEG_RDY;
329
330 if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) ==
331 (PHY_LINK_UP | PHY_AUTONEG_RDY))
332 cphy_cause |= cphy_cause_link_change;
333 }
334 return cphy_cause;
335}
336
337static void mv88e1xxx_destroy(struct cphy *cphy)
338{
339 kfree(cphy);
340}
341
342static struct cphy_ops mv88e1xxx_ops = {
343 .destroy = mv88e1xxx_destroy,
344 .reset = mv88e1xxx_reset,
345 .interrupt_enable = mv88e1xxx_interrupt_enable,
346 .interrupt_disable = mv88e1xxx_interrupt_disable,
347 .interrupt_clear = mv88e1xxx_interrupt_clear,
348 .interrupt_handler = mv88e1xxx_interrupt_handler,
349 .autoneg_enable = mv88e1xxx_autoneg_enable,
350 .autoneg_disable = mv88e1xxx_autoneg_disable,
351 .autoneg_restart = mv88e1xxx_autoneg_restart,
352 .advertise = mv88e1xxx_advertise,
353 .set_loopback = mv88e1xxx_set_loopback,
354 .set_speed_duplex = mv88e1xxx_set_speed_duplex,
355 .get_link_status = mv88e1xxx_get_link_status,
356};
357
358static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr,
359 struct mdio_ops *mdio_ops)
360{
361 struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
362
363 if (!cphy) return NULL;
364
365 cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops);
366
367 /* Configure particular PHY's to run in a different mode. */
368 if ((board_info(adapter)->caps & SUPPORTED_TP) &&
369 board_info(adapter)->chip_phy == CHBT_PHY_88E1111) {
370 /*
371 * Configure the PHY transmitter as class A to reduce EMI.
372 */
373 (void) simple_mdio_write(cphy,
374 MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB);
375 (void) simple_mdio_write(cphy,
376 MV88E1XXX_EXTENDED_REGISTER, 0x8004);
377 }
378 (void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */
379
380 /* LED */
381 if (is_T2(adapter)) {
382 (void) simple_mdio_write(cphy,
383 MV88E1XXX_LED_CONTROL_REGISTER, 0x1);
384 }
385
386 return cphy;
387}
388
389static int mv88e1xxx_phy_reset(adapter_t* adapter)
390{
391 return 0;
392}
393
394struct gphy t1_mv88e1xxx_ops = {
395 mv88e1xxx_phy_create,
396 mv88e1xxx_phy_reset
397};
diff --git a/drivers/net/chelsio/mv88e1xxx.h b/drivers/net/chelsio/mv88e1xxx.h
new file mode 100644
index 000000000000..967cc4286359
--- /dev/null
+++ b/drivers/net/chelsio/mv88e1xxx.h
@@ -0,0 +1,127 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */
2#ifndef CHELSIO_MV8E1XXX_H
3#define CHELSIO_MV8E1XXX_H
4
5#ifndef BMCR_SPEED1000
6# define BMCR_SPEED1000 0x40
7#endif
8
9#ifndef ADVERTISE_PAUSE
10# define ADVERTISE_PAUSE 0x400
11#endif
12#ifndef ADVERTISE_PAUSE_ASYM
13# define ADVERTISE_PAUSE_ASYM 0x800
14#endif
15
16/* Gigabit MII registers */
17#define MII_GBCR 9 /* 1000Base-T control register */
18#define MII_GBSR 10 /* 1000Base-T status register */
19
20/* 1000Base-T control register fields */
21#define GBCR_ADV_1000HALF 0x100
22#define GBCR_ADV_1000FULL 0x200
23#define GBCR_PREFER_MASTER 0x400
24#define GBCR_MANUAL_AS_MASTER 0x800
25#define GBCR_MANUAL_CONFIG_ENABLE 0x1000
26
27/* 1000Base-T status register fields */
28#define GBSR_LP_1000HALF 0x400
29#define GBSR_LP_1000FULL 0x800
30#define GBSR_REMOTE_OK 0x1000
31#define GBSR_LOCAL_OK 0x2000
32#define GBSR_LOCAL_MASTER 0x4000
33#define GBSR_MASTER_FAULT 0x8000
34
35/* Marvell PHY interrupt status bits. */
36#define MV88E1XXX_INTR_JABBER 0x0001
37#define MV88E1XXX_INTR_POLARITY_CHNG 0x0002
38#define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
39#define MV88E1XXX_INTR_DOWNSHIFT 0x0020
40#define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040
41#define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
42#define MV88E1XXX_INTR_FALSE_CARRIER 0x0100
43#define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200
44#define MV88E1XXX_INTR_LINK_CHNG 0x0400
45#define MV88E1XXX_INTR_AUTONEG_DONE 0x0800
46#define MV88E1XXX_INTR_PAGE_RECV 0x1000
47#define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000
48#define MV88E1XXX_INTR_SPEED_CHNG 0x4000
49#define MV88E1XXX_INTR_AUTONEG_ERR 0x8000
50
51/* Marvell PHY specific registers. */
52#define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16
53#define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17
54#define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18
55#define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19
56#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20
57#define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21
58#define MV88E1XXX_RES_REGISTER 22
59#define MV88E1XXX_GLOBAL_STATUS_REGISTER 23
60#define MV88E1XXX_LED_CONTROL_REGISTER 24
61#define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25
62#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26
63#define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27
64#define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28
65#define MV88E1XXX_EXTENDED_ADDR_REGISTER 29
66#define MV88E1XXX_EXTENDED_REGISTER 30
67
68/* PHY specific control register fields */
69#define S_PSCR_MDI_XOVER_MODE 5
70#define M_PSCR_MDI_XOVER_MODE 0x3
71#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
72#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
73
74/* Extended PHY specific control register fields */
75#define S_DOWNSHIFT_ENABLE 8
76#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
77
78#define S_DOWNSHIFT_CNT 9
79#define M_DOWNSHIFT_CNT 0x7
80#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
81#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
82
83/* PHY specific status register fields */
84#define S_PSSR_JABBER 0
85#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
86
87#define S_PSSR_POLARITY 1
88#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
89
90#define S_PSSR_RX_PAUSE 2
91#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
92
93#define S_PSSR_TX_PAUSE 3
94#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
95
96#define S_PSSR_ENERGY_DETECT 4
97#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
98
99#define S_PSSR_DOWNSHIFT_STATUS 5
100#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
101
102#define S_PSSR_MDI 6
103#define V_PSSR_MDI (1 << S_PSSR_MDI)
104
105#define S_PSSR_CABLE_LEN 7
106#define M_PSSR_CABLE_LEN 0x7
107#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
108#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
109
110#define S_PSSR_LINK 10
111#define V_PSSR_LINK (1 << S_PSSR_LINK)
112
113#define S_PSSR_STATUS_RESOLVED 11
114#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
115
116#define S_PSSR_PAGE_RECEIVED 12
117#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
118
119#define S_PSSR_DUPLEX 13
120#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
121
122#define S_PSSR_SPEED 14
123#define M_PSSR_SPEED 0x3
124#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
125#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
126
127#endif
diff --git a/drivers/net/chelsio/mv88x201x.c b/drivers/net/chelsio/mv88x201x.c
index db5034282782..c8e89480d906 100644
--- a/drivers/net/chelsio/mv88x201x.c
+++ b/drivers/net/chelsio/mv88x201x.c
@@ -85,29 +85,33 @@ static int mv88x201x_reset(struct cphy *cphy, int wait)
85 85
86static int mv88x201x_interrupt_enable(struct cphy *cphy) 86static int mv88x201x_interrupt_enable(struct cphy *cphy)
87{ 87{
88 u32 elmer;
89
90 /* Enable PHY LASI interrupts. */ 88 /* Enable PHY LASI interrupts. */
91 mdio_write(cphy, 0x1, 0x9002, 0x1); 89 mdio_write(cphy, 0x1, 0x9002, 0x1);
92 90
93 /* Enable Marvell interrupts through Elmer0. */ 91 /* Enable Marvell interrupts through Elmer0. */
94 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); 92 if (t1_is_asic(cphy->adapter)) {
95 elmer |= ELMER0_GP_BIT6; 93 u32 elmer;
96 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); 94
95 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
96 elmer |= ELMER0_GP_BIT6;
97 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
98 }
97 return 0; 99 return 0;
98} 100}
99 101
100static int mv88x201x_interrupt_disable(struct cphy *cphy) 102static int mv88x201x_interrupt_disable(struct cphy *cphy)
101{ 103{
102 u32 elmer;
103
104 /* Disable PHY LASI interrupts. */ 104 /* Disable PHY LASI interrupts. */
105 mdio_write(cphy, 0x1, 0x9002, 0x0); 105 mdio_write(cphy, 0x1, 0x9002, 0x0);
106 106
107 /* Disable Marvell interrupts through Elmer0. */ 107 /* Disable Marvell interrupts through Elmer0. */
108 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); 108 if (t1_is_asic(cphy->adapter)) {
109 elmer &= ~ELMER0_GP_BIT6; 109 u32 elmer;
110 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); 110
111 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
112 elmer &= ~ELMER0_GP_BIT6;
113 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
114 }
111 return 0; 115 return 0;
112} 116}
113 117
@@ -140,9 +144,11 @@ static int mv88x201x_interrupt_clear(struct cphy *cphy)
140#endif 144#endif
141 145
142 /* Clear Marvell interrupts through Elmer0. */ 146 /* Clear Marvell interrupts through Elmer0. */
143 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); 147 if (t1_is_asic(cphy->adapter)) {
144 elmer |= ELMER0_GP_BIT6; 148 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
145 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); 149 elmer |= ELMER0_GP_BIT6;
150 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
151 }
146 return 0; 152 return 0;
147} 153}
148 154
@@ -205,11 +211,11 @@ static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr,
205 struct mdio_ops *mdio_ops) 211 struct mdio_ops *mdio_ops)
206{ 212{
207 u32 val; 213 u32 val;
208 struct cphy *cphy = kmalloc(sizeof(*cphy), GFP_KERNEL); 214 struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
209 215
210 if (!cphy) 216 if (!cphy)
211 return NULL; 217 return NULL;
212 memset(cphy, 0, sizeof(*cphy)); 218
213 cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops); 219 cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops);
214 220
215 /* Commands the PHY to enable XFP's clock. */ 221 /* Commands the PHY to enable XFP's clock. */
diff --git a/drivers/net/chelsio/my3126.c b/drivers/net/chelsio/my3126.c
new file mode 100644
index 000000000000..0b90014d5b3e
--- /dev/null
+++ b/drivers/net/chelsio/my3126.c
@@ -0,0 +1,204 @@
1/* $Date: 2005/11/12 02:13:49 $ $RCSfile: my3126.c,v $ $Revision: 1.15 $ */
2#include "cphy.h"
3#include "elmer0.h"
4#include "suni1x10gexp_regs.h"
5
6/* Port Reset */
7static int my3126_reset(struct cphy *cphy, int wait)
8{
9 /*
10 * This can be done through registers. It is not required since
11 * a full chip reset is used.
12 */
13 return (0);
14}
15
16static int my3126_interrupt_enable(struct cphy *cphy)
17{
18 schedule_delayed_work(&cphy->phy_update, HZ/30);
19 t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo);
20 return (0);
21}
22
23static int my3126_interrupt_disable(struct cphy *cphy)
24{
25 cancel_rearming_delayed_work(&cphy->phy_update);
26 return (0);
27}
28
29static int my3126_interrupt_clear(struct cphy *cphy)
30{
31 return (0);
32}
33
34#define OFFSET(REG_ADDR) (REG_ADDR << 2)
35
36static int my3126_interrupt_handler(struct cphy *cphy)
37{
38 u32 val;
39 u16 val16;
40 u16 status;
41 u32 act_count;
42 adapter_t *adapter;
43 adapter = cphy->adapter;
44
45 if (cphy->count == 50) {
46 mdio_read(cphy, 0x1, 0x1, &val);
47 val16 = (u16) val;
48 status = cphy->bmsr ^ val16;
49
50 if (status & BMSR_LSTATUS)
51 t1_link_changed(adapter, 0);
52 cphy->bmsr = val16;
53
54 /* We have only enabled link change interrupts so it
55 must be that
56 */
57 cphy->count = 0;
58 }
59
60 t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),
61 SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
62 t1_tpi_read(adapter,
63 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count);
64 t1_tpi_read(adapter,
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
66 act_count += val;
67
68 /* Populate elmer_gpo with the register value */
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
70 cphy->elmer_gpo = val;
71
72 if ( (val & (1 << 8)) || (val & (1 << 19)) ||
73 (cphy->act_count == act_count) || cphy->act_on ) {
74 if (is_T2(adapter))
75 val |= (1 << 9);
76 else if (t1_is_T1B(adapter))
77 val |= (1 << 20);
78 cphy->act_on = 0;
79 } else {
80 if (is_T2(adapter))
81 val &= ~(1 << 9);
82 else if (t1_is_T1B(adapter))
83 val &= ~(1 << 20);
84 cphy->act_on = 1;
85 }
86
87 t1_tpi_write(adapter, A_ELMER0_GPO, val);
88
89 cphy->elmer_gpo = val;
90 cphy->act_count = act_count;
91 cphy->count++;
92
93 return cphy_cause_link_change;
94}
95
96static void my3216_poll(void *arg)
97{
98 my3126_interrupt_handler(arg);
99}
100
101static int my3126_set_loopback(struct cphy *cphy, int on)
102{
103 return (0);
104}
105
106/* To check the activity LED */
107static int my3126_get_link_status(struct cphy *cphy,
108 int *link_ok, int *speed, int *duplex, int *fc)
109{
110 u32 val;
111 u16 val16;
112 adapter_t *adapter;
113
114 adapter = cphy->adapter;
115 mdio_read(cphy, 0x1, 0x1, &val);
116 val16 = (u16) val;
117
118 /* Populate elmer_gpo with the register value */
119 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
120 cphy->elmer_gpo = val;
121
122 *link_ok = (val16 & BMSR_LSTATUS);
123
124 if (*link_ok) {
125 /* Turn on the LED. */
126 if (is_T2(adapter))
127 val &= ~(1 << 8);
128 else if (t1_is_T1B(adapter))
129 val &= ~(1 << 19);
130 } else {
131 /* Turn off the LED. */
132 if (is_T2(adapter))
133 val |= (1 << 8);
134 else if (t1_is_T1B(adapter))
135 val |= (1 << 19);
136 }
137
138 t1_tpi_write(adapter, A_ELMER0_GPO, val);
139 cphy->elmer_gpo = val;
140 *speed = SPEED_10000;
141 *duplex = DUPLEX_FULL;
142
143 /* need to add flow control */
144 if (fc)
145 *fc = PAUSE_RX | PAUSE_TX;
146
147 return (0);
148}
149
150static void my3126_destroy(struct cphy *cphy)
151{
152 kfree(cphy);
153}
154
155static struct cphy_ops my3126_ops = {
156 .destroy = my3126_destroy,
157 .reset = my3126_reset,
158 .interrupt_enable = my3126_interrupt_enable,
159 .interrupt_disable = my3126_interrupt_disable,
160 .interrupt_clear = my3126_interrupt_clear,
161 .interrupt_handler = my3126_interrupt_handler,
162 .get_link_status = my3126_get_link_status,
163 .set_loopback = my3126_set_loopback,
164};
165
166static struct cphy *my3126_phy_create(adapter_t *adapter,
167 int phy_addr, struct mdio_ops *mdio_ops)
168{
169 struct cphy *cphy = kzalloc(sizeof (*cphy), GFP_KERNEL);
170
171 if (cphy)
172 cphy_init(cphy, adapter, phy_addr, &my3126_ops, mdio_ops);
173
174 INIT_WORK(&cphy->phy_update, my3216_poll, cphy);
175 cphy->bmsr = 0;
176
177 return (cphy);
178}
179
180/* Chip Reset */
181static int my3126_phy_reset(adapter_t * adapter)
182{
183 u32 val;
184
185 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
186 val &= ~4;
187 t1_tpi_write(adapter, A_ELMER0_GPO, val);
188 msleep(100);
189
190 t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
191 msleep(1000);
192
193 /* Now lets enable the Laser. Delay 100us */
194 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
195 val |= 0x8000;
196 t1_tpi_write(adapter, A_ELMER0_GPO, val);
197 udelay(100);
198 return (0);
199}
200
201struct gphy t1_my3126_ops = {
202 my3126_phy_create,
203 my3126_phy_reset
204};
diff --git a/drivers/net/chelsio/pm3393.c b/drivers/net/chelsio/pm3393.c
index 04a1404fc65e..63cabeb98afe 100644
--- a/drivers/net/chelsio/pm3393.c
+++ b/drivers/net/chelsio/pm3393.c
@@ -43,21 +43,7 @@
43#include "elmer0.h" 43#include "elmer0.h"
44#include "suni1x10gexp_regs.h" 44#include "suni1x10gexp_regs.h"
45 45
46/* 802.3ae 10Gb/s MDIO Manageable Device(MMD) 46#include <linux/crc32.h>
47 */
48enum {
49 MMD_RESERVED,
50 MMD_PMAPMD,
51 MMD_WIS,
52 MMD_PCS,
53 MMD_PHY_XGXS, /* XGMII Extender Sublayer */
54 MMD_DTE_XGXS,
55};
56
57enum {
58 PHY_XGXS_CTRL_1,
59 PHY_XGXS_STATUS_1
60};
61 47
62#define OFFSET(REG_ADDR) (REG_ADDR << 2) 48#define OFFSET(REG_ADDR) (REG_ADDR << 2)
63 49
@@ -88,6 +74,8 @@ enum { /* RMON registers */
88 RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW, 74 RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
89 RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW, 75 RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
90 RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW, 76 RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
77 RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
78 RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
91 79
92 TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW, 80 TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
93 TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW, 81 TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
@@ -95,7 +83,9 @@ enum { /* RMON registers */
95 TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW, 83 TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
96 TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW, 84 TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
97 TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW, 85 TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
98 TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 86 TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
87 TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
88 TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
99}; 89};
100 90
101struct _cmac_instance { 91struct _cmac_instance {
@@ -124,12 +114,12 @@ static int pm3393_reset(struct cmac *cmac)
124 114
125/* 115/*
126 * Enable interrupts for the PM3393 116 * Enable interrupts for the PM3393
127 117 *
128 1. Enable PM3393 BLOCK interrupts. 118 * 1. Enable PM3393 BLOCK interrupts.
129 2. Enable PM3393 Master Interrupt bit(INTE) 119 * 2. Enable PM3393 Master Interrupt bit(INTE)
130 3. Enable ELMER's PM3393 bit. 120 * 3. Enable ELMER's PM3393 bit.
131 4. Enable Terminator external interrupt. 121 * 4. Enable Terminator external interrupt.
132*/ 122 */
133static int pm3393_interrupt_enable(struct cmac *cmac) 123static int pm3393_interrupt_enable(struct cmac *cmac)
134{ 124{
135 u32 pl_intr; 125 u32 pl_intr;
@@ -257,14 +247,12 @@ static int pm3393_interrupt_clear(struct cmac *cmac)
257static int pm3393_interrupt_handler(struct cmac *cmac) 247static int pm3393_interrupt_handler(struct cmac *cmac)
258{ 248{
259 u32 master_intr_status; 249 u32 master_intr_status;
260/* 250
261 1. Read master interrupt register.
262 2. Read BLOCK's interrupt status registers.
263 3. Handle BLOCK interrupts.
264*/
265 /* Read the master interrupt status register. */ 251 /* Read the master interrupt status register. */
266 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, 252 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
267 &master_intr_status); 253 &master_intr_status);
254 CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n",
255 master_intr_status);
268 256
269 /* TBD XXX Lets just clear everything for now */ 257 /* TBD XXX Lets just clear everything for now */
270 pm3393_interrupt_clear(cmac); 258 pm3393_interrupt_clear(cmac);
@@ -307,11 +295,7 @@ static int pm3393_enable_port(struct cmac *cmac, int which)
307 * The PHY doesn't give us link status indication on its own so have 295 * The PHY doesn't give us link status indication on its own so have
308 * the link management code query it instead. 296 * the link management code query it instead.
309 */ 297 */
310 { 298 t1_link_changed(cmac->adapter, 0);
311 extern void link_changed(adapter_t *adapter, int port_id);
312
313 link_changed(cmac->adapter, 0);
314 }
315 return 0; 299 return 0;
316} 300}
317 301
@@ -363,33 +347,6 @@ static int pm3393_set_mtu(struct cmac *cmac, int mtu)
363 return 0; 347 return 0;
364} 348}
365 349
366static u32 calc_crc(u8 *b, int len)
367{
368 int i;
369 u32 crc = (u32)~0;
370
371 /* calculate crc one bit at a time */
372 while (len--) {
373 crc ^= *b++;
374 for (i = 0; i < 8; i++) {
375 if (crc & 0x1)
376 crc = (crc >> 1) ^ 0xedb88320;
377 else
378 crc = (crc >> 1);
379 }
380 }
381
382 /* reverse bits */
383 crc = ((crc >> 4) & 0x0f0f0f0f) | ((crc << 4) & 0xf0f0f0f0);
384 crc = ((crc >> 2) & 0x33333333) | ((crc << 2) & 0xcccccccc);
385 crc = ((crc >> 1) & 0x55555555) | ((crc << 1) & 0xaaaaaaaa);
386 /* swap bytes */
387 crc = (crc >> 16) | (crc << 16);
388 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
389
390 return crc;
391}
392
393static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm) 350static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
394{ 351{
395 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX; 352 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
@@ -423,7 +380,7 @@ static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
423 u16 mc_filter[4] = { 0, }; 380 u16 mc_filter[4] = { 0, };
424 381
425 while ((addr = t1_get_next_mcaddr(rm))) { 382 while ((addr = t1_get_next_mcaddr(rm))) {
426 bit = (calc_crc(addr, ETH_ALEN) >> 23) & 0x3f; /* bit[23:28] */ 383 bit = (ether_crc(ETH_ALEN, addr) >> 23) & 0x3f; /* bit[23:28] */
427 mc_filter[bit >> 4] |= 1 << (bit & 0xf); 384 mc_filter[bit >> 4] |= 1 << (bit & 0xf);
428 } 385 }
429 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]); 386 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
@@ -471,20 +428,29 @@ static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
471 return 0; 428 return 0;
472} 429}
473 430
431static void pm3393_rmon_update(struct adapter *adapter, u32 offs, u64 *val,
432 int over)
433{
434 u32 val0, val1, val2;
435
436 t1_tpi_read(adapter, offs, &val0);
437 t1_tpi_read(adapter, offs + 4, &val1);
438 t1_tpi_read(adapter, offs + 8, &val2);
439
440 *val &= ~0ull << 40;
441 *val |= val0 & 0xffff;
442 *val |= (val1 & 0xffff) << 16;
443 *val |= (u64)(val2 & 0xff) << 32;
444
445 if (over)
446 *val += 1ull << 40;
447}
448
474#define RMON_UPDATE(mac, name, stat_name) \ 449#define RMON_UPDATE(mac, name, stat_name) \
475 { \ 450 pm3393_rmon_update((mac)->adapter, OFFSET(name), \
476 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \ 451 &(mac)->stats.stat_name, \
477 t1_tpi_read((mac)->adapter, OFFSET(((name)+1)), &val1); \ 452 (ro &((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2)))
478 t1_tpi_read((mac)->adapter, OFFSET(((name)+2)), &val2); \ 453
479 (mac)->stats.stat_name = ((u64)val0 & 0xffff) | \
480 (((u64)val1 & 0xffff) << 16) | \
481 (((u64)val2 & 0xff) << 32) | \
482 ((mac)->stats.stat_name & \
483 (~(u64)0 << 40)); \
484 if (ro & \
485 ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2)) \
486 (mac)->stats.stat_name += ((u64)1 << 40); \
487 }
488 454
489static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac, 455static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
490 int flag) 456 int flag)
@@ -519,6 +485,8 @@ static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
519 RMON_UPDATE(mac, RxJabbers, RxJabberErrors); 485 RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
520 RMON_UPDATE(mac, RxFragments, RxRuntErrors); 486 RMON_UPDATE(mac, RxFragments, RxRuntErrors);
521 RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors); 487 RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
488 RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
489 RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
522 490
523 /* Tx stats */ 491 /* Tx stats */
524 RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK); 492 RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
@@ -529,6 +497,8 @@ static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
529 RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK); 497 RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
530 RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK); 498 RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
531 RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames); 499 RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
500 RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
501 RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
532 502
533 return &mac->stats; 503 return &mac->stats;
534} 504}
@@ -631,10 +601,9 @@ static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
631{ 601{
632 struct cmac *cmac; 602 struct cmac *cmac;
633 603
634 cmac = kmalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL); 604 cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
635 if (!cmac) 605 if (!cmac)
636 return NULL; 606 return NULL;
637 memset(cmac, 0, sizeof(*cmac));
638 607
639 cmac->ops = &pm3393_ops; 608 cmac->ops = &pm3393_ops;
640 cmac->instance = (cmac_instance *) (cmac + 1); 609 cmac->instance = (cmac_instance *) (cmac + 1);
@@ -815,6 +784,12 @@ static int pm3393_mac_reset(adapter_t * adapter)
815 784
816 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock 785 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
817 && is_xaui_mabc_pll_locked); 786 && is_xaui_mabc_pll_locked);
787
788 CH_DBG(adapter, HW,
789 "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
790 "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
791 i, is_pl4_reset_finished, val, is_pl4_outof_lock,
792 is_xaui_mabc_pll_locked);
818 } 793 }
819 return successful_reset ? 0 : 1; 794 return successful_reset ? 0 : 1;
820} 795}
diff --git a/drivers/net/chelsio/regs.h b/drivers/net/chelsio/regs.h
index b90e11f40d1f..c80bf4d6d0a6 100644
--- a/drivers/net/chelsio/regs.h
+++ b/drivers/net/chelsio/regs.h
@@ -71,6 +71,10 @@
71#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) 71#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
72#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) 72#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
73 73
74#define S_DISABLE_CMDQ0_GTS 8
75#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
76#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)
77
74#define S_DISABLE_CMDQ1_GTS 9 78#define S_DISABLE_CMDQ1_GTS 9
75#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) 79#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
76#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U) 80#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
@@ -87,12 +91,18 @@
87#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN) 91#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
88#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U) 92#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
89 93
94#define S_FL_SELECTION_CRITERIA 13
95#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
96#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)
97
90#define S_ISCSI_COALESCE 14 98#define S_ISCSI_COALESCE 14
91#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE) 99#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
92#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U) 100#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
93 101
94#define S_RX_PKT_OFFSET 15 102#define S_RX_PKT_OFFSET 15
103#define M_RX_PKT_OFFSET 0x7
95#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET) 104#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
105#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
96 106
97#define S_VLAN_XTRACT 18 107#define S_VLAN_XTRACT 18
98#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT) 108#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
@@ -108,16 +118,114 @@
108#define A_SG_FL1BASELWR 0x20 118#define A_SG_FL1BASELWR 0x20
109#define A_SG_FL1BASEUPR 0x24 119#define A_SG_FL1BASEUPR 0x24
110#define A_SG_CMD0SIZE 0x28 120#define A_SG_CMD0SIZE 0x28
121
122#define S_CMDQ0_SIZE 0
123#define M_CMDQ0_SIZE 0x1ffff
124#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
125#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
126
111#define A_SG_FL0SIZE 0x2c 127#define A_SG_FL0SIZE 0x2c
128
129#define S_FL0_SIZE 0
130#define M_FL0_SIZE 0x1ffff
131#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
132#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
133
112#define A_SG_RSPSIZE 0x30 134#define A_SG_RSPSIZE 0x30
135
136#define S_RESPQ_SIZE 0
137#define M_RESPQ_SIZE 0x1ffff
138#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
139#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
140
113#define A_SG_RSPBASELWR 0x34 141#define A_SG_RSPBASELWR 0x34
114#define A_SG_RSPBASEUPR 0x38 142#define A_SG_RSPBASEUPR 0x38
115#define A_SG_FLTHRESHOLD 0x3c 143#define A_SG_FLTHRESHOLD 0x3c
144
145#define S_FL_THRESHOLD 0
146#define M_FL_THRESHOLD 0xffff
147#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
148#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
149
116#define A_SG_RSPQUEUECREDIT 0x40 150#define A_SG_RSPQUEUECREDIT 0x40
151
152#define S_RESPQ_CREDIT 0
153#define M_RESPQ_CREDIT 0x1ffff
154#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
155#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
156
117#define A_SG_SLEEPING 0x48 157#define A_SG_SLEEPING 0x48
158
159#define S_SLEEPING 0
160#define M_SLEEPING 0xffff
161#define V_SLEEPING(x) ((x) << S_SLEEPING)
162#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
163
118#define A_SG_INTRTIMER 0x4c 164#define A_SG_INTRTIMER 0x4c
165
166#define S_INTERRUPT_TIMER_COUNT 0
167#define M_INTERRUPT_TIMER_COUNT 0xffffff
168#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
169#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
170
171#define A_SG_CMD0PTR 0x50
172
173#define S_CMDQ0_POINTER 0
174#define M_CMDQ0_POINTER 0xffff
175#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
176#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
177
178#define S_CURRENT_GENERATION_BIT 16
179#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
180#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)
181
182#define A_SG_CMD1PTR 0x54
183
184#define S_CMDQ1_POINTER 0
185#define M_CMDQ1_POINTER 0xffff
186#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
187#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
188
189#define A_SG_FL0PTR 0x58
190
191#define S_FL0_POINTER 0
192#define M_FL0_POINTER 0xffff
193#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
194#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
195
196#define A_SG_FL1PTR 0x5c
197
198#define S_FL1_POINTER 0
199#define M_FL1_POINTER 0xffff
200#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
201#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
202
203#define A_SG_VERSION 0x6c
204
205#define S_DAY 0
206#define M_DAY 0x1f
207#define V_DAY(x) ((x) << S_DAY)
208#define G_DAY(x) (((x) >> S_DAY) & M_DAY)
209
210#define S_MONTH 5
211#define M_MONTH 0xf
212#define V_MONTH(x) ((x) << S_MONTH)
213#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
214
119#define A_SG_CMD1SIZE 0xb0 215#define A_SG_CMD1SIZE 0xb0
216
217#define S_CMDQ1_SIZE 0
218#define M_CMDQ1_SIZE 0x1ffff
219#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
220#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
221
120#define A_SG_FL1SIZE 0xb4 222#define A_SG_FL1SIZE 0xb4
223
224#define S_FL1_SIZE 0
225#define M_FL1_SIZE 0x1ffff
226#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
227#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
228
121#define A_SG_INT_ENABLE 0xb8 229#define A_SG_INT_ENABLE 0xb8
122 230
123#define S_RESPQ_EXHAUSTED 0 231#define S_RESPQ_EXHAUSTED 0
@@ -144,21 +252,369 @@
144#define A_SG_RESPACCUTIMER 0xc0 252#define A_SG_RESPACCUTIMER 0xc0
145 253
146/* MC3 registers */ 254/* MC3 registers */
255#define A_MC3_CFG 0x100
256
257#define S_CLK_ENABLE 0
258#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
259#define F_CLK_ENABLE V_CLK_ENABLE(1U)
147 260
148#define S_READY 1 261#define S_READY 1
149#define V_READY(x) ((x) << S_READY) 262#define V_READY(x) ((x) << S_READY)
150#define F_READY V_READY(1U) 263#define F_READY V_READY(1U)
151 264
152/* MC4 registers */ 265#define S_READ_TO_WRITE_DELAY 2
266#define M_READ_TO_WRITE_DELAY 0x7
267#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
268#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
269
270#define S_WRITE_TO_READ_DELAY 5
271#define M_WRITE_TO_READ_DELAY 0x7
272#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
273#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
153 274
275#define S_MC3_BANK_CYCLE 8
276#define M_MC3_BANK_CYCLE 0xf
277#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
278#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
279
280#define S_REFRESH_CYCLE 12
281#define M_REFRESH_CYCLE 0xf
282#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
283#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
284
285#define S_PRECHARGE_CYCLE 16
286#define M_PRECHARGE_CYCLE 0x3
287#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
288#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
289
290#define S_ACTIVE_TO_READ_WRITE_DELAY 18
291#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
292#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)
293
294#define S_ACTIVE_TO_PRECHARGE_DELAY 19
295#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7
296#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
297#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
298
299#define S_WRITE_RECOVERY_DELAY 22
300#define M_WRITE_RECOVERY_DELAY 0x3
301#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
302#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
303
304#define S_DENSITY 24
305#define M_DENSITY 0x3
306#define V_DENSITY(x) ((x) << S_DENSITY)
307#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
308
309#define S_ORGANIZATION 26
310#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
311#define F_ORGANIZATION V_ORGANIZATION(1U)
312
313#define S_BANKS 27
314#define V_BANKS(x) ((x) << S_BANKS)
315#define F_BANKS V_BANKS(1U)
316
317#define S_UNREGISTERED 28
318#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
319#define F_UNREGISTERED V_UNREGISTERED(1U)
320
321#define S_MC3_WIDTH 29
322#define M_MC3_WIDTH 0x3
323#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
324#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
325
326#define S_MC3_SLOW 31
327#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
328#define F_MC3_SLOW V_MC3_SLOW(1U)
329
330#define A_MC3_MODE 0x104
331
332#define S_MC3_MODE 0
333#define M_MC3_MODE 0x3fff
334#define V_MC3_MODE(x) ((x) << S_MC3_MODE)
335#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
336
337#define S_BUSY 31
338#define V_BUSY(x) ((x) << S_BUSY)
339#define F_BUSY V_BUSY(1U)
340
341#define A_MC3_EXT_MODE 0x108
342
343#define S_MC3_EXTENDED_MODE 0
344#define M_MC3_EXTENDED_MODE 0x3fff
345#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
346#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
347
348#define A_MC3_PRECHARG 0x10c
349#define A_MC3_REFRESH 0x110
350
351#define S_REFRESH_ENABLE 0
352#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
353#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)
354
355#define S_REFRESH_DIVISOR 1
356#define M_REFRESH_DIVISOR 0x3fff
357#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
358#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
359
360#define A_MC3_STROBE 0x114
361
362#define S_MASTER_DLL_RESET 0
363#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
364#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)
365
366#define S_MASTER_DLL_TAP_COUNT 1
367#define M_MASTER_DLL_TAP_COUNT 0xff
368#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
369#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
370
371#define S_MASTER_DLL_LOCKED 9
372#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
373#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)
374
375#define S_MASTER_DLL_MAX_TAP_COUNT 10
376#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
377#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)
378
379#define S_MASTER_DLL_TAP_COUNT_OFFSET 11
380#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f
381#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
382#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
383
384#define S_SLAVE_DLL_RESET 11
385#define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
386#define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U)
387
388#define S_SLAVE_DLL_DELTA 12
389#define M_SLAVE_DLL_DELTA 0xf
390#define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
391#define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
392
393#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17
394#define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f
395#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
396#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
397
398#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23
399#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
400#define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
401
402#define S_SLAVE_DELAY_LINE_TAP_COUNT 24
403#define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f
404#define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
405#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
406
407#define A_MC3_ECC_CNTL 0x118
408
409#define S_ECC_GENERATION_ENABLE 0
410#define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
411#define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U)
412
413#define S_ECC_CHECK_ENABLE 1
414#define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
415#define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U)
416
417#define S_CORRECTABLE_ERROR_COUNT 2
418#define M_CORRECTABLE_ERROR_COUNT 0xff
419#define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
420#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
421
422#define S_UNCORRECTABLE_ERROR_COUNT 10
423#define M_UNCORRECTABLE_ERROR_COUNT 0xff
424#define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
425#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
426
427#define A_MC3_CE_ADDR 0x11c
428
429#define S_MC3_CE_ADDR 4
430#define M_MC3_CE_ADDR 0xfffffff
431#define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
432#define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
433
434#define A_MC3_CE_DATA0 0x120
435#define A_MC3_CE_DATA1 0x124
436#define A_MC3_CE_DATA2 0x128
437#define A_MC3_CE_DATA3 0x12c
438#define A_MC3_CE_DATA4 0x130
439#define A_MC3_UE_ADDR 0x134
440
441#define S_MC3_UE_ADDR 4
442#define M_MC3_UE_ADDR 0xfffffff
443#define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
444#define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
445
446#define A_MC3_UE_DATA0 0x138
447#define A_MC3_UE_DATA1 0x13c
448#define A_MC3_UE_DATA2 0x140
449#define A_MC3_UE_DATA3 0x144
450#define A_MC3_UE_DATA4 0x148
451#define A_MC3_BD_ADDR 0x14c
452#define A_MC3_BD_DATA0 0x150
453#define A_MC3_BD_DATA1 0x154
454#define A_MC3_BD_DATA2 0x158
455#define A_MC3_BD_DATA3 0x15c
456#define A_MC3_BD_DATA4 0x160
457#define A_MC3_BD_OP 0x164
458
459#define S_BACK_DOOR_OPERATION 0
460#define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
461#define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U)
462
463#define A_MC3_BIST_ADDR_BEG 0x168
464#define A_MC3_BIST_ADDR_END 0x16c
465#define A_MC3_BIST_DATA 0x170
466#define A_MC3_BIST_OP 0x174
467
468#define S_OP 0
469#define V_OP(x) ((x) << S_OP)
470#define F_OP V_OP(1U)
471
472#define S_DATA_PATTERN 1
473#define M_DATA_PATTERN 0x3
474#define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
475#define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
476
477#define S_CONTINUOUS 3
478#define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
479#define F_CONTINUOUS V_CONTINUOUS(1U)
480
481#define A_MC3_INT_ENABLE 0x178
482
483#define S_MC3_CORR_ERR 0
484#define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
485#define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U)
486
487#define S_MC3_UNCORR_ERR 1
488#define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
489#define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U)
490
491#define S_MC3_PARITY_ERR 2
492#define M_MC3_PARITY_ERR 0xff
493#define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
494#define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
495
496#define S_MC3_ADDR_ERR 10
497#define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
498#define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U)
499
500#define A_MC3_INT_CAUSE 0x17c
501
502/* MC4 registers */
154#define A_MC4_CFG 0x180 503#define A_MC4_CFG 0x180
504
505#define S_POWER_UP 0
506#define V_POWER_UP(x) ((x) << S_POWER_UP)
507#define F_POWER_UP V_POWER_UP(1U)
508
509#define S_MC4_BANK_CYCLE 8
510#define M_MC4_BANK_CYCLE 0x7
511#define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
512#define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
513
514#define S_MC4_NARROW 24
515#define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
516#define F_MC4_NARROW V_MC4_NARROW(1U)
517
155#define S_MC4_SLOW 25 518#define S_MC4_SLOW 25
156#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW) 519#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
157#define F_MC4_SLOW V_MC4_SLOW(1U) 520#define F_MC4_SLOW V_MC4_SLOW(1U)
158 521
159/* TPI registers */ 522#define S_MC4A_WIDTH 24
523#define M_MC4A_WIDTH 0x3
524#define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
525#define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
526
527#define S_MC4A_SLOW 26
528#define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
529#define F_MC4A_SLOW V_MC4A_SLOW(1U)
530
531#define A_MC4_MODE 0x184
532
533#define S_MC4_MODE 0
534#define M_MC4_MODE 0x7fff
535#define V_MC4_MODE(x) ((x) << S_MC4_MODE)
536#define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
537
538#define A_MC4_EXT_MODE 0x188
539
540#define S_MC4_EXTENDED_MODE 0
541#define M_MC4_EXTENDED_MODE 0x7fff
542#define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
543#define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
544
545#define A_MC4_REFRESH 0x190
546#define A_MC4_STROBE 0x194
547#define A_MC4_ECC_CNTL 0x198
548#define A_MC4_CE_ADDR 0x19c
549
550#define S_MC4_CE_ADDR 4
551#define M_MC4_CE_ADDR 0xffffff
552#define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
553#define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
554
555#define A_MC4_CE_DATA0 0x1a0
556#define A_MC4_CE_DATA1 0x1a4
557#define A_MC4_CE_DATA2 0x1a8
558#define A_MC4_CE_DATA3 0x1ac
559#define A_MC4_CE_DATA4 0x1b0
560#define A_MC4_UE_ADDR 0x1b4
561
562#define S_MC4_UE_ADDR 4
563#define M_MC4_UE_ADDR 0xffffff
564#define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
565#define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
566
567#define A_MC4_UE_DATA0 0x1b8
568#define A_MC4_UE_DATA1 0x1bc
569#define A_MC4_UE_DATA2 0x1c0
570#define A_MC4_UE_DATA3 0x1c4
571#define A_MC4_UE_DATA4 0x1c8
572#define A_MC4_BD_ADDR 0x1cc
573
574#define S_MC4_BACK_DOOR_ADDR 0
575#define M_MC4_BACK_DOOR_ADDR 0xfffffff
576#define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
577#define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
578
579#define A_MC4_BD_DATA0 0x1d0
580#define A_MC4_BD_DATA1 0x1d4
581#define A_MC4_BD_DATA2 0x1d8
582#define A_MC4_BD_DATA3 0x1dc
583#define A_MC4_BD_DATA4 0x1e0
584#define A_MC4_BD_OP 0x1e4
585
586#define S_OPERATION 0
587#define V_OPERATION(x) ((x) << S_OPERATION)
588#define F_OPERATION V_OPERATION(1U)
589
590#define A_MC4_BIST_ADDR_BEG 0x1e8
591#define A_MC4_BIST_ADDR_END 0x1ec
592#define A_MC4_BIST_DATA 0x1f0
593#define A_MC4_BIST_OP 0x1f4
594#define A_MC4_INT_ENABLE 0x1f8
595
596#define S_MC4_CORR_ERR 0
597#define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
598#define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U)
599
600#define S_MC4_UNCORR_ERR 1
601#define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
602#define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U)
603
604#define S_MC4_ADDR_ERR 2
605#define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
606#define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U)
607
608#define A_MC4_INT_CAUSE 0x1fc
160 609
610/* TPI registers */
161#define A_TPI_ADDR 0x280 611#define A_TPI_ADDR 0x280
612
613#define S_TPI_ADDRESS 0
614#define M_TPI_ADDRESS 0xffffff
615#define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
616#define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
617
162#define A_TPI_WR_DATA 0x284 618#define A_TPI_WR_DATA 0x284
163#define A_TPI_RD_DATA 0x288 619#define A_TPI_RD_DATA 0x288
164#define A_TPI_CSR 0x28c 620#define A_TPI_CSR 0x28c
@@ -171,6 +627,10 @@
171#define V_TPIRDY(x) ((x) << S_TPIRDY) 627#define V_TPIRDY(x) ((x) << S_TPIRDY)
172#define F_TPIRDY V_TPIRDY(1U) 628#define F_TPIRDY V_TPIRDY(1U)
173 629
630#define S_INT_DIR 31
631#define V_INT_DIR(x) ((x) << S_INT_DIR)
632#define F_INT_DIR V_INT_DIR(1U)
633
174#define A_TPI_PAR 0x29c 634#define A_TPI_PAR 0x29c
175 635
176#define S_TPIPAR 0 636#define S_TPIPAR 0
@@ -178,14 +638,26 @@
178#define V_TPIPAR(x) ((x) << S_TPIPAR) 638#define V_TPIPAR(x) ((x) << S_TPIPAR)
179#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR) 639#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
180 640
181/* TP registers */
182 641
642/* TP registers */
183#define A_TP_IN_CONFIG 0x300 643#define A_TP_IN_CONFIG 0x300
184 644
645#define S_TP_IN_CSPI_TUNNEL 0
646#define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
647#define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U)
648
649#define S_TP_IN_CSPI_ETHERNET 1
650#define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
651#define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U)
652
185#define S_TP_IN_CSPI_CPL 3 653#define S_TP_IN_CSPI_CPL 3
186#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL) 654#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
187#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U) 655#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
188 656
657#define S_TP_IN_CSPI_POS 4
658#define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
659#define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U)
660
189#define S_TP_IN_CSPI_CHECK_IP_CSUM 5 661#define S_TP_IN_CSPI_CHECK_IP_CSUM 5
190#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM) 662#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
191#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U) 663#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
@@ -194,10 +666,22 @@
194#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM) 666#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
195#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U) 667#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
196 668
669#define S_TP_IN_ESPI_TUNNEL 7
670#define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
671#define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U)
672
197#define S_TP_IN_ESPI_ETHERNET 8 673#define S_TP_IN_ESPI_ETHERNET 8
198#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET) 674#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
199#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U) 675#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
200 676
677#define S_TP_IN_ESPI_CPL 10
678#define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
679#define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U)
680
681#define S_TP_IN_ESPI_POS 11
682#define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
683#define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U)
684
201#define S_TP_IN_ESPI_CHECK_IP_CSUM 12 685#define S_TP_IN_ESPI_CHECK_IP_CSUM 12
202#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM) 686#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
203#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U) 687#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
@@ -212,14 +696,42 @@
212 696
213#define A_TP_OUT_CONFIG 0x304 697#define A_TP_OUT_CONFIG 0x304
214 698
699#define S_TP_OUT_C_ETH 0
700#define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
701#define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U)
702
215#define S_TP_OUT_CSPI_CPL 2 703#define S_TP_OUT_CSPI_CPL 2
216#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL) 704#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
217#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U) 705#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
218 706
707#define S_TP_OUT_CSPI_POS 3
708#define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
709#define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U)
710
711#define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4
712#define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
713#define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
714
715#define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5
716#define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
717#define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
718
219#define S_TP_OUT_ESPI_ETHERNET 6 719#define S_TP_OUT_ESPI_ETHERNET 6
220#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET) 720#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
221#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U) 721#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
222 722
723#define S_TP_OUT_ESPI_TAG_ETHERNET 7
724#define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
725#define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U)
726
727#define S_TP_OUT_ESPI_CPL 8
728#define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
729#define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U)
730
731#define S_TP_OUT_ESPI_POS 9
732#define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
733#define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U)
734
223#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10 735#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
224#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM) 736#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
225#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U) 737#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
@@ -233,6 +745,16 @@
233#define S_IP_TTL 0 745#define S_IP_TTL 0
234#define M_IP_TTL 0xff 746#define M_IP_TTL 0xff
235#define V_IP_TTL(x) ((x) << S_IP_TTL) 747#define V_IP_TTL(x) ((x) << S_IP_TTL)
748#define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
749
750#define S_TCAM_SERVER_REGION_USAGE 8
751#define M_TCAM_SERVER_REGION_USAGE 0x3
752#define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
753#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
754
755#define S_QOS_MAPPING 10
756#define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
757#define F_QOS_MAPPING V_QOS_MAPPING(1U)
236 758
237#define S_TCP_CSUM 11 759#define S_TCP_CSUM 11
238#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM) 760#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
@@ -246,31 +768,476 @@
246#define V_IP_CSUM(x) ((x) << S_IP_CSUM) 768#define V_IP_CSUM(x) ((x) << S_IP_CSUM)
247#define F_IP_CSUM V_IP_CSUM(1U) 769#define F_IP_CSUM V_IP_CSUM(1U)
248 770
771#define S_IP_ID_SPLIT 14
772#define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
773#define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U)
774
249#define S_PATH_MTU 15 775#define S_PATH_MTU 15
250#define V_PATH_MTU(x) ((x) << S_PATH_MTU) 776#define V_PATH_MTU(x) ((x) << S_PATH_MTU)
251#define F_PATH_MTU V_PATH_MTU(1U) 777#define F_PATH_MTU V_PATH_MTU(1U)
252 778
253#define S_5TUPLE_LOOKUP 17 779#define S_5TUPLE_LOOKUP 17
780#define M_5TUPLE_LOOKUP 0x3
254#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP) 781#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
782#define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
783
784#define S_IP_FRAGMENT_DROP 19
785#define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
786#define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U)
787
788#define S_PING_DROP 20
789#define V_PING_DROP(x) ((x) << S_PING_DROP)
790#define F_PING_DROP V_PING_DROP(1U)
791
792#define S_PROTECT_MODE 21
793#define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
794#define F_PROTECT_MODE V_PROTECT_MODE(1U)
795
796#define S_SYN_COOKIE_ALGORITHM 22
797#define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
798#define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U)
799
800#define S_ATTACK_FILTER 23
801#define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
802#define F_ATTACK_FILTER V_ATTACK_FILTER(1U)
803
804#define S_INTERFACE_TYPE 24
805#define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
806#define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U)
807
808#define S_DISABLE_RX_FLOW_CONTROL 25
809#define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
810#define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U)
255 811
256#define S_SYN_COOKIE_PARAMETER 26 812#define S_SYN_COOKIE_PARAMETER 26
813#define M_SYN_COOKIE_PARAMETER 0x3f
257#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER) 814#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
815#define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
816
817#define A_TP_GLOBAL_RX_CREDITS 0x30c
818#define A_TP_CM_SIZE 0x310
819#define A_TP_CM_MM_BASE 0x314
820
821#define S_CM_MEMMGR_BASE 0
822#define M_CM_MEMMGR_BASE 0xfffffff
823#define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
824#define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
825
826#define A_TP_CM_TIMER_BASE 0x318
827
828#define S_CM_TIMER_BASE 0
829#define M_CM_TIMER_BASE 0xfffffff
830#define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
831#define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
832
833#define A_TP_PM_SIZE 0x31c
834#define A_TP_PM_TX_BASE 0x320
835#define A_TP_PM_DEFRAG_BASE 0x324
836#define A_TP_PM_RX_BASE 0x328
837#define A_TP_PM_RX_PG_SIZE 0x32c
838#define A_TP_PM_RX_MAX_PGS 0x330
839#define A_TP_PM_TX_PG_SIZE 0x334
840#define A_TP_PM_TX_MAX_PGS 0x338
841#define A_TP_TCP_OPTIONS 0x340
842
843#define S_TIMESTAMP 0
844#define M_TIMESTAMP 0x3
845#define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
846#define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
847
848#define S_WINDOW_SCALE 2
849#define M_WINDOW_SCALE 0x3
850#define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
851#define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
852
853#define S_SACK 4
854#define M_SACK 0x3
855#define V_SACK(x) ((x) << S_SACK)
856#define G_SACK(x) (((x) >> S_SACK) & M_SACK)
857
858#define S_ECN 6
859#define M_ECN 0x3
860#define V_ECN(x) ((x) << S_ECN)
861#define G_ECN(x) (((x) >> S_ECN) & M_ECN)
862
863#define S_SACK_ALGORITHM 8
864#define M_SACK_ALGORITHM 0x3
865#define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
866#define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
867
868#define S_MSS 10
869#define V_MSS(x) ((x) << S_MSS)
870#define F_MSS V_MSS(1U)
871
872#define S_DEFAULT_PEER_MSS 16
873#define M_DEFAULT_PEER_MSS 0xffff
874#define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
875#define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
876
877#define A_TP_DACK_CONFIG 0x344
878
879#define S_DACK_MODE 0
880#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
881#define F_DACK_MODE V_DACK_MODE(1U)
882
883#define S_DACK_AUTO_MGMT 1
884#define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
885#define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U)
886
887#define S_DACK_AUTO_CAREFUL 2
888#define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
889#define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U)
890
891#define S_DACK_MSS_SELECTOR 3
892#define M_DACK_MSS_SELECTOR 0x3
893#define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
894#define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
895
896#define S_DACK_BYTE_THRESHOLD 5
897#define M_DACK_BYTE_THRESHOLD 0xfffff
898#define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
899#define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
258 900
259#define A_TP_PC_CONFIG 0x348 901#define A_TP_PC_CONFIG 0x348
902
903#define S_TP_ACCESS_LATENCY 0
904#define M_TP_ACCESS_LATENCY 0xf
905#define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
906#define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
907
908#define S_HELD_FIN_DISABLE 4
909#define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
910#define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U)
911
912#define S_DDP_FC_ENABLE 5
913#define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
914#define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U)
915
916#define S_RDMA_ERR_ENABLE 6
917#define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
918#define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U)
919
920#define S_FAST_PDU_DELIVERY 7
921#define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
922#define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U)
923
924#define S_CLEAR_FIN 8
925#define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
926#define F_CLEAR_FIN V_CLEAR_FIN(1U)
927
260#define S_DIS_TX_FILL_WIN_PUSH 12 928#define S_DIS_TX_FILL_WIN_PUSH 12
261#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH) 929#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
262#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U) 930#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
263 931
264#define S_TP_PC_REV 30 932#define S_TP_PC_REV 30
265#define M_TP_PC_REV 0x3 933#define M_TP_PC_REV 0x3
934#define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
266#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV) 935#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
936
937#define A_TP_BACKOFF0 0x350
938
939#define S_ELEMENT0 0
940#define M_ELEMENT0 0xff
941#define V_ELEMENT0(x) ((x) << S_ELEMENT0)
942#define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
943
944#define S_ELEMENT1 8
945#define M_ELEMENT1 0xff
946#define V_ELEMENT1(x) ((x) << S_ELEMENT1)
947#define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
948
949#define S_ELEMENT2 16
950#define M_ELEMENT2 0xff
951#define V_ELEMENT2(x) ((x) << S_ELEMENT2)
952#define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
953
954#define S_ELEMENT3 24
955#define M_ELEMENT3 0xff
956#define V_ELEMENT3(x) ((x) << S_ELEMENT3)
957#define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
958
959#define A_TP_BACKOFF1 0x354
960#define A_TP_BACKOFF2 0x358
961#define A_TP_BACKOFF3 0x35c
962#define A_TP_PARA_REG0 0x360
963
964#define S_VAR_MULT 0
965#define M_VAR_MULT 0xf
966#define V_VAR_MULT(x) ((x) << S_VAR_MULT)
967#define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
968
969#define S_VAR_GAIN 4
970#define M_VAR_GAIN 0xf
971#define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
972#define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
973
974#define S_SRTT_GAIN 8
975#define M_SRTT_GAIN 0xf
976#define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
977#define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
978
979#define S_RTTVAR_INIT 12
980#define M_RTTVAR_INIT 0xf
981#define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
982#define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
983
984#define S_DUP_THRESH 20
985#define M_DUP_THRESH 0xf
986#define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
987#define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
988
989#define S_INIT_CONG_WIN 24
990#define M_INIT_CONG_WIN 0x7
991#define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
992#define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
993
994#define A_TP_PARA_REG1 0x364
995
996#define S_INITIAL_SLOW_START_THRESHOLD 0
997#define M_INITIAL_SLOW_START_THRESHOLD 0xffff
998#define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
999#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
1000
1001#define S_RECEIVE_BUFFER_SIZE 16
1002#define M_RECEIVE_BUFFER_SIZE 0xffff
1003#define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
1004#define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
1005
1006#define A_TP_PARA_REG2 0x368
1007
1008#define S_RX_COALESCE_SIZE 0
1009#define M_RX_COALESCE_SIZE 0xffff
1010#define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
1011#define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
1012
1013#define S_MAX_RX_SIZE 16
1014#define M_MAX_RX_SIZE 0xffff
1015#define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
1016#define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
1017
1018#define A_TP_PARA_REG3 0x36c
1019
1020#define S_RX_COALESCING_PSH_DELIVER 0
1021#define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1022#define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U)
1023
1024#define S_RX_COALESCING_ENABLE 1
1025#define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1026#define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U)
1027
1028#define S_TAHOE_ENABLE 2
1029#define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1030#define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U)
1031
1032#define S_MAX_REORDER_FRAGMENTS 12
1033#define M_MAX_REORDER_FRAGMENTS 0x7
1034#define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1035#define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1036
1037#define A_TP_TIMER_RESOLUTION 0x390
1038
1039#define S_DELAYED_ACK_TIMER_RESOLUTION 0
1040#define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f
1041#define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1042#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1043
1044#define S_GENERIC_TIMER_RESOLUTION 16
1045#define M_GENERIC_TIMER_RESOLUTION 0x3f
1046#define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1047#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1048
1049#define A_TP_2MSL 0x394
1050
1051#define S_2MSL 0
1052#define M_2MSL 0x3fffffff
1053#define V_2MSL(x) ((x) << S_2MSL)
1054#define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1055
1056#define A_TP_RXT_MIN 0x398
1057
1058#define S_RETRANSMIT_TIMER_MIN 0
1059#define M_RETRANSMIT_TIMER_MIN 0xffff
1060#define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1061#define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1062
1063#define A_TP_RXT_MAX 0x39c
1064
1065#define S_RETRANSMIT_TIMER_MAX 0
1066#define M_RETRANSMIT_TIMER_MAX 0x3fffffff
1067#define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1068#define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1069
1070#define A_TP_PERS_MIN 0x3a0
1071
1072#define S_PERSIST_TIMER_MIN 0
1073#define M_PERSIST_TIMER_MIN 0xffff
1074#define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1075#define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1076
1077#define A_TP_PERS_MAX 0x3a4
1078
1079#define S_PERSIST_TIMER_MAX 0
1080#define M_PERSIST_TIMER_MAX 0x3fffffff
1081#define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1082#define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1083
1084#define A_TP_KEEP_IDLE 0x3ac
1085
1086#define S_KEEP_ALIVE_IDLE_TIME 0
1087#define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff
1088#define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1089#define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1090
1091#define A_TP_KEEP_INTVL 0x3b0
1092
1093#define S_KEEP_ALIVE_INTERVAL_TIME 0
1094#define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff
1095#define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1096#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1097
1098#define A_TP_INIT_SRTT 0x3b4
1099
1100#define S_INITIAL_SRTT 0
1101#define M_INITIAL_SRTT 0xffff
1102#define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1103#define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1104
1105#define A_TP_DACK_TIME 0x3b8
1106
1107#define S_DELAYED_ACK_TIME 0
1108#define M_DELAYED_ACK_TIME 0x7ff
1109#define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1110#define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1111
1112#define A_TP_FINWAIT2_TIME 0x3bc
1113
1114#define S_FINWAIT2_TIME 0
1115#define M_FINWAIT2_TIME 0x3fffffff
1116#define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1117#define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1118
1119#define A_TP_FAST_FINWAIT2_TIME 0x3c0
1120
1121#define S_FAST_FINWAIT2_TIME 0
1122#define M_FAST_FINWAIT2_TIME 0x3fffffff
1123#define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1124#define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1125
1126#define A_TP_SHIFT_CNT 0x3c4
1127
1128#define S_KEEPALIVE_MAX 0
1129#define M_KEEPALIVE_MAX 0xff
1130#define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1131#define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1132
1133#define S_WINDOWPROBE_MAX 8
1134#define M_WINDOWPROBE_MAX 0xff
1135#define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1136#define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1137
1138#define S_RETRANSMISSION_MAX 16
1139#define M_RETRANSMISSION_MAX 0xff
1140#define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1141#define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1142
1143#define S_SYN_MAX 24
1144#define M_SYN_MAX 0xff
1145#define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1146#define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1147
1148#define A_TP_QOS_REG0 0x3e0
1149
1150#define S_L3_VALUE 0
1151#define M_L3_VALUE 0x3f
1152#define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1153#define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1154
1155#define A_TP_QOS_REG1 0x3e4
1156#define A_TP_QOS_REG2 0x3e8
1157#define A_TP_QOS_REG3 0x3ec
1158#define A_TP_QOS_REG4 0x3f0
1159#define A_TP_QOS_REG5 0x3f4
1160#define A_TP_QOS_REG6 0x3f8
1161#define A_TP_QOS_REG7 0x3fc
1162#define A_TP_MTU_REG0 0x404
1163#define A_TP_MTU_REG1 0x408
1164#define A_TP_MTU_REG2 0x40c
1165#define A_TP_MTU_REG3 0x410
1166#define A_TP_MTU_REG4 0x414
1167#define A_TP_MTU_REG5 0x418
1168#define A_TP_MTU_REG6 0x41c
1169#define A_TP_MTU_REG7 0x420
267#define A_TP_RESET 0x44c 1170#define A_TP_RESET 0x44c
1171
268#define S_TP_RESET 0 1172#define S_TP_RESET 0
269#define V_TP_RESET(x) ((x) << S_TP_RESET) 1173#define V_TP_RESET(x) ((x) << S_TP_RESET)
270#define F_TP_RESET V_TP_RESET(1U) 1174#define F_TP_RESET V_TP_RESET(1U)
271 1175
1176#define S_CM_MEMMGR_INIT 1
1177#define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1178#define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U)
1179
1180#define A_TP_MIB_INDEX 0x450
1181#define A_TP_MIB_DATA 0x454
1182#define A_TP_SYNC_TIME_HI 0x458
1183#define A_TP_SYNC_TIME_LO 0x45c
1184#define A_TP_CM_MM_RX_FLST_BASE 0x460
1185
1186#define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
1187#define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff
1188#define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1189#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1190
1191#define A_TP_CM_MM_TX_FLST_BASE 0x464
1192
1193#define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
1194#define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff
1195#define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1196#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1197
1198#define A_TP_CM_MM_P_FLST_BASE 0x468
1199
1200#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
1201#define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff
1202#define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1203#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1204
1205#define A_TP_CM_MM_MAX_P 0x46c
1206
1207#define S_CM_MEMMGR_MAX_PSTRUCT 0
1208#define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff
1209#define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1210#define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1211
272#define A_TP_INT_ENABLE 0x470 1212#define A_TP_INT_ENABLE 0x470
1213
1214#define S_TX_FREE_LIST_EMPTY 0
1215#define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1216#define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U)
1217
1218#define S_RX_FREE_LIST_EMPTY 1
1219#define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1220#define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U)
1221
273#define A_TP_INT_CAUSE 0x474 1222#define A_TP_INT_CAUSE 0x474
1223#define A_TP_TIMER_SEPARATOR 0x4a4
1224
1225#define S_DISABLE_PAST_TIMER_INSERTION 0
1226#define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1227#define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U)
1228
1229#define S_MODULATION_TIMER_SEPARATOR 1
1230#define M_MODULATION_TIMER_SEPARATOR 0x7fff
1231#define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1232#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1233
1234#define S_GLOBAL_TIMER_SEPARATOR 16
1235#define M_GLOBAL_TIMER_SEPARATOR 0xffff
1236#define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1237#define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1238
1239#define A_TP_CM_FC_MODE 0x4b0
1240#define A_TP_PC_CONGESTION_CNTL 0x4b4
274#define A_TP_TX_DROP_CONFIG 0x4b8 1241#define A_TP_TX_DROP_CONFIG 0x4b8
275 1242
276#define S_ENABLE_TX_DROP 31 1243#define S_ENABLE_TX_DROP 31
@@ -282,12 +1249,108 @@
282#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U) 1249#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
283 1250
284#define S_DROP_TICKS_CNT 4 1251#define S_DROP_TICKS_CNT 4
1252#define M_DROP_TICKS_CNT 0x3ffffff
285#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT) 1253#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1254#define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
286 1255
287#define S_NUM_PKTS_DROPPED 0 1256#define S_NUM_PKTS_DROPPED 0
1257#define M_NUM_PKTS_DROPPED 0xf
288#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED) 1258#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1259#define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1260
1261#define A_TP_TX_DROP_COUNT 0x4bc
1262
1263/* RAT registers */
1264#define A_RAT_ROUTE_CONTROL 0x580
1265
1266#define S_USE_ROUTE_TABLE 0
1267#define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1268#define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U)
1269
1270#define S_ENABLE_CSPI 1
1271#define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1272#define F_ENABLE_CSPI V_ENABLE_CSPI(1U)
1273
1274#define S_ENABLE_PCIX 2
1275#define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1276#define F_ENABLE_PCIX V_ENABLE_PCIX(1U)
1277
1278#define A_RAT_ROUTE_TABLE_INDEX 0x584
1279
1280#define S_ROUTE_TABLE_INDEX 0
1281#define M_ROUTE_TABLE_INDEX 0xf
1282#define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1283#define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1284
1285#define A_RAT_ROUTE_TABLE_DATA 0x588
1286#define A_RAT_NO_ROUTE 0x58c
1287
1288#define S_CPL_OPCODE 0
1289#define M_CPL_OPCODE 0xff
1290#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1291#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1292
1293#define A_RAT_INTR_ENABLE 0x590
1294
1295#define S_ZEROROUTEERROR 0
1296#define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1297#define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U)
1298
1299#define S_CSPIFRAMINGERROR 1
1300#define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1301#define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U)
1302
1303#define S_SGEFRAMINGERROR 2
1304#define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1305#define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U)
1306
1307#define S_TPFRAMINGERROR 3
1308#define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1309#define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U)
1310
1311#define A_RAT_INTR_CAUSE 0x594
289 1312
290/* CSPI registers */ 1313/* CSPI registers */
1314#define A_CSPI_RX_AE_WM 0x810
1315#define A_CSPI_RX_AF_WM 0x814
1316#define A_CSPI_CALENDAR_LEN 0x818
1317
1318#define S_CALENDARLENGTH 0
1319#define M_CALENDARLENGTH 0xffff
1320#define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1321#define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1322
1323#define A_CSPI_FIFO_STATUS_ENABLE 0x820
1324
1325#define S_FIFOSTATUSENABLE 0
1326#define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1327#define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U)
1328
1329#define A_CSPI_MAXBURST1_MAXBURST2 0x828
1330
1331#define S_MAXBURST1 0
1332#define M_MAXBURST1 0xffff
1333#define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1334#define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1335
1336#define S_MAXBURST2 16
1337#define M_MAXBURST2 0xffff
1338#define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1339#define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1340
1341#define A_CSPI_TRAIN 0x82c
1342
1343#define S_CSPI_TRAIN_ALPHA 0
1344#define M_CSPI_TRAIN_ALPHA 0xffff
1345#define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1346#define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1347
1348#define S_CSPI_TRAIN_DATA_MAXT 16
1349#define M_CSPI_TRAIN_DATA_MAXT 0xffff
1350#define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1351#define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1352
1353#define A_CSPI_INTR_STATUS 0x848
291 1354
292#define S_DIP4ERR 0 1355#define S_DIP4ERR 0
293#define V_DIP4ERR(x) ((x) << S_DIP4ERR) 1356#define V_DIP4ERR(x) ((x) << S_DIP4ERR)
@@ -309,22 +1372,63 @@
309#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR) 1372#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
310#define F_RAMPARITYERR V_RAMPARITYERR(1U) 1373#define F_RAMPARITYERR V_RAMPARITYERR(1U)
311 1374
312/* ESPI registers */ 1375#define A_CSPI_INTR_ENABLE 0x84c
313 1376
1377/* ESPI registers */
314#define A_ESPI_SCH_TOKEN0 0x880 1378#define A_ESPI_SCH_TOKEN0 0x880
1379
1380#define S_SCHTOKEN0 0
1381#define M_SCHTOKEN0 0xffff
1382#define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1383#define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1384
315#define A_ESPI_SCH_TOKEN1 0x884 1385#define A_ESPI_SCH_TOKEN1 0x884
1386
1387#define S_SCHTOKEN1 0
1388#define M_SCHTOKEN1 0xffff
1389#define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1390#define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1391
316#define A_ESPI_SCH_TOKEN2 0x888 1392#define A_ESPI_SCH_TOKEN2 0x888
1393
1394#define S_SCHTOKEN2 0
1395#define M_SCHTOKEN2 0xffff
1396#define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1397#define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1398
317#define A_ESPI_SCH_TOKEN3 0x88c 1399#define A_ESPI_SCH_TOKEN3 0x88c
1400
1401#define S_SCHTOKEN3 0
1402#define M_SCHTOKEN3 0xffff
1403#define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1404#define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1405
318#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890 1406#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1407
1408#define S_ALMOSTEMPTY 0
1409#define M_ALMOSTEMPTY 0xffff
1410#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1411#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1412
319#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894 1413#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1414
1415#define S_ALMOSTFULL 0
1416#define M_ALMOSTFULL 0xffff
1417#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1418#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1419
320#define A_ESPI_CALENDAR_LENGTH 0x898 1420#define A_ESPI_CALENDAR_LENGTH 0x898
321#define A_PORT_CONFIG 0x89c 1421#define A_PORT_CONFIG 0x89c
322 1422
323#define S_RX_NPORTS 0 1423#define S_RX_NPORTS 0
1424#define M_RX_NPORTS 0xff
324#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS) 1425#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1426#define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
325 1427
326#define S_TX_NPORTS 8 1428#define S_TX_NPORTS 8
1429#define M_TX_NPORTS 0xff
327#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS) 1430#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1431#define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
328 1432
329#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0 1433#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
330 1434
@@ -332,12 +1436,124 @@
332#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE) 1436#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
333#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U) 1437#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
334 1438
1439#define S_TXDROPENABLE 1
1440#define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1441#define F_TXDROPENABLE V_TXDROPENABLE(1U)
1442
1443#define S_RXENDIANMODE 2
1444#define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1445#define F_RXENDIANMODE V_RXENDIANMODE(1U)
1446
1447#define S_TXENDIANMODE 3
1448#define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)
1449#define F_TXENDIANMODE V_TXENDIANMODE(1U)
1450
335#define S_INTEL1010MODE 4 1451#define S_INTEL1010MODE 4
336#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE) 1452#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
337#define F_INTEL1010MODE V_INTEL1010MODE(1U) 1453#define F_INTEL1010MODE V_INTEL1010MODE(1U)
338 1454
339#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8 1455#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
340#define A_ESPI_TRAIN 0x8ac 1456#define A_ESPI_TRAIN 0x8ac
1457
1458#define S_MAXTRAINALPHA 0
1459#define M_MAXTRAINALPHA 0xffff
1460#define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)
1461#define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)
1462
1463#define S_MAXTRAINDATA 16
1464#define M_MAXTRAINDATA 0xffff
1465#define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)
1466#define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)
1467
1468#define A_RAM_STATUS 0x8b0
1469
1470#define S_RXFIFOPARITYERROR 0
1471#define M_RXFIFOPARITYERROR 0x3ff
1472#define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)
1473#define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)
1474
1475#define S_TXFIFOPARITYERROR 10
1476#define M_TXFIFOPARITYERROR 0x3ff
1477#define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)
1478#define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)
1479
1480#define S_RXFIFOOVERFLOW 20
1481#define M_RXFIFOOVERFLOW 0x3ff
1482#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
1483#define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)
1484
1485#define A_TX_DROP_COUNT0 0x8b4
1486
1487#define S_TXPORT0DROPCNT 0
1488#define M_TXPORT0DROPCNT 0xffff
1489#define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)
1490#define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)
1491
1492#define S_TXPORT1DROPCNT 16
1493#define M_TXPORT1DROPCNT 0xffff
1494#define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)
1495#define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)
1496
1497#define A_TX_DROP_COUNT1 0x8b8
1498
1499#define S_TXPORT2DROPCNT 0
1500#define M_TXPORT2DROPCNT 0xffff
1501#define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)
1502#define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)
1503
1504#define S_TXPORT3DROPCNT 16
1505#define M_TXPORT3DROPCNT 0xffff
1506#define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)
1507#define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)
1508
1509#define A_RX_DROP_COUNT0 0x8bc
1510
1511#define S_RXPORT0DROPCNT 0
1512#define M_RXPORT0DROPCNT 0xffff
1513#define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)
1514#define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)
1515
1516#define S_RXPORT1DROPCNT 16
1517#define M_RXPORT1DROPCNT 0xffff
1518#define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)
1519#define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)
1520
1521#define A_RX_DROP_COUNT1 0x8c0
1522
1523#define S_RXPORT2DROPCNT 0
1524#define M_RXPORT2DROPCNT 0xffff
1525#define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)
1526#define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)
1527
1528#define S_RXPORT3DROPCNT 16
1529#define M_RXPORT3DROPCNT 0xffff
1530#define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)
1531#define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)
1532
1533#define A_DIP4_ERROR_COUNT 0x8c4
1534
1535#define S_DIP4ERRORCNT 0
1536#define M_DIP4ERRORCNT 0xfff
1537#define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)
1538#define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)
1539
1540#define S_DIP4ERRORCNTSHADOW 12
1541#define M_DIP4ERRORCNTSHADOW 0xfff
1542#define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)
1543#define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)
1544
1545#define S_TRICN_RX_TRAIN_ERR 24
1546#define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)
1547#define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U)
1548
1549#define S_TRICN_RX_TRAINING 25
1550#define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)
1551#define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U)
1552
1553#define S_TRICN_RX_TRAIN_OK 26
1554#define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)
1555#define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U)
1556
341#define A_ESPI_INTR_STATUS 0x8c8 1557#define A_ESPI_INTR_STATUS 0x8c8
342 1558
343#define S_DIP2PARITYERR 5 1559#define S_DIP2PARITYERR 5
@@ -347,19 +1563,56 @@
347#define A_ESPI_INTR_ENABLE 0x8cc 1563#define A_ESPI_INTR_ENABLE 0x8cc
348#define A_RX_DROP_THRESHOLD 0x8d0 1564#define A_RX_DROP_THRESHOLD 0x8d0
349#define A_ESPI_RX_RESET 0x8ec 1565#define A_ESPI_RX_RESET 0x8ec
1566
1567#define S_ESPI_RX_LNK_RST 0
1568#define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)
1569#define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U)
1570
1571#define S_ESPI_RX_CORE_RST 1
1572#define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)
1573#define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U)
1574
1575#define S_RX_CLK_STATUS 2
1576#define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)
1577#define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U)
1578
350#define A_ESPI_MISC_CONTROL 0x8f0 1579#define A_ESPI_MISC_CONTROL 0x8f0
351 1580
352#define S_OUT_OF_SYNC_COUNT 0 1581#define S_OUT_OF_SYNC_COUNT 0
1582#define M_OUT_OF_SYNC_COUNT 0xf
353#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT) 1583#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
1584#define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)
1585
1586#define S_DIP2_COUNT_MODE_ENABLE 4
1587#define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)
1588#define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U)
354 1589
355#define S_DIP2_PARITY_ERR_THRES 5 1590#define S_DIP2_PARITY_ERR_THRES 5
1591#define M_DIP2_PARITY_ERR_THRES 0xf
356#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES) 1592#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
1593#define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)
357 1594
358#define S_DIP4_THRES 9 1595#define S_DIP4_THRES 9
1596#define M_DIP4_THRES 0xfff
359#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES) 1597#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
1598#define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)
1599
1600#define S_DIP4_THRES_ENABLE 21
1601#define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)
1602#define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U)
1603
1604#define S_FORCE_DISABLE_STATUS 22
1605#define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)
1606#define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U)
1607
1608#define S_DYNAMIC_DESKEW 23
1609#define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)
1610#define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U)
360 1611
361#define S_MONITORED_PORT_NUM 25 1612#define S_MONITORED_PORT_NUM 25
1613#define M_MONITORED_PORT_NUM 0x3
362#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM) 1614#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
1615#define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)
363 1616
364#define S_MONITORED_DIRECTION 27 1617#define S_MONITORED_DIRECTION 27
365#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION) 1618#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
@@ -370,33 +1623,125 @@
370#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U) 1623#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)
371 1624
372#define A_ESPI_DIP2_ERR_COUNT 0x8f4 1625#define A_ESPI_DIP2_ERR_COUNT 0x8f4
1626
1627#define S_DIP2_ERR_CNT 0
1628#define M_DIP2_ERR_CNT 0xf
1629#define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)
1630#define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)
1631
373#define A_ESPI_CMD_ADDR 0x8f8 1632#define A_ESPI_CMD_ADDR 0x8f8
374 1633
375#define S_WRITE_DATA 0 1634#define S_WRITE_DATA 0
1635#define M_WRITE_DATA 0xff
376#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA) 1636#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
1637#define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)
377 1638
378#define S_REGISTER_OFFSET 8 1639#define S_REGISTER_OFFSET 8
1640#define M_REGISTER_OFFSET 0xf
379#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET) 1641#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
1642#define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)
380 1643
381#define S_CHANNEL_ADDR 12 1644#define S_CHANNEL_ADDR 12
1645#define M_CHANNEL_ADDR 0xf
382#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR) 1646#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
1647#define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)
383 1648
384#define S_MODULE_ADDR 16 1649#define S_MODULE_ADDR 16
1650#define M_MODULE_ADDR 0x3
385#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR) 1651#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
1652#define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)
386 1653
387#define S_BUNDLE_ADDR 20 1654#define S_BUNDLE_ADDR 20
1655#define M_BUNDLE_ADDR 0x3
388#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR) 1656#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
1657#define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)
389 1658
390#define S_SPI4_COMMAND 24 1659#define S_SPI4_COMMAND 24
1660#define M_SPI4_COMMAND 0xff
391#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND) 1661#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
1662#define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)
392 1663
393#define A_ESPI_GOSTAT 0x8fc 1664#define A_ESPI_GOSTAT 0x8fc
1665
1666#define S_READ_DATA 0
1667#define M_READ_DATA 0xff
1668#define V_READ_DATA(x) ((x) << S_READ_DATA)
1669#define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)
1670
394#define S_ESPI_CMD_BUSY 8 1671#define S_ESPI_CMD_BUSY 8
395#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY) 1672#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
396#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U) 1673#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)
397 1674
398/* PL registers */ 1675#define S_ERROR_ACK 9
1676#define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)
1677#define F_ERROR_ACK V_ERROR_ACK(1U)
1678
1679#define S_UNMAPPED_ERR 10
1680#define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)
1681#define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U)
1682
1683#define S_TRANSACTION_TIMER 16
1684#define M_TRANSACTION_TIMER 0xff
1685#define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)
1686#define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)
1687
1688
1689/* ULP registers */
1690#define A_ULP_ULIMIT 0x980
1691#define A_ULP_TAGMASK 0x984
1692#define A_ULP_HREG_INDEX 0x988
1693#define A_ULP_HREG_DATA 0x98c
1694#define A_ULP_INT_ENABLE 0x990
1695#define A_ULP_INT_CAUSE 0x994
399 1696
1697#define S_HREG_PAR_ERR 0
1698#define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)
1699#define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U)
1700
1701#define S_EGRS_DATA_PAR_ERR 1
1702#define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)
1703#define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U)
1704
1705#define S_INGRS_DATA_PAR_ERR 2
1706#define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)
1707#define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U)
1708
1709#define S_PM_INTR 3
1710#define V_PM_INTR(x) ((x) << S_PM_INTR)
1711#define F_PM_INTR V_PM_INTR(1U)
1712
1713#define S_PM_E2C_SYNC_ERR 4
1714#define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)
1715#define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U)
1716
1717#define S_PM_C2E_SYNC_ERR 5
1718#define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)
1719#define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U)
1720
1721#define S_PM_E2C_EMPTY_ERR 6
1722#define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)
1723#define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U)
1724
1725#define S_PM_C2E_EMPTY_ERR 7
1726#define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)
1727#define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U)
1728
1729#define S_PM_PAR_ERR 8
1730#define M_PM_PAR_ERR 0xffff
1731#define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)
1732#define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)
1733
1734#define S_PM_E2C_WRT_FULL 24
1735#define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)
1736#define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U)
1737
1738#define S_PM_C2E_WRT_FULL 25
1739#define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)
1740#define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U)
1741
1742#define A_ULP_PIO_CTRL 0x998
1743
1744/* PL registers */
400#define A_PL_ENABLE 0xa00 1745#define A_PL_ENABLE 0xa00
401 1746
402#define S_PL_INTR_SGE_ERR 0 1747#define S_PL_INTR_SGE_ERR 0
@@ -407,14 +1752,38 @@
407#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA) 1752#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
408#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U) 1753#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)
409 1754
1755#define S_PL_INTR_MC3 2
1756#define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)
1757#define F_PL_INTR_MC3 V_PL_INTR_MC3(1U)
1758
1759#define S_PL_INTR_MC4 3
1760#define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)
1761#define F_PL_INTR_MC4 V_PL_INTR_MC4(1U)
1762
1763#define S_PL_INTR_MC5 4
1764#define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)
1765#define F_PL_INTR_MC5 V_PL_INTR_MC5(1U)
1766
1767#define S_PL_INTR_RAT 5
1768#define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)
1769#define F_PL_INTR_RAT V_PL_INTR_RAT(1U)
1770
410#define S_PL_INTR_TP 6 1771#define S_PL_INTR_TP 6
411#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP) 1772#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
412#define F_PL_INTR_TP V_PL_INTR_TP(1U) 1773#define F_PL_INTR_TP V_PL_INTR_TP(1U)
413 1774
1775#define S_PL_INTR_ULP 7
1776#define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)
1777#define F_PL_INTR_ULP V_PL_INTR_ULP(1U)
1778
414#define S_PL_INTR_ESPI 8 1779#define S_PL_INTR_ESPI 8
415#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI) 1780#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
416#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U) 1781#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)
417 1782
1783#define S_PL_INTR_CSPI 9
1784#define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)
1785#define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U)
1786
418#define S_PL_INTR_PCIX 10 1787#define S_PL_INTR_PCIX 10
419#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX) 1788#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
420#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) 1789#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)
@@ -426,43 +1795,374 @@
426#define A_PL_CAUSE 0xa04 1795#define A_PL_CAUSE 0xa04
427 1796
428/* MC5 registers */ 1797/* MC5 registers */
429
430#define A_MC5_CONFIG 0xc04 1798#define A_MC5_CONFIG 0xc04
431 1799
1800#define S_MODE 0
1801#define V_MODE(x) ((x) << S_MODE)
1802#define F_MODE V_MODE(1U)
1803
432#define S_TCAM_RESET 1 1804#define S_TCAM_RESET 1
433#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET) 1805#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
434#define F_TCAM_RESET V_TCAM_RESET(1U) 1806#define F_TCAM_RESET V_TCAM_RESET(1U)
435 1807
1808#define S_TCAM_READY 2
1809#define V_TCAM_READY(x) ((x) << S_TCAM_READY)
1810#define F_TCAM_READY V_TCAM_READY(1U)
1811
1812#define S_DBGI_ENABLE 4
1813#define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)
1814#define F_DBGI_ENABLE V_DBGI_ENABLE(1U)
1815
436#define S_M_BUS_ENABLE 5 1816#define S_M_BUS_ENABLE 5
437#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE) 1817#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
438#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U) 1818#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)
439 1819
440/* PCICFG registers */ 1820#define S_PARITY_ENABLE 6
1821#define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)
1822#define F_PARITY_ENABLE V_PARITY_ENABLE(1U)
1823
1824#define S_SYN_ISSUE_MODE 7
1825#define M_SYN_ISSUE_MODE 0x3
1826#define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)
1827#define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)
1828
1829#define S_BUILD 16
1830#define V_BUILD(x) ((x) << S_BUILD)
1831#define F_BUILD V_BUILD(1U)
1832
1833#define S_COMPRESSION_ENABLE 17
1834#define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)
1835#define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U)
1836
1837#define S_NUM_LIP 18
1838#define M_NUM_LIP 0x3f
1839#define V_NUM_LIP(x) ((x) << S_NUM_LIP)
1840#define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)
1841
1842#define S_TCAM_PART_CNT 24
1843#define M_TCAM_PART_CNT 0x3
1844#define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)
1845#define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)
1846
1847#define S_TCAM_PART_TYPE 26
1848#define M_TCAM_PART_TYPE 0x3
1849#define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)
1850#define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)
1851
1852#define S_TCAM_PART_SIZE 28
1853#define M_TCAM_PART_SIZE 0x3
1854#define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)
1855#define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)
1856
1857#define S_TCAM_PART_TYPE_HI 30
1858#define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)
1859#define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U)
1860
1861#define A_MC5_SIZE 0xc08
1862
1863#define S_SIZE 0
1864#define M_SIZE 0x3fffff
1865#define V_SIZE(x) ((x) << S_SIZE)
1866#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1867
1868#define A_MC5_ROUTING_TABLE_INDEX 0xc0c
441 1869
1870#define S_START_OF_ROUTING_TABLE 0
1871#define M_START_OF_ROUTING_TABLE 0x3fffff
1872#define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)
1873#define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)
1874
1875#define A_MC5_SERVER_INDEX 0xc14
1876
1877#define S_START_OF_SERVER_INDEX 0
1878#define M_START_OF_SERVER_INDEX 0x3fffff
1879#define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)
1880#define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)
1881
1882#define A_MC5_LIP_RAM_ADDR 0xc18
1883
1884#define S_LOCAL_IP_RAM_ADDR 0
1885#define M_LOCAL_IP_RAM_ADDR 0x3f
1886#define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)
1887#define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)
1888
1889#define S_RAM_WRITE_ENABLE 8
1890#define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)
1891#define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U)
1892
1893#define A_MC5_LIP_RAM_DATA 0xc1c
1894#define A_MC5_RSP_LATENCY 0xc20
1895
1896#define S_SEARCH_RESPONSE_LATENCY 0
1897#define M_SEARCH_RESPONSE_LATENCY 0x1f
1898#define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)
1899#define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
1900
1901#define S_LEARN_RESPONSE_LATENCY 8
1902#define M_LEARN_RESPONSE_LATENCY 0x1f
1903#define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)
1904#define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)
1905
1906#define A_MC5_PARITY_LATENCY 0xc24
1907
1908#define S_SRCHLAT 0
1909#define M_SRCHLAT 0x1f
1910#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1911#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
1912
1913#define S_PARLAT 8
1914#define M_PARLAT 0x1f
1915#define V_PARLAT(x) ((x) << S_PARLAT)
1916#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
1917
1918#define A_MC5_WR_LRN_VERIFY 0xc28
1919
1920#define S_POVEREN 0
1921#define V_POVEREN(x) ((x) << S_POVEREN)
1922#define F_POVEREN V_POVEREN(1U)
1923
1924#define S_LRNVEREN 1
1925#define V_LRNVEREN(x) ((x) << S_LRNVEREN)
1926#define F_LRNVEREN V_LRNVEREN(1U)
1927
1928#define S_VWVEREN 2
1929#define V_VWVEREN(x) ((x) << S_VWVEREN)
1930#define F_VWVEREN V_VWVEREN(1U)
1931
1932#define A_MC5_PART_ID_INDEX 0xc2c
1933
1934#define S_IDINDEX 0
1935#define M_IDINDEX 0xf
1936#define V_IDINDEX(x) ((x) << S_IDINDEX)
1937#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
1938
1939#define A_MC5_RESET_MAX 0xc30
1940
1941#define S_RSTMAX 0
1942#define M_RSTMAX 0x1ff
1943#define V_RSTMAX(x) ((x) << S_RSTMAX)
1944#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
1945
1946#define A_MC5_INT_ENABLE 0xc40
1947
1948#define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0
1949#define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)
1950#define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)
1951
1952#define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 1
1953#define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)
1954#define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)
1955
1956#define S_MC5_INT_HIT_IN_RT_REGION_ERR 2
1957#define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)
1958#define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)
1959
1960#define S_MC5_INT_MISS_ERR 3
1961#define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)
1962#define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U)
1963
1964#define S_MC5_INT_LIP0_ERR 4
1965#define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)
1966#define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U)
1967
1968#define S_MC5_INT_LIP_MISS_ERR 5
1969#define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)
1970#define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U)
1971
1972#define S_MC5_INT_PARITY_ERR 6
1973#define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)
1974#define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U)
1975
1976#define S_MC5_INT_ACTIVE_REGION_FULL 7
1977#define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)
1978#define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U)
1979
1980#define S_MC5_INT_NFA_SRCH_ERR 8
1981#define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)
1982#define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U)
1983
1984#define S_MC5_INT_SYN_COOKIE 9
1985#define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)
1986#define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U)
1987
1988#define S_MC5_INT_SYN_COOKIE_BAD 10
1989#define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)
1990#define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U)
1991
1992#define S_MC5_INT_SYN_COOKIE_OFF 11
1993#define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)
1994#define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U)
1995
1996#define S_MC5_INT_UNKNOWN_CMD 15
1997#define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)
1998#define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U)
1999
2000#define S_MC5_INT_REQUESTQ_PARITY_ERR 16
2001#define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)
2002#define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U)
2003
2004#define S_MC5_INT_DISPATCHQ_PARITY_ERR 17
2005#define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)
2006#define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)
2007
2008#define S_MC5_INT_DEL_ACT_EMPTY 18
2009#define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)
2010#define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U)
2011
2012#define A_MC5_INT_CAUSE 0xc44
2013#define A_MC5_INT_TID 0xc48
2014#define A_MC5_INT_PTID 0xc4c
2015#define A_MC5_DBGI_CONFIG 0xc74
2016#define A_MC5_DBGI_REQ_CMD 0xc78
2017
2018#define S_CMDMODE 0
2019#define M_CMDMODE 0x7
2020#define V_CMDMODE(x) ((x) << S_CMDMODE)
2021#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
2022
2023#define S_SADRSEL 4
2024#define V_SADRSEL(x) ((x) << S_SADRSEL)
2025#define F_SADRSEL V_SADRSEL(1U)
2026
2027#define S_WRITE_BURST_SIZE 22
2028#define M_WRITE_BURST_SIZE 0x3ff
2029#define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)
2030#define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)
2031
2032#define A_MC5_DBGI_REQ_ADDR0 0xc7c
2033#define A_MC5_DBGI_REQ_ADDR1 0xc80
2034#define A_MC5_DBGI_REQ_ADDR2 0xc84
2035#define A_MC5_DBGI_REQ_DATA0 0xc88
2036#define A_MC5_DBGI_REQ_DATA1 0xc8c
2037#define A_MC5_DBGI_REQ_DATA2 0xc90
2038#define A_MC5_DBGI_REQ_DATA3 0xc94
2039#define A_MC5_DBGI_REQ_DATA4 0xc98
2040#define A_MC5_DBGI_REQ_MASK0 0xc9c
2041#define A_MC5_DBGI_REQ_MASK1 0xca0
2042#define A_MC5_DBGI_REQ_MASK2 0xca4
2043#define A_MC5_DBGI_REQ_MASK3 0xca8
2044#define A_MC5_DBGI_REQ_MASK4 0xcac
2045#define A_MC5_DBGI_RSP_STATUS 0xcb0
2046
2047#define S_DBGI_RSP_VALID 0
2048#define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)
2049#define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U)
2050
2051#define S_DBGI_RSP_HIT 1
2052#define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)
2053#define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U)
2054
2055#define S_DBGI_RSP_ERR 2
2056#define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)
2057#define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U)
2058
2059#define S_DBGI_RSP_ERR_REASON 8
2060#define M_DBGI_RSP_ERR_REASON 0x7
2061#define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)
2062#define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)
2063
2064#define A_MC5_DBGI_RSP_DATA0 0xcb4
2065#define A_MC5_DBGI_RSP_DATA1 0xcb8
2066#define A_MC5_DBGI_RSP_DATA2 0xcbc
2067#define A_MC5_DBGI_RSP_DATA3 0xcc0
2068#define A_MC5_DBGI_RSP_DATA4 0xcc4
2069#define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2070#define A_MC5_POPEN_DATA_WR_CMD 0xccc
2071#define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2072#define A_MC5_AOPEN_SRCH_CMD 0xcd4
2073#define A_MC5_AOPEN_LRN_CMD 0xcd8
2074#define A_MC5_SYN_SRCH_CMD 0xcdc
2075#define A_MC5_SYN_LRN_CMD 0xce0
2076#define A_MC5_ACK_SRCH_CMD 0xce4
2077#define A_MC5_ACK_LRN_CMD 0xce8
2078#define A_MC5_ILOOKUP_CMD 0xcec
2079#define A_MC5_ELOOKUP_CMD 0xcf0
2080#define A_MC5_DATA_WRITE_CMD 0xcf4
2081#define A_MC5_DATA_READ_CMD 0xcf8
2082#define A_MC5_MASK_WRITE_CMD 0xcfc
2083
2084/* PCICFG registers */
442#define A_PCICFG_PM_CSR 0x44 2085#define A_PCICFG_PM_CSR 0x44
443#define A_PCICFG_VPD_ADDR 0x4a 2086#define A_PCICFG_VPD_ADDR 0x4a
444 2087
2088#define S_VPD_ADDR 0
2089#define M_VPD_ADDR 0x7fff
2090#define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)
2091#define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)
2092
445#define S_VPD_OP_FLAG 15 2093#define S_VPD_OP_FLAG 15
446#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG) 2094#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
447#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U) 2095#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)
448 2096
449#define A_PCICFG_VPD_DATA 0x4c 2097#define A_PCICFG_VPD_DATA 0x4c
450 2098#define A_PCICFG_PCIX_CMD 0x60
451#define A_PCICFG_INTR_ENABLE 0xf4 2099#define A_PCICFG_INTR_ENABLE 0xf4
452#define A_PCICFG_INTR_CAUSE 0xf8
453 2100
2101#define S_MASTER_PARITY_ERR 0
2102#define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)
2103#define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U)
2104
2105#define S_SIG_TARGET_ABORT 1
2106#define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)
2107#define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U)
2108
2109#define S_RCV_TARGET_ABORT 2
2110#define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)
2111#define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U)
2112
2113#define S_RCV_MASTER_ABORT 3
2114#define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)
2115#define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U)
2116
2117#define S_SIG_SYS_ERR 4
2118#define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)
2119#define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U)
2120
2121#define S_DET_PARITY_ERR 5
2122#define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)
2123#define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U)
2124
2125#define S_PIO_PARITY_ERR 6
2126#define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)
2127#define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U)
2128
2129#define S_WF_PARITY_ERR 7
2130#define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)
2131#define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U)
2132
2133#define S_RF_PARITY_ERR 8
2134#define M_RF_PARITY_ERR 0x3
2135#define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)
2136#define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)
2137
2138#define S_CF_PARITY_ERR 10
2139#define M_CF_PARITY_ERR 0x3
2140#define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)
2141#define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)
2142
2143#define A_PCICFG_INTR_CAUSE 0xf8
454#define A_PCICFG_MODE 0xfc 2144#define A_PCICFG_MODE 0xfc
455 2145
456#define S_PCI_MODE_64BIT 0 2146#define S_PCI_MODE_64BIT 0
457#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT) 2147#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
458#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U) 2148#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)
459 2149
2150#define S_PCI_MODE_66MHZ 1
2151#define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)
2152#define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U)
2153
2154#define S_PCI_MODE_PCIX_INITPAT 2
2155#define M_PCI_MODE_PCIX_INITPAT 0x7
2156#define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)
2157#define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)
2158
460#define S_PCI_MODE_PCIX 5 2159#define S_PCI_MODE_PCIX 5
461#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX) 2160#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
462#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U) 2161#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)
463 2162
464#define S_PCI_MODE_CLK 6 2163#define S_PCI_MODE_CLK 6
465#define M_PCI_MODE_CLK 0x3 2164#define M_PCI_MODE_CLK 0x3
2165#define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)
466#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK) 2166#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
467 2167
468#endif /* _CXGB_REGS_H_ */ 2168#endif /* _CXGB_REGS_H_ */
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index 9799c12380fc..0ca8d876e16f 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -42,12 +42,14 @@
42#include <linux/types.h> 42#include <linux/types.h>
43#include <linux/errno.h> 43#include <linux/errno.h>
44#include <linux/pci.h> 44#include <linux/pci.h>
45#include <linux/ktime.h>
45#include <linux/netdevice.h> 46#include <linux/netdevice.h>
46#include <linux/etherdevice.h> 47#include <linux/etherdevice.h>
47#include <linux/if_vlan.h> 48#include <linux/if_vlan.h>
48#include <linux/skbuff.h> 49#include <linux/skbuff.h>
49#include <linux/init.h> 50#include <linux/init.h>
50#include <linux/mm.h> 51#include <linux/mm.h>
52#include <linux/tcp.h>
51#include <linux/ip.h> 53#include <linux/ip.h>
52#include <linux/in.h> 54#include <linux/in.h>
53#include <linux/if_arp.h> 55#include <linux/if_arp.h>
@@ -57,10 +59,8 @@
57#include "regs.h" 59#include "regs.h"
58#include "espi.h" 60#include "espi.h"
59 61
60 62/* This belongs in if_ether.h */
61#ifdef NETIF_F_TSO 63#define ETH_P_CPL5 0xf
62#include <linux/tcp.h>
63#endif
64 64
65#define SGE_CMDQ_N 2 65#define SGE_CMDQ_N 2
66#define SGE_FREELQ_N 2 66#define SGE_FREELQ_N 2
@@ -73,6 +73,7 @@
73#define SGE_INTRTIMER_NRES 1000 73#define SGE_INTRTIMER_NRES 1000
74#define SGE_RX_COPY_THRES 256 74#define SGE_RX_COPY_THRES 256
75#define SGE_RX_SM_BUF_SIZE 1536 75#define SGE_RX_SM_BUF_SIZE 1536
76#define SGE_TX_DESC_MAX_PLEN 16384
76 77
77# define SGE_RX_DROP_THRES 2 78# define SGE_RX_DROP_THRES 2
78 79
@@ -184,17 +185,17 @@ struct cmdQ {
184 unsigned long status; /* HW DMA fetch status */ 185 unsigned long status; /* HW DMA fetch status */
185 unsigned int in_use; /* # of in-use command descriptors */ 186 unsigned int in_use; /* # of in-use command descriptors */
186 unsigned int size; /* # of descriptors */ 187 unsigned int size; /* # of descriptors */
187 unsigned int processed; /* total # of descs HW has processed */ 188 unsigned int processed; /* total # of descs HW has processed */
188 unsigned int cleaned; /* total # of descs SW has reclaimed */ 189 unsigned int cleaned; /* total # of descs SW has reclaimed */
189 unsigned int stop_thres; /* SW TX queue suspend threshold */ 190 unsigned int stop_thres; /* SW TX queue suspend threshold */
190 u16 pidx; /* producer index (SW) */ 191 u16 pidx; /* producer index (SW) */
191 u16 cidx; /* consumer index (HW) */ 192 u16 cidx; /* consumer index (HW) */
192 u8 genbit; /* current generation (=valid) bit */ 193 u8 genbit; /* current generation (=valid) bit */
193 u8 sop; /* is next entry start of packet? */ 194 u8 sop; /* is next entry start of packet? */
194 struct cmdQ_e *entries; /* HW command descriptor Q */ 195 struct cmdQ_e *entries; /* HW command descriptor Q */
195 struct cmdQ_ce *centries; /* SW command context descriptor Q */ 196 struct cmdQ_ce *centries; /* SW command context descriptor Q */
196 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
197 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ 197 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */
198 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
198}; 199};
199 200
200struct freelQ { 201struct freelQ {
@@ -203,8 +204,8 @@ struct freelQ {
203 u16 pidx; /* producer index (SW) */ 204 u16 pidx; /* producer index (SW) */
204 u16 cidx; /* consumer index (HW) */ 205 u16 cidx; /* consumer index (HW) */
205 u16 rx_buffer_size; /* Buffer size on this free list */ 206 u16 rx_buffer_size; /* Buffer size on this free list */
206 u16 dma_offset; /* DMA offset to align IP headers */ 207 u16 dma_offset; /* DMA offset to align IP headers */
207 u16 recycleq_idx; /* skb recycle q to use */ 208 u16 recycleq_idx; /* skb recycle q to use */
208 u8 genbit; /* current generation (=valid) bit */ 209 u8 genbit; /* current generation (=valid) bit */
209 struct freelQ_e *entries; /* HW freelist descriptor Q */ 210 struct freelQ_e *entries; /* HW freelist descriptor Q */
210 struct freelQ_ce *centries; /* SW freelist context descriptor Q */ 211 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
@@ -226,6 +227,29 @@ enum {
226 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ 227 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */
227}; 228};
228 229
230/* T204 TX SW scheduler */
231
232/* Per T204 TX port */
233struct sched_port {
234 unsigned int avail; /* available bits - quota */
235 unsigned int drain_bits_per_1024ns; /* drain rate */
236 unsigned int speed; /* drain rate, mbps */
237 unsigned int mtu; /* mtu size */
238 struct sk_buff_head skbq; /* pending skbs */
239};
240
241/* Per T204 device */
242struct sched {
243 ktime_t last_updated; /* last time quotas were computed */
244 unsigned int max_avail; /* max bits to be sent to any port */
245 unsigned int port; /* port index (round robin ports) */
246 unsigned int num; /* num skbs in per port queues */
247 struct sched_port p[MAX_NPORTS];
248 struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
249};
250static void restart_sched(unsigned long);
251
252
229/* 253/*
230 * Main SGE data structure 254 * Main SGE data structure
231 * 255 *
@@ -243,18 +267,240 @@ struct sge {
243 unsigned int rx_pkt_pad; /* RX padding for L2 packets */ 267 unsigned int rx_pkt_pad; /* RX padding for L2 packets */
244 unsigned int jumbo_fl; /* jumbo freelist Q index */ 268 unsigned int jumbo_fl; /* jumbo freelist Q index */
245 unsigned int intrtimer_nres; /* no-resource interrupt timer */ 269 unsigned int intrtimer_nres; /* no-resource interrupt timer */
246 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ 270 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
247 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ 271 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
248 struct timer_list espibug_timer; 272 struct timer_list espibug_timer;
249 unsigned int espibug_timeout; 273 unsigned long espibug_timeout;
250 struct sk_buff *espibug_skb; 274 struct sk_buff *espibug_skb[MAX_NPORTS];
251 u32 sge_control; /* shadow value of sge control reg */ 275 u32 sge_control; /* shadow value of sge control reg */
252 struct sge_intr_counts stats; 276 struct sge_intr_counts stats;
253 struct sge_port_stats port_stats[MAX_NPORTS]; 277 struct sge_port_stats *port_stats[MAX_NPORTS];
278 struct sched *tx_sched;
254 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; 279 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
255}; 280};
256 281
257/* 282/*
283 * stop tasklet and free all pending skb's
284 */
285static void tx_sched_stop(struct sge *sge)
286{
287 struct sched *s = sge->tx_sched;
288 int i;
289
290 tasklet_kill(&s->sched_tsk);
291
292 for (i = 0; i < MAX_NPORTS; i++)
293 __skb_queue_purge(&s->p[s->port].skbq);
294}
295
296/*
297 * t1_sched_update_parms() is called when the MTU or link speed changes. It
298 * re-computes scheduler parameters to scope with the change.
299 */
300unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
301 unsigned int mtu, unsigned int speed)
302{
303 struct sched *s = sge->tx_sched;
304 struct sched_port *p = &s->p[port];
305 unsigned int max_avail_segs;
306
307 pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
308 if (speed)
309 p->speed = speed;
310 if (mtu)
311 p->mtu = mtu;
312
313 if (speed || mtu) {
314 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
315 do_div(drain, (p->mtu + 50) * 1000);
316 p->drain_bits_per_1024ns = (unsigned int) drain;
317
318 if (p->speed < 1000)
319 p->drain_bits_per_1024ns =
320 90 * p->drain_bits_per_1024ns / 100;
321 }
322
323 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
324 p->drain_bits_per_1024ns -= 16;
325 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
326 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
327 } else {
328 s->max_avail = 16384;
329 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
330 }
331
332 pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
333 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
334 p->speed, s->max_avail, max_avail_segs,
335 p->drain_bits_per_1024ns);
336
337 return max_avail_segs * (p->mtu - 40);
338}
339
340/*
341 * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
342 * data that can be pushed per port.
343 */
344void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
345{
346 struct sched *s = sge->tx_sched;
347 unsigned int i;
348
349 s->max_avail = val;
350 for (i = 0; i < MAX_NPORTS; i++)
351 t1_sched_update_parms(sge, i, 0, 0);
352}
353
354/*
355 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
356 * is draining.
357 */
358void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
359 unsigned int val)
360{
361 struct sched *s = sge->tx_sched;
362 struct sched_port *p = &s->p[port];
363 p->drain_bits_per_1024ns = val * 1024 / 1000;
364 t1_sched_update_parms(sge, port, 0, 0);
365}
366
367
368/*
369 * get_clock() implements a ns clock (see ktime_get)
370 */
371static inline ktime_t get_clock(void)
372{
373 struct timespec ts;
374
375 ktime_get_ts(&ts);
376 return timespec_to_ktime(ts);
377}
378
379/*
380 * tx_sched_init() allocates resources and does basic initialization.
381 */
382static int tx_sched_init(struct sge *sge)
383{
384 struct sched *s;
385 int i;
386
387 s = kzalloc(sizeof (struct sched), GFP_KERNEL);
388 if (!s)
389 return -ENOMEM;
390
391 pr_debug("tx_sched_init\n");
392 tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
393 sge->tx_sched = s;
394
395 for (i = 0; i < MAX_NPORTS; i++) {
396 skb_queue_head_init(&s->p[i].skbq);
397 t1_sched_update_parms(sge, i, 1500, 1000);
398 }
399
400 return 0;
401}
402
403/*
404 * sched_update_avail() computes the delta since the last time it was called
405 * and updates the per port quota (number of bits that can be sent to the any
406 * port).
407 */
408static inline int sched_update_avail(struct sge *sge)
409{
410 struct sched *s = sge->tx_sched;
411 ktime_t now = get_clock();
412 unsigned int i;
413 long long delta_time_ns;
414
415 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
416
417 pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
418 if (delta_time_ns < 15000)
419 return 0;
420
421 for (i = 0; i < MAX_NPORTS; i++) {
422 struct sched_port *p = &s->p[i];
423 unsigned int delta_avail;
424
425 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
426 p->avail = min(p->avail + delta_avail, s->max_avail);
427 }
428
429 s->last_updated = now;
430
431 return 1;
432}
433
434/*
435 * sched_skb() is called from two different places. In the tx path, any
436 * packet generating load on an output port will call sched_skb()
437 * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
438 * context (skb == NULL).
439 * The scheduler only returns a skb (which will then be sent) if the
440 * length of the skb is <= the current quota of the output port.
441 */
442static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
443 unsigned int credits)
444{
445 struct sched *s = sge->tx_sched;
446 struct sk_buff_head *skbq;
447 unsigned int i, len, update = 1;
448
449 pr_debug("sched_skb %p\n", skb);
450 if (!skb) {
451 if (!s->num)
452 return NULL;
453 } else {
454 skbq = &s->p[skb->dev->if_port].skbq;
455 __skb_queue_tail(skbq, skb);
456 s->num++;
457 skb = NULL;
458 }
459
460 if (credits < MAX_SKB_FRAGS + 1)
461 goto out;
462
463 again:
464 for (i = 0; i < MAX_NPORTS; i++) {
465 s->port = ++s->port & (MAX_NPORTS - 1);
466 skbq = &s->p[s->port].skbq;
467
468 skb = skb_peek(skbq);
469
470 if (!skb)
471 continue;
472
473 len = skb->len;
474 if (len <= s->p[s->port].avail) {
475 s->p[s->port].avail -= len;
476 s->num--;
477 __skb_unlink(skb, skbq);
478 goto out;
479 }
480 skb = NULL;
481 }
482
483 if (update-- && sched_update_avail(sge))
484 goto again;
485
486 out:
487 /* If there are more pending skbs, we use the hardware to schedule us
488 * again.
489 */
490 if (s->num && !skb) {
491 struct cmdQ *q = &sge->cmdQ[0];
492 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
493 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
494 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
495 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
496 }
497 }
498 pr_debug("sched_skb ret %p\n", skb);
499
500 return skb;
501}
502
503/*
258 * PIO to indicate that memory mapped Q contains valid descriptor(s). 504 * PIO to indicate that memory mapped Q contains valid descriptor(s).
259 */ 505 */
260static inline void doorbell_pio(struct adapter *adapter, u32 val) 506static inline void doorbell_pio(struct adapter *adapter, u32 val)
@@ -335,10 +581,9 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
335 goto err_no_mem; 581 goto err_no_mem;
336 memset(q->entries, 0, size); 582 memset(q->entries, 0, size);
337 size = sizeof(struct freelQ_ce) * q->size; 583 size = sizeof(struct freelQ_ce) * q->size;
338 q->centries = kmalloc(size, GFP_KERNEL); 584 q->centries = kzalloc(size, GFP_KERNEL);
339 if (!q->centries) 585 if (!q->centries)
340 goto err_no_mem; 586 goto err_no_mem;
341 memset(q->centries, 0, size);
342 } 587 }
343 588
344 /* 589 /*
@@ -351,8 +596,11 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
351 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + 596 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
352 sizeof(struct cpl_rx_data) + 597 sizeof(struct cpl_rx_data) +
353 sge->freelQ[!sge->jumbo_fl].dma_offset; 598 sge->freelQ[!sge->jumbo_fl].dma_offset;
354 sge->freelQ[sge->jumbo_fl].rx_buffer_size = (16 * 1024) - 599
355 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 600 size = (16 * 1024) -
601 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
602
603 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
356 604
357 /* 605 /*
358 * Setup which skb recycle Q should be used when recycling buffers from 606 * Setup which skb recycle Q should be used when recycling buffers from
@@ -389,17 +637,23 @@ static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
389 q->in_use -= n; 637 q->in_use -= n;
390 ce = &q->centries[cidx]; 638 ce = &q->centries[cidx];
391 while (n--) { 639 while (n--) {
392 if (q->sop) 640 if (q->sop) {
393 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), 641 if (likely(pci_unmap_len(ce, dma_len))) {
394 pci_unmap_len(ce, dma_len), 642 pci_unmap_single(pdev,
395 PCI_DMA_TODEVICE); 643 pci_unmap_addr(ce, dma_addr),
396 else 644 pci_unmap_len(ce, dma_len),
397 pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr), 645 PCI_DMA_TODEVICE);
398 pci_unmap_len(ce, dma_len), 646 q->sop = 0;
399 PCI_DMA_TODEVICE); 647 }
400 q->sop = 0; 648 } else {
649 if (likely(pci_unmap_len(ce, dma_len))) {
650 pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr),
651 pci_unmap_len(ce, dma_len),
652 PCI_DMA_TODEVICE);
653 }
654 }
401 if (ce->skb) { 655 if (ce->skb) {
402 dev_kfree_skb(ce->skb); 656 dev_kfree_skb_any(ce->skb);
403 q->sop = 1; 657 q->sop = 1;
404 } 658 }
405 ce++; 659 ce++;
@@ -463,10 +717,9 @@ static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
463 goto err_no_mem; 717 goto err_no_mem;
464 memset(q->entries, 0, size); 718 memset(q->entries, 0, size);
465 size = sizeof(struct cmdQ_ce) * q->size; 719 size = sizeof(struct cmdQ_ce) * q->size;
466 q->centries = kmalloc(size, GFP_KERNEL); 720 q->centries = kzalloc(size, GFP_KERNEL);
467 if (!q->centries) 721 if (!q->centries)
468 goto err_no_mem; 722 goto err_no_mem;
469 memset(q->centries, 0, size);
470 } 723 }
471 724
472 /* 725 /*
@@ -506,7 +759,7 @@ void t1_set_vlan_accel(struct adapter *adapter, int on_off)
506 sge->sge_control |= F_VLAN_XTRACT; 759 sge->sge_control |= F_VLAN_XTRACT;
507 if (adapter->open_device_map) { 760 if (adapter->open_device_map) {
508 writel(sge->sge_control, adapter->regs + A_SG_CONTROL); 761 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
509 readl(adapter->regs + A_SG_CONTROL); /* flush */ 762 readl(adapter->regs + A_SG_CONTROL); /* flush */
510 } 763 }
511} 764}
512 765
@@ -540,7 +793,6 @@ static void configure_sge(struct sge *sge, struct sge_params *p)
540 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | 793 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
541 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | 794 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
542 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | 795 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
543 F_DISABLE_FL0_GTS | F_DISABLE_FL1_GTS |
544 V_RX_PKT_OFFSET(sge->rx_pkt_pad); 796 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
545 797
546#if defined(__BIG_ENDIAN_BITFIELD) 798#if defined(__BIG_ENDIAN_BITFIELD)
@@ -568,9 +820,12 @@ static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
568 */ 820 */
569void t1_sge_destroy(struct sge *sge) 821void t1_sge_destroy(struct sge *sge)
570{ 822{
571 if (sge->espibug_skb) 823 int i;
572 kfree_skb(sge->espibug_skb);
573 824
825 for_each_port(sge->adapter, i)
826 free_percpu(sge->port_stats[i]);
827
828 kfree(sge->tx_sched);
574 free_tx_resources(sge); 829 free_tx_resources(sge);
575 free_rx_resources(sge); 830 free_rx_resources(sge);
576 kfree(sge); 831 kfree(sge);
@@ -735,14 +990,28 @@ int t1_sge_intr_error_handler(struct sge *sge)
735 return 0; 990 return 0;
736} 991}
737 992
738const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge) 993const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
739{ 994{
740 return &sge->stats; 995 return &sge->stats;
741} 996}
742 997
743const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port) 998void t1_sge_get_port_stats(const struct sge *sge, int port,
999 struct sge_port_stats *ss)
744{ 1000{
745 return &sge->port_stats[port]; 1001 int cpu;
1002
1003 memset(ss, 0, sizeof(*ss));
1004 for_each_possible_cpu(cpu) {
1005 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
1006
1007 ss->rx_packets += st->rx_packets;
1008 ss->rx_cso_good += st->rx_cso_good;
1009 ss->tx_packets += st->tx_packets;
1010 ss->tx_cso += st->tx_cso;
1011 ss->tx_tso += st->tx_tso;
1012 ss->vlan_xtract += st->vlan_xtract;
1013 ss->vlan_insert += st->vlan_insert;
1014 }
746} 1015}
747 1016
748/** 1017/**
@@ -856,6 +1125,99 @@ static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
856} 1125}
857 1126
858/* 1127/*
1128 * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1129 * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1130 * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1131 * Note that the *_large_page_tx_descs stuff will be optimized out when
1132 * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1133 *
1134 * compute_large_page_descs() computes how many additional descriptors are
1135 * required to break down the stack's request.
1136 */
1137static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1138{
1139 unsigned int count = 0;
1140 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1141 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1142 unsigned int i, len = skb->len - skb->data_len;
1143 while (len > SGE_TX_DESC_MAX_PLEN) {
1144 count++;
1145 len -= SGE_TX_DESC_MAX_PLEN;
1146 }
1147 for (i = 0; nfrags--; i++) {
1148 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1149 len = frag->size;
1150 while (len > SGE_TX_DESC_MAX_PLEN) {
1151 count++;
1152 len -= SGE_TX_DESC_MAX_PLEN;
1153 }
1154 }
1155 }
1156 return count;
1157}
1158
1159/*
1160 * Write a cmdQ entry.
1161 *
1162 * Since this function writes the 'flags' field, it must not be used to
1163 * write the first cmdQ entry.
1164 */
1165static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1166 unsigned int len, unsigned int gen,
1167 unsigned int eop)
1168{
1169 if (unlikely(len > SGE_TX_DESC_MAX_PLEN))
1170 BUG();
1171 e->addr_lo = (u32)mapping;
1172 e->addr_hi = (u64)mapping >> 32;
1173 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1174 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1175}
1176
1177/*
1178 * See comment for previous function.
1179 *
1180 * write_tx_descs_large_page() writes additional SGE tx descriptors if
1181 * *desc_len exceeds HW's capability.
1182 */
1183static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1184 struct cmdQ_e **e,
1185 struct cmdQ_ce **ce,
1186 unsigned int *gen,
1187 dma_addr_t *desc_mapping,
1188 unsigned int *desc_len,
1189 unsigned int nfrags,
1190 struct cmdQ *q)
1191{
1192 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1193 struct cmdQ_e *e1 = *e;
1194 struct cmdQ_ce *ce1 = *ce;
1195
1196 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1197 *desc_len -= SGE_TX_DESC_MAX_PLEN;
1198 write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1199 *gen, nfrags == 0 && *desc_len == 0);
1200 ce1->skb = NULL;
1201 pci_unmap_len_set(ce1, dma_len, 0);
1202 *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1203 if (*desc_len) {
1204 ce1++;
1205 e1++;
1206 if (++pidx == q->size) {
1207 pidx = 0;
1208 *gen ^= 1;
1209 ce1 = q->centries;
1210 e1 = q->entries;
1211 }
1212 }
1213 }
1214 *e = e1;
1215 *ce = ce1;
1216 }
1217 return pidx;
1218}
1219
1220/*
859 * Write the command descriptors to transmit the given skb starting at 1221 * Write the command descriptors to transmit the given skb starting at
860 * descriptor pidx with the given generation. 1222 * descriptor pidx with the given generation.
861 */ 1223 */
@@ -863,50 +1225,84 @@ static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
863 unsigned int pidx, unsigned int gen, 1225 unsigned int pidx, unsigned int gen,
864 struct cmdQ *q) 1226 struct cmdQ *q)
865{ 1227{
866 dma_addr_t mapping; 1228 dma_addr_t mapping, desc_mapping;
867 struct cmdQ_e *e, *e1; 1229 struct cmdQ_e *e, *e1;
868 struct cmdQ_ce *ce; 1230 struct cmdQ_ce *ce;
869 unsigned int i, flags, nfrags = skb_shinfo(skb)->nr_frags; 1231 unsigned int i, flags, first_desc_len, desc_len,
1232 nfrags = skb_shinfo(skb)->nr_frags;
870 1233
871 mapping = pci_map_single(adapter->pdev, skb->data, 1234 e = e1 = &q->entries[pidx];
872 skb->len - skb->data_len, PCI_DMA_TODEVICE);
873 ce = &q->centries[pidx]; 1235 ce = &q->centries[pidx];
1236
1237 mapping = pci_map_single(adapter->pdev, skb->data,
1238 skb->len - skb->data_len, PCI_DMA_TODEVICE);
1239
1240 desc_mapping = mapping;
1241 desc_len = skb->len - skb->data_len;
1242
1243 flags = F_CMD_DATAVALID | F_CMD_SOP |
1244 V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1245 V_CMD_GEN2(gen);
1246 first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1247 desc_len : SGE_TX_DESC_MAX_PLEN;
1248 e->addr_lo = (u32)desc_mapping;
1249 e->addr_hi = (u64)desc_mapping >> 32;
1250 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1251 ce->skb = NULL;
1252 pci_unmap_len_set(ce, dma_len, 0);
1253
1254 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1255 desc_len > SGE_TX_DESC_MAX_PLEN) {
1256 desc_mapping += first_desc_len;
1257 desc_len -= first_desc_len;
1258 e1++;
1259 ce++;
1260 if (++pidx == q->size) {
1261 pidx = 0;
1262 gen ^= 1;
1263 e1 = q->entries;
1264 ce = q->centries;
1265 }
1266 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1267 &desc_mapping, &desc_len,
1268 nfrags, q);
1269
1270 if (likely(desc_len))
1271 write_tx_desc(e1, desc_mapping, desc_len, gen,
1272 nfrags == 0);
1273 }
1274
874 ce->skb = NULL; 1275 ce->skb = NULL;
875 pci_unmap_addr_set(ce, dma_addr, mapping); 1276 pci_unmap_addr_set(ce, dma_addr, mapping);
876 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len); 1277 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len);
877 1278
878 flags = F_CMD_DATAVALID | F_CMD_SOP | V_CMD_EOP(nfrags == 0) | 1279 for (i = 0; nfrags--; i++) {
879 V_CMD_GEN2(gen);
880 e = &q->entries[pidx];
881 e->addr_lo = (u32)mapping;
882 e->addr_hi = (u64)mapping >> 32;
883 e->len_gen = V_CMD_LEN(skb->len - skb->data_len) | V_CMD_GEN1(gen);
884 for (e1 = e, i = 0; nfrags--; i++) {
885 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1280 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
886
887 ce++;
888 e1++; 1281 e1++;
1282 ce++;
889 if (++pidx == q->size) { 1283 if (++pidx == q->size) {
890 pidx = 0; 1284 pidx = 0;
891 gen ^= 1; 1285 gen ^= 1;
892 ce = q->centries;
893 e1 = q->entries; 1286 e1 = q->entries;
1287 ce = q->centries;
894 } 1288 }
895 1289
896 mapping = pci_map_page(adapter->pdev, frag->page, 1290 mapping = pci_map_page(adapter->pdev, frag->page,
897 frag->page_offset, frag->size, 1291 frag->page_offset, frag->size,
898 PCI_DMA_TODEVICE); 1292 PCI_DMA_TODEVICE);
1293 desc_mapping = mapping;
1294 desc_len = frag->size;
1295
1296 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1297 &desc_mapping, &desc_len,
1298 nfrags, q);
1299 if (likely(desc_len))
1300 write_tx_desc(e1, desc_mapping, desc_len, gen,
1301 nfrags == 0);
899 ce->skb = NULL; 1302 ce->skb = NULL;
900 pci_unmap_addr_set(ce, dma_addr, mapping); 1303 pci_unmap_addr_set(ce, dma_addr, mapping);
901 pci_unmap_len_set(ce, dma_len, frag->size); 1304 pci_unmap_len_set(ce, dma_len, frag->size);
902
903 e1->addr_lo = (u32)mapping;
904 e1->addr_hi = (u64)mapping >> 32;
905 e1->len_gen = V_CMD_LEN(frag->size) | V_CMD_GEN1(gen);
906 e1->flags = F_CMD_DATAVALID | V_CMD_EOP(nfrags == 0) |
907 V_CMD_GEN2(gen);
908 } 1305 }
909
910 ce->skb = skb; 1306 ce->skb = skb;
911 wmb(); 1307 wmb();
912 e->flags = flags; 1308 e->flags = flags;
@@ -920,26 +1316,56 @@ static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
920 unsigned int reclaim = q->processed - q->cleaned; 1316 unsigned int reclaim = q->processed - q->cleaned;
921 1317
922 if (reclaim) { 1318 if (reclaim) {
1319 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1320 q->processed, q->cleaned);
923 free_cmdQ_buffers(sge, q, reclaim); 1321 free_cmdQ_buffers(sge, q, reclaim);
924 q->cleaned += reclaim; 1322 q->cleaned += reclaim;
925 } 1323 }
926} 1324}
927 1325
928#ifndef SET_ETHTOOL_OPS
929# define __netif_rx_complete(dev) netif_rx_complete(dev)
930#endif
931
932/* 1326/*
933 * We cannot use the standard netif_rx_schedule_prep() because we have multiple 1327 * Called from tasklet. Checks the scheduler for any
934 * ports plus the TOE all multiplexing onto a single response queue, therefore 1328 * pending skbs that can be sent.
935 * accepting new responses cannot depend on the state of any particular port.
936 * So define our own equivalent that omits the netif_running() test.
937 */ 1329 */
938static inline int napi_schedule_prep(struct net_device *dev) 1330static void restart_sched(unsigned long arg)
939{ 1331{
940 return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state); 1332 struct sge *sge = (struct sge *) arg;
941} 1333 struct adapter *adapter = sge->adapter;
1334 struct cmdQ *q = &sge->cmdQ[0];
1335 struct sk_buff *skb;
1336 unsigned int credits, queued_skb = 0;
942 1337
1338 spin_lock(&q->lock);
1339 reclaim_completed_tx(sge, q);
1340
1341 credits = q->size - q->in_use;
1342 pr_debug("restart_sched credits=%d\n", credits);
1343 while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1344 unsigned int genbit, pidx, count;
1345 count = 1 + skb_shinfo(skb)->nr_frags;
1346 count += compute_large_page_tx_descs(skb);
1347 q->in_use += count;
1348 genbit = q->genbit;
1349 pidx = q->pidx;
1350 q->pidx += count;
1351 if (q->pidx >= q->size) {
1352 q->pidx -= q->size;
1353 q->genbit ^= 1;
1354 }
1355 write_tx_descs(adapter, skb, pidx, genbit, q);
1356 credits = q->size - q->in_use;
1357 queued_skb = 1;
1358 }
1359
1360 if (queued_skb) {
1361 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1362 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1363 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1364 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1365 }
1366 }
1367 spin_unlock(&q->lock);
1368}
943 1369
944/** 1370/**
945 * sge_rx - process an ingress ethernet packet 1371 * sge_rx - process an ingress ethernet packet
@@ -954,31 +1380,39 @@ static int sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
954 struct sk_buff *skb; 1380 struct sk_buff *skb;
955 struct cpl_rx_pkt *p; 1381 struct cpl_rx_pkt *p;
956 struct adapter *adapter = sge->adapter; 1382 struct adapter *adapter = sge->adapter;
1383 struct sge_port_stats *st;
957 1384
958 sge->stats.ethernet_pkts++;
959 skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad, 1385 skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad,
960 sge->rx_pkt_pad, 2, SGE_RX_COPY_THRES, 1386 sge->rx_pkt_pad, 2, SGE_RX_COPY_THRES,
961 SGE_RX_DROP_THRES); 1387 SGE_RX_DROP_THRES);
962 if (!skb) { 1388 if (unlikely(!skb)) {
963 sge->port_stats[0].rx_drops++; /* charge only port 0 for now */ 1389 sge->stats.rx_drops++;
964 return 0; 1390 return 0;
965 } 1391 }
966 1392
967 p = (struct cpl_rx_pkt *)skb->data; 1393 p = (struct cpl_rx_pkt *)skb->data;
968 skb_pull(skb, sizeof(*p)); 1394 skb_pull(skb, sizeof(*p));
1395 if (p->iff >= adapter->params.nports) {
1396 kfree_skb(skb);
1397 return 0;
1398 }
1399
969 skb->dev = adapter->port[p->iff].dev; 1400 skb->dev = adapter->port[p->iff].dev;
970 skb->dev->last_rx = jiffies; 1401 skb->dev->last_rx = jiffies;
1402 st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id());
1403 st->rx_packets++;
1404
971 skb->protocol = eth_type_trans(skb, skb->dev); 1405 skb->protocol = eth_type_trans(skb, skb->dev);
972 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff && 1406 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
973 skb->protocol == htons(ETH_P_IP) && 1407 skb->protocol == htons(ETH_P_IP) &&
974 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { 1408 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
975 sge->port_stats[p->iff].rx_cso_good++; 1409 ++st->rx_cso_good;
976 skb->ip_summed = CHECKSUM_UNNECESSARY; 1410 skb->ip_summed = CHECKSUM_UNNECESSARY;
977 } else 1411 } else
978 skb->ip_summed = CHECKSUM_NONE; 1412 skb->ip_summed = CHECKSUM_NONE;
979 1413
980 if (unlikely(adapter->vlan_grp && p->vlan_valid)) { 1414 if (unlikely(adapter->vlan_grp && p->vlan_valid)) {
981 sge->port_stats[p->iff].vlan_xtract++; 1415 st->vlan_xtract++;
982 if (adapter->params.sge.polling) 1416 if (adapter->params.sge.polling)
983 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, 1417 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp,
984 ntohs(p->vlan)); 1418 ntohs(p->vlan));
@@ -1039,18 +1473,24 @@ static unsigned int update_tx_info(struct adapter *adapter,
1039 struct cmdQ *cmdq = &sge->cmdQ[0]; 1473 struct cmdQ *cmdq = &sge->cmdQ[0];
1040 1474
1041 cmdq->processed += pr0; 1475 cmdq->processed += pr0;
1042 1476 if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1477 freelQs_empty(sge);
1478 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1479 }
1043 if (flags & F_CMDQ0_ENABLE) { 1480 if (flags & F_CMDQ0_ENABLE) {
1044 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); 1481 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1045 1482
1046 if (cmdq->cleaned + cmdq->in_use != cmdq->processed && 1483 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1047 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { 1484 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1048 set_bit(CMDQ_STAT_RUNNING, &cmdq->status); 1485 set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1049 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1486 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1050 } 1487 }
1051 flags &= ~F_CMDQ0_ENABLE; 1488 if (sge->tx_sched)
1489 tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1490
1491 flags &= ~F_CMDQ0_ENABLE;
1052 } 1492 }
1053 1493
1054 if (unlikely(sge->stopped_tx_queues != 0)) 1494 if (unlikely(sge->stopped_tx_queues != 0))
1055 restart_tx_queues(sge); 1495 restart_tx_queues(sge);
1056 1496
@@ -1241,20 +1681,21 @@ static irqreturn_t t1_interrupt_napi(int irq, void *data)
1241 if (e->GenerationBit == q->genbit) { 1681 if (e->GenerationBit == q->genbit) {
1242 if (e->DataValid || 1682 if (e->DataValid ||
1243 process_pure_responses(adapter, e)) { 1683 process_pure_responses(adapter, e)) {
1244 if (likely(napi_schedule_prep(sge->netdev))) 1684 if (likely(__netif_rx_schedule_prep(sge->netdev)))
1245 __netif_rx_schedule(sge->netdev); 1685 __netif_rx_schedule(sge->netdev);
1246 else 1686 else if (net_ratelimit())
1247 printk(KERN_CRIT 1687 printk(KERN_INFO
1248 "NAPI schedule failure!\n"); 1688 "NAPI schedule failure!\n");
1249 } else 1689 } else
1250 writel(q->cidx, adapter->regs + A_SG_SLEEPING); 1690 writel(q->cidx, adapter->regs + A_SG_SLEEPING);
1691
1251 handled = 1; 1692 handled = 1;
1252 goto unlock; 1693 goto unlock;
1253 } else 1694 } else
1254 writel(q->cidx, adapter->regs + A_SG_SLEEPING); 1695 writel(q->cidx, adapter->regs + A_SG_SLEEPING);
1255 } else 1696 } else if (readl(adapter->regs + A_PL_CAUSE) & F_PL_INTR_SGE_DATA) {
1256 if (readl(adapter->regs + A_PL_CAUSE) & F_PL_INTR_SGE_DATA) 1697 printk(KERN_ERR "data interrupt while NAPI running\n");
1257 printk(KERN_ERR "data interrupt while NAPI running\n"); 1698 }
1258 1699
1259 handled = t1_slow_intr_handler(adapter); 1700 handled = t1_slow_intr_handler(adapter);
1260 if (!handled) 1701 if (!handled)
@@ -1335,34 +1776,59 @@ static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1335{ 1776{
1336 struct sge *sge = adapter->sge; 1777 struct sge *sge = adapter->sge;
1337 struct cmdQ *q = &sge->cmdQ[qid]; 1778 struct cmdQ *q = &sge->cmdQ[qid];
1338 unsigned int credits, pidx, genbit, count; 1779 unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1780
1781 if (!spin_trylock(&q->lock))
1782 return NETDEV_TX_LOCKED;
1339 1783
1340 spin_lock(&q->lock);
1341 reclaim_completed_tx(sge, q); 1784 reclaim_completed_tx(sge, q);
1342 1785
1343 pidx = q->pidx; 1786 pidx = q->pidx;
1344 credits = q->size - q->in_use; 1787 credits = q->size - q->in_use;
1345 count = 1 + skb_shinfo(skb)->nr_frags; 1788 count = 1 + skb_shinfo(skb)->nr_frags;
1789 count += compute_large_page_tx_descs(skb);
1346 1790
1347 { /* Ethernet packet */ 1791 /* Ethernet packet */
1348 if (unlikely(credits < count)) { 1792 if (unlikely(credits < count)) {
1793 if (!netif_queue_stopped(dev)) {
1349 netif_stop_queue(dev); 1794 netif_stop_queue(dev);
1350 set_bit(dev->if_port, &sge->stopped_tx_queues); 1795 set_bit(dev->if_port, &sge->stopped_tx_queues);
1351 sge->stats.cmdQ_full[2]++; 1796 sge->stats.cmdQ_full[2]++;
1352 spin_unlock(&q->lock); 1797 CH_ERR("%s: Tx ring full while queue awake!\n",
1353 if (!netif_queue_stopped(dev)) 1798 adapter->name);
1354 CH_ERR("%s: Tx ring full while queue awake!\n",
1355 adapter->name);
1356 return NETDEV_TX_BUSY;
1357 } 1799 }
1358 if (unlikely(credits - count < q->stop_thres)) { 1800 spin_unlock(&q->lock);
1359 sge->stats.cmdQ_full[2]++; 1801 return NETDEV_TX_BUSY;
1360 netif_stop_queue(dev); 1802 }
1361 set_bit(dev->if_port, &sge->stopped_tx_queues); 1803
1804 if (unlikely(credits - count < q->stop_thres)) {
1805 netif_stop_queue(dev);
1806 set_bit(dev->if_port, &sge->stopped_tx_queues);
1807 sge->stats.cmdQ_full[2]++;
1808 }
1809
1810 /* T204 cmdQ0 skbs that are destined for a certain port have to go
1811 * through the scheduler.
1812 */
1813 if (sge->tx_sched && !qid && skb->dev) {
1814 use_sched:
1815 use_sched_skb = 1;
1816 /* Note that the scheduler might return a different skb than
1817 * the one passed in.
1818 */
1819 skb = sched_skb(sge, skb, credits);
1820 if (!skb) {
1821 spin_unlock(&q->lock);
1822 return NETDEV_TX_OK;
1362 } 1823 }
1824 pidx = q->pidx;
1825 count = 1 + skb_shinfo(skb)->nr_frags;
1826 count += compute_large_page_tx_descs(skb);
1363 } 1827 }
1828
1364 q->in_use += count; 1829 q->in_use += count;
1365 genbit = q->genbit; 1830 genbit = q->genbit;
1831 pidx = q->pidx;
1366 q->pidx += count; 1832 q->pidx += count;
1367 if (q->pidx >= q->size) { 1833 if (q->pidx >= q->size) {
1368 q->pidx -= q->size; 1834 q->pidx -= q->size;
@@ -1388,6 +1854,14 @@ static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1388 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1854 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1389 } 1855 }
1390 } 1856 }
1857
1858 if (use_sched_skb) {
1859 if (spin_trylock(&q->lock)) {
1860 credits = q->size - q->in_use;
1861 skb = NULL;
1862 goto use_sched;
1863 }
1864 }
1391 return NETDEV_TX_OK; 1865 return NETDEV_TX_OK;
1392} 1866}
1393 1867
@@ -1412,16 +1886,20 @@ static inline int eth_hdr_len(const void *data)
1412int t1_start_xmit(struct sk_buff *skb, struct net_device *dev) 1886int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1413{ 1887{
1414 struct adapter *adapter = dev->priv; 1888 struct adapter *adapter = dev->priv;
1415 struct sge_port_stats *st = &adapter->sge->port_stats[dev->if_port];
1416 struct sge *sge = adapter->sge; 1889 struct sge *sge = adapter->sge;
1890 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port], smp_processor_id());
1417 struct cpl_tx_pkt *cpl; 1891 struct cpl_tx_pkt *cpl;
1892 struct sk_buff *orig_skb = skb;
1893 int ret;
1894
1895 if (skb->protocol == htons(ETH_P_CPL5))
1896 goto send;
1418 1897
1419#ifdef NETIF_F_TSO 1898 if (skb_shinfo(skb)->gso_size) {
1420 if (skb_is_gso(skb)) {
1421 int eth_type; 1899 int eth_type;
1422 struct cpl_tx_pkt_lso *hdr; 1900 struct cpl_tx_pkt_lso *hdr;
1423 1901
1424 st->tso++; 1902 ++st->tx_tso;
1425 1903
1426 eth_type = skb->nh.raw - skb->data == ETH_HLEN ? 1904 eth_type = skb->nh.raw - skb->data == ETH_HLEN ?
1427 CPL_ETH_II : CPL_ETH_II_VLAN; 1905 CPL_ETH_II : CPL_ETH_II_VLAN;
@@ -1432,13 +1910,10 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1432 hdr->ip_hdr_words = skb->nh.iph->ihl; 1910 hdr->ip_hdr_words = skb->nh.iph->ihl;
1433 hdr->tcp_hdr_words = skb->h.th->doff; 1911 hdr->tcp_hdr_words = skb->h.th->doff;
1434 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, 1912 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1435 skb_shinfo(skb)->gso_size)); 1913 skb_shinfo(skb)->gso_size));
1436 hdr->len = htonl(skb->len - sizeof(*hdr)); 1914 hdr->len = htonl(skb->len - sizeof(*hdr));
1437 cpl = (struct cpl_tx_pkt *)hdr; 1915 cpl = (struct cpl_tx_pkt *)hdr;
1438 sge->stats.tx_lso_pkts++; 1916 } else {
1439 } else
1440#endif
1441 {
1442 /* 1917 /*
1443 * Packets shorter than ETH_HLEN can break the MAC, drop them 1918 * Packets shorter than ETH_HLEN can break the MAC, drop them
1444 * early. Also, we may get oversized packets because some 1919 * early. Also, we may get oversized packets because some
@@ -1447,6 +1922,8 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1447 */ 1922 */
1448 if (unlikely(skb->len < ETH_HLEN || 1923 if (unlikely(skb->len < ETH_HLEN ||
1449 skb->len > dev->mtu + eth_hdr_len(skb->data))) { 1924 skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1925 pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1926 skb->len, eth_hdr_len(skb->data), dev->mtu);
1450 dev_kfree_skb_any(skb); 1927 dev_kfree_skb_any(skb);
1451 return NETDEV_TX_OK; 1928 return NETDEV_TX_OK;
1452 } 1929 }
@@ -1456,9 +1933,9 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1456 * components, such as pktgen, do not handle it right. 1933 * components, such as pktgen, do not handle it right.
1457 * Complain when this happens but try to fix things up. 1934 * Complain when this happens but try to fix things up.
1458 */ 1935 */
1459 if (unlikely(skb_headroom(skb) < 1936 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1460 dev->hard_header_len - ETH_HLEN)) { 1937 pr_debug("%s: headroom %d header_len %d\n", dev->name,
1461 struct sk_buff *orig_skb = skb; 1938 skb_headroom(skb), dev->hard_header_len);
1462 1939
1463 if (net_ratelimit()) 1940 if (net_ratelimit())
1464 printk(KERN_ERR "%s: inadequate headroom in " 1941 printk(KERN_ERR "%s: inadequate headroom in "
@@ -1471,19 +1948,21 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1471 1948
1472 if (!(adapter->flags & UDP_CSUM_CAPABLE) && 1949 if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
1473 skb->ip_summed == CHECKSUM_PARTIAL && 1950 skb->ip_summed == CHECKSUM_PARTIAL &&
1474 skb->nh.iph->protocol == IPPROTO_UDP) 1951 skb->nh.iph->protocol == IPPROTO_UDP) {
1475 if (unlikely(skb_checksum_help(skb))) { 1952 if (unlikely(skb_checksum_help(skb))) {
1953 pr_debug("%s: unable to do udp checksum\n", dev->name);
1476 dev_kfree_skb_any(skb); 1954 dev_kfree_skb_any(skb);
1477 return NETDEV_TX_OK; 1955 return NETDEV_TX_OK;
1478 } 1956 }
1957 }
1479 1958
1480 /* Hmmm, assuming to catch the gratious arp... and we'll use 1959 /* Hmmm, assuming to catch the gratious arp... and we'll use
1481 * it to flush out stuck espi packets... 1960 * it to flush out stuck espi packets...
1482 */ 1961 */
1483 if (unlikely(!adapter->sge->espibug_skb)) { 1962 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1484 if (skb->protocol == htons(ETH_P_ARP) && 1963 if (skb->protocol == htons(ETH_P_ARP) &&
1485 skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) { 1964 skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) {
1486 adapter->sge->espibug_skb = skb; 1965 adapter->sge->espibug_skb[dev->if_port] = skb;
1487 /* We want to re-use this skb later. We 1966 /* We want to re-use this skb later. We
1488 * simply bump the reference count and it 1967 * simply bump the reference count and it
1489 * will not be freed... 1968 * will not be freed...
@@ -1499,8 +1978,6 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1499 /* the length field isn't used so don't bother setting it */ 1978 /* the length field isn't used so don't bother setting it */
1500 1979
1501 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); 1980 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1502 sge->stats.tx_do_cksum += (skb->ip_summed == CHECKSUM_PARTIAL);
1503 sge->stats.tx_reg_pkts++;
1504 } 1981 }
1505 cpl->iff = dev->if_port; 1982 cpl->iff = dev->if_port;
1506 1983
@@ -1513,8 +1990,19 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1513#endif 1990#endif
1514 cpl->vlan_valid = 0; 1991 cpl->vlan_valid = 0;
1515 1992
1993send:
1994 st->tx_packets++;
1516 dev->trans_start = jiffies; 1995 dev->trans_start = jiffies;
1517 return t1_sge_tx(skb, adapter, 0, dev); 1996 ret = t1_sge_tx(skb, adapter, 0, dev);
1997
1998 /* If transmit busy, and we reallocated skb's due to headroom limit,
1999 * then silently discard to avoid leak.
2000 */
2001 if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
2002 dev_kfree_skb_any(skb);
2003 ret = NETDEV_TX_OK;
2004 }
2005 return ret;
1518} 2006}
1519 2007
1520/* 2008/*
@@ -1532,10 +2020,9 @@ static void sge_tx_reclaim_cb(unsigned long data)
1532 continue; 2020 continue;
1533 2021
1534 reclaim_completed_tx(sge, q); 2022 reclaim_completed_tx(sge, q);
1535 if (i == 0 && q->in_use) /* flush pending credits */ 2023 if (i == 0 && q->in_use) { /* flush pending credits */
1536 writel(F_CMDQ0_ENABLE, 2024 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1537 sge->adapter->regs + A_SG_DOORBELL); 2025 }
1538
1539 spin_unlock(&q->lock); 2026 spin_unlock(&q->lock);
1540 } 2027 }
1541 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 2028 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
@@ -1582,11 +2069,20 @@ int t1_sge_configure(struct sge *sge, struct sge_params *p)
1582 */ 2069 */
1583void t1_sge_stop(struct sge *sge) 2070void t1_sge_stop(struct sge *sge)
1584{ 2071{
2072 int i;
1585 writel(0, sge->adapter->regs + A_SG_CONTROL); 2073 writel(0, sge->adapter->regs + A_SG_CONTROL);
1586 (void) readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ 2074 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
2075
1587 if (is_T2(sge->adapter)) 2076 if (is_T2(sge->adapter))
1588 del_timer_sync(&sge->espibug_timer); 2077 del_timer_sync(&sge->espibug_timer);
2078
1589 del_timer_sync(&sge->tx_reclaim_timer); 2079 del_timer_sync(&sge->tx_reclaim_timer);
2080 if (sge->tx_sched)
2081 tx_sched_stop(sge);
2082
2083 for (i = 0; i < MAX_NPORTS; i++)
2084 if (sge->espibug_skb[i])
2085 kfree_skb(sge->espibug_skb[i]);
1590} 2086}
1591 2087
1592/* 2088/*
@@ -1599,74 +2095,128 @@ void t1_sge_start(struct sge *sge)
1599 2095
1600 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); 2096 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1601 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); 2097 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1602 (void) readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ 2098 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1603 2099
1604 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 2100 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1605 2101
1606 if (is_T2(sge->adapter)) 2102 if (is_T2(sge->adapter))
1607 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 2103 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1608} 2104}
1609 2105
1610/* 2106/*
1611 * Callback for the T2 ESPI 'stuck packet feature' workaorund 2107 * Callback for the T2 ESPI 'stuck packet feature' workaorund
1612 */ 2108 */
1613static void espibug_workaround(void *data) 2109static void espibug_workaround_t204(unsigned long data)
1614{ 2110{
1615 struct adapter *adapter = (struct adapter *)data; 2111 struct adapter *adapter = (struct adapter *)data;
1616 struct sge *sge = adapter->sge; 2112 struct sge *sge = adapter->sge;
2113 unsigned int nports = adapter->params.nports;
2114 u32 seop[MAX_NPORTS];
1617 2115
1618 if (netif_running(adapter->port[0].dev)) { 2116 if (adapter->open_device_map & PORT_MASK) {
1619 struct sk_buff *skb = sge->espibug_skb; 2117 int i;
1620 2118 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) {
1621 u32 seop = t1_espi_get_mon(adapter, 0x930, 0); 2119 return;
1622 2120 }
1623 if ((seop & 0xfff0fff) == 0xfff && skb) { 2121 for (i = 0; i < nports; i++) {
1624 if (!skb->cb[0]) { 2122 struct sk_buff *skb = sge->espibug_skb[i];
1625 u8 ch_mac_addr[ETH_ALEN] = 2123 if ( (netif_running(adapter->port[i].dev)) &&
1626 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0}; 2124 !(netif_queue_stopped(adapter->port[i].dev)) &&
1627 memcpy(skb->data + sizeof(struct cpl_tx_pkt), 2125 (seop[i] && ((seop[i] & 0xfff) == 0)) &&
1628 ch_mac_addr, ETH_ALEN); 2126 skb ) {
1629 memcpy(skb->data + skb->len - 10, ch_mac_addr, 2127 if (!skb->cb[0]) {
1630 ETH_ALEN); 2128 u8 ch_mac_addr[ETH_ALEN] =
1631 skb->cb[0] = 0xff; 2129 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
2130 memcpy(skb->data + sizeof(struct cpl_tx_pkt),
2131 ch_mac_addr, ETH_ALEN);
2132 memcpy(skb->data + skb->len - 10,
2133 ch_mac_addr, ETH_ALEN);
2134 skb->cb[0] = 0xff;
2135 }
2136
2137 /* bump the reference count to avoid freeing of
2138 * the skb once the DMA has completed.
2139 */
2140 skb = skb_get(skb);
2141 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
1632 } 2142 }
1633
1634 /* bump the reference count to avoid freeing of the
1635 * skb once the DMA has completed.
1636 */
1637 skb = skb_get(skb);
1638 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
1639 } 2143 }
1640 } 2144 }
1641 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 2145 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1642} 2146}
1643 2147
2148static void espibug_workaround(unsigned long data)
2149{
2150 struct adapter *adapter = (struct adapter *)data;
2151 struct sge *sge = adapter->sge;
2152
2153 if (netif_running(adapter->port[0].dev)) {
2154 struct sk_buff *skb = sge->espibug_skb[0];
2155 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2156
2157 if ((seop & 0xfff0fff) == 0xfff && skb) {
2158 if (!skb->cb[0]) {
2159 u8 ch_mac_addr[ETH_ALEN] =
2160 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
2161 memcpy(skb->data + sizeof(struct cpl_tx_pkt),
2162 ch_mac_addr, ETH_ALEN);
2163 memcpy(skb->data + skb->len - 10, ch_mac_addr,
2164 ETH_ALEN);
2165 skb->cb[0] = 0xff;
2166 }
2167
2168 /* bump the reference count to avoid freeing of the
2169 * skb once the DMA has completed.
2170 */
2171 skb = skb_get(skb);
2172 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2173 }
2174 }
2175 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2176}
2177
1644/* 2178/*
1645 * Creates a t1_sge structure and returns suggested resource parameters. 2179 * Creates a t1_sge structure and returns suggested resource parameters.
1646 */ 2180 */
1647struct sge * __devinit t1_sge_create(struct adapter *adapter, 2181struct sge * __devinit t1_sge_create(struct adapter *adapter,
1648 struct sge_params *p) 2182 struct sge_params *p)
1649{ 2183{
1650 struct sge *sge = kmalloc(sizeof(*sge), GFP_KERNEL); 2184 struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2185 int i;
1651 2186
1652 if (!sge) 2187 if (!sge)
1653 return NULL; 2188 return NULL;
1654 memset(sge, 0, sizeof(*sge));
1655 2189
1656 sge->adapter = adapter; 2190 sge->adapter = adapter;
1657 sge->netdev = adapter->port[0].dev; 2191 sge->netdev = adapter->port[0].dev;
1658 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; 2192 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
1659 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; 2193 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
1660 2194
2195 for_each_port(adapter, i) {
2196 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2197 if (!sge->port_stats[i])
2198 goto nomem_port;
2199 }
2200
1661 init_timer(&sge->tx_reclaim_timer); 2201 init_timer(&sge->tx_reclaim_timer);
1662 sge->tx_reclaim_timer.data = (unsigned long)sge; 2202 sge->tx_reclaim_timer.data = (unsigned long)sge;
1663 sge->tx_reclaim_timer.function = sge_tx_reclaim_cb; 2203 sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
1664 2204
1665 if (is_T2(sge->adapter)) { 2205 if (is_T2(sge->adapter)) {
1666 init_timer(&sge->espibug_timer); 2206 init_timer(&sge->espibug_timer);
1667 sge->espibug_timer.function = (void *)&espibug_workaround; 2207
2208 if (adapter->params.nports > 1) {
2209 tx_sched_init(sge);
2210 sge->espibug_timer.function = espibug_workaround_t204;
2211 } else {
2212 sge->espibug_timer.function = espibug_workaround;
2213 }
1668 sge->espibug_timer.data = (unsigned long)sge->adapter; 2214 sge->espibug_timer.data = (unsigned long)sge->adapter;
2215
1669 sge->espibug_timeout = 1; 2216 sge->espibug_timeout = 1;
2217 /* for T204, every 10ms */
2218 if (adapter->params.nports > 1)
2219 sge->espibug_timeout = HZ/100;
1670 } 2220 }
1671 2221
1672 2222
@@ -1674,10 +2224,25 @@ struct sge * __devinit t1_sge_create(struct adapter *adapter,
1674 p->cmdQ_size[1] = SGE_CMDQ1_E_N; 2224 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
1675 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; 2225 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
1676 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; 2226 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
1677 p->rx_coalesce_usecs = 50; 2227 if (sge->tx_sched) {
2228 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2229 p->rx_coalesce_usecs = 15;
2230 else
2231 p->rx_coalesce_usecs = 50;
2232 } else
2233 p->rx_coalesce_usecs = 50;
2234
1678 p->coalesce_enable = 0; 2235 p->coalesce_enable = 0;
1679 p->sample_interval_usecs = 0; 2236 p->sample_interval_usecs = 0;
1680 p->polling = 0; 2237 p->polling = 0;
1681 2238
1682 return sge; 2239 return sge;
2240nomem_port:
2241 while (i >= 0) {
2242 free_percpu(sge->port_stats[i]);
2243 --i;
2244 }
2245 kfree(sge);
2246 return NULL;
2247
1683} 2248}
diff --git a/drivers/net/chelsio/sge.h b/drivers/net/chelsio/sge.h
index 91af47bab7be..7ceb0117d039 100644
--- a/drivers/net/chelsio/sge.h
+++ b/drivers/net/chelsio/sge.h
@@ -44,6 +44,9 @@
44#include <asm/byteorder.h> 44#include <asm/byteorder.h>
45 45
46struct sge_intr_counts { 46struct sge_intr_counts {
47 unsigned int rx_drops; /* # of packets dropped due to no mem */
48 unsigned int pure_rsps; /* # of non-payload responses */
49 unsigned int unhandled_irqs; /* # of unhandled interrupts */
47 unsigned int respQ_empty; /* # times respQ empty */ 50 unsigned int respQ_empty; /* # times respQ empty */
48 unsigned int respQ_overflow; /* # respQ overflow (fatal) */ 51 unsigned int respQ_overflow; /* # respQ overflow (fatal) */
49 unsigned int freelistQ_empty; /* # times freelist empty */ 52 unsigned int freelistQ_empty; /* # times freelist empty */
@@ -51,24 +54,16 @@ struct sge_intr_counts {
51 unsigned int pkt_mismatch; 54 unsigned int pkt_mismatch;
52 unsigned int cmdQ_full[3]; /* not HW IRQ, host cmdQ[] full */ 55 unsigned int cmdQ_full[3]; /* not HW IRQ, host cmdQ[] full */
53 unsigned int cmdQ_restarted[3];/* # of times cmdQ X was restarted */ 56 unsigned int cmdQ_restarted[3];/* # of times cmdQ X was restarted */
54 unsigned int ethernet_pkts; /* # of Ethernet packets received */
55 unsigned int offload_pkts; /* # of offload packets received */
56 unsigned int offload_bundles; /* # of offload pkt bundles delivered */
57 unsigned int pure_rsps; /* # of non-payload responses */
58 unsigned int unhandled_irqs; /* # of unhandled interrupts */
59 unsigned int tx_ipfrags;
60 unsigned int tx_reg_pkts;
61 unsigned int tx_lso_pkts;
62 unsigned int tx_do_cksum;
63}; 57};
64 58
65struct sge_port_stats { 59struct sge_port_stats {
66 unsigned long rx_cso_good; /* # of successful RX csum offloads */ 60 u64 rx_packets; /* # of Ethernet packets received */
67 unsigned long tx_cso; /* # of TX checksum offloads */ 61 u64 rx_cso_good; /* # of successful RX csum offloads */
68 unsigned long vlan_xtract; /* # of VLAN tag extractions */ 62 u64 tx_packets; /* # of TX packets */
69 unsigned long vlan_insert; /* # of VLAN tag extractions */ 63 u64 tx_cso; /* # of TX checksum offloads */
70 unsigned long tso; /* # of TSO requests */ 64 u64 tx_tso; /* # of TSO requests */
71 unsigned long rx_drops; /* # of packets dropped due to no mem */ 65 u64 vlan_xtract; /* # of VLAN tag extractions */
66 u64 vlan_insert; /* # of VLAN tag insertions */
72}; 67};
73 68
74struct sk_buff; 69struct sk_buff;
@@ -90,7 +85,11 @@ int t1_sge_intr_error_handler(struct sge *);
90void t1_sge_intr_enable(struct sge *); 85void t1_sge_intr_enable(struct sge *);
91void t1_sge_intr_disable(struct sge *); 86void t1_sge_intr_disable(struct sge *);
92void t1_sge_intr_clear(struct sge *); 87void t1_sge_intr_clear(struct sge *);
93const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge); 88const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge);
94const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port); 89void t1_sge_get_port_stats(const struct sge *sge, int port, struct sge_port_stats *);
90void t1_sched_set_max_avail_bytes(struct sge *, unsigned int);
91void t1_sched_set_drain_bits_per_us(struct sge *, unsigned int, unsigned int);
92unsigned int t1_sched_update_parms(struct sge *, unsigned int, unsigned int,
93 unsigned int);
95 94
96#endif /* _CXGB_SGE_H_ */ 95#endif /* _CXGB_SGE_H_ */
diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c
index 12e4e96dba2d..22ed9a383c08 100644
--- a/drivers/net/chelsio/subr.c
+++ b/drivers/net/chelsio/subr.c
@@ -43,6 +43,7 @@
43#include "gmac.h" 43#include "gmac.h"
44#include "cphy.h" 44#include "cphy.h"
45#include "sge.h" 45#include "sge.h"
46#include "tp.h"
46#include "espi.h" 47#include "espi.h"
47 48
48/** 49/**
@@ -59,7 +60,7 @@
59 * otherwise. 60 * otherwise.
60 */ 61 */
61static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, 62static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
62 int attempts, int delay) 63 int attempts, int delay)
63{ 64{
64 while (1) { 65 while (1) {
65 u32 val = readl(adapter->regs + reg) & mask; 66 u32 val = readl(adapter->regs + reg) & mask;
@@ -78,7 +79,7 @@ static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
78/* 79/*
79 * Write a register over the TPI interface (unlocked and locked versions). 80 * Write a register over the TPI interface (unlocked and locked versions).
80 */ 81 */
81static int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) 82int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
82{ 83{
83 int tpi_busy; 84 int tpi_busy;
84 85
@@ -98,16 +99,16 @@ int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
98{ 99{
99 int ret; 100 int ret;
100 101
101 spin_lock(&(adapter)->tpi_lock); 102 spin_lock(&adapter->tpi_lock);
102 ret = __t1_tpi_write(adapter, addr, value); 103 ret = __t1_tpi_write(adapter, addr, value);
103 spin_unlock(&(adapter)->tpi_lock); 104 spin_unlock(&adapter->tpi_lock);
104 return ret; 105 return ret;
105} 106}
106 107
107/* 108/*
108 * Read a register over the TPI interface (unlocked and locked versions). 109 * Read a register over the TPI interface (unlocked and locked versions).
109 */ 110 */
110static int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp) 111int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
111{ 112{
112 int tpi_busy; 113 int tpi_busy;
113 114
@@ -128,18 +129,26 @@ int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
128{ 129{
129 int ret; 130 int ret;
130 131
131 spin_lock(&(adapter)->tpi_lock); 132 spin_lock(&adapter->tpi_lock);
132 ret = __t1_tpi_read(adapter, addr, valp); 133 ret = __t1_tpi_read(adapter, addr, valp);
133 spin_unlock(&(adapter)->tpi_lock); 134 spin_unlock(&adapter->tpi_lock);
134 return ret; 135 return ret;
135} 136}
136 137
137/* 138/*
139 * Set a TPI parameter.
140 */
141static void t1_tpi_par(adapter_t *adapter, u32 value)
142{
143 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144}
145
146/*
138 * Called when a port's link settings change to propagate the new values to the 147 * Called when a port's link settings change to propagate the new values to the
139 * associated PHY and MAC. After performing the common tasks it invokes an 148 * associated PHY and MAC. After performing the common tasks it invokes an
140 * OS-specific handler. 149 * OS-specific handler.
141 */ 150 */
142/* static */ void link_changed(adapter_t *adapter, int port_id) 151void t1_link_changed(adapter_t *adapter, int port_id)
143{ 152{
144 int link_ok, speed, duplex, fc; 153 int link_ok, speed, duplex, fc;
145 struct cphy *phy = adapter->port[port_id].phy; 154 struct cphy *phy = adapter->port[port_id].phy;
@@ -159,23 +168,83 @@ int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
159 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc); 168 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
160 lc->fc = (unsigned char)fc; 169 lc->fc = (unsigned char)fc;
161 } 170 }
162 t1_link_changed(adapter, port_id, link_ok, speed, duplex, fc); 171 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
163} 172}
164 173
165static int t1_pci_intr_handler(adapter_t *adapter) 174static int t1_pci_intr_handler(adapter_t *adapter)
166{ 175{
167 u32 pcix_cause; 176 u32 pcix_cause;
168 177
169 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause); 178 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
170 179
171 if (pcix_cause) { 180 if (pcix_cause) {
172 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 181 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
173 pcix_cause); 182 pcix_cause);
174 t1_fatal_err(adapter); /* PCI errors are fatal */ 183 t1_fatal_err(adapter); /* PCI errors are fatal */
175 } 184 }
176 return 0; 185 return 0;
177} 186}
178 187
188#ifdef CONFIG_CHELSIO_T1_COUGAR
189#include "cspi.h"
190#endif
191#ifdef CONFIG_CHELSIO_T1_1G
192#include "fpga_defs.h"
193
194/*
195 * PHY interrupt handler for FPGA boards.
196 */
197static int fpga_phy_intr_handler(adapter_t *adapter)
198{
199 int p;
200 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
201
202 for_each_port(adapter, p)
203 if (cause & (1 << p)) {
204 struct cphy *phy = adapter->port[p].phy;
205 int phy_cause = phy->ops->interrupt_handler(phy);
206
207 if (phy_cause & cphy_cause_link_change)
208 t1_link_changed(adapter, p);
209 }
210 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
211 return 0;
212}
213
214/*
215 * Slow path interrupt handler for FPGAs.
216 */
217static int fpga_slow_intr(adapter_t *adapter)
218{
219 u32 cause = readl(adapter->regs + A_PL_CAUSE);
220
221 cause &= ~F_PL_INTR_SGE_DATA;
222 if (cause & F_PL_INTR_SGE_ERR)
223 t1_sge_intr_error_handler(adapter->sge);
224
225 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
226 fpga_phy_intr_handler(adapter);
227
228 if (cause & FPGA_PCIX_INTERRUPT_TP) {
229 /*
230 * FPGA doesn't support MC4 interrupts and it requires
231 * this odd layer of indirection for MC5.
232 */
233 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234
235 /* Clear TP interrupt */
236 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
237 }
238 if (cause & FPGA_PCIX_INTERRUPT_PCIX)
239 t1_pci_intr_handler(adapter);
240
241 /* Clear the interrupts just processed. */
242 if (cause)
243 writel(cause, adapter->regs + A_PL_CAUSE);
244
245 return cause != 0;
246}
247#endif
179 248
180/* 249/*
181 * Wait until Elmer's MI1 interface is ready for new operations. 250 * Wait until Elmer's MI1 interface is ready for new operations.
@@ -212,12 +281,62 @@ static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
212 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val); 281 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
213} 282}
214 283
284#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
285/*
286 * Elmer MI1 MDIO read/write operations.
287 */
288static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
289 int reg_addr, unsigned int *valp)
290{
291 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
292
293 if (mmd_addr)
294 return -EINVAL;
295
296 spin_lock(&adapter->tpi_lock);
297 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
298 __t1_tpi_write(adapter,
299 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
300 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
301 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
302 spin_unlock(&adapter->tpi_lock);
303 return 0;
304}
305
306static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
307 int reg_addr, unsigned int val)
308{
309 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
310
311 if (mmd_addr)
312 return -EINVAL;
313
314 spin_lock(&adapter->tpi_lock);
315 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
316 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
317 __t1_tpi_write(adapter,
318 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
319 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
320 spin_unlock(&adapter->tpi_lock);
321 return 0;
322}
323
324#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
325static struct mdio_ops mi1_mdio_ops = {
326 mi1_mdio_init,
327 mi1_mdio_read,
328 mi1_mdio_write
329};
330#endif
331
332#endif
333
215static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, 334static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
216 int reg_addr, unsigned int *valp) 335 int reg_addr, unsigned int *valp)
217{ 336{
218 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); 337 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
219 338
220 spin_lock(&(adapter)->tpi_lock); 339 spin_lock(&adapter->tpi_lock);
221 340
222 /* Write the address we want. */ 341 /* Write the address we want. */
223 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); 342 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
@@ -227,12 +346,13 @@ static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
227 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 346 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
228 347
229 /* Write the operation we want. */ 348 /* Write the operation we want. */
230 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ); 349 __t1_tpi_write(adapter,
350 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
231 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 351 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
232 352
233 /* Read the data. */ 353 /* Read the data. */
234 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp); 354 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
235 spin_unlock(&(adapter)->tpi_lock); 355 spin_unlock(&adapter->tpi_lock);
236 return 0; 356 return 0;
237} 357}
238 358
@@ -241,7 +361,7 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
241{ 361{
242 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); 362 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
243 363
244 spin_lock(&(adapter)->tpi_lock); 364 spin_lock(&adapter->tpi_lock);
245 365
246 /* Write the address we want. */ 366 /* Write the address we want. */
247 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); 367 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
@@ -254,7 +374,7 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
254 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); 374 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
255 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE); 375 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
256 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 376 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
257 spin_unlock(&(adapter)->tpi_lock); 377 spin_unlock(&adapter->tpi_lock);
258 return 0; 378 return 0;
259} 379}
260 380
@@ -265,12 +385,25 @@ static struct mdio_ops mi1_mdio_ext_ops = {
265}; 385};
266 386
267enum { 387enum {
388 CH_BRD_T110_1CU,
268 CH_BRD_N110_1F, 389 CH_BRD_N110_1F,
269 CH_BRD_N210_1F, 390 CH_BRD_N210_1F,
391 CH_BRD_T210_1F,
392 CH_BRD_T210_1CU,
393 CH_BRD_N204_4CU,
270}; 394};
271 395
272static struct board_info t1_board[] = { 396static struct board_info t1_board[] = {
273 397
398{ CHBT_BOARD_CHT110, 1/*ports#*/,
399 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
400 CHBT_MAC_PM3393, CHBT_PHY_MY3126,
401 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
402 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
403 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
404 &t1_my3126_ops, &mi1_mdio_ext_ops,
405 "Chelsio T110 1x10GBase-CX4 TOE" },
406
274{ CHBT_BOARD_N110, 1/*ports#*/, 407{ CHBT_BOARD_N110, 1/*ports#*/,
275 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1, 408 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
276 CHBT_MAC_PM3393, CHBT_PHY_88X2010, 409 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
@@ -289,12 +422,47 @@ static struct board_info t1_board[] = {
289 &t1_mv88x201x_ops, &mi1_mdio_ext_ops, 422 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
290 "Chelsio N210 1x10GBaseX NIC" }, 423 "Chelsio N210 1x10GBaseX NIC" },
291 424
425{ CHBT_BOARD_CHT210, 1/*ports#*/,
426 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
427 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
428 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
429 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
430 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
431 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
432 "Chelsio T210 1x10GBaseX TOE" },
433
434{ CHBT_BOARD_CHT210, 1/*ports#*/,
435 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
436 CHBT_MAC_PM3393, CHBT_PHY_MY3126,
437 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
438 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
439 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
440 &t1_my3126_ops, &mi1_mdio_ext_ops,
441 "Chelsio T210 1x10GBase-CX4 TOE" },
442
443#ifdef CONFIG_CHELSIO_T1_1G
444{ CHBT_BOARD_CHN204, 4/*ports#*/,
445 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
446 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
447 SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111,
448 100000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
449 4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
450 0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops,
451 &t1_mv88e1xxx_ops, &mi1_mdio_ops,
452 "Chelsio N204 4x100/1000BaseT NIC" },
453#endif
454
292}; 455};
293 456
294struct pci_device_id t1_pci_tbl[] = { 457struct pci_device_id t1_pci_tbl[] = {
458 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
459 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
295 CH_DEVICE(7, 0, CH_BRD_N110_1F), 460 CH_DEVICE(7, 0, CH_BRD_N110_1F),
296 CH_DEVICE(10, 1, CH_BRD_N210_1F), 461 CH_DEVICE(10, 1, CH_BRD_N210_1F),
297 { 0, } 462 CH_DEVICE(11, 1, CH_BRD_T210_1F),
463 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
464 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
465 { 0 }
298}; 466};
299 467
300MODULE_DEVICE_TABLE(pci, t1_pci_tbl); 468MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
@@ -390,9 +558,14 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
390 if (lc->supported & SUPPORTED_Autoneg) { 558 if (lc->supported & SUPPORTED_Autoneg) {
391 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE); 559 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
392 if (fc) { 560 if (fc) {
393 lc->advertising |= ADVERTISED_ASYM_PAUSE; 561 if (fc == ((PAUSE_RX | PAUSE_TX) &
394 if (fc == (PAUSE_RX | PAUSE_TX)) 562 (mac->adapter->params.nports < 2)))
395 lc->advertising |= ADVERTISED_PAUSE; 563 lc->advertising |= ADVERTISED_PAUSE;
564 else {
565 lc->advertising |= ADVERTISED_ASYM_PAUSE;
566 if (fc == PAUSE_RX)
567 lc->advertising |= ADVERTISED_PAUSE;
568 }
396 } 569 }
397 phy->ops->advertise(phy, lc->advertising); 570 phy->ops->advertise(phy, lc->advertising);
398 571
@@ -403,11 +576,15 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
403 mac->ops->set_speed_duplex_fc(mac, lc->speed, 576 mac->ops->set_speed_duplex_fc(mac, lc->speed,
404 lc->duplex, fc); 577 lc->duplex, fc);
405 /* Also disables autoneg */ 578 /* Also disables autoneg */
579 phy->state = PHY_AUTONEG_RDY;
406 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); 580 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
407 phy->ops->reset(phy, 0); 581 phy->ops->reset(phy, 0);
408 } else 582 } else {
583 phy->state = PHY_AUTONEG_EN;
409 phy->ops->autoneg_enable(phy); /* also resets PHY */ 584 phy->ops->autoneg_enable(phy); /* also resets PHY */
585 }
410 } else { 586 } else {
587 phy->state = PHY_AUTONEG_RDY;
411 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc); 588 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
412 lc->fc = (unsigned char)fc; 589 lc->fc = (unsigned char)fc;
413 phy->ops->reset(phy, 0); 590 phy->ops->reset(phy, 0);
@@ -418,24 +595,109 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
418/* 595/*
419 * External interrupt handler for boards using elmer0. 596 * External interrupt handler for boards using elmer0.
420 */ 597 */
421int elmer0_ext_intr_handler(adapter_t *adapter) 598int t1_elmer0_ext_intr_handler(adapter_t *adapter)
422{ 599{
423 struct cphy *phy; 600 struct cphy *phy;
424 int phy_cause; 601 int phy_cause;
425 u32 cause; 602 u32 cause;
426 603
427 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause); 604 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
428 605
429 switch (board_info(adapter)->board) { 606 switch (board_info(adapter)->board) {
607#ifdef CONFIG_CHELSIO_T1_1G
608 case CHBT_BOARD_CHT204:
609 case CHBT_BOARD_CHT204E:
610 case CHBT_BOARD_CHN204:
611 case CHBT_BOARD_CHT204V: {
612 int i, port_bit;
613 for_each_port(adapter, i) {
614 port_bit = i + 1;
615 if (!(cause & (1 << port_bit))) continue;
616
617 phy = adapter->port[i].phy;
618 phy_cause = phy->ops->interrupt_handler(phy);
619 if (phy_cause & cphy_cause_link_change)
620 t1_link_changed(adapter, i);
621 }
622 break;
623 }
624 case CHBT_BOARD_CHT101:
625 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
626 phy = adapter->port[0].phy;
627 phy_cause = phy->ops->interrupt_handler(phy);
628 if (phy_cause & cphy_cause_link_change)
629 t1_link_changed(adapter, 0);
630 }
631 break;
632 case CHBT_BOARD_7500: {
633 int p;
634 /*
635 * Elmer0's interrupt cause isn't useful here because there is
636 * only one bit that can be set for all 4 ports. This means
637 * we are forced to check every PHY's interrupt status
638 * register to see who initiated the interrupt.
639 */
640 for_each_port(adapter, p) {
641 phy = adapter->port[p].phy;
642 phy_cause = phy->ops->interrupt_handler(phy);
643 if (phy_cause & cphy_cause_link_change)
644 t1_link_changed(adapter, p);
645 }
646 break;
647 }
648#endif
649 case CHBT_BOARD_CHT210:
430 case CHBT_BOARD_N210: 650 case CHBT_BOARD_N210:
431 case CHBT_BOARD_N110: 651 case CHBT_BOARD_N110:
432 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */ 652 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
433 phy = adapter->port[0].phy; 653 phy = adapter->port[0].phy;
434 phy_cause = phy->ops->interrupt_handler(phy); 654 phy_cause = phy->ops->interrupt_handler(phy);
435 if (phy_cause & cphy_cause_link_change) 655 if (phy_cause & cphy_cause_link_change)
436 link_changed(adapter, 0); 656 t1_link_changed(adapter, 0);
657 }
658 break;
659 case CHBT_BOARD_8000:
660 case CHBT_BOARD_CHT110:
661 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
662 cause);
663 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
664 struct cmac *mac = adapter->port[0].mac;
665
666 mac->ops->interrupt_handler(mac);
437 } 667 }
668 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
669 u32 mod_detect;
670
671 t1_tpi_read(adapter,
672 A_ELMER0_GPI_STAT, &mod_detect);
673 CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
674 mod_detect ? "removed" : "inserted");
675 }
438 break; 676 break;
677#ifdef CONFIG_CHELSIO_T1_COUGAR
678 case CHBT_BOARD_COUGAR:
679 if (adapter->params.nports == 1) {
680 if (cause & ELMER0_GP_BIT1) { /* Vitesse MAC */
681 struct cmac *mac = adapter->port[0].mac;
682 mac->ops->interrupt_handler(mac);
683 }
684 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
685 }
686 } else {
687 int i, port_bit;
688
689 for_each_port(adapter, i) {
690 port_bit = i ? i + 1 : 0;
691 if (!(cause & (1 << port_bit))) continue;
692
693 phy = adapter->port[i].phy;
694 phy_cause = phy->ops->interrupt_handler(phy);
695 if (phy_cause & cphy_cause_link_change)
696 t1_link_changed(adapter, i);
697 }
698 }
699 break;
700#endif
439 } 701 }
440 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause); 702 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
441 return 0; 703 return 0;
@@ -445,11 +707,11 @@ int elmer0_ext_intr_handler(adapter_t *adapter)
445void t1_interrupts_enable(adapter_t *adapter) 707void t1_interrupts_enable(adapter_t *adapter)
446{ 708{
447 unsigned int i; 709 unsigned int i;
448 u32 pl_intr;
449 710
450 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR; 711 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
451 712
452 t1_sge_intr_enable(adapter->sge); 713 t1_sge_intr_enable(adapter->sge);
714 t1_tp_intr_enable(adapter->tp);
453 if (adapter->espi) { 715 if (adapter->espi) {
454 adapter->slow_intr_mask |= F_PL_INTR_ESPI; 716 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
455 t1_espi_intr_enable(adapter->espi); 717 t1_espi_intr_enable(adapter->espi);
@@ -462,15 +724,17 @@ void t1_interrupts_enable(adapter_t *adapter)
462 } 724 }
463 725
464 /* Enable PCIX & external chip interrupts on ASIC boards. */ 726 /* Enable PCIX & external chip interrupts on ASIC boards. */
465 pl_intr = readl(adapter->regs + A_PL_ENABLE); 727 if (t1_is_asic(adapter)) {
728 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
466 729
467 /* PCI-X interrupts */ 730 /* PCI-X interrupts */
468 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 731 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
469 0xffffffff); 732 0xffffffff);
470 733
471 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX; 734 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
472 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX; 735 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
473 writel(pl_intr, adapter->regs + A_PL_ENABLE); 736 writel(pl_intr, adapter->regs + A_PL_ENABLE);
737 }
474} 738}
475 739
476/* Disables all interrupts. */ 740/* Disables all interrupts. */
@@ -479,6 +743,7 @@ void t1_interrupts_disable(adapter_t* adapter)
479 unsigned int i; 743 unsigned int i;
480 744
481 t1_sge_intr_disable(adapter->sge); 745 t1_sge_intr_disable(adapter->sge);
746 t1_tp_intr_disable(adapter->tp);
482 if (adapter->espi) 747 if (adapter->espi)
483 t1_espi_intr_disable(adapter->espi); 748 t1_espi_intr_disable(adapter->espi);
484 749
@@ -489,7 +754,8 @@ void t1_interrupts_disable(adapter_t* adapter)
489 } 754 }
490 755
491 /* Disable PCIX & external chip interrupts. */ 756 /* Disable PCIX & external chip interrupts. */
492 writel(0, adapter->regs + A_PL_ENABLE); 757 if (t1_is_asic(adapter))
758 writel(0, adapter->regs + A_PL_ENABLE);
493 759
494 /* PCI-X interrupts */ 760 /* PCI-X interrupts */
495 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0); 761 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
@@ -501,10 +767,9 @@ void t1_interrupts_disable(adapter_t* adapter)
501void t1_interrupts_clear(adapter_t* adapter) 767void t1_interrupts_clear(adapter_t* adapter)
502{ 768{
503 unsigned int i; 769 unsigned int i;
504 u32 pl_intr;
505
506 770
507 t1_sge_intr_clear(adapter->sge); 771 t1_sge_intr_clear(adapter->sge);
772 t1_tp_intr_clear(adapter->tp);
508 if (adapter->espi) 773 if (adapter->espi)
509 t1_espi_intr_clear(adapter->espi); 774 t1_espi_intr_clear(adapter->espi);
510 775
@@ -515,10 +780,12 @@ void t1_interrupts_clear(adapter_t* adapter)
515 } 780 }
516 781
517 /* Enable interrupts for external devices. */ 782 /* Enable interrupts for external devices. */
518 pl_intr = readl(adapter->regs + A_PL_CAUSE); 783 if (t1_is_asic(adapter)) {
784 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
519 785
520 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX, 786 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
521 adapter->regs + A_PL_CAUSE); 787 adapter->regs + A_PL_CAUSE);
788 }
522 789
523 /* PCI-X interrupts */ 790 /* PCI-X interrupts */
524 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff); 791 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
@@ -527,7 +794,7 @@ void t1_interrupts_clear(adapter_t* adapter)
527/* 794/*
528 * Slow path interrupt handler for ASICs. 795 * Slow path interrupt handler for ASICs.
529 */ 796 */
530int t1_slow_intr_handler(adapter_t *adapter) 797static int asic_slow_intr(adapter_t *adapter)
531{ 798{
532 u32 cause = readl(adapter->regs + A_PL_CAUSE); 799 u32 cause = readl(adapter->regs + A_PL_CAUSE);
533 800
@@ -536,89 +803,54 @@ int t1_slow_intr_handler(adapter_t *adapter)
536 return 0; 803 return 0;
537 if (cause & F_PL_INTR_SGE_ERR) 804 if (cause & F_PL_INTR_SGE_ERR)
538 t1_sge_intr_error_handler(adapter->sge); 805 t1_sge_intr_error_handler(adapter->sge);
806 if (cause & F_PL_INTR_TP)
807 t1_tp_intr_handler(adapter->tp);
539 if (cause & F_PL_INTR_ESPI) 808 if (cause & F_PL_INTR_ESPI)
540 t1_espi_intr_handler(adapter->espi); 809 t1_espi_intr_handler(adapter->espi);
541 if (cause & F_PL_INTR_PCIX) 810 if (cause & F_PL_INTR_PCIX)
542 t1_pci_intr_handler(adapter); 811 t1_pci_intr_handler(adapter);
543 if (cause & F_PL_INTR_EXT) 812 if (cause & F_PL_INTR_EXT)
544 t1_elmer0_ext_intr(adapter); 813 t1_elmer0_ext_intr_handler(adapter);
545 814
546 /* Clear the interrupts just processed. */ 815 /* Clear the interrupts just processed. */
547 writel(cause, adapter->regs + A_PL_CAUSE); 816 writel(cause, adapter->regs + A_PL_CAUSE);
548 (void)readl(adapter->regs + A_PL_CAUSE); /* flush writes */ 817 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
549 return 1; 818 return 1;
550} 819}
551 820
552/* Pause deadlock avoidance parameters */ 821int t1_slow_intr_handler(adapter_t *adapter)
553#define DROP_MSEC 16
554#define DROP_PKTS_CNT 1
555
556static void set_csum_offload(adapter_t *adapter, u32 csum_bit, int enable)
557{
558 u32 val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
559
560 if (enable)
561 val |= csum_bit;
562 else
563 val &= ~csum_bit;
564 writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
565}
566
567void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable)
568{
569 set_csum_offload(adapter, F_IP_CSUM, enable);
570}
571
572void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable)
573{
574 set_csum_offload(adapter, F_UDP_CSUM, enable);
575}
576
577void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable)
578{ 822{
579 set_csum_offload(adapter, F_TCP_CSUM, enable); 823#ifdef CONFIG_CHELSIO_T1_1G
824 if (!t1_is_asic(adapter))
825 return fpga_slow_intr(adapter);
826#endif
827 return asic_slow_intr(adapter);
580} 828}
581 829
582static void t1_tp_reset(adapter_t *adapter, unsigned int tp_clk) 830/* Power sequencing is a work-around for Intel's XPAKs. */
831static void power_sequence_xpak(adapter_t* adapter)
583{ 832{
584 u32 val; 833 u32 mod_detect;
585 834 u32 gpo;
586 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM | 835
587 F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET; 836 /* Check for XPAK */
588 val |= F_TP_IN_ESPI_CHECK_IP_CSUM | 837 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
589 F_TP_IN_ESPI_CHECK_TCP_CSUM; 838 if (!(ELMER0_GP_BIT5 & mod_detect)) {
590 writel(val, adapter->regs + A_TP_IN_CONFIG); 839 /* XPAK is present */
591 writel(F_TP_OUT_CSPI_CPL | 840 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
592 F_TP_OUT_ESPI_ETHERNET | 841 gpo |= ELMER0_GP_BIT18;
593 F_TP_OUT_ESPI_GENERATE_IP_CSUM | 842 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
594 F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
595 adapter->regs + A_TP_OUT_CONFIG);
596
597 val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
598 val &= ~(F_IP_CSUM | F_UDP_CSUM | F_TCP_CSUM);
599 writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
600
601 /*
602 * Enable pause frame deadlock prevention.
603 */
604 if (is_T2(adapter)) {
605 u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
606
607 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
608 V_DROP_TICKS_CNT(drop_ticks) |
609 V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
610 adapter->regs + A_TP_TX_DROP_CONFIG);
611 } 843 }
612
613 writel(F_TP_RESET, adapter->regs + A_TP_RESET);
614} 844}
615 845
616int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi, 846int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
617 struct adapter_params *p) 847 struct adapter_params *p)
618{ 848{
619 p->chip_version = bi->chip_term; 849 p->chip_version = bi->chip_term;
850 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
620 if (p->chip_version == CHBT_TERM_T1 || 851 if (p->chip_version == CHBT_TERM_T1 ||
621 p->chip_version == CHBT_TERM_T2) { 852 p->chip_version == CHBT_TERM_T2 ||
853 p->chip_version == CHBT_TERM_FPGA) {
622 u32 val = readl(adapter->regs + A_TP_PC_CONFIG); 854 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
623 855
624 val = G_TP_PC_REV(val); 856 val = G_TP_PC_REV(val);
@@ -640,11 +872,38 @@ int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
640static int board_init(adapter_t *adapter, const struct board_info *bi) 872static int board_init(adapter_t *adapter, const struct board_info *bi)
641{ 873{
642 switch (bi->board) { 874 switch (bi->board) {
875 case CHBT_BOARD_8000:
643 case CHBT_BOARD_N110: 876 case CHBT_BOARD_N110:
644 case CHBT_BOARD_N210: 877 case CHBT_BOARD_N210:
645 writel(V_TPIPAR(0xf), adapter->regs + A_TPI_PAR); 878 case CHBT_BOARD_CHT210:
879 case CHBT_BOARD_COUGAR:
880 t1_tpi_par(adapter, 0xf);
646 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800); 881 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
647 break; 882 break;
883 case CHBT_BOARD_CHT110:
884 t1_tpi_par(adapter, 0xf);
885 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
886
887 /* TBD XXX Might not need. This fixes a problem
888 * described in the Intel SR XPAK errata.
889 */
890 power_sequence_xpak(adapter);
891 break;
892#ifdef CONFIG_CHELSIO_T1_1G
893 case CHBT_BOARD_CHT204E:
894 /* add config space write here */
895 case CHBT_BOARD_CHT204:
896 case CHBT_BOARD_CHT204V:
897 case CHBT_BOARD_CHN204:
898 t1_tpi_par(adapter, 0xf);
899 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
900 break;
901 case CHBT_BOARD_CHT101:
902 case CHBT_BOARD_7500:
903 t1_tpi_par(adapter, 0xf);
904 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
905 break;
906#endif
648 } 907 }
649 return 0; 908 return 0;
650} 909}
@@ -666,11 +925,16 @@ int t1_init_hw_modules(adapter_t *adapter)
666 adapter->regs + A_MC5_CONFIG); 925 adapter->regs + A_MC5_CONFIG);
667 } 926 }
668 927
928#ifdef CONFIG_CHELSIO_T1_COUGAR
929 if (adapter->cspi && t1_cspi_init(adapter->cspi))
930 goto out_err;
931#endif
669 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac, 932 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
670 bi->espi_nports)) 933 bi->espi_nports))
671 goto out_err; 934 goto out_err;
672 935
673 t1_tp_reset(adapter, bi->clock_core); 936 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
937 goto out_err;
674 938
675 err = t1_sge_configure(adapter->sge, &adapter->params.sge); 939 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
676 if (err) 940 if (err)
@@ -714,8 +978,14 @@ void t1_free_sw_modules(adapter_t *adapter)
714 978
715 if (adapter->sge) 979 if (adapter->sge)
716 t1_sge_destroy(adapter->sge); 980 t1_sge_destroy(adapter->sge);
981 if (adapter->tp)
982 t1_tp_destroy(adapter->tp);
717 if (adapter->espi) 983 if (adapter->espi)
718 t1_espi_destroy(adapter->espi); 984 t1_espi_destroy(adapter->espi);
985#ifdef CONFIG_CHELSIO_T1_COUGAR
986 if (adapter->cspi)
987 t1_cspi_destroy(adapter->cspi);
988#endif
719} 989}
720 990
721static void __devinit init_link_config(struct link_config *lc, 991static void __devinit init_link_config(struct link_config *lc,
@@ -735,6 +1005,13 @@ static void __devinit init_link_config(struct link_config *lc,
735 } 1005 }
736} 1006}
737 1007
1008#ifdef CONFIG_CHELSIO_T1_COUGAR
1009 if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
1010 CH_ERR("%s: CSPI initialization failed\n",
1011 adapter->name);
1012 goto error;
1013 }
1014#endif
738 1015
739/* 1016/*
740 * Allocate and initialize the data structures that hold the SW state of 1017 * Allocate and initialize the data structures that hold the SW state of
@@ -762,6 +1039,13 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
762 goto error; 1039 goto error;
763 } 1040 }
764 1041
1042 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1043 if (!adapter->tp) {
1044 CH_ERR("%s: TP initialization failed\n",
1045 adapter->name);
1046 goto error;
1047 }
1048
765 board_init(adapter, bi); 1049 board_init(adapter, bi);
766 bi->mdio_ops->init(adapter, bi); 1050 bi->mdio_ops->init(adapter, bi);
767 if (bi->gphy->reset) 1051 if (bi->gphy->reset)
@@ -793,7 +1077,9 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
793 * Get the port's MAC addresses either from the EEPROM if one 1077 * Get the port's MAC addresses either from the EEPROM if one
794 * exists or the one hardcoded in the MAC. 1078 * exists or the one hardcoded in the MAC.
795 */ 1079 */
796 if (vpd_macaddress_get(adapter, i, hw_addr)) { 1080 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1081 mac->ops->macaddress_get(mac, hw_addr);
1082 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
797 CH_ERR("%s: could not read MAC address from VPD ROM\n", 1083 CH_ERR("%s: could not read MAC address from VPD ROM\n",
798 adapter->port[i].dev->name); 1084 adapter->port[i].dev->name);
799 goto error; 1085 goto error;
@@ -806,7 +1092,7 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
806 t1_interrupts_clear(adapter); 1092 t1_interrupts_clear(adapter);
807 return 0; 1093 return 0;
808 1094
809 error: 1095error:
810 t1_free_sw_modules(adapter); 1096 t1_free_sw_modules(adapter);
811 return -1; 1097 return -1;
812} 1098}
diff --git a/drivers/net/chelsio/suni1x10gexp_regs.h b/drivers/net/chelsio/suni1x10gexp_regs.h
index 81816c2b708a..269d097dd927 100644
--- a/drivers/net/chelsio/suni1x10gexp_regs.h
+++ b/drivers/net/chelsio/suni1x10gexp_regs.h
@@ -32,6 +32,30 @@
32#ifndef _CXGB_SUNI1x10GEXP_REGS_H_ 32#ifndef _CXGB_SUNI1x10GEXP_REGS_H_
33#define _CXGB_SUNI1x10GEXP_REGS_H_ 33#define _CXGB_SUNI1x10GEXP_REGS_H_
34 34
35/*
36** Space allocated for each Exact Match Filter
37** There are 8 filter configurations
38*/
39#define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
40
41#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
42
43/*
44** Space allocated for VLAN-Id Filter
45** There are 8 filter configurations
46*/
47#define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
48
49#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
50
51/*
52** Space allocated for each MSTAT Counter
53*/
54#define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
55
56#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
57
58
35/******************************************************************************/ 59/******************************************************************************/
36/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/ 60/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
37/******************************************************************************/ 61/******************************************************************************/
@@ -39,33 +63,125 @@
39/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */ 63/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
40/******************************************************************************/ 64/******************************************************************************/
41 65
66
67#define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
68#define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
69#define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
70#define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
42#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004 71#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
72#define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
73
74#define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
75#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007
76#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008
77#define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009
78#define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A
79#define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B
80
81#define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C
43#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D 82#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
44#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E 83#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
84#define SUNI1x10GEXP_REG_FREE 0x000F
85
86#define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010
87#define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011
88
89#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100
90#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101
45#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102 91#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
92#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103
46#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104 93#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
94#define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107
95
47#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040 96#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
97#define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041
48#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042 98#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
49#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043 99#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
50#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045 100#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
51#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046 101#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
52#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047 102#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
53#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048 103#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
104#define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049
105#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
106#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
107#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
108#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)
109#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A
110#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B
111#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C
54#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D 112#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
55#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E 113#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
56#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F 114#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
115#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050
116#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051
117#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052
118#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053
119#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054
120#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055
121#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056
122#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057
123#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058
124#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059
125#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A
126#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B
127#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C
128#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D
129#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E
130#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F
131#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060
132#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061
133#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062
134#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063
135#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064
136#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065
137#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066
138#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067
139#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068
140#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069
57#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A 141#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
58#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B 142#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
59#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C 143#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
60#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D 144#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
61#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E 145#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
146#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F
62#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070 147#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
148
149#define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081
150#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084
151#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085
152#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086
153#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087
63#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088 154#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
64#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089 155#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
156#define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A
65#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B 157#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
66#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C 158#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
159#define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092
160
161#define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0
162#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1
163#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2
164#define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3
165#define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4
166#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5
67#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7 167#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
68#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8 168#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
169#define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9
170#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA
171#define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB
172#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC
173#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD
174#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE
175#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF
176#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0
177#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1
178#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2
179#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3
180#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4
181#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5
182#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6
183#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7
184
69#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100 185#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
70#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101 186#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
71#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102 187#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
@@ -75,50 +191,321 @@
75#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106 191#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
76#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107 192#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
77#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108 193#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
194#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109
195#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A
196#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B
197#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C
198#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
199#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
200#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
78#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110 201#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
202#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111
203#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112
204#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113
79#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114 205#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
206#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115
207#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116
208#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117
209#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118
210#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119
211#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A
212#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B
213#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C
214#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D
215#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E
216#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F
80#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120 217#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
218#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121
219#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122
220#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123
81#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124 221#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
222#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125
223#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126
224#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127
82#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128 225#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
226#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129
227#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A
228#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B
229#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C
230#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D
231#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E
232#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F
83#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130 233#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
234#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131
235#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132
236#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133
237#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134
238#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135
239#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136
240#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137
84#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138 241#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
242#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139
243#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A
244#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B
85#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C 245#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
246#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D
247#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E
248#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F
86#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140 249#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
250#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141
251#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142
252#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143
87#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144 253#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
254#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145
255#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146
256#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147
257#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148
258#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149
259#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A
260#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B
88#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C 261#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
262#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D
263#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E
264#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F
89#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150 265#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
266#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151
267#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152
268#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153
90#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154 269#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
270#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155
271#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156
272#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157
91#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158 273#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
274#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159
275#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A
276#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B
277#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C
278#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D
279#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E
280#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F
281#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160
282#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161
283#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162
284#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163
285#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164
286#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165
287#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166
288#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167
289#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168
290#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169
291#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A
292#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B
293#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C
294#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D
295#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E
296#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F
297#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170
298#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171
299#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172
300#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173
301#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174
302#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175
303#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176
304#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177
305#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178
306#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179
307#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a
308#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b
309#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c
310#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d
311#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e
312#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f
313#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180
314#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181
315#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182
316#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183
317#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184
318#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185
319#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186
320#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187
321#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188
322#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189
323#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A
324#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B
325#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C
326#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D
327#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E
328#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F
329#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190
330#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191
331#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192
332#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193
92#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194 333#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
334#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195
335#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196
336#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197
337#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198
338#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199
339#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A
340#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B
93#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C 341#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
342#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D
343#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E
344#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F
94#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0 345#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
346#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1
347#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2
348#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3
349#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4
350#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5
351#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6
352#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7
95#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8 353#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
354#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9
355#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA
356#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB
357#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC
358#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD
359#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE
360#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF
96#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0 361#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
362#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1
363#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2
364#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3
365#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4
366#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5
367#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6
368#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7
97#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8 369#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
370#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9
371#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA
372#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB
98#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC 373#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
374#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD
375#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE
376#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF
377#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0
378#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1
379#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2
380#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3
381#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4
382#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5
383#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6
384#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7
385#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8
386#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9
387#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA
388#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB
389#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC
390#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD
391#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE
392#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF
393#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0
394#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1
395#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2
396#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3
397#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4
398#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5
399#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6
400#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7
401#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8
402#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9
403#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA
404#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB
405#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC
406#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD
407#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE
408#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF
409#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0
410#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1
411#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2
412#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3
413#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4
414#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5
415#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6
416#define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51
417
418#define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200
419#define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201
99#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209 420#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
100#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A 421#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
422#define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D
423#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E
424#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F
425#define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210
426#define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211
427
428#define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240
429#define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241
430#define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242
431#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243
432#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244
433#define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245
434
435#define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280
101#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282 436#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
102#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283 437#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
438#define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284
439
103#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300 440#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
104#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301 441#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
105#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302 442#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
443#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303
444#define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304
445#define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305
446
106#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040 447#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
448#define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041
107#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042 449#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
108#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043 450#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
451#define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044
109#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045 452#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045
453#define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046
110#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047 454#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047
111#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048 455#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048
112#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049 456#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049
457#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D
458#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E
459#define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051
460#define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052
461
462#define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080
113#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084 463#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084
114#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085 464#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085
465#define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086
466
467#define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0
468#define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1
469#define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2
470#define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3
471#define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4
472#define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5
115#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6 473#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6
116#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7 474#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7
475#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8
476#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9
477#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA
478#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB
479#define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC
480#define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD
481#define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE
482#define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF
483#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0
484#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1
485#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2
486#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3
487
488
489#define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200
490#define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201
491#define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202
492#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203
493#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204
494#define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205
495#define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206
496#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207
117#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C 497#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C
118#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D 498#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D
499#define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210
500
501#define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280
119#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282 502#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282
120#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283 503#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283
121 504
505
506/*----------------------------------------*/
507#define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480
508
122/******************************************************************************/ 509/******************************************************************************/
123/* -- End register offset definitions -- */ 510/* -- End register offset definitions -- */
124/******************************************************************************/ 511/******************************************************************************/
@@ -127,6 +514,81 @@
127/** SUNI-1x10GE-XP REGISTER BIT MASKS **/ 514/** SUNI-1x10GE-XP REGISTER BIT MASKS **/
128/******************************************************************************/ 515/******************************************************************************/
129 516
517#define SUNI1x10GEXP_BITMSK_BITS_1 0x00001
518#define SUNI1x10GEXP_BITMSK_BITS_2 0x00003
519#define SUNI1x10GEXP_BITMSK_BITS_3 0x00007
520#define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f
521#define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f
522#define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f
523#define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f
524#define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff
525#define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff
526#define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff
527#define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff
528#define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff
529#define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff
530#define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff
531#define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff
532#define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff
533
534#define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
535#define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
536#define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
537#define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
538#define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
539#define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
540#define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
541#define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
542#define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
543#define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
544#define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
545#define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
546#define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
547#define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
548#define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
549
550#define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
551
552
553
554/*----------------------------------------------------------------------------
555 * Register 0x0001: S/UNI-1x10GE-XP Product Revision
556 * Bit 3-0 REVISION
557 *----------------------------------------------------------------------------*/
558#define SUNI1x10GEXP_BITMSK_REVISION 0x000F
559
560/*----------------------------------------------------------------------------
561 * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
562 * Bit 2 XAUI_ARESETB
563 * Bit 1 PL4_ARESETB
564 * Bit 0 DRESETB
565 *----------------------------------------------------------------------------*/
566#define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004
567#define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002
568#define SUNI1x10GEXP_BITMSK_DRESETB 0x0001
569
570/*----------------------------------------------------------------------------
571 * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
572 * Bit 11 PL4IO_OUTCLKSEL
573 * Bit 9 SYSPCSLB
574 * Bit 8 LINEPCSLB
575 * Bit 7 MSTAT_BYPASS
576 * Bit 6 RXXG_BYPASS
577 * Bit 5 TXXG_BYPASS
578 * Bit 4 SOP_PAD_EN
579 * Bit 1 LOS_INV
580 * Bit 0 OVERRIDE_LOS
581 *----------------------------------------------------------------------------*/
582#define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800
583#define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200
584#define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100
585#define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080
586#define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040
587#define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020
588#define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010
589#define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002
590#define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001
591
130/*---------------------------------------------------------------------------- 592/*----------------------------------------------------------------------------
131 * Register 0x0004: S/UNI-1x10GE-XP Device Status 593 * Register 0x0004: S/UNI-1x10GE-XP Device Status
132 * Bit 9 TOP_SXRA_EXPIRED 594 * Bit 9 TOP_SXRA_EXPIRED
@@ -141,7 +603,10 @@
141 * Bit 0 TOP_PL4_OUT_ROOL 603 * Bit 0 TOP_PL4_OUT_ROOL
142 *----------------------------------------------------------------------------*/ 604 *----------------------------------------------------------------------------*/
143#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200 605#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200
606#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100
607#define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080
144#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040 608#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040
609#define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020
145#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010 610#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010
146#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008 611#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008
147#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004 612#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004
@@ -149,12 +614,219 @@
149#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001 614#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001
150 615
151/*---------------------------------------------------------------------------- 616/*----------------------------------------------------------------------------
617 * Register 0x0005: Global Performance Update and Clock Monitors
618 * Bit 15 TIP
619 * Bit 8 XAUI_REF_CLKA
620 * Bit 7 RXLANE3CLKA
621 * Bit 6 RXLANE2CLKA
622 * Bit 5 RXLANE1CLKA
623 * Bit 4 RXLANE0CLKA
624 * Bit 3 CSUCLKA
625 * Bit 2 TDCLKA
626 * Bit 1 RSCLKA
627 * Bit 0 RDCLKA
628 *----------------------------------------------------------------------------*/
629#define SUNI1x10GEXP_BITMSK_TIP 0x8000
630#define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100
631#define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080
632#define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040
633#define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020
634#define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010
635#define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008
636#define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004
637#define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002
638#define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001
639
640/*----------------------------------------------------------------------------
641 * Register 0x0006: MDIO Command
642 * Bit 4 MDIO_RDINC
643 * Bit 3 MDIO_RSTAT
644 * Bit 2 MDIO_LCTLD
645 * Bit 1 MDIO_LCTLA
646 * Bit 0 MDIO_SPRE
647 *----------------------------------------------------------------------------*/
648#define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010
649#define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008
650#define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004
651#define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002
652#define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001
653
654/*----------------------------------------------------------------------------
655 * Register 0x0007: MDIO Interrupt Enable
656 * Bit 0 MDIO_BUSY_EN
657 *----------------------------------------------------------------------------*/
658#define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001
659
660/*----------------------------------------------------------------------------
661 * Register 0x0008: MDIO Interrupt Status
662 * Bit 0 MDIO_BUSYI
663 *----------------------------------------------------------------------------*/
664#define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001
665
666/*----------------------------------------------------------------------------
667 * Register 0x0009: MMD PHY Address
668 * Bit 12-8 MDIO_DEVADR
669 * Bit 4-0 MDIO_PRTADR
670 *----------------------------------------------------------------------------*/
671#define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00
672#define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8
673#define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F
674#define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0
675
676/*----------------------------------------------------------------------------
677 * Register 0x000C: OAM Interface Control
678 * Bit 6 MDO_OD_ENB
679 * Bit 5 MDI_INV
680 * Bit 4 MDI_SEL
681 * Bit 3 RXOAMEN
682 * Bit 2 RXOAMCLKEN
683 * Bit 1 TXOAMEN
684 * Bit 0 TXOAMCLKEN
685 *----------------------------------------------------------------------------*/
686#define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040
687#define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020
688#define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010
689#define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008
690#define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004
691#define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002
692#define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001
693
694/*----------------------------------------------------------------------------
695 * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
696 * Bit 15 TOP_PL4IO_INT
697 * Bit 14 TOP_IRAM_INT
698 * Bit 13 TOP_ERAM_INT
699 * Bit 12 TOP_XAUI_INT
700 * Bit 11 TOP_MSTAT_INT
701 * Bit 10 TOP_RXXG_INT
702 * Bit 9 TOP_TXXG_INT
703 * Bit 8 TOP_XRF_INT
704 * Bit 7 TOP_XTEF_INT
705 * Bit 6 TOP_MDIO_BUSY_INT
706 * Bit 5 TOP_RXOAM_INT
707 * Bit 4 TOP_TXOAM_INT
708 * Bit 3 TOP_IFLX_INT
709 * Bit 2 TOP_EFLX_INT
710 * Bit 1 TOP_PL4ODP_INT
711 * Bit 0 TOP_PL4IDU_INT
712 *----------------------------------------------------------------------------*/
713#define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000
714#define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000
715#define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000
716#define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000
717#define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800
718#define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400
719#define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200
720#define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100
721#define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080
722#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040
723#define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020
724#define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010
725#define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008
726#define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004
727#define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002
728#define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001
729
730/*----------------------------------------------------------------------------
152 * Register 0x000E:PM3393 Global interrupt enable 731 * Register 0x000E:PM3393 Global interrupt enable
153 * Bit 15 TOP_INTE 732 * Bit 15 TOP_INTE
154 *----------------------------------------------------------------------------*/ 733 *----------------------------------------------------------------------------*/
155#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000 734#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000
156 735
157/*---------------------------------------------------------------------------- 736/*----------------------------------------------------------------------------
737 * Register 0x0010: XTEF Miscellaneous Control
738 * Bit 7 RF_VAL
739 * Bit 6 RF_OVERRIDE
740 * Bit 5 LF_VAL
741 * Bit 4 LF_OVERRIDE
742 *----------------------------------------------------------------------------*/
743#define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080
744#define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040
745#define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020
746#define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010
747#define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0
748
749/*----------------------------------------------------------------------------
750 * Register 0x0011: XRF Miscellaneous Control
751 * Bit 6-4 EN_IDLE_REP
752 *----------------------------------------------------------------------------*/
753#define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070
754
755/*----------------------------------------------------------------------------
756 * Register 0x0100: SERDES 3125 Configuration Register 1
757 * Bit 10 RXEQB_3
758 * Bit 8 RXEQB_2
759 * Bit 6 RXEQB_1
760 * Bit 4 RXEQB_0
761 *----------------------------------------------------------------------------*/
762#define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0
763#define SUNI1x10GEXP_BITOFF_RXEQB_3 10
764#define SUNI1x10GEXP_BITOFF_RXEQB_2 8
765#define SUNI1x10GEXP_BITOFF_RXEQB_1 6
766#define SUNI1x10GEXP_BITOFF_RXEQB_0 4
767
768/*----------------------------------------------------------------------------
769 * Register 0x0101: SERDES 3125 Configuration Register 2
770 * Bit 12 YSEL
771 * Bit 7 PRE_EMPH_3
772 * Bit 6 PRE_EMPH_2
773 * Bit 5 PRE_EMPH_1
774 * Bit 4 PRE_EMPH_0
775 *----------------------------------------------------------------------------*/
776#define SUNI1x10GEXP_BITMSK_YSEL 0x1000
777#define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0
778#define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080
779#define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040
780#define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020
781#define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010
782
783/*----------------------------------------------------------------------------
784 * Register 0x0102: SERDES 3125 Interrupt Enable Register
785 * Bit 3 LASIE
786 * Bit 2 SPLL_RAE
787 * Bit 1 MPLL_RAE
788 * Bit 0 PLL_LOCKE
789 *----------------------------------------------------------------------------*/
790#define SUNI1x10GEXP_BITMSK_LASIE 0x0008
791#define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004
792#define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002
793#define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001
794
795/*----------------------------------------------------------------------------
796 * Register 0x0103: SERDES 3125 Interrupt Visibility Register
797 * Bit 3 LASIV
798 * Bit 2 SPLL_RAV
799 * Bit 1 MPLL_RAV
800 * Bit 0 PLL_LOCKV
801 *----------------------------------------------------------------------------*/
802#define SUNI1x10GEXP_BITMSK_LASIV 0x0008
803#define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004
804#define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002
805#define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001
806
807/*----------------------------------------------------------------------------
808 * Register 0x0104: SERDES 3125 Interrupt Status Register
809 * Bit 3 LASII
810 * Bit 2 SPLL_RAI
811 * Bit 1 MPLL_RAI
812 * Bit 0 PLL_LOCKI
813 *----------------------------------------------------------------------------*/
814#define SUNI1x10GEXP_BITMSK_LASII 0x0008
815#define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004
816#define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002
817#define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001
818
819/*----------------------------------------------------------------------------
820 * Register 0x0107: SERDES 3125 Test Configuration
821 * Bit 12 DUALTX
822 * Bit 10 HC_1
823 * Bit 9 HC_0
824 *----------------------------------------------------------------------------*/
825#define SUNI1x10GEXP_BITMSK_DUALTX 0x1000
826#define SUNI1x10GEXP_BITMSK_HC 0x0600
827#define SUNI1x10GEXP_BITOFF_HC_0 9
828
829/*----------------------------------------------------------------------------
158 * Register 0x2040: RXXG Configuration 1 830 * Register 0x2040: RXXG Configuration 1
159 * Bit 15 RXXG_RXEN 831 * Bit 15 RXXG_RXEN
160 * Bit 14 RXXG_ROCF 832 * Bit 14 RXXG_ROCF
@@ -168,11 +840,84 @@
168 * Bit 2-0 RXXG_MIFG 840 * Bit 2-0 RXXG_MIFG
169 *----------------------------------------------------------------------------*/ 841 *----------------------------------------------------------------------------*/
170#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000 842#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000
843#define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000
844#define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000
171#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400 845#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400
846#define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200
847#define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100
172#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080 848#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080
849#define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020
173#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008 850#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008
174 851
175/*---------------------------------------------------------------------------- 852/*----------------------------------------------------------------------------
853 * Register 0x02041: RXXG Configuration 2
854 * Bit 7-0 RXXG_HDRSIZE
855 *----------------------------------------------------------------------------*/
856#define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF
857
858/*----------------------------------------------------------------------------
859 * Register 0x2042: RXXG Configuration 3
860 * Bit 15 RXXG_MIN_LERRE
861 * Bit 14 RXXG_MAX_LERRE
862 * Bit 12 RXXG_LINE_ERRE
863 * Bit 10 RXXG_RX_OVRE
864 * Bit 9 RXXG_ADR_FILTERE
865 * Bit 8 RXXG_ERR_FILTERE
866 * Bit 5 RXXG_PRMB_ERRE
867 *----------------------------------------------------------------------------*/
868#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000
869#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000
870#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000
871#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400
872#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200
873#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100
874#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
875
876/*----------------------------------------------------------------------------
877 * Register 0x2043: RXXG Interrupt
878 * Bit 15 RXXG_MIN_LERRI
879 * Bit 14 RXXG_MAX_LERRI
880 * Bit 12 RXXG_LINE_ERRI
881 * Bit 10 RXXG_RX_OVRI
882 * Bit 9 RXXG_ADR_FILTERI
883 * Bit 8 RXXG_ERR_FILTERI
884 * Bit 5 RXXG_PRMB_ERRE
885 *----------------------------------------------------------------------------*/
886#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000
887#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000
888#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000
889#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400
890#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200
891#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100
892#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
893
894/*----------------------------------------------------------------------------
895 * Register 0x2049: RXXG Receive FIFO Threshold
896 * Bit 2-0 RXXG_CUT_THRU
897 *----------------------------------------------------------------------------*/
898#define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007
899#define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0
900
901/*----------------------------------------------------------------------------
902 * Register 0x2062H - 0x2069: RXXG Exact Match VID
903 * Bit 11-0 RXXG_VID_MATCH
904 *----------------------------------------------------------------------------*/
905#define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF
906#define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0
907
908/*----------------------------------------------------------------------------
909 * Register 0x206EH - 0x206F: RXXG Address Filter Control
910 * Bit 3 RXXG_FORWARD_ENABLE
911 * Bit 2 RXXG_VLAN_ENABLE
912 * Bit 1 RXXG_SRC_ADDR
913 * Bit 0 RXXG_MATCH_ENABLE
914 *----------------------------------------------------------------------------*/
915#define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008
916#define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004
917#define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002
918#define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001
919
920/*----------------------------------------------------------------------------
176 * Register 0x2070: RXXG Address Filter Control 2 921 * Register 0x2070: RXXG Address Filter Control 2
177 * Bit 1 RXXG_PMODE 922 * Bit 1 RXXG_PMODE
178 * Bit 0 RXXG_MHASH_EN 923 * Bit 0 RXXG_MHASH_EN
@@ -181,15 +926,446 @@
181#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001 926#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001
182 927
183/*---------------------------------------------------------------------------- 928/*----------------------------------------------------------------------------
929 * Register 0x2081: XRF Control Register 2
930 * Bit 6 EN_PKT_GEN
931 * Bit 4-2 PATT
932 *----------------------------------------------------------------------------*/
933#define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040
934#define SUNI1x10GEXP_BITMSK_PATT 0x001C
935#define SUNI1x10GEXP_BITOFF_PATT 2
936
937/*----------------------------------------------------------------------------
938 * Register 0x2088: XRF Interrupt Enable
939 * Bit 12-9 LANE_HICERE
940 * Bit 8-5 HS_SD_LANEE
941 * Bit 4 ALIGN_STATUS_ERRE
942 * Bit 3-0 LANE_SYNC_STAT_ERRE
943 *----------------------------------------------------------------------------*/
944#define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00
945#define SUNI1x10GEXP_BITOFF_LANE_HICERE 9
946#define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0
947#define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5
948#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010
949#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F
950#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0
951
952/*----------------------------------------------------------------------------
953 * Register 0x2089: XRF Interrupt Status
954 * Bit 12-9 LANE_HICERI
955 * Bit 8-5 HS_SD_LANEI
956 * Bit 4 ALIGN_STATUS_ERRI
957 * Bit 3-0 LANE_SYNC_STAT_ERRI
958 *----------------------------------------------------------------------------*/
959#define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00
960#define SUNI1x10GEXP_BITOFF_LANE_HICERI 9
961#define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0
962#define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5
963#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010
964#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F
965#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0
966
967/*----------------------------------------------------------------------------
968 * Register 0x208A: XRF Error Status
969 * Bit 8-5 HS_SD_LANE
970 * Bit 4 ALIGN_STATUS_ERR
971 * Bit 3-0 LANE_SYNC_STAT_ERR
972 *----------------------------------------------------------------------------*/
973#define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100
974#define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080
975#define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040
976#define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020
977#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010
978#define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008
979#define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004
980#define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002
981#define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001
982
983/*----------------------------------------------------------------------------
984 * Register 0x208B: XRF Diagnostic Interrupt Enable
985 * Bit 7-4 LANE_OVERRUNE
986 * Bit 3-0 LANE_UNDERRUNE
987 *----------------------------------------------------------------------------*/
988#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0
989#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4
990#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F
991#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0
992
993/*----------------------------------------------------------------------------
994 * Register 0x208C: XRF Diagnostic Interrupt Status
995 * Bit 7-4 LANE_OVERRUNI
996 * Bit 3-0 LANE_UNDERRUNI
997 *----------------------------------------------------------------------------*/
998#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0
999#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4
1000#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F
1001#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0
1002
1003/*----------------------------------------------------------------------------
1004 * Register 0x20C0: RXOAM Configuration
1005 * Bit 15 RXOAM_BUSY
1006 * Bit 14-12 RXOAM_F2_SEL
1007 * Bit 10-8 RXOAM_F1_SEL
1008 * Bit 7-6 RXOAM_FILTER_CTRL
1009 * Bit 5-0 RXOAM_PX_EN
1010 *----------------------------------------------------------------------------*/
1011#define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000
1012#define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000
1013#define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 12
1014#define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700
1015#define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 8
1016#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0
1017#define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 6
1018#define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F
1019#define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0
1020
1021/*----------------------------------------------------------------------------
1022 * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1023 * Bit 15-8 RXOAM_FX_MASK
1024 * Bit 7-0 RXOAM_FX_VAL
1025 *----------------------------------------------------------------------------*/
1026#define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00
1027#define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 8
1028#define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF
1029#define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0
1030
1031/*----------------------------------------------------------------------------
1032 * Register 0x20C3: RXOAM Configuration Register 2
1033 * Bit 13 RXOAM_REC_BYTE_VAL
1034 * Bit 11-10 RXOAM_BYPASS_MODE
1035 * Bit 5-0 RXOAM_PX_CLEAR
1036 *----------------------------------------------------------------------------*/
1037#define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000
1038#define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00
1039#define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 10
1040#define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F
1041#define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0
1042
1043/*----------------------------------------------------------------------------
1044 * Register 0x20C4: RXOAM HEC Configuration
1045 * Bit 15-8 RXOAM_COSET
1046 * Bit 2 RXOAM_HEC_ERR_PKT
1047 * Bit 0 RXOAM_HEC_EN
1048 *----------------------------------------------------------------------------*/
1049#define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00
1050#define SUNI1x10GEXP_BITOFF_RXOAM_COSET 8
1051#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004
1052#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001
1053
1054/*----------------------------------------------------------------------------
1055 * Register 0x20C7: RXOAM Interrupt Enable
1056 * Bit 10 RXOAM_FILTER_THRSHE
1057 * Bit 9 RXOAM_OAM_ERRE
1058 * Bit 8 RXOAM_HECE_THRSHE
1059 * Bit 7 RXOAM_SOPE
1060 * Bit 6 RXOAM_RFE
1061 * Bit 5 RXOAM_LFE
1062 * Bit 4 RXOAM_DV_ERRE
1063 * Bit 3 RXOAM_DATA_INVALIDE
1064 * Bit 2 RXOAM_FILTER_DROPE
1065 * Bit 1 RXOAM_HECE
1066 * Bit 0 RXOAM_OFLE
1067 *----------------------------------------------------------------------------*/
1068#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400
1069#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200
1070#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100
1071#define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080
1072#define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040
1073#define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020
1074#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010
1075#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008
1076#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004
1077#define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002
1078#define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001
1079
1080/*----------------------------------------------------------------------------
1081 * Register 0x20C8: RXOAM Interrupt Status
1082 * Bit 10 RXOAM_FILTER_THRSHI
1083 * Bit 9 RXOAM_OAM_ERRI
1084 * Bit 8 RXOAM_HECE_THRSHI
1085 * Bit 7 RXOAM_SOPI
1086 * Bit 6 RXOAM_RFI
1087 * Bit 5 RXOAM_LFI
1088 * Bit 4 RXOAM_DV_ERRI
1089 * Bit 3 RXOAM_DATA_INVALIDI
1090 * Bit 2 RXOAM_FILTER_DROPI
1091 * Bit 1 RXOAM_HECI
1092 * Bit 0 RXOAM_OFLI
1093 *----------------------------------------------------------------------------*/
1094#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400
1095#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200
1096#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100
1097#define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080
1098#define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040
1099#define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020
1100#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010
1101#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008
1102#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004
1103#define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002
1104#define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001
1105
1106/*----------------------------------------------------------------------------
1107 * Register 0x20C9: RXOAM Status
1108 * Bit 10 RXOAM_FILTER_THRSHV
1109 * Bit 8 RXOAM_HECE_THRSHV
1110 * Bit 6 RXOAM_RFV
1111 * Bit 5 RXOAM_LFV
1112 *----------------------------------------------------------------------------*/
1113#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400
1114#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100
1115#define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040
1116#define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020
1117
1118/*----------------------------------------------------------------------------
184 * Register 0x2100: MSTAT Control 1119 * Register 0x2100: MSTAT Control
185 * Bit 2 MSTAT_WRITE 1120 * Bit 2 MSTAT_WRITE
186 * Bit 1 MSTAT_CLEAR 1121 * Bit 1 MSTAT_CLEAR
187 * Bit 0 MSTAT_SNAP 1122 * Bit 0 MSTAT_SNAP
188 *----------------------------------------------------------------------------*/ 1123 *----------------------------------------------------------------------------*/
1124#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004
189#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002 1125#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002
190#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001 1126#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001
191 1127
192/*---------------------------------------------------------------------------- 1128/*----------------------------------------------------------------------------
1129 * Register 0x2109: MSTAT Counter Write Address
1130 * Bit 5-0 MSTAT_WRITE_ADDRESS
1131 *----------------------------------------------------------------------------*/
1132#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1133#define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1134
1135/*----------------------------------------------------------------------------
1136 * Register 0x2200: IFLX Global Configuration Register
1137 * Bit 15 IFLX_IRCU_ENABLE
1138 * Bit 14 IFLX_IDSWT_ENABLE
1139 * Bit 13-0 IFLX_IFD_CNT
1140 *----------------------------------------------------------------------------*/
1141#define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000
1142#define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000
1143#define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF
1144#define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0
1145
1146/*----------------------------------------------------------------------------
1147 * Register 0x2209: IFLX FIFO Overflow Enable
1148 * Bit 0 IFLX_OVFE
1149 *----------------------------------------------------------------------------*/
1150#define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1151
1152/*----------------------------------------------------------------------------
1153 * Register 0x220A: IFLX FIFO Overflow Interrupt
1154 * Bit 0 IFLX_OVFI
1155 *----------------------------------------------------------------------------*/
1156#define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1157
1158/*----------------------------------------------------------------------------
1159 * Register 0x220D: IFLX Indirect Channel Address
1160 * Bit 15 IFLX_BUSY
1161 * Bit 14 IFLX_RWB
1162 *----------------------------------------------------------------------------*/
1163#define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000
1164#define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000
1165
1166/*----------------------------------------------------------------------------
1167 * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1168 * Bit 9-0 IFLX_LOLIM
1169 *----------------------------------------------------------------------------*/
1170#define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF
1171#define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0
1172
1173/*----------------------------------------------------------------------------
1174 * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1175 * Bit 9-0 IFLX_HILIM
1176 *----------------------------------------------------------------------------*/
1177#define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF
1178#define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0
1179
1180/*----------------------------------------------------------------------------
1181 * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1182 * Bit 15 IFLX_FULL
1183 * Bit 14 IFLX_AFULL
1184 * Bit 13-0 IFLX_AFTH
1185 *----------------------------------------------------------------------------*/
1186#define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000
1187#define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000
1188#define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF
1189#define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0
1190
1191/*----------------------------------------------------------------------------
1192 * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1193 * Bit 15 IFLX_EMPTY
1194 * Bit 14 IFLX_AEMPTY
1195 * Bit 13-0 IFLX_AETH
1196 *----------------------------------------------------------------------------*/
1197#define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000
1198#define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000
1199#define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF
1200#define SUNI1x10GEXP_BITOFF_IFLX_AETH 0
1201
1202/*----------------------------------------------------------------------------
1203 * Register 0x2240: PL4MOS Configuration Register
1204 * Bit 3 PL4MOS_RE_INIT
1205 * Bit 2 PL4MOS_EN
1206 * Bit 1 PL4MOS_NO_STATUS
1207 *----------------------------------------------------------------------------*/
1208#define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008
1209#define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004
1210#define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002
1211
1212/*----------------------------------------------------------------------------
1213 * Register 0x2243: PL4MOS MaxBurst1 Register
1214 * Bit 11-0 PL4MOS_MAX_BURST1
1215 *----------------------------------------------------------------------------*/
1216#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF
1217#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0
1218
1219/*----------------------------------------------------------------------------
1220 * Register 0x2244: PL4MOS MaxBurst2 Register
1221 * Bit 11-0 PL4MOS_MAX_BURST2
1222 *----------------------------------------------------------------------------*/
1223#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF
1224#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0
1225
1226/*----------------------------------------------------------------------------
1227 * Register 0x2245: PL4MOS Transfer Size Register
1228 * Bit 7-0 PL4MOS_MAX_TRANSFER
1229 *----------------------------------------------------------------------------*/
1230#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF
1231#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0
1232
1233/*----------------------------------------------------------------------------
1234 * Register 0x2280: PL4ODP Configuration
1235 * Bit 15-12 PL4ODP_REPEAT_T
1236 * Bit 8 PL4ODP_SOP_RULE
1237 * Bit 1 PL4ODP_EN_PORTS
1238 * Bit 0 PL4ODP_EN_DFWD
1239 *----------------------------------------------------------------------------*/
1240#define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000
1241#define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 12
1242#define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100
1243#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002
1244#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001
1245
1246/*----------------------------------------------------------------------------
1247 * Register 0x2282: PL4ODP Interrupt Mask
1248 * Bit 0 PL4ODP_OUT_DISE
1249 *----------------------------------------------------------------------------*/
1250#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001
1251
1252
1253
1254#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080
1255#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040
1256#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008
1257#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004
1258#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002
1259
1260
1261/*----------------------------------------------------------------------------
1262 * Register 0x2283: PL4ODP Interrupt
1263 * Bit 0 PL4ODP_OUT_DISI
1264 *----------------------------------------------------------------------------*/
1265#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001
1266
1267
1268
1269#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080
1270#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040
1271#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008
1272#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004
1273#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002
1274
1275/*----------------------------------------------------------------------------
1276 * Register 0x2300: PL4IO Lock Detect Status
1277 * Bit 15 PL4IO_OUT_ROOLV
1278 * Bit 12 PL4IO_IS_ROOLV
1279 * Bit 11 PL4IO_DIP2_ERRV
1280 * Bit 8 PL4IO_ID_ROOLV
1281 * Bit 4 PL4IO_IS_DOOLV
1282 * Bit 0 PL4IO_ID_DOOLV
1283 *----------------------------------------------------------------------------*/
1284#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000
1285#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000
1286#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800
1287#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100
1288#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010
1289#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001
1290
1291/*----------------------------------------------------------------------------
1292 * Register 0x2301: PL4IO Lock Detect Change
1293 * Bit 15 PL4IO_OUT_ROOLI
1294 * Bit 12 PL4IO_IS_ROOLI
1295 * Bit 11 PL4IO_DIP2_ERRI
1296 * Bit 8 PL4IO_ID_ROOLI
1297 * Bit 4 PL4IO_IS_DOOLI
1298 * Bit 0 PL4IO_ID_DOOLI
1299 *----------------------------------------------------------------------------*/
1300#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000
1301#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000
1302#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800
1303#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100
1304#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010
1305#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001
1306
1307/*----------------------------------------------------------------------------
1308 * Register 0x2302: PL4IO Lock Detect Mask
1309 * Bit 15 PL4IO_OUT_ROOLE
1310 * Bit 12 PL4IO_IS_ROOLE
1311 * Bit 11 PL4IO_DIP2_ERRE
1312 * Bit 8 PL4IO_ID_ROOLE
1313 * Bit 4 PL4IO_IS_DOOLE
1314 * Bit 0 PL4IO_ID_DOOLE
1315 *----------------------------------------------------------------------------*/
1316#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000
1317#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000
1318#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800
1319#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100
1320#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010
1321#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001
1322
1323/*----------------------------------------------------------------------------
1324 * Register 0x2303: PL4IO Lock Detect Limits
1325 * Bit 15-8 PL4IO_REF_LIMIT
1326 * Bit 7-0 PL4IO_TRAN_LIMIT
1327 *----------------------------------------------------------------------------*/
1328#define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00
1329#define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 8
1330#define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF
1331#define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0
1332
1333/*----------------------------------------------------------------------------
1334 * Register 0x2304: PL4IO Calendar Repetitions
1335 * Bit 15-8 PL4IO_IN_MUL
1336 * Bit 7-0 PL4IO_OUT_MUL
1337 *----------------------------------------------------------------------------*/
1338#define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00
1339#define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 8
1340#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF
1341#define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0
1342
1343/*----------------------------------------------------------------------------
1344 * Register 0x2305: PL4IO Configuration
1345 * Bit 15 PL4IO_DIP2_ERR_CHK
1346 * Bit 11 PL4IO_ODAT_DIS
1347 * Bit 10 PL4IO_TRAIN_DIS
1348 * Bit 9 PL4IO_OSTAT_DIS
1349 * Bit 8 PL4IO_ISTAT_DIS
1350 * Bit 7 PL4IO_NO_ISTAT
1351 * Bit 6 PL4IO_STAT_OUTSEL
1352 * Bit 5 PL4IO_INSEL
1353 * Bit 4 PL4IO_DLSEL
1354 * Bit 1-0 PL4IO_OUTSEL
1355 *----------------------------------------------------------------------------*/
1356#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000
1357#define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800
1358#define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400
1359#define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200
1360#define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100
1361#define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080
1362#define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040
1363#define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020
1364#define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010
1365#define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003
1366#define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0
1367
1368/*----------------------------------------------------------------------------
193 * Register 0x3040: TXXG Configuration Register 1 1369 * Register 0x3040: TXXG Configuration Register 1
194 * Bit 15 TXXG_TXEN0 1370 * Bit 15 TXXG_TXEN0
195 * Bit 13 TXXG_HOSTPAUSE 1371 * Bit 13 TXXG_HOSTPAUSE
@@ -202,12 +1378,266 @@
202 * Bit 0 TXXG_SPRE 1378 * Bit 0 TXXG_SPRE
203 *----------------------------------------------------------------------------*/ 1379 *----------------------------------------------------------------------------*/
204#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000 1380#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000
1381#define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000
1382#define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80
205#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7 1383#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7
206#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020 1384#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020
207#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010 1385#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010
208#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008 1386#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008
209#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004 1387#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004
210#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002 1388#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002
1389#define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001
1390
1391/*----------------------------------------------------------------------------
1392 * Register 0x3041: TXXG Configuration Register 2
1393 * Bit 7-0 TXXG_HDRSIZE
1394 *----------------------------------------------------------------------------*/
1395#define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF
1396
1397/*----------------------------------------------------------------------------
1398 * Register 0x3042: TXXG Configuration Register 3
1399 * Bit 15 TXXG_FIFO_ERRE
1400 * Bit 14 TXXG_FIFO_UDRE
1401 * Bit 13 TXXG_MAX_LERRE
1402 * Bit 12 TXXG_MIN_LERRE
1403 * Bit 11 TXXG_XFERE
1404 *----------------------------------------------------------------------------*/
1405#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000
1406#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000
1407#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000
1408#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000
1409#define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800
1410
1411/*----------------------------------------------------------------------------
1412 * Register 0x3043: TXXG Interrupt
1413 * Bit 15 TXXG_FIFO_ERRI
1414 * Bit 14 TXXG_FIFO_UDRI
1415 * Bit 13 TXXG_MAX_LERRI
1416 * Bit 12 TXXG_MIN_LERRI
1417 * Bit 11 TXXG_XFERI
1418 *----------------------------------------------------------------------------*/
1419#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000
1420#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000
1421#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000
1422#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000
1423#define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800
1424
1425/*----------------------------------------------------------------------------
1426 * Register 0x3044: TXXG Status Register
1427 * Bit 1 TXXG_TXACTIVE
1428 * Bit 0 TXXG_PAUSED
1429 *----------------------------------------------------------------------------*/
1430#define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002
1431#define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001
1432
1433/*----------------------------------------------------------------------------
1434 * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register
1435 * Bit 7-0 TXXG_TX_MINFR
1436 *----------------------------------------------------------------------------*/
1437#define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF
1438#define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0
1439
1440/*----------------------------------------------------------------------------
1441 * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1442 * Bit 7-0 TXXG_FC_PAUSE_QNTM
1443 *----------------------------------------------------------------------------*/
1444#define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF
1445#define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0
1446
1447/*----------------------------------------------------------------------------
1448 * Register 0x3080: XTEF Control
1449 * Bit 3-0 XTEF_FORCE_PARITY_ERR
1450 *----------------------------------------------------------------------------*/
1451#define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F
1452#define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0
1453
1454/*----------------------------------------------------------------------------
1455 * Register 0x3084: XTEF Interrupt Event Register
1456 * Bit 0 XTEF_LOST_SYNCI
1457 *----------------------------------------------------------------------------*/
1458#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001
1459
1460/*----------------------------------------------------------------------------
1461 * Register 0x3085: XTEF Interrupt Enable Register
1462 * Bit 0 XTEF_LOST_SYNCE
1463 *----------------------------------------------------------------------------*/
1464#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001
1465
1466/*----------------------------------------------------------------------------
1467 * Register 0x3086: XTEF Visibility Register
1468 * Bit 0 XTEF_LOST_SYNCV
1469 *----------------------------------------------------------------------------*/
1470#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001
1471
1472/*----------------------------------------------------------------------------
1473 * Register 0x30C0: TXOAM OAM Configuration
1474 * Bit 15 TXOAM_HEC_EN
1475 * Bit 14 TXOAM_EMPTYCODE_EN
1476 * Bit 13 TXOAM_FORCE_IDLE
1477 * Bit 12 TXOAM_IGNORE_IDLE
1478 * Bit 11-6 TXOAM_PX_OVERWRITE
1479 * Bit 5-0 TXOAM_PX_SEL
1480 *----------------------------------------------------------------------------*/
1481#define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000
1482#define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000
1483#define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000
1484#define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000
1485#define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0
1486#define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 6
1487#define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F
1488#define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0
1489
1490/*----------------------------------------------------------------------------
1491 * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1492 * Bit 15 TXOAM_MINIDIS
1493 * Bit 14 TXOAM_BUSY
1494 * Bit 13 TXOAM_TRANS_EN
1495 * Bit 10-0 TXOAM_MINIRATE
1496 *----------------------------------------------------------------------------*/
1497#define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000
1498#define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000
1499#define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000
1500#define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF
1501
1502/*----------------------------------------------------------------------------
1503 * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1504 * Bit 13-10 TXOAM_FTHRESH
1505 * Bit 9-6 TXOAM_MINIPOST
1506 * Bit 5-0 TXOAM_MINIPRE
1507 *----------------------------------------------------------------------------*/
1508#define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00
1509#define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 10
1510#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0
1511#define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 6
1512#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F
1513
1514/*----------------------------------------------------------------------------
1515 * Register 0x30C6: TXOAM Interrupt Enable
1516 * Bit 2 TXOAM_SOP_ERRE
1517 * Bit 1 TXOAM_OFLE
1518 * Bit 0 TXOAM_ERRE
1519 *----------------------------------------------------------------------------*/
1520#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004
1521#define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002
1522#define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001
1523
1524/*----------------------------------------------------------------------------
1525 * Register 0x30C7: TXOAM Interrupt Status
1526 * Bit 2 TXOAM_SOP_ERRI
1527 * Bit 1 TXOAM_OFLI
1528 * Bit 0 TXOAM_ERRI
1529 *----------------------------------------------------------------------------*/
1530#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004
1531#define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002
1532#define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001
1533
1534/*----------------------------------------------------------------------------
1535 * Register 0x30CF: TXOAM Coset
1536 * Bit 7-0 TXOAM_COSET
1537 *----------------------------------------------------------------------------*/
1538#define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF
1539
1540/*----------------------------------------------------------------------------
1541 * Register 0x3200: EFLX Global Configuration
1542 * Bit 15 EFLX_ERCU_EN
1543 * Bit 7 EFLX_EN_EDSWT
1544 *----------------------------------------------------------------------------*/
1545#define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000
1546#define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080
1547
1548/*----------------------------------------------------------------------------
1549 * Register 0x3201: EFLX ERCU Global Status
1550 * Bit 13 EFLX_OVF_ERR
1551 *----------------------------------------------------------------------------*/
1552#define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000
1553
1554/*----------------------------------------------------------------------------
1555 * Register 0x3202: EFLX Indirect Channel Address
1556 * Bit 15 EFLX_BUSY
1557 * Bit 14 EFLX_RDWRB
1558 *----------------------------------------------------------------------------*/
1559#define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000
1560#define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000
1561
1562/*----------------------------------------------------------------------------
1563 * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1564 *----------------------------------------------------------------------------*/
1565#define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF
1566#define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0
1567
1568/*----------------------------------------------------------------------------
1569 * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1570 *----------------------------------------------------------------------------*/
1571#define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF
1572#define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0
1573
1574/*----------------------------------------------------------------------------
1575 * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1576 * Bit 15 EFLX_FULL
1577 * Bit 14 EFLX_AFULL
1578 * Bit 13-0 EFLX_AFTH
1579 *----------------------------------------------------------------------------*/
1580#define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000
1581#define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000
1582#define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF
1583#define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0
1584
1585/*----------------------------------------------------------------------------
1586 * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1587 * Bit 15 EFLX_EMPTY
1588 * Bit 14 EFLX_AEMPTY
1589 * Bit 13-0 EFLX_AETH
1590 *----------------------------------------------------------------------------*/
1591#define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000
1592#define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000
1593#define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF
1594#define SUNI1x10GEXP_BITOFF_EFLX_AETH 0
1595
1596/*----------------------------------------------------------------------------
1597 * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1598 *----------------------------------------------------------------------------*/
1599#define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF
1600#define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0
1601
1602/*----------------------------------------------------------------------------
1603 * Register 0x320C: EFLX FIFO Overflow Error Enable
1604 * Bit 0 EFLX_OVFE
1605 *----------------------------------------------------------------------------*/
1606#define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001
1607
1608/*----------------------------------------------------------------------------
1609 * Register 0x320D: EFLX FIFO Overflow Error Indication
1610 * Bit 0 EFLX_OVFI
1611 *----------------------------------------------------------------------------*/
1612#define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001
1613
1614/*----------------------------------------------------------------------------
1615 * Register 0x3210: EFLX Channel Provision
1616 * Bit 0 EFLX_PROV
1617 *----------------------------------------------------------------------------*/
1618#define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001
1619
1620/*----------------------------------------------------------------------------
1621 * Register 0x3280: PL4IDU Configuration
1622 * Bit 2 PL4IDU_SYNCH_ON_TRAIN
1623 * Bit 1 PL4IDU_EN_PORTS
1624 * Bit 0 PL4IDU_EN_DFWD
1625 *----------------------------------------------------------------------------*/
1626#define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004
1627#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002
1628#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001
1629
1630/*----------------------------------------------------------------------------
1631 * Register 0x3282: PL4IDU Interrupt Mask
1632 * Bit 1 PL4IDU_DIP4E
1633 *----------------------------------------------------------------------------*/
1634#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002
1635
1636/*----------------------------------------------------------------------------
1637 * Register 0x3283: PL4IDU Interrupt
1638 * Bit 1 PL4IDU_DIP4I
1639 *----------------------------------------------------------------------------*/
1640#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002
211 1641
212#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */ 1642#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
213 1643
diff --git a/drivers/net/chelsio/tp.c b/drivers/net/chelsio/tp.c
new file mode 100644
index 000000000000..0ca0b6e19e43
--- /dev/null
+++ b/drivers/net/chelsio/tp.c
@@ -0,0 +1,178 @@
1/* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */
2#include "common.h"
3#include "regs.h"
4#include "tp.h"
5#ifdef CONFIG_CHELSIO_T1_1G
6#include "fpga_defs.h"
7#endif
8
9struct petp {
10 adapter_t *adapter;
11};
12
13/* Pause deadlock avoidance parameters */
14#define DROP_MSEC 16
15#define DROP_PKTS_CNT 1
16
17static void tp_init(adapter_t * ap, const struct tp_params *p,
18 unsigned int tp_clk)
19{
20 if (t1_is_asic(ap)) {
21 u32 val;
22
23 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
24 F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
25 if (!p->pm_size)
26 val |= F_OFFLOAD_DISABLE;
27 else
28 val |= F_TP_IN_ESPI_CHECK_IP_CSUM |
29 F_TP_IN_ESPI_CHECK_TCP_CSUM;
30 writel(val, ap->regs + A_TP_IN_CONFIG);
31 writel(F_TP_OUT_CSPI_CPL |
32 F_TP_OUT_ESPI_ETHERNET |
33 F_TP_OUT_ESPI_GENERATE_IP_CSUM |
34 F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
35 ap->regs + A_TP_OUT_CONFIG);
36 writel(V_IP_TTL(64) |
37 F_PATH_MTU /* IP DF bit */ |
38 V_5TUPLE_LOOKUP(p->use_5tuple_mode) |
39 V_SYN_COOKIE_PARAMETER(29),
40 ap->regs + A_TP_GLOBAL_CONFIG);
41 /*
42 * Enable pause frame deadlock prevention.
43 */
44 if (is_T2(ap) && ap->params.nports > 1) {
45 u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
46
47 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
48 V_DROP_TICKS_CNT(drop_ticks) |
49 V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
50 ap->regs + A_TP_TX_DROP_CONFIG);
51 }
52
53 }
54}
55
56void t1_tp_destroy(struct petp *tp)
57{
58 kfree(tp);
59}
60
61struct petp *__devinit t1_tp_create(adapter_t * adapter, struct tp_params *p)
62{
63 struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL);
64 if (!tp)
65 return NULL;
66
67 tp->adapter = adapter;
68
69 return tp;
70}
71
72void t1_tp_intr_enable(struct petp *tp)
73{
74 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
75
76#ifdef CONFIG_CHELSIO_T1_1G
77 if (!t1_is_asic(tp->adapter)) {
78 /* FPGA */
79 writel(0xffffffff,
80 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
81 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
82 tp->adapter->regs + A_PL_ENABLE);
83 } else
84#endif
85 {
86 /* We don't use any TP interrupts */
87 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
88 writel(tp_intr | F_PL_INTR_TP,
89 tp->adapter->regs + A_PL_ENABLE);
90 }
91}
92
93void t1_tp_intr_disable(struct petp *tp)
94{
95 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
96
97#ifdef CONFIG_CHELSIO_T1_1G
98 if (!t1_is_asic(tp->adapter)) {
99 /* FPGA */
100 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
101 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
102 tp->adapter->regs + A_PL_ENABLE);
103 } else
104#endif
105 {
106 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
107 writel(tp_intr & ~F_PL_INTR_TP,
108 tp->adapter->regs + A_PL_ENABLE);
109 }
110}
111
112void t1_tp_intr_clear(struct petp *tp)
113{
114#ifdef CONFIG_CHELSIO_T1_1G
115 if (!t1_is_asic(tp->adapter)) {
116 writel(0xffffffff,
117 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
118 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
119 return;
120 }
121#endif
122 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
123 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
124}
125
126int t1_tp_intr_handler(struct petp *tp)
127{
128 u32 cause;
129
130#ifdef CONFIG_CHELSIO_T1_1G
131 /* FPGA doesn't support TP interrupts. */
132 if (!t1_is_asic(tp->adapter))
133 return 1;
134#endif
135
136 cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
137 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
138 return 0;
139}
140
141static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable)
142{
143 u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
144
145 if (enable)
146 val |= csum_bit;
147 else
148 val &= ~csum_bit;
149 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
150}
151
152void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable)
153{
154 set_csum_offload(tp, F_IP_CSUM, enable);
155}
156
157void t1_tp_set_udp_checksum_offload(struct petp *tp, int enable)
158{
159 set_csum_offload(tp, F_UDP_CSUM, enable);
160}
161
162void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable)
163{
164 set_csum_offload(tp, F_TCP_CSUM, enable);
165}
166
167/*
168 * Initialize TP state. tp_params contains initial settings for some TP
169 * parameters, particularly the one-time PM and CM settings.
170 */
171int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk)
172{
173 adapter_t *adapter = tp->adapter;
174
175 tp_init(adapter, p, tp_clk);
176 writel(F_TP_RESET, adapter->regs + A_TP_RESET);
177 return 0;
178}
diff --git a/drivers/net/chelsio/tp.h b/drivers/net/chelsio/tp.h
new file mode 100644
index 000000000000..32fc71e58913
--- /dev/null
+++ b/drivers/net/chelsio/tp.h
@@ -0,0 +1,73 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: tp.h,v $ $Revision: 1.20 $ */
2#ifndef CHELSIO_TP_H
3#define CHELSIO_TP_H
4
5#include "common.h"
6
7#define TP_MAX_RX_COALESCING_SIZE 16224U
8
9struct tp_mib_statistics {
10
11 /* IP */
12 u32 ipInReceive_hi;
13 u32 ipInReceive_lo;
14 u32 ipInHdrErrors_hi;
15 u32 ipInHdrErrors_lo;
16 u32 ipInAddrErrors_hi;
17 u32 ipInAddrErrors_lo;
18 u32 ipInUnknownProtos_hi;
19 u32 ipInUnknownProtos_lo;
20 u32 ipInDiscards_hi;
21 u32 ipInDiscards_lo;
22 u32 ipInDelivers_hi;
23 u32 ipInDelivers_lo;
24 u32 ipOutRequests_hi;
25 u32 ipOutRequests_lo;
26 u32 ipOutDiscards_hi;
27 u32 ipOutDiscards_lo;
28 u32 ipOutNoRoutes_hi;
29 u32 ipOutNoRoutes_lo;
30 u32 ipReasmTimeout;
31 u32 ipReasmReqds;
32 u32 ipReasmOKs;
33 u32 ipReasmFails;
34
35 u32 reserved[8];
36
37 /* TCP */
38 u32 tcpActiveOpens;
39 u32 tcpPassiveOpens;
40 u32 tcpAttemptFails;
41 u32 tcpEstabResets;
42 u32 tcpOutRsts;
43 u32 tcpCurrEstab;
44 u32 tcpInSegs_hi;
45 u32 tcpInSegs_lo;
46 u32 tcpOutSegs_hi;
47 u32 tcpOutSegs_lo;
48 u32 tcpRetransSeg_hi;
49 u32 tcpRetransSeg_lo;
50 u32 tcpInErrs_hi;
51 u32 tcpInErrs_lo;
52 u32 tcpRtoMin;
53 u32 tcpRtoMax;
54};
55
56struct petp;
57struct tp_params;
58
59struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p);
60void t1_tp_destroy(struct petp *tp);
61
62void t1_tp_intr_disable(struct petp *tp);
63void t1_tp_intr_enable(struct petp *tp);
64void t1_tp_intr_clear(struct petp *tp);
65int t1_tp_intr_handler(struct petp *tp);
66
67void t1_tp_get_mib_statistics(adapter_t *adap, struct tp_mib_statistics *tps);
68void t1_tp_set_udp_checksum_offload(struct petp *tp, int enable);
69void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable);
70void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable);
71int t1_tp_set_coalescing_size(struct petp *tp, unsigned int size);
72int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk);
73#endif
diff --git a/drivers/net/chelsio/vsc7326.c b/drivers/net/chelsio/vsc7326.c
new file mode 100644
index 000000000000..85dc3b1dc309
--- /dev/null
+++ b/drivers/net/chelsio/vsc7326.c
@@ -0,0 +1,725 @@
1/* $Date: 2006/04/28 19:20:06 $ $RCSfile: vsc7326.c,v $ $Revision: 1.19 $ */
2
3/* Driver for Vitesse VSC7326 (Schaumburg) MAC */
4
5#include "gmac.h"
6#include "elmer0.h"
7#include "vsc7326_reg.h"
8
9/* Update fast changing statistics every 15 seconds */
10#define STATS_TICK_SECS 15
11/* 30 minutes for full statistics update */
12#define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS)
13
14#define MAX_MTU 9600
15
16/* The egress WM value 0x01a01fff should be used only when the
17 * interface is down (MAC port disabled). This is a workaround
18 * for disabling the T2/MAC flow-control. When the interface is
19 * enabled, the WM value should be set to 0x014a03F0.
20 */
21#define WM_DISABLE 0x01a01fff
22#define WM_ENABLE 0x014a03F0
23
24struct init_table {
25 u32 addr;
26 u32 data;
27};
28
29struct _cmac_instance {
30 u32 index;
31 u32 ticks;
32};
33
34#define INITBLOCK_SLEEP 0xffffffff
35
36static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
37{
38 u32 status, vlo, vhi;
39 int i;
40
41 spin_lock_bh(&adapter->mac_lock);
42 t1_tpi_read(adapter, (addr << 2) + 4, &vlo);
43 i = 0;
44 do {
45 t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
46 t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
47 status = (vhi << 16) | vlo;
48 i++;
49 } while (((status & 1) == 0) && (i < 50));
50 if (i == 50)
51 CH_ERR("Invalid tpi read from MAC, breaking loop.\n");
52
53 t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
54 t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);
55
56 *val = (vhi << 16) | vlo;
57
58 /* CH_ERR("rd: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
59 ((addr&0xe000)>>13), ((addr&0x1e00)>>9),
60 ((addr&0x01fe)>>1), *val); */
61 spin_unlock_bh(&adapter->mac_lock);
62}
63
64static void vsc_write(adapter_t *adapter, u32 addr, u32 data)
65{
66 spin_lock_bh(&adapter->mac_lock);
67 t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
68 t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
69 /* CH_ERR("wr: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
70 ((addr&0xe000)>>13), ((addr&0x1e00)>>9),
71 ((addr&0x01fe)>>1), data); */
72 spin_unlock_bh(&adapter->mac_lock);
73}
74
75/* Hard reset the MAC. This wipes out *all* configuration. */
76static void vsc7326_full_reset(adapter_t* adapter)
77{
78 u32 val;
79 u32 result = 0xffff;
80
81 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
82 val &= ~1;
83 t1_tpi_write(adapter, A_ELMER0_GPO, val);
84 udelay(2);
85 val |= 0x1; /* Enable mac MAC itself */
86 val |= 0x800; /* Turn off the red LED */
87 t1_tpi_write(adapter, A_ELMER0_GPO, val);
88 mdelay(1);
89 vsc_write(adapter, REG_SW_RESET, 0x80000001);
90 do {
91 mdelay(1);
92 vsc_read(adapter, REG_SW_RESET, &result);
93 } while (result != 0x0);
94}
95
96static struct init_table vsc7326_reset[] = {
97 { REG_IFACE_MODE, 0x00000000 },
98 { REG_CRC_CFG, 0x00000020 },
99 { REG_PLL_CLK_SPEED, 0x00050c00 },
100 { REG_PLL_CLK_SPEED, 0x00050c00 },
101 { REG_MSCH, 0x00002f14 },
102 { REG_SPI4_MISC, 0x00040409 },
103 { REG_SPI4_DESKEW, 0x00080000 },
104 { REG_SPI4_ING_SETUP2, 0x08080004 },
105 { REG_SPI4_ING_SETUP0, 0x04111004 },
106 { REG_SPI4_EGR_SETUP0, 0x80001a04 },
107 { REG_SPI4_ING_SETUP1, 0x02010000 },
108 { REG_AGE_INC(0), 0x00000000 },
109 { REG_AGE_INC(1), 0x00000000 },
110 { REG_ING_CONTROL, 0x0a200011 },
111 { REG_EGR_CONTROL, 0xa0010091 },
112};
113
114static struct init_table vsc7326_portinit[4][22] = {
115 { /* Port 0 */
116 /* FIFO setup */
117 { REG_DBG(0), 0x000004f0 },
118 { REG_HDX(0), 0x00073101 },
119 { REG_TEST(0,0), 0x00000022 },
120 { REG_TEST(1,0), 0x00000022 },
121 { REG_TOP_BOTTOM(0,0), 0x003f0000 },
122 { REG_TOP_BOTTOM(1,0), 0x00120000 },
123 { REG_HIGH_LOW_WM(0,0), 0x07460757 },
124 { REG_HIGH_LOW_WM(1,0), WM_DISABLE },
125 { REG_CT_THRHLD(0,0), 0x00000000 },
126 { REG_CT_THRHLD(1,0), 0x00000000 },
127 { REG_BUCKE(0), 0x0002ffff },
128 { REG_BUCKI(0), 0x0002ffff },
129 { REG_TEST(0,0), 0x00000020 },
130 { REG_TEST(1,0), 0x00000020 },
131 /* Port config */
132 { REG_MAX_LEN(0), 0x00002710 },
133 { REG_PORT_FAIL(0), 0x00000002 },
134 { REG_NORMALIZER(0), 0x00000a64 },
135 { REG_DENORM(0), 0x00000010 },
136 { REG_STICK_BIT(0), 0x03baa370 },
137 { REG_DEV_SETUP(0), 0x00000083 },
138 { REG_DEV_SETUP(0), 0x00000082 },
139 { REG_MODE_CFG(0), 0x0200259f },
140 },
141 { /* Port 1 */
142 /* FIFO setup */
143 { REG_DBG(1), 0x000004f0 },
144 { REG_HDX(1), 0x00073101 },
145 { REG_TEST(0,1), 0x00000022 },
146 { REG_TEST(1,1), 0x00000022 },
147 { REG_TOP_BOTTOM(0,1), 0x007e003f },
148 { REG_TOP_BOTTOM(1,1), 0x00240012 },
149 { REG_HIGH_LOW_WM(0,1), 0x07460757 },
150 { REG_HIGH_LOW_WM(1,1), WM_DISABLE },
151 { REG_CT_THRHLD(0,1), 0x00000000 },
152 { REG_CT_THRHLD(1,1), 0x00000000 },
153 { REG_BUCKE(1), 0x0002ffff },
154 { REG_BUCKI(1), 0x0002ffff },
155 { REG_TEST(0,1), 0x00000020 },
156 { REG_TEST(1,1), 0x00000020 },
157 /* Port config */
158 { REG_MAX_LEN(1), 0x00002710 },
159 { REG_PORT_FAIL(1), 0x00000002 },
160 { REG_NORMALIZER(1), 0x00000a64 },
161 { REG_DENORM(1), 0x00000010 },
162 { REG_STICK_BIT(1), 0x03baa370 },
163 { REG_DEV_SETUP(1), 0x00000083 },
164 { REG_DEV_SETUP(1), 0x00000082 },
165 { REG_MODE_CFG(1), 0x0200259f },
166 },
167 { /* Port 2 */
168 /* FIFO setup */
169 { REG_DBG(2), 0x000004f0 },
170 { REG_HDX(2), 0x00073101 },
171 { REG_TEST(0,2), 0x00000022 },
172 { REG_TEST(1,2), 0x00000022 },
173 { REG_TOP_BOTTOM(0,2), 0x00bd007e },
174 { REG_TOP_BOTTOM(1,2), 0x00360024 },
175 { REG_HIGH_LOW_WM(0,2), 0x07460757 },
176 { REG_HIGH_LOW_WM(1,2), WM_DISABLE },
177 { REG_CT_THRHLD(0,2), 0x00000000 },
178 { REG_CT_THRHLD(1,2), 0x00000000 },
179 { REG_BUCKE(2), 0x0002ffff },
180 { REG_BUCKI(2), 0x0002ffff },
181 { REG_TEST(0,2), 0x00000020 },
182 { REG_TEST(1,2), 0x00000020 },
183 /* Port config */
184 { REG_MAX_LEN(2), 0x00002710 },
185 { REG_PORT_FAIL(2), 0x00000002 },
186 { REG_NORMALIZER(2), 0x00000a64 },
187 { REG_DENORM(2), 0x00000010 },
188 { REG_STICK_BIT(2), 0x03baa370 },
189 { REG_DEV_SETUP(2), 0x00000083 },
190 { REG_DEV_SETUP(2), 0x00000082 },
191 { REG_MODE_CFG(2), 0x0200259f },
192 },
193 { /* Port 3 */
194 /* FIFO setup */
195 { REG_DBG(3), 0x000004f0 },
196 { REG_HDX(3), 0x00073101 },
197 { REG_TEST(0,3), 0x00000022 },
198 { REG_TEST(1,3), 0x00000022 },
199 { REG_TOP_BOTTOM(0,3), 0x00fc00bd },
200 { REG_TOP_BOTTOM(1,3), 0x00480036 },
201 { REG_HIGH_LOW_WM(0,3), 0x07460757 },
202 { REG_HIGH_LOW_WM(1,3), WM_DISABLE },
203 { REG_CT_THRHLD(0,3), 0x00000000 },
204 { REG_CT_THRHLD(1,3), 0x00000000 },
205 { REG_BUCKE(3), 0x0002ffff },
206 { REG_BUCKI(3), 0x0002ffff },
207 { REG_TEST(0,3), 0x00000020 },
208 { REG_TEST(1,3), 0x00000020 },
209 /* Port config */
210 { REG_MAX_LEN(3), 0x00002710 },
211 { REG_PORT_FAIL(3), 0x00000002 },
212 { REG_NORMALIZER(3), 0x00000a64 },
213 { REG_DENORM(3), 0x00000010 },
214 { REG_STICK_BIT(3), 0x03baa370 },
215 { REG_DEV_SETUP(3), 0x00000083 },
216 { REG_DEV_SETUP(3), 0x00000082 },
217 { REG_MODE_CFG(3), 0x0200259f },
218 },
219};
220
221static void run_table(adapter_t *adapter, struct init_table *ib, int len)
222{
223 int i;
224
225 for (i = 0; i < len; i++) {
226 if (ib[i].addr == INITBLOCK_SLEEP) {
227 udelay( ib[i].data );
228 CH_ERR("sleep %d us\n",ib[i].data);
229 } else {
230 vsc_write( adapter, ib[i].addr, ib[i].data );
231 }
232 }
233}
234
235static int bist_rd(adapter_t *adapter, int moduleid, int address)
236{
237 int data=0;
238 u32 result=0;
239
240 if( (address != 0x0) &&
241 (address != 0x1) &&
242 (address != 0x2) &&
243 (address != 0xd) &&
244 (address != 0xe))
245 CH_ERR("No bist address: 0x%x\n", address);
246
247 data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
248 ((moduleid & 0xff) << 0));
249 vsc_write(adapter, REG_RAM_BIST_CMD, data);
250
251 udelay(10);
252
253 vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
254 if((result & (1<<9)) != 0x0)
255 CH_ERR("Still in bist read: 0x%x\n", result);
256 else if((result & (1<<8)) != 0x0)
257 CH_ERR("bist read error: 0x%x\n", result);
258
259 return(result & 0xff);
260}
261
262static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
263{
264 int data=0;
265 u32 result=0;
266
267 if( (address != 0x0) &&
268 (address != 0x1) &&
269 (address != 0x2) &&
270 (address != 0xd) &&
271 (address != 0xe))
272 CH_ERR("No bist address: 0x%x\n", address);
273
274 if( value>255 )
275 CH_ERR("Suspicious write out of range value: 0x%x\n", value);
276
277 data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
278 ((moduleid & 0xff) << 0));
279 vsc_write(adapter, REG_RAM_BIST_CMD, data);
280
281 udelay(5);
282
283 vsc_read(adapter, REG_RAM_BIST_CMD, &result);
284 if((result & (1<<27)) != 0x0)
285 CH_ERR("Still in bist write: 0x%x\n", result);
286 else if((result & (1<<26)) != 0x0)
287 CH_ERR("bist write error: 0x%x\n", result);
288
289 return(0);
290}
291
292static int run_bist(adapter_t *adapter, int moduleid)
293{
294 /*run bist*/
295 (void) bist_wr(adapter,moduleid, 0x00, 0x02);
296 (void) bist_wr(adapter,moduleid, 0x01, 0x01);
297
298 return(0);
299}
300
301static int check_bist(adapter_t *adapter, int moduleid)
302{
303 int result=0;
304 int column=0;
305 /*check bist*/
306 result = bist_rd(adapter,moduleid, 0x02);
307 column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +
308 (bist_rd(adapter,moduleid, 0x0d)));
309 if ((result & 3) != 0x3)
310 CH_ERR("Result: 0x%x BIST error in ram %d, column: 0x%04x\n",
311 result, moduleid, column);
312 return(0);
313}
314
315static int enable_mem(adapter_t *adapter, int moduleid)
316{
317 /*enable mem*/
318 (void) bist_wr(adapter,moduleid, 0x00, 0x00);
319 return(0);
320}
321
322static int run_bist_all(adapter_t *adapter)
323{
324 int port=0;
325 u32 val=0;
326
327 vsc_write(adapter, REG_MEM_BIST, 0x5);
328 vsc_read(adapter, REG_MEM_BIST, &val);
329
330 for(port=0; port<12; port++){
331 vsc_write(adapter, REG_DEV_SETUP(port), 0x0);
332 }
333
334 udelay(300);
335 vsc_write(adapter, REG_SPI4_MISC, 0x00040409);
336 udelay(300);
337
338 (void) run_bist(adapter,13);
339 (void) run_bist(adapter,14);
340 (void) run_bist(adapter,20);
341 (void) run_bist(adapter,21);
342 mdelay(200);
343 (void) check_bist(adapter,13);
344 (void) check_bist(adapter,14);
345 (void) check_bist(adapter,20);
346 (void) check_bist(adapter,21);
347 udelay(100);
348 (void) enable_mem(adapter,13);
349 (void) enable_mem(adapter,14);
350 (void) enable_mem(adapter,20);
351 (void) enable_mem(adapter,21);
352 udelay(300);
353 vsc_write(adapter, REG_SPI4_MISC, 0x60040400);
354 udelay(300);
355 for(port=0; port<12; port++){
356 vsc_write(adapter, REG_DEV_SETUP(port), 0x1);
357 }
358 udelay(300);
359 vsc_write(adapter, REG_MEM_BIST, 0x0);
360 mdelay(10);
361 return(0);
362}
363
364static int mac_intr_handler(struct cmac *mac)
365{
366 return 0;
367}
368
369static int mac_intr_enable(struct cmac *mac)
370{
371 return 0;
372}
373
374static int mac_intr_disable(struct cmac *mac)
375{
376 return 0;
377}
378
379static int mac_intr_clear(struct cmac *mac)
380{
381 return 0;
382}
383
384/* Expect MAC address to be in network byte order. */
385static int mac_set_address(struct cmac* mac, u8 addr[6])
386{
387 u32 val;
388 int port = mac->instance->index;
389
390 vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port),
391 (addr[3] << 16) | (addr[4] << 8) | addr[5]);
392 vsc_write(mac->adapter, REG_MAC_HIGH_ADDR(port),
393 (addr[0] << 16) | (addr[1] << 8) | addr[2]);
394
395 vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &val);
396 val &= ~0xf0000000;
397 vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, val | (port << 28));
398
399 vsc_write(mac->adapter, REG_ING_FFILT_MASK0,
400 0xffff0000 | (addr[4] << 8) | addr[5]);
401 vsc_write(mac->adapter, REG_ING_FFILT_MASK1,
402 0xffff0000 | (addr[2] << 8) | addr[3]);
403 vsc_write(mac->adapter, REG_ING_FFILT_MASK2,
404 0xffff0000 | (addr[0] << 8) | addr[1]);
405 return 0;
406}
407
408static int mac_get_address(struct cmac *mac, u8 addr[6])
409{
410 u32 addr_lo, addr_hi;
411 int port = mac->instance->index;
412
413 vsc_read(mac->adapter, REG_MAC_LOW_ADDR(port), &addr_lo);
414 vsc_read(mac->adapter, REG_MAC_HIGH_ADDR(port), &addr_hi);
415
416 addr[0] = (u8) (addr_hi >> 16);
417 addr[1] = (u8) (addr_hi >> 8);
418 addr[2] = (u8) addr_hi;
419 addr[3] = (u8) (addr_lo >> 16);
420 addr[4] = (u8) (addr_lo >> 8);
421 addr[5] = (u8) addr_lo;
422 return 0;
423}
424
425/* This is intended to reset a port, not the whole MAC */
426static int mac_reset(struct cmac *mac)
427{
428 int index = mac->instance->index;
429
430 run_table(mac->adapter, vsc7326_portinit[index],
431 ARRAY_SIZE(vsc7326_portinit[index]));
432
433 return 0;
434}
435
436static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
437{
438 u32 v;
439 int port = mac->instance->index;
440
441 vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &v);
442 v |= 1 << 12;
443
444 if (t1_rx_mode_promisc(rm))
445 v &= ~(1 << (port + 16));
446 else
447 v |= 1 << (port + 16);
448
449 vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, v);
450 return 0;
451}
452
453static int mac_set_mtu(struct cmac *mac, int mtu)
454{
455 int port = mac->instance->index;
456
457 if (mtu > MAX_MTU)
458 return -EINVAL;
459
460 /* max_len includes header and FCS */
461 vsc_write(mac->adapter, REG_MAX_LEN(port), mtu + 14 + 4);
462 return 0;
463}
464
465static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
466 int fc)
467{
468 u32 v;
469 int enable, port = mac->instance->index;
470
471 if (speed >= 0 && speed != SPEED_10 && speed != SPEED_100 &&
472 speed != SPEED_1000)
473 return -1;
474 if (duplex > 0 && duplex != DUPLEX_FULL)
475 return -1;
476
477 if (speed >= 0) {
478 vsc_read(mac->adapter, REG_MODE_CFG(port), &v);
479 enable = v & 3; /* save tx/rx enables */
480 v &= ~0xf;
481 v |= 4; /* full duplex */
482 if (speed == SPEED_1000)
483 v |= 8; /* GigE */
484 enable |= v;
485 vsc_write(mac->adapter, REG_MODE_CFG(port), v);
486
487 if (speed == SPEED_1000)
488 v = 0x82;
489 else if (speed == SPEED_100)
490 v = 0x84;
491 else /* SPEED_10 */
492 v = 0x86;
493 vsc_write(mac->adapter, REG_DEV_SETUP(port), v | 1); /* reset */
494 vsc_write(mac->adapter, REG_DEV_SETUP(port), v);
495 vsc_read(mac->adapter, REG_DBG(port), &v);
496 v &= ~0xff00;
497 if (speed == SPEED_1000)
498 v |= 0x400;
499 else if (speed == SPEED_100)
500 v |= 0x2000;
501 else /* SPEED_10 */
502 v |= 0xff00;
503 vsc_write(mac->adapter, REG_DBG(port), v);
504
505 vsc_write(mac->adapter, REG_TX_IFG(port),
506 speed == SPEED_1000 ? 5 : 0x11);
507 if (duplex == DUPLEX_HALF)
508 enable = 0x0; /* 100 or 10 */
509 else if (speed == SPEED_1000)
510 enable = 0xc;
511 else /* SPEED_100 or 10 */
512 enable = 0x4;
513 enable |= 0x9 << 10; /* IFG1 */
514 enable |= 0x6 << 6; /* IFG2 */
515 enable |= 0x1 << 4; /* VLAN */
516 enable |= 0x3; /* RX/TX EN */
517 vsc_write(mac->adapter, REG_MODE_CFG(port), enable);
518
519 }
520
521 vsc_read(mac->adapter, REG_PAUSE_CFG(port), &v);
522 v &= 0xfff0ffff;
523 v |= 0x20000; /* xon/xoff */
524 if (fc & PAUSE_RX)
525 v |= 0x40000;
526 if (fc & PAUSE_TX)
527 v |= 0x80000;
528 if (fc == (PAUSE_RX | PAUSE_TX))
529 v |= 0x10000;
530 vsc_write(mac->adapter, REG_PAUSE_CFG(port), v);
531 return 0;
532}
533
534static int mac_enable(struct cmac *mac, int which)
535{
536 u32 val;
537 int port = mac->instance->index;
538
539 /* Write the correct WM value when the port is enabled. */
540 vsc_write(mac->adapter, REG_HIGH_LOW_WM(1,port), WM_ENABLE);
541
542 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
543 if (which & MAC_DIRECTION_RX)
544 val |= 0x2;
545 if (which & MAC_DIRECTION_TX)
546 val |= 1;
547 vsc_write(mac->adapter, REG_MODE_CFG(port), val);
548 return 0;
549}
550
551static int mac_disable(struct cmac *mac, int which)
552{
553 u32 val;
554 int i, port = mac->instance->index;
555
556 /* Reset the port, this also writes the correct WM value */
557 mac_reset(mac);
558
559 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
560 if (which & MAC_DIRECTION_RX)
561 val &= ~0x2;
562 if (which & MAC_DIRECTION_TX)
563 val &= ~0x1;
564 vsc_write(mac->adapter, REG_MODE_CFG(port), val);
565 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
566
567 /* Clear stats */
568 for (i = 0; i <= 0x3a; ++i)
569 vsc_write(mac->adapter, CRA(4, port, i), 0);
570
571 /* Clear sofware counters */
572 memset(&mac->stats, 0, sizeof(struct cmac_statistics));
573
574 return 0;
575}
576
577static void rmon_update(struct cmac *mac, unsigned int addr, u64 *stat)
578{
579 u32 v, lo;
580
581 vsc_read(mac->adapter, addr, &v);
582 lo = *stat;
583 *stat = *stat - lo + v;
584
585 if (v == 0)
586 return;
587
588 if (v < lo)
589 *stat += (1ULL << 32);
590}
591
592static void port_stats_update(struct cmac *mac)
593{
594 int port = mac->instance->index;
595
596 /* Rx stats */
597 rmon_update(mac, REG_RX_OK_BYTES(port), &mac->stats.RxOctetsOK);
598 rmon_update(mac, REG_RX_BAD_BYTES(port), &mac->stats.RxOctetsBad);
599 rmon_update(mac, REG_RX_UNICAST(port), &mac->stats.RxUnicastFramesOK);
600 rmon_update(mac, REG_RX_MULTICAST(port),
601 &mac->stats.RxMulticastFramesOK);
602 rmon_update(mac, REG_RX_BROADCAST(port),
603 &mac->stats.RxBroadcastFramesOK);
604 rmon_update(mac, REG_CRC(port), &mac->stats.RxFCSErrors);
605 rmon_update(mac, REG_RX_ALIGNMENT(port), &mac->stats.RxAlignErrors);
606 rmon_update(mac, REG_RX_OVERSIZE(port),
607 &mac->stats.RxFrameTooLongErrors);
608 rmon_update(mac, REG_RX_PAUSE(port), &mac->stats.RxPauseFrames);
609 rmon_update(mac, REG_RX_JABBERS(port), &mac->stats.RxJabberErrors);
610 rmon_update(mac, REG_RX_FRAGMENTS(port), &mac->stats.RxRuntErrors);
611 rmon_update(mac, REG_RX_UNDERSIZE(port), &mac->stats.RxRuntErrors);
612 rmon_update(mac, REG_RX_SYMBOL_CARRIER(port),
613 &mac->stats.RxSymbolErrors);
614 rmon_update(mac, REG_RX_SIZE_1519_TO_MAX(port),
615 &mac->stats.RxJumboFramesOK);
616
617 /* Tx stats (skip collision stats as we are full-duplex only) */
618 rmon_update(mac, REG_TX_OK_BYTES(port), &mac->stats.TxOctetsOK);
619 rmon_update(mac, REG_TX_UNICAST(port), &mac->stats.TxUnicastFramesOK);
620 rmon_update(mac, REG_TX_MULTICAST(port),
621 &mac->stats.TxMulticastFramesOK);
622 rmon_update(mac, REG_TX_BROADCAST(port),
623 &mac->stats.TxBroadcastFramesOK);
624 rmon_update(mac, REG_TX_PAUSE(port), &mac->stats.TxPauseFrames);
625 rmon_update(mac, REG_TX_UNDERRUN(port), &mac->stats.TxUnderrun);
626 rmon_update(mac, REG_TX_SIZE_1519_TO_MAX(port),
627 &mac->stats.TxJumboFramesOK);
628}
629
630/*
631 * This function is called periodically to accumulate the current values of the
632 * RMON counters into the port statistics. Since the counters are only 32 bits
633 * some of them can overflow in less than a minute at GigE speeds, so this
634 * function should be called every 30 seconds or so.
635 *
636 * To cut down on reading costs we update only the octet counters at each tick
637 * and do a full update at major ticks, which can be every 30 minutes or more.
638 */
639static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
640 int flag)
641{
642 if (flag == MAC_STATS_UPDATE_FULL ||
643 mac->instance->ticks >= MAJOR_UPDATE_TICKS) {
644 port_stats_update(mac);
645 mac->instance->ticks = 0;
646 } else {
647 int port = mac->instance->index;
648
649 rmon_update(mac, REG_RX_OK_BYTES(port),
650 &mac->stats.RxOctetsOK);
651 rmon_update(mac, REG_RX_BAD_BYTES(port),
652 &mac->stats.RxOctetsBad);
653 rmon_update(mac, REG_TX_OK_BYTES(port),
654 &mac->stats.TxOctetsOK);
655 mac->instance->ticks++;
656 }
657 return &mac->stats;
658}
659
660static void mac_destroy(struct cmac *mac)
661{
662 kfree(mac);
663}
664
665static struct cmac_ops vsc7326_ops = {
666 .destroy = mac_destroy,
667 .reset = mac_reset,
668 .interrupt_handler = mac_intr_handler,
669 .interrupt_enable = mac_intr_enable,
670 .interrupt_disable = mac_intr_disable,
671 .interrupt_clear = mac_intr_clear,
672 .enable = mac_enable,
673 .disable = mac_disable,
674 .set_mtu = mac_set_mtu,
675 .set_rx_mode = mac_set_rx_mode,
676 .set_speed_duplex_fc = mac_set_speed_duplex_fc,
677 .statistics_update = mac_update_statistics,
678 .macaddress_get = mac_get_address,
679 .macaddress_set = mac_set_address,
680};
681
682static struct cmac *vsc7326_mac_create(adapter_t *adapter, int index)
683{
684 struct cmac *mac;
685 u32 val;
686 int i;
687
688 mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
689 if (!mac) return NULL;
690
691 mac->ops = &vsc7326_ops;
692 mac->instance = (cmac_instance *)(mac + 1);
693 mac->adapter = adapter;
694
695 mac->instance->index = index;
696 mac->instance->ticks = 0;
697
698 i = 0;
699 do {
700 u32 vhi, vlo;
701
702 vhi = vlo = 0;
703 t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
704 udelay(1);
705 t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
706 udelay(5);
707 val = (vhi << 16) | vlo;
708 } while ((++i < 10000) && (val == 0xffffffff));
709
710 return mac;
711}
712
713static int vsc7326_mac_reset(adapter_t *adapter)
714{
715 vsc7326_full_reset(adapter);
716 (void) run_bist_all(adapter);
717 run_table(adapter, vsc7326_reset, ARRAY_SIZE(vsc7326_reset));
718 return 0;
719}
720
721struct gmac t1_vsc7326_ops = {
722 .stats_update_period = STATS_TICK_SECS,
723 .create = vsc7326_mac_create,
724 .reset = vsc7326_mac_reset,
725};
diff --git a/drivers/net/chelsio/vsc7326_reg.h b/drivers/net/chelsio/vsc7326_reg.h
new file mode 100644
index 000000000000..491bcf75c4fb
--- /dev/null
+++ b/drivers/net/chelsio/vsc7326_reg.h
@@ -0,0 +1,286 @@
1/* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */
2#ifndef _VSC7321_REG_H_
3#define _VSC7321_REG_H_
4
5/* Register definitions for Vitesse VSC7321 (Meigs II) MAC
6 *
7 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
8 * PD0011-01-14-Meigs-II 2002-12-12
9 */
10
11/* Just 'cause it's in here doesn't mean it's used. */
12
13#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
14
15/* System and CPU comm's registers */
16#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
17#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
18#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
19#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
20#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
21#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
22#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
23#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
24#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
25#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
26#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */
27#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */
28#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */
29#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */
30#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */
31#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */
32#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */
33
34/* Aggregator registers */
35#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */
36#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */
37#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */
38#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */
39#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */
40#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */
41#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */
42#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */
43#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */
44#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */
45#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */
46#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */
47
48/* BIST registers */
49/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
50/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
51#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */
52#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */
53#define BIST_PORT_SELECT 0x00 /* BIST port select */
54#define BIST_COMMAND 0x01 /* BIST enable/disable */
55#define BIST_STATUS 0x02 /* BIST operation status */
56#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */
57#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */
58#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */
59#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */
60#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */
61#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */
62#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */
63#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */
64#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */
65
66/* FIFO registers
67 * ie = 0 for ingress, 1 for egress
68 * fn = FIFO number, 0-9
69 */
70#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */
71#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */
72#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */
73#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */
74#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */
75#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */
76#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */
77#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
78#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
79#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
80
81/* Traffic shaper buckets
82 * ie = 0 for ingress, 1 for egress
83 * bn = bucket number 0-10 (yes, 11 buckets)
84 */
85/* OK, this one's kinda ugly. Some hardware designers are perverse. */
86#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
87#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
88
89#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */
90#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */
91#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */
92#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */
93#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */
94#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */
95#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
96#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */
97/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */
98#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */
99#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */
100#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */
101#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */
102#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */
103#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */
104#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */
105
106/* SPI4 interface */
107#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */
108#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */
109#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */
110#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */
111#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */
112#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */
113#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
114#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */
115#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */
116#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */
117#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */
118#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */
119#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */
120#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */
121#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */
122#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */
123#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */
124#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */
125#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */
126#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */
127
128#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */
129
130/* 10GbE MAC Block Registers */
131/* Note that those registers that are exactly the same for 10GbE as for
132 * tri-speed are only defined with the version that needs a port number.
133 * Pass 0xa in those cases.
134 *
135 * Also note that despite the presence of a MAC address register, this part
136 * does no ingress MAC address filtering. That register is used only for
137 * pause frame detection and generation.
138 */
139/* 10GbE specific, and different from tri-speed */
140#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */
141#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */
142#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */
143#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
144#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */
145#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */
146#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
147#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */
148#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */
149#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */
150#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */
151#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */
152#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */
153#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */
154#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */
155#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */
156#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */
157#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */
158#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */
159#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */
160#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */
161#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */
162#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */
163
164/* pn = port number 0-9 for tri-speed, 10 for 10GbE */
165/* Both tri-speed and 10GbE */
166#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */
167#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */
168#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */
169
170/* tri-speed only
171 * pn = port number, 0-9
172 */
173#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */
174#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */
175#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */
176#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */
177#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */
178#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */
179#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */
180#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */
181#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */
182#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */
183#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */
184#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */
185#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */
186#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */
187#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */
188#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */
189#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */
190#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */
191#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */
192#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */
193
194/* Statistics */
195/* pn = port number, 0-a, a = 10GbE */
196#define REG_RX_IN_BYTES(pn) CRA(0x4,pn,0x00) /* # Rx in octets */
197#define REG_RX_SYMBOL_CARRIER(pn) CRA(0x4,pn,0x01) /* Frames w/ symbol errors */
198#define REG_RX_PAUSE(pn) CRA(0x4,pn,0x02) /* # pause frames received */
199#define REG_RX_UNSUP_OPCODE(pn) CRA(0x4,pn,0x03) /* # control frames with unsupported opcode */
200#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,0x04) /* # octets in good frames */
201#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,0x05) /* # octets in bad frames */
202#define REG_RX_UNICAST(pn) CRA(0x4,pn,0x06) /* # good unicast frames */
203#define REG_RX_MULTICAST(pn) CRA(0x4,pn,0x07) /* # good multicast frames */
204#define REG_RX_BROADCAST(pn) CRA(0x4,pn,0x08) /* # good broadcast frames */
205#define REG_CRC(pn) CRA(0x4,pn,0x09) /* # frames w/ bad CRC only */
206#define REG_RX_ALIGNMENT(pn) CRA(0x4,pn,0x0a) /* # frames w/ alignment err */
207#define REG_RX_UNDERSIZE(pn) CRA(0x4,pn,0x0b) /* # frames undersize */
208#define REG_RX_FRAGMENTS(pn) CRA(0x4,pn,0x0c) /* # frames undersize w/ crc err */
209#define REG_RX_IN_RANGE_LENGTH_ERROR(pn) CRA(0x4,pn,0x0d) /* # frames with length error */
210#define REG_RX_OUT_OF_RANGE_ERROR(pn) CRA(0x4,pn,0x0e) /* # frames with illegal length field */
211#define REG_RX_OVERSIZE(pn) CRA(0x4,pn,0x0f) /* # frames oversize */
212#define REG_RX_JABBERS(pn) CRA(0x4,pn,0x10) /* # frames oversize w/ crc err */
213#define REG_RX_SIZE_64(pn) CRA(0x4,pn,0x11) /* # frames 64 octets long */
214#define REG_RX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x12) /* # frames 65-127 octets */
215#define REG_RX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x13) /* # frames 128-255 */
216#define REG_RX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x14) /* # frames 256-511 */
217#define REG_RX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x15) /* # frames 512-1023 */
218#define REG_RX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x16) /* # frames 1024-1518 */
219#define REG_RX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x17) /* # frames 1519-max */
220
221#define REG_TX_OUT_BYTES(pn) CRA(0x4,pn,0x18) /* # octets tx */
222#define REG_TX_PAUSE(pn) CRA(0x4,pn,0x19) /* # pause frames sent */
223#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,0x1a) /* # octets tx OK */
224#define REG_TX_UNICAST(pn) CRA(0x4,pn,0x1b) /* # frames unicast */
225#define REG_TX_MULTICAST(pn) CRA(0x4,pn,0x1c) /* # frames multicast */
226#define REG_TX_BROADCAST(pn) CRA(0x4,pn,0x1d) /* # frames broadcast */
227#define REG_TX_MULTIPLE_COLL(pn) CRA(0x4,pn,0x1e) /* # frames tx after multiple collisions */
228#define REG_TX_LATE_COLL(pn) CRA(0x4,pn,0x1f) /* # late collisions detected */
229#define REG_TX_XCOLL(pn) CRA(0x4,pn,0x20) /* # frames lost, excessive collisions */
230#define REG_TX_DEFER(pn) CRA(0x4,pn,0x21) /* # frames deferred on first tx attempt */
231#define REG_TX_XDEFER(pn) CRA(0x4,pn,0x22) /* # frames excessively deferred */
232#define REG_TX_CSENSE(pn) CRA(0x4,pn,0x23) /* carrier sense errors at frame end */
233#define REG_TX_SIZE_64(pn) CRA(0x4,pn,0x24) /* # frames 64 octets long */
234#define REG_TX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x25) /* # frames 65-127 octets */
235#define REG_TX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x26) /* # frames 128-255 */
236#define REG_TX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x27) /* # frames 256-511 */
237#define REG_TX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x28) /* # frames 512-1023 */
238#define REG_TX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x29) /* # frames 1024-1518 */
239#define REG_TX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x2a) /* # frames 1519-max */
240#define REG_TX_SINGLE_COLL(pn) CRA(0x4,pn,0x2b) /* # frames tx after single collision */
241#define REG_TX_BACKOFF2(pn) CRA(0x4,pn,0x2c) /* # frames tx ok after 2 backoffs/collisions */
242#define REG_TX_BACKOFF3(pn) CRA(0x4,pn,0x2d) /* after 3 backoffs/collisions */
243#define REG_TX_BACKOFF4(pn) CRA(0x4,pn,0x2e) /* after 4 */
244#define REG_TX_BACKOFF5(pn) CRA(0x4,pn,0x2f) /* after 5 */
245#define REG_TX_BACKOFF6(pn) CRA(0x4,pn,0x30) /* after 6 */
246#define REG_TX_BACKOFF7(pn) CRA(0x4,pn,0x31) /* after 7 */
247#define REG_TX_BACKOFF8(pn) CRA(0x4,pn,0x32) /* after 8 */
248#define REG_TX_BACKOFF9(pn) CRA(0x4,pn,0x33) /* after 9 */
249#define REG_TX_BACKOFF10(pn) CRA(0x4,pn,0x34) /* after 10 */
250#define REG_TX_BACKOFF11(pn) CRA(0x4,pn,0x35) /* after 11 */
251#define REG_TX_BACKOFF12(pn) CRA(0x4,pn,0x36) /* after 12 */
252#define REG_TX_BACKOFF13(pn) CRA(0x4,pn,0x37) /* after 13 */
253#define REG_TX_BACKOFF14(pn) CRA(0x4,pn,0x38) /* after 14 */
254#define REG_TX_BACKOFF15(pn) CRA(0x4,pn,0x39) /* after 15 */
255#define REG_TX_UNDERRUN(pn) CRA(0x4,pn,0x3a) /* # frames dropped from underrun */
256#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */
257#define REG_RX_IPG_SHRINK(pn) CRA(0x4,pn,0x3c) /* # of IPG shrinks detected */
258
259#define REG_STAT_STICKY1G(pn) CRA(0x4,pn,0x3e) /* tri-speed sticky bits */
260#define REG_STAT_STICKY10G CRA(0x4,0xa,0x3e) /* 10GbE sticky bits */
261#define REG_STAT_INIT(pn) CRA(0x4,pn,0x3f) /* Clear all statistics */
262
263/* MII-Management Block registers */
264/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If
265 * we hooked up to the one with separate directions, the middle 0x0 needs to
266 * change to 0x1. And the current errata states that MII-M 1 doesn't work.
267 */
268
269#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */
270#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */
271#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */
272#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */
273
274#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
275#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
276#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
277#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
278#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
279#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
280#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
281#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
282
283
284/* Whew. */
285
286#endif
diff --git a/drivers/net/chelsio/vsc8244.c b/drivers/net/chelsio/vsc8244.c
new file mode 100644
index 000000000000..c493e783d459
--- /dev/null
+++ b/drivers/net/chelsio/vsc8244.c
@@ -0,0 +1,368 @@
1/*
2 * This file is part of the Chelsio T2 Ethernet driver.
3 *
4 * Copyright (C) 2005 Chelsio Communications. All rights reserved.
5 *
6 * This program is distributed in the hope that it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
9 * release for licensing terms and conditions.
10 */
11
12#include "common.h"
13#include "cphy.h"
14#include "elmer0.h"
15
16#ifndef ADVERTISE_PAUSE_CAP
17# define ADVERTISE_PAUSE_CAP 0x400
18#endif
19#ifndef ADVERTISE_PAUSE_ASYM
20# define ADVERTISE_PAUSE_ASYM 0x800
21#endif
22
23/* Gigabit MII registers */
24#ifndef MII_CTRL1000
25# define MII_CTRL1000 9
26#endif
27
28#ifndef ADVERTISE_1000FULL
29# define ADVERTISE_1000FULL 0x200
30# define ADVERTISE_1000HALF 0x100
31#endif
32
33/* VSC8244 PHY specific registers. */
34enum {
35 VSC8244_INTR_ENABLE = 25,
36 VSC8244_INTR_STATUS = 26,
37 VSC8244_AUX_CTRL_STAT = 28,
38};
39
40enum {
41 VSC_INTR_RX_ERR = 1 << 0,
42 VSC_INTR_MS_ERR = 1 << 1, /* master/slave resolution error */
43 VSC_INTR_CABLE = 1 << 2, /* cable impairment */
44 VSC_INTR_FALSE_CARR = 1 << 3, /* false carrier */
45 VSC_INTR_MEDIA_CHG = 1 << 4, /* AMS media change */
46 VSC_INTR_RX_FIFO = 1 << 5, /* Rx FIFO over/underflow */
47 VSC_INTR_TX_FIFO = 1 << 6, /* Tx FIFO over/underflow */
48 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
49 VSC_INTR_SYMBOL_ERR = 1 << 8, /* symbol error */
50 VSC_INTR_NEG_DONE = 1 << 10, /* autoneg done */
51 VSC_INTR_NEG_ERR = 1 << 11, /* autoneg error */
52 VSC_INTR_LINK_CHG = 1 << 13, /* link change */
53 VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */
54};
55
56#define CFG_CHG_INTR_MASK (VSC_INTR_LINK_CHG | VSC_INTR_NEG_ERR | \
57 VSC_INTR_NEG_DONE)
58#define INTR_MASK (CFG_CHG_INTR_MASK | VSC_INTR_TX_FIFO | VSC_INTR_RX_FIFO | \
59 VSC_INTR_ENABLE)
60
61/* PHY specific auxiliary control & status register fields */
62#define S_ACSR_ACTIPHY_TMR 0
63#define M_ACSR_ACTIPHY_TMR 0x3
64#define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR)
65
66#define S_ACSR_SPEED 3
67#define M_ACSR_SPEED 0x3
68#define G_ACSR_SPEED(x) (((x) >> S_ACSR_SPEED) & M_ACSR_SPEED)
69
70#define S_ACSR_DUPLEX 5
71#define F_ACSR_DUPLEX (1 << S_ACSR_DUPLEX)
72
73#define S_ACSR_ACTIPHY 6
74#define F_ACSR_ACTIPHY (1 << S_ACSR_ACTIPHY)
75
76/*
77 * Reset the PHY. This PHY completes reset immediately so we never wait.
78 */
79static int vsc8244_reset(struct cphy *cphy, int wait)
80{
81 int err;
82 unsigned int ctl;
83
84 err = simple_mdio_read(cphy, MII_BMCR, &ctl);
85 if (err)
86 return err;
87
88 ctl &= ~BMCR_PDOWN;
89 ctl |= BMCR_RESET;
90 return simple_mdio_write(cphy, MII_BMCR, ctl);
91}
92
93static int vsc8244_intr_enable(struct cphy *cphy)
94{
95 simple_mdio_write(cphy, VSC8244_INTR_ENABLE, INTR_MASK);
96
97 /* Enable interrupts through Elmer */
98 if (t1_is_asic(cphy->adapter)) {
99 u32 elmer;
100
101 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
102 elmer |= ELMER0_GP_BIT1;
103 if (is_T2(cphy->adapter)) {
104 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
105 }
106 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
107 }
108
109 return 0;
110}
111
112static int vsc8244_intr_disable(struct cphy *cphy)
113{
114 simple_mdio_write(cphy, VSC8244_INTR_ENABLE, 0);
115
116 if (t1_is_asic(cphy->adapter)) {
117 u32 elmer;
118
119 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
120 elmer &= ~ELMER0_GP_BIT1;
121 if (is_T2(cphy->adapter)) {
122 elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
123 }
124 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
125 }
126
127 return 0;
128}
129
130static int vsc8244_intr_clear(struct cphy *cphy)
131{
132 u32 val;
133 u32 elmer;
134
135 /* Clear PHY interrupts by reading the register. */
136 simple_mdio_read(cphy, VSC8244_INTR_ENABLE, &val);
137
138 if (t1_is_asic(cphy->adapter)) {
139 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
140 elmer |= ELMER0_GP_BIT1;
141 if (is_T2(cphy->adapter)) {
142 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
143 }
144 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
145 }
146
147 return 0;
148}
149
150/*
151 * Force the PHY speed and duplex. This also disables auto-negotiation, except
152 * for 1Gb/s, where auto-negotiation is mandatory.
153 */
154static int vsc8244_set_speed_duplex(struct cphy *phy, int speed, int duplex)
155{
156 int err;
157 unsigned int ctl;
158
159 err = simple_mdio_read(phy, MII_BMCR, &ctl);
160 if (err)
161 return err;
162
163 if (speed >= 0) {
164 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
165 if (speed == SPEED_100)
166 ctl |= BMCR_SPEED100;
167 else if (speed == SPEED_1000)
168 ctl |= BMCR_SPEED1000;
169 }
170 if (duplex >= 0) {
171 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
172 if (duplex == DUPLEX_FULL)
173 ctl |= BMCR_FULLDPLX;
174 }
175 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */
176 ctl |= BMCR_ANENABLE;
177 return simple_mdio_write(phy, MII_BMCR, ctl);
178}
179
180int t1_mdio_set_bits(struct cphy *phy, int mmd, int reg, unsigned int bits)
181{
182 int ret;
183 unsigned int val;
184
185 ret = mdio_read(phy, mmd, reg, &val);
186 if (!ret)
187 ret = mdio_write(phy, mmd, reg, val | bits);
188 return ret;
189}
190
191static int vsc8244_autoneg_enable(struct cphy *cphy)
192{
193 return t1_mdio_set_bits(cphy, 0, MII_BMCR,
194 BMCR_ANENABLE | BMCR_ANRESTART);
195}
196
197static int vsc8244_autoneg_restart(struct cphy *cphy)
198{
199 return t1_mdio_set_bits(cphy, 0, MII_BMCR, BMCR_ANRESTART);
200}
201
202static int vsc8244_advertise(struct cphy *phy, unsigned int advertise_map)
203{
204 int err;
205 unsigned int val = 0;
206
207 err = simple_mdio_read(phy, MII_CTRL1000, &val);
208 if (err)
209 return err;
210
211 val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
212 if (advertise_map & ADVERTISED_1000baseT_Half)
213 val |= ADVERTISE_1000HALF;
214 if (advertise_map & ADVERTISED_1000baseT_Full)
215 val |= ADVERTISE_1000FULL;
216
217 err = simple_mdio_write(phy, MII_CTRL1000, val);
218 if (err)
219 return err;
220
221 val = 1;
222 if (advertise_map & ADVERTISED_10baseT_Half)
223 val |= ADVERTISE_10HALF;
224 if (advertise_map & ADVERTISED_10baseT_Full)
225 val |= ADVERTISE_10FULL;
226 if (advertise_map & ADVERTISED_100baseT_Half)
227 val |= ADVERTISE_100HALF;
228 if (advertise_map & ADVERTISED_100baseT_Full)
229 val |= ADVERTISE_100FULL;
230 if (advertise_map & ADVERTISED_PAUSE)
231 val |= ADVERTISE_PAUSE_CAP;
232 if (advertise_map & ADVERTISED_ASYM_PAUSE)
233 val |= ADVERTISE_PAUSE_ASYM;
234 return simple_mdio_write(phy, MII_ADVERTISE, val);
235}
236
237static int vsc8244_get_link_status(struct cphy *cphy, int *link_ok,
238 int *speed, int *duplex, int *fc)
239{
240 unsigned int bmcr, status, lpa, adv;
241 int err, sp = -1, dplx = -1, pause = 0;
242
243 err = simple_mdio_read(cphy, MII_BMCR, &bmcr);
244 if (!err)
245 err = simple_mdio_read(cphy, MII_BMSR, &status);
246 if (err)
247 return err;
248
249 if (link_ok) {
250 /*
251 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
252 * once more to get the current link state.
253 */
254 if (!(status & BMSR_LSTATUS))
255 err = simple_mdio_read(cphy, MII_BMSR, &status);
256 if (err)
257 return err;
258 *link_ok = (status & BMSR_LSTATUS) != 0;
259 }
260 if (!(bmcr & BMCR_ANENABLE)) {
261 dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
262 if (bmcr & BMCR_SPEED1000)
263 sp = SPEED_1000;
264 else if (bmcr & BMCR_SPEED100)
265 sp = SPEED_100;
266 else
267 sp = SPEED_10;
268 } else if (status & BMSR_ANEGCOMPLETE) {
269 err = simple_mdio_read(cphy, VSC8244_AUX_CTRL_STAT, &status);
270 if (err)
271 return err;
272
273 dplx = (status & F_ACSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
274 sp = G_ACSR_SPEED(status);
275 if (sp == 0)
276 sp = SPEED_10;
277 else if (sp == 1)
278 sp = SPEED_100;
279 else
280 sp = SPEED_1000;
281
282 if (fc && dplx == DUPLEX_FULL) {
283 err = simple_mdio_read(cphy, MII_LPA, &lpa);
284 if (!err)
285 err = simple_mdio_read(cphy, MII_ADVERTISE,
286 &adv);
287 if (err)
288 return err;
289
290 if (lpa & adv & ADVERTISE_PAUSE_CAP)
291 pause = PAUSE_RX | PAUSE_TX;
292 else if ((lpa & ADVERTISE_PAUSE_CAP) &&
293 (lpa & ADVERTISE_PAUSE_ASYM) &&
294 (adv & ADVERTISE_PAUSE_ASYM))
295 pause = PAUSE_TX;
296 else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
297 (adv & ADVERTISE_PAUSE_CAP))
298 pause = PAUSE_RX;
299 }
300 }
301 if (speed)
302 *speed = sp;
303 if (duplex)
304 *duplex = dplx;
305 if (fc)
306 *fc = pause;
307 return 0;
308}
309
310static int vsc8244_intr_handler(struct cphy *cphy)
311{
312 unsigned int cause;
313 int err, cphy_cause = 0;
314
315 err = simple_mdio_read(cphy, VSC8244_INTR_STATUS, &cause);
316 if (err)
317 return err;
318
319 cause &= INTR_MASK;
320 if (cause & CFG_CHG_INTR_MASK)
321 cphy_cause |= cphy_cause_link_change;
322 if (cause & (VSC_INTR_RX_FIFO | VSC_INTR_TX_FIFO))
323 cphy_cause |= cphy_cause_fifo_error;
324 return cphy_cause;
325}
326
327static void vsc8244_destroy(struct cphy *cphy)
328{
329 kfree(cphy);
330}
331
332static struct cphy_ops vsc8244_ops = {
333 .destroy = vsc8244_destroy,
334 .reset = vsc8244_reset,
335 .interrupt_enable = vsc8244_intr_enable,
336 .interrupt_disable = vsc8244_intr_disable,
337 .interrupt_clear = vsc8244_intr_clear,
338 .interrupt_handler = vsc8244_intr_handler,
339 .autoneg_enable = vsc8244_autoneg_enable,
340 .autoneg_restart = vsc8244_autoneg_restart,
341 .advertise = vsc8244_advertise,
342 .set_speed_duplex = vsc8244_set_speed_duplex,
343 .get_link_status = vsc8244_get_link_status
344};
345
346static struct cphy* vsc8244_phy_create(adapter_t *adapter, int phy_addr, struct mdio_ops *mdio_ops)
347{
348 struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
349
350 if (!cphy) return NULL;
351
352 cphy_init(cphy, adapter, phy_addr, &vsc8244_ops, mdio_ops);
353
354 return cphy;
355}
356
357
358static int vsc8244_phy_reset(adapter_t* adapter)
359{
360 return 0;
361}
362
363struct gphy t1_vsc8244_ops = {
364 vsc8244_phy_create,
365 vsc8244_phy_reset
366};
367
368
diff --git a/drivers/net/chelsio/vsc8244_reg.h b/drivers/net/chelsio/vsc8244_reg.h
new file mode 100644
index 000000000000..d3c1829055cb
--- /dev/null
+++ b/drivers/net/chelsio/vsc8244_reg.h
@@ -0,0 +1,172 @@
1/* $Date: 2005/11/23 16:28:53 $ $RCSfile: vsc8244_reg.h,v $ $Revision: 1.1 $ */
2#ifndef CHELSIO_MV8E1XXX_H
3#define CHELSIO_MV8E1XXX_H
4
5#ifndef BMCR_SPEED1000
6# define BMCR_SPEED1000 0x40
7#endif
8
9#ifndef ADVERTISE_PAUSE
10# define ADVERTISE_PAUSE 0x400
11#endif
12#ifndef ADVERTISE_PAUSE_ASYM
13# define ADVERTISE_PAUSE_ASYM 0x800
14#endif
15
16/* Gigabit MII registers */
17#define MII_GBMR 1 /* 1000Base-T mode register */
18#define MII_GBCR 9 /* 1000Base-T control register */
19#define MII_GBSR 10 /* 1000Base-T status register */
20
21/* 1000Base-T control register fields */
22#define GBCR_ADV_1000HALF 0x100
23#define GBCR_ADV_1000FULL 0x200
24#define GBCR_PREFER_MASTER 0x400
25#define GBCR_MANUAL_AS_MASTER 0x800
26#define GBCR_MANUAL_CONFIG_ENABLE 0x1000
27
28/* 1000Base-T status register fields */
29#define GBSR_LP_1000HALF 0x400
30#define GBSR_LP_1000FULL 0x800
31#define GBSR_REMOTE_OK 0x1000
32#define GBSR_LOCAL_OK 0x2000
33#define GBSR_LOCAL_MASTER 0x4000
34#define GBSR_MASTER_FAULT 0x8000
35
36/* Vitesse PHY interrupt status bits. */
37#if 0
38#define VSC8244_INTR_JABBER 0x0001
39#define VSC8244_INTR_POLARITY_CHNG 0x0002
40#define VSC8244_INTR_ENG_DETECT_CHNG 0x0010
41#define VSC8244_INTR_DOWNSHIFT 0x0020
42#define VSC8244_INTR_MDI_XOVER_CHNG 0x0040
43#define VSC8244_INTR_FIFO_OVER_UNDER 0x0080
44#define VSC8244_INTR_FALSE_CARRIER 0x0100
45#define VSC8244_INTR_SYMBOL_ERROR 0x0200
46#define VSC8244_INTR_LINK_CHNG 0x0400
47#define VSC8244_INTR_AUTONEG_DONE 0x0800
48#define VSC8244_INTR_PAGE_RECV 0x1000
49#define VSC8244_INTR_DUPLEX_CHNG 0x2000
50#define VSC8244_INTR_SPEED_CHNG 0x4000
51#define VSC8244_INTR_AUTONEG_ERR 0x8000
52#else
53//#define VSC8244_INTR_JABBER 0x0001
54//#define VSC8244_INTR_POLARITY_CHNG 0x0002
55//#define VSC8244_INTR_BIT2 0x0004
56//#define VSC8244_INTR_BIT3 0x0008
57#define VSC8244_INTR_RX_ERR 0x0001
58#define VSC8244_INTR_MASTER_SLAVE 0x0002
59#define VSC8244_INTR_CABLE_IMPAIRED 0x0004
60#define VSC8244_INTR_FALSE_CARRIER 0x0008
61//#define VSC8244_INTR_ENG_DETECT_CHNG 0x0010
62//#define VSC8244_INTR_DOWNSHIFT 0x0020
63//#define VSC8244_INTR_MDI_XOVER_CHNG 0x0040
64//#define VSC8244_INTR_FIFO_OVER_UNDER 0x0080
65#define VSC8244_INTR_BIT4 0x0010
66#define VSC8244_INTR_FIFO_RX 0x0020
67#define VSC8244_INTR_FIFO_OVER_UNDER 0x0040
68#define VSC8244_INTR_LOCK_LOST 0x0080
69//#define VSC8244_INTR_FALSE_CARRIER 0x0100
70//#define VSC8244_INTR_SYMBOL_ERROR 0x0200
71//#define VSC8244_INTR_LINK_CHNG 0x0400
72//#define VSC8244_INTR_AUTONEG_DONE 0x0800
73#define VSC8244_INTR_SYMBOL_ERROR 0x0100
74#define VSC8244_INTR_ENG_DETECT_CHNG 0x0200
75#define VSC8244_INTR_AUTONEG_DONE 0x0400
76#define VSC8244_INTR_AUTONEG_ERR 0x0800
77//#define VSC8244_INTR_PAGE_RECV 0x1000
78//#define VSC8244_INTR_DUPLEX_CHNG 0x2000
79//#define VSC8244_INTR_SPEED_CHNG 0x4000
80//#define VSC8244_INTR_AUTONEG_ERR 0x8000
81#define VSC8244_INTR_DUPLEX_CHNG 0x1000
82#define VSC8244_INTR_LINK_CHNG 0x2000
83#define VSC8244_INTR_SPEED_CHNG 0x4000
84#define VSC8244_INTR_STATUS 0x8000
85#endif
86
87
88/* Vitesse PHY specific registers. */
89#define VSC8244_SPECIFIC_CNTRL_REGISTER 16
90#define VSC8244_SPECIFIC_STATUS_REGISTER 0x1c
91#define VSC8244_INTERRUPT_ENABLE_REGISTER 0x19
92#define VSC8244_INTERRUPT_STATUS_REGISTER 0x1a
93#define VSC8244_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20
94#define VSC8244_RECV_ERR_CNTR_REGISTER 21
95#define VSC8244_RES_REGISTER 22
96#define VSC8244_GLOBAL_STATUS_REGISTER 23
97#define VSC8244_LED_CONTROL_REGISTER 24
98#define VSC8244_MANUAL_LED_OVERRIDE_REGISTER 25
99#define VSC8244_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26
100#define VSC8244_EXT_PHY_SPECIFIC_STATUS_REGISTER 27
101#define VSC8244_VIRTUAL_CABLE_TESTER_REGISTER 28
102#define VSC8244_EXTENDED_ADDR_REGISTER 29
103#define VSC8244_EXTENDED_REGISTER 30
104
105/* PHY specific control register fields */
106#define S_PSCR_MDI_XOVER_MODE 5
107#define M_PSCR_MDI_XOVER_MODE 0x3
108#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
109#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
110
111/* Extended PHY specific control register fields */
112#define S_DOWNSHIFT_ENABLE 8
113#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
114
115#define S_DOWNSHIFT_CNT 9
116#define M_DOWNSHIFT_CNT 0x7
117#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
118#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
119
120/* PHY specific status register fields */
121#define S_PSSR_JABBER 0
122#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
123
124#define S_PSSR_POLARITY 1
125#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
126
127#define S_PSSR_RX_PAUSE 2
128#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
129
130#define S_PSSR_TX_PAUSE 3
131#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
132
133#define S_PSSR_ENERGY_DETECT 4
134#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
135
136#define S_PSSR_DOWNSHIFT_STATUS 5
137#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
138
139#define S_PSSR_MDI 6
140#define V_PSSR_MDI (1 << S_PSSR_MDI)
141
142#define S_PSSR_CABLE_LEN 7
143#define M_PSSR_CABLE_LEN 0x7
144#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
145#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
146
147//#define S_PSSR_LINK 10
148//#define S_PSSR_LINK 13
149#define S_PSSR_LINK 2
150#define V_PSSR_LINK (1 << S_PSSR_LINK)
151
152//#define S_PSSR_STATUS_RESOLVED 11
153//#define S_PSSR_STATUS_RESOLVED 10
154#define S_PSSR_STATUS_RESOLVED 15
155#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
156
157#define S_PSSR_PAGE_RECEIVED 12
158#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
159
160//#define S_PSSR_DUPLEX 13
161//#define S_PSSR_DUPLEX 12
162#define S_PSSR_DUPLEX 5
163#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
164
165//#define S_PSSR_SPEED 14
166//#define S_PSSR_SPEED 14
167#define S_PSSR_SPEED 3
168#define M_PSSR_SPEED 0x3
169#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
170#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
171
172#endif
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index 4ffc9b44a8e1..dec70c2b374a 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -588,10 +588,10 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
588 goto out2; 588 goto out2;
589 } 589 }
590 } 590 }
591 printk(KERN_DEBUG "PP_addr at %x[%x]: 0x%x\n",
592 ioaddr, ADD_PORT, readword(ioaddr, ADD_PORT));
593 591
594 ioaddr &= ~3; 592 ioaddr &= ~3;
593 printk(KERN_DEBUG "PP_addr at %x[%x]: 0x%x\n",
594 ioaddr, ADD_PORT, readword(ioaddr, ADD_PORT));
595 writeword(ioaddr, ADD_PORT, PP_ChipID); 595 writeword(ioaddr, ADD_PORT, PP_ChipID);
596 596
597 tmp = readword(ioaddr, DATA_PORT); 597 tmp = readword(ioaddr, DATA_PORT);
diff --git a/drivers/net/defxx.c b/drivers/net/defxx.c
index 8f514cc0debd..dc3ab3b5c8cb 100644
--- a/drivers/net/defxx.c
+++ b/drivers/net/defxx.c
@@ -192,6 +192,7 @@
192 * 04 Aug 2003 macro Converted to the DMA API. 192 * 04 Aug 2003 macro Converted to the DMA API.
193 * 14 Aug 2004 macro Fix device names reported. 193 * 14 Aug 2004 macro Fix device names reported.
194 * 14 Jun 2005 macro Use irqreturn_t. 194 * 14 Jun 2005 macro Use irqreturn_t.
195 * 23 Oct 2006 macro Big-endian host support.
195 */ 196 */
196 197
197/* Include files */ 198/* Include files */
@@ -218,8 +219,8 @@
218 219
219/* Version information string should be updated prior to each new release! */ 220/* Version information string should be updated prior to each new release! */
220#define DRV_NAME "defxx" 221#define DRV_NAME "defxx"
221#define DRV_VERSION "v1.08" 222#define DRV_VERSION "v1.09"
222#define DRV_RELDATE "2005/06/14" 223#define DRV_RELDATE "2006/10/23"
223 224
224static char version[] __devinitdata = 225static char version[] __devinitdata =
225 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 226 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
@@ -859,6 +860,7 @@ static int __devinit dfx_driver_init(struct net_device *dev,
859 print_name); 860 print_name);
860 return(DFX_K_FAILURE); 861 return(DFX_K_FAILURE);
861 } 862 }
863 data = cpu_to_le32(data);
862 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32)); 864 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
863 865
864 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 866 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
@@ -867,6 +869,7 @@ static int __devinit dfx_driver_init(struct net_device *dev,
867 print_name); 869 print_name);
868 return(DFX_K_FAILURE); 870 return(DFX_K_FAILURE);
869 } 871 }
872 data = cpu_to_le32(data);
870 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16)); 873 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
871 874
872 /* 875 /*
@@ -1085,27 +1088,23 @@ static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1085 } 1088 }
1086 1089
1087 /* 1090 /*
1088 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state 1091 * Set the base address of Descriptor Block and bring adapter
1092 * to DMA_AVAILABLE state.
1089 * 1093 *
1090 * Note: We also set the literal and data swapping requirements in this 1094 * Note: We also set the literal and data swapping requirements
1091 * command. Since this driver presently runs on Intel platforms 1095 * in this command.
1092 * which are Little Endian, we'll tell the adapter to byte swap
1093 * data only. This code will need to change when we support
1094 * Big Endian systems (eg. PowerPC).
1095 * 1096 *
1096 * Assumption: 32-bit physical address of descriptor block is 8Kbyte 1097 * Assumption: 32-bit physical address of descriptor block
1097 * aligned. That is, bits 0-12 of the address must be zero. 1098 * is 8Kbyte aligned.
1098 */ 1099 */
1099 1100 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
1100 if (dfx_hw_port_ctrl_req(bp, 1101 (u32)(bp->descr_block_phys |
1101 PI_PCTRL_M_INIT, 1102 PI_PDATA_A_INIT_M_BSWAP_INIT),
1102 (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA), 1103 0, NULL) != DFX_K_SUCCESS) {
1103 0, 1104 printk("%s: Could not set descriptor block address!\n",
1104 NULL) != DFX_K_SUCCESS) 1105 bp->dev->name);
1105 { 1106 return DFX_K_FAILURE;
1106 printk("%s: Could not set descriptor block address!\n", bp->dev->name); 1107 }
1107 return(DFX_K_FAILURE);
1108 }
1109 1108
1110 /* Set transmit flush timeout value */ 1109 /* Set transmit flush timeout value */
1111 1110
diff --git a/drivers/net/defxx.h b/drivers/net/defxx.h
index 8b1e9a11ca21..2ce8f97253eb 100644
--- a/drivers/net/defxx.h
+++ b/drivers/net/defxx.h
@@ -25,6 +25,7 @@
25 * macros to DEFXX.C. 25 * macros to DEFXX.C.
26 * 12-Sep-96 LVS Removed packet request header pointers. 26 * 12-Sep-96 LVS Removed packet request header pointers.
27 * 04 Aug 2003 macro Converted to the DMA API. 27 * 04 Aug 2003 macro Converted to the DMA API.
28 * 23 Oct 2006 macro Big-endian host support.
28 */ 29 */
29 30
30#ifndef _DEFXX_H_ 31#ifndef _DEFXX_H_
@@ -1344,7 +1345,7 @@ typedef struct
1344 1345
1345/* Register definition structures are defined for both big and little endian systems */ 1346/* Register definition structures are defined for both big and little endian systems */
1346 1347
1347#ifndef BIG_ENDIAN 1348#ifndef __BIG_ENDIAN
1348 1349
1349/* Little endian format of Type 1 Producer register */ 1350/* Little endian format of Type 1 Producer register */
1350 1351
@@ -1402,7 +1403,11 @@ typedef union
1402 } index; 1403 } index;
1403 } PI_TYPE_2_CONSUMER; 1404 } PI_TYPE_2_CONSUMER;
1404 1405
1405#else 1406/* Define swapping required by DMA transfers. */
1407#define PI_PDATA_A_INIT_M_BSWAP_INIT \
1408 (PI_PDATA_A_INIT_M_BSWAP_DATA)
1409
1410#else /* __BIG_ENDIAN */
1406 1411
1407/* Big endian format of Type 1 Producer register */ 1412/* Big endian format of Type 1 Producer register */
1408 1413
@@ -1460,7 +1465,11 @@ typedef union
1460 } index; 1465 } index;
1461 } PI_TYPE_2_CONSUMER; 1466 } PI_TYPE_2_CONSUMER;
1462 1467
1463#endif /* #ifndef BIG_ENDIAN */ 1468/* Define swapping required by DMA transfers. */
1469#define PI_PDATA_A_INIT_M_BSWAP_INIT \
1470 (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
1471
1472#endif /* __BIG_ENDIAN */
1464 1473
1465/* Define EISA controller register offsets */ 1474/* Define EISA controller register offsets */
1466 1475
diff --git a/drivers/net/depca.c b/drivers/net/depca.c
index f87f6e3dc721..5113eef755b9 100644
--- a/drivers/net/depca.c
+++ b/drivers/net/depca.c
@@ -1252,24 +1252,22 @@ static void set_multicast_list(struct net_device *dev)
1252 struct depca_private *lp = (struct depca_private *) dev->priv; 1252 struct depca_private *lp = (struct depca_private *) dev->priv;
1253 u_long ioaddr = dev->base_addr; 1253 u_long ioaddr = dev->base_addr;
1254 1254
1255 if (dev) { 1255 netif_stop_queue(dev);
1256 netif_stop_queue(dev); 1256 while (lp->tx_old != lp->tx_new); /* Wait for the ring to empty */
1257 while (lp->tx_old != lp->tx_new); /* Wait for the ring to empty */
1258
1259 STOP_DEPCA; /* Temporarily stop the depca. */
1260 depca_init_ring(dev); /* Initialize the descriptor rings */
1261 1257
1262 if (dev->flags & IFF_PROMISC) { /* Set promiscuous mode */ 1258 STOP_DEPCA; /* Temporarily stop the depca. */
1263 lp->init_block.mode |= PROM; 1259 depca_init_ring(dev); /* Initialize the descriptor rings */
1264 } else {
1265 SetMulticastFilter(dev);
1266 lp->init_block.mode &= ~PROM; /* Unset promiscuous mode */
1267 }
1268 1260
1269 LoadCSRs(dev); /* Reload CSR3 */ 1261 if (dev->flags & IFF_PROMISC) { /* Set promiscuous mode */
1270 InitRestartDepca(dev); /* Resume normal operation. */ 1262 lp->init_block.mode |= PROM;
1271 netif_start_queue(dev); /* Unlock the TX ring */ 1263 } else {
1264 SetMulticastFilter(dev);
1265 lp->init_block.mode &= ~PROM; /* Unset promiscuous mode */
1272 } 1266 }
1267
1268 LoadCSRs(dev); /* Reload CSR3 */
1269 InitRestartDepca(dev); /* Resume normal operation. */
1270 netif_start_queue(dev); /* Unlock the TX ring */
1273} 1271}
1274 1272
1275/* 1273/*
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index e7737d02bb05..03bf164f9e8d 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -1215,7 +1215,7 @@ static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb
1215* the literal in the instruction before the code is loaded, the 1215* the literal in the instruction before the code is loaded, the
1216* driver can change the algorithm. 1216* driver can change the algorithm.
1217* 1217*
1218* INTDELAY - This loads the dead-man timer with its inital value. 1218* INTDELAY - This loads the dead-man timer with its initial value.
1219* When this timer expires the interrupt is asserted, and the 1219* When this timer expires the interrupt is asserted, and the
1220* timer is reset each time a new packet is received. (see 1220* timer is reset each time a new packet is received. (see
1221* BUNDLEMAX below to set the limit on number of chained packets) 1221* BUNDLEMAX below to set the limit on number of chained packets)
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 7ecce438d258..f091042b146e 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -59,6 +59,9 @@
59#include <linux/capability.h> 59#include <linux/capability.h>
60#include <linux/in.h> 60#include <linux/in.h>
61#include <linux/ip.h> 61#include <linux/ip.h>
62#ifdef NETIF_F_TSO6
63#include <linux/ipv6.h>
64#endif
62#include <linux/tcp.h> 65#include <linux/tcp.h>
63#include <linux/udp.h> 66#include <linux/udp.h>
64#include <net/pkt_sched.h> 67#include <net/pkt_sched.h>
@@ -254,6 +257,17 @@ struct e1000_adapter {
254 spinlock_t tx_queue_lock; 257 spinlock_t tx_queue_lock;
255#endif 258#endif
256 atomic_t irq_sem; 259 atomic_t irq_sem;
260 unsigned int detect_link;
261 unsigned int total_tx_bytes;
262 unsigned int total_tx_packets;
263 unsigned int total_rx_bytes;
264 unsigned int total_rx_packets;
265 /* Interrupt Throttle Rate */
266 uint32_t itr;
267 uint32_t itr_setting;
268 uint16_t tx_itr;
269 uint16_t rx_itr;
270
257 struct work_struct reset_task; 271 struct work_struct reset_task;
258 uint8_t fc_autoneg; 272 uint8_t fc_autoneg;
259 273
@@ -262,6 +276,7 @@ struct e1000_adapter {
262 276
263 /* TX */ 277 /* TX */
264 struct e1000_tx_ring *tx_ring; /* One per active queue */ 278 struct e1000_tx_ring *tx_ring; /* One per active queue */
279 unsigned int restart_queue;
265 unsigned long tx_queue_len; 280 unsigned long tx_queue_len;
266 uint32_t txd_cmd; 281 uint32_t txd_cmd;
267 uint32_t tx_int_delay; 282 uint32_t tx_int_delay;
@@ -310,8 +325,6 @@ struct e1000_adapter {
310 uint64_t gorcl_old; 325 uint64_t gorcl_old;
311 uint16_t rx_ps_bsize0; 326 uint16_t rx_ps_bsize0;
312 327
313 /* Interrupt Throttle Rate */
314 uint32_t itr;
315 328
316 /* OS defined structs */ 329 /* OS defined structs */
317 struct net_device *netdev; 330 struct net_device *netdev;
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index c564adbd669b..da459f7177c6 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -85,6 +85,7 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
85 { "tx_single_coll_ok", E1000_STAT(stats.scc) }, 85 { "tx_single_coll_ok", E1000_STAT(stats.scc) },
86 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) }, 86 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
87 { "tx_timeout_count", E1000_STAT(tx_timeout_count) }, 87 { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
88 { "tx_restart_queue", E1000_STAT(restart_queue) },
88 { "rx_long_length_errors", E1000_STAT(stats.roc) }, 89 { "rx_long_length_errors", E1000_STAT(stats.roc) },
89 { "rx_short_length_errors", E1000_STAT(stats.ruc) }, 90 { "rx_short_length_errors", E1000_STAT(stats.ruc) },
90 { "rx_align_errors", E1000_STAT(stats.algnerrc) }, 91 { "rx_align_errors", E1000_STAT(stats.algnerrc) },
@@ -133,9 +134,7 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
133 134
134 if (hw->autoneg == 1) { 135 if (hw->autoneg == 1) {
135 ecmd->advertising |= ADVERTISED_Autoneg; 136 ecmd->advertising |= ADVERTISED_Autoneg;
136
137 /* the e1000 autoneg seems to match ethtool nicely */ 137 /* the e1000 autoneg seems to match ethtool nicely */
138
139 ecmd->advertising |= hw->autoneg_advertised; 138 ecmd->advertising |= hw->autoneg_advertised;
140 } 139 }
141 140
@@ -285,7 +284,7 @@ e1000_set_pauseparam(struct net_device *netdev,
285 e1000_reset(adapter); 284 e1000_reset(adapter);
286 } else 285 } else
287 retval = ((hw->media_type == e1000_media_type_fiber) ? 286 retval = ((hw->media_type == e1000_media_type_fiber) ?
288 e1000_setup_link(hw) : e1000_force_mac_fc(hw)); 287 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
289 288
290 clear_bit(__E1000_RESETTING, &adapter->flags); 289 clear_bit(__E1000_RESETTING, &adapter->flags);
291 return retval; 290 return retval;
@@ -350,6 +349,13 @@ e1000_set_tso(struct net_device *netdev, uint32_t data)
350 else 349 else
351 netdev->features &= ~NETIF_F_TSO; 350 netdev->features &= ~NETIF_F_TSO;
352 351
352#ifdef NETIF_F_TSO6
353 if (data)
354 netdev->features |= NETIF_F_TSO6;
355 else
356 netdev->features &= ~NETIF_F_TSO6;
357#endif
358
353 DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); 359 DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled");
354 adapter->tso_force = TRUE; 360 adapter->tso_force = TRUE;
355 return 0; 361 return 0;
@@ -774,7 +780,7 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
774 /* The status register is Read Only, so a write should fail. 780 /* The status register is Read Only, so a write should fail.
775 * Some bits that get toggled are ignored. 781 * Some bits that get toggled are ignored.
776 */ 782 */
777 switch (adapter->hw.mac_type) { 783 switch (adapter->hw.mac_type) {
778 /* there are several bits on newer hardware that are r/w */ 784 /* there are several bits on newer hardware that are r/w */
779 case e1000_82571: 785 case e1000_82571:
780 case e1000_82572: 786 case e1000_82572:
@@ -802,12 +808,14 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
802 } 808 }
803 /* restore previous status */ 809 /* restore previous status */
804 E1000_WRITE_REG(&adapter->hw, STATUS, before); 810 E1000_WRITE_REG(&adapter->hw, STATUS, before);
811
805 if (adapter->hw.mac_type != e1000_ich8lan) { 812 if (adapter->hw.mac_type != e1000_ich8lan) {
806 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); 813 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
807 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); 814 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
808 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); 815 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
809 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); 816 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
810 } 817 }
818
811 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); 819 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
812 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); 820 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
813 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF); 821 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
@@ -820,8 +828,9 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
820 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF); 828 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
821 829
822 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); 830 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
831
823 before = (adapter->hw.mac_type == e1000_ich8lan ? 832 before = (adapter->hw.mac_type == e1000_ich8lan ?
824 0x06C3B33E : 0x06DFB3FE); 833 0x06C3B33E : 0x06DFB3FE);
825 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB); 834 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
826 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); 835 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
827 836
@@ -834,10 +843,10 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
834 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 843 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
835 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); 844 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
836 value = (adapter->hw.mac_type == e1000_ich8lan ? 845 value = (adapter->hw.mac_type == e1000_ich8lan ?
837 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES); 846 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
838 for (i = 0; i < value; i++) { 847 for (i = 0; i < value; i++) {
839 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, 848 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
840 0xFFFFFFFF); 849 0xFFFFFFFF);
841 } 850 }
842 851
843 } else { 852 } else {
@@ -883,8 +892,7 @@ e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
883} 892}
884 893
885static irqreturn_t 894static irqreturn_t
886e1000_test_intr(int irq, 895e1000_test_intr(int irq, void *data)
887 void *data)
888{ 896{
889 struct net_device *netdev = (struct net_device *) data; 897 struct net_device *netdev = (struct net_device *) data;
890 struct e1000_adapter *adapter = netdev_priv(netdev); 898 struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -905,11 +913,11 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
905 913
906 /* NOTE: we don't test MSI interrupts here, yet */ 914 /* NOTE: we don't test MSI interrupts here, yet */
907 /* Hook up test interrupt handler just for this test */ 915 /* Hook up test interrupt handler just for this test */
908 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, 916 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
909 netdev->name, netdev)) 917 netdev))
910 shared_int = FALSE; 918 shared_int = FALSE;
911 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, 919 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
912 netdev->name, netdev)) { 920 netdev->name, netdev)) {
913 *data = 1; 921 *data = 1;
914 return -1; 922 return -1;
915 } 923 }
@@ -925,6 +933,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
925 933
926 if (adapter->hw.mac_type == e1000_ich8lan && i == 8) 934 if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
927 continue; 935 continue;
936
928 /* Interrupt to test */ 937 /* Interrupt to test */
929 mask = 1 << i; 938 mask = 1 << i;
930 939
@@ -1674,7 +1683,7 @@ e1000_diag_test(struct net_device *netdev,
1674 if (e1000_link_test(adapter, &data[4])) 1683 if (e1000_link_test(adapter, &data[4]))
1675 eth_test->flags |= ETH_TEST_FL_FAILED; 1684 eth_test->flags |= ETH_TEST_FL_FAILED;
1676 1685
1677 /* Offline tests aren't run; pass by default */ 1686 /* Online tests aren't run; pass by default */
1678 data[0] = 0; 1687 data[0] = 0;
1679 data[1] = 0; 1688 data[1] = 0;
1680 data[2] = 0; 1689 data[2] = 0;
@@ -1717,6 +1726,7 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter, struct ethtool_wol
1717 retval = 0; 1726 retval = 0;
1718 break; 1727 break;
1719 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1728 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1729 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1720 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1730 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1721 /* quad port adapters only support WoL on port A */ 1731 /* quad port adapters only support WoL on port A */
1722 if (!adapter->quad_port_a) { 1732 if (!adapter->quad_port_a) {
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 65077f39da69..3655d902b0bd 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -385,6 +385,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
385 case E1000_DEV_ID_82571EB_FIBER: 385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES: 386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_QUAD_COPPER: 387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
388 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
388 hw->mac_type = e1000_82571; 389 hw->mac_type = e1000_82571;
389 break; 390 break;
390 case E1000_DEV_ID_82572EI_COPPER: 391 case E1000_DEV_ID_82572EI_COPPER:
@@ -408,6 +409,8 @@ e1000_set_mac_type(struct e1000_hw *hw)
408 case E1000_DEV_ID_ICH8_IGP_AMT: 409 case E1000_DEV_ID_ICH8_IGP_AMT:
409 case E1000_DEV_ID_ICH8_IGP_C: 410 case E1000_DEV_ID_ICH8_IGP_C:
410 case E1000_DEV_ID_ICH8_IFE: 411 case E1000_DEV_ID_ICH8_IFE:
412 case E1000_DEV_ID_ICH8_IFE_GT:
413 case E1000_DEV_ID_ICH8_IFE_G:
411 case E1000_DEV_ID_ICH8_IGP_M: 414 case E1000_DEV_ID_ICH8_IGP_M:
412 hw->mac_type = e1000_ich8lan; 415 hw->mac_type = e1000_ich8lan;
413 break; 416 break;
@@ -2367,6 +2370,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2367 2370
2368 /* Need to reset the PHY or these changes will be ignored */ 2371 /* Need to reset the PHY or these changes will be ignored */
2369 mii_ctrl_reg |= MII_CR_RESET; 2372 mii_ctrl_reg |= MII_CR_RESET;
2373
2370 /* Disable MDI-X support for 10/100 */ 2374 /* Disable MDI-X support for 10/100 */
2371 } else if (hw->phy_type == e1000_phy_ife) { 2375 } else if (hw->phy_type == e1000_phy_ife) {
2372 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 2376 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
@@ -2379,6 +2383,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2379 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 2383 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2380 if (ret_val) 2384 if (ret_val)
2381 return ret_val; 2385 return ret_val;
2386
2382 } else { 2387 } else {
2383 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2388 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2384 * forced whenever speed or duplex are forced. 2389 * forced whenever speed or duplex are forced.
@@ -3868,7 +3873,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3868* 3873*
3869* hw - Struct containing variables accessed by shared code 3874* hw - Struct containing variables accessed by shared code
3870* 3875*
3871* Sets bit 15 of the MII Control regiser 3876* Sets bit 15 of the MII Control register
3872******************************************************************************/ 3877******************************************************************************/
3873int32_t 3878int32_t
3874e1000_phy_reset(struct e1000_hw *hw) 3879e1000_phy_reset(struct e1000_hw *hw)
@@ -3940,14 +3945,15 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3940 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3945 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3941 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3946 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3942 3947
3943 /* Write VR power-down enable */ 3948 /* Write VR power-down enable - bits 9:8 should be 10b */
3944 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3945 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data | 3950 phy_data |= (1 << 9);
3946 IGP3_VR_CTRL_MODE_SHUT); 3951 phy_data &= ~(1 << 8);
3952 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3947 3953
3948 /* Read it back and test */ 3954 /* Read it back and test */
3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3955 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3950 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry) 3956 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3951 break; 3957 break;
3952 3958
3953 /* Issue PHY reset and repeat at most one more time */ 3959 /* Issue PHY reset and repeat at most one more time */
@@ -4549,7 +4555,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4549 case e1000_ich8lan: 4555 case e1000_ich8lan:
4550 { 4556 {
4551 int32_t i = 0; 4557 int32_t i = 0;
4552 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); 4558 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4553 4559
4554 eeprom->type = e1000_eeprom_ich8; 4560 eeprom->type = e1000_eeprom_ich8;
4555 eeprom->use_eerd = FALSE; 4561 eeprom->use_eerd = FALSE;
@@ -4565,12 +4571,14 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4565 } 4571 }
4566 } 4572 }
4567 4573
4568 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) * 4574 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4569 ICH8_FLASH_SECTOR_SIZE; 4575 ICH_FLASH_SECTOR_SIZE;
4576
4577 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4578 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4579
4580 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4570 4581
4571 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4572 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4573 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4574 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4582 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4575 4583
4576 break; 4584 break;
@@ -5620,8 +5628,8 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5620 * signature is valid. We want to do this after the write 5628 * signature is valid. We want to do this after the write
5621 * has completed so that we don't mark the segment valid 5629 * has completed so that we don't mark the segment valid
5622 * while the write is still in progress */ 5630 * while the write is still in progress */
5623 if (i == E1000_ICH8_NVM_SIG_WORD) 5631 if (i == E1000_ICH_NVM_SIG_WORD)
5624 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte; 5632 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5625 5633
5626 error = e1000_verify_write_ich8_byte(hw, 5634 error = e1000_verify_write_ich8_byte(hw,
5627 (i << 1) + new_bank_offset + 1, high_byte); 5635 (i << 1) + new_bank_offset + 1, high_byte);
@@ -5643,18 +5651,18 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5643 * erase as well since these bits are 11 to start with 5651 * erase as well since these bits are 11 to start with
5644 * and we need to change bit 14 to 0b */ 5652 * and we need to change bit 14 to 0b */
5645 e1000_read_ich8_byte(hw, 5653 e1000_read_ich8_byte(hw,
5646 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5654 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5647 &high_byte); 5655 &high_byte);
5648 high_byte &= 0xBF; 5656 high_byte &= 0xBF;
5649 error = e1000_verify_write_ich8_byte(hw, 5657 error = e1000_verify_write_ich8_byte(hw,
5650 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); 5658 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5651 /* And invalidate the previously valid segment by setting 5659 /* And invalidate the previously valid segment by setting
5652 * its signature word (0x13) high_byte to 0b. This can be 5660 * its signature word (0x13) high_byte to 0b. This can be
5653 * done without an erase because flash erase sets all bits 5661 * done without an erase because flash erase sets all bits
5654 * to 1's. We can write 1's to 0's without an erase */ 5662 * to 1's. We can write 1's to 0's without an erase */
5655 if (error == E1000_SUCCESS) { 5663 if (error == E1000_SUCCESS) {
5656 error = e1000_verify_write_ich8_byte(hw, 5664 error = e1000_verify_write_ich8_byte(hw,
5657 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); 5665 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5658 } 5666 }
5659 5667
5660 /* Clear the now not used entry in the cache */ 5668 /* Clear the now not used entry in the cache */
@@ -5841,6 +5849,7 @@ e1000_mta_set(struct e1000_hw *hw,
5841 hash_reg = (hash_value >> 5) & 0x7F; 5849 hash_reg = (hash_value >> 5) & 0x7F;
5842 if (hw->mac_type == e1000_ich8lan) 5850 if (hw->mac_type == e1000_ich8lan)
5843 hash_reg &= 0x1F; 5851 hash_reg &= 0x1F;
5852
5844 hash_bit = hash_value & 0x1F; 5853 hash_bit = hash_value & 0x1F;
5845 5854
5846 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5855 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -6026,6 +6035,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6026 else 6035 else
6027 eeprom_data = ID_LED_DEFAULT; 6036 eeprom_data = ID_LED_DEFAULT;
6028 } 6037 }
6038
6029 for (i = 0; i < 4; i++) { 6039 for (i = 0; i < 4; i++) {
6030 temp = (eeprom_data >> (i << 2)) & led_mask; 6040 temp = (eeprom_data >> (i << 2)) & led_mask;
6031 switch (temp) { 6041 switch (temp) {
@@ -8486,7 +8496,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8486 8496
8487 DEBUGFUNC("e1000_ich8_cycle_init"); 8497 DEBUGFUNC("e1000_ich8_cycle_init");
8488 8498
8489 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8499 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8490 8500
8491 /* May be check the Flash Des Valid bit in Hw status */ 8501 /* May be check the Flash Des Valid bit in Hw status */
8492 if (hsfsts.hsf_status.fldesvalid == 0) { 8502 if (hsfsts.hsf_status.fldesvalid == 0) {
@@ -8499,7 +8509,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8499 hsfsts.hsf_status.flcerr = 1; 8509 hsfsts.hsf_status.flcerr = 1;
8500 hsfsts.hsf_status.dael = 1; 8510 hsfsts.hsf_status.dael = 1;
8501 8511
8502 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); 8512 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8503 8513
8504 /* Either we should have a hardware SPI cycle in progress bit to check 8514 /* Either we should have a hardware SPI cycle in progress bit to check
8505 * against, in order to start a new cycle or FDONE bit should be changed 8515 * against, in order to start a new cycle or FDONE bit should be changed
@@ -8514,13 +8524,13 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8514 /* There is no cycle running at present, so we can start a cycle */ 8524 /* There is no cycle running at present, so we can start a cycle */
8515 /* Begin by setting Flash Cycle Done. */ 8525 /* Begin by setting Flash Cycle Done. */
8516 hsfsts.hsf_status.flcdone = 1; 8526 hsfsts.hsf_status.flcdone = 1;
8517 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); 8527 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8518 error = E1000_SUCCESS; 8528 error = E1000_SUCCESS;
8519 } else { 8529 } else {
8520 /* otherwise poll for sometime so the current cycle has a chance 8530 /* otherwise poll for sometime so the current cycle has a chance
8521 * to end before giving up. */ 8531 * to end before giving up. */
8522 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) { 8532 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8523 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8533 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8524 if (hsfsts.hsf_status.flcinprog == 0) { 8534 if (hsfsts.hsf_status.flcinprog == 0) {
8525 error = E1000_SUCCESS; 8535 error = E1000_SUCCESS;
8526 break; 8536 break;
@@ -8531,7 +8541,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8531 /* Successful in waiting for previous cycle to timeout, 8541 /* Successful in waiting for previous cycle to timeout,
8532 * now set the Flash Cycle Done. */ 8542 * now set the Flash Cycle Done. */
8533 hsfsts.hsf_status.flcdone = 1; 8543 hsfsts.hsf_status.flcdone = 1;
8534 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); 8544 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8535 } else { 8545 } else {
8536 DEBUGOUT("Flash controller busy, cannot get access"); 8546 DEBUGOUT("Flash controller busy, cannot get access");
8537 } 8547 }
@@ -8553,13 +8563,13 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8553 uint32_t i = 0; 8563 uint32_t i = 0;
8554 8564
8555 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 8565 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8556 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8566 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8557 hsflctl.hsf_ctrl.flcgo = 1; 8567 hsflctl.hsf_ctrl.flcgo = 1;
8558 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8568 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8559 8569
8560 /* wait till FDONE bit is set to 1 */ 8570 /* wait till FDONE bit is set to 1 */
8561 do { 8571 do {
8562 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8572 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8563 if (hsfsts.hsf_status.flcdone == 1) 8573 if (hsfsts.hsf_status.flcdone == 1)
8564 break; 8574 break;
8565 udelay(1); 8575 udelay(1);
@@ -8593,10 +8603,10 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8593 DEBUGFUNC("e1000_read_ich8_data"); 8603 DEBUGFUNC("e1000_read_ich8_data");
8594 8604
8595 if (size < 1 || size > 2 || data == 0x0 || 8605 if (size < 1 || size > 2 || data == 0x0 ||
8596 index > ICH8_FLASH_LINEAR_ADDR_MASK) 8606 index > ICH_FLASH_LINEAR_ADDR_MASK)
8597 return error; 8607 return error;
8598 8608
8599 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + 8609 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8600 hw->flash_base_addr; 8610 hw->flash_base_addr;
8601 8611
8602 do { 8612 do {
@@ -8606,25 +8616,25 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8606 if (error != E1000_SUCCESS) 8616 if (error != E1000_SUCCESS)
8607 break; 8617 break;
8608 8618
8609 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8619 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8610 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 8620 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8611 hsflctl.hsf_ctrl.fldbcount = size - 1; 8621 hsflctl.hsf_ctrl.fldbcount = size - 1;
8612 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ; 8622 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8613 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8623 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8614 8624
8615 /* Write the last 24 bits of index into Flash Linear address field in 8625 /* Write the last 24 bits of index into Flash Linear address field in
8616 * Flash Address */ 8626 * Flash Address */
8617 /* TODO: TBD maybe check the index against the size of flash */ 8627 /* TODO: TBD maybe check the index against the size of flash */
8618 8628
8619 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8629 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8620 8630
8621 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); 8631 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8622 8632
8623 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole 8633 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8624 * sequence a few more times, else read in (shift in) the Flash Data0, 8634 * sequence a few more times, else read in (shift in) the Flash Data0,
8625 * the order is least significant byte first msb to lsb */ 8635 * the order is least significant byte first msb to lsb */
8626 if (error == E1000_SUCCESS) { 8636 if (error == E1000_SUCCESS) {
8627 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0); 8637 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8628 if (size == 1) { 8638 if (size == 1) {
8629 *data = (uint8_t)(flash_data & 0x000000FF); 8639 *data = (uint8_t)(flash_data & 0x000000FF);
8630 } else if (size == 2) { 8640 } else if (size == 2) {
@@ -8634,9 +8644,9 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8634 } else { 8644 } else {
8635 /* If we've gotten here, then things are probably completely hosed, 8645 /* If we've gotten here, then things are probably completely hosed,
8636 * but if the error condition is detected, it won't hurt to give 8646 * but if the error condition is detected, it won't hurt to give
8637 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. 8647 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8638 */ 8648 */
8639 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8649 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8640 if (hsfsts.hsf_status.flcerr == 1) { 8650 if (hsfsts.hsf_status.flcerr == 1) {
8641 /* Repeat for some time before giving up. */ 8651 /* Repeat for some time before giving up. */
8642 continue; 8652 continue;
@@ -8645,7 +8655,7 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8645 break; 8655 break;
8646 } 8656 }
8647 } 8657 }
8648 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); 8658 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8649 8659
8650 return error; 8660 return error;
8651} 8661}
@@ -8672,10 +8682,10 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8672 DEBUGFUNC("e1000_write_ich8_data"); 8682 DEBUGFUNC("e1000_write_ich8_data");
8673 8683
8674 if (size < 1 || size > 2 || data > size * 0xff || 8684 if (size < 1 || size > 2 || data > size * 0xff ||
8675 index > ICH8_FLASH_LINEAR_ADDR_MASK) 8685 index > ICH_FLASH_LINEAR_ADDR_MASK)
8676 return error; 8686 return error;
8677 8687
8678 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + 8688 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8679 hw->flash_base_addr; 8689 hw->flash_base_addr;
8680 8690
8681 do { 8691 do {
@@ -8685,34 +8695,34 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8685 if (error != E1000_SUCCESS) 8695 if (error != E1000_SUCCESS)
8686 break; 8696 break;
8687 8697
8688 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8698 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8689 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 8699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8690 hsflctl.hsf_ctrl.fldbcount = size -1; 8700 hsflctl.hsf_ctrl.fldbcount = size -1;
8691 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE; 8701 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8692 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8702 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8693 8703
8694 /* Write the last 24 bits of index into Flash Linear address field in 8704 /* Write the last 24 bits of index into Flash Linear address field in
8695 * Flash Address */ 8705 * Flash Address */
8696 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8706 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8697 8707
8698 if (size == 1) 8708 if (size == 1)
8699 flash_data = (uint32_t)data & 0x00FF; 8709 flash_data = (uint32_t)data & 0x00FF;
8700 else 8710 else
8701 flash_data = (uint32_t)data; 8711 flash_data = (uint32_t)data;
8702 8712
8703 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data); 8713 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8704 8714
8705 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole 8715 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8706 * sequence a few more times else done */ 8716 * sequence a few more times else done */
8707 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); 8717 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8708 if (error == E1000_SUCCESS) { 8718 if (error == E1000_SUCCESS) {
8709 break; 8719 break;
8710 } else { 8720 } else {
8711 /* If we're here, then things are most likely completely hosed, 8721 /* If we're here, then things are most likely completely hosed,
8712 * but if the error condition is detected, it won't hurt to give 8722 * but if the error condition is detected, it won't hurt to give
8713 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. 8723 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8714 */ 8724 */
8715 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8725 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8716 if (hsfsts.hsf_status.flcerr == 1) { 8726 if (hsfsts.hsf_status.flcerr == 1) {
8717 /* Repeat for some time before giving up. */ 8727 /* Repeat for some time before giving up. */
8718 continue; 8728 continue;
@@ -8721,7 +8731,7 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8721 break; 8731 break;
8722 } 8732 }
8723 } 8733 }
8724 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); 8734 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8725 8735
8726 return error; 8736 return error;
8727} 8737}
@@ -8840,7 +8850,7 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8840 int32_t j = 0; 8850 int32_t j = 0;
8841 int32_t error_flag = 0; 8851 int32_t error_flag = 0;
8842 8852
8843 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8853 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8844 8854
8845 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ 8855 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8846 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 8856 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
@@ -8853,19 +8863,14 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8853 * 11: The Hw sector size is 64K bytes */ 8863 * 11: The Hw sector size is 64K bytes */
8854 if (hsfsts.hsf_status.berasesz == 0x0) { 8864 if (hsfsts.hsf_status.berasesz == 0x0) {
8855 /* Hw sector size 256 */ 8865 /* Hw sector size 256 */
8856 sub_sector_size = ICH8_FLASH_SEG_SIZE_256; 8866 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8857 bank_size = ICH8_FLASH_SECTOR_SIZE; 8867 bank_size = ICH_FLASH_SECTOR_SIZE;
8858 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; 8868 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8859 } else if (hsfsts.hsf_status.berasesz == 0x1) { 8869 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8860 bank_size = ICH8_FLASH_SEG_SIZE_4K; 8870 bank_size = ICH_FLASH_SEG_SIZE_4K;
8861 iteration = 1;
8862 } else if (hw->mac_type != e1000_ich8lan &&
8863 hsfsts.hsf_status.berasesz == 0x2) {
8864 /* 8K erase size invalid for ICH8 - added in for ICH9 */
8865 bank_size = ICH9_FLASH_SEG_SIZE_8K;
8866 iteration = 1; 8871 iteration = 1;
8867 } else if (hsfsts.hsf_status.berasesz == 0x3) { 8872 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8868 bank_size = ICH8_FLASH_SEG_SIZE_64K; 8873 bank_size = ICH_FLASH_SEG_SIZE_64K;
8869 iteration = 1; 8874 iteration = 1;
8870 } else { 8875 } else {
8871 return error; 8876 return error;
@@ -8883,9 +8888,9 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8883 8888
8884 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash 8889 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8885 * Control */ 8890 * Control */
8886 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8891 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8887 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE; 8892 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8888 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8893 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8889 8894
8890 /* Write the last 24 bits of an index within the block into Flash 8895 /* Write the last 24 bits of an index within the block into Flash
8891 * Linear address field in Flash Address. This probably needs to 8896 * Linear address field in Flash Address. This probably needs to
@@ -8893,17 +8898,17 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8893 * the software bank size (4, 8 or 64 KBytes) */ 8898 * the software bank size (4, 8 or 64 KBytes) */
8894 flash_linear_address = bank * bank_size + j * sub_sector_size; 8899 flash_linear_address = bank * bank_size + j * sub_sector_size;
8895 flash_linear_address += hw->flash_base_addr; 8900 flash_linear_address += hw->flash_base_addr;
8896 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK; 8901 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8897 8902
8898 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8903 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8899 8904
8900 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_ERASE_TIMEOUT); 8905 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8901 /* Check if FCERR is set to 1. If 1, clear it and try the whole 8906 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8902 * sequence a few more times else Done */ 8907 * sequence a few more times else Done */
8903 if (error == E1000_SUCCESS) { 8908 if (error == E1000_SUCCESS) {
8904 break; 8909 break;
8905 } else { 8910 } else {
8906 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8911 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8907 if (hsfsts.hsf_status.flcerr == 1) { 8912 if (hsfsts.hsf_status.flcerr == 1) {
8908 /* repeat for some time before giving up */ 8913 /* repeat for some time before giving up */
8909 continue; 8914 continue;
@@ -8912,7 +8917,7 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8912 break; 8917 break;
8913 } 8918 }
8914 } 8919 }
8915 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 8920 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8916 if (error_flag == 1) 8921 if (error_flag == 1)
8917 break; 8922 break;
8918 } 8923 }
@@ -9013,5 +9018,3 @@ e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9013 return E1000_SUCCESS; 9018 return E1000_SUCCESS;
9014} 9019}
9015 9020
9016
9017
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 449a60303e07..3321fb13bfa9 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -128,11 +128,13 @@ typedef enum {
128/* PCI bus widths */ 128/* PCI bus widths */
129typedef enum { 129typedef enum {
130 e1000_bus_width_unknown = 0, 130 e1000_bus_width_unknown = 0,
131 /* These PCIe values should literally match the possible return values
132 * from config space */
133 e1000_bus_width_pciex_1 = 1,
134 e1000_bus_width_pciex_2 = 2,
135 e1000_bus_width_pciex_4 = 4,
131 e1000_bus_width_32, 136 e1000_bus_width_32,
132 e1000_bus_width_64, 137 e1000_bus_width_64,
133 e1000_bus_width_pciex_1,
134 e1000_bus_width_pciex_2,
135 e1000_bus_width_pciex_4,
136 e1000_bus_width_reserved 138 e1000_bus_width_reserved
137} e1000_bus_width; 139} e1000_bus_width;
138 140
@@ -326,6 +328,7 @@ int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
326int32_t e1000_phy_reset(struct e1000_hw *hw); 328int32_t e1000_phy_reset(struct e1000_hw *hw);
327int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 329int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
328int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 330int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
331
329void e1000_phy_powerdown_workaround(struct e1000_hw *hw); 332void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
330 333
331/* EEPROM Functions */ 334/* EEPROM Functions */
@@ -390,7 +393,6 @@ int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
390 uint16_t length); 393 uint16_t length);
391boolean_t e1000_check_mng_mode(struct e1000_hw *hw); 394boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
392boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 395boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
393
394int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 396int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
395int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 397int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
396int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 398int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
@@ -473,6 +475,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
473#define E1000_DEV_ID_82571EB_FIBER 0x105F 475#define E1000_DEV_ID_82571EB_FIBER 0x105F
474#define E1000_DEV_ID_82571EB_SERDES 0x1060 476#define E1000_DEV_ID_82571EB_SERDES 0x1060
475#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 477#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
478#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
476#define E1000_DEV_ID_82572EI_COPPER 0x107D 479#define E1000_DEV_ID_82572EI_COPPER 0x107D
477#define E1000_DEV_ID_82572EI_FIBER 0x107E 480#define E1000_DEV_ID_82572EI_FIBER 0x107E
478#define E1000_DEV_ID_82572EI_SERDES 0x107F 481#define E1000_DEV_ID_82572EI_SERDES 0x107F
@@ -490,6 +493,8 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
490#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 493#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
491#define E1000_DEV_ID_ICH8_IGP_C 0x104B 494#define E1000_DEV_ID_ICH8_IGP_C 0x104B
492#define E1000_DEV_ID_ICH8_IFE 0x104C 495#define E1000_DEV_ID_ICH8_IFE 0x104C
496#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
497#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
493#define E1000_DEV_ID_ICH8_IGP_M 0x104D 498#define E1000_DEV_ID_ICH8_IGP_M 0x104D
494 499
495 500
@@ -576,6 +581,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
576 * E1000_RAR_ENTRIES - 1 multicast addresses. 581 * E1000_RAR_ENTRIES - 1 multicast addresses.
577 */ 582 */
578#define E1000_RAR_ENTRIES 15 583#define E1000_RAR_ENTRIES 15
584
579#define E1000_RAR_ENTRIES_ICH8LAN 6 585#define E1000_RAR_ENTRIES_ICH8LAN 6
580 586
581#define MIN_NUMBER_OF_DESCRIPTORS 8 587#define MIN_NUMBER_OF_DESCRIPTORS 8
@@ -1335,9 +1341,9 @@ struct e1000_hw_stats {
1335 uint64_t gotch; 1341 uint64_t gotch;
1336 uint64_t rnbc; 1342 uint64_t rnbc;
1337 uint64_t ruc; 1343 uint64_t ruc;
1344 uint64_t rfc;
1338 uint64_t roc; 1345 uint64_t roc;
1339 uint64_t rlerrc; 1346 uint64_t rlerrc;
1340 uint64_t rfc;
1341 uint64_t rjc; 1347 uint64_t rjc;
1342 uint64_t mgprc; 1348 uint64_t mgprc;
1343 uint64_t mgpdc; 1349 uint64_t mgpdc;
@@ -1577,8 +1583,8 @@ struct e1000_hw {
1577#define E1000_HICR_FW_RESET 0xC0 1583#define E1000_HICR_FW_RESET 0xC0
1578 1584
1579#define E1000_SHADOW_RAM_WORDS 2048 1585#define E1000_SHADOW_RAM_WORDS 2048
1580#define E1000_ICH8_NVM_SIG_WORD 0x13 1586#define E1000_ICH_NVM_SIG_WORD 0x13
1581#define E1000_ICH8_NVM_SIG_MASK 0xC0 1587#define E1000_ICH_NVM_SIG_MASK 0xC0
1582 1588
1583/* EEPROM Read */ 1589/* EEPROM Read */
1584#define E1000_EERD_START 0x00000001 /* Start Read */ 1590#define E1000_EERD_START 0x00000001 /* Start Read */
@@ -3172,6 +3178,7 @@ struct e1000_host_command_info {
3172#define IGP3_VR_CTRL \ 3178#define IGP3_VR_CTRL \
3173 PHY_REG(776, 18) /* Voltage regulator control register */ 3179 PHY_REG(776, 18) /* Voltage regulator control register */
3174#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 3180#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3181#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
3175 3182
3176#define IGP3_CAPABILITY \ 3183#define IGP3_CAPABILITY \
3177 PHY_REG(776, 19) /* IGP3 Capability Register */ 3184 PHY_REG(776, 19) /* IGP3 Capability Register */
@@ -3256,41 +3263,40 @@ struct e1000_host_command_info {
3256#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 3263#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3257#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 3264#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3258 3265
3259#define ICH8_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 3266#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3260#define ICH8_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 3267#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3261#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 3268#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3262#define ICH8_FLASH_SEG_SIZE_256 256 3269#define ICH_FLASH_SEG_SIZE_256 256
3263#define ICH8_FLASH_SEG_SIZE_4K 4096 3270#define ICH_FLASH_SEG_SIZE_4K 4096
3264#define ICH9_FLASH_SEG_SIZE_8K 8192 3271#define ICH_FLASH_SEG_SIZE_64K 65536
3265#define ICH8_FLASH_SEG_SIZE_64K 65536 3272
3266 3273#define ICH_CYCLE_READ 0x0
3267#define ICH8_CYCLE_READ 0x0 3274#define ICH_CYCLE_RESERVED 0x1
3268#define ICH8_CYCLE_RESERVED 0x1 3275#define ICH_CYCLE_WRITE 0x2
3269#define ICH8_CYCLE_WRITE 0x2 3276#define ICH_CYCLE_ERASE 0x3
3270#define ICH8_CYCLE_ERASE 0x3 3277
3271 3278#define ICH_FLASH_GFPREG 0x0000
3272#define ICH8_FLASH_GFPREG 0x0000 3279#define ICH_FLASH_HSFSTS 0x0004
3273#define ICH8_FLASH_HSFSTS 0x0004 3280#define ICH_FLASH_HSFCTL 0x0006
3274#define ICH8_FLASH_HSFCTL 0x0006 3281#define ICH_FLASH_FADDR 0x0008
3275#define ICH8_FLASH_FADDR 0x0008 3282#define ICH_FLASH_FDATA0 0x0010
3276#define ICH8_FLASH_FDATA0 0x0010 3283#define ICH_FLASH_FRACC 0x0050
3277#define ICH8_FLASH_FRACC 0x0050 3284#define ICH_FLASH_FREG0 0x0054
3278#define ICH8_FLASH_FREG0 0x0054 3285#define ICH_FLASH_FREG1 0x0058
3279#define ICH8_FLASH_FREG1 0x0058 3286#define ICH_FLASH_FREG2 0x005C
3280#define ICH8_FLASH_FREG2 0x005C 3287#define ICH_FLASH_FREG3 0x0060
3281#define ICH8_FLASH_FREG3 0x0060 3288#define ICH_FLASH_FPR0 0x0074
3282#define ICH8_FLASH_FPR0 0x0074 3289#define ICH_FLASH_FPR1 0x0078
3283#define ICH8_FLASH_FPR1 0x0078 3290#define ICH_FLASH_SSFSTS 0x0090
3284#define ICH8_FLASH_SSFSTS 0x0090 3291#define ICH_FLASH_SSFCTL 0x0092
3285#define ICH8_FLASH_SSFCTL 0x0092 3292#define ICH_FLASH_PREOP 0x0094
3286#define ICH8_FLASH_PREOP 0x0094 3293#define ICH_FLASH_OPTYPE 0x0096
3287#define ICH8_FLASH_OPTYPE 0x0096 3294#define ICH_FLASH_OPMENU 0x0098
3288#define ICH8_FLASH_OPMENU 0x0098 3295
3289 3296#define ICH_FLASH_REG_MAPSIZE 0x00A0
3290#define ICH8_FLASH_REG_MAPSIZE 0x00A0 3297#define ICH_FLASH_SECTOR_SIZE 4096
3291#define ICH8_FLASH_SECTOR_SIZE 4096 3298#define ICH_GFPREG_BASE_MASK 0x1FFF
3292#define ICH8_GFPREG_BASE_MASK 0x1FFF 3299#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3293#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3294 3300
3295/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 3301/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3296/* Offset 04h HSFSTS */ 3302/* Offset 04h HSFSTS */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 03294400bc90..73f3a85fd238 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -27,6 +27,7 @@
27*******************************************************************************/ 27*******************************************************************************/
28 28
29#include "e1000.h" 29#include "e1000.h"
30#include <net/ip6_checksum.h>
30 31
31char e1000_driver_name[] = "e1000"; 32char e1000_driver_name[] = "e1000";
32static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
@@ -35,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
35#else 36#else
36#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
37#endif 38#endif
38#define DRV_VERSION "7.2.9-k4"DRIVERNAPI 39#define DRV_VERSION "7.3.15-k2"DRIVERNAPI
39char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
40static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
41 42
@@ -103,6 +104,9 @@ static struct pci_device_id e1000_pci_tbl[] = {
103 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 104 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BA), 105 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
105 INTEL_E1000_ETHERNET_DEVICE(0x10BB), 106 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
107 INTEL_E1000_ETHERNET_DEVICE(0x10BC),
108 INTEL_E1000_ETHERNET_DEVICE(0x10C4),
109 INTEL_E1000_ETHERNET_DEVICE(0x10C5),
106 /* required last entry */ 110 /* required last entry */
107 {0,} 111 {0,}
108}; 112};
@@ -154,6 +158,9 @@ static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
154static int e1000_change_mtu(struct net_device *netdev, int new_mtu); 158static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
155static int e1000_set_mac(struct net_device *netdev, void *p); 159static int e1000_set_mac(struct net_device *netdev, void *p);
156static irqreturn_t e1000_intr(int irq, void *data); 160static irqreturn_t e1000_intr(int irq, void *data);
161#ifdef CONFIG_PCI_MSI
162static irqreturn_t e1000_intr_msi(int irq, void *data);
163#endif
157static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter, 164static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
158 struct e1000_tx_ring *tx_ring); 165 struct e1000_tx_ring *tx_ring);
159#ifdef CONFIG_E1000_NAPI 166#ifdef CONFIG_E1000_NAPI
@@ -285,7 +292,7 @@ static int e1000_request_irq(struct e1000_adapter *adapter)
285 292
286 flags = IRQF_SHARED; 293 flags = IRQF_SHARED;
287#ifdef CONFIG_PCI_MSI 294#ifdef CONFIG_PCI_MSI
288 if (adapter->hw.mac_type > e1000_82547_rev_2) { 295 if (adapter->hw.mac_type >= e1000_82571) {
289 adapter->have_msi = TRUE; 296 adapter->have_msi = TRUE;
290 if ((err = pci_enable_msi(adapter->pdev))) { 297 if ((err = pci_enable_msi(adapter->pdev))) {
291 DPRINTK(PROBE, ERR, 298 DPRINTK(PROBE, ERR,
@@ -293,8 +300,14 @@ static int e1000_request_irq(struct e1000_adapter *adapter)
293 adapter->have_msi = FALSE; 300 adapter->have_msi = FALSE;
294 } 301 }
295 } 302 }
296 if (adapter->have_msi) 303 if (adapter->have_msi) {
297 flags &= ~IRQF_SHARED; 304 flags &= ~IRQF_SHARED;
305 err = request_irq(adapter->pdev->irq, &e1000_intr_msi, flags,
306 netdev->name, netdev);
307 if (err)
308 DPRINTK(PROBE, ERR,
309 "Unable to allocate interrupt Error: %d\n", err);
310 } else
298#endif 311#endif
299 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags, 312 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
300 netdev->name, netdev))) 313 netdev->name, netdev)))
@@ -375,7 +388,7 @@ e1000_update_mng_vlan(struct e1000_adapter *adapter)
375 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 388 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
376 * For ASF and Pass Through versions of f/w this means that the 389 * For ASF and Pass Through versions of f/w this means that the
377 * driver is no longer loaded. For AMT version (only with 82573) i 390 * driver is no longer loaded. For AMT version (only with 82573) i
378 * of the f/w this means that the netowrk i/f is closed. 391 * of the f/w this means that the network i/f is closed.
379 * 392 *
380 **/ 393 **/
381 394
@@ -416,7 +429,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
416 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 429 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
417 * For ASF and Pass Through versions of f/w this means that 430 * For ASF and Pass Through versions of f/w this means that
418 * the driver is loaded. For AMT version (only with 82573) 431 * the driver is loaded. For AMT version (only with 82573)
419 * of the f/w this means that the netowrk i/f is open. 432 * of the f/w this means that the network i/f is open.
420 * 433 *
421 **/ 434 **/
422 435
@@ -426,6 +439,7 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
426 uint32_t ctrl_ext; 439 uint32_t ctrl_ext;
427 uint32_t swsm; 440 uint32_t swsm;
428 uint32_t extcnf; 441 uint32_t extcnf;
442
429 /* Let firmware know the driver has taken over */ 443 /* Let firmware know the driver has taken over */
430 switch (adapter->hw.mac_type) { 444 switch (adapter->hw.mac_type) {
431 case e1000_82571: 445 case e1000_82571:
@@ -601,9 +615,6 @@ void
601e1000_reset(struct e1000_adapter *adapter) 615e1000_reset(struct e1000_adapter *adapter)
602{ 616{
603 uint32_t pba, manc; 617 uint32_t pba, manc;
604#ifdef DISABLE_MULR
605 uint32_t tctl;
606#endif
607 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF; 618 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
608 619
609 /* Repartition Pba for greater than 9k mtu 620 /* Repartition Pba for greater than 9k mtu
@@ -670,12 +681,7 @@ e1000_reset(struct e1000_adapter *adapter)
670 e1000_reset_hw(&adapter->hw); 681 e1000_reset_hw(&adapter->hw);
671 if (adapter->hw.mac_type >= e1000_82544) 682 if (adapter->hw.mac_type >= e1000_82544)
672 E1000_WRITE_REG(&adapter->hw, WUC, 0); 683 E1000_WRITE_REG(&adapter->hw, WUC, 0);
673#ifdef DISABLE_MULR
674 /* disable Multiple Reads in Transmit Control Register for debugging */
675 tctl = E1000_READ_REG(hw, TCTL);
676 E1000_WRITE_REG(hw, TCTL, tctl & ~E1000_TCTL_MULR);
677 684
678#endif
679 if (e1000_init_hw(&adapter->hw)) 685 if (e1000_init_hw(&adapter->hw))
680 DPRINTK(PROBE, ERR, "Hardware Error\n"); 686 DPRINTK(PROBE, ERR, "Hardware Error\n");
681 e1000_update_mng_vlan(adapter); 687 e1000_update_mng_vlan(adapter);
@@ -851,9 +857,9 @@ e1000_probe(struct pci_dev *pdev,
851 (adapter->hw.mac_type != e1000_82547)) 857 (adapter->hw.mac_type != e1000_82547))
852 netdev->features |= NETIF_F_TSO; 858 netdev->features |= NETIF_F_TSO;
853 859
854#ifdef NETIF_F_TSO_IPV6 860#ifdef NETIF_F_TSO6
855 if (adapter->hw.mac_type > e1000_82547_rev_2) 861 if (adapter->hw.mac_type > e1000_82547_rev_2)
856 netdev->features |= NETIF_F_TSO_IPV6; 862 netdev->features |= NETIF_F_TSO6;
857#endif 863#endif
858#endif 864#endif
859 if (pci_using_dac) 865 if (pci_using_dac)
@@ -967,6 +973,7 @@ e1000_probe(struct pci_dev *pdev,
967 break; 973 break;
968 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 974 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
969 case E1000_DEV_ID_82571EB_QUAD_COPPER: 975 case E1000_DEV_ID_82571EB_QUAD_COPPER:
976 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
970 /* if quad port adapter, disable WoL on all but port A */ 977 /* if quad port adapter, disable WoL on all but port A */
971 if (global_quad_port_a != 0) 978 if (global_quad_port_a != 0)
972 adapter->eeprom_wol = 0; 979 adapter->eeprom_wol = 0;
@@ -1278,12 +1285,10 @@ e1000_open(struct net_device *netdev)
1278 return -EBUSY; 1285 return -EBUSY;
1279 1286
1280 /* allocate transmit descriptors */ 1287 /* allocate transmit descriptors */
1281
1282 if ((err = e1000_setup_all_tx_resources(adapter))) 1288 if ((err = e1000_setup_all_tx_resources(adapter)))
1283 goto err_setup_tx; 1289 goto err_setup_tx;
1284 1290
1285 /* allocate receive descriptors */ 1291 /* allocate receive descriptors */
1286
1287 if ((err = e1000_setup_all_rx_resources(adapter))) 1292 if ((err = e1000_setup_all_rx_resources(adapter)))
1288 goto err_setup_rx; 1293 goto err_setup_rx;
1289 1294
@@ -1568,6 +1573,8 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1568 1573
1569 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 1574 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1570 tarc = E1000_READ_REG(hw, TARC0); 1575 tarc = E1000_READ_REG(hw, TARC0);
1576 /* set the speed mode bit, we'll clear it if we're not at
1577 * gigabit link later */
1571 tarc |= (1 << 21); 1578 tarc |= (1 << 21);
1572 E1000_WRITE_REG(hw, TARC0, tarc); 1579 E1000_WRITE_REG(hw, TARC0, tarc);
1573 } else if (hw->mac_type == e1000_80003es2lan) { 1580 } else if (hw->mac_type == e1000_80003es2lan) {
@@ -1582,8 +1589,11 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1582 e1000_config_collision_dist(hw); 1589 e1000_config_collision_dist(hw);
1583 1590
1584 /* Setup Transmit Descriptor Settings for eop descriptor */ 1591 /* Setup Transmit Descriptor Settings for eop descriptor */
1585 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP | 1592 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1586 E1000_TXD_CMD_IFCS; 1593
1594 /* only set IDE if we are delaying interrupts using the timers */
1595 if (adapter->tx_int_delay)
1596 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1587 1597
1588 if (hw->mac_type < e1000_82543) 1598 if (hw->mac_type < e1000_82543)
1589 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 1599 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
@@ -1820,8 +1830,11 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1820 /* Configure extra packet-split registers */ 1830 /* Configure extra packet-split registers */
1821 rfctl = E1000_READ_REG(&adapter->hw, RFCTL); 1831 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1822 rfctl |= E1000_RFCTL_EXTEN; 1832 rfctl |= E1000_RFCTL_EXTEN;
1823 /* disable IPv6 packet split support */ 1833 /* disable packet split support for IPv6 extension headers,
1824 rfctl |= E1000_RFCTL_IPV6_DIS; 1834 * because some malformed IPv6 headers can hang the RX */
1835 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1836 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1837
1825 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl); 1838 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1826 1839
1827 rctl |= E1000_RCTL_DTYP_PS; 1840 rctl |= E1000_RCTL_DTYP_PS;
@@ -1884,7 +1897,7 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1884 1897
1885 if (hw->mac_type >= e1000_82540) { 1898 if (hw->mac_type >= e1000_82540) {
1886 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 1899 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1887 if (adapter->itr > 1) 1900 if (adapter->itr_setting != 0)
1888 E1000_WRITE_REG(hw, ITR, 1901 E1000_WRITE_REG(hw, ITR,
1889 1000000000 / (adapter->itr * 256)); 1902 1000000000 / (adapter->itr * 256));
1890 } 1903 }
@@ -1894,11 +1907,11 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1894 /* Reset delay timers after every interrupt */ 1907 /* Reset delay timers after every interrupt */
1895 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 1908 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1896#ifdef CONFIG_E1000_NAPI 1909#ifdef CONFIG_E1000_NAPI
1897 /* Auto-Mask interrupts upon ICR read. */ 1910 /* Auto-Mask interrupts upon ICR access */
1898 ctrl_ext |= E1000_CTRL_EXT_IAME; 1911 ctrl_ext |= E1000_CTRL_EXT_IAME;
1912 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1899#endif 1913#endif
1900 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1914 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1901 E1000_WRITE_REG(hw, IAM, ~0);
1902 E1000_WRITE_FLUSH(hw); 1915 E1000_WRITE_FLUSH(hw);
1903 } 1916 }
1904 1917
@@ -1937,6 +1950,12 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1937 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 1950 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1938 } 1951 }
1939 1952
1953 /* enable early receives on 82573, only takes effect if using > 2048
1954 * byte total frame size. for example only for jumbo frames */
1955#define E1000_ERT_2048 0x100
1956 if (hw->mac_type == e1000_82573)
1957 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
1958
1940 /* Enable Receives */ 1959 /* Enable Receives */
1941 E1000_WRITE_REG(hw, RCTL, rctl); 1960 E1000_WRITE_REG(hw, RCTL, rctl);
1942} 1961}
@@ -1990,10 +2009,13 @@ e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1990 buffer_info->dma, 2009 buffer_info->dma,
1991 buffer_info->length, 2010 buffer_info->length,
1992 PCI_DMA_TODEVICE); 2011 PCI_DMA_TODEVICE);
2012 buffer_info->dma = 0;
1993 } 2013 }
1994 if (buffer_info->skb) 2014 if (buffer_info->skb) {
1995 dev_kfree_skb_any(buffer_info->skb); 2015 dev_kfree_skb_any(buffer_info->skb);
1996 memset(buffer_info, 0, sizeof(struct e1000_buffer)); 2016 buffer_info->skb = NULL;
2017 }
2018 /* buffer_info must be completely set up in the transmit path */
1997} 2019}
1998 2020
1999/** 2021/**
@@ -2417,6 +2439,7 @@ e1000_watchdog(unsigned long data)
2417 DPRINTK(LINK, INFO, 2439 DPRINTK(LINK, INFO,
2418 "Gigabit has been disabled, downgrading speed\n"); 2440 "Gigabit has been disabled, downgrading speed\n");
2419 } 2441 }
2442
2420 if (adapter->hw.mac_type == e1000_82573) { 2443 if (adapter->hw.mac_type == e1000_82573) {
2421 e1000_enable_tx_pkt_filtering(&adapter->hw); 2444 e1000_enable_tx_pkt_filtering(&adapter->hw);
2422 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id) 2445 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
@@ -2461,13 +2484,12 @@ e1000_watchdog(unsigned long data)
2461 if ((adapter->hw.mac_type == e1000_82571 || 2484 if ((adapter->hw.mac_type == e1000_82571 ||
2462 adapter->hw.mac_type == e1000_82572) && 2485 adapter->hw.mac_type == e1000_82572) &&
2463 txb2b == 0) { 2486 txb2b == 0) {
2464#define SPEED_MODE_BIT (1 << 21)
2465 uint32_t tarc0; 2487 uint32_t tarc0;
2466 tarc0 = E1000_READ_REG(&adapter->hw, TARC0); 2488 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2467 tarc0 &= ~SPEED_MODE_BIT; 2489 tarc0 &= ~(1 << 21);
2468 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0); 2490 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2469 } 2491 }
2470 2492
2471#ifdef NETIF_F_TSO 2493#ifdef NETIF_F_TSO
2472 /* disable TSO for pcie and 10/100 speeds, to avoid 2494 /* disable TSO for pcie and 10/100 speeds, to avoid
2473 * some hardware issues */ 2495 * some hardware issues */
@@ -2479,9 +2501,15 @@ e1000_watchdog(unsigned long data)
2479 DPRINTK(PROBE,INFO, 2501 DPRINTK(PROBE,INFO,
2480 "10/100 speed: disabling TSO\n"); 2502 "10/100 speed: disabling TSO\n");
2481 netdev->features &= ~NETIF_F_TSO; 2503 netdev->features &= ~NETIF_F_TSO;
2504#ifdef NETIF_F_TSO6
2505 netdev->features &= ~NETIF_F_TSO6;
2506#endif
2482 break; 2507 break;
2483 case SPEED_1000: 2508 case SPEED_1000:
2484 netdev->features |= NETIF_F_TSO; 2509 netdev->features |= NETIF_F_TSO;
2510#ifdef NETIF_F_TSO6
2511 netdev->features |= NETIF_F_TSO6;
2512#endif
2485 break; 2513 break;
2486 default: 2514 default:
2487 /* oops */ 2515 /* oops */
@@ -2548,19 +2576,6 @@ e1000_watchdog(unsigned long data)
2548 } 2576 }
2549 } 2577 }
2550 2578
2551 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2552 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2553 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2554 * asymmetrical Tx or Rx gets ITR=8000; everyone
2555 * else is between 2000-8000. */
2556 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2557 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2558 adapter->gotcl - adapter->gorcl :
2559 adapter->gorcl - adapter->gotcl) / 10000;
2560 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2561 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2562 }
2563
2564 /* Cause software interrupt to ensure rx ring is cleaned */ 2579 /* Cause software interrupt to ensure rx ring is cleaned */
2565 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0); 2580 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2566 2581
@@ -2576,6 +2591,135 @@ e1000_watchdog(unsigned long data)
2576 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); 2591 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2577} 2592}
2578 2593
2594enum latency_range {
2595 lowest_latency = 0,
2596 low_latency = 1,
2597 bulk_latency = 2,
2598 latency_invalid = 255
2599};
2600
2601/**
2602 * e1000_update_itr - update the dynamic ITR value based on statistics
2603 * Stores a new ITR value based on packets and byte
2604 * counts during the last interrupt. The advantage of per interrupt
2605 * computation is faster updates and more accurate ITR for the current
2606 * traffic pattern. Constants in this function were computed
2607 * based on theoretical maximum wire speed and thresholds were set based
2608 * on testing data as well as attempting to minimize response time
2609 * while increasing bulk throughput.
2610 * this functionality is controlled by the InterruptThrottleRate module
2611 * parameter (see e1000_param.c)
2612 * @adapter: pointer to adapter
2613 * @itr_setting: current adapter->itr
2614 * @packets: the number of packets during this measurement interval
2615 * @bytes: the number of bytes during this measurement interval
2616 **/
2617static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2618 uint16_t itr_setting,
2619 int packets,
2620 int bytes)
2621{
2622 unsigned int retval = itr_setting;
2623 struct e1000_hw *hw = &adapter->hw;
2624
2625 if (unlikely(hw->mac_type < e1000_82540))
2626 goto update_itr_done;
2627
2628 if (packets == 0)
2629 goto update_itr_done;
2630
2631
2632 switch (itr_setting) {
2633 case lowest_latency:
2634 if ((packets < 5) && (bytes > 512))
2635 retval = low_latency;
2636 break;
2637 case low_latency: /* 50 usec aka 20000 ints/s */
2638 if (bytes > 10000) {
2639 if ((packets < 10) ||
2640 ((bytes/packets) > 1200))
2641 retval = bulk_latency;
2642 else if ((packets > 35))
2643 retval = lowest_latency;
2644 } else if (packets <= 2 && bytes < 512)
2645 retval = lowest_latency;
2646 break;
2647 case bulk_latency: /* 250 usec aka 4000 ints/s */
2648 if (bytes > 25000) {
2649 if (packets > 35)
2650 retval = low_latency;
2651 } else {
2652 if (bytes < 6000)
2653 retval = low_latency;
2654 }
2655 break;
2656 }
2657
2658update_itr_done:
2659 return retval;
2660}
2661
2662static void e1000_set_itr(struct e1000_adapter *adapter)
2663{
2664 struct e1000_hw *hw = &adapter->hw;
2665 uint16_t current_itr;
2666 uint32_t new_itr = adapter->itr;
2667
2668 if (unlikely(hw->mac_type < e1000_82540))
2669 return;
2670
2671 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2672 if (unlikely(adapter->link_speed != SPEED_1000)) {
2673 current_itr = 0;
2674 new_itr = 4000;
2675 goto set_itr_now;
2676 }
2677
2678 adapter->tx_itr = e1000_update_itr(adapter,
2679 adapter->tx_itr,
2680 adapter->total_tx_packets,
2681 adapter->total_tx_bytes);
2682 adapter->rx_itr = e1000_update_itr(adapter,
2683 adapter->rx_itr,
2684 adapter->total_rx_packets,
2685 adapter->total_rx_bytes);
2686
2687 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2688
2689 /* conservative mode eliminates the lowest_latency setting */
2690 if (current_itr == lowest_latency && (adapter->itr_setting == 3))
2691 current_itr = low_latency;
2692
2693 switch (current_itr) {
2694 /* counts and packets in update_itr are dependent on these numbers */
2695 case lowest_latency:
2696 new_itr = 70000;
2697 break;
2698 case low_latency:
2699 new_itr = 20000; /* aka hwitr = ~200 */
2700 break;
2701 case bulk_latency:
2702 new_itr = 4000;
2703 break;
2704 default:
2705 break;
2706 }
2707
2708set_itr_now:
2709 if (new_itr != adapter->itr) {
2710 /* this attempts to bias the interrupt rate towards Bulk
2711 * by adding intermediate steps when interrupt rate is
2712 * increasing */
2713 new_itr = new_itr > adapter->itr ?
2714 min(adapter->itr + (new_itr >> 2), new_itr) :
2715 new_itr;
2716 adapter->itr = new_itr;
2717 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2718 }
2719
2720 return;
2721}
2722
2579#define E1000_TX_FLAGS_CSUM 0x00000001 2723#define E1000_TX_FLAGS_CSUM 0x00000001
2580#define E1000_TX_FLAGS_VLAN 0x00000002 2724#define E1000_TX_FLAGS_VLAN 0x00000002
2581#define E1000_TX_FLAGS_TSO 0x00000004 2725#define E1000_TX_FLAGS_TSO 0x00000004
@@ -2616,7 +2760,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2616 0); 2760 0);
2617 cmd_length = E1000_TXD_CMD_IP; 2761 cmd_length = E1000_TXD_CMD_IP;
2618 ipcse = skb->h.raw - skb->data - 1; 2762 ipcse = skb->h.raw - skb->data - 1;
2619#ifdef NETIF_F_TSO_IPV6 2763#ifdef NETIF_F_TSO6
2620 } else if (skb->protocol == htons(ETH_P_IPV6)) { 2764 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2621 skb->nh.ipv6h->payload_len = 0; 2765 skb->nh.ipv6h->payload_len = 0;
2622 skb->h.th->check = 2766 skb->h.th->check =
@@ -2652,6 +2796,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2652 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 2796 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2653 2797
2654 buffer_info->time_stamp = jiffies; 2798 buffer_info->time_stamp = jiffies;
2799 buffer_info->next_to_watch = i;
2655 2800
2656 if (++i == tx_ring->count) i = 0; 2801 if (++i == tx_ring->count) i = 0;
2657 tx_ring->next_to_use = i; 2802 tx_ring->next_to_use = i;
@@ -2680,12 +2825,13 @@ e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2680 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 2825 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
2681 2826
2682 context_desc->upper_setup.tcp_fields.tucss = css; 2827 context_desc->upper_setup.tcp_fields.tucss = css;
2683 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum; 2828 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
2684 context_desc->upper_setup.tcp_fields.tucse = 0; 2829 context_desc->upper_setup.tcp_fields.tucse = 0;
2685 context_desc->tcp_seg_setup.data = 0; 2830 context_desc->tcp_seg_setup.data = 0;
2686 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT); 2831 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2687 2832
2688 buffer_info->time_stamp = jiffies; 2833 buffer_info->time_stamp = jiffies;
2834 buffer_info->next_to_watch = i;
2689 2835
2690 if (unlikely(++i == tx_ring->count)) i = 0; 2836 if (unlikely(++i == tx_ring->count)) i = 0;
2691 tx_ring->next_to_use = i; 2837 tx_ring->next_to_use = i;
@@ -2754,6 +2900,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2754 size, 2900 size,
2755 PCI_DMA_TODEVICE); 2901 PCI_DMA_TODEVICE);
2756 buffer_info->time_stamp = jiffies; 2902 buffer_info->time_stamp = jiffies;
2903 buffer_info->next_to_watch = i;
2757 2904
2758 len -= size; 2905 len -= size;
2759 offset += size; 2906 offset += size;
@@ -2793,6 +2940,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2793 size, 2940 size,
2794 PCI_DMA_TODEVICE); 2941 PCI_DMA_TODEVICE);
2795 buffer_info->time_stamp = jiffies; 2942 buffer_info->time_stamp = jiffies;
2943 buffer_info->next_to_watch = i;
2796 2944
2797 len -= size; 2945 len -= size;
2798 offset += size; 2946 offset += size;
@@ -2858,6 +3006,9 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2858 3006
2859 tx_ring->next_to_use = i; 3007 tx_ring->next_to_use = i;
2860 writel(i, adapter->hw.hw_addr + tx_ring->tdt); 3008 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
3009 /* we need this if more than one processor can write to our tail
3010 * at a time, it syncronizes IO on IA64/Altix systems */
3011 mmiowb();
2861} 3012}
2862 3013
2863/** 3014/**
@@ -2951,6 +3102,7 @@ static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
2951 3102
2952 /* A reprieve! */ 3103 /* A reprieve! */
2953 netif_start_queue(netdev); 3104 netif_start_queue(netdev);
3105 ++adapter->restart_queue;
2954 return 0; 3106 return 0;
2955} 3107}
2956 3108
@@ -3009,9 +3161,9 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3009 max_per_txd = min(mss << 2, max_per_txd); 3161 max_per_txd = min(mss << 2, max_per_txd);
3010 max_txd_pwr = fls(max_per_txd) - 1; 3162 max_txd_pwr = fls(max_per_txd) - 1;
3011 3163
3012 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 3164 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3013 * points to just header, pull a few bytes of payload from 3165 * points to just header, pull a few bytes of payload from
3014 * frags into skb->data */ 3166 * frags into skb->data */
3015 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); 3167 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
3016 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) { 3168 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
3017 switch (adapter->hw.mac_type) { 3169 switch (adapter->hw.mac_type) {
@@ -3316,12 +3468,12 @@ e1000_update_stats(struct e1000_adapter *adapter)
3316 adapter->stats.roc += E1000_READ_REG(hw, ROC); 3468 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3317 3469
3318 if (adapter->hw.mac_type != e1000_ich8lan) { 3470 if (adapter->hw.mac_type != e1000_ich8lan) {
3319 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64); 3471 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3320 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127); 3472 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3321 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255); 3473 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3322 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511); 3474 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3323 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023); 3475 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3324 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522); 3476 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3325 } 3477 }
3326 3478
3327 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS); 3479 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
@@ -3352,12 +3504,12 @@ e1000_update_stats(struct e1000_adapter *adapter)
3352 adapter->stats.tpr += E1000_READ_REG(hw, TPR); 3504 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3353 3505
3354 if (adapter->hw.mac_type != e1000_ich8lan) { 3506 if (adapter->hw.mac_type != e1000_ich8lan) {
3355 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64); 3507 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3356 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127); 3508 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3357 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255); 3509 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3358 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511); 3510 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3359 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023); 3511 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3360 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522); 3512 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3361 } 3513 }
3362 3514
3363 adapter->stats.mptc += E1000_READ_REG(hw, MPTC); 3515 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
@@ -3383,18 +3535,17 @@ e1000_update_stats(struct e1000_adapter *adapter)
3383 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC); 3535 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3384 3536
3385 if (adapter->hw.mac_type != e1000_ich8lan) { 3537 if (adapter->hw.mac_type != e1000_ich8lan) {
3386 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC); 3538 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3387 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC); 3539 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3388 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC); 3540 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3389 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC); 3541 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3390 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC); 3542 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3391 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC); 3543 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3392 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC); 3544 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3393 } 3545 }
3394 } 3546 }
3395 3547
3396 /* Fill out the OS statistics structure */ 3548 /* Fill out the OS statistics structure */
3397
3398 adapter->net_stats.rx_packets = adapter->stats.gprc; 3549 adapter->net_stats.rx_packets = adapter->stats.gprc;
3399 adapter->net_stats.tx_packets = adapter->stats.gptc; 3550 adapter->net_stats.tx_packets = adapter->stats.gptc;
3400 adapter->net_stats.rx_bytes = adapter->stats.gorcl; 3551 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
@@ -3426,7 +3577,6 @@ e1000_update_stats(struct e1000_adapter *adapter)
3426 /* Tx Dropped needs to be maintained elsewhere */ 3577 /* Tx Dropped needs to be maintained elsewhere */
3427 3578
3428 /* Phy Stats */ 3579 /* Phy Stats */
3429
3430 if (hw->media_type == e1000_media_type_copper) { 3580 if (hw->media_type == e1000_media_type_copper) {
3431 if ((adapter->link_speed == SPEED_1000) && 3581 if ((adapter->link_speed == SPEED_1000) &&
3432 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 3582 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
@@ -3442,6 +3592,95 @@ e1000_update_stats(struct e1000_adapter *adapter)
3442 3592
3443 spin_unlock_irqrestore(&adapter->stats_lock, flags); 3593 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3444} 3594}
3595#ifdef CONFIG_PCI_MSI
3596
3597/**
3598 * e1000_intr_msi - Interrupt Handler
3599 * @irq: interrupt number
3600 * @data: pointer to a network interface device structure
3601 **/
3602
3603static
3604irqreturn_t e1000_intr_msi(int irq, void *data)
3605{
3606 struct net_device *netdev = data;
3607 struct e1000_adapter *adapter = netdev_priv(netdev);
3608 struct e1000_hw *hw = &adapter->hw;
3609#ifndef CONFIG_E1000_NAPI
3610 int i;
3611#endif
3612
3613 /* this code avoids the read of ICR but has to get 1000 interrupts
3614 * at every link change event before it will notice the change */
3615 if (++adapter->detect_link >= 1000) {
3616 uint32_t icr = E1000_READ_REG(hw, ICR);
3617#ifdef CONFIG_E1000_NAPI
3618 /* read ICR disables interrupts using IAM, so keep up with our
3619 * enable/disable accounting */
3620 atomic_inc(&adapter->irq_sem);
3621#endif
3622 adapter->detect_link = 0;
3623 if ((icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) &&
3624 (icr & E1000_ICR_INT_ASSERTED)) {
3625 hw->get_link_status = 1;
3626 /* 80003ES2LAN workaround--
3627 * For packet buffer work-around on link down event;
3628 * disable receives here in the ISR and
3629 * reset adapter in watchdog
3630 */
3631 if (netif_carrier_ok(netdev) &&
3632 (adapter->hw.mac_type == e1000_80003es2lan)) {
3633 /* disable receives */
3634 uint32_t rctl = E1000_READ_REG(hw, RCTL);
3635 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3636 }
3637 /* guard against interrupt when we're going down */
3638 if (!test_bit(__E1000_DOWN, &adapter->flags))
3639 mod_timer(&adapter->watchdog_timer,
3640 jiffies + 1);
3641 }
3642 } else {
3643 E1000_WRITE_REG(hw, ICR, (0xffffffff & ~(E1000_ICR_RXSEQ |
3644 E1000_ICR_LSC)));
3645 /* bummer we have to flush here, but things break otherwise as
3646 * some event appears to be lost or delayed and throughput
3647 * drops. In almost all tests this flush is un-necessary */
3648 E1000_WRITE_FLUSH(hw);
3649#ifdef CONFIG_E1000_NAPI
3650 /* Interrupt Auto-Mask (IAM)...upon writing ICR, interrupts are
3651 * masked. No need for the IMC write, but it does mean we
3652 * should account for it ASAP. */
3653 atomic_inc(&adapter->irq_sem);
3654#endif
3655 }
3656
3657#ifdef CONFIG_E1000_NAPI
3658 if (likely(netif_rx_schedule_prep(netdev))) {
3659 adapter->total_tx_bytes = 0;
3660 adapter->total_tx_packets = 0;
3661 adapter->total_rx_bytes = 0;
3662 adapter->total_rx_packets = 0;
3663 __netif_rx_schedule(netdev);
3664 } else
3665 e1000_irq_enable(adapter);
3666#else
3667 adapter->total_tx_bytes = 0;
3668 adapter->total_rx_bytes = 0;
3669 adapter->total_tx_packets = 0;
3670 adapter->total_rx_packets = 0;
3671
3672 for (i = 0; i < E1000_MAX_INTR; i++)
3673 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3674 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
3675 break;
3676
3677 if (likely(adapter->itr_setting & 3))
3678 e1000_set_itr(adapter);
3679#endif
3680
3681 return IRQ_HANDLED;
3682}
3683#endif
3445 3684
3446/** 3685/**
3447 * e1000_intr - Interrupt Handler 3686 * e1000_intr - Interrupt Handler
@@ -3458,7 +3697,17 @@ e1000_intr(int irq, void *data)
3458 uint32_t rctl, icr = E1000_READ_REG(hw, ICR); 3697 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
3459#ifndef CONFIG_E1000_NAPI 3698#ifndef CONFIG_E1000_NAPI
3460 int i; 3699 int i;
3461#else 3700#endif
3701 if (unlikely(!icr))
3702 return IRQ_NONE; /* Not our interrupt */
3703
3704#ifdef CONFIG_E1000_NAPI
3705 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3706 * not set, then the adapter didn't send an interrupt */
3707 if (unlikely(hw->mac_type >= e1000_82571 &&
3708 !(icr & E1000_ICR_INT_ASSERTED)))
3709 return IRQ_NONE;
3710
3462 /* Interrupt Auto-Mask...upon reading ICR, 3711 /* Interrupt Auto-Mask...upon reading ICR,
3463 * interrupts are masked. No need for the 3712 * interrupts are masked. No need for the
3464 * IMC write, but it does mean we should 3713 * IMC write, but it does mean we should
@@ -3467,14 +3716,6 @@ e1000_intr(int irq, void *data)
3467 atomic_inc(&adapter->irq_sem); 3716 atomic_inc(&adapter->irq_sem);
3468#endif 3717#endif
3469 3718
3470 if (unlikely(!icr)) {
3471#ifdef CONFIG_E1000_NAPI
3472 if (hw->mac_type >= e1000_82571)
3473 e1000_irq_enable(adapter);
3474#endif
3475 return IRQ_NONE; /* Not our interrupt */
3476 }
3477
3478 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { 3719 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3479 hw->get_link_status = 1; 3720 hw->get_link_status = 1;
3480 /* 80003ES2LAN workaround-- 3721 /* 80003ES2LAN workaround--
@@ -3495,13 +3736,20 @@ e1000_intr(int irq, void *data)
3495 3736
3496#ifdef CONFIG_E1000_NAPI 3737#ifdef CONFIG_E1000_NAPI
3497 if (unlikely(hw->mac_type < e1000_82571)) { 3738 if (unlikely(hw->mac_type < e1000_82571)) {
3739 /* disable interrupts, without the synchronize_irq bit */
3498 atomic_inc(&adapter->irq_sem); 3740 atomic_inc(&adapter->irq_sem);
3499 E1000_WRITE_REG(hw, IMC, ~0); 3741 E1000_WRITE_REG(hw, IMC, ~0);
3500 E1000_WRITE_FLUSH(hw); 3742 E1000_WRITE_FLUSH(hw);
3501 } 3743 }
3502 if (likely(netif_rx_schedule_prep(netdev))) 3744 if (likely(netif_rx_schedule_prep(netdev))) {
3745 adapter->total_tx_bytes = 0;
3746 adapter->total_tx_packets = 0;
3747 adapter->total_rx_bytes = 0;
3748 adapter->total_rx_packets = 0;
3503 __netif_rx_schedule(netdev); 3749 __netif_rx_schedule(netdev);
3504 else 3750 } else
3751 /* this really should not happen! if it does it is basically a
3752 * bug, but not a hard error, so enable ints and continue */
3505 e1000_irq_enable(adapter); 3753 e1000_irq_enable(adapter);
3506#else 3754#else
3507 /* Writing IMC and IMS is needed for 82547. 3755 /* Writing IMC and IMS is needed for 82547.
@@ -3519,16 +3767,23 @@ e1000_intr(int irq, void *data)
3519 E1000_WRITE_REG(hw, IMC, ~0); 3767 E1000_WRITE_REG(hw, IMC, ~0);
3520 } 3768 }
3521 3769
3770 adapter->total_tx_bytes = 0;
3771 adapter->total_rx_bytes = 0;
3772 adapter->total_tx_packets = 0;
3773 adapter->total_rx_packets = 0;
3774
3522 for (i = 0; i < E1000_MAX_INTR; i++) 3775 for (i = 0; i < E1000_MAX_INTR; i++)
3523 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) & 3776 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3524 !e1000_clean_tx_irq(adapter, adapter->tx_ring))) 3777 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
3525 break; 3778 break;
3526 3779
3780 if (likely(adapter->itr_setting & 3))
3781 e1000_set_itr(adapter);
3782
3527 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) 3783 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3528 e1000_irq_enable(adapter); 3784 e1000_irq_enable(adapter);
3529 3785
3530#endif 3786#endif
3531
3532 return IRQ_HANDLED; 3787 return IRQ_HANDLED;
3533} 3788}
3534 3789
@@ -3572,6 +3827,8 @@ e1000_clean(struct net_device *poll_dev, int *budget)
3572 if ((!tx_cleaned && (work_done == 0)) || 3827 if ((!tx_cleaned && (work_done == 0)) ||
3573 !netif_running(poll_dev)) { 3828 !netif_running(poll_dev)) {
3574quit_polling: 3829quit_polling:
3830 if (likely(adapter->itr_setting & 3))
3831 e1000_set_itr(adapter);
3575 netif_rx_complete(poll_dev); 3832 netif_rx_complete(poll_dev);
3576 e1000_irq_enable(adapter); 3833 e1000_irq_enable(adapter);
3577 return 0; 3834 return 0;
@@ -3598,6 +3855,7 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3598 unsigned int count = 0; 3855 unsigned int count = 0;
3599#endif 3856#endif
3600 boolean_t cleaned = FALSE; 3857 boolean_t cleaned = FALSE;
3858 unsigned int total_tx_bytes=0, total_tx_packets=0;
3601 3859
3602 i = tx_ring->next_to_clean; 3860 i = tx_ring->next_to_clean;
3603 eop = tx_ring->buffer_info[i].next_to_watch; 3861 eop = tx_ring->buffer_info[i].next_to_watch;
@@ -3609,13 +3867,19 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3609 buffer_info = &tx_ring->buffer_info[i]; 3867 buffer_info = &tx_ring->buffer_info[i];
3610 cleaned = (i == eop); 3868 cleaned = (i == eop);
3611 3869
3870 if (cleaned) {
3871 /* this packet count is wrong for TSO but has a
3872 * tendency to make dynamic ITR change more
3873 * towards bulk */
3874 total_tx_packets++;
3875 total_tx_bytes += buffer_info->skb->len;
3876 }
3612 e1000_unmap_and_free_tx_resource(adapter, buffer_info); 3877 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
3613 memset(tx_desc, 0, sizeof(struct e1000_tx_desc)); 3878 tx_desc->upper.data = 0;
3614 3879
3615 if (unlikely(++i == tx_ring->count)) i = 0; 3880 if (unlikely(++i == tx_ring->count)) i = 0;
3616 } 3881 }
3617 3882
3618
3619 eop = tx_ring->buffer_info[i].next_to_watch; 3883 eop = tx_ring->buffer_info[i].next_to_watch;
3620 eop_desc = E1000_TX_DESC(*tx_ring, eop); 3884 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3621#ifdef CONFIG_E1000_NAPI 3885#ifdef CONFIG_E1000_NAPI
@@ -3634,8 +3898,10 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3634 * sees the new next_to_clean. 3898 * sees the new next_to_clean.
3635 */ 3899 */
3636 smp_mb(); 3900 smp_mb();
3637 if (netif_queue_stopped(netdev)) 3901 if (netif_queue_stopped(netdev)) {
3638 netif_wake_queue(netdev); 3902 netif_wake_queue(netdev);
3903 ++adapter->restart_queue;
3904 }
3639 } 3905 }
3640 3906
3641 if (adapter->detect_tx_hung) { 3907 if (adapter->detect_tx_hung) {
@@ -3673,6 +3939,8 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3673 netif_stop_queue(netdev); 3939 netif_stop_queue(netdev);
3674 } 3940 }
3675 } 3941 }
3942 adapter->total_tx_bytes += total_tx_bytes;
3943 adapter->total_tx_packets += total_tx_packets;
3676 return cleaned; 3944 return cleaned;
3677} 3945}
3678 3946
@@ -3752,6 +4020,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3752 unsigned int i; 4020 unsigned int i;
3753 int cleaned_count = 0; 4021 int cleaned_count = 0;
3754 boolean_t cleaned = FALSE; 4022 boolean_t cleaned = FALSE;
4023 unsigned int total_rx_bytes=0, total_rx_packets=0;
3755 4024
3756 i = rx_ring->next_to_clean; 4025 i = rx_ring->next_to_clean;
3757 rx_desc = E1000_RX_DESC(*rx_ring, i); 4026 rx_desc = E1000_RX_DESC(*rx_ring, i);
@@ -3760,6 +4029,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3760 while (rx_desc->status & E1000_RXD_STAT_DD) { 4029 while (rx_desc->status & E1000_RXD_STAT_DD) {
3761 struct sk_buff *skb; 4030 struct sk_buff *skb;
3762 u8 status; 4031 u8 status;
4032
3763#ifdef CONFIG_E1000_NAPI 4033#ifdef CONFIG_E1000_NAPI
3764 if (*work_done >= work_to_do) 4034 if (*work_done >= work_to_do)
3765 break; 4035 break;
@@ -3817,6 +4087,10 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3817 * done after the TBI_ACCEPT workaround above */ 4087 * done after the TBI_ACCEPT workaround above */
3818 length -= 4; 4088 length -= 4;
3819 4089
4090 /* probably a little skewed due to removing CRC */
4091 total_rx_bytes += length;
4092 total_rx_packets++;
4093
3820 /* code added for copybreak, this should improve 4094 /* code added for copybreak, this should improve
3821 * performance for small packets with large amounts 4095 * performance for small packets with large amounts
3822 * of reassembly being done in the stack */ 4096 * of reassembly being done in the stack */
@@ -3832,12 +4106,11 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3832 /* save the skb in buffer_info as good */ 4106 /* save the skb in buffer_info as good */
3833 buffer_info->skb = skb; 4107 buffer_info->skb = skb;
3834 skb = new_skb; 4108 skb = new_skb;
3835 skb_put(skb, length);
3836 } 4109 }
3837 } else 4110 /* else just continue with the old one */
3838 skb_put(skb, length); 4111 }
3839
3840 /* end copybreak code */ 4112 /* end copybreak code */
4113 skb_put(skb, length);
3841 4114
3842 /* Receive Checksum Offload */ 4115 /* Receive Checksum Offload */
3843 e1000_rx_checksum(adapter, 4116 e1000_rx_checksum(adapter,
@@ -3886,6 +4159,8 @@ next_desc:
3886 if (cleaned_count) 4159 if (cleaned_count)
3887 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); 4160 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3888 4161
4162 adapter->total_rx_packets += total_rx_packets;
4163 adapter->total_rx_bytes += total_rx_bytes;
3889 return cleaned; 4164 return cleaned;
3890} 4165}
3891 4166
@@ -3915,6 +4190,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3915 uint32_t length, staterr; 4190 uint32_t length, staterr;
3916 int cleaned_count = 0; 4191 int cleaned_count = 0;
3917 boolean_t cleaned = FALSE; 4192 boolean_t cleaned = FALSE;
4193 unsigned int total_rx_bytes=0, total_rx_packets=0;
3918 4194
3919 i = rx_ring->next_to_clean; 4195 i = rx_ring->next_to_clean;
3920 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 4196 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
@@ -3999,7 +4275,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3999 goto copydone; 4275 goto copydone;
4000 } /* if */ 4276 } /* if */
4001 } 4277 }
4002 4278
4003 for (j = 0; j < adapter->rx_ps_pages; j++) { 4279 for (j = 0; j < adapter->rx_ps_pages; j++) {
4004 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j]))) 4280 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
4005 break; 4281 break;
@@ -4019,6 +4295,9 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4019 pskb_trim(skb, skb->len - 4); 4295 pskb_trim(skb, skb->len - 4);
4020 4296
4021copydone: 4297copydone:
4298 total_rx_bytes += skb->len;
4299 total_rx_packets++;
4300
4022 e1000_rx_checksum(adapter, staterr, 4301 e1000_rx_checksum(adapter, staterr,
4023 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb); 4302 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
4024 skb->protocol = eth_type_trans(skb, netdev); 4303 skb->protocol = eth_type_trans(skb, netdev);
@@ -4067,6 +4346,8 @@ next_desc:
4067 if (cleaned_count) 4346 if (cleaned_count)
4068 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); 4347 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4069 4348
4349 adapter->total_rx_packets += total_rx_packets;
4350 adapter->total_rx_bytes += total_rx_bytes;
4070 return cleaned; 4351 return cleaned;
4071} 4352}
4072 4353
@@ -4234,7 +4515,7 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
4234 } 4515 }
4235 4516
4236 skb = netdev_alloc_skb(netdev, 4517 skb = netdev_alloc_skb(netdev,
4237 adapter->rx_ps_bsize0 + NET_IP_ALIGN); 4518 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
4238 4519
4239 if (unlikely(!skb)) { 4520 if (unlikely(!skb)) {
4240 adapter->alloc_rx_buff_failed++; 4521 adapter->alloc_rx_buff_failed++;
@@ -4511,7 +4792,6 @@ e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4511 return E1000_SUCCESS; 4792 return E1000_SUCCESS;
4512} 4793}
4513 4794
4514
4515void 4795void
4516e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 4796e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4517{ 4797{
@@ -4534,12 +4814,12 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4534 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4814 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4535 4815
4536 if (adapter->hw.mac_type != e1000_ich8lan) { 4816 if (adapter->hw.mac_type != e1000_ich8lan) {
4537 /* enable VLAN receive filtering */ 4817 /* enable VLAN receive filtering */
4538 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4818 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4539 rctl |= E1000_RCTL_VFE; 4819 rctl |= E1000_RCTL_VFE;
4540 rctl &= ~E1000_RCTL_CFIEN; 4820 rctl &= ~E1000_RCTL_CFIEN;
4541 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4821 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4542 e1000_update_mng_vlan(adapter); 4822 e1000_update_mng_vlan(adapter);
4543 } 4823 }
4544 } else { 4824 } else {
4545 /* disable VLAN tag insert/strip */ 4825 /* disable VLAN tag insert/strip */
@@ -4548,14 +4828,16 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4548 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4828 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4549 4829
4550 if (adapter->hw.mac_type != e1000_ich8lan) { 4830 if (adapter->hw.mac_type != e1000_ich8lan) {
4551 /* disable VLAN filtering */ 4831 /* disable VLAN filtering */
4552 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4832 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4553 rctl &= ~E1000_RCTL_VFE; 4833 rctl &= ~E1000_RCTL_VFE;
4554 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4834 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4555 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) { 4835 if (adapter->mng_vlan_id !=
4556 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4836 (uint16_t)E1000_MNG_VLAN_NONE) {
4557 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4837 e1000_vlan_rx_kill_vid(netdev,
4558 } 4838 adapter->mng_vlan_id);
4839 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4840 }
4559 } 4841 }
4560 } 4842 }
4561 4843
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index a464cb290621..18afc0c25dac 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -107,17 +107,16 @@ typedef enum {
107 107
108#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 108#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
109 109
110#define E1000_WRITE_ICH8_REG(a, reg, value) ( \ 110#define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
111 writel((value), ((a)->flash_address + reg))) 111 writel((value), ((a)->flash_address + reg)))
112 112
113#define E1000_READ_ICH8_REG(a, reg) ( \ 113#define E1000_READ_ICH_FLASH_REG(a, reg) ( \
114 readl((a)->flash_address + reg)) 114 readl((a)->flash_address + reg))
115 115
116#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \ 116#define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
117 writew((value), ((a)->flash_address + reg))) 117 writew((value), ((a)->flash_address + reg)))
118 118
119#define E1000_READ_ICH8_REG16(a, reg) ( \ 119#define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
120 readw((a)->flash_address + reg)) 120 readw((a)->flash_address + reg))
121 121
122
123#endif /* _E1000_OSDEP_H_ */ 122#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 9c3c1acefccc..cbfcd7f2889f 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -44,16 +44,6 @@
44 */ 44 */
45 45
46#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 46#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
47/* Module Parameters are always initialized to -1, so that the driver
48 * can tell the difference between no user specified value or the
49 * user asking for the default value.
50 * The true default values are loaded in when e1000_check_options is called.
51 *
52 * This is a GCC extension to ANSI C.
53 * See the item "Labeled Elements in Initializers" in the section
54 * "Extensions to the C Language Family" of the GCC documentation.
55 */
56
57#define E1000_PARAM(X, desc) \ 47#define E1000_PARAM(X, desc) \
58 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 48 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
59 static int num_##X = 0; \ 49 static int num_##X = 0; \
@@ -67,7 +57,6 @@
67 * 57 *
68 * Default Value: 256 58 * Default Value: 256
69 */ 59 */
70
71E1000_PARAM(TxDescriptors, "Number of transmit descriptors"); 60E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
72 61
73/* Receive Descriptor Count 62/* Receive Descriptor Count
@@ -77,7 +66,6 @@ E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
77 * 66 *
78 * Default Value: 256 67 * Default Value: 256
79 */ 68 */
80
81E1000_PARAM(RxDescriptors, "Number of receive descriptors"); 69E1000_PARAM(RxDescriptors, "Number of receive descriptors");
82 70
83/* User Specified Speed Override 71/* User Specified Speed Override
@@ -90,7 +78,6 @@ E1000_PARAM(RxDescriptors, "Number of receive descriptors");
90 * 78 *
91 * Default Value: 0 79 * Default Value: 0
92 */ 80 */
93
94E1000_PARAM(Speed, "Speed setting"); 81E1000_PARAM(Speed, "Speed setting");
95 82
96/* User Specified Duplex Override 83/* User Specified Duplex Override
@@ -102,7 +89,6 @@ E1000_PARAM(Speed, "Speed setting");
102 * 89 *
103 * Default Value: 0 90 * Default Value: 0
104 */ 91 */
105
106E1000_PARAM(Duplex, "Duplex setting"); 92E1000_PARAM(Duplex, "Duplex setting");
107 93
108/* Auto-negotiation Advertisement Override 94/* Auto-negotiation Advertisement Override
@@ -119,8 +105,9 @@ E1000_PARAM(Duplex, "Duplex setting");
119 * 105 *
120 * Default Value: 0x2F (copper); 0x20 (fiber) 106 * Default Value: 0x2F (copper); 0x20 (fiber)
121 */ 107 */
122
123E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting"); 108E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
109#define AUTONEG_ADV_DEFAULT 0x2F
110#define AUTONEG_ADV_MASK 0x2F
124 111
125/* User Specified Flow Control Override 112/* User Specified Flow Control Override
126 * 113 *
@@ -132,8 +119,8 @@ E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
132 * 119 *
133 * Default Value: Read flow control settings from the EEPROM 120 * Default Value: Read flow control settings from the EEPROM
134 */ 121 */
135
136E1000_PARAM(FlowControl, "Flow Control setting"); 122E1000_PARAM(FlowControl, "Flow Control setting");
123#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
137 124
138/* XsumRX - Receive Checksum Offload Enable/Disable 125/* XsumRX - Receive Checksum Offload Enable/Disable
139 * 126 *
@@ -144,53 +131,54 @@ E1000_PARAM(FlowControl, "Flow Control setting");
144 * 131 *
145 * Default Value: 1 132 * Default Value: 1
146 */ 133 */
147
148E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload"); 134E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload");
149 135
150/* Transmit Interrupt Delay in units of 1.024 microseconds 136/* Transmit Interrupt Delay in units of 1.024 microseconds
137 * Tx interrupt delay needs to typically be set to something non zero
151 * 138 *
152 * Valid Range: 0-65535 139 * Valid Range: 0-65535
153 *
154 * Default Value: 64
155 */ 140 */
156
157E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay"); 141E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
142#define DEFAULT_TIDV 8
143#define MAX_TXDELAY 0xFFFF
144#define MIN_TXDELAY 0
158 145
159/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds 146/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
160 * 147 *
161 * Valid Range: 0-65535 148 * Valid Range: 0-65535
162 *
163 * Default Value: 0
164 */ 149 */
165
166E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay"); 150E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
151#define DEFAULT_TADV 32
152#define MAX_TXABSDELAY 0xFFFF
153#define MIN_TXABSDELAY 0
167 154
168/* Receive Interrupt Delay in units of 1.024 microseconds 155/* Receive Interrupt Delay in units of 1.024 microseconds
156 * hardware will likely hang if you set this to anything but zero.
169 * 157 *
170 * Valid Range: 0-65535 158 * Valid Range: 0-65535
171 *
172 * Default Value: 0
173 */ 159 */
174
175E1000_PARAM(RxIntDelay, "Receive Interrupt Delay"); 160E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
161#define DEFAULT_RDTR 0
162#define MAX_RXDELAY 0xFFFF
163#define MIN_RXDELAY 0
176 164
177/* Receive Absolute Interrupt Delay in units of 1.024 microseconds 165/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
178 * 166 *
179 * Valid Range: 0-65535 167 * Valid Range: 0-65535
180 *
181 * Default Value: 128
182 */ 168 */
183
184E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay"); 169E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
170#define DEFAULT_RADV 8
171#define MAX_RXABSDELAY 0xFFFF
172#define MIN_RXABSDELAY 0
185 173
186/* Interrupt Throttle Rate (interrupts/sec) 174/* Interrupt Throttle Rate (interrupts/sec)
187 * 175 *
188 * Valid Range: 100-100000 (0=off, 1=dynamic) 176 * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
189 *
190 * Default Value: 8000
191 */ 177 */
192
193E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); 178E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
179#define DEFAULT_ITR 3
180#define MAX_ITR 100000
181#define MIN_ITR 100
194 182
195/* Enable Smart Power Down of the PHY 183/* Enable Smart Power Down of the PHY
196 * 184 *
@@ -198,7 +186,6 @@ E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
198 * 186 *
199 * Default Value: 0 (disabled) 187 * Default Value: 0 (disabled)
200 */ 188 */
201
202E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); 189E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
203 190
204/* Enable Kumeran Lock Loss workaround 191/* Enable Kumeran Lock Loss workaround
@@ -207,33 +194,8 @@ E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
207 * 194 *
208 * Default Value: 1 (enabled) 195 * Default Value: 1 (enabled)
209 */ 196 */
210
211E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); 197E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
212 198
213#define AUTONEG_ADV_DEFAULT 0x2F
214#define AUTONEG_ADV_MASK 0x2F
215#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
216
217#define DEFAULT_RDTR 0
218#define MAX_RXDELAY 0xFFFF
219#define MIN_RXDELAY 0
220
221#define DEFAULT_RADV 128
222#define MAX_RXABSDELAY 0xFFFF
223#define MIN_RXABSDELAY 0
224
225#define DEFAULT_TIDV 64
226#define MAX_TXDELAY 0xFFFF
227#define MIN_TXDELAY 0
228
229#define DEFAULT_TADV 64
230#define MAX_TXABSDELAY 0xFFFF
231#define MIN_TXABSDELAY 0
232
233#define DEFAULT_ITR 8000
234#define MAX_ITR 100000
235#define MIN_ITR 100
236
237struct e1000_option { 199struct e1000_option {
238 enum { enable_option, range_option, list_option } type; 200 enum { enable_option, range_option, list_option } type;
239 char *name; 201 char *name;
@@ -510,15 +472,27 @@ e1000_check_options(struct e1000_adapter *adapter)
510 break; 472 break;
511 case 1: 473 case 1:
512 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 474 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
513 opt.name); 475 opt.name);
476 adapter->itr_setting = adapter->itr;
477 adapter->itr = 20000;
478 break;
479 case 3:
480 DPRINTK(PROBE, INFO,
481 "%s set to dynamic conservative mode\n",
482 opt.name);
483 adapter->itr_setting = adapter->itr;
484 adapter->itr = 20000;
514 break; 485 break;
515 default: 486 default:
516 e1000_validate_option(&adapter->itr, &opt, 487 e1000_validate_option(&adapter->itr, &opt,
517 adapter); 488 adapter);
489 /* save the setting, because the dynamic bits change itr */
490 adapter->itr_setting = adapter->itr;
518 break; 491 break;
519 } 492 }
520 } else { 493 } else {
521 adapter->itr = opt.def; 494 adapter->itr_setting = opt.def;
495 adapter->itr = 20000;
522 } 496 }
523 } 497 }
524 { /* Smart Power Down */ 498 { /* Smart Power Down */
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index c5ed635bce36..439f41338291 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -110,6 +110,8 @@
110 * 0.55: 22 Mar 2006: Add flow control (pause frame). 110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support. 111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
112 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections. 112 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
113 * 0.58: 30 Oct 2006: Added support for sideband management unit.
114 * 0.59: 30 Oct 2006: Added support for recoverable error.
113 * 115 *
114 * Known bugs: 116 * Known bugs:
115 * We suspect that on some hardware no TX done interrupts are generated. 117 * We suspect that on some hardware no TX done interrupts are generated.
@@ -126,7 +128,7 @@
126#else 128#else
127#define DRIVERNAPI 129#define DRIVERNAPI
128#endif 130#endif
129#define FORCEDETH_VERSION "0.57" 131#define FORCEDETH_VERSION "0.59"
130#define DRV_NAME "forcedeth" 132#define DRV_NAME "forcedeth"
131 133
132#include <linux/module.h> 134#include <linux/module.h>
@@ -174,11 +176,12 @@
174#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */ 176#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
175#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */ 177#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
176#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */ 178#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
179#define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
177 180
178enum { 181enum {
179 NvRegIrqStatus = 0x000, 182 NvRegIrqStatus = 0x000,
180#define NVREG_IRQSTAT_MIIEVENT 0x040 183#define NVREG_IRQSTAT_MIIEVENT 0x040
181#define NVREG_IRQSTAT_MASK 0x1ff 184#define NVREG_IRQSTAT_MASK 0x81ff
182 NvRegIrqMask = 0x004, 185 NvRegIrqMask = 0x004,
183#define NVREG_IRQ_RX_ERROR 0x0001 186#define NVREG_IRQ_RX_ERROR 0x0001
184#define NVREG_IRQ_RX 0x0002 187#define NVREG_IRQ_RX 0x0002
@@ -189,15 +192,16 @@ enum {
189#define NVREG_IRQ_LINK 0x0040 192#define NVREG_IRQ_LINK 0x0040
190#define NVREG_IRQ_RX_FORCED 0x0080 193#define NVREG_IRQ_RX_FORCED 0x0080
191#define NVREG_IRQ_TX_FORCED 0x0100 194#define NVREG_IRQ_TX_FORCED 0x0100
195#define NVREG_IRQ_RECOVER_ERROR 0x8000
192#define NVREG_IRQMASK_THROUGHPUT 0x00df 196#define NVREG_IRQMASK_THROUGHPUT 0x00df
193#define NVREG_IRQMASK_CPU 0x0040 197#define NVREG_IRQMASK_CPU 0x0040
194#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) 198#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
195#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) 199#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
196#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK) 200#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
197 201
198#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ 202#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
199 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ 203 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
200 NVREG_IRQ_TX_FORCED)) 204 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
201 205
202 NvRegUnknownSetupReg6 = 0x008, 206 NvRegUnknownSetupReg6 = 0x008,
203#define NVREG_UNKSETUP6_VAL 3 207#define NVREG_UNKSETUP6_VAL 3
@@ -222,6 +226,15 @@ enum {
222#define NVREG_MAC_RESET_ASSERT 0x0F3 226#define NVREG_MAC_RESET_ASSERT 0x0F3
223 NvRegTransmitterControl = 0x084, 227 NvRegTransmitterControl = 0x084,
224#define NVREG_XMITCTL_START 0x01 228#define NVREG_XMITCTL_START 0x01
229#define NVREG_XMITCTL_MGMT_ST 0x40000000
230#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
231#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
232#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
233#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
234#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
235#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
236#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
237#define NVREG_XMITCTL_HOST_LOADED 0x00004000
225 NvRegTransmitterStatus = 0x088, 238 NvRegTransmitterStatus = 0x088,
226#define NVREG_XMITSTAT_BUSY 0x01 239#define NVREG_XMITSTAT_BUSY 0x01
227 240
@@ -304,8 +317,8 @@ enum {
304#define NVREG_MIISTAT_LINKCHANGE 0x0008 317#define NVREG_MIISTAT_LINKCHANGE 0x0008
305#define NVREG_MIISTAT_MASK 0x000f 318#define NVREG_MIISTAT_MASK 0x000f
306#define NVREG_MIISTAT_MASK2 0x000f 319#define NVREG_MIISTAT_MASK2 0x000f
307 NvRegUnknownSetupReg4 = 0x184, 320 NvRegMIIMask = 0x184,
308#define NVREG_UNKSETUP4_VAL 8 321#define NVREG_MII_LINKCHANGE 0x0008
309 322
310 NvRegAdapterControl = 0x188, 323 NvRegAdapterControl = 0x188,
311#define NVREG_ADAPTCTL_START 0x02 324#define NVREG_ADAPTCTL_START 0x02
@@ -707,6 +720,7 @@ struct fe_priv {
707 unsigned int phy_model; 720 unsigned int phy_model;
708 u16 gigabit; 721 u16 gigabit;
709 int intr_test; 722 int intr_test;
723 int recover_error;
710 724
711 /* General data: RO fields */ 725 /* General data: RO fields */
712 dma_addr_t ring_addr; 726 dma_addr_t ring_addr;
@@ -719,6 +733,7 @@ struct fe_priv {
719 u32 driver_data; 733 u32 driver_data;
720 u32 register_size; 734 u32 register_size;
721 int rx_csum; 735 int rx_csum;
736 u32 mac_in_use;
722 737
723 void __iomem *base; 738 void __iomem *base;
724 739
@@ -2443,6 +2458,23 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
2443 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", 2458 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2444 dev->name, events); 2459 dev->name, events);
2445 } 2460 }
2461 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2462 spin_lock(&np->lock);
2463 /* disable interrupts on the nic */
2464 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2465 writel(0, base + NvRegIrqMask);
2466 else
2467 writel(np->irqmask, base + NvRegIrqMask);
2468 pci_push(base);
2469
2470 if (!np->in_shutdown) {
2471 np->nic_poll_irq = np->irqmask;
2472 np->recover_error = 1;
2473 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2474 }
2475 spin_unlock(&np->lock);
2476 break;
2477 }
2446#ifdef CONFIG_FORCEDETH_NAPI 2478#ifdef CONFIG_FORCEDETH_NAPI
2447 if (events & NVREG_IRQ_RX_ALL) { 2479 if (events & NVREG_IRQ_RX_ALL) {
2448 netif_rx_schedule(dev); 2480 netif_rx_schedule(dev);
@@ -2673,6 +2705,20 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
2673 spin_unlock_irqrestore(&np->lock, flags); 2705 spin_unlock_irqrestore(&np->lock, flags);
2674 np->link_timeout = jiffies + LINK_TIMEOUT; 2706 np->link_timeout = jiffies + LINK_TIMEOUT;
2675 } 2707 }
2708 if (events & NVREG_IRQ_RECOVER_ERROR) {
2709 spin_lock_irq(&np->lock);
2710 /* disable interrupts on the nic */
2711 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2712 pci_push(base);
2713
2714 if (!np->in_shutdown) {
2715 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2716 np->recover_error = 1;
2717 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2718 }
2719 spin_unlock_irq(&np->lock);
2720 break;
2721 }
2676 if (events & (NVREG_IRQ_UNKNOWN)) { 2722 if (events & (NVREG_IRQ_UNKNOWN)) {
2677 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", 2723 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2678 dev->name, events); 2724 dev->name, events);
@@ -2902,6 +2948,42 @@ static void nv_do_nic_poll(unsigned long data)
2902 } 2948 }
2903 np->nic_poll_irq = 0; 2949 np->nic_poll_irq = 0;
2904 2950
2951 if (np->recover_error) {
2952 np->recover_error = 0;
2953 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
2954 if (netif_running(dev)) {
2955 netif_tx_lock_bh(dev);
2956 spin_lock(&np->lock);
2957 /* stop engines */
2958 nv_stop_rx(dev);
2959 nv_stop_tx(dev);
2960 nv_txrx_reset(dev);
2961 /* drain rx queue */
2962 nv_drain_rx(dev);
2963 nv_drain_tx(dev);
2964 /* reinit driver view of the rx queue */
2965 set_bufsize(dev);
2966 if (nv_init_ring(dev)) {
2967 if (!np->in_shutdown)
2968 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2969 }
2970 /* reinit nic view of the rx queue */
2971 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2972 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2973 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2974 base + NvRegRingSizes);
2975 pci_push(base);
2976 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2977 pci_push(base);
2978
2979 /* restart rx engine */
2980 nv_start_rx(dev);
2981 nv_start_tx(dev);
2982 spin_unlock(&np->lock);
2983 netif_tx_unlock_bh(dev);
2984 }
2985 }
2986
2905 /* FIXME: Do we need synchronize_irq(dev->irq) here? */ 2987 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2906 2988
2907 writel(mask, base + NvRegIrqMask); 2989 writel(mask, base + NvRegIrqMask);
@@ -4030,6 +4112,54 @@ static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4030 /* nothing to do */ 4112 /* nothing to do */
4031}; 4113};
4032 4114
4115/* The mgmt unit and driver use a semaphore to access the phy during init */
4116static int nv_mgmt_acquire_sema(struct net_device *dev)
4117{
4118 u8 __iomem *base = get_hwbase(dev);
4119 int i;
4120 u32 tx_ctrl, mgmt_sema;
4121
4122 for (i = 0; i < 10; i++) {
4123 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4124 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4125 break;
4126 msleep(500);
4127 }
4128
4129 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4130 return 0;
4131
4132 for (i = 0; i < 2; i++) {
4133 tx_ctrl = readl(base + NvRegTransmitterControl);
4134 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4135 writel(tx_ctrl, base + NvRegTransmitterControl);
4136
4137 /* verify that semaphore was acquired */
4138 tx_ctrl = readl(base + NvRegTransmitterControl);
4139 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4140 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4141 return 1;
4142 else
4143 udelay(50);
4144 }
4145
4146 return 0;
4147}
4148
4149/* Indicate to mgmt unit whether driver is loaded or not */
4150static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded)
4151{
4152 u8 __iomem *base = get_hwbase(dev);
4153 u32 tx_ctrl;
4154
4155 tx_ctrl = readl(base + NvRegTransmitterControl);
4156 if (loaded)
4157 tx_ctrl |= NVREG_XMITCTL_HOST_LOADED;
4158 else
4159 tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED;
4160 writel(tx_ctrl, base + NvRegTransmitterControl);
4161}
4162
4033static int nv_open(struct net_device *dev) 4163static int nv_open(struct net_device *dev)
4034{ 4164{
4035 struct fe_priv *np = netdev_priv(dev); 4165 struct fe_priv *np = netdev_priv(dev);
@@ -4085,7 +4215,7 @@ static int nv_open(struct net_device *dev)
4085 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, 4215 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4086 KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); 4216 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4087 4217
4088 writel(0, base + NvRegUnknownSetupReg4); 4218 writel(0, base + NvRegMIIMask);
4089 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 4219 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4090 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); 4220 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4091 4221
@@ -4111,7 +4241,7 @@ static int nv_open(struct net_device *dev)
4111 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, 4241 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4112 base + NvRegAdapterControl); 4242 base + NvRegAdapterControl);
4113 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); 4243 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4114 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); 4244 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4115 if (np->wolenabled) 4245 if (np->wolenabled)
4116 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); 4246 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4117 4247
@@ -4230,6 +4360,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4230 u8 __iomem *base; 4360 u8 __iomem *base;
4231 int err, i; 4361 int err, i;
4232 u32 powerstate, txreg; 4362 u32 powerstate, txreg;
4363 u32 phystate_orig = 0, phystate;
4364 int phyinitialized = 0;
4233 4365
4234 dev = alloc_etherdev(sizeof(struct fe_priv)); 4366 dev = alloc_etherdev(sizeof(struct fe_priv));
4235 err = -ENOMEM; 4367 err = -ENOMEM;
@@ -4514,6 +4646,48 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4514 np->need_linktimer = 0; 4646 np->need_linktimer = 0;
4515 } 4647 }
4516 4648
4649 /* clear phy state and temporarily halt phy interrupts */
4650 writel(0, base + NvRegMIIMask);
4651 phystate = readl(base + NvRegAdapterControl);
4652 if (phystate & NVREG_ADAPTCTL_RUNNING) {
4653 phystate_orig = 1;
4654 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4655 writel(phystate, base + NvRegAdapterControl);
4656 }
4657 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4658
4659 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4660 writel(0x1, base + 0x204); pci_push(base);
4661 msleep(500);
4662 /* management unit running on the mac? */
4663 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4664 if (np->mac_in_use) {
4665 u32 mgmt_sync;
4666 /* management unit setup the phy already? */
4667 mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4668 if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) {
4669 if (!nv_mgmt_acquire_sema(dev)) {
4670 for (i = 0; i < 5000; i++) {
4671 msleep(1);
4672 mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4673 if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY)
4674 continue;
4675 if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT)
4676 phyinitialized = 1;
4677 break;
4678 }
4679 } else {
4680 /* we need to init the phy */
4681 }
4682 } else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
4683 /* phy is inited by SMU */
4684 phyinitialized = 1;
4685 } else {
4686 /* we need to init the phy */
4687 }
4688 }
4689 }
4690
4517 /* find a suitable phy */ 4691 /* find a suitable phy */
4518 for (i = 1; i <= 32; i++) { 4692 for (i = 1; i <= 32; i++) {
4519 int id1, id2; 4693 int id1, id2;
@@ -4545,8 +4719,14 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4545 goto out_error; 4719 goto out_error;
4546 } 4720 }
4547 4721
4548 /* reset it */ 4722 if (!phyinitialized) {
4549 phy_init(dev); 4723 /* reset it */
4724 phy_init(dev);
4725 }
4726
4727 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4728 nv_mgmt_driver_loaded(dev, 1);
4729 }
4550 4730
4551 /* set default link speed settings */ 4731 /* set default link speed settings */
4552 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; 4732 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
@@ -4565,6 +4745,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
4565 return 0; 4745 return 0;
4566 4746
4567out_error: 4747out_error:
4748 if (phystate_orig)
4749 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4750 if (np->mac_in_use)
4751 nv_mgmt_driver_loaded(dev, 0);
4568 pci_set_drvdata(pci_dev, NULL); 4752 pci_set_drvdata(pci_dev, NULL);
4569out_freering: 4753out_freering:
4570 free_rings(dev); 4754 free_rings(dev);
@@ -4594,6 +4778,9 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
4594 writel(np->orig_mac[0], base + NvRegMacAddrA); 4778 writel(np->orig_mac[0], base + NvRegMacAddrA);
4595 writel(np->orig_mac[1], base + NvRegMacAddrB); 4779 writel(np->orig_mac[1], base + NvRegMacAddrB);
4596 4780
4781 if (np->mac_in_use)
4782 nv_mgmt_driver_loaded(dev, 0);
4783
4597 /* free all structures */ 4784 /* free all structures */
4598 free_rings(dev); 4785 free_rings(dev);
4599 iounmap(get_hwbase(dev)); 4786 iounmap(get_hwbase(dev));
@@ -4603,6 +4790,50 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
4603 pci_set_drvdata(pci_dev, NULL); 4790 pci_set_drvdata(pci_dev, NULL);
4604} 4791}
4605 4792
4793#ifdef CONFIG_PM
4794static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4795{
4796 struct net_device *dev = pci_get_drvdata(pdev);
4797 struct fe_priv *np = netdev_priv(dev);
4798
4799 if (!netif_running(dev))
4800 goto out;
4801
4802 netif_device_detach(dev);
4803
4804 // Gross.
4805 nv_close(dev);
4806
4807 pci_save_state(pdev);
4808 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4809 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4810out:
4811 return 0;
4812}
4813
4814static int nv_resume(struct pci_dev *pdev)
4815{
4816 struct net_device *dev = pci_get_drvdata(pdev);
4817 int rc = 0;
4818
4819 if (!netif_running(dev))
4820 goto out;
4821
4822 netif_device_attach(dev);
4823
4824 pci_set_power_state(pdev, PCI_D0);
4825 pci_restore_state(pdev);
4826 pci_enable_wake(pdev, PCI_D0, 0);
4827
4828 rc = nv_open(dev);
4829out:
4830 return rc;
4831}
4832#else
4833#define nv_suspend NULL
4834#define nv_resume NULL
4835#endif /* CONFIG_PM */
4836
4606static struct pci_device_id pci_tbl[] = { 4837static struct pci_device_id pci_tbl[] = {
4607 { /* nForce Ethernet Controller */ 4838 { /* nForce Ethernet Controller */
4608 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), 4839 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
@@ -4658,43 +4889,59 @@ static struct pci_device_id pci_tbl[] = {
4658 }, 4889 },
4659 { /* MCP55 Ethernet Controller */ 4890 { /* MCP55 Ethernet Controller */
4660 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), 4891 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4661 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4892 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4662 }, 4893 },
4663 { /* MCP55 Ethernet Controller */ 4894 { /* MCP55 Ethernet Controller */
4664 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), 4895 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4665 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4896 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4666 }, 4897 },
4667 { /* MCP61 Ethernet Controller */ 4898 { /* MCP61 Ethernet Controller */
4668 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), 4899 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4669 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4900 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4670 }, 4901 },
4671 { /* MCP61 Ethernet Controller */ 4902 { /* MCP61 Ethernet Controller */
4672 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), 4903 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4673 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4904 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4674 }, 4905 },
4675 { /* MCP61 Ethernet Controller */ 4906 { /* MCP61 Ethernet Controller */
4676 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), 4907 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4677 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4908 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4678 }, 4909 },
4679 { /* MCP61 Ethernet Controller */ 4910 { /* MCP61 Ethernet Controller */
4680 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), 4911 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4681 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4912 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4682 }, 4913 },
4683 { /* MCP65 Ethernet Controller */ 4914 { /* MCP65 Ethernet Controller */
4684 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), 4915 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4685 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4916 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4686 }, 4917 },
4687 { /* MCP65 Ethernet Controller */ 4918 { /* MCP65 Ethernet Controller */
4688 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), 4919 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4689 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4920 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4690 }, 4921 },
4691 { /* MCP65 Ethernet Controller */ 4922 { /* MCP65 Ethernet Controller */
4692 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), 4923 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4693 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4924 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4694 }, 4925 },
4695 { /* MCP65 Ethernet Controller */ 4926 { /* MCP65 Ethernet Controller */
4696 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), 4927 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4697 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, 4928 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4929 },
4930 { /* MCP67 Ethernet Controller */
4931 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
4932 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4933 },
4934 { /* MCP67 Ethernet Controller */
4935 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
4936 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4937 },
4938 { /* MCP67 Ethernet Controller */
4939 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
4940 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4941 },
4942 { /* MCP67 Ethernet Controller */
4943 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
4944 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4698 }, 4945 },
4699 {0,}, 4946 {0,},
4700}; 4947};
@@ -4704,9 +4951,10 @@ static struct pci_driver driver = {
4704 .id_table = pci_tbl, 4951 .id_table = pci_tbl,
4705 .probe = nv_probe, 4952 .probe = nv_probe,
4706 .remove = __devexit_p(nv_remove), 4953 .remove = __devexit_p(nv_remove),
4954 .suspend = nv_suspend,
4955 .resume = nv_resume,
4707}; 4956};
4708 4957
4709
4710static int __init init_nic(void) 4958static int __init init_nic(void)
4711{ 4959{
4712 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); 4960 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index cb3958704a87..889d3a13e95e 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -779,7 +779,8 @@ static int fs_init_phy(struct net_device *dev)
779 fep->oldspeed = 0; 779 fep->oldspeed = 0;
780 fep->oldduplex = -1; 780 fep->oldduplex = -1;
781 if(fep->fpi->bus_id) 781 if(fep->fpi->bus_id)
782 phydev = phy_connect(dev, fep->fpi->bus_id, &fs_adjust_link, 0); 782 phydev = phy_connect(dev, fep->fpi->bus_id, &fs_adjust_link, 0,
783 PHY_INTERFACE_MODE_MII);
783 else { 784 else {
784 printk("No phy bus ID specified in BSP code\n"); 785 printk("No phy bus ID specified in BSP code\n");
785 return -EINVAL; 786 return -EINVAL;
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index a06d8d1aaceb..baa35144134c 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -9,7 +9,7 @@
9 * Author: Andy Fleming 9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala 10 * Maintainer: Kumar Gala
11 * 11 *
12 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. 12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * 13 *
14 * This program is free software; you can redistribute it and/or modify it 14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the 15 * under the terms of the GNU General Public License as published by the
@@ -133,6 +133,9 @@ static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
133#ifdef CONFIG_GFAR_NAPI 133#ifdef CONFIG_GFAR_NAPI
134static int gfar_poll(struct net_device *dev, int *budget); 134static int gfar_poll(struct net_device *dev, int *budget);
135#endif 135#endif
136#ifdef CONFIG_NET_POLL_CONTROLLER
137static void gfar_netpoll(struct net_device *dev);
138#endif
136int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); 139int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
137static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length); 140static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
138static void gfar_vlan_rx_register(struct net_device *netdev, 141static void gfar_vlan_rx_register(struct net_device *netdev,
@@ -260,6 +263,9 @@ static int gfar_probe(struct platform_device *pdev)
260 dev->poll = gfar_poll; 263 dev->poll = gfar_poll;
261 dev->weight = GFAR_DEV_WEIGHT; 264 dev->weight = GFAR_DEV_WEIGHT;
262#endif 265#endif
266#ifdef CONFIG_NET_POLL_CONTROLLER
267 dev->poll_controller = gfar_netpoll;
268#endif
263 dev->stop = gfar_close; 269 dev->stop = gfar_close;
264 dev->get_stats = gfar_get_stats; 270 dev->get_stats = gfar_get_stats;
265 dev->change_mtu = gfar_change_mtu; 271 dev->change_mtu = gfar_change_mtu;
@@ -392,6 +398,38 @@ static int gfar_remove(struct platform_device *pdev)
392} 398}
393 399
394 400
401/* Reads the controller's registers to determine what interface
402 * connects it to the PHY.
403 */
404static phy_interface_t gfar_get_interface(struct net_device *dev)
405{
406 struct gfar_private *priv = netdev_priv(dev);
407 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
408
409 if (ecntrl & ECNTRL_SGMII_MODE)
410 return PHY_INTERFACE_MODE_SGMII;
411
412 if (ecntrl & ECNTRL_TBI_MODE) {
413 if (ecntrl & ECNTRL_REDUCED_MODE)
414 return PHY_INTERFACE_MODE_RTBI;
415 else
416 return PHY_INTERFACE_MODE_TBI;
417 }
418
419 if (ecntrl & ECNTRL_REDUCED_MODE) {
420 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
421 return PHY_INTERFACE_MODE_RMII;
422 else
423 return PHY_INTERFACE_MODE_RGMII;
424 }
425
426 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
427 return PHY_INTERFACE_MODE_GMII;
428
429 return PHY_INTERFACE_MODE_MII;
430}
431
432
395/* Initializes driver's PHY state, and attaches to the PHY. 433/* Initializes driver's PHY state, and attaches to the PHY.
396 * Returns 0 on success. 434 * Returns 0 on success.
397 */ 435 */
@@ -403,6 +441,7 @@ static int init_phy(struct net_device *dev)
403 SUPPORTED_1000baseT_Full : 0; 441 SUPPORTED_1000baseT_Full : 0;
404 struct phy_device *phydev; 442 struct phy_device *phydev;
405 char phy_id[BUS_ID_SIZE]; 443 char phy_id[BUS_ID_SIZE];
444 phy_interface_t interface;
406 445
407 priv->oldlink = 0; 446 priv->oldlink = 0;
408 priv->oldspeed = 0; 447 priv->oldspeed = 0;
@@ -410,7 +449,9 @@ static int init_phy(struct net_device *dev)
410 449
411 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id); 450 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
412 451
413 phydev = phy_connect(dev, phy_id, &adjust_link, 0); 452 interface = gfar_get_interface(dev);
453
454 phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
414 455
415 if (IS_ERR(phydev)) { 456 if (IS_ERR(phydev)) {
416 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 457 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
@@ -1536,6 +1577,33 @@ static int gfar_poll(struct net_device *dev, int *budget)
1536} 1577}
1537#endif 1578#endif
1538 1579
1580#ifdef CONFIG_NET_POLL_CONTROLLER
1581/*
1582 * Polling 'interrupt' - used by things like netconsole to send skbs
1583 * without having to re-enable interrupts. It's not called while
1584 * the interrupt routine is executing.
1585 */
1586static void gfar_netpoll(struct net_device *dev)
1587{
1588 struct gfar_private *priv = netdev_priv(dev);
1589
1590 /* If the device has multiple interrupts, run tx/rx */
1591 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1592 disable_irq(priv->interruptTransmit);
1593 disable_irq(priv->interruptReceive);
1594 disable_irq(priv->interruptError);
1595 gfar_interrupt(priv->interruptTransmit, dev);
1596 enable_irq(priv->interruptError);
1597 enable_irq(priv->interruptReceive);
1598 enable_irq(priv->interruptTransmit);
1599 } else {
1600 disable_irq(priv->interruptTransmit);
1601 gfar_interrupt(priv->interruptTransmit, dev);
1602 enable_irq(priv->interruptTransmit);
1603 }
1604}
1605#endif
1606
1539/* The interrupt handler for devices with one interrupt */ 1607/* The interrupt handler for devices with one interrupt */
1540static irqreturn_t gfar_interrupt(int irq, void *dev_id) 1608static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1541{ 1609{
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index 9e81a50cf2be..39e9e321fcbc 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -160,7 +160,10 @@ extern const char gfar_driver_version[];
160 160
161#define ECNTRL_INIT_SETTINGS 0x00001000 161#define ECNTRL_INIT_SETTINGS 0x00001000
162#define ECNTRL_TBI_MODE 0x00000020 162#define ECNTRL_TBI_MODE 0x00000020
163#define ECNTRL_REDUCED_MODE 0x00000010
163#define ECNTRL_R100 0x00000008 164#define ECNTRL_R100 0x00000008
165#define ECNTRL_REDUCED_MII_MODE 0x00000004
166#define ECNTRL_SGMII_MODE 0x00000002
164 167
165#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE 168#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
166 169
diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c
index 86b3bb9bec2d..92420f007b97 100644
--- a/drivers/net/hamradio/6pack.c
+++ b/drivers/net/hamradio/6pack.c
@@ -914,7 +914,7 @@ static void decode_prio_command(struct sixpack *sp, unsigned char cmd)
914 printk(KERN_DEBUG "6pack: protocol violation\n"); 914 printk(KERN_DEBUG "6pack: protocol violation\n");
915 else 915 else
916 sp->status = 0; 916 sp->status = 0;
917 cmd &= !SIXP_RX_DCD_MASK; 917 cmd &= ~SIXP_RX_DCD_MASK;
918 } 918 }
919 sp->status = cmd & SIXP_PRIO_DATA_MASK; 919 sp->status = cmd & SIXP_PRIO_DATA_MASK;
920 } else { /* output watchdog char if idle */ 920 } else { /* output watchdog char if idle */
diff --git a/drivers/net/hydra.c b/drivers/net/hydra.c
index 91326ea3e12b..f970bfbb9db2 100644
--- a/drivers/net/hydra.c
+++ b/drivers/net/hydra.c
@@ -31,7 +31,16 @@
31#include <asm/amigahw.h> 31#include <asm/amigahw.h>
32#include <linux/zorro.h> 32#include <linux/zorro.h>
33 33
34#include "8390.h" 34#define EI_SHIFT(x) (ei_local->reg_offset[x])
35#define ei_inb(port) in_8(port)
36#define ei_outb(val,port) out_8(port,val)
37#define ei_inb_p(port) in_8(port)
38#define ei_outb_p(val,port) out_8(port,val)
39
40static const char version[] =
41 "8390.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
42
43#include "lib8390.c"
35 44
36#define NE_EN0_DCFG (0x0e*2) 45#define NE_EN0_DCFG (0x0e*2)
37 46
@@ -100,7 +109,7 @@ static int __devinit hydra_init(struct zorro_dev *z)
100 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 109 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
101 }; 110 };
102 111
103 dev = alloc_ei_netdev(); 112 dev = ____alloc_ei_netdev(0);
104 if (!dev) 113 if (!dev)
105 return -ENOMEM; 114 return -ENOMEM;
106 SET_MODULE_OWNER(dev); 115 SET_MODULE_OWNER(dev);
@@ -117,7 +126,7 @@ static int __devinit hydra_init(struct zorro_dev *z)
117 dev->irq = IRQ_AMIGA_PORTS; 126 dev->irq = IRQ_AMIGA_PORTS;
118 127
119 /* Install the Interrupt handler */ 128 /* Install the Interrupt handler */
120 if (request_irq(IRQ_AMIGA_PORTS, ei_interrupt, IRQF_SHARED, "Hydra Ethernet", 129 if (request_irq(IRQ_AMIGA_PORTS, __ei_interrupt, IRQF_SHARED, "Hydra Ethernet",
121 dev)) { 130 dev)) {
122 free_netdev(dev); 131 free_netdev(dev);
123 return -EAGAIN; 132 return -EAGAIN;
@@ -139,10 +148,10 @@ static int __devinit hydra_init(struct zorro_dev *z)
139 dev->open = &hydra_open; 148 dev->open = &hydra_open;
140 dev->stop = &hydra_close; 149 dev->stop = &hydra_close;
141#ifdef CONFIG_NET_POLL_CONTROLLER 150#ifdef CONFIG_NET_POLL_CONTROLLER
142 dev->poll_controller = ei_poll; 151 dev->poll_controller = __ei_poll;
143#endif 152#endif
144 153
145 NS8390_init(dev, 0); 154 __NS8390_init(dev, 0);
146 155
147 err = register_netdev(dev); 156 err = register_netdev(dev);
148 if (err) { 157 if (err) {
@@ -164,7 +173,7 @@ static int __devinit hydra_init(struct zorro_dev *z)
164 173
165static int hydra_open(struct net_device *dev) 174static int hydra_open(struct net_device *dev)
166{ 175{
167 ei_open(dev); 176 __ei_open(dev);
168 return 0; 177 return 0;
169} 178}
170 179
@@ -172,7 +181,7 @@ static int hydra_close(struct net_device *dev)
172{ 181{
173 if (ei_debug > 1) 182 if (ei_debug > 1)
174 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name); 183 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name);
175 ei_close(dev); 184 __ei_close(dev);
176 return 0; 185 return 0;
177} 186}
178 187
diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c
index f56b00ee385e..f0d30cf67b5f 100644
--- a/drivers/net/ioc3-eth.c
+++ b/drivers/net/ioc3-eth.c
@@ -57,7 +57,6 @@
57#include <net/ip.h> 57#include <net/ip.h>
58 58
59#include <asm/byteorder.h> 59#include <asm/byteorder.h>
60#include <asm/checksum.h>
61#include <asm/io.h> 60#include <asm/io.h>
62#include <asm/pgtable.h> 61#include <asm/pgtable.h>
63#include <asm/uaccess.h> 62#include <asm/uaccess.h>
diff --git a/drivers/net/irda/irda-usb.c b/drivers/net/irda/irda-usb.c
index 14bda765c2fa..6e95645e7245 100644
--- a/drivers/net/irda/irda-usb.c
+++ b/drivers/net/irda/irda-usb.c
@@ -1793,10 +1793,8 @@ err_out_3:
1793err_out_2: 1793err_out_2:
1794 usb_free_urb(self->tx_urb); 1794 usb_free_urb(self->tx_urb);
1795err_out_1: 1795err_out_1:
1796 for (i = 0; i < self->max_rx_urb; i++) { 1796 for (i = 0; i < self->max_rx_urb; i++)
1797 if (self->rx_urb[i]) 1797 usb_free_urb(self->rx_urb[i]);
1798 usb_free_urb(self->rx_urb[i]);
1799 }
1800 free_netdev(net); 1798 free_netdev(net);
1801err_out: 1799err_out:
1802 return ret; 1800 return ret;
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index d1ebb91ed278..e628126c9c49 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -1248,7 +1248,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
1248 if(likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1248 if(likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1249 struct ixgb_buffer *buffer_info; 1249 struct ixgb_buffer *buffer_info;
1250 css = skb->h.raw - skb->data; 1250 css = skb->h.raw - skb->data;
1251 cso = (skb->h.raw + skb->csum) - skb->data; 1251 cso = css + skb->csum_offset;
1252 1252
1253 i = adapter->tx_ring.next_to_use; 1253 i = adapter->tx_ring.next_to_use;
1254 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i); 1254 context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
diff --git a/drivers/net/lib8390.c b/drivers/net/lib8390.c
new file mode 100644
index 000000000000..e726c06b8dc6
--- /dev/null
+++ b/drivers/net/lib8390.c
@@ -0,0 +1,1097 @@
1/* 8390.c: A general NS8390 ethernet driver core for linux. */
2/*
3 Written 1992-94 by Donald Becker.
4
5 Copyright 1993 United States Government as represented by the
6 Director, National Security Agency.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16
17 This is the chip-specific code for many 8390-based ethernet adaptors.
18 This is not a complete driver, it must be combined with board-specific
19 code such as ne.c, wd.c, 3c503.c, etc.
20
21 Seeing how at least eight drivers use this code, (not counting the
22 PCMCIA ones either) it is easy to break some card by what seems like
23 a simple innocent change. Please contact me or Donald if you think
24 you have found something that needs changing. -- PG
25
26
27 Changelog:
28
29 Paul Gortmaker : remove set_bit lock, other cleanups.
30 Paul Gortmaker : add ei_get_8390_hdr() so we can pass skb's to
31 ei_block_input() for eth_io_copy_and_sum().
32 Paul Gortmaker : exchange static int ei_pingpong for a #define,
33 also add better Tx error handling.
34 Paul Gortmaker : rewrite Rx overrun handling as per NS specs.
35 Alexey Kuznetsov : use the 8390's six bit hash multicast filter.
36 Paul Gortmaker : tweak ANK's above multicast changes a bit.
37 Paul Gortmaker : update packet statistics for v2.1.x
38 Alan Cox : support arbitary stupid port mappings on the
39 68K Macintosh. Support >16bit I/O spaces
40 Paul Gortmaker : add kmod support for auto-loading of the 8390
41 module by all drivers that require it.
42 Alan Cox : Spinlocking work, added 'BUG_83C690'
43 Paul Gortmaker : Separate out Tx timeout code from Tx path.
44 Paul Gortmaker : Remove old unused single Tx buffer code.
45 Hayato Fujiwara : Add m32r support.
46 Paul Gortmaker : use skb_padto() instead of stack scratch area
47
48 Sources:
49 The National Semiconductor LAN Databook, and the 3Com 3c503 databook.
50
51 */
52
53#include <linux/module.h>
54#include <linux/kernel.h>
55#include <linux/jiffies.h>
56#include <linux/fs.h>
57#include <linux/types.h>
58#include <linux/string.h>
59#include <linux/bitops.h>
60#include <asm/system.h>
61#include <asm/uaccess.h>
62#include <asm/io.h>
63#include <asm/irq.h>
64#include <linux/delay.h>
65#include <linux/errno.h>
66#include <linux/fcntl.h>
67#include <linux/in.h>
68#include <linux/interrupt.h>
69#include <linux/init.h>
70#include <linux/crc32.h>
71
72#include <linux/netdevice.h>
73#include <linux/etherdevice.h>
74
75#define NS8390_CORE
76#include "8390.h"
77
78#define BUG_83C690
79
80/* These are the operational function interfaces to board-specific
81 routines.
82 void reset_8390(struct net_device *dev)
83 Resets the board associated with DEV, including a hardware reset of
84 the 8390. This is only called when there is a transmit timeout, and
85 it is always followed by 8390_init().
86 void block_output(struct net_device *dev, int count, const unsigned char *buf,
87 int start_page)
88 Write the COUNT bytes of BUF to the packet buffer at START_PAGE. The
89 "page" value uses the 8390's 256-byte pages.
90 void get_8390_hdr(struct net_device *dev, struct e8390_hdr *hdr, int ring_page)
91 Read the 4 byte, page aligned 8390 header. *If* there is a
92 subsequent read, it will be of the rest of the packet.
93 void block_input(struct net_device *dev, int count, struct sk_buff *skb, int ring_offset)
94 Read COUNT bytes from the packet buffer into the skb data area. Start
95 reading from RING_OFFSET, the address as the 8390 sees it. This will always
96 follow the read of the 8390 header.
97*/
98#define ei_reset_8390 (ei_local->reset_8390)
99#define ei_block_output (ei_local->block_output)
100#define ei_block_input (ei_local->block_input)
101#define ei_get_8390_hdr (ei_local->get_8390_hdr)
102
103/* use 0 for production, 1 for verification, >2 for debug */
104#ifndef ei_debug
105int ei_debug = 1;
106#endif
107
108/* Index to functions. */
109static void ei_tx_intr(struct net_device *dev);
110static void ei_tx_err(struct net_device *dev);
111static void ei_tx_timeout(struct net_device *dev);
112static void ei_receive(struct net_device *dev);
113static void ei_rx_overrun(struct net_device *dev);
114
115/* Routines generic to NS8390-based boards. */
116static void NS8390_trigger_send(struct net_device *dev, unsigned int length,
117 int start_page);
118static void set_multicast_list(struct net_device *dev);
119static void do_set_multicast_list(struct net_device *dev);
120static void __NS8390_init(struct net_device *dev, int startp);
121
122/*
123 * SMP and the 8390 setup.
124 *
125 * The 8390 isnt exactly designed to be multithreaded on RX/TX. There is
126 * a page register that controls bank and packet buffer access. We guard
127 * this with ei_local->page_lock. Nobody should assume or set the page other
128 * than zero when the lock is not held. Lock holders must restore page 0
129 * before unlocking. Even pure readers must take the lock to protect in
130 * page 0.
131 *
132 * To make life difficult the chip can also be very slow. We therefore can't
133 * just use spinlocks. For the longer lockups we disable the irq the device
134 * sits on and hold the lock. We must hold the lock because there is a dual
135 * processor case other than interrupts (get stats/set multicast list in
136 * parallel with each other and transmit).
137 *
138 * Note: in theory we can just disable the irq on the card _but_ there is
139 * a latency on SMP irq delivery. So we can easily go "disable irq" "sync irqs"
140 * enter lock, take the queued irq. So we waddle instead of flying.
141 *
142 * Finally by special arrangement for the purpose of being generally
143 * annoying the transmit function is called bh atomic. That places
144 * restrictions on the user context callers as disable_irq won't save
145 * them.
146 */
147
148
149
150/**
151 * ei_open - Open/initialize the board.
152 * @dev: network device to initialize
153 *
154 * This routine goes all-out, setting everything
155 * up anew at each open, even though many of these registers should only
156 * need to be set once at boot.
157 */
158static int __ei_open(struct net_device *dev)
159{
160 unsigned long flags;
161 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
162
163 /* The card I/O part of the driver (e.g. 3c503) can hook a Tx timeout
164 wrapper that does e.g. media check & then calls ei_tx_timeout. */
165 if (dev->tx_timeout == NULL)
166 dev->tx_timeout = ei_tx_timeout;
167 if (dev->watchdog_timeo <= 0)
168 dev->watchdog_timeo = TX_TIMEOUT;
169
170 /*
171 * Grab the page lock so we own the register set, then call
172 * the init function.
173 */
174
175 spin_lock_irqsave(&ei_local->page_lock, flags);
176 __NS8390_init(dev, 1);
177 /* Set the flag before we drop the lock, That way the IRQ arrives
178 after its set and we get no silly warnings */
179 netif_start_queue(dev);
180 spin_unlock_irqrestore(&ei_local->page_lock, flags);
181 ei_local->irqlock = 0;
182 return 0;
183}
184
185/**
186 * ei_close - shut down network device
187 * @dev: network device to close
188 *
189 * Opposite of ei_open(). Only used when "ifconfig <devname> down" is done.
190 */
191static int __ei_close(struct net_device *dev)
192{
193 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
194 unsigned long flags;
195
196 /*
197 * Hold the page lock during close
198 */
199
200 spin_lock_irqsave(&ei_local->page_lock, flags);
201 __NS8390_init(dev, 0);
202 spin_unlock_irqrestore(&ei_local->page_lock, flags);
203 netif_stop_queue(dev);
204 return 0;
205}
206
207/**
208 * ei_tx_timeout - handle transmit time out condition
209 * @dev: network device which has apparently fallen asleep
210 *
211 * Called by kernel when device never acknowledges a transmit has
212 * completed (or failed) - i.e. never posted a Tx related interrupt.
213 */
214
215static void ei_tx_timeout(struct net_device *dev)
216{
217 unsigned long e8390_base = dev->base_addr;
218 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
219 int txsr, isr, tickssofar = jiffies - dev->trans_start;
220 unsigned long flags;
221
222#if defined(CONFIG_M32R) && defined(CONFIG_SMP)
223 unsigned long icucr;
224
225 local_irq_save(flags);
226 icucr = inl(M32R_ICU_CR1_PORTL);
227 icucr |= M32R_ICUCR_ISMOD11;
228 outl(icucr, M32R_ICU_CR1_PORTL);
229 local_irq_restore(flags);
230#endif
231 ei_local->stat.tx_errors++;
232
233 spin_lock_irqsave(&ei_local->page_lock, flags);
234 txsr = ei_inb(e8390_base+EN0_TSR);
235 isr = ei_inb(e8390_base+EN0_ISR);
236 spin_unlock_irqrestore(&ei_local->page_lock, flags);
237
238 printk(KERN_DEBUG "%s: Tx timed out, %s TSR=%#2x, ISR=%#2x, t=%d.\n",
239 dev->name, (txsr & ENTSR_ABT) ? "excess collisions." :
240 (isr) ? "lost interrupt?" : "cable problem?", txsr, isr, tickssofar);
241
242 if (!isr && !ei_local->stat.tx_packets)
243 {
244 /* The 8390 probably hasn't gotten on the cable yet. */
245 ei_local->interface_num ^= 1; /* Try a different xcvr. */
246 }
247
248 /* Ugly but a reset can be slow, yet must be protected */
249
250 disable_irq_nosync_lockdep(dev->irq);
251 spin_lock(&ei_local->page_lock);
252
253 /* Try to restart the card. Perhaps the user has fixed something. */
254 ei_reset_8390(dev);
255 __NS8390_init(dev, 1);
256
257 spin_unlock(&ei_local->page_lock);
258 enable_irq_lockdep(dev->irq);
259 netif_wake_queue(dev);
260}
261
262/**
263 * ei_start_xmit - begin packet transmission
264 * @skb: packet to be sent
265 * @dev: network device to which packet is sent
266 *
267 * Sends a packet to an 8390 network device.
268 */
269
270static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
271{
272 unsigned long e8390_base = dev->base_addr;
273 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
274 int send_length = skb->len, output_page;
275 unsigned long flags;
276 char buf[ETH_ZLEN];
277 char *data = skb->data;
278
279 if (skb->len < ETH_ZLEN) {
280 memset(buf, 0, ETH_ZLEN); /* more efficient than doing just the needed bits */
281 memcpy(buf, data, skb->len);
282 send_length = ETH_ZLEN;
283 data = buf;
284 }
285
286 /* Mask interrupts from the ethercard.
287 SMP: We have to grab the lock here otherwise the IRQ handler
288 on another CPU can flip window and race the IRQ mask set. We end
289 up trashing the mcast filter not disabling irqs if we don't lock */
290
291 spin_lock_irqsave(&ei_local->page_lock, flags);
292 ei_outb_p(0x00, e8390_base + EN0_IMR);
293 spin_unlock_irqrestore(&ei_local->page_lock, flags);
294
295
296 /*
297 * Slow phase with lock held.
298 */
299
300 disable_irq_nosync_lockdep_irqsave(dev->irq, &flags);
301
302 spin_lock(&ei_local->page_lock);
303
304 ei_local->irqlock = 1;
305
306 /*
307 * We have two Tx slots available for use. Find the first free
308 * slot, and then perform some sanity checks. With two Tx bufs,
309 * you get very close to transmitting back-to-back packets. With
310 * only one Tx buf, the transmitter sits idle while you reload the
311 * card, leaving a substantial gap between each transmitted packet.
312 */
313
314 if (ei_local->tx1 == 0)
315 {
316 output_page = ei_local->tx_start_page;
317 ei_local->tx1 = send_length;
318 if (ei_debug && ei_local->tx2 > 0)
319 printk(KERN_DEBUG "%s: idle transmitter tx2=%d, lasttx=%d, txing=%d.\n",
320 dev->name, ei_local->tx2, ei_local->lasttx, ei_local->txing);
321 }
322 else if (ei_local->tx2 == 0)
323 {
324 output_page = ei_local->tx_start_page + TX_PAGES/2;
325 ei_local->tx2 = send_length;
326 if (ei_debug && ei_local->tx1 > 0)
327 printk(KERN_DEBUG "%s: idle transmitter, tx1=%d, lasttx=%d, txing=%d.\n",
328 dev->name, ei_local->tx1, ei_local->lasttx, ei_local->txing);
329 }
330 else
331 { /* We should never get here. */
332 if (ei_debug)
333 printk(KERN_DEBUG "%s: No Tx buffers free! tx1=%d tx2=%d last=%d\n",
334 dev->name, ei_local->tx1, ei_local->tx2, ei_local->lasttx);
335 ei_local->irqlock = 0;
336 netif_stop_queue(dev);
337 ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
338 spin_unlock(&ei_local->page_lock);
339 enable_irq_lockdep_irqrestore(dev->irq, &flags);
340 ei_local->stat.tx_errors++;
341 return 1;
342 }
343
344 /*
345 * Okay, now upload the packet and trigger a send if the transmitter
346 * isn't already sending. If it is busy, the interrupt handler will
347 * trigger the send later, upon receiving a Tx done interrupt.
348 */
349
350 ei_block_output(dev, send_length, data, output_page);
351
352 if (! ei_local->txing)
353 {
354 ei_local->txing = 1;
355 NS8390_trigger_send(dev, send_length, output_page);
356 dev->trans_start = jiffies;
357 if (output_page == ei_local->tx_start_page)
358 {
359 ei_local->tx1 = -1;
360 ei_local->lasttx = -1;
361 }
362 else
363 {
364 ei_local->tx2 = -1;
365 ei_local->lasttx = -2;
366 }
367 }
368 else ei_local->txqueue++;
369
370 if (ei_local->tx1 && ei_local->tx2)
371 netif_stop_queue(dev);
372 else
373 netif_start_queue(dev);
374
375 /* Turn 8390 interrupts back on. */
376 ei_local->irqlock = 0;
377 ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
378
379 spin_unlock(&ei_local->page_lock);
380 enable_irq_lockdep_irqrestore(dev->irq, &flags);
381
382 dev_kfree_skb (skb);
383 ei_local->stat.tx_bytes += send_length;
384
385 return 0;
386}
387
388/**
389 * ei_interrupt - handle the interrupts from an 8390
390 * @irq: interrupt number
391 * @dev_id: a pointer to the net_device
392 *
393 * Handle the ether interface interrupts. We pull packets from
394 * the 8390 via the card specific functions and fire them at the networking
395 * stack. We also handle transmit completions and wake the transmit path if
396 * necessary. We also update the counters and do other housekeeping as
397 * needed.
398 */
399
400static irqreturn_t __ei_interrupt(int irq, void *dev_id)
401{
402 struct net_device *dev = dev_id;
403 unsigned long e8390_base = dev->base_addr;
404 int interrupts, nr_serviced = 0;
405 struct ei_device *ei_local = netdev_priv(dev);
406
407 /*
408 * Protect the irq test too.
409 */
410
411 spin_lock(&ei_local->page_lock);
412
413 if (ei_local->irqlock)
414 {
415#if 1 /* This might just be an interrupt for a PCI device sharing this line */
416 /* The "irqlock" check is only for testing. */
417 printk(ei_local->irqlock
418 ? "%s: Interrupted while interrupts are masked! isr=%#2x imr=%#2x.\n"
419 : "%s: Reentering the interrupt handler! isr=%#2x imr=%#2x.\n",
420 dev->name, ei_inb_p(e8390_base + EN0_ISR),
421 ei_inb_p(e8390_base + EN0_IMR));
422#endif
423 spin_unlock(&ei_local->page_lock);
424 return IRQ_NONE;
425 }
426
427 /* Change to page 0 and read the intr status reg. */
428 ei_outb_p(E8390_NODMA+E8390_PAGE0, e8390_base + E8390_CMD);
429 if (ei_debug > 3)
430 printk(KERN_DEBUG "%s: interrupt(isr=%#2.2x).\n", dev->name,
431 ei_inb_p(e8390_base + EN0_ISR));
432
433 /* !!Assumption!! -- we stay in page 0. Don't break this. */
434 while ((interrupts = ei_inb_p(e8390_base + EN0_ISR)) != 0
435 && ++nr_serviced < MAX_SERVICE)
436 {
437 if (!netif_running(dev)) {
438 printk(KERN_WARNING "%s: interrupt from stopped card\n", dev->name);
439 /* rmk - acknowledge the interrupts */
440 ei_outb_p(interrupts, e8390_base + EN0_ISR);
441 interrupts = 0;
442 break;
443 }
444 if (interrupts & ENISR_OVER)
445 ei_rx_overrun(dev);
446 else if (interrupts & (ENISR_RX+ENISR_RX_ERR))
447 {
448 /* Got a good (?) packet. */
449 ei_receive(dev);
450 }
451 /* Push the next to-transmit packet through. */
452 if (interrupts & ENISR_TX)
453 ei_tx_intr(dev);
454 else if (interrupts & ENISR_TX_ERR)
455 ei_tx_err(dev);
456
457 if (interrupts & ENISR_COUNTERS)
458 {
459 ei_local->stat.rx_frame_errors += ei_inb_p(e8390_base + EN0_COUNTER0);
460 ei_local->stat.rx_crc_errors += ei_inb_p(e8390_base + EN0_COUNTER1);
461 ei_local->stat.rx_missed_errors+= ei_inb_p(e8390_base + EN0_COUNTER2);
462 ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */
463 }
464
465 /* Ignore any RDC interrupts that make it back to here. */
466 if (interrupts & ENISR_RDC)
467 {
468 ei_outb_p(ENISR_RDC, e8390_base + EN0_ISR);
469 }
470
471 ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, e8390_base + E8390_CMD);
472 }
473
474 if (interrupts && ei_debug)
475 {
476 ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, e8390_base + E8390_CMD);
477 if (nr_serviced >= MAX_SERVICE)
478 {
479 /* 0xFF is valid for a card removal */
480 if(interrupts!=0xFF)
481 printk(KERN_WARNING "%s: Too much work at interrupt, status %#2.2x\n",
482 dev->name, interrupts);
483 ei_outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */
484 } else {
485 printk(KERN_WARNING "%s: unknown interrupt %#2x\n", dev->name, interrupts);
486 ei_outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */
487 }
488 }
489 spin_unlock(&ei_local->page_lock);
490 return IRQ_RETVAL(nr_serviced > 0);
491}
492
493#ifdef CONFIG_NET_POLL_CONTROLLER
494static void __ei_poll(struct net_device *dev)
495{
496 disable_irq_lockdep(dev->irq);
497 __ei_interrupt(dev->irq, dev);
498 enable_irq_lockdep(dev->irq);
499}
500#endif
501
502/**
503 * ei_tx_err - handle transmitter error
504 * @dev: network device which threw the exception
505 *
506 * A transmitter error has happened. Most likely excess collisions (which
507 * is a fairly normal condition). If the error is one where the Tx will
508 * have been aborted, we try and send another one right away, instead of
509 * letting the failed packet sit and collect dust in the Tx buffer. This
510 * is a much better solution as it avoids kernel based Tx timeouts, and
511 * an unnecessary card reset.
512 *
513 * Called with lock held.
514 */
515
516static void ei_tx_err(struct net_device *dev)
517{
518 unsigned long e8390_base = dev->base_addr;
519 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
520 unsigned char txsr = ei_inb_p(e8390_base+EN0_TSR);
521 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU);
522
523#ifdef VERBOSE_ERROR_DUMP
524 printk(KERN_DEBUG "%s: transmitter error (%#2x): ", dev->name, txsr);
525 if (txsr & ENTSR_ABT)
526 printk("excess-collisions ");
527 if (txsr & ENTSR_ND)
528 printk("non-deferral ");
529 if (txsr & ENTSR_CRS)
530 printk("lost-carrier ");
531 if (txsr & ENTSR_FU)
532 printk("FIFO-underrun ");
533 if (txsr & ENTSR_CDH)
534 printk("lost-heartbeat ");
535 printk("\n");
536#endif
537
538 ei_outb_p(ENISR_TX_ERR, e8390_base + EN0_ISR); /* Ack intr. */
539
540 if (tx_was_aborted)
541 ei_tx_intr(dev);
542 else
543 {
544 ei_local->stat.tx_errors++;
545 if (txsr & ENTSR_CRS) ei_local->stat.tx_carrier_errors++;
546 if (txsr & ENTSR_CDH) ei_local->stat.tx_heartbeat_errors++;
547 if (txsr & ENTSR_OWC) ei_local->stat.tx_window_errors++;
548 }
549}
550
551/**
552 * ei_tx_intr - transmit interrupt handler
553 * @dev: network device for which tx intr is handled
554 *
555 * We have finished a transmit: check for errors and then trigger the next
556 * packet to be sent. Called with lock held.
557 */
558
559static void ei_tx_intr(struct net_device *dev)
560{
561 unsigned long e8390_base = dev->base_addr;
562 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
563 int status = ei_inb(e8390_base + EN0_TSR);
564
565 ei_outb_p(ENISR_TX, e8390_base + EN0_ISR); /* Ack intr. */
566
567 /*
568 * There are two Tx buffers, see which one finished, and trigger
569 * the send of another one if it exists.
570 */
571 ei_local->txqueue--;
572
573 if (ei_local->tx1 < 0)
574 {
575 if (ei_local->lasttx != 1 && ei_local->lasttx != -1)
576 printk(KERN_ERR "%s: bogus last_tx_buffer %d, tx1=%d.\n",
577 ei_local->name, ei_local->lasttx, ei_local->tx1);
578 ei_local->tx1 = 0;
579 if (ei_local->tx2 > 0)
580 {
581 ei_local->txing = 1;
582 NS8390_trigger_send(dev, ei_local->tx2, ei_local->tx_start_page + 6);
583 dev->trans_start = jiffies;
584 ei_local->tx2 = -1,
585 ei_local->lasttx = 2;
586 }
587 else ei_local->lasttx = 20, ei_local->txing = 0;
588 }
589 else if (ei_local->tx2 < 0)
590 {
591 if (ei_local->lasttx != 2 && ei_local->lasttx != -2)
592 printk("%s: bogus last_tx_buffer %d, tx2=%d.\n",
593 ei_local->name, ei_local->lasttx, ei_local->tx2);
594 ei_local->tx2 = 0;
595 if (ei_local->tx1 > 0)
596 {
597 ei_local->txing = 1;
598 NS8390_trigger_send(dev, ei_local->tx1, ei_local->tx_start_page);
599 dev->trans_start = jiffies;
600 ei_local->tx1 = -1;
601 ei_local->lasttx = 1;
602 }
603 else
604 ei_local->lasttx = 10, ei_local->txing = 0;
605 }
606// else printk(KERN_WARNING "%s: unexpected TX-done interrupt, lasttx=%d.\n",
607// dev->name, ei_local->lasttx);
608
609 /* Minimize Tx latency: update the statistics after we restart TXing. */
610 if (status & ENTSR_COL)
611 ei_local->stat.collisions++;
612 if (status & ENTSR_PTX)
613 ei_local->stat.tx_packets++;
614 else
615 {
616 ei_local->stat.tx_errors++;
617 if (status & ENTSR_ABT)
618 {
619 ei_local->stat.tx_aborted_errors++;
620 ei_local->stat.collisions += 16;
621 }
622 if (status & ENTSR_CRS)
623 ei_local->stat.tx_carrier_errors++;
624 if (status & ENTSR_FU)
625 ei_local->stat.tx_fifo_errors++;
626 if (status & ENTSR_CDH)
627 ei_local->stat.tx_heartbeat_errors++;
628 if (status & ENTSR_OWC)
629 ei_local->stat.tx_window_errors++;
630 }
631 netif_wake_queue(dev);
632}
633
634/**
635 * ei_receive - receive some packets
636 * @dev: network device with which receive will be run
637 *
638 * We have a good packet(s), get it/them out of the buffers.
639 * Called with lock held.
640 */
641
642static void ei_receive(struct net_device *dev)
643{
644 unsigned long e8390_base = dev->base_addr;
645 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
646 unsigned char rxing_page, this_frame, next_frame;
647 unsigned short current_offset;
648 int rx_pkt_count = 0;
649 struct e8390_pkt_hdr rx_frame;
650 int num_rx_pages = ei_local->stop_page-ei_local->rx_start_page;
651
652 while (++rx_pkt_count < 10)
653 {
654 int pkt_len, pkt_stat;
655
656 /* Get the rx page (incoming packet pointer). */
657 ei_outb_p(E8390_NODMA+E8390_PAGE1, e8390_base + E8390_CMD);
658 rxing_page = ei_inb_p(e8390_base + EN1_CURPAG);
659 ei_outb_p(E8390_NODMA+E8390_PAGE0, e8390_base + E8390_CMD);
660
661 /* Remove one frame from the ring. Boundary is always a page behind. */
662 this_frame = ei_inb_p(e8390_base + EN0_BOUNDARY) + 1;
663 if (this_frame >= ei_local->stop_page)
664 this_frame = ei_local->rx_start_page;
665
666 /* Someday we'll omit the previous, iff we never get this message.
667 (There is at least one clone claimed to have a problem.)
668
669 Keep quiet if it looks like a card removal. One problem here
670 is that some clones crash in roughly the same way.
671 */
672 if (ei_debug > 0 && this_frame != ei_local->current_page && (this_frame!=0x0 || rxing_page!=0xFF))
673 printk(KERN_ERR "%s: mismatched read page pointers %2x vs %2x.\n",
674 dev->name, this_frame, ei_local->current_page);
675
676 if (this_frame == rxing_page) /* Read all the frames? */
677 break; /* Done for now */
678
679 current_offset = this_frame << 8;
680 ei_get_8390_hdr(dev, &rx_frame, this_frame);
681
682 pkt_len = rx_frame.count - sizeof(struct e8390_pkt_hdr);
683 pkt_stat = rx_frame.status;
684
685 next_frame = this_frame + 1 + ((pkt_len+4)>>8);
686
687 /* Check for bogosity warned by 3c503 book: the status byte is never
688 written. This happened a lot during testing! This code should be
689 cleaned up someday. */
690 if (rx_frame.next != next_frame
691 && rx_frame.next != next_frame + 1
692 && rx_frame.next != next_frame - num_rx_pages
693 && rx_frame.next != next_frame + 1 - num_rx_pages) {
694 ei_local->current_page = rxing_page;
695 ei_outb(ei_local->current_page-1, e8390_base+EN0_BOUNDARY);
696 ei_local->stat.rx_errors++;
697 continue;
698 }
699
700 if (pkt_len < 60 || pkt_len > 1518)
701 {
702 if (ei_debug)
703 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x nxpg=%#2x.\n",
704 dev->name, rx_frame.count, rx_frame.status,
705 rx_frame.next);
706 ei_local->stat.rx_errors++;
707 ei_local->stat.rx_length_errors++;
708 }
709 else if ((pkt_stat & 0x0F) == ENRSR_RXOK)
710 {
711 struct sk_buff *skb;
712
713 skb = dev_alloc_skb(pkt_len+2);
714 if (skb == NULL)
715 {
716 if (ei_debug > 1)
717 printk(KERN_DEBUG "%s: Couldn't allocate a sk_buff of size %d.\n",
718 dev->name, pkt_len);
719 ei_local->stat.rx_dropped++;
720 break;
721 }
722 else
723 {
724 skb_reserve(skb,2); /* IP headers on 16 byte boundaries */
725 skb->dev = dev;
726 skb_put(skb, pkt_len); /* Make room */
727 ei_block_input(dev, pkt_len, skb, current_offset + sizeof(rx_frame));
728 skb->protocol=eth_type_trans(skb,dev);
729 netif_rx(skb);
730 dev->last_rx = jiffies;
731 ei_local->stat.rx_packets++;
732 ei_local->stat.rx_bytes += pkt_len;
733 if (pkt_stat & ENRSR_PHY)
734 ei_local->stat.multicast++;
735 }
736 }
737 else
738 {
739 if (ei_debug)
740 printk(KERN_DEBUG "%s: bogus packet: status=%#2x nxpg=%#2x size=%d\n",
741 dev->name, rx_frame.status, rx_frame.next,
742 rx_frame.count);
743 ei_local->stat.rx_errors++;
744 /* NB: The NIC counts CRC, frame and missed errors. */
745 if (pkt_stat & ENRSR_FO)
746 ei_local->stat.rx_fifo_errors++;
747 }
748 next_frame = rx_frame.next;
749
750 /* This _should_ never happen: it's here for avoiding bad clones. */
751 if (next_frame >= ei_local->stop_page) {
752 printk("%s: next frame inconsistency, %#2x\n", dev->name,
753 next_frame);
754 next_frame = ei_local->rx_start_page;
755 }
756 ei_local->current_page = next_frame;
757 ei_outb_p(next_frame-1, e8390_base+EN0_BOUNDARY);
758 }
759
760 /* We used to also ack ENISR_OVER here, but that would sometimes mask
761 a real overrun, leaving the 8390 in a stopped state with rec'vr off. */
762 ei_outb_p(ENISR_RX+ENISR_RX_ERR, e8390_base+EN0_ISR);
763 return;
764}
765
766/**
767 * ei_rx_overrun - handle receiver overrun
768 * @dev: network device which threw exception
769 *
770 * We have a receiver overrun: we have to kick the 8390 to get it started
771 * again. Problem is that you have to kick it exactly as NS prescribes in
772 * the updated datasheets, or "the NIC may act in an unpredictable manner."
773 * This includes causing "the NIC to defer indefinitely when it is stopped
774 * on a busy network." Ugh.
775 * Called with lock held. Don't call this with the interrupts off or your
776 * computer will hate you - it takes 10ms or so.
777 */
778
779static void ei_rx_overrun(struct net_device *dev)
780{
781 unsigned long e8390_base = dev->base_addr;
782 unsigned char was_txing, must_resend = 0;
783 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
784
785 /*
786 * Record whether a Tx was in progress and then issue the
787 * stop command.
788 */
789 was_txing = ei_inb_p(e8390_base+E8390_CMD) & E8390_TRANS;
790 ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD);
791
792 if (ei_debug > 1)
793 printk(KERN_DEBUG "%s: Receiver overrun.\n", dev->name);
794 ei_local->stat.rx_over_errors++;
795
796 /*
797 * Wait a full Tx time (1.2ms) + some guard time, NS says 1.6ms total.
798 * Early datasheets said to poll the reset bit, but now they say that
799 * it "is not a reliable indicator and subsequently should be ignored."
800 * We wait at least 10ms.
801 */
802
803 mdelay(10);
804
805 /*
806 * Reset RBCR[01] back to zero as per magic incantation.
807 */
808 ei_outb_p(0x00, e8390_base+EN0_RCNTLO);
809 ei_outb_p(0x00, e8390_base+EN0_RCNTHI);
810
811 /*
812 * See if any Tx was interrupted or not. According to NS, this
813 * step is vital, and skipping it will cause no end of havoc.
814 */
815
816 if (was_txing)
817 {
818 unsigned char tx_completed = ei_inb_p(e8390_base+EN0_ISR) & (ENISR_TX+ENISR_TX_ERR);
819 if (!tx_completed)
820 must_resend = 1;
821 }
822
823 /*
824 * Have to enter loopback mode and then restart the NIC before
825 * you are allowed to slurp packets up off the ring.
826 */
827 ei_outb_p(E8390_TXOFF, e8390_base + EN0_TXCR);
828 ei_outb_p(E8390_NODMA + E8390_PAGE0 + E8390_START, e8390_base + E8390_CMD);
829
830 /*
831 * Clear the Rx ring of all the debris, and ack the interrupt.
832 */
833 ei_receive(dev);
834 ei_outb_p(ENISR_OVER, e8390_base+EN0_ISR);
835
836 /*
837 * Leave loopback mode, and resend any packet that got stopped.
838 */
839 ei_outb_p(E8390_TXCONFIG, e8390_base + EN0_TXCR);
840 if (must_resend)
841 ei_outb_p(E8390_NODMA + E8390_PAGE0 + E8390_START + E8390_TRANS, e8390_base + E8390_CMD);
842}
843
844/*
845 * Collect the stats. This is called unlocked and from several contexts.
846 */
847
848static struct net_device_stats *get_stats(struct net_device *dev)
849{
850 unsigned long ioaddr = dev->base_addr;
851 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
852 unsigned long flags;
853
854 /* If the card is stopped, just return the present stats. */
855 if (!netif_running(dev))
856 return &ei_local->stat;
857
858 spin_lock_irqsave(&ei_local->page_lock,flags);
859 /* Read the counter registers, assuming we are in page 0. */
860 ei_local->stat.rx_frame_errors += ei_inb_p(ioaddr + EN0_COUNTER0);
861 ei_local->stat.rx_crc_errors += ei_inb_p(ioaddr + EN0_COUNTER1);
862 ei_local->stat.rx_missed_errors+= ei_inb_p(ioaddr + EN0_COUNTER2);
863 spin_unlock_irqrestore(&ei_local->page_lock, flags);
864
865 return &ei_local->stat;
866}
867
868/*
869 * Form the 64 bit 8390 multicast table from the linked list of addresses
870 * associated with this dev structure.
871 */
872
873static inline void make_mc_bits(u8 *bits, struct net_device *dev)
874{
875 struct dev_mc_list *dmi;
876
877 for (dmi=dev->mc_list; dmi; dmi=dmi->next)
878 {
879 u32 crc;
880 if (dmi->dmi_addrlen != ETH_ALEN)
881 {
882 printk(KERN_INFO "%s: invalid multicast address length given.\n", dev->name);
883 continue;
884 }
885 crc = ether_crc(ETH_ALEN, dmi->dmi_addr);
886 /*
887 * The 8390 uses the 6 most significant bits of the
888 * CRC to index the multicast table.
889 */
890 bits[crc>>29] |= (1<<((crc>>26)&7));
891 }
892}
893
894/**
895 * do_set_multicast_list - set/clear multicast filter
896 * @dev: net device for which multicast filter is adjusted
897 *
898 * Set or clear the multicast filter for this adaptor. May be called
899 * from a BH in 2.1.x. Must be called with lock held.
900 */
901
902static void do_set_multicast_list(struct net_device *dev)
903{
904 unsigned long e8390_base = dev->base_addr;
905 int i;
906 struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
907
908 if (!(dev->flags&(IFF_PROMISC|IFF_ALLMULTI)))
909 {
910 memset(ei_local->mcfilter, 0, 8);
911 if (dev->mc_list)
912 make_mc_bits(ei_local->mcfilter, dev);
913 }
914 else
915 memset(ei_local->mcfilter, 0xFF, 8); /* mcast set to accept-all */
916
917 /*
918 * DP8390 manuals don't specify any magic sequence for altering
919 * the multicast regs on an already running card. To be safe, we
920 * ensure multicast mode is off prior to loading up the new hash
921 * table. If this proves to be not enough, we can always resort
922 * to stopping the NIC, loading the table and then restarting.
923 *
924 * Bug Alert! The MC regs on the SMC 83C690 (SMC Elite and SMC
925 * Elite16) appear to be write-only. The NS 8390 data sheet lists
926 * them as r/w so this is a bug. The SMC 83C790 (SMC Ultra and
927 * Ultra32 EISA) appears to have this bug fixed.
928 */
929
930 if (netif_running(dev))
931 ei_outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR);
932 ei_outb_p(E8390_NODMA + E8390_PAGE1, e8390_base + E8390_CMD);
933 for(i = 0; i < 8; i++)
934 {
935 ei_outb_p(ei_local->mcfilter[i], e8390_base + EN1_MULT_SHIFT(i));
936#ifndef BUG_83C690
937 if(ei_inb_p(e8390_base + EN1_MULT_SHIFT(i))!=ei_local->mcfilter[i])
938 printk(KERN_ERR "Multicast filter read/write mismap %d\n",i);
939#endif
940 }
941 ei_outb_p(E8390_NODMA + E8390_PAGE0, e8390_base + E8390_CMD);
942
943 if(dev->flags&IFF_PROMISC)
944 ei_outb_p(E8390_RXCONFIG | 0x18, e8390_base + EN0_RXCR);
945 else if(dev->flags&IFF_ALLMULTI || dev->mc_list)
946 ei_outb_p(E8390_RXCONFIG | 0x08, e8390_base + EN0_RXCR);
947 else
948 ei_outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR);
949 }
950
951/*
952 * Called without lock held. This is invoked from user context and may
953 * be parallel to just about everything else. Its also fairly quick and
954 * not called too often. Must protect against both bh and irq users
955 */
956
957static void set_multicast_list(struct net_device *dev)
958{
959 unsigned long flags;
960 struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
961
962 spin_lock_irqsave(&ei_local->page_lock, flags);
963 do_set_multicast_list(dev);
964 spin_unlock_irqrestore(&ei_local->page_lock, flags);
965}
966
967/**
968 * ethdev_setup - init rest of 8390 device struct
969 * @dev: network device structure to init
970 *
971 * Initialize the rest of the 8390 device structure. Do NOT __init
972 * this, as it is used by 8390 based modular drivers too.
973 */
974
975static void ethdev_setup(struct net_device *dev)
976{
977 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
978 if (ei_debug > 1)
979 printk(version);
980
981 dev->hard_start_xmit = &ei_start_xmit;
982 dev->get_stats = get_stats;
983 dev->set_multicast_list = &set_multicast_list;
984
985 ether_setup(dev);
986
987 spin_lock_init(&ei_local->page_lock);
988}
989
990/**
991 * alloc_ei_netdev - alloc_etherdev counterpart for 8390
992 * @size: extra bytes to allocate
993 *
994 * Allocate 8390-specific net_device.
995 */
996static struct net_device *____alloc_ei_netdev(int size)
997{
998 return alloc_netdev(sizeof(struct ei_device) + size, "eth%d",
999 ethdev_setup);
1000}
1001
1002
1003
1004
1005/* This page of functions should be 8390 generic */
1006/* Follow National Semi's recommendations for initializing the "NIC". */
1007
1008/**
1009 * NS8390_init - initialize 8390 hardware
1010 * @dev: network device to initialize
1011 * @startp: boolean. non-zero value to initiate chip processing
1012 *
1013 * Must be called with lock held.
1014 */
1015
1016static void __NS8390_init(struct net_device *dev, int startp)
1017{
1018 unsigned long e8390_base = dev->base_addr;
1019 struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
1020 int i;
1021 int endcfg = ei_local->word16
1022 ? (0x48 | ENDCFG_WTS | (ei_local->bigendian ? ENDCFG_BOS : 0))
1023 : 0x48;
1024
1025 if(sizeof(struct e8390_pkt_hdr)!=4)
1026 panic("8390.c: header struct mispacked\n");
1027 /* Follow National Semi's recommendations for initing the DP83902. */
1028 ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD); /* 0x21 */
1029 ei_outb_p(endcfg, e8390_base + EN0_DCFG); /* 0x48 or 0x49 */
1030 /* Clear the remote byte count registers. */
1031 ei_outb_p(0x00, e8390_base + EN0_RCNTLO);
1032 ei_outb_p(0x00, e8390_base + EN0_RCNTHI);
1033 /* Set to monitor and loopback mode -- this is vital!. */
1034 ei_outb_p(E8390_RXOFF, e8390_base + EN0_RXCR); /* 0x20 */
1035 ei_outb_p(E8390_TXOFF, e8390_base + EN0_TXCR); /* 0x02 */
1036 /* Set the transmit page and receive ring. */
1037 ei_outb_p(ei_local->tx_start_page, e8390_base + EN0_TPSR);
1038 ei_local->tx1 = ei_local->tx2 = 0;
1039 ei_outb_p(ei_local->rx_start_page, e8390_base + EN0_STARTPG);
1040 ei_outb_p(ei_local->stop_page-1, e8390_base + EN0_BOUNDARY); /* 3c503 says 0x3f,NS0x26*/
1041 ei_local->current_page = ei_local->rx_start_page; /* assert boundary+1 */
1042 ei_outb_p(ei_local->stop_page, e8390_base + EN0_STOPPG);
1043 /* Clear the pending interrupts and mask. */
1044 ei_outb_p(0xFF, e8390_base + EN0_ISR);
1045 ei_outb_p(0x00, e8390_base + EN0_IMR);
1046
1047 /* Copy the station address into the DS8390 registers. */
1048
1049 ei_outb_p(E8390_NODMA + E8390_PAGE1 + E8390_STOP, e8390_base+E8390_CMD); /* 0x61 */
1050 for(i = 0; i < 6; i++)
1051 {
1052 ei_outb_p(dev->dev_addr[i], e8390_base + EN1_PHYS_SHIFT(i));
1053 if (ei_debug > 1 && ei_inb_p(e8390_base + EN1_PHYS_SHIFT(i))!=dev->dev_addr[i])
1054 printk(KERN_ERR "Hw. address read/write mismap %d\n",i);
1055 }
1056
1057 ei_outb_p(ei_local->rx_start_page, e8390_base + EN1_CURPAG);
1058 ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD);
1059
1060 netif_start_queue(dev);
1061 ei_local->tx1 = ei_local->tx2 = 0;
1062 ei_local->txing = 0;
1063
1064 if (startp)
1065 {
1066 ei_outb_p(0xff, e8390_base + EN0_ISR);
1067 ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
1068 ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, e8390_base+E8390_CMD);
1069 ei_outb_p(E8390_TXCONFIG, e8390_base + EN0_TXCR); /* xmit on. */
1070 /* 3c503 TechMan says rxconfig only after the NIC is started. */
1071 ei_outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR); /* rx on, */
1072 do_set_multicast_list(dev); /* (re)load the mcast table */
1073 }
1074}
1075
1076/* Trigger a transmit start, assuming the length is valid.
1077 Always called with the page lock held */
1078
1079static void NS8390_trigger_send(struct net_device *dev, unsigned int length,
1080 int start_page)
1081{
1082 unsigned long e8390_base = dev->base_addr;
1083 struct ei_device *ei_local __attribute((unused)) = (struct ei_device *) netdev_priv(dev);
1084
1085 ei_outb_p(E8390_NODMA+E8390_PAGE0, e8390_base+E8390_CMD);
1086
1087 if (ei_inb_p(e8390_base + E8390_CMD) & E8390_TRANS)
1088 {
1089 printk(KERN_WARNING "%s: trigger_send() called with the transmitter busy.\n",
1090 dev->name);
1091 return;
1092 }
1093 ei_outb_p(length & 0xff, e8390_base + EN0_TCNTLO);
1094 ei_outb_p(length >> 8, e8390_base + EN0_TCNTHI);
1095 ei_outb_p(start_page, e8390_base + EN0_TPSR);
1096 ei_outb_p(E8390_NODMA+E8390_TRANS+E8390_START, e8390_base+E8390_CMD);
1097}
diff --git a/drivers/net/mac8390.c b/drivers/net/mac8390.c
index ade6ff852e1a..a12bb64e3694 100644
--- a/drivers/net/mac8390.c
+++ b/drivers/net/mac8390.c
@@ -39,7 +39,16 @@
39#include <asm/hwtest.h> 39#include <asm/hwtest.h>
40#include <asm/macints.h> 40#include <asm/macints.h>
41 41
42#include "8390.h" 42static char version[] =
43 "mac8390.c: v0.4 2001-05-15 David Huggins-Daines <dhd@debian.org> and others\n";
44
45#define EI_SHIFT(x) (ei_local->reg_offset[x])
46#define ei_inb(port) in_8(port)
47#define ei_outb(val,port) out_8(port,val)
48#define ei_inb_p(port) in_8(port)
49#define ei_outb_p(val,port) out_8(port,val)
50
51#include "lib8390.c"
43 52
44#define WD_START_PG 0x00 /* First page of TX buffer */ 53#define WD_START_PG 0x00 /* First page of TX buffer */
45#define CABLETRON_RX_START_PG 0x00 /* First page of RX buffer */ 54#define CABLETRON_RX_START_PG 0x00 /* First page of RX buffer */
@@ -116,9 +125,6 @@ static int useresources[] = {
116 1, /* dayna-lc */ 125 1, /* dayna-lc */
117}; 126};
118 127
119static char version[] __initdata =
120 "mac8390.c: v0.4 2001-05-15 David Huggins-Daines <dhd@debian.org> and others\n";
121
122extern enum mac8390_type mac8390_ident(struct nubus_dev * dev); 128extern enum mac8390_type mac8390_ident(struct nubus_dev * dev);
123extern int mac8390_memsize(unsigned long membase); 129extern int mac8390_memsize(unsigned long membase);
124extern int mac8390_memtest(struct net_device * dev); 130extern int mac8390_memtest(struct net_device * dev);
@@ -237,7 +243,7 @@ struct net_device * __init mac8390_probe(int unit)
237 if (!MACH_IS_MAC) 243 if (!MACH_IS_MAC)
238 return ERR_PTR(-ENODEV); 244 return ERR_PTR(-ENODEV);
239 245
240 dev = alloc_ei_netdev(); 246 dev = ____alloc_ei_netdev(0);
241 if (!dev) 247 if (!dev)
242 return ERR_PTR(-ENOMEM); 248 return ERR_PTR(-ENOMEM);
243 249
@@ -438,7 +444,7 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd
438 dev->open = &mac8390_open; 444 dev->open = &mac8390_open;
439 dev->stop = &mac8390_close; 445 dev->stop = &mac8390_close;
440#ifdef CONFIG_NET_POLL_CONTROLLER 446#ifdef CONFIG_NET_POLL_CONTROLLER
441 dev->poll_controller = ei_poll; 447 dev->poll_controller = __ei_poll;
442#endif 448#endif
443 449
444 /* GAR, ei_status is actually a macro even though it looks global */ 450 /* GAR, ei_status is actually a macro even though it looks global */
@@ -510,7 +516,7 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd
510 return -ENODEV; 516 return -ENODEV;
511 } 517 }
512 518
513 NS8390_init(dev, 0); 519 __NS8390_init(dev, 0);
514 520
515 /* Good, done, now spit out some messages */ 521 /* Good, done, now spit out some messages */
516 printk(KERN_INFO "%s: %s in slot %X (type %s)\n", 522 printk(KERN_INFO "%s: %s in slot %X (type %s)\n",
@@ -532,8 +538,8 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd
532 538
533static int mac8390_open(struct net_device *dev) 539static int mac8390_open(struct net_device *dev)
534{ 540{
535 ei_open(dev); 541 __ei_open(dev);
536 if (request_irq(dev->irq, ei_interrupt, 0, "8390 Ethernet", dev)) { 542 if (request_irq(dev->irq, __ei_interrupt, 0, "8390 Ethernet", dev)) {
537 printk ("%s: unable to get IRQ %d.\n", dev->name, dev->irq); 543 printk ("%s: unable to get IRQ %d.\n", dev->name, dev->irq);
538 return -EAGAIN; 544 return -EAGAIN;
539 } 545 }
@@ -543,7 +549,7 @@ static int mac8390_open(struct net_device *dev)
543static int mac8390_close(struct net_device *dev) 549static int mac8390_close(struct net_device *dev)
544{ 550{
545 free_irq(dev->irq, dev); 551 free_irq(dev->irq, dev);
546 ei_close(dev); 552 __ei_close(dev);
547 return 0; 553 return 0;
548} 554}
549 555
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
new file mode 100644
index 000000000000..bd0ce98c939c
--- /dev/null
+++ b/drivers/net/macb.c
@@ -0,0 +1,1210 @@
1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/slab.h>
17#include <linux/init.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/mii.h>
21#include <linux/mutex.h>
22#include <linux/dma-mapping.h>
23#include <linux/ethtool.h>
24#include <linux/platform_device.h>
25
26#include <asm/arch/board.h>
27
28#include "macb.h"
29
30#define to_net_dev(class) container_of(class, struct net_device, class_dev)
31
32#define RX_BUFFER_SIZE 128
33#define RX_RING_SIZE 512
34#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
35
36/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
37#define RX_OFFSET 2
38
39#define TX_RING_SIZE 128
40#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
41#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
42
43#define TX_RING_GAP(bp) \
44 (TX_RING_SIZE - (bp)->tx_pending)
45#define TX_BUFFS_AVAIL(bp) \
46 (((bp)->tx_tail <= (bp)->tx_head) ? \
47 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
48 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
49#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
50
51#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
52
53/* minimum number of free TX descriptors before waking up TX process */
54#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
55
56#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
57 | MACB_BIT(ISR_ROVR))
58
59static void __macb_set_hwaddr(struct macb *bp)
60{
61 u32 bottom;
62 u16 top;
63
64 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
65 macb_writel(bp, SA1B, bottom);
66 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
67 macb_writel(bp, SA1T, top);
68}
69
70static void __init macb_get_hwaddr(struct macb *bp)
71{
72 u32 bottom;
73 u16 top;
74 u8 addr[6];
75
76 bottom = macb_readl(bp, SA1B);
77 top = macb_readl(bp, SA1T);
78
79 addr[0] = bottom & 0xff;
80 addr[1] = (bottom >> 8) & 0xff;
81 addr[2] = (bottom >> 16) & 0xff;
82 addr[3] = (bottom >> 24) & 0xff;
83 addr[4] = top & 0xff;
84 addr[5] = (top >> 8) & 0xff;
85
86 if (is_valid_ether_addr(addr))
87 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
88}
89
90static void macb_enable_mdio(struct macb *bp)
91{
92 unsigned long flags;
93 u32 reg;
94
95 spin_lock_irqsave(&bp->lock, flags);
96 reg = macb_readl(bp, NCR);
97 reg |= MACB_BIT(MPE);
98 macb_writel(bp, NCR, reg);
99 macb_writel(bp, IER, MACB_BIT(MFD));
100 spin_unlock_irqrestore(&bp->lock, flags);
101}
102
103static void macb_disable_mdio(struct macb *bp)
104{
105 unsigned long flags;
106 u32 reg;
107
108 spin_lock_irqsave(&bp->lock, flags);
109 reg = macb_readl(bp, NCR);
110 reg &= ~MACB_BIT(MPE);
111 macb_writel(bp, NCR, reg);
112 macb_writel(bp, IDR, MACB_BIT(MFD));
113 spin_unlock_irqrestore(&bp->lock, flags);
114}
115
116static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
117{
118 struct macb *bp = netdev_priv(dev);
119 int value;
120
121 mutex_lock(&bp->mdio_mutex);
122
123 macb_enable_mdio(bp);
124 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
125 | MACB_BF(RW, MACB_MAN_READ)
126 | MACB_BF(PHYA, phy_id)
127 | MACB_BF(REGA, location)
128 | MACB_BF(CODE, MACB_MAN_CODE)));
129
130 wait_for_completion(&bp->mdio_complete);
131
132 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
133 macb_disable_mdio(bp);
134 mutex_unlock(&bp->mdio_mutex);
135
136 return value;
137}
138
139static void macb_mdio_write(struct net_device *dev, int phy_id,
140 int location, int val)
141{
142 struct macb *bp = netdev_priv(dev);
143
144 dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
145 phy_id, location, val);
146
147 mutex_lock(&bp->mdio_mutex);
148 macb_enable_mdio(bp);
149
150 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
151 | MACB_BF(RW, MACB_MAN_WRITE)
152 | MACB_BF(PHYA, phy_id)
153 | MACB_BF(REGA, location)
154 | MACB_BF(CODE, MACB_MAN_CODE)
155 | MACB_BF(DATA, val)));
156
157 wait_for_completion(&bp->mdio_complete);
158
159 macb_disable_mdio(bp);
160 mutex_unlock(&bp->mdio_mutex);
161}
162
163static int macb_phy_probe(struct macb *bp)
164{
165 int phy_address;
166 u16 phyid1, phyid2;
167
168 for (phy_address = 0; phy_address < 32; phy_address++) {
169 phyid1 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID1);
170 phyid2 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID2);
171
172 if (phyid1 != 0xffff && phyid1 != 0x0000
173 && phyid2 != 0xffff && phyid2 != 0x0000)
174 break;
175 }
176
177 if (phy_address == 32)
178 return -ENODEV;
179
180 dev_info(&bp->pdev->dev,
181 "detected PHY at address %d (ID %04x:%04x)\n",
182 phy_address, phyid1, phyid2);
183
184 bp->mii.phy_id = phy_address;
185 return 0;
186}
187
188static void macb_set_media(struct macb *bp, int media)
189{
190 u32 reg;
191
192 spin_lock_irq(&bp->lock);
193 reg = macb_readl(bp, NCFGR);
194 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
195 if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
196 reg |= MACB_BIT(SPD);
197 if (media & ADVERTISE_FULL)
198 reg |= MACB_BIT(FD);
199 macb_writel(bp, NCFGR, reg);
200 spin_unlock_irq(&bp->lock);
201}
202
203static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
204{
205 struct mii_if_info *mii = &bp->mii;
206 unsigned int old_carrier, new_carrier;
207 int advertise, lpa, media, duplex;
208
209 /* if forced media, go no further */
210 if (mii->force_media)
211 return;
212
213 /* check current and old link status */
214 old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
215 new_carrier = (unsigned int) mii_link_ok(mii);
216
217 /* if carrier state did not change, assume nothing else did */
218 if (!init_media && old_carrier == new_carrier)
219 return;
220
221 /* no carrier, nothing much to do */
222 if (!new_carrier) {
223 netif_carrier_off(mii->dev);
224 printk(KERN_INFO "%s: link down\n", mii->dev->name);
225 return;
226 }
227
228 /*
229 * we have carrier, see who's on the other end
230 */
231 netif_carrier_on(mii->dev);
232
233 /* get MII advertise and LPA values */
234 if (!init_media && mii->advertising) {
235 advertise = mii->advertising;
236 } else {
237 advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
238 mii->advertising = advertise;
239 }
240 lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
241
242 /* figure out media and duplex from advertise and LPA values */
243 media = mii_nway_result(lpa & advertise);
244 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
245
246 if (ok_to_print)
247 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
248 mii->dev->name,
249 media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
250 duplex ? "full" : "half", lpa);
251
252 mii->full_duplex = duplex;
253
254 /* Let the MAC know about the new link state */
255 macb_set_media(bp, media);
256}
257
258static void macb_update_stats(struct macb *bp)
259{
260 u32 __iomem *reg = bp->regs + MACB_PFR;
261 u32 *p = &bp->hw_stats.rx_pause_frames;
262 u32 *end = &bp->hw_stats.tx_pause_frames + 1;
263
264 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
265
266 for(; p < end; p++, reg++)
267 *p += readl(reg);
268}
269
270static void macb_periodic_task(void *arg)
271{
272 struct macb *bp = arg;
273
274 macb_update_stats(bp);
275 macb_check_media(bp, 1, 0);
276
277 schedule_delayed_work(&bp->periodic_task, HZ);
278}
279
280static void macb_tx(struct macb *bp)
281{
282 unsigned int tail;
283 unsigned int head;
284 u32 status;
285
286 status = macb_readl(bp, TSR);
287 macb_writel(bp, TSR, status);
288
289 dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
290 (unsigned long)status);
291
292 if (status & MACB_BIT(UND)) {
293 printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
294 bp->dev->name);
295 bp->tx_head = bp->tx_tail = 0;
296 }
297
298 if (!(status & MACB_BIT(COMP)))
299 /*
300 * This may happen when a buffer becomes complete
301 * between reading the ISR and scanning the
302 * descriptors. Nothing to worry about.
303 */
304 return;
305
306 head = bp->tx_head;
307 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
308 struct ring_info *rp = &bp->tx_skb[tail];
309 struct sk_buff *skb = rp->skb;
310 u32 bufstat;
311
312 BUG_ON(skb == NULL);
313
314 rmb();
315 bufstat = bp->tx_ring[tail].ctrl;
316
317 if (!(bufstat & MACB_BIT(TX_USED)))
318 break;
319
320 dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
321 tail, skb->data);
322 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
323 DMA_TO_DEVICE);
324 bp->stats.tx_packets++;
325 bp->stats.tx_bytes += skb->len;
326 rp->skb = NULL;
327 dev_kfree_skb_irq(skb);
328 }
329
330 bp->tx_tail = tail;
331 if (netif_queue_stopped(bp->dev) &&
332 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
333 netif_wake_queue(bp->dev);
334}
335
336static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
337 unsigned int last_frag)
338{
339 unsigned int len;
340 unsigned int frag;
341 unsigned int offset = 0;
342 struct sk_buff *skb;
343
344 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
345
346 dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
347 first_frag, last_frag, len);
348
349 skb = dev_alloc_skb(len + RX_OFFSET);
350 if (!skb) {
351 bp->stats.rx_dropped++;
352 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
353 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
354 if (frag == last_frag)
355 break;
356 }
357 wmb();
358 return 1;
359 }
360
361 skb_reserve(skb, RX_OFFSET);
362 skb->dev = bp->dev;
363 skb->ip_summed = CHECKSUM_NONE;
364 skb_put(skb, len);
365
366 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
367 unsigned int frag_len = RX_BUFFER_SIZE;
368
369 if (offset + frag_len > len) {
370 BUG_ON(frag != last_frag);
371 frag_len = len - offset;
372 }
373 memcpy(skb->data + offset,
374 bp->rx_buffers + (RX_BUFFER_SIZE * frag),
375 frag_len);
376 offset += RX_BUFFER_SIZE;
377 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
378 wmb();
379
380 if (frag == last_frag)
381 break;
382 }
383
384 skb->protocol = eth_type_trans(skb, bp->dev);
385
386 bp->stats.rx_packets++;
387 bp->stats.rx_bytes += len;
388 bp->dev->last_rx = jiffies;
389 dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
390 skb->len, skb->csum);
391 netif_receive_skb(skb);
392
393 return 0;
394}
395
396/* Mark DMA descriptors from begin up to and not including end as unused */
397static void discard_partial_frame(struct macb *bp, unsigned int begin,
398 unsigned int end)
399{
400 unsigned int frag;
401
402 for (frag = begin; frag != end; frag = NEXT_RX(frag))
403 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
404 wmb();
405
406 /*
407 * When this happens, the hardware stats registers for
408 * whatever caused this is updated, so we don't have to record
409 * anything.
410 */
411}
412
413static int macb_rx(struct macb *bp, int budget)
414{
415 int received = 0;
416 unsigned int tail = bp->rx_tail;
417 int first_frag = -1;
418
419 for (; budget > 0; tail = NEXT_RX(tail)) {
420 u32 addr, ctrl;
421
422 rmb();
423 addr = bp->rx_ring[tail].addr;
424 ctrl = bp->rx_ring[tail].ctrl;
425
426 if (!(addr & MACB_BIT(RX_USED)))
427 break;
428
429 if (ctrl & MACB_BIT(RX_SOF)) {
430 if (first_frag != -1)
431 discard_partial_frame(bp, first_frag, tail);
432 first_frag = tail;
433 }
434
435 if (ctrl & MACB_BIT(RX_EOF)) {
436 int dropped;
437 BUG_ON(first_frag == -1);
438
439 dropped = macb_rx_frame(bp, first_frag, tail);
440 first_frag = -1;
441 if (!dropped) {
442 received++;
443 budget--;
444 }
445 }
446 }
447
448 if (first_frag != -1)
449 bp->rx_tail = first_frag;
450 else
451 bp->rx_tail = tail;
452
453 return received;
454}
455
456static int macb_poll(struct net_device *dev, int *budget)
457{
458 struct macb *bp = netdev_priv(dev);
459 int orig_budget, work_done, retval = 0;
460 u32 status;
461
462 status = macb_readl(bp, RSR);
463 macb_writel(bp, RSR, status);
464
465 if (!status) {
466 /*
467 * This may happen if an interrupt was pending before
468 * this function was called last time, and no packets
469 * have been received since.
470 */
471 netif_rx_complete(dev);
472 goto out;
473 }
474
475 dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
476 (unsigned long)status, *budget);
477
478 if (!(status & MACB_BIT(REC))) {
479 dev_warn(&bp->pdev->dev,
480 "No RX buffers complete, status = %02lx\n",
481 (unsigned long)status);
482 netif_rx_complete(dev);
483 goto out;
484 }
485
486 orig_budget = *budget;
487 if (orig_budget > dev->quota)
488 orig_budget = dev->quota;
489
490 work_done = macb_rx(bp, orig_budget);
491 if (work_done < orig_budget) {
492 netif_rx_complete(dev);
493 retval = 0;
494 } else {
495 retval = 1;
496 }
497
498 /*
499 * We've done what we can to clean the buffers. Make sure we
500 * get notified when new packets arrive.
501 */
502out:
503 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
504
505 /* TODO: Handle errors */
506
507 return retval;
508}
509
510static irqreturn_t macb_interrupt(int irq, void *dev_id)
511{
512 struct net_device *dev = dev_id;
513 struct macb *bp = netdev_priv(dev);
514 u32 status;
515
516 status = macb_readl(bp, ISR);
517
518 if (unlikely(!status))
519 return IRQ_NONE;
520
521 spin_lock(&bp->lock);
522
523 while (status) {
524 if (status & MACB_BIT(MFD))
525 complete(&bp->mdio_complete);
526
527 /* close possible race with dev_close */
528 if (unlikely(!netif_running(dev))) {
529 macb_writel(bp, IDR, ~0UL);
530 break;
531 }
532
533 if (status & MACB_RX_INT_FLAGS) {
534 if (netif_rx_schedule_prep(dev)) {
535 /*
536 * There's no point taking any more interrupts
537 * until we have processed the buffers
538 */
539 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
540 dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
541 __netif_rx_schedule(dev);
542 }
543 }
544
545 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
546 macb_tx(bp);
547
548 /*
549 * Link change detection isn't possible with RMII, so we'll
550 * add that if/when we get our hands on a full-blown MII PHY.
551 */
552
553 if (status & MACB_BIT(HRESP)) {
554 /*
555 * TODO: Reset the hardware, and maybe move the printk
556 * to a lower-priority context as well (work queue?)
557 */
558 printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
559 dev->name);
560 }
561
562 status = macb_readl(bp, ISR);
563 }
564
565 spin_unlock(&bp->lock);
566
567 return IRQ_HANDLED;
568}
569
570static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
571{
572 struct macb *bp = netdev_priv(dev);
573 dma_addr_t mapping;
574 unsigned int len, entry;
575 u32 ctrl;
576
577#ifdef DEBUG
578 int i;
579 dev_dbg(&bp->pdev->dev,
580 "start_xmit: len %u head %p data %p tail %p end %p\n",
581 skb->len, skb->head, skb->data, skb->tail, skb->end);
582 dev_dbg(&bp->pdev->dev,
583 "data:");
584 for (i = 0; i < 16; i++)
585 printk(" %02x", (unsigned int)skb->data[i]);
586 printk("\n");
587#endif
588
589 len = skb->len;
590 spin_lock_irq(&bp->lock);
591
592 /* This is a hard error, log it. */
593 if (TX_BUFFS_AVAIL(bp) < 1) {
594 netif_stop_queue(dev);
595 spin_unlock_irq(&bp->lock);
596 dev_err(&bp->pdev->dev,
597 "BUG! Tx Ring full when queue awake!\n");
598 dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
599 bp->tx_head, bp->tx_tail);
600 return 1;
601 }
602
603 entry = bp->tx_head;
604 dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
605 mapping = dma_map_single(&bp->pdev->dev, skb->data,
606 len, DMA_TO_DEVICE);
607 bp->tx_skb[entry].skb = skb;
608 bp->tx_skb[entry].mapping = mapping;
609 dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
610 skb->data, (unsigned long)mapping);
611
612 ctrl = MACB_BF(TX_FRMLEN, len);
613 ctrl |= MACB_BIT(TX_LAST);
614 if (entry == (TX_RING_SIZE - 1))
615 ctrl |= MACB_BIT(TX_WRAP);
616
617 bp->tx_ring[entry].addr = mapping;
618 bp->tx_ring[entry].ctrl = ctrl;
619 wmb();
620
621 entry = NEXT_TX(entry);
622 bp->tx_head = entry;
623
624 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
625
626 if (TX_BUFFS_AVAIL(bp) < 1)
627 netif_stop_queue(dev);
628
629 spin_unlock_irq(&bp->lock);
630
631 dev->trans_start = jiffies;
632
633 return 0;
634}
635
636static void macb_free_consistent(struct macb *bp)
637{
638 if (bp->tx_skb) {
639 kfree(bp->tx_skb);
640 bp->tx_skb = NULL;
641 }
642 if (bp->rx_ring) {
643 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
644 bp->rx_ring, bp->rx_ring_dma);
645 bp->rx_ring = NULL;
646 }
647 if (bp->tx_ring) {
648 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
649 bp->tx_ring, bp->tx_ring_dma);
650 bp->tx_ring = NULL;
651 }
652 if (bp->rx_buffers) {
653 dma_free_coherent(&bp->pdev->dev,
654 RX_RING_SIZE * RX_BUFFER_SIZE,
655 bp->rx_buffers, bp->rx_buffers_dma);
656 bp->rx_buffers = NULL;
657 }
658}
659
660static int macb_alloc_consistent(struct macb *bp)
661{
662 int size;
663
664 size = TX_RING_SIZE * sizeof(struct ring_info);
665 bp->tx_skb = kmalloc(size, GFP_KERNEL);
666 if (!bp->tx_skb)
667 goto out_err;
668
669 size = RX_RING_BYTES;
670 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
671 &bp->rx_ring_dma, GFP_KERNEL);
672 if (!bp->rx_ring)
673 goto out_err;
674 dev_dbg(&bp->pdev->dev,
675 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
676 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
677
678 size = TX_RING_BYTES;
679 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
680 &bp->tx_ring_dma, GFP_KERNEL);
681 if (!bp->tx_ring)
682 goto out_err;
683 dev_dbg(&bp->pdev->dev,
684 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
685 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
686
687 size = RX_RING_SIZE * RX_BUFFER_SIZE;
688 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
689 &bp->rx_buffers_dma, GFP_KERNEL);
690 if (!bp->rx_buffers)
691 goto out_err;
692 dev_dbg(&bp->pdev->dev,
693 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
694 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
695
696 return 0;
697
698out_err:
699 macb_free_consistent(bp);
700 return -ENOMEM;
701}
702
703static void macb_init_rings(struct macb *bp)
704{
705 int i;
706 dma_addr_t addr;
707
708 addr = bp->rx_buffers_dma;
709 for (i = 0; i < RX_RING_SIZE; i++) {
710 bp->rx_ring[i].addr = addr;
711 bp->rx_ring[i].ctrl = 0;
712 addr += RX_BUFFER_SIZE;
713 }
714 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
715
716 for (i = 0; i < TX_RING_SIZE; i++) {
717 bp->tx_ring[i].addr = 0;
718 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
719 }
720 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
721
722 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
723}
724
725static void macb_reset_hw(struct macb *bp)
726{
727 /* Make sure we have the write buffer for ourselves */
728 wmb();
729
730 /*
731 * Disable RX and TX (XXX: Should we halt the transmission
732 * more gracefully?)
733 */
734 macb_writel(bp, NCR, 0);
735
736 /* Clear the stats registers (XXX: Update stats first?) */
737 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
738
739 /* Clear all status flags */
740 macb_writel(bp, TSR, ~0UL);
741 macb_writel(bp, RSR, ~0UL);
742
743 /* Disable all interrupts */
744 macb_writel(bp, IDR, ~0UL);
745 macb_readl(bp, ISR);
746}
747
748static void macb_init_hw(struct macb *bp)
749{
750 u32 config;
751
752 macb_reset_hw(bp);
753 __macb_set_hwaddr(bp);
754
755 config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
756 config |= MACB_BIT(PAE); /* PAuse Enable */
757 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
758 if (bp->dev->flags & IFF_PROMISC)
759 config |= MACB_BIT(CAF); /* Copy All Frames */
760 if (!(bp->dev->flags & IFF_BROADCAST))
761 config |= MACB_BIT(NBC); /* No BroadCast */
762 macb_writel(bp, NCFGR, config);
763
764 /* Initialize TX and RX buffers */
765 macb_writel(bp, RBQP, bp->rx_ring_dma);
766 macb_writel(bp, TBQP, bp->tx_ring_dma);
767
768 /* Enable TX and RX */
769 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
770
771 /* Enable interrupts */
772 macb_writel(bp, IER, (MACB_BIT(RCOMP)
773 | MACB_BIT(RXUBR)
774 | MACB_BIT(ISR_TUND)
775 | MACB_BIT(ISR_RLE)
776 | MACB_BIT(TXERR)
777 | MACB_BIT(TCOMP)
778 | MACB_BIT(ISR_ROVR)
779 | MACB_BIT(HRESP)));
780}
781
782static void macb_init_phy(struct net_device *dev)
783{
784 struct macb *bp = netdev_priv(dev);
785
786 /* Set some reasonable default settings */
787 macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
788 ADVERTISE_CSMA | ADVERTISE_ALL);
789 macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
790 (BMCR_SPEED100 | BMCR_ANENABLE
791 | BMCR_ANRESTART | BMCR_FULLDPLX));
792}
793
794static int macb_open(struct net_device *dev)
795{
796 struct macb *bp = netdev_priv(dev);
797 int err;
798
799 dev_dbg(&bp->pdev->dev, "open\n");
800
801 if (!is_valid_ether_addr(dev->dev_addr))
802 return -EADDRNOTAVAIL;
803
804 err = macb_alloc_consistent(bp);
805 if (err) {
806 printk(KERN_ERR
807 "%s: Unable to allocate DMA memory (error %d)\n",
808 dev->name, err);
809 return err;
810 }
811
812 macb_init_rings(bp);
813 macb_init_hw(bp);
814 macb_init_phy(dev);
815
816 macb_check_media(bp, 1, 1);
817 netif_start_queue(dev);
818
819 schedule_delayed_work(&bp->periodic_task, HZ);
820
821 return 0;
822}
823
824static int macb_close(struct net_device *dev)
825{
826 struct macb *bp = netdev_priv(dev);
827 unsigned long flags;
828
829 cancel_rearming_delayed_work(&bp->periodic_task);
830
831 netif_stop_queue(dev);
832
833 spin_lock_irqsave(&bp->lock, flags);
834 macb_reset_hw(bp);
835 netif_carrier_off(dev);
836 spin_unlock_irqrestore(&bp->lock, flags);
837
838 macb_free_consistent(bp);
839
840 return 0;
841}
842
843static struct net_device_stats *macb_get_stats(struct net_device *dev)
844{
845 struct macb *bp = netdev_priv(dev);
846 struct net_device_stats *nstat = &bp->stats;
847 struct macb_stats *hwstat = &bp->hw_stats;
848
849 /* Convert HW stats into netdevice stats */
850 nstat->rx_errors = (hwstat->rx_fcs_errors +
851 hwstat->rx_align_errors +
852 hwstat->rx_resource_errors +
853 hwstat->rx_overruns +
854 hwstat->rx_oversize_pkts +
855 hwstat->rx_jabbers +
856 hwstat->rx_undersize_pkts +
857 hwstat->sqe_test_errors +
858 hwstat->rx_length_mismatch);
859 nstat->tx_errors = (hwstat->tx_late_cols +
860 hwstat->tx_excessive_cols +
861 hwstat->tx_underruns +
862 hwstat->tx_carrier_errors);
863 nstat->collisions = (hwstat->tx_single_cols +
864 hwstat->tx_multiple_cols +
865 hwstat->tx_excessive_cols);
866 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
867 hwstat->rx_jabbers +
868 hwstat->rx_undersize_pkts +
869 hwstat->rx_length_mismatch);
870 nstat->rx_over_errors = hwstat->rx_resource_errors;
871 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
872 nstat->rx_frame_errors = hwstat->rx_align_errors;
873 nstat->rx_fifo_errors = hwstat->rx_overruns;
874 /* XXX: What does "missed" mean? */
875 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
876 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
877 nstat->tx_fifo_errors = hwstat->tx_underruns;
878 /* Don't know about heartbeat or window errors... */
879
880 return nstat;
881}
882
883static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
884{
885 struct macb *bp = netdev_priv(dev);
886 int ret;
887 unsigned long flags;
888
889 spin_lock_irqsave(&bp->lock, flags);
890 ret = mii_ethtool_gset(&bp->mii, cmd);
891 spin_unlock_irqrestore(&bp->lock, flags);
892
893 return ret;
894}
895
896static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
897{
898 struct macb *bp = netdev_priv(dev);
899 int ret;
900 unsigned long flags;
901
902 spin_lock_irqsave(&bp->lock, flags);
903 ret = mii_ethtool_sset(&bp->mii, cmd);
904 spin_unlock_irqrestore(&bp->lock, flags);
905
906 return ret;
907}
908
909static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
910{
911 struct macb *bp = netdev_priv(dev);
912
913 strcpy(info->driver, bp->pdev->dev.driver->name);
914 strcpy(info->version, "$Revision: 1.14 $");
915 strcpy(info->bus_info, bp->pdev->dev.bus_id);
916}
917
918static int macb_nway_reset(struct net_device *dev)
919{
920 struct macb *bp = netdev_priv(dev);
921 return mii_nway_restart(&bp->mii);
922}
923
924static struct ethtool_ops macb_ethtool_ops = {
925 .get_settings = macb_get_settings,
926 .set_settings = macb_set_settings,
927 .get_drvinfo = macb_get_drvinfo,
928 .nway_reset = macb_nway_reset,
929 .get_link = ethtool_op_get_link,
930};
931
932static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
933{
934 struct macb *bp = netdev_priv(dev);
935 int ret;
936 unsigned long flags;
937
938 if (!netif_running(dev))
939 return -EINVAL;
940
941 spin_lock_irqsave(&bp->lock, flags);
942 ret = generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
943 spin_unlock_irqrestore(&bp->lock, flags);
944
945 return ret;
946}
947
948static ssize_t macb_mii_show(const struct class_device *cd, char *buf,
949 unsigned long addr)
950{
951 struct net_device *dev = to_net_dev(cd);
952 struct macb *bp = netdev_priv(dev);
953 ssize_t ret = -EINVAL;
954
955 if (netif_running(dev)) {
956 int value;
957 value = macb_mdio_read(dev, bp->mii.phy_id, addr);
958 ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
959 }
960
961 return ret;
962}
963
964#define MII_ENTRY(name, addr) \
965static ssize_t show_##name(struct class_device *cd, char *buf) \
966{ \
967 return macb_mii_show(cd, buf, addr); \
968} \
969static CLASS_DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
970
971MII_ENTRY(bmcr, MII_BMCR);
972MII_ENTRY(bmsr, MII_BMSR);
973MII_ENTRY(physid1, MII_PHYSID1);
974MII_ENTRY(physid2, MII_PHYSID2);
975MII_ENTRY(advertise, MII_ADVERTISE);
976MII_ENTRY(lpa, MII_LPA);
977MII_ENTRY(expansion, MII_EXPANSION);
978
979static struct attribute *macb_mii_attrs[] = {
980 &class_device_attr_bmcr.attr,
981 &class_device_attr_bmsr.attr,
982 &class_device_attr_physid1.attr,
983 &class_device_attr_physid2.attr,
984 &class_device_attr_advertise.attr,
985 &class_device_attr_lpa.attr,
986 &class_device_attr_expansion.attr,
987 NULL,
988};
989
990static struct attribute_group macb_mii_group = {
991 .name = "mii",
992 .attrs = macb_mii_attrs,
993};
994
995static void macb_unregister_sysfs(struct net_device *net)
996{
997 struct class_device *class_dev = &net->class_dev;
998
999 sysfs_remove_group(&class_dev->kobj, &macb_mii_group);
1000}
1001
1002static int macb_register_sysfs(struct net_device *net)
1003{
1004 struct class_device *class_dev = &net->class_dev;
1005 int ret;
1006
1007 ret = sysfs_create_group(&class_dev->kobj, &macb_mii_group);
1008 if (ret)
1009 printk(KERN_WARNING
1010 "%s: sysfs mii attribute registration failed: %d\n",
1011 net->name, ret);
1012 return ret;
1013}
1014static int __devinit macb_probe(struct platform_device *pdev)
1015{
1016 struct eth_platform_data *pdata;
1017 struct resource *regs;
1018 struct net_device *dev;
1019 struct macb *bp;
1020 unsigned long pclk_hz;
1021 u32 config;
1022 int err = -ENXIO;
1023
1024 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1025 if (!regs) {
1026 dev_err(&pdev->dev, "no mmio resource defined\n");
1027 goto err_out;
1028 }
1029
1030 err = -ENOMEM;
1031 dev = alloc_etherdev(sizeof(*bp));
1032 if (!dev) {
1033 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1034 goto err_out;
1035 }
1036
1037 SET_MODULE_OWNER(dev);
1038 SET_NETDEV_DEV(dev, &pdev->dev);
1039
1040 /* TODO: Actually, we have some interesting features... */
1041 dev->features |= 0;
1042
1043 bp = netdev_priv(dev);
1044 bp->pdev = pdev;
1045 bp->dev = dev;
1046
1047 spin_lock_init(&bp->lock);
1048
1049 bp->pclk = clk_get(&pdev->dev, "pclk");
1050 if (IS_ERR(bp->pclk)) {
1051 dev_err(&pdev->dev, "failed to get pclk\n");
1052 goto err_out_free_dev;
1053 }
1054 bp->hclk = clk_get(&pdev->dev, "hclk");
1055 if (IS_ERR(bp->hclk)) {
1056 dev_err(&pdev->dev, "failed to get hclk\n");
1057 goto err_out_put_pclk;
1058 }
1059
1060 clk_enable(bp->pclk);
1061 clk_enable(bp->hclk);
1062
1063 bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
1064 if (!bp->regs) {
1065 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1066 err = -ENOMEM;
1067 goto err_out_disable_clocks;
1068 }
1069
1070 dev->irq = platform_get_irq(pdev, 0);
1071 err = request_irq(dev->irq, macb_interrupt, SA_SAMPLE_RANDOM,
1072 dev->name, dev);
1073 if (err) {
1074 printk(KERN_ERR
1075 "%s: Unable to request IRQ %d (error %d)\n",
1076 dev->name, dev->irq, err);
1077 goto err_out_iounmap;
1078 }
1079
1080 dev->open = macb_open;
1081 dev->stop = macb_close;
1082 dev->hard_start_xmit = macb_start_xmit;
1083 dev->get_stats = macb_get_stats;
1084 dev->do_ioctl = macb_ioctl;
1085 dev->poll = macb_poll;
1086 dev->weight = 64;
1087 dev->ethtool_ops = &macb_ethtool_ops;
1088
1089 dev->base_addr = regs->start;
1090
1091 INIT_WORK(&bp->periodic_task, macb_periodic_task, bp);
1092 mutex_init(&bp->mdio_mutex);
1093 init_completion(&bp->mdio_complete);
1094
1095 /* Set MII management clock divider */
1096 pclk_hz = clk_get_rate(bp->pclk);
1097 if (pclk_hz <= 20000000)
1098 config = MACB_BF(CLK, MACB_CLK_DIV8);
1099 else if (pclk_hz <= 40000000)
1100 config = MACB_BF(CLK, MACB_CLK_DIV16);
1101 else if (pclk_hz <= 80000000)
1102 config = MACB_BF(CLK, MACB_CLK_DIV32);
1103 else
1104 config = MACB_BF(CLK, MACB_CLK_DIV64);
1105 macb_writel(bp, NCFGR, config);
1106
1107 bp->mii.dev = dev;
1108 bp->mii.mdio_read = macb_mdio_read;
1109 bp->mii.mdio_write = macb_mdio_write;
1110 bp->mii.phy_id_mask = 0x1f;
1111 bp->mii.reg_num_mask = 0x1f;
1112
1113 macb_get_hwaddr(bp);
1114 err = macb_phy_probe(bp);
1115 if (err) {
1116 dev_err(&pdev->dev, "Failed to detect PHY, aborting.\n");
1117 goto err_out_free_irq;
1118 }
1119
1120 pdata = pdev->dev.platform_data;
1121 if (pdata && pdata->is_rmii)
1122 macb_writel(bp, USRIO, 0);
1123 else
1124 macb_writel(bp, USRIO, MACB_BIT(MII));
1125
1126 bp->tx_pending = DEF_TX_RING_PENDING;
1127
1128 err = register_netdev(dev);
1129 if (err) {
1130 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1131 goto err_out_free_irq;
1132 }
1133
1134 platform_set_drvdata(pdev, dev);
1135
1136 macb_register_sysfs(dev);
1137
1138 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
1139 "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
1140 dev->name, dev->base_addr, dev->irq,
1141 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1142 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1143
1144 return 0;
1145
1146err_out_free_irq:
1147 free_irq(dev->irq, dev);
1148err_out_iounmap:
1149 iounmap(bp->regs);
1150err_out_disable_clocks:
1151 clk_disable(bp->hclk);
1152 clk_disable(bp->pclk);
1153 clk_put(bp->hclk);
1154err_out_put_pclk:
1155 clk_put(bp->pclk);
1156err_out_free_dev:
1157 free_netdev(dev);
1158err_out:
1159 platform_set_drvdata(pdev, NULL);
1160 return err;
1161}
1162
1163static int __devexit macb_remove(struct platform_device *pdev)
1164{
1165 struct net_device *dev;
1166 struct macb *bp;
1167
1168 dev = platform_get_drvdata(pdev);
1169
1170 if (dev) {
1171 bp = netdev_priv(dev);
1172 macb_unregister_sysfs(dev);
1173 unregister_netdev(dev);
1174 free_irq(dev->irq, dev);
1175 iounmap(bp->regs);
1176 clk_disable(bp->hclk);
1177 clk_disable(bp->pclk);
1178 clk_put(bp->hclk);
1179 clk_put(bp->pclk);
1180 free_netdev(dev);
1181 platform_set_drvdata(pdev, NULL);
1182 }
1183
1184 return 0;
1185}
1186
1187static struct platform_driver macb_driver = {
1188 .probe = macb_probe,
1189 .remove = __devexit_p(macb_remove),
1190 .driver = {
1191 .name = "macb",
1192 },
1193};
1194
1195static int __init macb_init(void)
1196{
1197 return platform_driver_register(&macb_driver);
1198}
1199
1200static void __exit macb_exit(void)
1201{
1202 platform_driver_unregister(&macb_driver);
1203}
1204
1205module_init(macb_init);
1206module_exit(macb_exit);
1207
1208MODULE_LICENSE("GPL");
1209MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
1210MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
new file mode 100644
index 000000000000..8c253db69881
--- /dev/null
+++ b/drivers/net/macb.h
@@ -0,0 +1,387 @@
1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _MACB_H
11#define _MACB_H
12
13/* MACB register offsets */
14#define MACB_NCR 0x0000
15#define MACB_NCFGR 0x0004
16#define MACB_NSR 0x0008
17#define MACB_TSR 0x0014
18#define MACB_RBQP 0x0018
19#define MACB_TBQP 0x001c
20#define MACB_RSR 0x0020
21#define MACB_ISR 0x0024
22#define MACB_IER 0x0028
23#define MACB_IDR 0x002c
24#define MACB_IMR 0x0030
25#define MACB_MAN 0x0034
26#define MACB_PTR 0x0038
27#define MACB_PFR 0x003c
28#define MACB_FTO 0x0040
29#define MACB_SCF 0x0044
30#define MACB_MCF 0x0048
31#define MACB_FRO 0x004c
32#define MACB_FCSE 0x0050
33#define MACB_ALE 0x0054
34#define MACB_DTF 0x0058
35#define MACB_LCOL 0x005c
36#define MACB_EXCOL 0x0060
37#define MACB_TUND 0x0064
38#define MACB_CSE 0x0068
39#define MACB_RRE 0x006c
40#define MACB_ROVR 0x0070
41#define MACB_RSE 0x0074
42#define MACB_ELE 0x0078
43#define MACB_RJA 0x007c
44#define MACB_USF 0x0080
45#define MACB_STE 0x0084
46#define MACB_RLE 0x0088
47#define MACB_TPF 0x008c
48#define MACB_HRB 0x0090
49#define MACB_HRT 0x0094
50#define MACB_SA1B 0x0098
51#define MACB_SA1T 0x009c
52#define MACB_SA2B 0x00a0
53#define MACB_SA2T 0x00a4
54#define MACB_SA3B 0x00a8
55#define MACB_SA3T 0x00ac
56#define MACB_SA4B 0x00b0
57#define MACB_SA4T 0x00b4
58#define MACB_TID 0x00b8
59#define MACB_TPQ 0x00bc
60#define MACB_USRIO 0x00c0
61#define MACB_WOL 0x00c4
62
63/* Bitfields in NCR */
64#define MACB_LB_OFFSET 0
65#define MACB_LB_SIZE 1
66#define MACB_LLB_OFFSET 1
67#define MACB_LLB_SIZE 1
68#define MACB_RE_OFFSET 2
69#define MACB_RE_SIZE 1
70#define MACB_TE_OFFSET 3
71#define MACB_TE_SIZE 1
72#define MACB_MPE_OFFSET 4
73#define MACB_MPE_SIZE 1
74#define MACB_CLRSTAT_OFFSET 5
75#define MACB_CLRSTAT_SIZE 1
76#define MACB_INCSTAT_OFFSET 6
77#define MACB_INCSTAT_SIZE 1
78#define MACB_WESTAT_OFFSET 7
79#define MACB_WESTAT_SIZE 1
80#define MACB_BP_OFFSET 8
81#define MACB_BP_SIZE 1
82#define MACB_TSTART_OFFSET 9
83#define MACB_TSTART_SIZE 1
84#define MACB_THALT_OFFSET 10
85#define MACB_THALT_SIZE 1
86#define MACB_NCR_TPF_OFFSET 11
87#define MACB_NCR_TPF_SIZE 1
88#define MACB_TZQ_OFFSET 12
89#define MACB_TZQ_SIZE 1
90
91/* Bitfields in NCFGR */
92#define MACB_SPD_OFFSET 0
93#define MACB_SPD_SIZE 1
94#define MACB_FD_OFFSET 1
95#define MACB_FD_SIZE 1
96#define MACB_BIT_RATE_OFFSET 2
97#define MACB_BIT_RATE_SIZE 1
98#define MACB_JFRAME_OFFSET 3
99#define MACB_JFRAME_SIZE 1
100#define MACB_CAF_OFFSET 4
101#define MACB_CAF_SIZE 1
102#define MACB_NBC_OFFSET 5
103#define MACB_NBC_SIZE 1
104#define MACB_NCFGR_MTI_OFFSET 6
105#define MACB_NCFGR_MTI_SIZE 1
106#define MACB_UNI_OFFSET 7
107#define MACB_UNI_SIZE 1
108#define MACB_BIG_OFFSET 8
109#define MACB_BIG_SIZE 1
110#define MACB_EAE_OFFSET 9
111#define MACB_EAE_SIZE 1
112#define MACB_CLK_OFFSET 10
113#define MACB_CLK_SIZE 2
114#define MACB_RTY_OFFSET 12
115#define MACB_RTY_SIZE 1
116#define MACB_PAE_OFFSET 13
117#define MACB_PAE_SIZE 1
118#define MACB_RBOF_OFFSET 14
119#define MACB_RBOF_SIZE 2
120#define MACB_RLCE_OFFSET 16
121#define MACB_RLCE_SIZE 1
122#define MACB_DRFCS_OFFSET 17
123#define MACB_DRFCS_SIZE 1
124#define MACB_EFRHD_OFFSET 18
125#define MACB_EFRHD_SIZE 1
126#define MACB_IRXFCS_OFFSET 19
127#define MACB_IRXFCS_SIZE 1
128
129/* Bitfields in NSR */
130#define MACB_NSR_LINK_OFFSET 0
131#define MACB_NSR_LINK_SIZE 1
132#define MACB_MDIO_OFFSET 1
133#define MACB_MDIO_SIZE 1
134#define MACB_IDLE_OFFSET 2
135#define MACB_IDLE_SIZE 1
136
137/* Bitfields in TSR */
138#define MACB_UBR_OFFSET 0
139#define MACB_UBR_SIZE 1
140#define MACB_COL_OFFSET 1
141#define MACB_COL_SIZE 1
142#define MACB_TSR_RLE_OFFSET 2
143#define MACB_TSR_RLE_SIZE 1
144#define MACB_TGO_OFFSET 3
145#define MACB_TGO_SIZE 1
146#define MACB_BEX_OFFSET 4
147#define MACB_BEX_SIZE 1
148#define MACB_COMP_OFFSET 5
149#define MACB_COMP_SIZE 1
150#define MACB_UND_OFFSET 6
151#define MACB_UND_SIZE 1
152
153/* Bitfields in RSR */
154#define MACB_BNA_OFFSET 0
155#define MACB_BNA_SIZE 1
156#define MACB_REC_OFFSET 1
157#define MACB_REC_SIZE 1
158#define MACB_OVR_OFFSET 2
159#define MACB_OVR_SIZE 1
160
161/* Bitfields in ISR/IER/IDR/IMR */
162#define MACB_MFD_OFFSET 0
163#define MACB_MFD_SIZE 1
164#define MACB_RCOMP_OFFSET 1
165#define MACB_RCOMP_SIZE 1
166#define MACB_RXUBR_OFFSET 2
167#define MACB_RXUBR_SIZE 1
168#define MACB_TXUBR_OFFSET 3
169#define MACB_TXUBR_SIZE 1
170#define MACB_ISR_TUND_OFFSET 4
171#define MACB_ISR_TUND_SIZE 1
172#define MACB_ISR_RLE_OFFSET 5
173#define MACB_ISR_RLE_SIZE 1
174#define MACB_TXERR_OFFSET 6
175#define MACB_TXERR_SIZE 1
176#define MACB_TCOMP_OFFSET 7
177#define MACB_TCOMP_SIZE 1
178#define MACB_ISR_LINK_OFFSET 9
179#define MACB_ISR_LINK_SIZE 1
180#define MACB_ISR_ROVR_OFFSET 10
181#define MACB_ISR_ROVR_SIZE 1
182#define MACB_HRESP_OFFSET 11
183#define MACB_HRESP_SIZE 1
184#define MACB_PFR_OFFSET 12
185#define MACB_PFR_SIZE 1
186#define MACB_PTZ_OFFSET 13
187#define MACB_PTZ_SIZE 1
188
189/* Bitfields in MAN */
190#define MACB_DATA_OFFSET 0
191#define MACB_DATA_SIZE 16
192#define MACB_CODE_OFFSET 16
193#define MACB_CODE_SIZE 2
194#define MACB_REGA_OFFSET 18
195#define MACB_REGA_SIZE 5
196#define MACB_PHYA_OFFSET 23
197#define MACB_PHYA_SIZE 5
198#define MACB_RW_OFFSET 28
199#define MACB_RW_SIZE 2
200#define MACB_SOF_OFFSET 30
201#define MACB_SOF_SIZE 2
202
203/* Bitfields in USRIO */
204#define MACB_MII_OFFSET 0
205#define MACB_MII_SIZE 1
206#define MACB_EAM_OFFSET 1
207#define MACB_EAM_SIZE 1
208#define MACB_TX_PAUSE_OFFSET 2
209#define MACB_TX_PAUSE_SIZE 1
210#define MACB_TX_PAUSE_ZERO_OFFSET 3
211#define MACB_TX_PAUSE_ZERO_SIZE 1
212
213/* Bitfields in WOL */
214#define MACB_IP_OFFSET 0
215#define MACB_IP_SIZE 16
216#define MACB_MAG_OFFSET 16
217#define MACB_MAG_SIZE 1
218#define MACB_ARP_OFFSET 17
219#define MACB_ARP_SIZE 1
220#define MACB_SA1_OFFSET 18
221#define MACB_SA1_SIZE 1
222#define MACB_WOL_MTI_OFFSET 19
223#define MACB_WOL_MTI_SIZE 1
224
225/* Constants for CLK */
226#define MACB_CLK_DIV8 0
227#define MACB_CLK_DIV16 1
228#define MACB_CLK_DIV32 2
229#define MACB_CLK_DIV64 3
230
231/* Constants for MAN register */
232#define MACB_MAN_SOF 1
233#define MACB_MAN_WRITE 1
234#define MACB_MAN_READ 2
235#define MACB_MAN_CODE 2
236
237/* Bit manipulation macros */
238#define MACB_BIT(name) \
239 (1 << MACB_##name##_OFFSET)
240#define MACB_BF(name,value) \
241 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
242 << MACB_##name##_OFFSET)
243#define MACB_BFEXT(name,value)\
244 (((value) >> MACB_##name##_OFFSET) \
245 & ((1 << MACB_##name##_SIZE) - 1))
246#define MACB_BFINS(name,value,old) \
247 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
248 << MACB_##name##_OFFSET)) \
249 | MACB_BF(name,value))
250
251/* Register access macros */
252#define macb_readl(port,reg) \
253 readl((port)->regs + MACB_##reg)
254#define macb_writel(port,reg,value) \
255 writel((value), (port)->regs + MACB_##reg)
256
257struct dma_desc {
258 u32 addr;
259 u32 ctrl;
260};
261
262/* DMA descriptor bitfields */
263#define MACB_RX_USED_OFFSET 0
264#define MACB_RX_USED_SIZE 1
265#define MACB_RX_WRAP_OFFSET 1
266#define MACB_RX_WRAP_SIZE 1
267#define MACB_RX_WADDR_OFFSET 2
268#define MACB_RX_WADDR_SIZE 30
269
270#define MACB_RX_FRMLEN_OFFSET 0
271#define MACB_RX_FRMLEN_SIZE 12
272#define MACB_RX_OFFSET_OFFSET 12
273#define MACB_RX_OFFSET_SIZE 2
274#define MACB_RX_SOF_OFFSET 14
275#define MACB_RX_SOF_SIZE 1
276#define MACB_RX_EOF_OFFSET 15
277#define MACB_RX_EOF_SIZE 1
278#define MACB_RX_CFI_OFFSET 16
279#define MACB_RX_CFI_SIZE 1
280#define MACB_RX_VLAN_PRI_OFFSET 17
281#define MACB_RX_VLAN_PRI_SIZE 3
282#define MACB_RX_PRI_TAG_OFFSET 20
283#define MACB_RX_PRI_TAG_SIZE 1
284#define MACB_RX_VLAN_TAG_OFFSET 21
285#define MACB_RX_VLAN_TAG_SIZE 1
286#define MACB_RX_TYPEID_MATCH_OFFSET 22
287#define MACB_RX_TYPEID_MATCH_SIZE 1
288#define MACB_RX_SA4_MATCH_OFFSET 23
289#define MACB_RX_SA4_MATCH_SIZE 1
290#define MACB_RX_SA3_MATCH_OFFSET 24
291#define MACB_RX_SA3_MATCH_SIZE 1
292#define MACB_RX_SA2_MATCH_OFFSET 25
293#define MACB_RX_SA2_MATCH_SIZE 1
294#define MACB_RX_SA1_MATCH_OFFSET 26
295#define MACB_RX_SA1_MATCH_SIZE 1
296#define MACB_RX_EXT_MATCH_OFFSET 28
297#define MACB_RX_EXT_MATCH_SIZE 1
298#define MACB_RX_UHASH_MATCH_OFFSET 29
299#define MACB_RX_UHASH_MATCH_SIZE 1
300#define MACB_RX_MHASH_MATCH_OFFSET 30
301#define MACB_RX_MHASH_MATCH_SIZE 1
302#define MACB_RX_BROADCAST_OFFSET 31
303#define MACB_RX_BROADCAST_SIZE 1
304
305#define MACB_TX_FRMLEN_OFFSET 0
306#define MACB_TX_FRMLEN_SIZE 11
307#define MACB_TX_LAST_OFFSET 15
308#define MACB_TX_LAST_SIZE 1
309#define MACB_TX_NOCRC_OFFSET 16
310#define MACB_TX_NOCRC_SIZE 1
311#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
312#define MACB_TX_BUF_EXHAUSTED_SIZE 1
313#define MACB_TX_UNDERRUN_OFFSET 28
314#define MACB_TX_UNDERRUN_SIZE 1
315#define MACB_TX_ERROR_OFFSET 29
316#define MACB_TX_ERROR_SIZE 1
317#define MACB_TX_WRAP_OFFSET 30
318#define MACB_TX_WRAP_SIZE 1
319#define MACB_TX_USED_OFFSET 31
320#define MACB_TX_USED_SIZE 1
321
322struct ring_info {
323 struct sk_buff *skb;
324 dma_addr_t mapping;
325};
326
327/*
328 * Hardware-collected statistics. Used when updating the network
329 * device stats by a periodic timer.
330 */
331struct macb_stats {
332 u32 rx_pause_frames;
333 u32 tx_ok;
334 u32 tx_single_cols;
335 u32 tx_multiple_cols;
336 u32 rx_ok;
337 u32 rx_fcs_errors;
338 u32 rx_align_errors;
339 u32 tx_deferred;
340 u32 tx_late_cols;
341 u32 tx_excessive_cols;
342 u32 tx_underruns;
343 u32 tx_carrier_errors;
344 u32 rx_resource_errors;
345 u32 rx_overruns;
346 u32 rx_symbol_errors;
347 u32 rx_oversize_pkts;
348 u32 rx_jabbers;
349 u32 rx_undersize_pkts;
350 u32 sqe_test_errors;
351 u32 rx_length_mismatch;
352 u32 tx_pause_frames;
353};
354
355struct macb {
356 void __iomem *regs;
357
358 unsigned int rx_tail;
359 struct dma_desc *rx_ring;
360 void *rx_buffers;
361
362 unsigned int tx_head, tx_tail;
363 struct dma_desc *tx_ring;
364 struct ring_info *tx_skb;
365
366 spinlock_t lock;
367 struct platform_device *pdev;
368 struct clk *pclk;
369 struct clk *hclk;
370 struct net_device *dev;
371 struct net_device_stats stats;
372 struct macb_stats hw_stats;
373
374 dma_addr_t rx_ring_dma;
375 dma_addr_t tx_ring_dma;
376 dma_addr_t rx_buffers_dma;
377
378 unsigned int rx_pending, tx_pending;
379
380 struct work_struct periodic_task;
381
382 struct mutex mdio_mutex;
383 struct completion mdio_complete;
384 struct mii_if_info mii;
385};
386
387#endif /* _MACB_H */
diff --git a/drivers/net/meth.c b/drivers/net/meth.c
index c1aa60b9a982..e1d97cdf649e 100644
--- a/drivers/net/meth.c
+++ b/drivers/net/meth.c
@@ -33,7 +33,6 @@
33#include <asm/ip32/ip32_ints.h> 33#include <asm/ip32/ip32_ints.h>
34 34
35#include <asm/io.h> 35#include <asm/io.h>
36#include <asm/checksum.h>
37#include <asm/scatterlist.h> 36#include <asm/scatterlist.h>
38#include <linux/dma-mapping.h> 37#include <linux/dma-mapping.h>
39 38
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 98703e086ee7..38df42802386 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -1955,7 +1955,7 @@ again:
1955 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST); 1955 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1956 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1956 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1957 cksum_offset = (skb->h.raw - skb->data); 1957 cksum_offset = (skb->h.raw - skb->data);
1958 pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data; 1958 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
1959 /* If the headers are excessively large, then we must 1959 /* If the headers are excessively large, then we must
1960 * fall back to a software checksum */ 1960 * fall back to a software checksum */
1961 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) { 1961 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
diff --git a/drivers/net/myri_sbus.c b/drivers/net/myri_sbus.c
index 7747bfd99f91..ee26ef52289f 100644
--- a/drivers/net/myri_sbus.c
+++ b/drivers/net/myri_sbus.c
@@ -39,7 +39,6 @@ static char version[] =
39#include <asm/auxio.h> 39#include <asm/auxio.h>
40#include <asm/pgtable.h> 40#include <asm/pgtable.h>
41#include <asm/irq.h> 41#include <asm/irq.h>
42#include <asm/checksum.h>
43 42
44#include "myri_sbus.h" 43#include "myri_sbus.h"
45#include "myri_code.h" 44#include "myri_code.h"
diff --git a/drivers/net/ne-h8300.c b/drivers/net/ne-h8300.c
index eb893d7e8834..38fd525f0f13 100644
--- a/drivers/net/ne-h8300.c
+++ b/drivers/net/ne-h8300.c
@@ -33,6 +33,8 @@ static const char version1[] =
33#include <asm/io.h> 33#include <asm/io.h>
34#include <asm/irq.h> 34#include <asm/irq.h>
35 35
36#define EI_SHIFT(x) (ei_local->reg_offset[x])
37
36#include "8390.h" 38#include "8390.h"
37 39
38#define DRV_NAME "ne-h8300" 40#define DRV_NAME "ne-h8300"
@@ -52,6 +54,11 @@ static const char version1[] =
52 54
53/* ---- No user-serviceable parts below ---- */ 55/* ---- No user-serviceable parts below ---- */
54 56
57static const char version[] =
58 "8390.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
59
60#include "lib8390.c"
61
55#define NE_BASE (dev->base_addr) 62#define NE_BASE (dev->base_addr)
56#define NE_CMD 0x00 63#define NE_CMD 0x00
57#define NE_DATAPORT (ei_status.word16?0x20:0x10) /* NatSemi-defined port window offset. */ 64#define NE_DATAPORT (ei_status.word16?0x20:0x10) /* NatSemi-defined port window offset. */
@@ -162,7 +169,7 @@ static void cleanup_card(struct net_device *dev)
162#ifndef MODULE 169#ifndef MODULE
163struct net_device * __init ne_probe(int unit) 170struct net_device * __init ne_probe(int unit)
164{ 171{
165 struct net_device *dev = alloc_ei_netdev(); 172 struct net_device *dev = ____alloc_ei_netdev(0);
166 int err; 173 int err;
167 174
168 if (!dev) 175 if (!dev)
@@ -283,7 +290,7 @@ static int __init ne_probe1(struct net_device *dev, int ioaddr)
283 290
284 /* Snarf the interrupt now. There's no point in waiting since we cannot 291 /* Snarf the interrupt now. There's no point in waiting since we cannot
285 share and the board will usually be enabled. */ 292 share and the board will usually be enabled. */
286 ret = request_irq(dev->irq, ei_interrupt, 0, name, dev); 293 ret = request_irq(dev->irq, __ei_interrupt, 0, name, dev);
287 if (ret) { 294 if (ret) {
288 printk (" unable to get IRQ %d (errno=%d).\n", dev->irq, ret); 295 printk (" unable to get IRQ %d (errno=%d).\n", dev->irq, ret);
289 goto err_out; 296 goto err_out;
@@ -318,9 +325,9 @@ static int __init ne_probe1(struct net_device *dev, int ioaddr)
318 dev->open = &ne_open; 325 dev->open = &ne_open;
319 dev->stop = &ne_close; 326 dev->stop = &ne_close;
320#ifdef CONFIG_NET_POLL_CONTROLLER 327#ifdef CONFIG_NET_POLL_CONTROLLER
321 dev->poll_controller = ei_poll; 328 dev->poll_controller = __ei_poll;
322#endif 329#endif
323 NS8390_init(dev, 0); 330 __NS8390_init(dev, 0);
324 331
325 ret = register_netdev(dev); 332 ret = register_netdev(dev);
326 if (ret) 333 if (ret)
@@ -335,7 +342,7 @@ err_out:
335 342
336static int ne_open(struct net_device *dev) 343static int ne_open(struct net_device *dev)
337{ 344{
338 ei_open(dev); 345 __ei_open(dev);
339 return 0; 346 return 0;
340} 347}
341 348
@@ -343,7 +350,7 @@ static int ne_close(struct net_device *dev)
343{ 350{
344 if (ei_debug > 1) 351 if (ei_debug > 1)
345 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name); 352 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name);
346 ei_close(dev); 353 __ei_close(dev);
347 return 0; 354 return 0;
348} 355}
349 356
@@ -584,7 +591,7 @@ retry:
584 if (time_after(jiffies, dma_start + 2*HZ/100)) { /* 20ms */ 591 if (time_after(jiffies, dma_start + 2*HZ/100)) { /* 20ms */
585 printk(KERN_WARNING "%s: timeout waiting for Tx RDC.\n", dev->name); 592 printk(KERN_WARNING "%s: timeout waiting for Tx RDC.\n", dev->name);
586 ne_reset_8390(dev); 593 ne_reset_8390(dev);
587 NS8390_init(dev,1); 594 __NS8390_init(dev,1);
588 break; 595 break;
589 } 596 }
590 597
@@ -620,7 +627,7 @@ int init_module(void)
620 int err; 627 int err;
621 628
622 for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) { 629 for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) {
623 struct net_device *dev = alloc_ei_netdev(); 630 struct net_device *dev = ____alloc_ei_netdev(0);
624 if (!dev) 631 if (!dev)
625 break; 632 break;
626 if (io[this_dev]) { 633 if (io[this_dev]) {
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index bf58db29e2ed..69233f6aa05c 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -60,7 +60,6 @@ static struct netpoll np = {
60 .local_port = 6665, 60 .local_port = 6665,
61 .remote_port = 6666, 61 .remote_port = 6666,
62 .remote_mac = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, 62 .remote_mac = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
63 .drop = netpoll_queue,
64}; 63};
65static int configured = 0; 64static int configured = 0;
66 65
@@ -102,6 +101,8 @@ __setup("netconsole=", option_setup);
102 101
103static int init_netconsole(void) 102static int init_netconsole(void)
104{ 103{
104 int err;
105
105 if(strlen(config)) 106 if(strlen(config))
106 option_setup(config); 107 option_setup(config);
107 108
@@ -110,8 +111,9 @@ static int init_netconsole(void)
110 return 0; 111 return 0;
111 } 112 }
112 113
113 if(netpoll_setup(&np)) 114 err = netpoll_setup(&np);
114 return -EINVAL; 115 if (err)
116 return err;
115 117
116 register_console(&netconsole); 118 register_console(&netconsole);
117 printk(KERN_INFO "netconsole: network logging started\n"); 119 printk(KERN_INFO "netconsole: network logging started\n");
diff --git a/drivers/net/netxen/Makefile b/drivers/net/netxen/Makefile
new file mode 100644
index 000000000000..a07cdc6f7384
--- /dev/null
+++ b/drivers/net/netxen/Makefile
@@ -0,0 +1,35 @@
1# Copyright (C) 2003 - 2006 NetXen, Inc.
2# All rights reserved.
3#
4# This program is free software; you can redistribute it and/or
5# modify it under the terms of the GNU General Public License
6# as published by the Free Software Foundation; either version 2
7# of the License, or (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful, but
10# WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 59 Temple Place - Suite 330, Boston,
17# MA 02111-1307, USA.
18#
19# The full GNU General Public License is included in this distribution
20# in the file called LICENSE.
21#
22# Contact Information:
23# info@netxen.com
24# NetXen,
25# 3965 Freedom Circle, Fourth floor,
26# Santa Clara, CA 95054
27#
28# Makefile for the NetXen NIC Driver
29#
30
31
32obj-$(CONFIG_NETXEN_NIC) := netxen_nic.o
33
34netxen_nic-y := netxen_nic_hw.o netxen_nic_main.o netxen_nic_init.o \
35 netxen_nic_isr.o netxen_nic_ethtool.o netxen_nic_niu.o
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
new file mode 100644
index 000000000000..d925053fe597
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic.h
@@ -0,0 +1,1028 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30#ifndef _NETXEN_NIC_H_
31#define _NETXEN_NIC_H_
32
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/types.h>
36#include <linux/compiler.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/ioport.h>
41#include <linux/pci.h>
42#include <linux/netdevice.h>
43#include <linux/etherdevice.h>
44#include <linux/ip.h>
45#include <linux/in.h>
46#include <linux/tcp.h>
47#include <linux/skbuff.h>
48#include <linux/version.h>
49
50#include <linux/ethtool.h>
51#include <linux/mii.h>
52#include <linux/interrupt.h>
53#include <linux/timer.h>
54
55#include <linux/mm.h>
56#include <linux/mman.h>
57
58#include <asm/system.h>
59#include <asm/io.h>
60#include <asm/byteorder.h>
61#include <asm/uaccess.h>
62#include <asm/pgtable.h>
63
64#include "netxen_nic_hw.h"
65
66#define NETXEN_NIC_BUILD_NO "5"
67#define _NETXEN_NIC_LINUX_MAJOR 2
68#define _NETXEN_NIC_LINUX_MINOR 3
69#define _NETXEN_NIC_LINUX_SUBVERSION 59
70#define NETXEN_NIC_LINUX_VERSIONID "2.3.59" "-" NETXEN_NIC_BUILD_NO
71#define NETXEN_NIC_FW_VERSIONID "2.3.59"
72
73#define RCV_DESC_RINGSIZE \
74 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
75#define STATUS_DESC_RINGSIZE \
76 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
77#define TX_RINGSIZE \
78 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
79#define RCV_BUFFSIZE \
80 (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
81#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
82
83#define NETXEN_NETDEV_STATUS 0x1
84
85#define ADDR_IN_WINDOW1(off) \
86 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
87
88/*
89 * normalize a 64MB crb address to 32MB PCI window
90 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
91 */
92#define NETXEN_CRB_NORMAL(reg) \
93 (reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST
94
95#define NETXEN_CRB_NORMALIZE(adapter, reg) \
96 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
97
98#define FIRST_PAGE_GROUP_START 0
99#define FIRST_PAGE_GROUP_END 0x400000
100
101#define SECOND_PAGE_GROUP_START 0x4000000
102#define SECOND_PAGE_GROUP_END 0x66BC000
103
104#define THIRD_PAGE_GROUP_START 0x70E4000
105#define THIRD_PAGE_GROUP_END 0x8000000
106
107#define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
108#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
109#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
110
111#define MAX_RX_BUFFER_LENGTH 2000
112#define MAX_RX_JUMBO_BUFFER_LENGTH 9046
113#define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - NET_IP_ALIGN)
114#define RX_JUMBO_DMA_MAP_LEN \
115 (MAX_RX_JUMBO_BUFFER_LENGTH - NET_IP_ALIGN)
116#define NETXEN_ROM_ROUNDUP 0x80000000ULL
117
118/*
119 * Maximum number of ring contexts
120 */
121#define MAX_RING_CTX 1
122
123/* Opcodes to be used with the commands */
124enum {
125 TX_ETHER_PKT = 0x01,
126/* The following opcodes are for IP checksum */
127 TX_TCP_PKT,
128 TX_UDP_PKT,
129 TX_IP_PKT,
130 TX_TCP_LSO,
131 TX_IPSEC,
132 TX_IPSEC_CMD
133};
134
135/* The following opcodes are for internal consumption. */
136#define NETXEN_CONTROL_OP 0x10
137#define PEGNET_REQUEST 0x11
138
139#define MAX_NUM_CARDS 4
140
141#define MAX_BUFFERS_PER_CMD 32
142
143/*
144 * Following are the states of the Phantom. Phantom will set them and
145 * Host will read to check if the fields are correct.
146 */
147#define PHAN_INITIALIZE_START 0xff00
148#define PHAN_INITIALIZE_FAILED 0xffff
149#define PHAN_INITIALIZE_COMPLETE 0xff01
150
151/* Host writes the following to notify that it has done the init-handshake */
152#define PHAN_INITIALIZE_ACK 0xf00f
153
154#define NUM_RCV_DESC_RINGS 2 /* No of Rcv Descriptor contexts */
155
156/* descriptor types */
157#define RCV_DESC_NORMAL 0x01
158#define RCV_DESC_JUMBO 0x02
159#define RCV_DESC_NORMAL_CTXID 0
160#define RCV_DESC_JUMBO_CTXID 1
161
162#define RCV_DESC_TYPE(ID) \
163 ((ID == RCV_DESC_JUMBO_CTXID) ? RCV_DESC_JUMBO : RCV_DESC_NORMAL)
164
165#define MAX_CMD_DESCRIPTORS 1024
166#define MAX_RCV_DESCRIPTORS 32768
167#define MAX_JUMBO_RCV_DESCRIPTORS 1024
168#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
169#define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
170#define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
171#define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
172#define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS)
173#define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
174
175#define MIN_TX_COUNT 4096
176#define MIN_RX_COUNT 4096
177
178#define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
179
180#define PHAN_PEG_RCV_INITIALIZED 0xff01
181#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
182
183#define get_next_index(index, length) \
184 (((index) + 1) & ((length) - 1))
185
186#define get_index_range(index,length,count) \
187 (((index) + (count)) & ((length) - 1))
188
189/*
190 * Following data structures describe the descriptors that will be used.
191 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
192 * we are doing LSO (above the 1500 size packet) only.
193 */
194
195/*
196 * The size of reference handle been changed to 16 bits to pass the MSS fields
197 * for the LSO packet
198 */
199
200#define FLAGS_CHECKSUM_ENABLED 0x01
201#define FLAGS_LSO_ENABLED 0x02
202#define FLAGS_IPSEC_SA_ADD 0x04
203#define FLAGS_IPSEC_SA_DELETE 0x08
204#define FLAGS_VLAN_TAGGED 0x10
205
206#define CMD_DESC_TOTAL_LENGTH(cmd_desc) \
207 ((cmd_desc)->length_tcp_hdr & 0x00FFFFFF)
208#define CMD_DESC_TCP_HDR_OFFSET(cmd_desc) \
209 (((cmd_desc)->length_tcp_hdr >> 24) & 0x0FF)
210#define CMD_DESC_PORT(cmd_desc) ((cmd_desc)->port_ctxid & 0x0F)
211#define CMD_DESC_CTX_ID(cmd_desc) (((cmd_desc)->port_ctxid >> 4) & 0x0F)
212
213#define CMD_DESC_TOTAL_LENGTH_WRT(cmd_desc, var) \
214 ((cmd_desc)->length_tcp_hdr |= ((var) & 0x00FFFFFF))
215#define CMD_DESC_TCP_HDR_OFFSET_WRT(cmd_desc, var) \
216 ((cmd_desc)->length_tcp_hdr |= (((var) << 24) & 0xFF000000))
217#define CMD_DESC_PORT_WRT(cmd_desc, var) \
218 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
219
220struct cmd_desc_type0 {
221 u64 netxen_next; /* for fragments handled by Phantom */
222 union {
223 struct {
224 u32 addr_low_part2;
225 u32 addr_high_part2;
226 };
227 u64 addr_buffer2;
228 };
229
230 /* Bit pattern: 0-23 total length, 24-32 tcp header offset */
231 u32 length_tcp_hdr;
232 u8 ip_hdr_offset; /* For LSO only */
233 u8 num_of_buffers; /* total number of segments */
234 u8 flags; /* as defined above */
235 u8 opcode;
236
237 u16 reference_handle; /* changed to u16 to add mss */
238 u16 mss; /* passed by NDIS_PACKET for LSO */
239 /* Bit pattern 0-3 port, 0-3 ctx id */
240 u8 port_ctxid;
241 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
242 u16 conn_id; /* IPSec offoad only */
243
244 union {
245 struct {
246 u32 addr_low_part3;
247 u32 addr_high_part3;
248 };
249 u64 addr_buffer3;
250 };
251
252 union {
253 struct {
254 u32 addr_low_part1;
255 u32 addr_high_part1;
256 };
257 u64 addr_buffer1;
258 };
259
260 u16 buffer1_length;
261 u16 buffer2_length;
262 u16 buffer3_length;
263 u16 buffer4_length;
264
265 union {
266 struct {
267 u32 addr_low_part4;
268 u32 addr_high_part4;
269 };
270 u64 addr_buffer4;
271 };
272
273} __attribute__ ((aligned(64)));
274
275/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
276struct rcv_desc {
277 u16 reference_handle;
278 u16 reserved;
279 u32 buffer_length; /* allocated buffer length (usually 2K) */
280 u64 addr_buffer;
281};
282
283/* opcode field in status_desc */
284#define RCV_NIC_PKT (0xA)
285#define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
286
287/* for status field in status_desc */
288#define STATUS_NEED_CKSUM (1)
289#define STATUS_CKSUM_OK (2)
290
291/* owner bits of status_desc */
292#define STATUS_OWNER_HOST (0x1)
293#define STATUS_OWNER_PHANTOM (0x2)
294
295#define NETXEN_PROT_IP (1)
296#define NETXEN_PROT_UNKNOWN (0)
297
298/* Note: sizeof(status_desc) should always be a mutliple of 2 */
299#define STATUS_DESC_PORT(status_desc) \
300 ((status_desc)->port_status_type_op & 0x0F)
301#define STATUS_DESC_STATUS(status_desc) \
302 (((status_desc)->port_status_type_op >> 4) & 0x0F)
303#define STATUS_DESC_TYPE(status_desc) \
304 (((status_desc)->port_status_type_op >> 8) & 0x0F)
305#define STATUS_DESC_OPCODE(status_desc) \
306 (((status_desc)->port_status_type_op >> 12) & 0x0F)
307
308struct status_desc {
309 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-15 opcode */
310 u16 port_status_type_op;
311 u16 total_length; /* NIC mode */
312 u16 reference_handle; /* handle for the associated packet */
313 /* Bit pattern: 0-1 owner, 2-5 protocol */
314 u16 owner; /* Owner of the descriptor */
315} __attribute__ ((aligned(8)));
316
317enum {
318 NETXEN_RCV_PEG_0 = 0,
319 NETXEN_RCV_PEG_1
320};
321/* The version of the main data structure */
322#define NETXEN_BDINFO_VERSION 1
323
324/* Magic number to let user know flash is programmed */
325#define NETXEN_BDINFO_MAGIC 0x12345678
326
327/* Max number of Gig ports on a Phantom board */
328#define NETXEN_MAX_PORTS 4
329
330typedef enum {
331 NETXEN_BRDTYPE_P1_BD = 0x0000,
332 NETXEN_BRDTYPE_P1_SB = 0x0001,
333 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
334 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
335
336 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
337 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
338 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
339 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
340 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
341
342 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
343 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
344 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
345} netxen_brdtype_t;
346
347typedef enum {
348 NETXEN_BRDMFG_INVENTEC = 1
349} netxen_brdmfg;
350
351typedef enum {
352 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
353 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
354 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
355 MEM_ORG_256Mbx4 = 0x3,
356 MEM_ORG_256Mbx8 = 0x4,
357 MEM_ORG_256Mbx16 = 0x5,
358 MEM_ORG_512Mbx4 = 0x6,
359 MEM_ORG_512Mbx8 = 0x7,
360 MEM_ORG_512Mbx16 = 0x8,
361 MEM_ORG_1Gbx4 = 0x9,
362 MEM_ORG_1Gbx8 = 0xa,
363 MEM_ORG_1Gbx16 = 0xb,
364 MEM_ORG_2Gbx4 = 0xc,
365 MEM_ORG_2Gbx8 = 0xd,
366 MEM_ORG_2Gbx16 = 0xe,
367 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
368 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
369} netxen_mn_mem_org_t;
370
371typedef enum {
372 MEM_ORG_512Kx36 = 0x0,
373 MEM_ORG_1Mx36 = 0x1,
374 MEM_ORG_2Mx36 = 0x2
375} netxen_sn_mem_org_t;
376
377typedef enum {
378 MEM_DEPTH_4MB = 0x1,
379 MEM_DEPTH_8MB = 0x2,
380 MEM_DEPTH_16MB = 0x3,
381 MEM_DEPTH_32MB = 0x4,
382 MEM_DEPTH_64MB = 0x5,
383 MEM_DEPTH_128MB = 0x6,
384 MEM_DEPTH_256MB = 0x7,
385 MEM_DEPTH_512MB = 0x8,
386 MEM_DEPTH_1GB = 0x9,
387 MEM_DEPTH_2GB = 0xa,
388 MEM_DEPTH_4GB = 0xb,
389 MEM_DEPTH_8GB = 0xc,
390 MEM_DEPTH_16GB = 0xd,
391 MEM_DEPTH_32GB = 0xe
392} netxen_mem_depth_t;
393
394struct netxen_board_info {
395 u32 header_version;
396
397 u32 board_mfg;
398 u32 board_type;
399 u32 board_num;
400 u32 chip_id;
401 u32 chip_minor;
402 u32 chip_major;
403 u32 chip_pkg;
404 u32 chip_lot;
405
406 u32 port_mask; /* available niu ports */
407 u32 peg_mask; /* available pegs */
408 u32 icache_ok; /* can we run with icache? */
409 u32 dcache_ok; /* can we run with dcache? */
410 u32 casper_ok;
411
412 u32 mac_addr_lo_0;
413 u32 mac_addr_lo_1;
414 u32 mac_addr_lo_2;
415 u32 mac_addr_lo_3;
416
417 /* MN-related config */
418 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
419 u32 mn_sync_shift_cclk;
420 u32 mn_sync_shift_mclk;
421 u32 mn_wb_en;
422 u32 mn_crystal_freq; /* in MHz */
423 u32 mn_speed; /* in MHz */
424 u32 mn_org;
425 u32 mn_depth;
426 u32 mn_ranks_0; /* ranks per slot */
427 u32 mn_ranks_1; /* ranks per slot */
428 u32 mn_rd_latency_0;
429 u32 mn_rd_latency_1;
430 u32 mn_rd_latency_2;
431 u32 mn_rd_latency_3;
432 u32 mn_rd_latency_4;
433 u32 mn_rd_latency_5;
434 u32 mn_rd_latency_6;
435 u32 mn_rd_latency_7;
436 u32 mn_rd_latency_8;
437 u32 mn_dll_val[18];
438 u32 mn_mode_reg; /* MIU DDR Mode Register */
439 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
440 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
441 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
442 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
443
444 /* SN-related config */
445 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
446 u32 sn_pt_mode; /* pass through mode */
447 u32 sn_ecc_en;
448 u32 sn_wb_en;
449 u32 sn_crystal_freq;
450 u32 sn_speed;
451 u32 sn_org;
452 u32 sn_depth;
453 u32 sn_dll_tap;
454 u32 sn_rd_latency;
455
456 u32 mac_addr_hi_0;
457 u32 mac_addr_hi_1;
458 u32 mac_addr_hi_2;
459 u32 mac_addr_hi_3;
460
461 u32 magic; /* indicates flash has been initialized */
462
463 u32 mn_rdimm;
464 u32 mn_dll_override;
465
466};
467
468#define FLASH_NUM_PORTS (4)
469
470struct netxen_flash_mac_addr {
471 u32 flash_addr[32];
472};
473
474struct netxen_user_old_info {
475 u8 flash_md5[16];
476 u8 crbinit_md5[16];
477 u8 brdcfg_md5[16];
478 /* bootloader */
479 u32 bootld_version;
480 u32 bootld_size;
481 u8 bootld_md5[16];
482 /* image */
483 u32 image_version;
484 u32 image_size;
485 u8 image_md5[16];
486 /* primary image status */
487 u32 primary_status;
488 u32 secondary_present;
489
490 /* MAC address , 4 ports */
491 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
492};
493#define FLASH_NUM_MAC_PER_PORT 32
494struct netxen_user_info {
495 u8 flash_md5[16 * 64];
496 /* bootloader */
497 u32 bootld_version;
498 u32 bootld_size;
499 /* image */
500 u32 image_version;
501 u32 image_size;
502 /* primary image status */
503 u32 primary_status;
504 u32 secondary_present;
505
506 /* MAC address , 4 ports, 32 address per port */
507 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
508 u32 sub_sys_id;
509 u8 serial_num[32];
510
511 /* Any user defined data */
512};
513
514/*
515 * Flash Layout - new format.
516 */
517struct netxen_new_user_info {
518 u8 flash_md5[16 * 64];
519 /* bootloader */
520 u32 bootld_version;
521 u32 bootld_size;
522 /* image */
523 u32 image_version;
524 u32 image_size;
525 /* primary image status */
526 u32 primary_status;
527 u32 secondary_present;
528
529 /* MAC address , 4 ports, 32 address per port */
530 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
531 u32 sub_sys_id;
532 u8 serial_num[32];
533
534 /* Any user defined data */
535};
536
537#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
538#define SECONDARY_IMAGE_ABSENT 0xffffffff
539#define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
540#define PRIMARY_IMAGE_BAD 0xffffffff
541
542/* Flash memory map */
543typedef enum {
544 CRBINIT_START = 0, /* Crbinit section */
545 BRDCFG_START = 0x4000, /* board config */
546 INITCODE_START = 0x6000, /* pegtune code */
547 BOOTLD_START = 0x10000, /* bootld */
548 IMAGE_START = 0x43000, /* compressed image */
549 SECONDARY_START = 0x200000, /* backup images */
550 PXE_START = 0x3E0000, /* user defined region */
551 USER_START = 0x3E8000, /* User defined region for new boards */
552 FIXED_START = 0x3F0000 /* backup of crbinit */
553} netxen_flash_map_t;
554
555#define USER_START_OLD PXE_START /* for backward compatibility */
556
557#define FLASH_START (CRBINIT_START)
558#define INIT_SECTOR (0)
559#define PRIMARY_START (BOOTLD_START)
560#define FLASH_CRBINIT_SIZE (0x4000)
561#define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
562#define FLASH_USER_SIZE (sizeof(netxen_user_info)/sizeof(u32))
563#define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START)
564#define NUM_PRIMARY_SECTORS (0x20)
565#define NUM_CONFIG_SECTORS (1)
566#define PFX "netxen: "
567
568/* Note: Make sure to not call this before adapter->port is valid */
569#if !defined(NETXEN_DEBUG)
570#define DPRINTK(klevel, fmt, args...) do { \
571 } while (0)
572#else
573#define DPRINTK(klevel, fmt, args...) do { \
574 printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
575 (adapter != NULL && adapter->port != NULL && \
576 adapter->port[0] != NULL && \
577 adapter->port[0]->netdev != NULL) ? \
578 adapter->port[0]->netdev->name : NULL, \
579 ## args); } while(0)
580#endif
581
582/* Number of status descriptors to handle per interrupt */
583#define MAX_STATUS_HANDLE (128)
584
585/*
586 * netxen_skb_frag{} is to contain mapping info for each SG list. This
587 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
588 */
589struct netxen_skb_frag {
590 u64 dma;
591 u32 length;
592};
593
594/* Following defines are for the state of the buffers */
595#define NETXEN_BUFFER_FREE 0
596#define NETXEN_BUFFER_BUSY 1
597
598/*
599 * There will be one netxen_buffer per skb packet. These will be
600 * used to save the dma info for pci_unmap_page()
601 */
602struct netxen_cmd_buffer {
603 struct sk_buff *skb;
604 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
605 u32 total_length;
606 u32 mss;
607 u16 port;
608 u8 cmd;
609 u8 frag_count;
610 unsigned long time_stamp;
611 u32 state;
612 u32 no_of_descriptors;
613};
614
615/* In rx_buffer, we do not need multiple fragments as is a single buffer */
616struct netxen_rx_buffer {
617 struct sk_buff *skb;
618 u64 dma;
619 u16 ref_handle;
620 u16 state;
621};
622
623/* Board types */
624#define NETXEN_NIC_GBE 0x01
625#define NETXEN_NIC_XGBE 0x02
626
627/*
628 * One hardware_context{} per adapter
629 * contains interrupt info as well shared hardware info.
630 */
631struct netxen_hardware_context {
632 struct pci_dev *pdev;
633 void __iomem *pci_base0;
634 void __iomem *pci_base1;
635 void __iomem *pci_base2;
636
637 u8 revision_id;
638 u16 board_type;
639 u16 max_ports;
640 struct netxen_board_info boardcfg;
641 u32 xg_linkup;
642 u32 qg_linksup;
643 /* Address of cmd ring in Phantom */
644 struct cmd_desc_type0 *cmd_desc_head;
645 char *pauseaddr;
646 struct pci_dev *cmd_desc_pdev;
647 dma_addr_t cmd_desc_phys_addr;
648 dma_addr_t pause_physaddr;
649 struct pci_dev *pause_pdev;
650 struct netxen_adapter *adapter;
651};
652
653#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
654#define ETHERNET_FCS_SIZE 4
655
656struct netxen_adapter_stats {
657 u64 ints;
658 u64 hostints;
659 u64 otherints;
660 u64 process_rcv;
661 u64 process_xmit;
662 u64 noxmitdone;
663 u64 xmitcsummed;
664 u64 post_called;
665 u64 posted;
666 u64 lastposted;
667 u64 goodskbposts;
668};
669
670/*
671 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
672 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
673 */
674struct netxen_rcv_desc_ctx {
675 u32 flags;
676 u32 producer;
677 u32 rcv_pending; /* Num of bufs posted in phantom */
678 u32 rcv_free; /* Num of bufs in free list */
679 dma_addr_t phys_addr;
680 struct pci_dev *phys_pdev;
681 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
682 u32 max_rx_desc_count;
683 u32 dma_size;
684 u32 skb_size;
685 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
686 int begin_alloc;
687};
688
689/*
690 * Receive context. There is one such structure per instance of the
691 * receive processing. Any state information that is relevant to
692 * the receive, and is must be in this structure. The global data may be
693 * present elsewhere.
694 */
695struct netxen_recv_context {
696 struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
697 u32 status_rx_producer;
698 u32 status_rx_consumer;
699 dma_addr_t rcv_status_desc_phys_addr;
700 struct pci_dev *rcv_status_desc_pdev;
701 struct status_desc *rcv_status_desc_head;
702};
703
704#define NETXEN_NIC_MSI_ENABLED 0x02
705
706struct netxen_drvops;
707
708struct netxen_adapter {
709 struct netxen_hardware_context ahw;
710 int port_count; /* Number of configured ports */
711 int active_ports; /* Number of open ports */
712 struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */
713 spinlock_t tx_lock;
714 spinlock_t lock;
715 struct work_struct watchdog_task;
716 struct work_struct tx_timeout_task;
717 struct timer_list watchdog_timer;
718
719 u32 curr_window;
720
721 u32 cmd_producer;
722 u32 cmd_consumer;
723
724 u32 last_cmd_consumer;
725 u32 max_tx_desc_count;
726 u32 max_rx_desc_count;
727 u32 max_jumbo_rx_desc_count;
728 /* Num of instances active on cmd buffer ring */
729 u32 proc_cmd_buf_counter;
730
731 u32 num_threads, total_threads; /*Use to keep track of xmit threads */
732
733 u32 flags;
734 u32 irq;
735 int driver_mismatch;
736 u32 temp;
737
738 struct netxen_adapter_stats stats;
739
740 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
741
742 /*
743 * Receive instances. These can be either one per port,
744 * or one per peg, etc.
745 */
746 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
747
748 int is_up;
749 int work_done;
750 struct netxen_drvops *ops;
751}; /* netxen_adapter structure */
752
753/* Max number of xmit producer threads that can run simultaneously */
754#define MAX_XMIT_PRODUCERS 16
755
756struct netxen_port_stats {
757 u64 rcvdbadskb;
758 u64 xmitcalled;
759 u64 xmitedframes;
760 u64 xmitfinished;
761 u64 badskblen;
762 u64 nocmddescriptor;
763 u64 polled;
764 u64 uphappy;
765 u64 updropped;
766 u64 uplcong;
767 u64 uphcong;
768 u64 upmcong;
769 u64 updunno;
770 u64 skbfreed;
771 u64 txdropped;
772 u64 txnullskb;
773 u64 csummed;
774 u64 no_rcv;
775 u64 rxbytes;
776 u64 txbytes;
777};
778
779struct netxen_port {
780 struct netxen_adapter *adapter;
781
782 u16 portnum; /* GBE port number */
783 u16 link_speed;
784 u16 link_duplex;
785 u16 link_autoneg;
786
787 int flags;
788
789 struct net_device *netdev;
790 struct pci_dev *pdev;
791 struct net_device_stats net_stats;
792 struct netxen_port_stats stats;
793};
794
795#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
796 ((adapter)->ahw.pci_base0 + (off))
797#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
798 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
799#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
800 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
801
802static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
803 unsigned long off)
804{
805 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
806 return (adapter->ahw.pci_base0 + off);
807 } else if ((off < SECOND_PAGE_GROUP_END) &&
808 (off >= SECOND_PAGE_GROUP_START)) {
809 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
810 } else if ((off < THIRD_PAGE_GROUP_END) &&
811 (off >= THIRD_PAGE_GROUP_START)) {
812 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
813 }
814 return NULL;
815}
816
817static inline void __iomem *pci_base(struct netxen_adapter *adapter,
818 unsigned long off)
819{
820 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
821 return adapter->ahw.pci_base0;
822 } else if ((off < SECOND_PAGE_GROUP_END) &&
823 (off >= SECOND_PAGE_GROUP_START)) {
824 return adapter->ahw.pci_base1;
825 } else if ((off < THIRD_PAGE_GROUP_END) &&
826 (off >= THIRD_PAGE_GROUP_START)) {
827 return adapter->ahw.pci_base2;
828 }
829 return NULL;
830}
831
832struct netxen_drvops {
833 int (*enable_phy_interrupts) (struct netxen_adapter *, int);
834 int (*disable_phy_interrupts) (struct netxen_adapter *, int);
835 void (*handle_phy_intr) (struct netxen_adapter *);
836 int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t);
837 int (*set_mtu) (struct netxen_port *, int);
838 int (*set_promisc) (struct netxen_adapter *, int,
839 netxen_niu_prom_mode_t);
840 int (*unset_promisc) (struct netxen_adapter *, int,
841 netxen_niu_prom_mode_t);
842 int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *);
843 int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val);
844 int (*init_port) (struct netxen_adapter *, int);
845 void (*init_niu) (struct netxen_adapter *);
846 int (*stop_port) (struct netxen_adapter *, int);
847};
848
849extern char netxen_nic_driver_name[];
850
851int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
852 int port);
853int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
854 int port);
855int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
856 int port);
857int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
858 int port);
859int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
860 int port);
861int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
862 int port);
863void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
864void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
865void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port,
866 long enable);
867void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port,
868 long enable);
869int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg,
870 __le32 * readval);
871int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy,
872 long reg, __le32 val);
873
874/* Functions available from netxen_nic_hw.c */
875int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu);
876int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu);
877void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
878void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
879void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
880int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
881void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
882void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
883
884int netxen_nic_get_board_info(struct netxen_adapter *adapter);
885int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
886 int len);
887int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
888 int len);
889void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
890 unsigned long off, int data);
891
892/* Functions from netxen_nic_init.c */
893void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
894void netxen_load_firmware(struct netxen_adapter *adapter);
895int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
896int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
897int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data);
898int netxen_rom_se(struct netxen_adapter *adapter, int addr);
899int netxen_do_rom_se(struct netxen_adapter *adapter, int addr);
900
901/* Functions from netxen_nic_isr.c */
902void netxen_nic_isr_other(struct netxen_adapter *adapter);
903void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port,
904 u32 link);
905void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port,
906 u32 enable);
907void netxen_nic_stop_all_ports(struct netxen_adapter *adapter);
908void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
909void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
910void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
911 struct pci_dev **used_dev);
912void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
913int netxen_init_firmware(struct netxen_adapter *adapter);
914void netxen_free_hw_resources(struct netxen_adapter *adapter);
915void netxen_tso_check(struct netxen_adapter *adapter,
916 struct cmd_desc_type0 *desc, struct sk_buff *skb);
917int netxen_nic_hw_resources(struct netxen_adapter *adapter);
918void netxen_nic_clear_stats(struct netxen_adapter *adapter);
919int
920netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
921 struct netxen_port *port);
922int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
923int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
924void netxen_watchdog_task(unsigned long v);
925void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
926 u32 ringid);
927void netxen_process_cmd_ring(unsigned long data);
928u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
929void netxen_nic_set_multi(struct net_device *netdev);
930int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
931int netxen_nic_set_mac(struct net_device *netdev, void *p);
932struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
933
934static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
935{
936 /*
937 * ISR_INT_MASK: Can be read from window 0 or 1.
938 */
939 writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
940
941}
942
943static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
944{
945 u32 mask;
946
947 switch (adapter->ahw.board_type) {
948 case NETXEN_NIC_GBE:
949 mask = 0x77b;
950 break;
951 case NETXEN_NIC_XGBE:
952 mask = 0x77f;
953 break;
954 default:
955 mask = 0x7ff;
956 break;
957 }
958
959 writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
960
961 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
962 mask = 0xbff;
963 writel(mask, PCI_OFFSET_SECOND_RANGE(adapter,
964 ISR_INT_TARGET_MASK));
965 }
966}
967
968/*
969 * NetXen Board information
970 */
971
972#define NETXEN_MAX_SHORT_NAME 16
973struct netxen_brdinfo {
974 netxen_brdtype_t brdtype; /* type of board */
975 long ports; /* max no of physical ports */
976 char short_name[NETXEN_MAX_SHORT_NAME];
977};
978
979static const struct netxen_brdinfo netxen_boards[] = {
980 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
981 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
982 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
983 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
984 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
985 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
986};
987
988#define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo))
989
990static inline void get_brd_port_by_type(u32 type, int *ports)
991{
992 int i, found = 0;
993 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
994 if (netxen_boards[i].brdtype == type) {
995 *ports = netxen_boards[i].ports;
996 found = 1;
997 break;
998 }
999 }
1000 if (!found)
1001 *ports = 0;
1002}
1003
1004static inline void get_brd_name_by_type(u32 type, char *name)
1005{
1006 int i, found = 0;
1007 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1008 if (netxen_boards[i].brdtype == type) {
1009 strcpy(name, netxen_boards[i].short_name);
1010 found = 1;
1011 break;
1012 }
1013
1014 }
1015 if (!found)
1016 name = "Unknown";
1017}
1018
1019int netxen_is_flash_supported(struct netxen_adapter *adapter);
1020int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
1021
1022extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1023extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1024 int *valp);
1025
1026extern struct ethtool_ops netxen_nic_ethtool_ops;
1027
1028#endif /* __NETXEN_NIC_H_ */
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
new file mode 100644
index 000000000000..9a914aeba5bc
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -0,0 +1,741 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * ethtool support for netxen nic
31 *
32 */
33
34#include <linux/types.h>
35#include <asm/uaccess.h>
36#include <linux/pci.h>
37#include <asm/io.h>
38#include <linux/netdevice.h>
39#include <linux/ethtool.h>
40#include <linux/version.h>
41
42#include "netxen_nic_hw.h"
43#include "netxen_nic.h"
44#include "netxen_nic_phan_reg.h"
45#include "netxen_nic_ioctl.h"
46
47struct netxen_nic_stats {
48 char stat_string[ETH_GSTRING_LEN];
49 int sizeof_stat;
50 int stat_offset;
51};
52
53#define NETXEN_NIC_STAT(m) sizeof(((struct netxen_port *)0)->m), \
54 offsetof(struct netxen_port, m)
55
56#define NETXEN_NIC_PORT_WINDOW 0x10000
57#define NETXEN_NIC_INVALID_DATA 0xDEADBEEF
58
59static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = {
60 {"rcvd_bad_skb", NETXEN_NIC_STAT(stats.rcvdbadskb)},
61 {"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)},
62 {"xmited_frames", NETXEN_NIC_STAT(stats.xmitedframes)},
63 {"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)},
64 {"bad_skb_len", NETXEN_NIC_STAT(stats.badskblen)},
65 {"no_cmd_desc", NETXEN_NIC_STAT(stats.nocmddescriptor)},
66 {"polled", NETXEN_NIC_STAT(stats.polled)},
67 {"uphappy", NETXEN_NIC_STAT(stats.uphappy)},
68 {"updropped", NETXEN_NIC_STAT(stats.updropped)},
69 {"uplcong", NETXEN_NIC_STAT(stats.uplcong)},
70 {"uphcong", NETXEN_NIC_STAT(stats.uphcong)},
71 {"upmcong", NETXEN_NIC_STAT(stats.upmcong)},
72 {"updunno", NETXEN_NIC_STAT(stats.updunno)},
73 {"skb_freed", NETXEN_NIC_STAT(stats.skbfreed)},
74 {"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)},
75 {"tx_null_skb", NETXEN_NIC_STAT(stats.txnullskb)},
76 {"csummed", NETXEN_NIC_STAT(stats.csummed)},
77 {"no_rcv", NETXEN_NIC_STAT(stats.no_rcv)},
78 {"rx_bytes", NETXEN_NIC_STAT(stats.rxbytes)},
79 {"tx_bytes", NETXEN_NIC_STAT(stats.txbytes)},
80};
81
82#define NETXEN_NIC_STATS_LEN \
83 sizeof(netxen_nic_gstrings_stats) / sizeof(struct netxen_nic_stats)
84
85static const char netxen_nic_gstrings_test[][ETH_GSTRING_LEN] = {
86 "Register_Test_offline", "EEPROM_Test_offline",
87 "Interrupt_Test_offline", "Loopback_Test_offline",
88 "Link_Test_on_offline"
89};
90
91#define NETXEN_NIC_TEST_LEN sizeof(netxen_nic_gstrings_test) / ETH_GSTRING_LEN
92
93#define NETXEN_NIC_REGS_COUNT 42
94#define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32))
95#define NETXEN_MAX_EEPROM_LEN 1024
96
97static int netxen_nic_get_eeprom_len(struct net_device *dev)
98{
99 struct netxen_port *port = netdev_priv(dev);
100 struct netxen_adapter *adapter = port->adapter;
101 int n;
102
103 if ((netxen_rom_fast_read(adapter, 0, &n) == 0)
104 && (n & NETXEN_ROM_ROUNDUP)) {
105 n &= ~NETXEN_ROM_ROUNDUP;
106 if (n < NETXEN_MAX_EEPROM_LEN)
107 return n;
108 }
109 return 0;
110}
111
112static void
113netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
114{
115 struct netxen_port *port = netdev_priv(dev);
116 struct netxen_adapter *adapter = port->adapter;
117 u32 fw_major = 0;
118 u32 fw_minor = 0;
119 u32 fw_build = 0;
120
121 strncpy(drvinfo->driver, "netxen_nic", 32);
122 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
123 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
124 NETXEN_FW_VERSION_MAJOR));
125 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
126 NETXEN_FW_VERSION_MINOR));
127 fw_build = readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
128 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
129
130 strncpy(drvinfo->bus_info, pci_name(port->pdev), 32);
131 drvinfo->n_stats = NETXEN_NIC_STATS_LEN;
132 drvinfo->testinfo_len = NETXEN_NIC_TEST_LEN;
133 drvinfo->regdump_len = NETXEN_NIC_REGS_LEN;
134 drvinfo->eedump_len = netxen_nic_get_eeprom_len(dev);
135}
136
137static int
138netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
139{
140 struct netxen_port *port = netdev_priv(dev);
141 struct netxen_adapter *adapter = port->adapter;
142 struct netxen_board_info *boardinfo = &adapter->ahw.boardcfg;
143
144 /* read which mode */
145 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
146 ecmd->supported = (SUPPORTED_10baseT_Half |
147 SUPPORTED_10baseT_Full |
148 SUPPORTED_100baseT_Half |
149 SUPPORTED_100baseT_Full |
150 SUPPORTED_1000baseT_Half |
151 SUPPORTED_1000baseT_Full);
152
153 ecmd->advertising = (ADVERTISED_100baseT_Half |
154 ADVERTISED_100baseT_Full |
155 ADVERTISED_1000baseT_Half |
156 ADVERTISED_1000baseT_Full);
157
158 ecmd->port = PORT_TP;
159
160 if (netif_running(dev)) {
161 ecmd->speed = port->link_speed;
162 ecmd->duplex = port->link_duplex;
163 } else
164 return -EIO; /* link absent */
165 } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
166 ecmd->supported = (SUPPORTED_TP |
167 SUPPORTED_1000baseT_Full |
168 SUPPORTED_10000baseT_Full);
169 ecmd->advertising = (ADVERTISED_TP |
170 ADVERTISED_1000baseT_Full |
171 ADVERTISED_10000baseT_Full);
172 ecmd->port = PORT_TP;
173
174 ecmd->speed = SPEED_10000;
175 ecmd->duplex = DUPLEX_FULL;
176 ecmd->autoneg = AUTONEG_DISABLE;
177 } else
178 return -EIO;
179
180 ecmd->phy_address = port->portnum;
181 ecmd->transceiver = XCVR_EXTERNAL;
182
183 switch ((netxen_brdtype_t) boardinfo->board_type) {
184 case NETXEN_BRDTYPE_P2_SB35_4G:
185 case NETXEN_BRDTYPE_P2_SB31_2G:
186 ecmd->supported |= SUPPORTED_Autoneg;
187 ecmd->advertising |= ADVERTISED_Autoneg;
188 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
189 ecmd->supported |= SUPPORTED_TP;
190 ecmd->advertising |= ADVERTISED_TP;
191 ecmd->port = PORT_TP;
192 ecmd->autoneg = (boardinfo->board_type ==
193 NETXEN_BRDTYPE_P2_SB31_10G_CX4) ?
194 (AUTONEG_DISABLE) : (port->link_autoneg);
195 break;
196 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
197 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
198 ecmd->supported |= SUPPORTED_MII;
199 ecmd->advertising |= ADVERTISED_MII;
200 ecmd->port = PORT_FIBRE;
201 ecmd->autoneg = AUTONEG_DISABLE;
202 break;
203 case NETXEN_BRDTYPE_P2_SB31_10G:
204 ecmd->supported |= SUPPORTED_FIBRE;
205 ecmd->advertising |= ADVERTISED_FIBRE;
206 ecmd->port = PORT_FIBRE;
207 ecmd->autoneg = AUTONEG_DISABLE;
208 break;
209 default:
210 printk(KERN_ERR "netxen-nic: Unsupported board model %d\n",
211 (netxen_brdtype_t) boardinfo->board_type);
212 return -EIO;
213
214 }
215
216 return 0;
217}
218
219static int
220netxen_nic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
221{
222 struct netxen_port *port = netdev_priv(dev);
223 struct netxen_adapter *adapter = port->adapter;
224 __le32 status;
225
226 /* read which mode */
227 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
228 /* autonegotiation */
229 if (adapter->ops->phy_write
230 && adapter->ops->phy_write(adapter, port->portnum,
231 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
232 (__le32) ecmd->autoneg) != 0)
233 return -EIO;
234 else
235 port->link_autoneg = ecmd->autoneg;
236
237 if (adapter->ops->phy_read
238 && adapter->ops->phy_read(adapter, port->portnum,
239 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
240 &status) != 0)
241 return -EIO;
242
243 /* speed */
244 switch (ecmd->speed) {
245 case SPEED_10:
246 netxen_set_phy_speed(status, 0);
247 break;
248 case SPEED_100:
249 netxen_set_phy_speed(status, 1);
250 break;
251 case SPEED_1000:
252 netxen_set_phy_speed(status, 2);
253 break;
254 }
255 /* set duplex mode */
256 if (ecmd->duplex == DUPLEX_HALF)
257 netxen_clear_phy_duplex(status);
258 if (ecmd->duplex == DUPLEX_FULL)
259 netxen_set_phy_duplex(status);
260 if (adapter->ops->phy_write
261 && adapter->ops->phy_write(adapter, port->portnum,
262 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
263 *((int *)&status)) != 0)
264 return -EIO;
265 else {
266 port->link_speed = ecmd->speed;
267 port->link_duplex = ecmd->duplex;
268 }
269 } else
270 return -EOPNOTSUPP;
271
272 if (netif_running(dev)) {
273 dev->stop(dev);
274 dev->open(dev);
275 }
276 return 0;
277}
278
279static int netxen_nic_get_regs_len(struct net_device *dev)
280{
281 return NETXEN_NIC_REGS_LEN;
282}
283
284struct netxen_niu_regs {
285 __le32 reg[NETXEN_NIC_REGS_COUNT];
286};
287
288static struct netxen_niu_regs niu_registers[] = {
289 {
290 /* GB Mode */
291 {
292 NETXEN_NIU_GB_SERDES_RESET,
293 NETXEN_NIU_GB0_MII_MODE,
294 NETXEN_NIU_GB1_MII_MODE,
295 NETXEN_NIU_GB2_MII_MODE,
296 NETXEN_NIU_GB3_MII_MODE,
297 NETXEN_NIU_GB0_GMII_MODE,
298 NETXEN_NIU_GB1_GMII_MODE,
299 NETXEN_NIU_GB2_GMII_MODE,
300 NETXEN_NIU_GB3_GMII_MODE,
301 NETXEN_NIU_REMOTE_LOOPBACK,
302 NETXEN_NIU_GB0_HALF_DUPLEX,
303 NETXEN_NIU_GB1_HALF_DUPLEX,
304 NETXEN_NIU_RESET_SYS_FIFOS,
305 NETXEN_NIU_GB_CRC_DROP,
306 NETXEN_NIU_GB_DROP_WRONGADDR,
307 NETXEN_NIU_TEST_MUX_CTL,
308
309 NETXEN_NIU_GB_MAC_CONFIG_0(0),
310 NETXEN_NIU_GB_MAC_CONFIG_1(0),
311 NETXEN_NIU_GB_HALF_DUPLEX_CTRL(0),
312 NETXEN_NIU_GB_MAX_FRAME_SIZE(0),
313 NETXEN_NIU_GB_TEST_REG(0),
314 NETXEN_NIU_GB_MII_MGMT_CONFIG(0),
315 NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
316 NETXEN_NIU_GB_MII_MGMT_ADDR(0),
317 NETXEN_NIU_GB_MII_MGMT_CTRL(0),
318 NETXEN_NIU_GB_MII_MGMT_STATUS(0),
319 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
320 NETXEN_NIU_GB_INTERFACE_CTRL(0),
321 NETXEN_NIU_GB_INTERFACE_STATUS(0),
322 NETXEN_NIU_GB_STATION_ADDR_0(0),
323 NETXEN_NIU_GB_STATION_ADDR_1(0),
324 -1,
325 }
326 },
327 {
328 /* XG Mode */
329 {
330 NETXEN_NIU_XG_SINGLE_TERM,
331 NETXEN_NIU_XG_DRIVE_HI,
332 NETXEN_NIU_XG_DRIVE_LO,
333 NETXEN_NIU_XG_DTX,
334 NETXEN_NIU_XG_DEQ,
335 NETXEN_NIU_XG_WORD_ALIGN,
336 NETXEN_NIU_XG_RESET,
337 NETXEN_NIU_XG_POWER_DOWN,
338 NETXEN_NIU_XG_RESET_PLL,
339 NETXEN_NIU_XG_SERDES_LOOPBACK,
340 NETXEN_NIU_XG_DO_BYTE_ALIGN,
341 NETXEN_NIU_XG_TX_ENABLE,
342 NETXEN_NIU_XG_RX_ENABLE,
343 NETXEN_NIU_XG_STATUS,
344 NETXEN_NIU_XG_PAUSE_THRESHOLD,
345 NETXEN_NIU_XGE_CONFIG_0,
346 NETXEN_NIU_XGE_CONFIG_1,
347 NETXEN_NIU_XGE_IPG,
348 NETXEN_NIU_XGE_STATION_ADDR_0_HI,
349 NETXEN_NIU_XGE_STATION_ADDR_0_1,
350 NETXEN_NIU_XGE_STATION_ADDR_1_LO,
351 NETXEN_NIU_XGE_STATUS,
352 NETXEN_NIU_XGE_MAX_FRAME_SIZE,
353 NETXEN_NIU_XGE_PAUSE_FRAME_VALUE,
354 NETXEN_NIU_XGE_TX_BYTE_CNT,
355 NETXEN_NIU_XGE_TX_FRAME_CNT,
356 NETXEN_NIU_XGE_RX_BYTE_CNT,
357 NETXEN_NIU_XGE_RX_FRAME_CNT,
358 NETXEN_NIU_XGE_AGGR_ERROR_CNT,
359 NETXEN_NIU_XGE_MULTICAST_FRAME_CNT,
360 NETXEN_NIU_XGE_UNICAST_FRAME_CNT,
361 NETXEN_NIU_XGE_CRC_ERROR_CNT,
362 NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR,
363 NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR,
364 NETXEN_NIU_XGE_LOCAL_ERROR_CNT,
365 NETXEN_NIU_XGE_REMOTE_ERROR_CNT,
366 NETXEN_NIU_XGE_CONTROL_CHAR_CNT,
367 NETXEN_NIU_XGE_PAUSE_FRAME_CNT,
368 -1,
369 }
370 }
371};
372
373static void
374netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
375{
376 struct netxen_port *port = netdev_priv(dev);
377 struct netxen_adapter *adapter = port->adapter;
378 __le32 mode, *regs_buff = p;
379 void __iomem *addr;
380 int i, window;
381
382 memset(p, 0, NETXEN_NIC_REGS_LEN);
383 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
384 (port->pdev)->device;
385 /* which mode */
386 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_MODE, &regs_buff[0]);
387 mode = regs_buff[0];
388
389 /* Common registers to all the modes */
390 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER,
391 &regs_buff[2]);
392 /* GB/XGB Mode */
393 mode = (mode / 2) - 1;
394 window = 0;
395 if (mode <= 1) {
396 for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) {
397 /* GB: port specific registers */
398 if (mode == 0 && i >= 19)
399 window = port->portnum * NETXEN_NIC_PORT_WINDOW;
400
401 NETXEN_NIC_LOCKED_READ_REG(niu_registers[mode].
402 reg[i - 3] + window,
403 &regs_buff[i]);
404 }
405
406 }
407}
408
409static void
410netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
411{
412 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
413 /* options can be added depending upon the mode */
414 wol->wolopts = 0;
415}
416
417static u32 netxen_nic_get_link(struct net_device *dev)
418{
419 struct netxen_port *port = netdev_priv(dev);
420 struct netxen_adapter *adapter = port->adapter;
421 __le32 status;
422
423 /* read which mode */
424 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
425 if (adapter->ops->phy_read
426 && adapter->ops->phy_read(adapter, port->portnum,
427 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
428 &status) != 0)
429 return -EIO;
430 else
431 return (netxen_get_phy_link(status));
432 } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
433 int val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
434 return val == XG_LINK_UP;
435 }
436 return -EIO;
437}
438
439static int
440netxen_nic_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
441 u8 * bytes)
442{
443 struct netxen_port *port = netdev_priv(dev);
444 struct netxen_adapter *adapter = port->adapter;
445 int offset;
446
447 if (eeprom->len == 0)
448 return -EINVAL;
449
450 eeprom->magic = (port->pdev)->vendor | ((port->pdev)->device << 16);
451 for (offset = 0; offset < eeprom->len; offset++)
452 if (netxen_rom_fast_read
453 (adapter, (8 * offset) + 8, (int *)eeprom->data) == -1)
454 return -EIO;
455 return 0;
456}
457
458static void
459netxen_nic_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring)
460{
461 struct netxen_port *port = netdev_priv(dev);
462 struct netxen_adapter *adapter = port->adapter;
463 int i, j;
464
465 ring->rx_pending = 0;
466 for (i = 0; i < MAX_RCV_CTX; ++i) {
467 for (j = 0; j < NUM_RCV_DESC_RINGS; j++)
468 ring->rx_pending +=
469 adapter->recv_ctx[i].rcv_desc[j].rcv_pending;
470 }
471
472 ring->rx_max_pending = adapter->max_rx_desc_count;
473 ring->tx_max_pending = adapter->max_tx_desc_count;
474 ring->rx_mini_max_pending = 0;
475 ring->rx_mini_pending = 0;
476 ring->rx_jumbo_max_pending = 0;
477 ring->rx_jumbo_pending = 0;
478}
479
480static void
481netxen_nic_get_pauseparam(struct net_device *dev,
482 struct ethtool_pauseparam *pause)
483{
484 struct netxen_port *port = netdev_priv(dev);
485 struct netxen_adapter *adapter = port->adapter;
486 __le32 val;
487
488 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
489 /* get flow control settings */
490 netxen_nic_read_w0(adapter,
491 NETXEN_NIU_GB_MAC_CONFIG_0(port->portnum),
492 (u32 *) & val);
493 pause->rx_pause = netxen_gb_get_rx_flowctl(val);
494 pause->tx_pause = netxen_gb_get_tx_flowctl(val);
495 /* get autoneg settings */
496 pause->autoneg = port->link_autoneg;
497 }
498}
499
500static int
501netxen_nic_set_pauseparam(struct net_device *dev,
502 struct ethtool_pauseparam *pause)
503{
504 struct netxen_port *port = netdev_priv(dev);
505 struct netxen_adapter *adapter = port->adapter;
506 __le32 val;
507 unsigned int autoneg;
508
509 /* read mode */
510 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
511 /* set flow control */
512 netxen_nic_read_w0(adapter,
513 NETXEN_NIU_GB_MAC_CONFIG_0(port->portnum),
514 (u32 *) & val);
515 if (pause->tx_pause)
516 netxen_gb_tx_flowctl(val);
517 else
518 netxen_gb_unset_tx_flowctl(val);
519 if (pause->rx_pause)
520 netxen_gb_rx_flowctl(val);
521 else
522 netxen_gb_unset_rx_flowctl(val);
523
524 netxen_nic_write_w0(adapter,
525 NETXEN_NIU_GB_MAC_CONFIG_0(port->portnum),
526 *(u32 *) (&val));
527 /* set autoneg */
528 autoneg = pause->autoneg;
529 if (adapter->ops->phy_write
530 && adapter->ops->phy_write(adapter, port->portnum,
531 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
532 (__le32) autoneg) != 0)
533 return -EIO;
534 else {
535 port->link_autoneg = pause->autoneg;
536 return 0;
537 }
538 } else
539 return -EOPNOTSUPP;
540}
541
542static int netxen_nic_reg_test(struct net_device *dev)
543{
544 struct netxen_port *port = netdev_priv(dev);
545 struct netxen_adapter *adapter = port->adapter;
546 u32 data_read, data_written, save;
547 __le32 mode;
548
549 /*
550 * first test the "Read Only" registers by writing which mode
551 */
552 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
553 if (netxen_get_niu_enable_ge(mode)) { /* GB Mode */
554 netxen_nic_read_w0(adapter,
555 NETXEN_NIU_GB_MII_MGMT_STATUS(port->portnum),
556 &data_read);
557
558 save = data_read;
559 if (data_read)
560 data_written = data_read & NETXEN_NIC_INVALID_DATA;
561 else
562 data_written = NETXEN_NIC_INVALID_DATA;
563 netxen_nic_write_w0(adapter,
564 NETXEN_NIU_GB_MII_MGMT_STATUS(port->
565 portnum),
566 data_written);
567 netxen_nic_read_w0(adapter,
568 NETXEN_NIU_GB_MII_MGMT_STATUS(port->portnum),
569 &data_read);
570
571 if (data_written == data_read) {
572 netxen_nic_write_w0(adapter,
573 NETXEN_NIU_GB_MII_MGMT_STATUS(port->
574 portnum),
575 save);
576
577 return 0;
578 }
579
580 /* netxen_niu_gb_mii_mgmt_indicators is read only */
581 netxen_nic_read_w0(adapter,
582 NETXEN_NIU_GB_MII_MGMT_INDICATE(port->
583 portnum),
584 &data_read);
585
586 save = data_read;
587 if (data_read)
588 data_written = data_read & NETXEN_NIC_INVALID_DATA;
589 else
590 data_written = NETXEN_NIC_INVALID_DATA;
591 netxen_nic_write_w0(adapter,
592 NETXEN_NIU_GB_MII_MGMT_INDICATE(port->
593 portnum),
594 data_written);
595
596 netxen_nic_read_w0(adapter,
597 NETXEN_NIU_GB_MII_MGMT_INDICATE(port->
598 portnum),
599 &data_read);
600
601 if (data_written == data_read) {
602 netxen_nic_write_w0(adapter,
603 NETXEN_NIU_GB_MII_MGMT_INDICATE
604 (port->portnum), save);
605 return 0;
606 }
607
608 /* netxen_niu_gb_interface_status is read only */
609 netxen_nic_read_w0(adapter,
610 NETXEN_NIU_GB_INTERFACE_STATUS(port->
611 portnum),
612 &data_read);
613
614 save = data_read;
615 if (data_read)
616 data_written = data_read & NETXEN_NIC_INVALID_DATA;
617 else
618 data_written = NETXEN_NIC_INVALID_DATA;
619 netxen_nic_write_w0(adapter,
620 NETXEN_NIU_GB_INTERFACE_STATUS(port->
621 portnum),
622 data_written);
623
624 netxen_nic_read_w0(adapter,
625 NETXEN_NIU_GB_INTERFACE_STATUS(port->
626 portnum),
627 &data_read);
628
629 if (data_written == data_read) {
630 netxen_nic_write_w0(adapter,
631 NETXEN_NIU_GB_INTERFACE_STATUS
632 (port->portnum), save);
633
634 return 0;
635 }
636 } /* GB Mode */
637 return 1;
638}
639
640static int netxen_nic_diag_test_count(struct net_device *dev)
641{
642 return NETXEN_NIC_TEST_LEN;
643}
644
645static void
646netxen_nic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
647 u64 * data)
648{
649 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { /* offline tests */
650 /* link test */
651 if (!(data[4] = (u64) netxen_nic_get_link(dev)))
652 eth_test->flags |= ETH_TEST_FL_FAILED;
653
654 if (netif_running(dev))
655 dev->stop(dev);
656
657 /* register tests */
658 if (!(data[0] = netxen_nic_reg_test(dev)))
659 eth_test->flags |= ETH_TEST_FL_FAILED;
660 /* other tests pass as of now */
661 data[1] = data[2] = data[3] = 1;
662 if (netif_running(dev))
663 dev->open(dev);
664 } else { /* online tests */
665 /* link test */
666 if (!(data[4] = (u64) netxen_nic_get_link(dev)))
667 eth_test->flags |= ETH_TEST_FL_FAILED;
668
669 /* other tests pass by default */
670 data[0] = data[1] = data[2] = data[3] = 1;
671 }
672}
673
674static void
675netxen_nic_get_strings(struct net_device *dev, u32 stringset, u8 * data)
676{
677 int index;
678
679 switch (stringset) {
680 case ETH_SS_TEST:
681 memcpy(data, *netxen_nic_gstrings_test,
682 NETXEN_NIC_TEST_LEN * ETH_GSTRING_LEN);
683 break;
684 case ETH_SS_STATS:
685 for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
686 memcpy(data + index * ETH_GSTRING_LEN,
687 netxen_nic_gstrings_stats[index].stat_string,
688 ETH_GSTRING_LEN);
689 }
690 break;
691 }
692}
693
694static int netxen_nic_get_stats_count(struct net_device *dev)
695{
696 return NETXEN_NIC_STATS_LEN;
697}
698
699static void
700netxen_nic_get_ethtool_stats(struct net_device *dev,
701 struct ethtool_stats *stats, u64 * data)
702{
703 struct netxen_port *port = netdev_priv(dev);
704 int index;
705
706 for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
707 char *p =
708 (char *)port + netxen_nic_gstrings_stats[index].stat_offset;
709 data[index] =
710 (netxen_nic_gstrings_stats[index].sizeof_stat ==
711 sizeof(u64)) ? *(u64 *) p : *(u32 *) p;
712 }
713
714}
715
716struct ethtool_ops netxen_nic_ethtool_ops = {
717 .get_settings = netxen_nic_get_settings,
718 .set_settings = netxen_nic_set_settings,
719 .get_drvinfo = netxen_nic_get_drvinfo,
720 .get_regs_len = netxen_nic_get_regs_len,
721 .get_regs = netxen_nic_get_regs,
722 .get_wol = netxen_nic_get_wol,
723 .get_link = netxen_nic_get_link,
724 .get_eeprom_len = netxen_nic_get_eeprom_len,
725 .get_eeprom = netxen_nic_get_eeprom,
726 .get_ringparam = netxen_nic_get_ringparam,
727 .get_pauseparam = netxen_nic_get_pauseparam,
728 .set_pauseparam = netxen_nic_set_pauseparam,
729 .get_tx_csum = ethtool_op_get_tx_csum,
730 .set_tx_csum = ethtool_op_set_tx_csum,
731 .get_sg = ethtool_op_get_sg,
732 .set_sg = ethtool_op_set_sg,
733 .get_tso = ethtool_op_get_tso,
734 .set_tso = ethtool_op_set_tso,
735 .self_test_count = netxen_nic_diag_test_count,
736 .self_test = netxen_nic_diag_test,
737 .get_strings = netxen_nic_get_strings,
738 .get_stats_count = netxen_nic_get_stats_count,
739 .get_ethtool_stats = netxen_nic_get_ethtool_stats,
740 .get_perm_addr = ethtool_op_get_perm_addr,
741};
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
new file mode 100644
index 000000000000..72c6ec4ee2a0
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -0,0 +1,678 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30#ifndef __NETXEN_NIC_HDR_H_
31#define __NETXEN_NIC_HDR_H_
32
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/version.h>
36
37#include <asm/semaphore.h>
38#include <linux/spinlock.h>
39#include <asm/irq.h>
40#include <linux/init.h>
41#include <linux/errno.h>
42#include <linux/pci.h>
43#include <linux/types.h>
44#include <asm/uaccess.h>
45#include <asm/string.h> /* for memset */
46
47/*
48 * The basic unit of access when reading/writing control registers.
49 */
50
51typedef __le32 netxen_crbword_t; /* single word in CRB space */
52
53enum {
54 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
55 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
56 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
57 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
58 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
59 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
60 NETXEN_HW_H6_CH_HUB_ADR = 0x08
61};
62
63/* Hub 0 */
64enum {
65 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
66 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
67};
68
69/* Hub 1 */
70enum {
71 NETXEN_HW_PS_CRB_AGT_ADR = 0x73,
72 NETXEN_HW_SS_CRB_AGT_ADR = 0x20,
73 NETXEN_HW_RPMX3_CRB_AGT_ADR = 0x0b,
74 NETXEN_HW_QMS_CRB_AGT_ADR = 0x00,
75 NETXEN_HW_SQGS0_CRB_AGT_ADR = 0x01,
76 NETXEN_HW_SQGS1_CRB_AGT_ADR = 0x02,
77 NETXEN_HW_SQGS2_CRB_AGT_ADR = 0x03,
78 NETXEN_HW_SQGS3_CRB_AGT_ADR = 0x04,
79 NETXEN_HW_C2C0_CRB_AGT_ADR = 0x58,
80 NETXEN_HW_C2C1_CRB_AGT_ADR = 0x59,
81 NETXEN_HW_C2C2_CRB_AGT_ADR = 0x5a,
82 NETXEN_HW_RPMX2_CRB_AGT_ADR = 0x0a,
83 NETXEN_HW_RPMX4_CRB_AGT_ADR = 0x0c,
84 NETXEN_HW_RPMX7_CRB_AGT_ADR = 0x0f,
85 NETXEN_HW_RPMX9_CRB_AGT_ADR = 0x12,
86 NETXEN_HW_SMB_CRB_AGT_ADR = 0x18
87};
88
89/* Hub 2 */
90enum {
91 NETXEN_HW_NIU_CRB_AGT_ADR = 0x31,
92 NETXEN_HW_I2C0_CRB_AGT_ADR = 0x19,
93 NETXEN_HW_I2C1_CRB_AGT_ADR = 0x29,
94
95 NETXEN_HW_SN_CRB_AGT_ADR = 0x10,
96 NETXEN_HW_I2Q_CRB_AGT_ADR = 0x20,
97 NETXEN_HW_LPC_CRB_AGT_ADR = 0x22,
98 NETXEN_HW_ROMUSB_CRB_AGT_ADR = 0x21,
99 NETXEN_HW_QM_CRB_AGT_ADR = 0x66,
100 NETXEN_HW_SQG0_CRB_AGT_ADR = 0x60,
101 NETXEN_HW_SQG1_CRB_AGT_ADR = 0x61,
102 NETXEN_HW_SQG2_CRB_AGT_ADR = 0x62,
103 NETXEN_HW_SQG3_CRB_AGT_ADR = 0x63,
104 NETXEN_HW_RPMX1_CRB_AGT_ADR = 0x09,
105 NETXEN_HW_RPMX5_CRB_AGT_ADR = 0x0d,
106 NETXEN_HW_RPMX6_CRB_AGT_ADR = 0x0e,
107 NETXEN_HW_RPMX8_CRB_AGT_ADR = 0x11
108};
109
110/* Hub 3 */
111enum {
112 NETXEN_HW_PH_CRB_AGT_ADR = 0x1A,
113 NETXEN_HW_SRE_CRB_AGT_ADR = 0x50,
114 NETXEN_HW_EG_CRB_AGT_ADR = 0x51,
115 NETXEN_HW_RPMX0_CRB_AGT_ADR = 0x08
116};
117
118/* Hub 4 */
119enum {
120 NETXEN_HW_PEGN0_CRB_AGT_ADR = 0x40,
121 NETXEN_HW_PEGN1_CRB_AGT_ADR,
122 NETXEN_HW_PEGN2_CRB_AGT_ADR,
123 NETXEN_HW_PEGN3_CRB_AGT_ADR,
124 NETXEN_HW_PEGNI_CRB_AGT_ADR,
125 NETXEN_HW_PEGND_CRB_AGT_ADR,
126 NETXEN_HW_PEGNC_CRB_AGT_ADR,
127 NETXEN_HW_PEGR0_CRB_AGT_ADR,
128 NETXEN_HW_PEGR1_CRB_AGT_ADR,
129 NETXEN_HW_PEGR2_CRB_AGT_ADR,
130 NETXEN_HW_PEGR3_CRB_AGT_ADR
131};
132
133/* Hub 5 */
134enum {
135 NETXEN_HW_PEGS0_CRB_AGT_ADR = 0x40,
136 NETXEN_HW_PEGS1_CRB_AGT_ADR,
137 NETXEN_HW_PEGS2_CRB_AGT_ADR,
138 NETXEN_HW_PEGS3_CRB_AGT_ADR,
139 NETXEN_HW_PEGSI_CRB_AGT_ADR,
140 NETXEN_HW_PEGSD_CRB_AGT_ADR,
141 NETXEN_HW_PEGSC_CRB_AGT_ADR
142};
143
144/* Hub 6 */
145enum {
146 NETXEN_HW_CAS0_CRB_AGT_ADR = 0x46,
147 NETXEN_HW_CAS1_CRB_AGT_ADR = 0x47,
148 NETXEN_HW_CAS2_CRB_AGT_ADR = 0x48,
149 NETXEN_HW_CAS3_CRB_AGT_ADR = 0x49,
150 NETXEN_HW_NCM_CRB_AGT_ADR = 0x16,
151 NETXEN_HW_TMR_CRB_AGT_ADR = 0x17,
152 NETXEN_HW_XDMA_CRB_AGT_ADR = 0x05,
153 NETXEN_HW_OCM0_CRB_AGT_ADR = 0x06,
154 NETXEN_HW_OCM1_CRB_AGT_ADR = 0x07
155};
156
157/* Floaters - non existent modules */
158#define NETXEN_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
159
160/* This field defines PCI/X adr [25:20] of agents on the CRB */
161enum {
162 NETXEN_HW_PX_MAP_CRB_PH = 0,
163 NETXEN_HW_PX_MAP_CRB_PS,
164 NETXEN_HW_PX_MAP_CRB_MN,
165 NETXEN_HW_PX_MAP_CRB_MS,
166 NETXEN_HW_PX_MAP_CRB_PGR1,
167 NETXEN_HW_PX_MAP_CRB_SRE,
168 NETXEN_HW_PX_MAP_CRB_NIU,
169 NETXEN_HW_PX_MAP_CRB_QMN,
170 NETXEN_HW_PX_MAP_CRB_SQN0,
171 NETXEN_HW_PX_MAP_CRB_SQN1,
172 NETXEN_HW_PX_MAP_CRB_SQN2,
173 NETXEN_HW_PX_MAP_CRB_SQN3,
174 NETXEN_HW_PX_MAP_CRB_QMS,
175 NETXEN_HW_PX_MAP_CRB_SQS0,
176 NETXEN_HW_PX_MAP_CRB_SQS1,
177 NETXEN_HW_PX_MAP_CRB_SQS2,
178 NETXEN_HW_PX_MAP_CRB_SQS3,
179 NETXEN_HW_PX_MAP_CRB_PGN0,
180 NETXEN_HW_PX_MAP_CRB_PGN1,
181 NETXEN_HW_PX_MAP_CRB_PGN2,
182 NETXEN_HW_PX_MAP_CRB_PGN3,
183 NETXEN_HW_PX_MAP_CRB_PGND,
184 NETXEN_HW_PX_MAP_CRB_PGNI,
185 NETXEN_HW_PX_MAP_CRB_PGS0,
186 NETXEN_HW_PX_MAP_CRB_PGS1,
187 NETXEN_HW_PX_MAP_CRB_PGS2,
188 NETXEN_HW_PX_MAP_CRB_PGS3,
189 NETXEN_HW_PX_MAP_CRB_PGSD,
190 NETXEN_HW_PX_MAP_CRB_PGSI,
191 NETXEN_HW_PX_MAP_CRB_SN,
192 NETXEN_HW_PX_MAP_CRB_PGR2,
193 NETXEN_HW_PX_MAP_CRB_EG,
194 NETXEN_HW_PX_MAP_CRB_PH2,
195 NETXEN_HW_PX_MAP_CRB_PS2,
196 NETXEN_HW_PX_MAP_CRB_CAM,
197 NETXEN_HW_PX_MAP_CRB_CAS0,
198 NETXEN_HW_PX_MAP_CRB_CAS1,
199 NETXEN_HW_PX_MAP_CRB_CAS2,
200 NETXEN_HW_PX_MAP_CRB_C2C0,
201 NETXEN_HW_PX_MAP_CRB_C2C1,
202 NETXEN_HW_PX_MAP_CRB_TIMR,
203 NETXEN_HW_PX_MAP_CRB_PGR3,
204 NETXEN_HW_PX_MAP_CRB_RPMX1,
205 NETXEN_HW_PX_MAP_CRB_RPMX2,
206 NETXEN_HW_PX_MAP_CRB_RPMX3,
207 NETXEN_HW_PX_MAP_CRB_RPMX4,
208 NETXEN_HW_PX_MAP_CRB_RPMX5,
209 NETXEN_HW_PX_MAP_CRB_RPMX6,
210 NETXEN_HW_PX_MAP_CRB_RPMX7,
211 NETXEN_HW_PX_MAP_CRB_XDMA,
212 NETXEN_HW_PX_MAP_CRB_I2Q,
213 NETXEN_HW_PX_MAP_CRB_ROMUSB,
214 NETXEN_HW_PX_MAP_CRB_CAS3,
215 NETXEN_HW_PX_MAP_CRB_RPMX0,
216 NETXEN_HW_PX_MAP_CRB_RPMX8,
217 NETXEN_HW_PX_MAP_CRB_RPMX9,
218 NETXEN_HW_PX_MAP_CRB_OCM0,
219 NETXEN_HW_PX_MAP_CRB_OCM1,
220 NETXEN_HW_PX_MAP_CRB_SMB,
221 NETXEN_HW_PX_MAP_CRB_I2C0,
222 NETXEN_HW_PX_MAP_CRB_I2C1,
223 NETXEN_HW_PX_MAP_CRB_LPC,
224 NETXEN_HW_PX_MAP_CRB_PGNC,
225 NETXEN_HW_PX_MAP_CRB_PGR0
226};
227
228/* This field defines CRB adr [31:20] of the agents */
229
230#define NETXEN_HW_CRB_HUB_AGT_ADR_MN \
231 ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MN_CRB_AGT_ADR)
232#define NETXEN_HW_CRB_HUB_AGT_ADR_PH \
233 ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_PH_CRB_AGT_ADR)
234#define NETXEN_HW_CRB_HUB_AGT_ADR_MS \
235 ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MS_CRB_AGT_ADR)
236
237#define NETXEN_HW_CRB_HUB_AGT_ADR_PS \
238 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_PS_CRB_AGT_ADR)
239#define NETXEN_HW_CRB_HUB_AGT_ADR_SS \
240 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SS_CRB_AGT_ADR)
241#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3 \
242 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX3_CRB_AGT_ADR)
243#define NETXEN_HW_CRB_HUB_AGT_ADR_QMS \
244 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_QMS_CRB_AGT_ADR)
245#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS0 \
246 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS0_CRB_AGT_ADR)
247#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS1 \
248 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS1_CRB_AGT_ADR)
249#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS2 \
250 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS2_CRB_AGT_ADR)
251#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS3 \
252 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS3_CRB_AGT_ADR)
253#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C0 \
254 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C0_CRB_AGT_ADR)
255#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C1 \
256 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C1_CRB_AGT_ADR)
257#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2 \
258 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX2_CRB_AGT_ADR)
259#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4 \
260 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX4_CRB_AGT_ADR)
261#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7 \
262 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX7_CRB_AGT_ADR)
263#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9 \
264 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX9_CRB_AGT_ADR)
265#define NETXEN_HW_CRB_HUB_AGT_ADR_SMB \
266 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SMB_CRB_AGT_ADR)
267
268#define NETXEN_HW_CRB_HUB_AGT_ADR_NIU \
269 ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_NIU_CRB_AGT_ADR)
270#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C0 \
271 ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C0_CRB_AGT_ADR)
272#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C1 \
273 ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C1_CRB_AGT_ADR)
274
275#define NETXEN_HW_CRB_HUB_AGT_ADR_SRE \
276 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SRE_CRB_AGT_ADR)
277#define NETXEN_HW_CRB_HUB_AGT_ADR_EG \
278 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_EG_CRB_AGT_ADR)
279#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0 \
280 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX0_CRB_AGT_ADR)
281#define NETXEN_HW_CRB_HUB_AGT_ADR_QMN \
282 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_QM_CRB_AGT_ADR)
283#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN0 \
284 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG0_CRB_AGT_ADR)
285#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN1 \
286 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG1_CRB_AGT_ADR)
287#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN2 \
288 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG2_CRB_AGT_ADR)
289#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN3 \
290 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG3_CRB_AGT_ADR)
291#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1 \
292 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX1_CRB_AGT_ADR)
293#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5 \
294 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX5_CRB_AGT_ADR)
295#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6 \
296 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX6_CRB_AGT_ADR)
297#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8 \
298 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX8_CRB_AGT_ADR)
299#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS0 \
300 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS0_CRB_AGT_ADR)
301#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS1 \
302 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS1_CRB_AGT_ADR)
303#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS2 \
304 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS2_CRB_AGT_ADR)
305#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS3 \
306 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS3_CRB_AGT_ADR)
307
308#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNI \
309 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNI_CRB_AGT_ADR)
310#define NETXEN_HW_CRB_HUB_AGT_ADR_PGND \
311 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGND_CRB_AGT_ADR)
312#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN0 \
313 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN0_CRB_AGT_ADR)
314#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN1 \
315 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN1_CRB_AGT_ADR)
316#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN2 \
317 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR)
318#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \
319 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR)
320#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \
321 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR)
322#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \
323 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR0_CRB_AGT_ADR)
324#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR1 \
325 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR1_CRB_AGT_ADR)
326#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR2 \
327 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR2_CRB_AGT_ADR)
328#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR3 \
329 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR3_CRB_AGT_ADR)
330
331#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSI \
332 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSI_CRB_AGT_ADR)
333#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSD \
334 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSD_CRB_AGT_ADR)
335#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS0 \
336 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS0_CRB_AGT_ADR)
337#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS1 \
338 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS1_CRB_AGT_ADR)
339#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS2 \
340 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS2_CRB_AGT_ADR)
341#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS3 \
342 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS3_CRB_AGT_ADR)
343#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSC \
344 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSC_CRB_AGT_ADR)
345
346#define NETXEN_HW_CRB_HUB_AGT_ADR_CAM \
347 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_NCM_CRB_AGT_ADR)
348#define NETXEN_HW_CRB_HUB_AGT_ADR_TIMR \
349 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_TMR_CRB_AGT_ADR)
350#define NETXEN_HW_CRB_HUB_AGT_ADR_XDMA \
351 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_XDMA_CRB_AGT_ADR)
352#define NETXEN_HW_CRB_HUB_AGT_ADR_SN \
353 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_SN_CRB_AGT_ADR)
354#define NETXEN_HW_CRB_HUB_AGT_ADR_I2Q \
355 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_I2Q_CRB_AGT_ADR)
356#define NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB \
357 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_ROMUSB_CRB_AGT_ADR)
358#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM0 \
359 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM0_CRB_AGT_ADR)
360#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM1 \
361 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM1_CRB_AGT_ADR)
362#define NETXEN_HW_CRB_HUB_AGT_ADR_LPC \
363 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_LPC_CRB_AGT_ADR)
364
365/*
366 * MAX_RCV_CTX : The number of receive contexts that are available on
367 * the phantom.
368 */
369#define MAX_RCV_CTX 1
370
371#define NETXEN_SRE_INT_STATUS (NETXEN_CRB_SRE + 0x00034)
372#define NETXEN_SRE_PBI_ACTIVE_STATUS (NETXEN_CRB_SRE + 0x01014)
373#define NETXEN_SRE_L1RE_CTL (NETXEN_CRB_SRE + 0x03000)
374#define NETXEN_SRE_L2RE_CTL (NETXEN_CRB_SRE + 0x05000)
375#define NETXEN_SRE_BUF_CTL (NETXEN_CRB_SRE + 0x01000)
376
377#define NETXEN_DMA_BASE(U) (NETXEN_CRB_PCIX_MD + 0x20000 + ((U)<<16))
378#define NETXEN_DMA_COMMAND(U) (NETXEN_DMA_BASE(U) + 0x00008)
379
380#define NETXEN_I2Q_CLR_PCI_HI (NETXEN_CRB_I2Q + 0x00034)
381
382#define PEG_NETWORK_BASE(N) (NETXEN_CRB_PEG_NET_0 + (((N)&3) << 20))
383#define CRB_REG_EX_PC 0x3c
384
385#define ROMUSB_GLB (NETXEN_CRB_ROMUSB + 0x00000)
386#define ROMUSB_ROM (NETXEN_CRB_ROMUSB + 0x10000)
387
388#define NETXEN_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
389#define NETXEN_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
390#define NETXEN_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
391#define NETXEN_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
392#define NETXEN_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
393#define NETXEN_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
394#define NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
395
396#define NETXEN_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
397
398#define NETXEN_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
399#define NETXEN_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
400#define NETXEN_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
401#define NETXEN_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
402#define NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
403#define NETXEN_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
404
405/* Lock IDs for ROM lock */
406#define ROM_LOCK_DRIVER 0x0d417340
407
408/******************************************************************************
409*
410* Definitions specific to M25P flash
411*
412*******************************************************************************
413* Instructions
414*/
415#define M25P_INSTR_WREN 0x06
416#define M25P_INSTR_WRDI 0x04
417#define M25P_INSTR_RDID 0x9f
418#define M25P_INSTR_RDSR 0x05
419#define M25P_INSTR_WRSR 0x01
420#define M25P_INSTR_READ 0x03
421#define M25P_INSTR_FAST_READ 0x0b
422#define M25P_INSTR_PP 0x02
423#define M25P_INSTR_SE 0xd8
424#define M25P_INSTR_BE 0xc7
425#define M25P_INSTR_DP 0xb9
426#define M25P_INSTR_RES 0xab
427
428/* all are 1MB windows */
429
430#define NETXEN_PCI_CRB_WINDOWSIZE 0x00100000
431#define NETXEN_PCI_CRB_WINDOW(A) \
432 (NETXEN_PCI_CRBSPACE + (A)*NETXEN_PCI_CRB_WINDOWSIZE)
433
434#define NETXEN_CRB_NIU NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_NIU)
435#define NETXEN_CRB_SRE NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SRE)
436#define NETXEN_CRB_ROMUSB \
437 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB)
438#define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q)
439#define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64)
440
441#define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH)
442#define NETXEN_CRB_PCIX_HOST2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH2)
443#define NETXEN_CRB_PEG_NET_0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN0)
444#define NETXEN_CRB_PEG_NET_1 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN1)
445#define NETXEN_CRB_PEG_NET_2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN2)
446#define NETXEN_CRB_PEG_NET_3 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN3)
447#define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND)
448#define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI)
449#define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN)
450
451#define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS)
452#define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD
453
454#define ISR_INT_VECTOR (NETXEN_PCIX_PS_REG(PCIX_INT_VECTOR))
455#define ISR_INT_MASK (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
456#define ISR_INT_MASK_SLOW (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
457#define ISR_INT_TARGET_STATUS (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS))
458#define ISR_INT_TARGET_MASK (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK))
459
460#define NETXEN_PCI_MAPSIZE 128
461#define NETXEN_PCI_DDR_NET (0x00000000UL)
462#define NETXEN_PCI_QDR_NET (0x04000000UL)
463#define NETXEN_PCI_DIRECT_CRB (0x04400000UL)
464#define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL)
465#define NETXEN_PCI_OCM0 (0x05000000UL)
466#define NETXEN_PCI_OCM0_MAX (0x050fffffUL)
467#define NETXEN_PCI_OCM1 (0x05100000UL)
468#define NETXEN_PCI_OCM1_MAX (0x051fffffUL)
469#define NETXEN_PCI_CRBSPACE (0x06000000UL)
470
471#define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM)
472
473#define NETXEN_ADDR_DDR_NET (0x0000000000000000ULL)
474#define NETXEN_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
475#define NETXEN_ADDR_OCM0 (0x0000000200000000ULL)
476#define NETXEN_ADDR_OCM0_MAX (0x00000002000fffffULL)
477#define NETXEN_ADDR_OCM1 (0x0000000200400000ULL)
478#define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL)
479#define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL)
480#define NETXEN_ADDR_QDR_NET_MAX (0x00000003003fffffULL)
481
482 /* 200ms delay in each loop */
483#define NETXEN_NIU_PHY_WAITLEN 200000
484 /* 10 seconds before we give up */
485#define NETXEN_NIU_PHY_WAITMAX 50
486#define NETXEN_NIU_MAX_GBE_PORTS 4
487
488#define NETXEN_NIU_MODE (NETXEN_CRB_NIU + 0x00000)
489
490#define NETXEN_NIU_XG_SINGLE_TERM (NETXEN_CRB_NIU + 0x00004)
491#define NETXEN_NIU_XG_DRIVE_HI (NETXEN_CRB_NIU + 0x00008)
492#define NETXEN_NIU_XG_DRIVE_LO (NETXEN_CRB_NIU + 0x0000c)
493#define NETXEN_NIU_XG_DTX (NETXEN_CRB_NIU + 0x00010)
494#define NETXEN_NIU_XG_DEQ (NETXEN_CRB_NIU + 0x00014)
495#define NETXEN_NIU_XG_WORD_ALIGN (NETXEN_CRB_NIU + 0x00018)
496#define NETXEN_NIU_XG_RESET (NETXEN_CRB_NIU + 0x0001c)
497#define NETXEN_NIU_XG_POWER_DOWN (NETXEN_CRB_NIU + 0x00020)
498#define NETXEN_NIU_XG_RESET_PLL (NETXEN_CRB_NIU + 0x00024)
499#define NETXEN_NIU_XG_SERDES_LOOPBACK (NETXEN_CRB_NIU + 0x00028)
500#define NETXEN_NIU_XG_DO_BYTE_ALIGN (NETXEN_CRB_NIU + 0x0002c)
501#define NETXEN_NIU_XG_TX_ENABLE (NETXEN_CRB_NIU + 0x00030)
502#define NETXEN_NIU_XG_RX_ENABLE (NETXEN_CRB_NIU + 0x00034)
503#define NETXEN_NIU_XG_STATUS (NETXEN_CRB_NIU + 0x00038)
504#define NETXEN_NIU_XG_PAUSE_THRESHOLD (NETXEN_CRB_NIU + 0x0003c)
505#define NETXEN_NIU_INT_MASK (NETXEN_CRB_NIU + 0x00040)
506#define NETXEN_NIU_ACTIVE_INT (NETXEN_CRB_NIU + 0x00044)
507#define NETXEN_NIU_MASKABLE_INT (NETXEN_CRB_NIU + 0x00048)
508
509#define NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER (NETXEN_CRB_NIU + 0x0004c)
510
511#define NETXEN_NIU_GB_SERDES_RESET (NETXEN_CRB_NIU + 0x00050)
512#define NETXEN_NIU_GB0_GMII_MODE (NETXEN_CRB_NIU + 0x00054)
513#define NETXEN_NIU_GB0_MII_MODE (NETXEN_CRB_NIU + 0x00058)
514#define NETXEN_NIU_GB1_GMII_MODE (NETXEN_CRB_NIU + 0x0005c)
515#define NETXEN_NIU_GB1_MII_MODE (NETXEN_CRB_NIU + 0x00060)
516#define NETXEN_NIU_GB2_GMII_MODE (NETXEN_CRB_NIU + 0x00064)
517#define NETXEN_NIU_GB2_MII_MODE (NETXEN_CRB_NIU + 0x00068)
518#define NETXEN_NIU_GB3_GMII_MODE (NETXEN_CRB_NIU + 0x0006c)
519#define NETXEN_NIU_GB3_MII_MODE (NETXEN_CRB_NIU + 0x00070)
520#define NETXEN_NIU_REMOTE_LOOPBACK (NETXEN_CRB_NIU + 0x00074)
521#define NETXEN_NIU_GB0_HALF_DUPLEX (NETXEN_CRB_NIU + 0x00078)
522#define NETXEN_NIU_GB1_HALF_DUPLEX (NETXEN_CRB_NIU + 0x0007c)
523#define NETXEN_NIU_RESET_SYS_FIFOS (NETXEN_CRB_NIU + 0x00088)
524#define NETXEN_NIU_GB_CRC_DROP (NETXEN_CRB_NIU + 0x0008c)
525#define NETXEN_NIU_GB_DROP_WRONGADDR (NETXEN_CRB_NIU + 0x00090)
526#define NETXEN_NIU_TEST_MUX_CTL (NETXEN_CRB_NIU + 0x00094)
527#define NETXEN_NIU_XG_PAUSE_CTL (NETXEN_CRB_NIU + 0x00098)
528#define NETXEN_NIU_XG_PAUSE_LEVEL (NETXEN_CRB_NIU + 0x000dc)
529#define NETXEN_NIU_XG_SEL (NETXEN_CRB_NIU + 0x00128)
530
531#define NETXEN_NIU_FULL_LEVEL_XG (NETXEN_CRB_NIU + 0x00450)
532
533#define NETXEN_NIU_XG1_RESET (NETXEN_CRB_NIU + 0x0011c)
534#define NETXEN_NIU_XG1_POWER_DOWN (NETXEN_CRB_NIU + 0x00120)
535#define NETXEN_NIU_XG1_RESET_PLL (NETXEN_CRB_NIU + 0x00124)
536
537#define NETXEN_MAC_ADDR_CNTL_REG (NETXEN_CRB_NIU + 0x1000)
538
539#define NETXEN_MULTICAST_ADDR_HI_0 (NETXEN_CRB_NIU + 0x1010)
540#define NETXEN_MULTICAST_ADDR_HI_1 (NETXEN_CRB_NIU + 0x1014)
541#define NETXEN_MULTICAST_ADDR_HI_2 (NETXEN_CRB_NIU + 0x1018)
542#define NETXEN_MULTICAST_ADDR_HI_3 (NETXEN_CRB_NIU + 0x101c)
543
544#define NETXEN_NIU_GB_MAC_CONFIG_0(I) \
545 (NETXEN_CRB_NIU + 0x30000 + (I)*0x10000)
546#define NETXEN_NIU_GB_MAC_CONFIG_1(I) \
547 (NETXEN_CRB_NIU + 0x30004 + (I)*0x10000)
548#define NETXEN_NIU_GB_MAC_IPG_IFG(I) \
549 (NETXEN_CRB_NIU + 0x30008 + (I)*0x10000)
550#define NETXEN_NIU_GB_HALF_DUPLEX_CTRL(I) \
551 (NETXEN_CRB_NIU + 0x3000c + (I)*0x10000)
552#define NETXEN_NIU_GB_MAX_FRAME_SIZE(I) \
553 (NETXEN_CRB_NIU + 0x30010 + (I)*0x10000)
554#define NETXEN_NIU_GB_TEST_REG(I) \
555 (NETXEN_CRB_NIU + 0x3001c + (I)*0x10000)
556#define NETXEN_NIU_GB_MII_MGMT_CONFIG(I) \
557 (NETXEN_CRB_NIU + 0x30020 + (I)*0x10000)
558#define NETXEN_NIU_GB_MII_MGMT_COMMAND(I) \
559 (NETXEN_CRB_NIU + 0x30024 + (I)*0x10000)
560#define NETXEN_NIU_GB_MII_MGMT_ADDR(I) \
561 (NETXEN_CRB_NIU + 0x30028 + (I)*0x10000)
562#define NETXEN_NIU_GB_MII_MGMT_CTRL(I) \
563 (NETXEN_CRB_NIU + 0x3002c + (I)*0x10000)
564#define NETXEN_NIU_GB_MII_MGMT_STATUS(I) \
565 (NETXEN_CRB_NIU + 0x30030 + (I)*0x10000)
566#define NETXEN_NIU_GB_MII_MGMT_INDICATE(I) \
567 (NETXEN_CRB_NIU + 0x30034 + (I)*0x10000)
568#define NETXEN_NIU_GB_INTERFACE_CTRL(I) \
569 (NETXEN_CRB_NIU + 0x30038 + (I)*0x10000)
570#define NETXEN_NIU_GB_INTERFACE_STATUS(I) \
571 (NETXEN_CRB_NIU + 0x3003c + (I)*0x10000)
572#define NETXEN_NIU_GB_STATION_ADDR_0(I) \
573 (NETXEN_CRB_NIU + 0x30040 + (I)*0x10000)
574#define NETXEN_NIU_GB_STATION_ADDR_1(I) \
575 (NETXEN_CRB_NIU + 0x30044 + (I)*0x10000)
576
577#define NETXEN_NIU_XGE_CONFIG_0 (NETXEN_CRB_NIU + 0x70000)
578#define NETXEN_NIU_XGE_CONFIG_1 (NETXEN_CRB_NIU + 0x70004)
579#define NETXEN_NIU_XGE_IPG (NETXEN_CRB_NIU + 0x70008)
580#define NETXEN_NIU_XGE_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x7000c)
581#define NETXEN_NIU_XGE_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x70010)
582#define NETXEN_NIU_XGE_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x70014)
583#define NETXEN_NIU_XGE_STATUS (NETXEN_CRB_NIU + 0x70018)
584#define NETXEN_NIU_XGE_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x7001c)
585#define NETXEN_NIU_XGE_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x70020)
586#define NETXEN_NIU_XGE_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x70024)
587#define NETXEN_NIU_XGE_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x70028)
588#define NETXEN_NIU_XGE_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x7002c)
589#define NETXEN_NIU_XGE_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x70030)
590#define NETXEN_NIU_XGE_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x70034)
591#define NETXEN_NIU_XGE_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x70038)
592#define NETXEN_NIU_XGE_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x7003c)
593#define NETXEN_NIU_XGE_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x70040)
594#define NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70044)
595#define NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70048)
596#define NETXEN_NIU_XGE_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x7004c)
597#define NETXEN_NIU_XGE_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x70050)
598#define NETXEN_NIU_XGE_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x70054)
599#define NETXEN_NIU_XGE_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x70058)
600#define NETXEN_NIU_XG1_CONFIG_0 (NETXEN_CRB_NIU + 0x80000)
601#define NETXEN_NIU_XG1_CONFIG_1 (NETXEN_CRB_NIU + 0x80004)
602#define NETXEN_NIU_XG1_IPG (NETXEN_CRB_NIU + 0x80008)
603#define NETXEN_NIU_XG1_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x8000c)
604#define NETXEN_NIU_XG1_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x80010)
605#define NETXEN_NIU_XG1_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x80014)
606#define NETXEN_NIU_XG1_STATUS (NETXEN_CRB_NIU + 0x80018)
607#define NETXEN_NIU_XG1_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x8001c)
608#define NETXEN_NIU_XG1_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x80020)
609#define NETXEN_NIU_XG1_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x80024)
610#define NETXEN_NIU_XG1_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x80028)
611#define NETXEN_NIU_XG1_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x8002c)
612#define NETXEN_NIU_XG1_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x80030)
613#define NETXEN_NIU_XG1_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x80034)
614#define NETXEN_NIU_XG1_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x80038)
615#define NETXEN_NIU_XG1_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x8003c)
616#define NETXEN_NIU_XG1_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x80040)
617#define NETXEN_NIU_XG1_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80044)
618#define NETXEN_NIU_XG1_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80048)
619#define NETXEN_NIU_XG1_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x8004c)
620#define NETXEN_NIU_XG1_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x80050)
621#define NETXEN_NIU_XG1_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x80054)
622#define NETXEN_NIU_XG1_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x80058)
623
624/* XG Link status */
625#define XG_LINK_UP 0x10
626#define XG_LINK_DOWN 0x20
627
628#define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000)
629#define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg))
630#define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150))
631#define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154))
632#define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158))
633#define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100))
634
635#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120))
636
637/* Lock IDs for PHY lock */
638#define PHY_LOCK_DRIVER 0x44524956
639
640/* Used for PS PCI Memory access */
641#define PCIX_PS_OP_ADDR_LO (0x10000)
642/* via CRB (PS side only) */
643#define PCIX_PS_OP_ADDR_HI (0x10004)
644
645#define PCIX_INT_VECTOR (0x10100)
646#define PCIX_INT_MASK (0x10104)
647
648#define PCIX_MN_WINDOW (0x10200)
649#define PCIX_MS_WINDOW (0x10204)
650#define PCIX_SN_WINDOW (0x10208)
651#define PCIX_CRB_WINDOW (0x10210)
652
653#define PCIX_TARGET_STATUS (0x10118)
654#define PCIX_TARGET_MASK (0x10128)
655
656#define PCIX_MSI_F0 (0x13000)
657
658#define PCIX_PS_MEM_SPACE (0x90000)
659
660#define NETXEN_PCIX_PH_REG(reg) (NETXEN_CRB_PCIE + (reg))
661#define NETXEN_PCIX_PS_REG(reg) (NETXEN_CRB_PCIX_MD + (reg))
662
663#define NETXEN_PCIE_REG(reg) (NETXEN_CRB_PCIE + (reg))
664
665#define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
666
667#define PCIE_DCR 0x00d8
668
669#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
670#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
671#define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */
672#define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */
673
674#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
675
676#define PCIE_MAX_MASTER_SPLIT (0x14048)
677
678#endif /* __NETXEN_NIC_HDR_H_ */
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
new file mode 100644
index 000000000000..105c24f0ad4c
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -0,0 +1,1010 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34#include "netxen_nic.h"
35#include "netxen_nic_hw.h"
36#include "netxen_nic_phan_reg.h"
37
38/* PCI Windowing for DDR regions. */
39
40#define ADDR_IN_RANGE(addr, low, high) \
41 (((addr) <= (high)) && ((addr) >= (low)))
42
43#define NETXEN_FLASH_BASE (BOOTLD_START)
44#define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
45#define NETXEN_MAX_MTU 8000
46#define NETXEN_MIN_MTU 64
47#define NETXEN_ETH_FCS_SIZE 4
48#define NETXEN_ENET_HEADER_SIZE 14
49#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
50#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
51#define NETXEN_NIU_HDRSIZE (0x1 << 6)
52#define NETXEN_NIU_TLRSIZE (0x1 << 5)
53
54#define lower32(x) ((u32)((x) & 0xffffffff))
55#define upper32(x) \
56 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
57
58#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
59#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
60#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
61#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
62
63#define NETXEN_NIC_WINDOW_MARGIN 0x100000
64
65unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
66 unsigned long long addr);
67void netxen_free_hw_resources(struct netxen_adapter *adapter);
68
69int netxen_nic_set_mac(struct net_device *netdev, void *p)
70{
71 struct netxen_port *port = netdev_priv(netdev);
72 struct netxen_adapter *adapter = port->adapter;
73 struct sockaddr *addr = p;
74
75 if (netif_running(netdev))
76 return -EBUSY;
77
78 if (!is_valid_ether_addr(addr->sa_data))
79 return -EADDRNOTAVAIL;
80
81 DPRINTK(INFO, "valid ether addr\n");
82 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
83
84 if (adapter->ops->macaddr_set)
85 adapter->ops->macaddr_set(port, addr->sa_data);
86
87 return 0;
88}
89
90/*
91 * netxen_nic_set_multi - Multicast
92 */
93void netxen_nic_set_multi(struct net_device *netdev)
94{
95 struct netxen_port *port = netdev_priv(netdev);
96 struct netxen_adapter *adapter = port->adapter;
97 struct dev_mc_list *mc_ptr;
98 __le32 netxen_mac_addr_cntl_data = 0;
99
100 mc_ptr = netdev->mc_list;
101 if (netdev->flags & IFF_PROMISC) {
102 if (adapter->ops->set_promisc)
103 adapter->ops->set_promisc(adapter,
104 port->portnum,
105 NETXEN_NIU_PROMISC_MODE);
106 } else {
107 if (adapter->ops->unset_promisc &&
108 adapter->ahw.boardcfg.board_type
109 != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
110 adapter->ops->unset_promisc(adapter,
111 port->portnum,
112 NETXEN_NIU_NON_PROMISC_MODE);
113 }
114 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
115 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
116 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
117 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
118 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
119 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
120 netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
121 netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
122 netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
123 netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
124 } else {
125 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
126 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
127 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
128 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
129 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
130 }
131 writel(netxen_mac_addr_cntl_data,
132 NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
133 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
134 writel(netxen_mac_addr_cntl_data,
135 NETXEN_CRB_NORMALIZE(adapter,
136 NETXEN_MULTICAST_ADDR_HI_0));
137 } else {
138 writel(netxen_mac_addr_cntl_data,
139 NETXEN_CRB_NORMALIZE(adapter,
140 NETXEN_MULTICAST_ADDR_HI_1));
141 }
142 netxen_mac_addr_cntl_data = 0;
143 writel(netxen_mac_addr_cntl_data,
144 NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
145}
146
147/*
148 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
149 * @returns 0 on success, negative on failure
150 */
151int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
152{
153 struct netxen_port *port = netdev_priv(netdev);
154 struct netxen_adapter *adapter = port->adapter;
155 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
156
157 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
158 printk(KERN_ERR "%s: %s %d is not supported.\n",
159 netxen_nic_driver_name, netdev->name, mtu);
160 return -EINVAL;
161 }
162
163 if (adapter->ops->set_mtu)
164 adapter->ops->set_mtu(port, mtu);
165 netdev->mtu = mtu;
166
167 return 0;
168}
169
170/*
171 * check if the firmware has been downloaded and ready to run and
172 * setup the address for the descriptors in the adapter
173 */
174int netxen_nic_hw_resources(struct netxen_adapter *adapter)
175{
176 struct netxen_hardware_context *hw = &adapter->ahw;
177 u32 state = 0;
178 void *addr;
179 void *pause_addr;
180 int loops = 0, err = 0;
181 int ctx, ring;
182 u32 card_cmdring = 0;
183 struct netxen_rcv_desc_crb *rcv_desc_crb = NULL;
184 struct netxen_recv_context *recv_ctx;
185 struct netxen_rcv_desc_ctx *rcv_desc;
186
187 DPRINTK(INFO, "crb_base: %lx %lx", NETXEN_PCI_CRBSPACE,
188 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
189 DPRINTK(INFO, "cam base: %lx %lx", NETXEN_CRB_CAM,
190 pci_base_offset(adapter, NETXEN_CRB_CAM));
191 DPRINTK(INFO, "cam RAM: %lx %lx", NETXEN_CAM_RAM_BASE,
192 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
193 DPRINTK(INFO, "NIC base:%lx %lx\n", NIC_CRB_BASE_PORT1,
194 pci_base_offset(adapter, NIC_CRB_BASE_PORT1));
195
196 /* Window 1 call */
197 card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
198
199 DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
200 card_cmdring);
201
202 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
203 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
204 loops = 0;
205 state = 0;
206 /* Window 1 call */
207 state = readl(NETXEN_CRB_NORMALIZE(adapter,
208 recv_crb_registers[ctx].
209 crb_rcvpeg_state));
210 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
211 udelay(100);
212 /* Window 1 call */
213 state = readl(NETXEN_CRB_NORMALIZE(adapter,
214 recv_crb_registers
215 [ctx].
216 crb_rcvpeg_state));
217 loops++;
218 }
219 if (loops >= 20) {
220 printk(KERN_ERR "Rcv Peg initialization not complete:"
221 "%x.\n", state);
222 err = -EIO;
223 return err;
224 }
225 }
226 DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
227
228 addr = netxen_alloc(adapter->ahw.pdev,
229 sizeof(struct cmd_desc_type0) *
230 adapter->max_tx_desc_count,
231 &hw->cmd_desc_phys_addr, &hw->cmd_desc_pdev);
232
233 if (addr == NULL) {
234 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
235 return -ENOMEM;
236 }
237
238 pause_addr = netxen_alloc(adapter->ahw.pdev, 512,
239 (dma_addr_t *) & hw->pause_physaddr,
240 &hw->pause_pdev);
241 if (pause_addr == NULL) {
242 DPRINTK(1, ERR, "bad return from pci_alloc_consistent\n");
243 return -ENOMEM;
244 }
245
246 hw->pauseaddr = (char *)pause_addr;
247 {
248 u64 *ptr = (u64 *) pause_addr;
249 *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
250 *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
251 *ptr++ = NETXEN_NIC_UNIT_PAUSE_ADDR;
252 *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
253 *ptr++ = NETXEN_NIC_EPG_PAUSE_ADDR1;
254 *ptr++ = NETXEN_NIC_EPG_PAUSE_ADDR2;
255 }
256
257 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
258
259 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
260 recv_ctx = &adapter->recv_ctx[ctx];
261
262 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
263 rcv_desc = &recv_ctx->rcv_desc[ring];
264 addr = netxen_alloc(adapter->ahw.pdev,
265 RCV_DESC_RINGSIZE,
266 &rcv_desc->phys_addr,
267 &rcv_desc->phys_pdev);
268 if (addr == NULL) {
269 DPRINTK(ERR, "bad return from "
270 "pci_alloc_consistent\n");
271 netxen_free_hw_resources(adapter);
272 err = -ENOMEM;
273 return err;
274 }
275 rcv_desc->desc_head = (struct rcv_desc *)addr;
276 }
277
278 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
279 &recv_ctx->rcv_status_desc_phys_addr,
280 &recv_ctx->rcv_status_desc_pdev);
281 if (addr == NULL) {
282 DPRINTK(ERR, "bad return from"
283 " pci_alloc_consistent\n");
284 netxen_free_hw_resources(adapter);
285 err = -ENOMEM;
286 return err;
287 }
288 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
289 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
290 rcv_desc = &recv_ctx->rcv_desc[ring];
291 rcv_desc_crb =
292 &recv_crb_registers[ctx].rcv_desc_crb[ring];
293 DPRINTK(INFO, "ring #%d crb global ring reg 0x%x\n",
294 ring, rcv_desc_crb->crb_globalrcv_ring);
295 /* Window = 1 */
296 writel(lower32(rcv_desc->phys_addr),
297 NETXEN_CRB_NORMALIZE(adapter,
298 rcv_desc_crb->
299 crb_globalrcv_ring));
300 DPRINTK(INFO, "GLOBAL_RCV_RING ctx %d, addr 0x%x"
301 " val 0x%llx,"
302 " virt %p\n", ctx,
303 rcv_desc_crb->crb_globalrcv_ring,
304 (unsigned long long)rcv_desc->phys_addr,
305 +rcv_desc->desc_head);
306 }
307
308 /* Window = 1 */
309 writel(lower32(recv_ctx->rcv_status_desc_phys_addr),
310 NETXEN_CRB_NORMALIZE(adapter,
311 recv_crb_registers[ctx].
312 crb_rcvstatus_ring));
313 DPRINTK(INFO, "RCVSTATUS_RING, ctx %d, addr 0x%x,"
314 " val 0x%x,virt%p\n",
315 ctx,
316 recv_crb_registers[ctx].crb_rcvstatus_ring,
317 (unsigned long long)recv_ctx->rcv_status_desc_phys_addr,
318 recv_ctx->rcv_status_desc_head);
319 }
320 /* Window = 1 */
321 writel(lower32(hw->pause_physaddr),
322 NETXEN_CRB_NORMALIZE(adapter, CRB_PAUSE_ADDR_LO));
323 writel(upper32(hw->pause_physaddr),
324 NETXEN_CRB_NORMALIZE(adapter, CRB_PAUSE_ADDR_HI));
325
326 writel(lower32(hw->cmd_desc_phys_addr),
327 NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
328 writel(upper32(hw->cmd_desc_phys_addr),
329 NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_HI));
330 return err;
331}
332
333void netxen_free_hw_resources(struct netxen_adapter *adapter)
334{
335 struct netxen_recv_context *recv_ctx;
336 struct netxen_rcv_desc_ctx *rcv_desc;
337 int ctx, ring;
338
339 if (adapter->ahw.cmd_desc_head != NULL) {
340 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
341 sizeof(struct cmd_desc_type0) *
342 adapter->max_tx_desc_count,
343 adapter->ahw.cmd_desc_head,
344 adapter->ahw.cmd_desc_phys_addr);
345 adapter->ahw.cmd_desc_head = NULL;
346 }
347 if (adapter->ahw.pauseaddr != NULL) {
348 pci_free_consistent(adapter->ahw.pause_pdev, 512,
349 adapter->ahw.pauseaddr,
350 adapter->ahw.pause_physaddr);
351 adapter->ahw.pauseaddr = NULL;
352 }
353
354 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
355 recv_ctx = &adapter->recv_ctx[ctx];
356 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
357 rcv_desc = &recv_ctx->rcv_desc[ring];
358
359 if (rcv_desc->desc_head != NULL) {
360 pci_free_consistent(rcv_desc->phys_pdev,
361 RCV_DESC_RINGSIZE,
362 rcv_desc->desc_head,
363 rcv_desc->phys_addr);
364 rcv_desc->desc_head = NULL;
365 }
366 }
367
368 if (recv_ctx->rcv_status_desc_head != NULL) {
369 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
370 STATUS_DESC_RINGSIZE,
371 recv_ctx->rcv_status_desc_head,
372 recv_ctx->
373 rcv_status_desc_phys_addr);
374 recv_ctx->rcv_status_desc_head = NULL;
375 }
376 }
377}
378
379void netxen_tso_check(struct netxen_adapter *adapter,
380 struct cmd_desc_type0 *desc, struct sk_buff *skb)
381{
382 if (desc->mss) {
383 desc->total_hdr_length = sizeof(struct ethhdr) +
384 ((skb->nh.iph)->ihl * sizeof(u32)) +
385 ((skb->h.th)->doff * sizeof(u32));
386 desc->opcode = TX_TCP_LSO;
387 } else if (skb->ip_summed == CHECKSUM_COMPLETE) {
388 if (skb->nh.iph->protocol == IPPROTO_TCP) {
389 desc->opcode = TX_TCP_PKT;
390 } else if (skb->nh.iph->protocol == IPPROTO_UDP) {
391 desc->opcode = TX_UDP_PKT;
392 } else {
393 return;
394 }
395 }
396 adapter->stats.xmitcsummed++;
397 CMD_DESC_TCP_HDR_OFFSET_WRT(desc, skb->h.raw - skb->data);
398 desc->length_tcp_hdr = cpu_to_le32(desc->length_tcp_hdr);
399 desc->ip_hdr_offset = skb->nh.raw - skb->data;
400}
401
402int netxen_is_flash_supported(struct netxen_adapter *adapter)
403{
404 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
405 int addr, val01, val02, i, j;
406
407 /* if the flash size less than 4Mb, make huge war cry and die */
408 for (j = 1; j < 4; j++) {
409 addr = j * NETXEN_NIC_WINDOW_MARGIN;
410 for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
411 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
412 && netxen_rom_fast_read(adapter, (addr + locs[i]),
413 &val02) == 0) {
414 if (val01 == val02)
415 return -1;
416 } else
417 return -1;
418 }
419 }
420
421 return 0;
422}
423
424static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
425 int size, u32 * buf)
426{
427 int i, addr;
428 u32 *ptr32;
429
430 addr = base;
431 ptr32 = buf;
432 for (i = 0; i < size / sizeof(u32); i++) {
433 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
434 return -1;
435 ptr32++;
436 addr += sizeof(u32);
437 }
438 if ((char *)buf + size > (char *)ptr32) {
439 u32 local;
440
441 if (netxen_rom_fast_read(adapter, addr, &local) == -1)
442 return -1;
443 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
444 }
445
446 return 0;
447}
448
449int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
450{
451 u32 *pmac = (u32 *) & mac[0];
452
453 if (netxen_get_flash_block(adapter,
454 USER_START +
455 offsetof(struct netxen_new_user_info,
456 mac_addr),
457 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
458 return -1;
459 }
460 if (*mac == ~0ULL) {
461 if (netxen_get_flash_block(adapter,
462 USER_START_OLD +
463 offsetof(struct netxen_user_old_info,
464 mac_addr),
465 FLASH_NUM_PORTS * sizeof(u64),
466 pmac) == -1)
467 return -1;
468 if (*mac == ~0ULL)
469 return -1;
470 }
471 return 0;
472}
473
474/*
475 * Changes the CRB window to the specified window.
476 */
477void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
478{
479 void __iomem *offset;
480 u32 tmp;
481 int count = 0;
482
483 if (adapter->curr_window == wndw)
484 return;
485
486 /*
487 * Move the CRB window.
488 * We need to write to the "direct access" region of PCI
489 * to avoid a race condition where the window register has
490 * not been successfully written across CRB before the target
491 * register address is received by PCI. The direct region bypasses
492 * the CRB bus.
493 */
494 offset =
495 PCI_OFFSET_SECOND_RANGE(adapter,
496 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
497
498 if (wndw & 0x1)
499 wndw = NETXEN_WINDOW_ONE;
500
501 writel(wndw, offset);
502
503 /* MUST make sure window is set before we forge on... */
504 while ((tmp = readl(offset)) != wndw) {
505 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
506 "registered properly: 0x%08x.\n",
507 netxen_nic_driver_name, __FUNCTION__, tmp);
508 mdelay(1);
509 if (count >= 10)
510 break;
511 count++;
512 }
513
514 adapter->curr_window = wndw;
515}
516
517void netxen_load_firmware(struct netxen_adapter *adapter)
518{
519 int i;
520 long data, size = 0;
521 long flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
522 u64 off;
523 void __iomem *addr;
524
525 size = NETXEN_FIRMWARE_LEN;
526 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
527
528 for (i = 0; i < size; i++) {
529 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
530 DPRINTK(ERR,
531 "Error in netxen_rom_fast_read(). Will skip"
532 "loading flash image\n");
533 return;
534 }
535 off = netxen_nic_pci_set_window(adapter, memaddr);
536 addr = pci_base_offset(adapter, off);
537 writel(data, addr);
538 flashaddr += 4;
539 memaddr += 4;
540 }
541 udelay(100);
542 /* make sure Casper is powered on */
543 writel(0x3fff,
544 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
545 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
546
547 udelay(100);
548}
549
550int
551netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
552 int len)
553{
554 void __iomem *addr;
555
556 if (ADDR_IN_WINDOW1(off)) {
557 addr = NETXEN_CRB_NORMALIZE(adapter, off);
558 } else { /* Window 0 */
559 addr = pci_base_offset(adapter, off);
560 netxen_nic_pci_change_crbwindow(adapter, 0);
561 }
562
563 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
564 " data %llx len %d\n",
565 pci_base(adapter, off), off, addr,
566 *(unsigned long long *)data, len);
567 if (!addr) {
568 netxen_nic_pci_change_crbwindow(adapter, 1);
569 return 1;
570 }
571
572 switch (len) {
573 case 1:
574 writeb(*(u8 *) data, addr);
575 break;
576 case 2:
577 writew(*(u16 *) data, addr);
578 break;
579 case 4:
580 writel(*(u32 *) data, addr);
581 break;
582 case 8:
583 writeq(*(u64 *) data, addr);
584 break;
585 default:
586 DPRINTK(INFO,
587 "writing data %lx to offset %llx, num words=%d\n",
588 *(unsigned long *)data, off, (len >> 3));
589
590 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
591 (len >> 3));
592 break;
593 }
594 if (!ADDR_IN_WINDOW1(off))
595 netxen_nic_pci_change_crbwindow(adapter, 1);
596
597 return 0;
598}
599
600int
601netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
602 int len)
603{
604 void __iomem *addr;
605
606 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
607 addr = NETXEN_CRB_NORMALIZE(adapter, off);
608 } else { /* Window 0 */
609 addr = pci_base_offset(adapter, off);
610 netxen_nic_pci_change_crbwindow(adapter, 0);
611 }
612
613 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
614 pci_base(adapter, off), off, addr);
615 if (!addr) {
616 netxen_nic_pci_change_crbwindow(adapter, 1);
617 return 1;
618 }
619 switch (len) {
620 case 1:
621 *(u8 *) data = readb(addr);
622 break;
623 case 2:
624 *(u16 *) data = readw(addr);
625 break;
626 case 4:
627 *(u32 *) data = readl(addr);
628 break;
629 case 8:
630 *(u64 *) data = readq(addr);
631 break;
632 default:
633 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
634 (len >> 3));
635 break;
636 }
637 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
638
639 if (!ADDR_IN_WINDOW1(off))
640 netxen_nic_pci_change_crbwindow(adapter, 1);
641
642 return 0;
643}
644
645void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
646{ /* Only for window 1 */
647 void __iomem *addr;
648
649 addr = NETXEN_CRB_NORMALIZE(adapter, off);
650 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
651 pci_base(adapter, off), off, addr);
652 writel(val, addr);
653
654}
655
656int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
657{ /* Only for window 1 */
658 void __iomem *addr;
659 int val;
660
661 addr = NETXEN_CRB_NORMALIZE(adapter, off);
662 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
663 adapter->ahw.pci_base, off, addr);
664 val = readl(addr);
665 writel(val, addr);
666
667 return val;
668}
669
670/* Change the window to 0, write and change back to window 1. */
671void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
672{
673 void __iomem *addr;
674
675 netxen_nic_pci_change_crbwindow(adapter, 0);
676 addr = pci_base_offset(adapter, index);
677 writel(value, addr);
678 netxen_nic_pci_change_crbwindow(adapter, 1);
679}
680
681/* Change the window to 0, read and change back to window 1. */
682void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
683{
684 void __iomem *addr;
685
686 addr = pci_base_offset(adapter, index);
687
688 netxen_nic_pci_change_crbwindow(adapter, 0);
689 *value = readl(addr);
690 netxen_nic_pci_change_crbwindow(adapter, 1);
691}
692
693int netxen_pci_set_window_warning_count = 0;
694
695unsigned long
696netxen_nic_pci_set_window(struct netxen_adapter *adapter,
697 unsigned long long addr)
698{
699 static int ddr_mn_window = -1;
700 static int qdr_sn_window = -1;
701 int window;
702
703 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
704 /* DDR network side */
705 addr -= NETXEN_ADDR_DDR_NET;
706 window = (addr >> 25) & 0x3ff;
707 if (ddr_mn_window != window) {
708 ddr_mn_window = window;
709 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
710 NETXEN_PCIX_PH_REG
711 (PCIX_MN_WINDOW)));
712 /* MUST make sure window is set before we forge on... */
713 readl(PCI_OFFSET_SECOND_RANGE(adapter,
714 NETXEN_PCIX_PH_REG
715 (PCIX_MN_WINDOW)));
716 }
717 addr -= (window * NETXEN_WINDOW_ONE);
718 addr += NETXEN_PCI_DDR_NET;
719 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
720 addr -= NETXEN_ADDR_OCM0;
721 addr += NETXEN_PCI_OCM0;
722 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
723 addr -= NETXEN_ADDR_OCM1;
724 addr += NETXEN_PCI_OCM1;
725 } else
726 if (ADDR_IN_RANGE
727 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
728 /* QDR network side */
729 addr -= NETXEN_ADDR_QDR_NET;
730 window = (addr >> 22) & 0x3f;
731 if (qdr_sn_window != window) {
732 qdr_sn_window = window;
733 writel((window << 22),
734 PCI_OFFSET_SECOND_RANGE(adapter,
735 NETXEN_PCIX_PH_REG
736 (PCIX_SN_WINDOW)));
737 /* MUST make sure window is set before we forge on... */
738 readl(PCI_OFFSET_SECOND_RANGE(adapter,
739 NETXEN_PCIX_PH_REG
740 (PCIX_SN_WINDOW)));
741 }
742 addr -= (window * 0x400000);
743 addr += NETXEN_PCI_QDR_NET;
744 } else {
745 /*
746 * peg gdb frequently accesses memory that doesn't exist,
747 * this limits the chit chat so debugging isn't slowed down.
748 */
749 if ((netxen_pci_set_window_warning_count++ < 8)
750 || (netxen_pci_set_window_warning_count % 64 == 0))
751 printk("%s: Warning:netxen_nic_pci_set_window()"
752 " Unknown address range!\n",
753 netxen_nic_driver_name);
754
755 }
756 return addr;
757}
758
759int netxen_nic_get_board_info(struct netxen_adapter *adapter)
760{
761 int rv = 0;
762 int addr = BRDCFG_START;
763 struct netxen_board_info *boardinfo;
764 int index;
765 u32 *ptr32;
766
767 boardinfo = &adapter->ahw.boardcfg;
768 ptr32 = (u32 *) boardinfo;
769
770 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
771 index++) {
772 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
773 return -EIO;
774 }
775 ptr32++;
776 addr += sizeof(u32);
777 }
778 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
779 printk("%s: ERROR reading %s board config."
780 " Read %x, expected %x\n", netxen_nic_driver_name,
781 netxen_nic_driver_name,
782 boardinfo->magic, NETXEN_BDINFO_MAGIC);
783 rv = -1;
784 }
785 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
786 printk("%s: Unknown board config version."
787 " Read %x, expected %x\n", netxen_nic_driver_name,
788 boardinfo->header_version, NETXEN_BDINFO_VERSION);
789 rv = -1;
790 }
791
792 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
793 switch ((netxen_brdtype_t) boardinfo->board_type) {
794 case NETXEN_BRDTYPE_P2_SB35_4G:
795 adapter->ahw.board_type = NETXEN_NIC_GBE;
796 break;
797 case NETXEN_BRDTYPE_P2_SB31_10G:
798 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
799 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
800 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
801 adapter->ahw.board_type = NETXEN_NIC_XGBE;
802 break;
803 case NETXEN_BRDTYPE_P1_BD:
804 case NETXEN_BRDTYPE_P1_SB:
805 case NETXEN_BRDTYPE_P1_SMAX:
806 case NETXEN_BRDTYPE_P1_SOCK:
807 adapter->ahw.board_type = NETXEN_NIC_GBE;
808 break;
809 default:
810 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
811 boardinfo->board_type);
812 break;
813 }
814
815 return rv;
816}
817
818/* NIU access sections */
819
820int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu)
821{
822 struct netxen_adapter *adapter = port->adapter;
823 netxen_nic_write_w0(adapter,
824 NETXEN_NIU_GB_MAX_FRAME_SIZE(port->portnum),
825 new_mtu);
826 return 0;
827}
828
829int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu)
830{
831 struct netxen_adapter *adapter = port->adapter;
832 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
833 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
834 return 0;
835}
836
837void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
838{
839 int portno;
840 for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++)
841 netxen_niu_gbe_init_port(adapter, portno);
842}
843
844void netxen_nic_stop_all_ports(struct netxen_adapter *adapter)
845{
846 int port_nr;
847 struct netxen_port *port;
848
849 for (port_nr = 0; port_nr < adapter->ahw.max_ports; port_nr++) {
850 port = adapter->port[port_nr];
851 if (adapter->ops->stop_port)
852 adapter->ops->stop_port(adapter, port->portnum);
853 }
854}
855
856void
857netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
858 int data)
859{
860 void __iomem *addr;
861
862 if (ADDR_IN_WINDOW1(off)) {
863 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
864 } else {
865 netxen_nic_pci_change_crbwindow(adapter, 0);
866 addr = pci_base_offset(adapter, off);
867 writel(data, addr);
868 netxen_nic_pci_change_crbwindow(adapter, 1);
869 }
870}
871
872void netxen_nic_set_link_parameters(struct netxen_port *port)
873{
874 struct netxen_adapter *adapter = port->adapter;
875 __le32 status;
876 u16 autoneg;
877 __le32 mode;
878
879 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
880 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
881 if (adapter->ops->phy_read
882 && adapter->ops->
883 phy_read(adapter, port->portnum,
884 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
885 &status) == 0) {
886 if (netxen_get_phy_link(status)) {
887 switch (netxen_get_phy_speed(status)) {
888 case 0:
889 port->link_speed = SPEED_10;
890 break;
891 case 1:
892 port->link_speed = SPEED_100;
893 break;
894 case 2:
895 port->link_speed = SPEED_1000;
896 break;
897 default:
898 port->link_speed = -1;
899 break;
900 }
901 switch (netxen_get_phy_duplex(status)) {
902 case 0:
903 port->link_duplex = DUPLEX_HALF;
904 break;
905 case 1:
906 port->link_duplex = DUPLEX_FULL;
907 break;
908 default:
909 port->link_duplex = -1;
910 break;
911 }
912 if (adapter->ops->phy_read
913 && adapter->ops->
914 phy_read(adapter, port->portnum,
915 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
916 (__le32 *) & autoneg) != 0)
917 port->link_autoneg = autoneg;
918 } else
919 goto link_down;
920 } else {
921 link_down:
922 port->link_speed = -1;
923 port->link_duplex = -1;
924 }
925 }
926}
927
928void netxen_nic_flash_print(struct netxen_adapter *adapter)
929{
930 int valid = 1;
931 u32 fw_major = 0;
932 u32 fw_minor = 0;
933 u32 fw_build = 0;
934 char brd_name[NETXEN_MAX_SHORT_NAME];
935 struct netxen_new_user_info user_info;
936 int i, addr = USER_START;
937 u32 *ptr32;
938
939 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
940 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
941 printk
942 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
943 board_info->magic, NETXEN_BDINFO_MAGIC);
944 valid = 0;
945 }
946 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
947 printk("NetXen Unknown board config version."
948 " Read %x, expected %x\n",
949 board_info->header_version, NETXEN_BDINFO_VERSION);
950 valid = 0;
951 }
952 if (valid) {
953 ptr32 = (u32 *) & user_info;
954 for (i = 0;
955 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
956 i++) {
957 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
958 printk("%s: ERROR reading %s board userarea.\n",
959 netxen_nic_driver_name,
960 netxen_nic_driver_name);
961 return;
962 }
963 ptr32++;
964 addr += sizeof(u32);
965 }
966 get_brd_name_by_type(board_info->board_type, brd_name);
967
968 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
969 brd_name, user_info.serial_num, board_info->chip_id);
970
971 printk("NetXen %s Board #%d, Chip id 0x%x\n",
972 board_info->board_type == 0x0b ? "XGB" : "GBE",
973 board_info->board_num, board_info->chip_id);
974 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
975 NETXEN_FW_VERSION_MAJOR));
976 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
977 NETXEN_FW_VERSION_MINOR));
978 fw_build =
979 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
980
981 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
982 fw_build);
983 }
984 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
985 printk(KERN_ERR "The mismatch in driver version and firmware "
986 "version major number\n"
987 "Driver version major number = %d \t"
988 "Firmware version major number = %d \n",
989 _NETXEN_NIC_LINUX_MAJOR, fw_major);
990 adapter->driver_mismatch = 1;
991 }
992 if (fw_minor != _NETXEN_NIC_LINUX_MINOR) {
993 printk(KERN_ERR "The mismatch in driver version and firmware "
994 "version minor number\n"
995 "Driver version minor number = %d \t"
996 "Firmware version minor number = %d \n",
997 _NETXEN_NIC_LINUX_MINOR, fw_minor);
998 adapter->driver_mismatch = 1;
999 }
1000 if (adapter->driver_mismatch)
1001 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
1002 fw_major, fw_minor);
1003}
1004
1005int netxen_crb_read_val(struct netxen_adapter *adapter, unsigned long off)
1006{
1007 int data;
1008 netxen_nic_hw_read_wx(adapter, off, &data, 4);
1009 return data;
1010}
diff --git a/drivers/net/netxen/netxen_nic_hw.h b/drivers/net/netxen/netxen_nic_hw.h
new file mode 100644
index 000000000000..201a636b7ab8
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_hw.h
@@ -0,0 +1,482 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Structures, enums, and macros for the MAC
31 *
32 */
33
34#ifndef __NETXEN_NIC_HW_H_
35#define __NETXEN_NIC_HW_H_
36
37#include "netxen_nic_hdr.h"
38
39/* Hardware memory size of 128 meg */
40#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
41
42#ifndef readq
43static inline u64 readq(void __iomem * addr)
44{
45 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
46}
47#endif
48
49#ifndef writeq
50static inline void writeq(u64 val, void __iomem * addr)
51{
52 writel(((u32) (val)), (addr));
53 writel(((u32) (val >> 32)), (addr + 4));
54}
55#endif
56
57static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr,
58 u64 __iomem * addr,
59 int num_words)
60{
61 int num;
62 for (num = 0; num < num_words; num++) {
63 writeq(readq((void __iomem *)data_ptr), addr);
64 addr++;
65 data_ptr++;
66 }
67}
68
69static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr,
70 u64 __iomem * addr, int num_words)
71{
72 int num;
73 for (num = 0; num < num_words; num++) {
74 writeq(readq((void __iomem *)addr), data_ptr);
75 addr++;
76 data_ptr++;
77 }
78
79}
80
81struct netxen_adapter;
82
83#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
84
85#define NETXEN_NIC_LOCKED_READ_REG(X, Y) \
86 addr = pci_base_offset(adapter, (X)); \
87 *(u32 *)Y = readl(addr);
88
89struct netxen_port;
90void netxen_nic_set_link_parameters(struct netxen_port *port);
91void netxen_nic_flash_print(struct netxen_adapter *adapter);
92int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off,
93 void *data, int len);
94void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
95 unsigned long off, int data);
96int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off,
97 void *data, int len);
98
99typedef u8 netxen_ethernet_macaddr_t[6];
100
101/* Nibble or Byte mode for phy interface (GbE mode only) */
102typedef enum {
103 NETXEN_NIU_10_100_MB = 0,
104 NETXEN_NIU_1000_MB
105} netxen_niu_gbe_ifmode_t;
106
107#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
108
109/*
110 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
111 *
112 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
113 * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
114 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable
115 * Bit 3 : rx_synced => R/O: recv enable synched to recv stream
116 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
117 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
118 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
119 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
120 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
121 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
122 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
123 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
124 */
125
126#define netxen_gb_enable_tx(config_word) \
127 set_bit(0, (unsigned long*)(&config_word))
128#define netxen_gb_enable_rx(config_word) \
129 set_bit(2, (unsigned long*)(&config_word))
130#define netxen_gb_tx_flowctl(config_word) \
131 set_bit(4, (unsigned long*)(&config_word))
132#define netxen_gb_rx_flowctl(config_word) \
133 set_bit(5, (unsigned long*)(&config_word))
134#define netxen_gb_tx_reset_pb(config_word) \
135 set_bit(16, (unsigned long*)(&config_word))
136#define netxen_gb_rx_reset_pb(config_word) \
137 set_bit(17, (unsigned long*)(&config_word))
138#define netxen_gb_tx_reset_mac(config_word) \
139 set_bit(18, (unsigned long*)(&config_word))
140#define netxen_gb_rx_reset_mac(config_word) \
141 set_bit(19, (unsigned long*)(&config_word))
142#define netxen_gb_soft_reset(config_word) \
143 set_bit(31, (unsigned long*)(&config_word))
144
145#define netxen_gb_unset_tx_flowctl(config_word) \
146 clear_bit(4, (unsigned long *)(&config_word))
147#define netxen_gb_unset_rx_flowctl(config_word) \
148 clear_bit(5, (unsigned long*)(&config_word))
149
150#define netxen_gb_get_tx_synced(config_word) \
151 _netxen_crb_get_bit((config_word), 1)
152#define netxen_gb_get_rx_synced(config_word) \
153 _netxen_crb_get_bit((config_word), 3)
154#define netxen_gb_get_tx_flowctl(config_word) \
155 _netxen_crb_get_bit((config_word), 4)
156#define netxen_gb_get_rx_flowctl(config_word) \
157 _netxen_crb_get_bit((config_word), 5)
158#define netxen_gb_get_soft_reset(config_word) \
159 _netxen_crb_get_bit((config_word), 31)
160
161/*
162 * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
163 *
164 * Bit 0 : duplex => 1:full duplex mode, 0:half duplex
165 * Bit 1 : crc_enable => 1:append CRC to xmit frames, 0:dont append
166 * Bit 2 : padshort => 1:pad short frames and add CRC, 0:dont pad
167 * Bit 4 : checklength => 1:check framelen with actual,0:dont check
168 * Bit 5 : hugeframes => 1:allow oversize xmit frames, 0:dont allow
169 * Bits 8-9 : intfmode => 01:nibble (10/100), 10:byte (1000)
170 * Bits 12-15 : preamblelen => preamble field length in bytes, default 7
171 */
172
173#define netxen_gb_set_duplex(config_word) \
174 set_bit(0, (unsigned long*)&config_word)
175#define netxen_gb_set_crc_enable(config_word) \
176 set_bit(1, (unsigned long*)&config_word)
177#define netxen_gb_set_padshort(config_word) \
178 set_bit(2, (unsigned long*)&config_word)
179#define netxen_gb_set_checklength(config_word) \
180 set_bit(4, (unsigned long*)&config_word)
181#define netxen_gb_set_hugeframes(config_word) \
182 set_bit(5, (unsigned long*)&config_word)
183#define netxen_gb_set_preamblelen(config_word, val) \
184 ((config_word) |= ((val) << 12) & 0xF000)
185#define netxen_gb_set_intfmode(config_word, val) \
186 ((config_word) |= ((val) << 8) & 0x300)
187
188#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
189
190#define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
191 ((config_word) |= ((val) & 0x07))
192#define netxen_gb_mii_mgmt_reset(config_word) \
193 set_bit(31, (unsigned long*)&config_word)
194#define netxen_gb_mii_mgmt_unset(config_word) \
195 clear_bit(31, (unsigned long*)&config_word)
196
197/*
198 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
199 * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
200 * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
201 */
202
203#define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
204 set_bit(0, (unsigned long*)&config_word)
205#define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
206 ((config_word) |= ((val) & 0x1F))
207#define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
208 ((config_word) |= (((val) & 0x1F) << 8))
209
210/*
211 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
212 * Read-only register.
213 * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
214 * Bit 1 : scanning => 1:scan operation in progress, 0:idle
215 * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
216 */
217#define netxen_get_gb_mii_mgmt_busy(config_word) \
218 _netxen_crb_get_bit(config_word, 0)
219#define netxen_get_gb_mii_mgmt_scanning(config_word) \
220 _netxen_crb_get_bit(config_word, 1)
221#define netxen_get_gb_mii_mgmt_notvalid(config_word) \
222 _netxen_crb_get_bit(config_word, 2)
223
224/*
225 * PHY-Specific MII control/status registers.
226 */
227typedef enum {
228 NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0,
229 NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1,
230 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2,
231 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3,
232 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4,
233 NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5,
234 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6,
235 NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7,
236 NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8,
237 NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9,
238 NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10,
239 NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15,
240 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16,
241 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17,
242 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18,
243 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19,
244 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20,
245 NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21,
246 NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24,
247 NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25,
248 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26,
249 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
250} netxen_niu_phy_register_t;
251
252/*
253 * PHY-Specific Status Register (reg 17).
254 *
255 * Bit 0 : jabber => 1:jabber detected, 0:not
256 * Bit 1 : polarity => 1:polarity reversed, 0:normal
257 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
258 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
259 * Bit 4 : energydetect => 1:sleep, 0:active
260 * Bit 5 : downshift => 1:downshift, 0:no downshift
261 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
262 * Bits 7-9 : cablelen => not valid in 10Mb/s mode
263 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
264 * Bit 10 : link => 1:link up, 0:link down
265 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
266 * Bit 12 : pagercvd => 1:page received, 0:page not received
267 * Bit 13 : duplex => 1:full duplex, 0:half duplex
268 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
269 */
270
271#define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
272#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
273
274#define netxen_set_phy_speed(config_word, val) \
275 ((config_word) |= ((val & 0x03) << 14))
276#define netxen_set_phy_duplex(config_word) \
277 set_bit(13, (unsigned long*)&config_word)
278#define netxen_clear_phy_duplex(config_word) \
279 clear_bit(13, (unsigned long*)&config_word)
280
281#define netxen_get_phy_jabber(config_word) \
282 _netxen_crb_get_bit(config_word, 0)
283#define netxen_get_phy_polarity(config_word) \
284 _netxen_crb_get_bit(config_word, 1)
285#define netxen_get_phy_recvpause(config_word) \
286 _netxen_crb_get_bit(config_word, 2)
287#define netxen_get_phy_xmitpause(config_word) \
288 _netxen_crb_get_bit(config_word, 3)
289#define netxen_get_phy_energydetect(config_word) \
290 _netxen_crb_get_bit(config_word, 4)
291#define netxen_get_phy_downshift(config_word) \
292 _netxen_crb_get_bit(config_word, 5)
293#define netxen_get_phy_crossover(config_word) \
294 _netxen_crb_get_bit(config_word, 6)
295#define netxen_get_phy_link(config_word) \
296 _netxen_crb_get_bit(config_word, 10)
297#define netxen_get_phy_resolved(config_word) \
298 _netxen_crb_get_bit(config_word, 11)
299#define netxen_get_phy_pagercvd(config_word) \
300 _netxen_crb_get_bit(config_word, 12)
301#define netxen_get_phy_duplex(config_word) \
302 _netxen_crb_get_bit(config_word, 13)
303
304/*
305 * Interrupt Register definition
306 * This definition applies to registers 18 and 19 (int enable and int status).
307 * Bit 0 : jabber
308 * Bit 1 : polarity_changed
309 * Bit 4 : energy_detect
310 * Bit 5 : downshift
311 * Bit 6 : mdi_xover_changed
312 * Bit 7 : fifo_over_underflow
313 * Bit 8 : false_carrier
314 * Bit 9 : symbol_error
315 * Bit 10: link_status_changed
316 * Bit 11: autoneg_completed
317 * Bit 12: page_received
318 * Bit 13: duplex_changed
319 * Bit 14: speed_changed
320 * Bit 15: autoneg_error
321 */
322
323#define netxen_get_phy_int_jabber(config_word) \
324 _netxen_crb_get_bit(config_word, 0)
325#define netxen_get_phy_int_polarity_changed(config_word) \
326 _netxen_crb_get_bit(config_word, 1)
327#define netxen_get_phy_int_energy_detect(config_word) \
328 _netxen_crb_get_bit(config_word, 4)
329#define netxen_get_phy_int_downshift(config_word) \
330 _netxen_crb_get_bit(config_word, 5)
331#define netxen_get_phy_int_mdi_xover_changed(config_word) \
332 _netxen_crb_get_bit(config_word, 6)
333#define netxen_get_phy_int_fifo_over_underflow(config_word) \
334 _netxen_crb_get_bit(config_word, 7)
335#define netxen_get_phy_int_false_carrier(config_word) \
336 _netxen_crb_get_bit(config_word, 8)
337#define netxen_get_phy_int_symbol_error(config_word) \
338 _netxen_crb_get_bit(config_word, 9)
339#define netxen_get_phy_int_link_status_changed(config_word) \
340 _netxen_crb_get_bit(config_word, 10)
341#define netxen_get_phy_int_autoneg_completed(config_word) \
342 _netxen_crb_get_bit(config_word, 11)
343#define netxen_get_phy_int_page_received(config_word) \
344 _netxen_crb_get_bit(config_word, 12)
345#define netxen_get_phy_int_duplex_changed(config_word) \
346 _netxen_crb_get_bit(config_word, 13)
347#define netxen_get_phy_int_speed_changed(config_word) \
348 _netxen_crb_get_bit(config_word, 14)
349#define netxen_get_phy_int_autoneg_error(config_word) \
350 _netxen_crb_get_bit(config_word, 15)
351
352#define netxen_set_phy_int_link_status_changed(config_word) \
353 set_bit(10, (unsigned long*)&config_word)
354#define netxen_set_phy_int_autoneg_completed(config_word) \
355 set_bit(11, (unsigned long*)&config_word)
356#define netxen_set_phy_int_speed_changed(config_word) \
357 set_bit(14, (unsigned long*)&config_word)
358
359/*
360 * NIU Mode Register.
361 * Bit 0 : enable FibreChannel
362 * Bit 1 : enable 10/100/1000 Ethernet
363 * Bit 2 : enable 10Gb Ethernet
364 */
365
366#define netxen_get_niu_enable_ge(config_word) \
367 _netxen_crb_get_bit(config_word, 1)
368
369/* Promiscous mode options (GbE mode only) */
370typedef enum {
371 NETXEN_NIU_PROMISC_MODE = 0,
372 NETXEN_NIU_NON_PROMISC_MODE
373} netxen_niu_prom_mode_t;
374
375/*
376 * NIU GB Drop CRC Register
377 *
378 * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
379 * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
380 * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
381 * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
382 */
383
384#define netxen_set_gb_drop_gb0(config_word) \
385 set_bit(0, (unsigned long*)&config_word)
386#define netxen_set_gb_drop_gb1(config_word) \
387 set_bit(1, (unsigned long*)&config_word)
388#define netxen_set_gb_drop_gb2(config_word) \
389 set_bit(2, (unsigned long*)&config_word)
390#define netxen_set_gb_drop_gb3(config_word) \
391 set_bit(3, (unsigned long*)&config_word)
392
393#define netxen_clear_gb_drop_gb0(config_word) \
394 clear_bit(0, (unsigned long*)&config_word)
395#define netxen_clear_gb_drop_gb1(config_word) \
396 clear_bit(1, (unsigned long*)&config_word)
397#define netxen_clear_gb_drop_gb2(config_word) \
398 clear_bit(2, (unsigned long*)&config_word)
399#define netxen_clear_gb_drop_gb3(config_word) \
400 clear_bit(3, (unsigned long*)&config_word)
401
402/*
403 * NIU XG MAC Config Register
404 *
405 * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
406 * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
407 * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
408 * Bit 27: xaui_framer_reset
409 * Bit 28: xaui_rx_reset
410 * Bit 29: xaui_tx_reset
411 * Bit 30: xg_ingress_afifo_reset
412 * Bit 31: xg_egress_afifo_reset
413 */
414
415#define netxen_xg_soft_reset(config_word) \
416 set_bit(4, (unsigned long*)&config_word)
417
418/*
419 * MAC Control Register
420 *
421 * Bit 0-1 : id_pool0
422 * Bit 2 : enable_xtnd0
423 * Bit 4-5 : id_pool1
424 * Bit 6 : enable_xtnd1
425 * Bit 8-9 : id_pool2
426 * Bit 10 : enable_xtnd2
427 * Bit 12-13 : id_pool3
428 * Bit 14 : enable_xtnd3
429 * Bit 24-25 : mode_select
430 * Bit 28-31 : enable_pool
431 */
432
433#define netxen_nic_mcr_set_id_pool0(config, val) \
434 ((config) |= ((val) &0x03))
435#define netxen_nic_mcr_set_enable_xtnd0(config) \
436 (set_bit(3, (unsigned long *)&(config)))
437#define netxen_nic_mcr_set_id_pool1(config, val) \
438 ((config) |= (((val) & 0x03) << 4))
439#define netxen_nic_mcr_set_enable_xtnd1(config) \
440 (set_bit(6, (unsigned long *)&(config)))
441#define netxen_nic_mcr_set_id_pool2(config, val) \
442 ((config) |= (((val) & 0x03) << 8))
443#define netxen_nic_mcr_set_enable_xtnd2(config) \
444 (set_bit(10, (unsigned long *)&(config)))
445#define netxen_nic_mcr_set_id_pool3(config, val) \
446 ((config) |= (((val) & 0x03) << 12))
447#define netxen_nic_mcr_set_enable_xtnd3(config) \
448 (set_bit(14, (unsigned long *)&(config)))
449#define netxen_nic_mcr_set_mode_select(config, val) \
450 ((config) |= (((val) & 0x03) << 24))
451#define netxen_nic_mcr_set_enable_pool(config, val) \
452 ((config) |= (((val) & 0x0f) << 28))
453
454/* Set promiscuous mode for a GbE interface */
455int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port,
456 netxen_niu_prom_mode_t mode);
457int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
458 int port, netxen_niu_prom_mode_t mode);
459
460/* get/set the MAC address for a given MAC */
461int netxen_niu_macaddr_get(struct netxen_adapter *adapter, int port,
462 netxen_ethernet_macaddr_t * addr);
463int netxen_niu_macaddr_set(struct netxen_port *port,
464 netxen_ethernet_macaddr_t addr);
465
466/* XG versons */
467int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int port,
468 netxen_ethernet_macaddr_t * addr);
469int netxen_niu_xg_macaddr_set(struct netxen_port *port,
470 netxen_ethernet_macaddr_t addr);
471
472/* Generic enable for GbE ports. Will detect the speed of the link. */
473int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
474
475int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
476
477/* Disable a GbE interface */
478int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port);
479
480int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port);
481
482#endif /* __NETXEN_NIC_HW_H_ */
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
new file mode 100644
index 000000000000..0dca029bc3e5
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -0,0 +1,1304 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to initialize the Phantom Hardware
31 *
32 */
33
34#include <linux/netdevice.h>
35#include <linux/delay.h>
36#include "netxen_nic.h"
37#include "netxen_nic_hw.h"
38#include "netxen_nic_ioctl.h"
39#include "netxen_nic_phan_reg.h"
40
41struct crb_addr_pair {
42 long addr;
43 long data;
44};
45
46#define NETXEN_MAX_CRB_XFORM 60
47static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
48#define NETXEN_ADDR_ERROR ((unsigned long ) 0xffffffff )
49
50#define crb_addr_transform(name) \
51 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
52 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
53
54#define NETXEN_NIC_XDMA_RESET 0x8000ff
55
56static inline void
57netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
58 unsigned long off, int *data)
59{
60 void __iomem *addr = pci_base_offset(adapter, off);
61 writel(*data, addr);
62}
63
64static void crb_addr_transform_setup(void)
65{
66 crb_addr_transform(XDMA);
67 crb_addr_transform(TIMR);
68 crb_addr_transform(SRE);
69 crb_addr_transform(SQN3);
70 crb_addr_transform(SQN2);
71 crb_addr_transform(SQN1);
72 crb_addr_transform(SQN0);
73 crb_addr_transform(SQS3);
74 crb_addr_transform(SQS2);
75 crb_addr_transform(SQS1);
76 crb_addr_transform(SQS0);
77 crb_addr_transform(RPMX7);
78 crb_addr_transform(RPMX6);
79 crb_addr_transform(RPMX5);
80 crb_addr_transform(RPMX4);
81 crb_addr_transform(RPMX3);
82 crb_addr_transform(RPMX2);
83 crb_addr_transform(RPMX1);
84 crb_addr_transform(RPMX0);
85 crb_addr_transform(ROMUSB);
86 crb_addr_transform(SN);
87 crb_addr_transform(QMN);
88 crb_addr_transform(QMS);
89 crb_addr_transform(PGNI);
90 crb_addr_transform(PGND);
91 crb_addr_transform(PGN3);
92 crb_addr_transform(PGN2);
93 crb_addr_transform(PGN1);
94 crb_addr_transform(PGN0);
95 crb_addr_transform(PGSI);
96 crb_addr_transform(PGSD);
97 crb_addr_transform(PGS3);
98 crb_addr_transform(PGS2);
99 crb_addr_transform(PGS1);
100 crb_addr_transform(PGS0);
101 crb_addr_transform(PS);
102 crb_addr_transform(PH);
103 crb_addr_transform(NIU);
104 crb_addr_transform(I2Q);
105 crb_addr_transform(EG);
106 crb_addr_transform(MN);
107 crb_addr_transform(MS);
108 crb_addr_transform(CAS2);
109 crb_addr_transform(CAS1);
110 crb_addr_transform(CAS0);
111 crb_addr_transform(CAM);
112 crb_addr_transform(C2C1);
113 crb_addr_transform(C2C0);
114}
115
116int netxen_init_firmware(struct netxen_adapter *adapter)
117{
118 u32 state = 0, loops = 0, err = 0;
119
120 /* Window 1 call */
121 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
122
123 if (state == PHAN_INITIALIZE_ACK)
124 return 0;
125
126 while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
127 udelay(100);
128 /* Window 1 call */
129 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
130
131 loops++;
132 }
133 if (loops >= 2000) {
134 printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
135 state);
136 err = -EIO;
137 return err;
138 }
139 /* Window 1 call */
140 writel(PHAN_INITIALIZE_ACK,
141 NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
142
143 return err;
144}
145
146#define NETXEN_ADDR_LIMIT 0xffffffffULL
147
148void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
149 struct pci_dev **used_dev)
150{
151 void *addr;
152
153 addr = pci_alloc_consistent(pdev, sz, ptr);
154 if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
155 *used_dev = pdev;
156 return addr;
157 }
158 pci_free_consistent(pdev, sz, addr, *ptr);
159 addr = pci_alloc_consistent(NULL, sz, ptr);
160 *used_dev = NULL;
161 return addr;
162}
163
164void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
165{
166 int ctxid, ring;
167 u32 i;
168 u32 num_rx_bufs = 0;
169 struct netxen_rcv_desc_ctx *rcv_desc;
170
171 DPRINTK(INFO, "initializing some queues: %p\n", adapter);
172 for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
173 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
174 struct netxen_rx_buffer *rx_buf;
175 rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
176 rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
177 rcv_desc->begin_alloc = 0;
178 rx_buf = rcv_desc->rx_buf_arr;
179 num_rx_bufs = rcv_desc->max_rx_desc_count;
180 /*
181 * Now go through all of them, set reference handles
182 * and put them in the queues.
183 */
184 for (i = 0; i < num_rx_bufs; i++) {
185 rx_buf->ref_handle = i;
186 rx_buf->state = NETXEN_BUFFER_FREE;
187
188 DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
189 "%p\n", ctxid, i, rx_buf);
190 rx_buf++;
191 }
192 }
193 }
194 DPRINTK(INFO, "initialized buffers for %s and %s\n",
195 "adapter->free_cmd_buf_list", "adapter->free_rxbuf");
196}
197
198void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
199{
200 int ports = 0;
201 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
202
203 if (netxen_nic_get_board_info(adapter) != 0)
204 printk("%s: Error getting board config info.\n",
205 netxen_nic_driver_name);
206 get_brd_port_by_type(board_info->board_type, &ports);
207 if (ports == 0)
208 printk(KERN_ERR "%s: Unknown board type\n",
209 netxen_nic_driver_name);
210 adapter->ahw.max_ports = ports;
211}
212
213void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
214{
215 struct netxen_drvops *ops = adapter->ops;
216 switch (adapter->ahw.board_type) {
217 case NETXEN_NIC_GBE:
218 ops->enable_phy_interrupts =
219 netxen_niu_gbe_enable_phy_interrupts;
220 ops->disable_phy_interrupts =
221 netxen_niu_gbe_disable_phy_interrupts;
222 ops->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
223 ops->macaddr_set = netxen_niu_macaddr_set;
224 ops->set_mtu = netxen_nic_set_mtu_gb;
225 ops->set_promisc = netxen_niu_set_promiscuous_mode;
226 ops->unset_promisc = netxen_niu_set_promiscuous_mode;
227 ops->phy_read = netxen_niu_gbe_phy_read;
228 ops->phy_write = netxen_niu_gbe_phy_write;
229 ops->init_port = netxen_niu_gbe_init_port;
230 ops->init_niu = netxen_nic_init_niu_gb;
231 ops->stop_port = netxen_niu_disable_gbe_port;
232 break;
233
234 case NETXEN_NIC_XGBE:
235 ops->enable_phy_interrupts =
236 netxen_niu_xgbe_enable_phy_interrupts;
237 ops->disable_phy_interrupts =
238 netxen_niu_xgbe_disable_phy_interrupts;
239 ops->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
240 ops->macaddr_set = netxen_niu_xg_macaddr_set;
241 ops->set_mtu = netxen_nic_set_mtu_xgb;
242 ops->init_port = netxen_niu_xg_init_port;
243 ops->set_promisc = netxen_niu_xg_set_promiscuous_mode;
244 ops->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
245 ops->stop_port = netxen_niu_disable_xg_port;
246 break;
247
248 default:
249 break;
250 }
251}
252
253/*
254 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
255 * address to external PCI CRB address.
256 */
257unsigned long netxen_decode_crb_addr(unsigned long addr)
258{
259 int i;
260 unsigned long base_addr, offset, pci_base;
261
262 crb_addr_transform_setup();
263
264 pci_base = NETXEN_ADDR_ERROR;
265 base_addr = addr & 0xfff00000;
266 offset = addr & 0x000fffff;
267
268 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
269 if (crb_addr_xform[i] == base_addr) {
270 pci_base = i << 20;
271 break;
272 }
273 }
274 if (pci_base == NETXEN_ADDR_ERROR)
275 return pci_base;
276 else
277 return (pci_base + offset);
278}
279
280static long rom_max_timeout = 10000;
281static long rom_lock_timeout = 1000000;
282
283static inline int rom_lock(struct netxen_adapter *adapter)
284{
285 int iter;
286 u32 done = 0;
287 int timeout = 0;
288
289 while (!done) {
290 /* acquire semaphore2 from PCI HW block */
291 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
292 &done);
293 if (done == 1)
294 break;
295 if (timeout >= rom_lock_timeout)
296 return -EIO;
297
298 timeout++;
299 /*
300 * Yield CPU
301 */
302 if (!in_atomic())
303 schedule();
304 else {
305 for (iter = 0; iter < 20; iter++)
306 cpu_relax(); /*This a nop instr on i386 */
307 }
308 }
309 netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
310 return 0;
311}
312
313int netxen_wait_rom_done(struct netxen_adapter *adapter)
314{
315 long timeout = 0;
316 long done = 0;
317
318 while (done == 0) {
319 done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
320 done &= 2;
321 timeout++;
322 if (timeout >= rom_max_timeout) {
323 printk("Timeout reached waiting for rom done");
324 return -EIO;
325 }
326 }
327 return 0;
328}
329
330static inline int netxen_rom_wren(struct netxen_adapter *adapter)
331{
332 /* Set write enable latch in ROM status register */
333 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
334 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
335 M25P_INSTR_WREN);
336 if (netxen_wait_rom_done(adapter)) {
337 return -1;
338 }
339 return 0;
340}
341
342static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
343 unsigned int addr)
344{
345 unsigned int data = 0xdeaddead;
346 data = netxen_nic_reg_read(adapter, addr);
347 return data;
348}
349
350static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
351{
352 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
353 M25P_INSTR_RDSR);
354 if (netxen_wait_rom_done(adapter)) {
355 return -1;
356 }
357 return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
358}
359
360static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
361{
362 u32 val;
363
364 /* release semaphore2 */
365 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
366
367}
368
369int netxen_rom_wip_poll(struct netxen_adapter *adapter)
370{
371 long timeout = 0;
372 long wip = 1;
373 int val;
374 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
375 while (wip != 0) {
376 val = netxen_do_rom_rdsr(adapter);
377 wip = val & 1;
378 timeout++;
379 if (timeout > rom_max_timeout) {
380 return -1;
381 }
382 }
383 return 0;
384}
385
386static inline int do_rom_fast_write(struct netxen_adapter *adapter,
387 int addr, int data)
388{
389 if (netxen_rom_wren(adapter)) {
390 return -1;
391 }
392 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
393 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
394 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
395 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
396 M25P_INSTR_PP);
397 if (netxen_wait_rom_done(adapter)) {
398 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
399 return -1;
400 }
401
402 return netxen_rom_wip_poll(adapter);
403}
404
405static inline int
406do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
407{
408 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
409 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
410 udelay(100); /* prevent bursting on CRB */
411 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
412 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
413 if (netxen_wait_rom_done(adapter)) {
414 printk("Error waiting for rom done\n");
415 return -EIO;
416 }
417 /* reset abyte_cnt and dummy_byte_cnt */
418 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
419 udelay(100); /* prevent bursting on CRB */
420 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
421
422 *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
423 return 0;
424}
425
426int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
427{
428 int ret;
429
430 if (rom_lock(adapter) != 0)
431 return -EIO;
432
433 ret = do_rom_fast_read(adapter, addr, valp);
434 netxen_rom_unlock(adapter);
435 return ret;
436}
437
438int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
439{
440 int ret = 0;
441
442 if (rom_lock(adapter) != 0) {
443 return -1;
444 }
445 ret = do_rom_fast_write(adapter, addr, data);
446 netxen_rom_unlock(adapter);
447 return ret;
448}
449int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
450{
451 netxen_rom_wren(adapter);
452 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
453 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
454 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
455 M25P_INSTR_SE);
456 if (netxen_wait_rom_done(adapter)) {
457 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
458 return -1;
459 }
460 return netxen_rom_wip_poll(adapter);
461}
462
463int netxen_rom_se(struct netxen_adapter *adapter, int addr)
464{
465 int ret = 0;
466 if (rom_lock(adapter) != 0) {
467 return -1;
468 }
469 ret = netxen_do_rom_se(adapter, addr);
470 netxen_rom_unlock(adapter);
471 return ret;
472}
473
474#define NETXEN_BOARDTYPE 0x4008
475#define NETXEN_BOARDNUM 0x400c
476#define NETXEN_CHIPNUM 0x4010
477#define NETXEN_ROMBUS_RESET 0xFFFFFFFF
478#define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
479#define NETXEN_ROM_FOUND_INIT 0x400
480
481int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
482{
483 int addr, val, status;
484 int n, i;
485 int init_delay = 0;
486 struct crb_addr_pair *buf;
487 unsigned long off;
488
489 /* resetall */
490 status = netxen_nic_get_board_info(adapter);
491 if (status)
492 printk("%s: netxen_pinit_from_rom: Error getting board info\n",
493 netxen_nic_driver_name);
494
495 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
496 NETXEN_ROMBUS_RESET);
497
498 if (verbose) {
499 int val;
500 if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
501 printk("P2 ROM board type: 0x%08x\n", val);
502 else
503 printk("Could not read board type\n");
504 if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
505 printk("P2 ROM board num: 0x%08x\n", val);
506 else
507 printk("Could not read board number\n");
508 if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
509 printk("P2 ROM chip num: 0x%08x\n", val);
510 else
511 printk("Could not read chip number\n");
512 }
513
514 if (netxen_rom_fast_read(adapter, 0, &n) == 0
515 && (n & NETXEN_ROM_FIRST_BARRIER)) {
516 n &= ~NETXEN_ROM_ROUNDUP;
517 if (n < NETXEN_ROM_FOUND_INIT) {
518 if (verbose)
519 printk("%s: %d CRB init values found"
520 " in ROM.\n", netxen_nic_driver_name, n);
521 } else {
522 printk("%s:n=0x%x Error! NetXen card flash not"
523 " initialized.\n", __FUNCTION__, n);
524 return -EIO;
525 }
526 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
527 if (buf == NULL) {
528 printk("%s: netxen_pinit_from_rom: Unable to calloc "
529 "memory.\n", netxen_nic_driver_name);
530 return -ENOMEM;
531 }
532 for (i = 0; i < n; i++) {
533 if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
534 || netxen_rom_fast_read(adapter, 8 * i + 8,
535 &addr) != 0)
536 return -EIO;
537
538 buf[i].addr = addr;
539 buf[i].data = val;
540
541 if (verbose)
542 printk("%s: PCI: 0x%08x == 0x%08x\n",
543 netxen_nic_driver_name, (unsigned int)
544 netxen_decode_crb_addr((unsigned long)
545 addr), val);
546 }
547 for (i = 0; i < n; i++) {
548
549 off =
550 netxen_decode_crb_addr((unsigned long)buf[i].addr) +
551 NETXEN_PCI_CRBSPACE;
552 /* skipping cold reboot MAGIC */
553 if (off == NETXEN_CAM_RAM(0x1fc))
554 continue;
555
556 /* After writing this register, HW needs time for CRB */
557 /* to quiet down (else crb_window returns 0xffffffff) */
558 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
559 init_delay = 1;
560 /* hold xdma in reset also */
561 buf[i].data = NETXEN_NIC_XDMA_RESET;
562 }
563
564 if (ADDR_IN_WINDOW1(off)) {
565 writel(buf[i].data,
566 NETXEN_CRB_NORMALIZE(adapter, off));
567 } else {
568 netxen_nic_pci_change_crbwindow(adapter, 0);
569 writel(buf[i].data,
570 pci_base_offset(adapter, off));
571
572 netxen_nic_pci_change_crbwindow(adapter, 1);
573 }
574 if (init_delay == 1) {
575 ssleep(1);
576 init_delay = 0;
577 }
578 msleep(1);
579 }
580 kfree(buf);
581
582 /* disable_peg_cache_all */
583
584 /* unreset_net_cache */
585 netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
586 4);
587 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
588 (val & 0xffffff0f));
589 /* p2dn replyCount */
590 netxen_crb_writelit_adapter(adapter,
591 NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
592 /* disable_peg_cache 0 */
593 netxen_crb_writelit_adapter(adapter,
594 NETXEN_CRB_PEG_NET_D + 0x4c, 8);
595 /* disable_peg_cache 1 */
596 netxen_crb_writelit_adapter(adapter,
597 NETXEN_CRB_PEG_NET_I + 0x4c, 8);
598
599 /* peg_clr_all */
600
601 /* peg_clr 0 */
602 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
603 0);
604 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
605 0);
606 /* peg_clr 1 */
607 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
608 0);
609 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
610 0);
611 /* peg_clr 2 */
612 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
613 0);
614 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
615 0);
616 /* peg_clr 3 */
617 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
618 0);
619 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
620 0);
621 }
622 return 0;
623}
624
625void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
626{
627 u32 val = 0;
628 int loops = 0;
629
630 if (!pegtune_val) {
631 while (val != PHAN_INITIALIZE_COMPLETE && loops < 200000) {
632 udelay(100);
633 schedule();
634 val =
635 readl(NETXEN_CRB_NORMALIZE
636 (adapter, CRB_CMDPEG_STATE));
637 loops++;
638 }
639 if (val != PHAN_INITIALIZE_COMPLETE)
640 printk("WARNING: Initial boot wait loop failed...\n");
641 }
642}
643
644int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
645{
646 int ctx;
647
648 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
649 struct netxen_recv_context *recv_ctx =
650 &(adapter->recv_ctx[ctx]);
651 u32 consumer;
652 struct status_desc *desc_head;
653 struct status_desc *desc;
654
655 consumer = recv_ctx->status_rx_consumer;
656 desc_head = recv_ctx->rcv_status_desc_head;
657 desc = &desc_head[consumer];
658
659 if (((le16_to_cpu(desc->owner)) & STATUS_OWNER_HOST))
660 return 1;
661 }
662
663 return 0;
664}
665
666static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
667{
668 int port_num;
669 struct netxen_port *port;
670 struct net_device *netdev;
671 uint32_t temp, temp_state, temp_val;
672 int rv = 0;
673
674 temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
675
676 temp_state = nx_get_temp_state(temp);
677 temp_val = nx_get_temp_val(temp);
678
679 if (temp_state == NX_TEMP_PANIC) {
680 printk(KERN_ALERT
681 "%s: Device temperature %d degrees C exceeds"
682 " maximum allowed. Hardware has been shut down.\n",
683 netxen_nic_driver_name, temp_val);
684 for (port_num = 0; port_num < adapter->ahw.max_ports;
685 port_num++) {
686 port = adapter->port[port_num];
687 netdev = port->netdev;
688
689 netif_carrier_off(netdev);
690 netif_stop_queue(netdev);
691 }
692 rv = 1;
693 } else if (temp_state == NX_TEMP_WARN) {
694 if (adapter->temp == NX_TEMP_NORMAL) {
695 printk(KERN_ALERT
696 "%s: Device temperature %d degrees C "
697 "exceeds operating range."
698 " Immediate action needed.\n",
699 netxen_nic_driver_name, temp_val);
700 }
701 } else {
702 if (adapter->temp == NX_TEMP_WARN) {
703 printk(KERN_INFO
704 "%s: Device temperature is now %d degrees C"
705 " in normal range.\n", netxen_nic_driver_name,
706 temp_val);
707 }
708 }
709 adapter->temp = temp_state;
710 return rv;
711}
712
713void netxen_watchdog_task(unsigned long v)
714{
715 int port_num;
716 struct netxen_port *port;
717 struct net_device *netdev;
718 struct netxen_adapter *adapter = (struct netxen_adapter *)v;
719
720 if (netxen_nic_check_temp(adapter))
721 return;
722
723 for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
724 port = adapter->port[port_num];
725 netdev = port->netdev;
726
727 if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
728 printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
729 netxen_nic_driver_name, port_num, netdev->name);
730 netif_carrier_on(netdev);
731 }
732
733 if (netif_queue_stopped(netdev))
734 netif_wake_queue(netdev);
735 }
736
737 if (adapter->ops->handle_phy_intr)
738 adapter->ops->handle_phy_intr(adapter);
739 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
740}
741
742/*
743 * netxen_process_rcv() send the received packet to the protocol stack.
744 * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
745 * invoke the routine to send more rx buffers to the Phantom...
746 */
747void
748netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
749 struct status_desc *desc)
750{
751 struct netxen_port *port = adapter->port[STATUS_DESC_PORT(desc)];
752 struct pci_dev *pdev = port->pdev;
753 struct net_device *netdev = port->netdev;
754 int index = le16_to_cpu(desc->reference_handle);
755 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
756 struct netxen_rx_buffer *buffer;
757 struct sk_buff *skb;
758 u32 length = le16_to_cpu(desc->total_length);
759 u32 desc_ctx;
760 struct netxen_rcv_desc_ctx *rcv_desc;
761 int ret;
762
763 desc_ctx = STATUS_DESC_TYPE(desc);
764 if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
765 printk("%s: %s Bad Rcv descriptor ring\n",
766 netxen_nic_driver_name, netdev->name);
767 return;
768 }
769
770 rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
771 buffer = &rcv_desc->rx_buf_arr[index];
772
773 pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
774 PCI_DMA_FROMDEVICE);
775
776 skb = (struct sk_buff *)buffer->skb;
777
778 if (likely(STATUS_DESC_STATUS(desc) == STATUS_CKSUM_OK)) {
779 port->stats.csummed++;
780 skb->ip_summed = CHECKSUM_UNNECESSARY;
781 } else
782 skb->ip_summed = CHECKSUM_NONE;
783 skb->dev = netdev;
784 skb_put(skb, length);
785 skb->protocol = eth_type_trans(skb, netdev);
786
787 ret = netif_receive_skb(skb);
788
789 /*
790 * RH: Do we need these stats on a regular basis. Can we get it from
791 * Linux stats.
792 */
793 switch (ret) {
794 case NET_RX_SUCCESS:
795 port->stats.uphappy++;
796 break;
797
798 case NET_RX_CN_LOW:
799 port->stats.uplcong++;
800 break;
801
802 case NET_RX_CN_MOD:
803 port->stats.upmcong++;
804 break;
805
806 case NET_RX_CN_HIGH:
807 port->stats.uphcong++;
808 break;
809
810 case NET_RX_DROP:
811 port->stats.updropped++;
812 break;
813
814 default:
815 port->stats.updunno++;
816 break;
817 }
818
819 netdev->last_rx = jiffies;
820
821 rcv_desc->rcv_free++;
822 rcv_desc->rcv_pending--;
823
824 /*
825 * We just consumed one buffer so post a buffer.
826 */
827 adapter->stats.post_called++;
828 buffer->skb = NULL;
829 buffer->state = NETXEN_BUFFER_FREE;
830
831 port->stats.no_rcv++;
832 port->stats.rxbytes += length;
833}
834
835/* Process Receive status ring */
836u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
837{
838 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
839 struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
840 struct status_desc *desc; /* used to read status desc here */
841 u32 consumer = recv_ctx->status_rx_consumer;
842 int count = 0, ring;
843
844 DPRINTK(INFO, "procesing receive\n");
845 /*
846 * we assume in this case that there is only one port and that is
847 * port #1...changes need to be done in firmware to indicate port
848 * number as part of the descriptor. This way we will be able to get
849 * the netdev which is associated with that device.
850 */
851 while (count < max) {
852 desc = &desc_head[consumer];
853 if (!((le16_to_cpu(desc->owner)) & STATUS_OWNER_HOST)) {
854 DPRINTK(ERR, "desc %p ownedby %x\n", desc, desc->owner);
855 break;
856 }
857 netxen_process_rcv(adapter, ctxid, desc);
858 desc->owner = STATUS_OWNER_PHANTOM;
859 consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
860 count++;
861 }
862 if (count) {
863 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
864 netxen_post_rx_buffers(adapter, ctxid, ring);
865 }
866 }
867
868 /* update the consumer index in phantom */
869 if (count) {
870 adapter->stats.process_rcv++;
871 recv_ctx->status_rx_consumer = consumer;
872
873 /* Window = 1 */
874 writel(consumer,
875 NETXEN_CRB_NORMALIZE(adapter,
876 recv_crb_registers[ctxid].
877 crb_rcv_status_consumer));
878 }
879
880 return count;
881}
882
883/* Process Command status ring */
884void netxen_process_cmd_ring(unsigned long data)
885{
886 u32 last_consumer;
887 u32 consumer;
888 struct netxen_adapter *adapter = (struct netxen_adapter *)data;
889 int count = 0;
890 struct netxen_cmd_buffer *buffer;
891 struct netxen_port *port; /* port #1 */
892 struct netxen_port *nport;
893 struct pci_dev *pdev;
894 struct netxen_skb_frag *frag;
895 u32 i;
896 struct sk_buff *skb = NULL;
897 int p;
898
899 spin_lock(&adapter->tx_lock);
900 last_consumer = adapter->last_cmd_consumer;
901 DPRINTK(INFO, "procesing xmit complete\n");
902 /* we assume in this case that there is only one port and that is
903 * port #1...changes need to be done in firmware to indicate port
904 * number as part of the descriptor. This way we will be able to get
905 * the netdev which is associated with that device.
906 */
907 consumer =
908 readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_CONSUMER_OFFSET));
909
910 if (last_consumer == consumer) { /* Ring is empty */
911 DPRINTK(INFO, "last_consumer %d == consumer %d\n",
912 last_consumer, consumer);
913 spin_unlock(&adapter->tx_lock);
914 return;
915 }
916
917 adapter->proc_cmd_buf_counter++;
918 adapter->stats.process_xmit++;
919 /*
920 * Not needed - does not seem to be used anywhere.
921 * adapter->cmd_consumer = consumer;
922 */
923 spin_unlock(&adapter->tx_lock);
924
925 while ((last_consumer != consumer) && (count < MAX_STATUS_HANDLE)) {
926 buffer = &adapter->cmd_buf_arr[last_consumer];
927 port = adapter->port[buffer->port];
928 pdev = port->pdev;
929 frag = &buffer->frag_array[0];
930 skb = buffer->skb;
931 if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
932 pci_unmap_single(pdev, frag->dma, frag->length,
933 PCI_DMA_TODEVICE);
934 for (i = 1; i < buffer->frag_count; i++) {
935 DPRINTK(INFO, "getting fragment no %d\n", i);
936 frag++; /* Get the next frag */
937 pci_unmap_page(pdev, frag->dma, frag->length,
938 PCI_DMA_TODEVICE);
939 }
940
941 port->stats.skbfreed++;
942 dev_kfree_skb_any(skb);
943 skb = NULL;
944 } else if (adapter->proc_cmd_buf_counter == 1) {
945 port->stats.txnullskb++;
946 }
947 if (unlikely(netif_queue_stopped(port->netdev)
948 && netif_carrier_ok(port->netdev))
949 && ((jiffies - port->netdev->trans_start) >
950 port->netdev->watchdog_timeo)) {
951 schedule_work(&port->adapter->tx_timeout_task);
952 }
953
954 last_consumer = get_next_index(last_consumer,
955 adapter->max_tx_desc_count);
956 count++;
957 }
958 adapter->stats.noxmitdone += count;
959
960 count = 0;
961 spin_lock(&adapter->tx_lock);
962 if ((--adapter->proc_cmd_buf_counter) == 0) {
963 adapter->last_cmd_consumer = last_consumer;
964 while ((adapter->last_cmd_consumer != consumer)
965 && (count < MAX_STATUS_HANDLE)) {
966 buffer =
967 &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
968 count++;
969 if (buffer->skb)
970 break;
971 else
972 adapter->last_cmd_consumer =
973 get_next_index(adapter->last_cmd_consumer,
974 adapter->max_tx_desc_count);
975 }
976 }
977 if (count) {
978 for (p = 0; p < adapter->ahw.max_ports; p++) {
979 nport = adapter->port[p];
980 if (netif_queue_stopped(nport->netdev)
981 && (nport->flags & NETXEN_NETDEV_STATUS)) {
982 netif_wake_queue(nport->netdev);
983 nport->flags &= ~NETXEN_NETDEV_STATUS;
984 }
985 }
986 }
987
988 spin_unlock(&adapter->tx_lock);
989 DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
990 __FUNCTION__);
991}
992
993/*
994 * netxen_post_rx_buffers puts buffer in the Phantom memory
995 */
996void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
997{
998 struct pci_dev *pdev = adapter->ahw.pdev;
999 struct sk_buff *skb;
1000 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
1001 struct netxen_rcv_desc_ctx *rcv_desc = NULL;
1002 struct netxen_recv_crb *crbarea = &recv_crb_registers[ctx];
1003 struct netxen_rcv_desc_crb *rcv_desc_crb = NULL;
1004 u32 producer;
1005 struct rcv_desc *pdesc;
1006 struct netxen_rx_buffer *buffer;
1007 int count = 0;
1008 int index = 0;
1009
1010 adapter->stats.post_called++;
1011 rcv_desc = &recv_ctx->rcv_desc[ringid];
1012 rcv_desc_crb = &crbarea->rcv_desc_crb[ringid];
1013
1014 producer = rcv_desc->producer;
1015 index = rcv_desc->begin_alloc;
1016 buffer = &rcv_desc->rx_buf_arr[index];
1017 /* We can start writing rx descriptors into the phantom memory. */
1018 while (buffer->state == NETXEN_BUFFER_FREE) {
1019 skb = dev_alloc_skb(rcv_desc->skb_size);
1020 if (unlikely(!skb)) {
1021 /*
1022 * We need to schedule the posting of buffers to the pegs.
1023 */
1024 rcv_desc->begin_alloc = index;
1025 DPRINTK(ERR, "netxen_post_rx_buffers: "
1026 " allocated only %d buffers\n", count);
1027 break;
1028 }
1029 count++; /* now there should be no failure */
1030 pdesc = &rcv_desc->desc_head[producer];
1031 skb_reserve(skb, NET_IP_ALIGN);
1032 /*
1033 * This will be setup when we receive the
1034 * buffer after it has been filled
1035 * skb->dev = netdev;
1036 */
1037 buffer->skb = skb;
1038 buffer->state = NETXEN_BUFFER_BUSY;
1039 buffer->dma = pci_map_single(pdev, skb->data,
1040 rcv_desc->dma_size,
1041 PCI_DMA_FROMDEVICE);
1042 /* make a rcv descriptor */
1043 pdesc->reference_handle = le16_to_cpu(buffer->ref_handle);
1044 pdesc->buffer_length = le16_to_cpu(rcv_desc->dma_size);
1045 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
1046 DPRINTK(INFO, "done writing descripter\n");
1047 producer =
1048 get_next_index(producer, rcv_desc->max_rx_desc_count);
1049 index = get_next_index(index, rcv_desc->max_rx_desc_count);
1050 buffer = &rcv_desc->rx_buf_arr[index];
1051 }
1052
1053 /* if we did allocate buffers, then write the count to Phantom */
1054 if (count) {
1055 rcv_desc->begin_alloc = index;
1056 rcv_desc->rcv_pending += count;
1057 adapter->stats.lastposted = count;
1058 adapter->stats.posted += count;
1059 rcv_desc->producer = producer;
1060 if (rcv_desc->rcv_free >= 32) {
1061 rcv_desc->rcv_free = 0;
1062 /* Window = 1 */
1063 writel((producer - 1) &
1064 (rcv_desc->max_rx_desc_count - 1),
1065 NETXEN_CRB_NORMALIZE(adapter,
1066 rcv_desc_crb->
1067 crb_rcv_producer_offset));
1068 wmb();
1069 }
1070 }
1071}
1072
1073int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
1074{
1075 if (find_diff_among(adapter->last_cmd_consumer,
1076 adapter->cmd_producer,
1077 adapter->max_tx_desc_count) > 0)
1078 return 1;
1079
1080 return 0;
1081}
1082
1083int
1084netxen_nic_fill_statistics(struct netxen_adapter *adapter,
1085 struct netxen_port *port,
1086 struct netxen_statistics *netxen_stats)
1087{
1088 void __iomem *addr;
1089
1090 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
1091 netxen_nic_pci_change_crbwindow(adapter, 0);
1092 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_TX_BYTE_CNT,
1093 &(netxen_stats->tx_bytes));
1094 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_TX_FRAME_CNT,
1095 &(netxen_stats->tx_packets));
1096 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_RX_BYTE_CNT,
1097 &(netxen_stats->rx_bytes));
1098 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_RX_FRAME_CNT,
1099 &(netxen_stats->rx_packets));
1100 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_AGGR_ERROR_CNT,
1101 &(netxen_stats->rx_errors));
1102 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_CRC_ERROR_CNT,
1103 &(netxen_stats->rx_crc_errors));
1104 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR,
1105 &(netxen_stats->
1106 rx_long_length_error));
1107 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR,
1108 &(netxen_stats->
1109 rx_short_length_error));
1110
1111 netxen_nic_pci_change_crbwindow(adapter, 1);
1112 } else {
1113 spin_lock_bh(&adapter->tx_lock);
1114 netxen_stats->tx_bytes = port->stats.txbytes;
1115 netxen_stats->tx_packets = port->stats.xmitedframes +
1116 port->stats.xmitfinished;
1117 netxen_stats->rx_bytes = port->stats.rxbytes;
1118 netxen_stats->rx_packets = port->stats.no_rcv;
1119 netxen_stats->rx_errors = port->stats.rcvdbadskb;
1120 netxen_stats->tx_errors = port->stats.nocmddescriptor;
1121 netxen_stats->rx_short_length_error = port->stats.uplcong;
1122 netxen_stats->rx_long_length_error = port->stats.uphcong;
1123 netxen_stats->rx_crc_errors = 0;
1124 netxen_stats->rx_mac_errors = 0;
1125 spin_unlock_bh(&adapter->tx_lock);
1126 }
1127 return 0;
1128}
1129
1130void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1131{
1132 struct netxen_port *port;
1133 int port_num;
1134
1135 memset(&adapter->stats, 0, sizeof(adapter->stats));
1136 for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
1137 port = adapter->port[port_num];
1138 memset(&port->stats, 0, sizeof(port->stats));
1139 }
1140}
1141
1142int
1143netxen_nic_clear_statistics(struct netxen_adapter *adapter,
1144 struct netxen_port *port)
1145{
1146 int data = 0;
1147
1148 netxen_nic_pci_change_crbwindow(adapter, 0);
1149
1150 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_TX_BYTE_CNT, &data);
1151 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_TX_FRAME_CNT,
1152 &data);
1153 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_RX_BYTE_CNT, &data);
1154 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_RX_FRAME_CNT,
1155 &data);
1156 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_AGGR_ERROR_CNT,
1157 &data);
1158 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_CRC_ERROR_CNT,
1159 &data);
1160 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR,
1161 &data);
1162 netxen_nic_locked_write_reg(adapter, NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR,
1163 &data);
1164
1165 netxen_nic_pci_change_crbwindow(adapter, 1);
1166 netxen_nic_clear_stats(adapter);
1167 return 0;
1168}
1169
1170int
1171netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
1172 struct netxen_port *port)
1173{
1174 struct netxen_nic_ioctl_data data;
1175 struct netxen_nic_ioctl_data *up_data;
1176 int retval = 0;
1177 struct netxen_statistics netxen_stats;
1178
1179 up_data = (void *)u_data;
1180
1181 DPRINTK(INFO, "doing ioctl for %p\n", adapter);
1182 if (copy_from_user(&data, (void __user *)up_data, sizeof(data))) {
1183 /* evil user tried to crash the kernel */
1184 DPRINTK(ERR, "bad copy from userland: %d\n", (int)sizeof(data));
1185 retval = -EFAULT;
1186 goto error_out;
1187 }
1188
1189 /* Shouldn't access beyond legal limits of "char u[64];" member */
1190 if (!data.ptr && (data.size > sizeof(data.u))) {
1191 /* evil user tried to crash the kernel */
1192 DPRINTK(ERR, "bad size: %d\n", data.size);
1193 retval = -EFAULT;
1194 goto error_out;
1195 }
1196
1197 switch (data.cmd) {
1198 case netxen_nic_cmd_pci_read:
1199 if ((retval = netxen_nic_hw_read_wx(adapter, data.off,
1200 &(data.u), data.size)))
1201 goto error_out;
1202 if (copy_to_user
1203 ((void __user *)&(up_data->u), &(data.u), data.size)) {
1204 DPRINTK(ERR, "bad copy to userland: %d\n",
1205 (int)sizeof(data));
1206 retval = -EFAULT;
1207 goto error_out;
1208 }
1209 data.rv = 0;
1210 break;
1211
1212 case netxen_nic_cmd_pci_write:
1213 data.rv = netxen_nic_hw_write_wx(adapter, data.off, &(data.u),
1214 data.size);
1215 break;
1216
1217 case netxen_nic_cmd_pci_config_read:
1218 switch (data.size) {
1219 case 1:
1220 data.rv = pci_read_config_byte(adapter->ahw.pdev,
1221 data.off,
1222 (char *)&(data.u));
1223 break;
1224 case 2:
1225 data.rv = pci_read_config_word(adapter->ahw.pdev,
1226 data.off,
1227 (short *)&(data.u));
1228 break;
1229 case 4:
1230 data.rv = pci_read_config_dword(adapter->ahw.pdev,
1231 data.off,
1232 (u32 *) & (data.u));
1233 break;
1234 }
1235 if (copy_to_user
1236 ((void __user *)&(up_data->u), &(data.u), data.size)) {
1237 DPRINTK(ERR, "bad copy to userland: %d\n",
1238 (int)sizeof(data));
1239 retval = -EFAULT;
1240 goto error_out;
1241 }
1242 break;
1243
1244 case netxen_nic_cmd_pci_config_write:
1245 switch (data.size) {
1246 case 1:
1247 data.rv = pci_write_config_byte(adapter->ahw.pdev,
1248 data.off,
1249 *(char *)&(data.u));
1250 break;
1251 case 2:
1252 data.rv = pci_write_config_word(adapter->ahw.pdev,
1253 data.off,
1254 *(short *)&(data.u));
1255 break;
1256 case 4:
1257 data.rv = pci_write_config_dword(adapter->ahw.pdev,
1258 data.off,
1259 *(u32 *) & (data.u));
1260 break;
1261 }
1262 break;
1263
1264 case netxen_nic_cmd_get_stats:
1265 data.rv =
1266 netxen_nic_fill_statistics(adapter, port, &netxen_stats);
1267 if (copy_to_user
1268 ((void __user *)(up_data->ptr), (void *)&netxen_stats,
1269 sizeof(struct netxen_statistics))) {
1270 DPRINTK(ERR, "bad copy to userland: %d\n",
1271 (int)sizeof(netxen_stats));
1272 retval = -EFAULT;
1273 goto error_out;
1274 }
1275 up_data->rv = data.rv;
1276 break;
1277
1278 case netxen_nic_cmd_clear_stats:
1279 data.rv = netxen_nic_clear_statistics(adapter, port);
1280 up_data->rv = data.rv;
1281 break;
1282
1283 case netxen_nic_cmd_get_version:
1284 if (copy_to_user
1285 ((void __user *)&(up_data->u), NETXEN_NIC_LINUX_VERSIONID,
1286 sizeof(NETXEN_NIC_LINUX_VERSIONID))) {
1287 DPRINTK(ERR, "bad copy to userland: %d\n",
1288 (int)sizeof(data));
1289 retval = -EFAULT;
1290 goto error_out;
1291 }
1292 break;
1293
1294 default:
1295 DPRINTK(INFO, "bad command %d for %p\n", data.cmd, adapter);
1296 retval = -EOPNOTSUPP;
1297 goto error_out;
1298 }
1299 put_user(data.rv, (u16 __user *) (&(up_data->rv)));
1300 DPRINTK(INFO, "done ioctl for %p well.\n", adapter);
1301
1302 error_out:
1303 return retval;
1304}
diff --git a/drivers/net/netxen/netxen_nic_ioctl.h b/drivers/net/netxen/netxen_nic_ioctl.h
new file mode 100644
index 000000000000..23e53adbf123
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_ioctl.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30#ifndef __NETXEN_NIC_IOCTL_H__
31#define __NETXEN_NIC_IOCTL_H__
32
33#include <linux/sockios.h>
34
35#define NETXEN_CMD_START SIOCDEVPRIVATE
36#define NETXEN_NIC_CMD (NETXEN_CMD_START + 1)
37#define NETXEN_NIC_NAME (NETXEN_CMD_START + 2)
38#define NETXEN_NIC_NAME_LEN 16
39#define NETXEN_NIC_NAME_RSP "NETXEN"
40
41typedef enum {
42 netxen_nic_cmd_none = 0,
43 netxen_nic_cmd_pci_read,
44 netxen_nic_cmd_pci_write,
45 netxen_nic_cmd_pci_mem_read,
46 netxen_nic_cmd_pci_mem_write,
47 netxen_nic_cmd_pci_config_read,
48 netxen_nic_cmd_pci_config_write,
49 netxen_nic_cmd_get_stats,
50 netxen_nic_cmd_clear_stats,
51 netxen_nic_cmd_get_version
52} netxen_nic_ioctl_cmd_t;
53
54struct netxen_nic_ioctl_data {
55 u32 cmd;
56 u32 unused1;
57 u64 off;
58 u32 size;
59 u32 rv;
60 char u[64];
61 void *ptr;
62};
63
64struct netxen_statistics {
65 u64 rx_packets;
66 u64 tx_packets;
67 u64 rx_bytes;
68 u64 rx_errors;
69 u64 tx_bytes;
70 u64 tx_errors;
71 u64 rx_crc_errors;
72 u64 rx_short_length_error;
73 u64 rx_long_length_error;
74 u64 rx_mac_errors;
75};
76
77#endif /* __NETXEN_NIC_IOCTL_H_ */
diff --git a/drivers/net/netxen/netxen_nic_isr.c b/drivers/net/netxen/netxen_nic_isr.c
new file mode 100644
index 000000000000..ae180fee8008
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_isr.c
@@ -0,0 +1,215 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30#include <linux/netdevice.h>
31#include <linux/delay.h>
32
33#include "netxen_nic.h"
34#include "netxen_nic_hw.h"
35#include "netxen_nic_phan_reg.h"
36
37/*
38 * netxen_nic_get_stats - Get System Network Statistics
39 * @netdev: network interface device structure
40 */
41struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
42{
43 struct netxen_port *port = netdev_priv(netdev);
44 struct net_device_stats *stats = &port->net_stats;
45
46 memset(stats, 0, sizeof(*stats));
47
48 /* total packets received */
49 stats->rx_packets = port->stats.no_rcv;
50 /* total packets transmitted */
51 stats->tx_packets = port->stats.xmitedframes + port->stats.xmitfinished;
52 /* total bytes received */
53 stats->rx_bytes = port->stats.rxbytes;
54 /* total bytes transmitted */
55 stats->tx_bytes = port->stats.txbytes;
56 /* bad packets received */
57 stats->rx_errors = port->stats.rcvdbadskb;
58 /* packet transmit problems */
59 stats->tx_errors = port->stats.nocmddescriptor;
60 /* no space in linux buffers */
61 stats->rx_dropped = port->stats.updropped;
62 /* no space available in linux */
63 stats->tx_dropped = port->stats.txdropped;
64
65 return stats;
66}
67
68void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 portno,
69 u32 link)
70{
71 struct netxen_port *pport = adapter->port[portno];
72 struct net_device *netdev = pport->netdev;
73
74 if (link)
75 netif_carrier_on(netdev);
76 else
77 netif_carrier_off(netdev);
78}
79
80void netxen_handle_port_int(struct netxen_adapter *adapter, u32 portno,
81 u32 enable)
82{
83 __le32 int_src;
84 struct netxen_port *port;
85
86 /* This should clear the interrupt source */
87 if (adapter->ops->phy_read)
88 adapter->ops->phy_read(adapter, portno,
89 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
90 &int_src);
91 if (int_src == 0) {
92 DPRINTK(INFO, "No phy interrupts for port #%d\n", portno);
93 return;
94 }
95 if (adapter->ops->disable_phy_interrupts)
96 adapter->ops->disable_phy_interrupts(adapter, portno);
97
98 port = adapter->port[portno];
99
100 if (netxen_get_phy_int_jabber(int_src))
101 DPRINTK(INFO, "NetXen: %s Jabber interrupt \n",
102 port->netdev->name);
103
104 if (netxen_get_phy_int_polarity_changed(int_src))
105 DPRINTK(INFO, "NetXen: %s POLARITY CHANGED int \n",
106 port->netdev->name);
107
108 if (netxen_get_phy_int_energy_detect(int_src))
109 DPRINTK(INFO, "NetXen: %s ENERGY DETECT INT \n",
110 port->netdev->name);
111
112 if (netxen_get_phy_int_downshift(int_src))
113 DPRINTK(INFO, "NetXen: %s DOWNSHIFT INT \n",
114 port->netdev->name);
115 /* write it down later.. */
116 if ((netxen_get_phy_int_speed_changed(int_src))
117 || (netxen_get_phy_int_link_status_changed(int_src))) {
118 __le32 status;
119
120 DPRINTK(INFO, "NetXen: %s SPEED CHANGED OR"
121 " LINK STATUS CHANGED \n", port->netdev->name);
122
123 if (adapter->ops->phy_read
124 && adapter->ops->phy_read(adapter, portno,
125 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
126 &status) == 0) {
127 if (netxen_get_phy_int_link_status_changed(int_src)) {
128 if (netxen_get_phy_link(status)) {
129 netxen_niu_gbe_init_port(adapter,
130 portno);
131 printk("%s: %s Link UP\n",
132 netxen_nic_driver_name,
133 port->netdev->name);
134
135 } else {
136 printk("%s: %s Link DOWN\n",
137 netxen_nic_driver_name,
138 port->netdev->name);
139 }
140 netxen_indicate_link_status(adapter, portno,
141 netxen_get_phy_link
142 (status));
143 }
144 }
145 }
146 if (adapter->ops->enable_phy_interrupts)
147 adapter->ops->enable_phy_interrupts(adapter, portno);
148}
149
150void netxen_nic_isr_other(struct netxen_adapter *adapter)
151{
152 u32 portno;
153 u32 val, linkup, qg_linksup;
154
155 /* verify the offset */
156 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
157 if (val == adapter->ahw.qg_linksup)
158 return;
159
160 qg_linksup = adapter->ahw.qg_linksup;
161 adapter->ahw.qg_linksup = val;
162 DPRINTK(1, INFO, "%s: link update 0x%08x\n", netxen_nic_driver_name,
163 val);
164 for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++) {
165 linkup = val & 1;
166 if (linkup != (qg_linksup & 1)) {
167 printk(KERN_INFO "%s: PORT %d link %s\n",
168 netxen_nic_driver_name, portno,
169 ((linkup == 0) ? "down" : "up"));
170 netxen_indicate_link_status(adapter, portno, linkup);
171 if (linkup)
172 netxen_nic_set_link_parameters(adapter->
173 port[portno]);
174
175 }
176 val = val >> 1;
177 qg_linksup = qg_linksup >> 1;
178 }
179
180 adapter->stats.otherints++;
181
182}
183
184void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter)
185{
186 netxen_nic_isr_other(adapter);
187}
188
189void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter)
190{
191 struct net_device *netdev = adapter->port[0]->netdev;
192 u32 val;
193
194 /* WINDOW = 1 */
195 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
196
197 if (adapter->ahw.xg_linkup == 1 && val != XG_LINK_UP) {
198 printk(KERN_INFO "%s: %s NIC Link is down\n",
199 netxen_nic_driver_name, netdev->name);
200 adapter->ahw.xg_linkup = 0;
201 /* read twice to clear sticky bits */
202 /* WINDOW = 0 */
203 netxen_nic_read_w0(adapter, NETXEN_NIU_XG_STATUS, &val);
204 netxen_nic_read_w0(adapter, NETXEN_NIU_XG_STATUS, &val);
205
206 if ((val & 0xffb) != 0xffb) {
207 printk(KERN_INFO "%s ISR: Sync/Align BAD: 0x%08x\n",
208 netxen_nic_driver_name, val);
209 }
210 } else if (adapter->ahw.xg_linkup == 0 && val == XG_LINK_UP) {
211 printk(KERN_INFO "%s: %s NIC Link is up\n",
212 netxen_nic_driver_name, netdev->name);
213 adapter->ahw.xg_linkup = 1;
214 }
215}
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
new file mode 100644
index 000000000000..1cb662d5bd76
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -0,0 +1,1161 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Main source file for NetXen NIC Driver on Linux
31 *
32 */
33
34#include <linux/vmalloc.h>
35#include "netxen_nic_hw.h"
36
37#include "netxen_nic.h"
38#define DEFINE_GLOBAL_RECV_CRB
39#include "netxen_nic_phan_reg.h"
40#include "netxen_nic_ioctl.h"
41
42#include <linux/dma-mapping.h>
43#include <linux/vmalloc.h>
44
45#define PHAN_VENDOR_ID 0x4040
46
47MODULE_DESCRIPTION("NetXen Multi port (1/10) Gigabit Network Driver");
48MODULE_LICENSE("GPL");
49MODULE_VERSION(NETXEN_NIC_LINUX_VERSIONID);
50
51char netxen_nic_driver_name[] = "netxen";
52static char netxen_nic_driver_string[] = "NetXen Network Driver version "
53 NETXEN_NIC_LINUX_VERSIONID;
54
55#define NETXEN_NETDEV_WEIGHT 120
56#define NETXEN_ADAPTER_UP_MAGIC 777
57#define NETXEN_NIC_PEG_TUNE 0
58
59/* Local functions to NetXen NIC driver */
60static int __devinit netxen_nic_probe(struct pci_dev *pdev,
61 const struct pci_device_id *ent);
62static void __devexit netxen_nic_remove(struct pci_dev *pdev);
63static int netxen_nic_open(struct net_device *netdev);
64static int netxen_nic_close(struct net_device *netdev);
65static int netxen_nic_xmit_frame(struct sk_buff *, struct net_device *);
66static void netxen_tx_timeout(struct net_device *netdev);
67static void netxen_tx_timeout_task(struct net_device *netdev);
68static void netxen_watchdog(unsigned long);
69static int netxen_handle_int(struct netxen_adapter *, struct net_device *);
70static int netxen_nic_ioctl(struct net_device *netdev,
71 struct ifreq *ifr, int cmd);
72static int netxen_nic_poll(struct net_device *dev, int *budget);
73#ifdef CONFIG_NET_POLL_CONTROLLER
74static void netxen_nic_poll_controller(struct net_device *netdev);
75#endif
76static irqreturn_t netxen_intr(int irq, void *data);
77
78/* PCI Device ID Table */
79static struct pci_device_id netxen_pci_tbl[] __devinitdata = {
80 {PCI_DEVICE(0x4040, 0x0001)},
81 {PCI_DEVICE(0x4040, 0x0002)},
82 {PCI_DEVICE(0x4040, 0x0003)},
83 {PCI_DEVICE(0x4040, 0x0004)},
84 {PCI_DEVICE(0x4040, 0x0005)},
85 {0,}
86};
87
88MODULE_DEVICE_TABLE(pci, netxen_pci_tbl);
89
90/*
91 * netxen_nic_probe()
92 *
93 * The Linux system will invoke this after identifying the vendor ID and
94 * device Id in the pci_tbl supported by this module.
95 *
96 * A quad port card has one operational PCI config space, (function 0),
97 * which is used to access all four ports.
98 *
99 * This routine will initialize the adapter, and setup the global parameters
100 * along with the port's specific structure.
101 */
102static int __devinit
103netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
104{
105 struct net_device *netdev = NULL;
106 struct netxen_adapter *adapter = NULL;
107 struct netxen_port *port = NULL;
108 u8 *mem_ptr0 = NULL;
109 u8 *mem_ptr1 = NULL;
110 u8 *mem_ptr2 = NULL;
111
112 unsigned long mem_base, mem_len;
113 int pci_using_dac, i, err;
114 int ring;
115 struct netxen_recv_context *recv_ctx = NULL;
116 struct netxen_rcv_desc_ctx *rcv_desc = NULL;
117 struct netxen_cmd_buffer *cmd_buf_arr = NULL;
118 u64 mac_addr[FLASH_NUM_PORTS + 1];
119 int valid_mac;
120
121 printk(KERN_INFO "%s \n", netxen_nic_driver_string);
122 if ((err = pci_enable_device(pdev)))
123 return err;
124 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
125 err = -ENODEV;
126 goto err_out_disable_pdev;
127 }
128
129 if ((err = pci_request_regions(pdev, netxen_nic_driver_name)))
130 goto err_out_disable_pdev;
131
132 pci_set_master(pdev);
133 if ((pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) &&
134 (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) == 0))
135 pci_using_dac = 1;
136 else {
137 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
138 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)))
139 goto err_out_free_res;
140
141 pci_using_dac = 0;
142 }
143
144 /* remap phys address */
145 mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */
146 mem_len = pci_resource_len(pdev, 0);
147
148 /* 128 Meg of memory */
149 mem_ptr0 = ioremap(mem_base, FIRST_PAGE_GROUP_SIZE);
150 mem_ptr1 =
151 ioremap(mem_base + SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_SIZE);
152 mem_ptr2 =
153 ioremap(mem_base + THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE);
154
155 if ((mem_ptr0 == 0UL) || (mem_ptr1 == 0UL) || (mem_ptr2 == 0UL)) {
156 DPRINTK(1, ERR,
157 "Cannot remap adapter memory aborting.:"
158 "0 -> %p, 1 -> %p, 2 -> %p\n",
159 mem_ptr0, mem_ptr1, mem_ptr2);
160
161 err = -EIO;
162 if (mem_ptr0)
163 iounmap(mem_ptr0);
164 if (mem_ptr1)
165 iounmap(mem_ptr1);
166 if (mem_ptr2)
167 iounmap(mem_ptr2);
168
169 goto err_out_free_res;
170 }
171
172/*
173 * Allocate a adapter structure which will manage all the initialization
174 * as well as the common resources for all ports...
175 * all the ports will have pointer to this adapter as well as Adapter
176 * will have pointers of all the ports structures.
177 */
178
179 /* One adapter structure for all 4 ports.... */
180 adapter = kzalloc(sizeof(struct netxen_adapter), GFP_KERNEL);
181 if (adapter == NULL) {
182 printk(KERN_ERR "%s: Could not allocate adapter memory:%d\n",
183 netxen_nic_driver_name,
184 (int)sizeof(struct netxen_adapter));
185 err = -ENOMEM;
186 goto err_out_iounmap;
187 }
188
189 adapter->max_tx_desc_count = MAX_CMD_DESCRIPTORS;
190 adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS;
191 adapter->max_jumbo_rx_desc_count = MAX_JUMBO_RCV_DESCRIPTORS;
192
193 pci_set_drvdata(pdev, adapter);
194
195 cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
196 if (cmd_buf_arr == NULL) {
197 err = -ENOMEM;
198 goto err_out_free_adapter;
199 }
200 memset(cmd_buf_arr, 0, TX_RINGSIZE);
201
202 for (i = 0; i < MAX_RCV_CTX; ++i) {
203 recv_ctx = &adapter->recv_ctx[i];
204 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
205 rcv_desc = &recv_ctx->rcv_desc[ring];
206 switch (RCV_DESC_TYPE(ring)) {
207 case RCV_DESC_NORMAL:
208 rcv_desc->max_rx_desc_count =
209 adapter->max_rx_desc_count;
210 rcv_desc->flags = RCV_DESC_NORMAL;
211 rcv_desc->dma_size = RX_DMA_MAP_LEN;
212 rcv_desc->skb_size = MAX_RX_BUFFER_LENGTH;
213 break;
214
215 case RCV_DESC_JUMBO:
216 rcv_desc->max_rx_desc_count =
217 adapter->max_jumbo_rx_desc_count;
218 rcv_desc->flags = RCV_DESC_JUMBO;
219 rcv_desc->dma_size = RX_JUMBO_DMA_MAP_LEN;
220 rcv_desc->skb_size = MAX_RX_JUMBO_BUFFER_LENGTH;
221 break;
222
223 }
224 rcv_desc->rx_buf_arr = (struct netxen_rx_buffer *)
225 vmalloc(RCV_BUFFSIZE);
226
227 if (rcv_desc->rx_buf_arr == NULL) {
228 err = -ENOMEM;
229 goto err_out_free_rx_buffer;
230 }
231 memset(rcv_desc->rx_buf_arr, 0, RCV_BUFFSIZE);
232 }
233
234 }
235
236 adapter->ops = kzalloc(sizeof(struct netxen_drvops), GFP_KERNEL);
237 if (adapter->ops == NULL) {
238 printk(KERN_ERR
239 "%s: Could not allocate memory for adapter->ops:%d\n",
240 netxen_nic_driver_name,
241 (int)sizeof(struct netxen_adapter));
242 err = -ENOMEM;
243 goto err_out_free_rx_buffer;
244 }
245
246 adapter->cmd_buf_arr = cmd_buf_arr;
247 adapter->ahw.pci_base0 = mem_ptr0;
248 adapter->ahw.pci_base1 = mem_ptr1;
249 adapter->ahw.pci_base2 = mem_ptr2;
250 spin_lock_init(&adapter->tx_lock);
251 spin_lock_init(&adapter->lock);
252#ifdef CONFIG_IA64
253 netxen_pinit_from_rom(adapter, 0);
254 udelay(500);
255 netxen_load_firmware(adapter);
256#endif
257
258 /* initialize the buffers in adapter */
259 netxen_initialize_adapter_sw(adapter);
260 /*
261 * Set the CRB window to invalid. If any register in window 0 is
262 * accessed it should set the window to 0 and then reset it to 1.
263 */
264 adapter->curr_window = 255;
265 /*
266 * Adapter in our case is quad port so initialize it before
267 * initializing the ports
268 */
269 netxen_initialize_adapter_hw(adapter); /* initialize the adapter */
270
271 netxen_initialize_adapter_ops(adapter);
272
273 init_timer(&adapter->watchdog_timer);
274 adapter->ahw.xg_linkup = 0;
275 adapter->watchdog_timer.function = &netxen_watchdog;
276 adapter->watchdog_timer.data = (unsigned long)adapter;
277 INIT_WORK(&adapter->watchdog_task,
278 (void (*)(void *))netxen_watchdog_task, adapter);
279 adapter->ahw.pdev = pdev;
280 adapter->proc_cmd_buf_counter = 0;
281 pci_read_config_byte(pdev, PCI_REVISION_ID, &adapter->ahw.revision_id);
282
283 if (pci_enable_msi(pdev)) {
284 adapter->flags &= ~NETXEN_NIC_MSI_ENABLED;
285 printk(KERN_WARNING "%s: unable to allocate MSI interrupt"
286 " error\n", netxen_nic_driver_name);
287 } else
288 adapter->flags |= NETXEN_NIC_MSI_ENABLED;
289
290 if (netxen_is_flash_supported(adapter) == 0 &&
291 netxen_get_flash_mac_addr(adapter, mac_addr) == 0)
292 valid_mac = 1;
293 else
294 valid_mac = 0;
295
296 /*
297 * Initialize all the CRB registers here.
298 */
299 writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_PRODUCER_OFFSET));
300 writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_CONSUMER_OFFSET));
301 writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
302
303 /* Unlock the HW, prompting the boot sequence */
304 writel(1,
305 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
306
307 /* Handshake with the card before we register the devices. */
308 netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
309
310 /* initialize the all the ports */
311
312 for (i = 0; i < adapter->ahw.max_ports; i++) {
313 netdev = alloc_etherdev(sizeof(struct netxen_port));
314 if (!netdev) {
315 printk(KERN_ERR "%s: could not allocate netdev for port"
316 " %d\n", netxen_nic_driver_name, i + 1);
317 goto err_out_free_dev;
318 }
319
320 SET_MODULE_OWNER(netdev);
321 SET_NETDEV_DEV(netdev, &pdev->dev);
322
323 port = netdev_priv(netdev);
324 port->netdev = netdev;
325 port->pdev = pdev;
326 port->adapter = adapter;
327 port->portnum = i; /* Gigabit port number from 0-3 */
328
329 netdev->open = netxen_nic_open;
330 netdev->stop = netxen_nic_close;
331 netdev->hard_start_xmit = netxen_nic_xmit_frame;
332 netdev->get_stats = netxen_nic_get_stats;
333 netdev->set_multicast_list = netxen_nic_set_multi;
334 netdev->set_mac_address = netxen_nic_set_mac;
335 netdev->change_mtu = netxen_nic_change_mtu;
336 netdev->do_ioctl = netxen_nic_ioctl;
337 netdev->tx_timeout = netxen_tx_timeout;
338 netdev->watchdog_timeo = HZ;
339
340 SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops);
341 netdev->poll = netxen_nic_poll;
342 netdev->weight = NETXEN_NETDEV_WEIGHT;
343#ifdef CONFIG_NET_POLL_CONTROLLER
344 netdev->poll_controller = netxen_nic_poll_controller;
345#endif
346 /* ScatterGather support */
347 netdev->features = NETIF_F_SG;
348 netdev->features |= NETIF_F_IP_CSUM;
349 netdev->features |= NETIF_F_TSO;
350
351 if (pci_using_dac)
352 netdev->features |= NETIF_F_HIGHDMA;
353
354 if (valid_mac) {
355 unsigned char *p = (unsigned char *)&mac_addr[i];
356 netdev->dev_addr[0] = *(p + 5);
357 netdev->dev_addr[1] = *(p + 4);
358 netdev->dev_addr[2] = *(p + 3);
359 netdev->dev_addr[3] = *(p + 2);
360 netdev->dev_addr[4] = *(p + 1);
361 netdev->dev_addr[5] = *(p + 0);
362
363 memcpy(netdev->perm_addr, netdev->dev_addr,
364 netdev->addr_len);
365 if (!is_valid_ether_addr(netdev->perm_addr)) {
366 printk(KERN_ERR "%s: Bad MAC address "
367 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
368 netxen_nic_driver_name,
369 netdev->dev_addr[0],
370 netdev->dev_addr[1],
371 netdev->dev_addr[2],
372 netdev->dev_addr[3],
373 netdev->dev_addr[4],
374 netdev->dev_addr[5]);
375 } else {
376 if (adapter->ops->macaddr_set)
377 adapter->ops->macaddr_set(port,
378 netdev->
379 dev_addr);
380 }
381 }
382 INIT_WORK(&adapter->tx_timeout_task,
383 (void (*)(void *))netxen_tx_timeout_task, netdev);
384 netif_carrier_off(netdev);
385 netif_stop_queue(netdev);
386
387 if ((err = register_netdev(netdev))) {
388 printk(KERN_ERR "%s: register_netdev failed port #%d"
389 " aborting\n", netxen_nic_driver_name, i + 1);
390 err = -EIO;
391 free_netdev(netdev);
392 goto err_out_free_dev;
393 }
394 adapter->port_count++;
395 adapter->active_ports = 0;
396 adapter->port[i] = port;
397 }
398
399 /*
400 * delay a while to ensure that the Pegs are up & running.
401 * Otherwise, we might see some flaky behaviour.
402 */
403 udelay(100);
404
405 switch (adapter->ahw.board_type) {
406 case NETXEN_NIC_GBE:
407 printk("%s: QUAD GbE board initialized\n",
408 netxen_nic_driver_name);
409 break;
410
411 case NETXEN_NIC_XGBE:
412 printk("%s: XGbE board initialized\n", netxen_nic_driver_name);
413 break;
414 }
415
416 adapter->driver_mismatch = 0;
417
418 return 0;
419
420 err_out_free_dev:
421 if (adapter->flags & NETXEN_NIC_MSI_ENABLED)
422 pci_disable_msi(pdev);
423 for (i = 0; i < adapter->port_count; i++) {
424 port = adapter->port[i];
425 if ((port) && (port->netdev)) {
426 unregister_netdev(port->netdev);
427 free_netdev(port->netdev);
428 }
429 }
430 kfree(adapter->ops);
431
432 err_out_free_rx_buffer:
433 for (i = 0; i < MAX_RCV_CTX; ++i) {
434 recv_ctx = &adapter->recv_ctx[i];
435 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
436 rcv_desc = &recv_ctx->rcv_desc[ring];
437 if (rcv_desc->rx_buf_arr != NULL) {
438 vfree(rcv_desc->rx_buf_arr);
439 rcv_desc->rx_buf_arr = NULL;
440 }
441 }
442 }
443
444 vfree(cmd_buf_arr);
445
446 kfree(adapter->port);
447
448 err_out_free_adapter:
449 pci_set_drvdata(pdev, NULL);
450 kfree(adapter);
451
452 err_out_iounmap:
453 iounmap(mem_ptr0);
454 iounmap(mem_ptr1);
455 iounmap(mem_ptr2);
456
457 err_out_free_res:
458 pci_release_regions(pdev);
459 err_out_disable_pdev:
460 pci_disable_device(pdev);
461 return err;
462}
463
464static void __devexit netxen_nic_remove(struct pci_dev *pdev)
465{
466 struct netxen_adapter *adapter;
467 struct netxen_port *port;
468 struct netxen_rx_buffer *buffer;
469 struct netxen_recv_context *recv_ctx;
470 struct netxen_rcv_desc_ctx *rcv_desc;
471 int i;
472 int ctxid, ring;
473
474 adapter = pci_get_drvdata(pdev);
475 if (adapter == NULL)
476 return;
477
478 netxen_nic_stop_all_ports(adapter);
479 /* leave the hw in the same state as reboot */
480 netxen_pinit_from_rom(adapter, 0);
481 udelay(500);
482 netxen_load_firmware(adapter);
483
484 if ((adapter->flags & NETXEN_NIC_MSI_ENABLED))
485 netxen_nic_disable_int(adapter);
486
487 udelay(500); /* Delay for a while to drain the DMA engines */
488 for (i = 0; i < adapter->port_count; i++) {
489 port = adapter->port[i];
490 if ((port) && (port->netdev)) {
491 unregister_netdev(port->netdev);
492 free_netdev(port->netdev);
493 }
494 }
495
496 if ((adapter->flags & NETXEN_NIC_MSI_ENABLED))
497 pci_disable_msi(pdev);
498 pci_set_drvdata(pdev, NULL);
499 if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC)
500 netxen_free_hw_resources(adapter);
501
502 iounmap(adapter->ahw.pci_base0);
503 iounmap(adapter->ahw.pci_base1);
504 iounmap(adapter->ahw.pci_base2);
505
506 pci_release_regions(pdev);
507 pci_disable_device(pdev);
508
509 for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
510 recv_ctx = &adapter->recv_ctx[ctxid];
511 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
512 rcv_desc = &recv_ctx->rcv_desc[ring];
513 for (i = 0; i < rcv_desc->max_rx_desc_count; ++i) {
514 buffer = &(rcv_desc->rx_buf_arr[i]);
515 if (buffer->state == NETXEN_BUFFER_FREE)
516 continue;
517 pci_unmap_single(pdev, buffer->dma,
518 rcv_desc->dma_size,
519 PCI_DMA_FROMDEVICE);
520 if (buffer->skb != NULL)
521 dev_kfree_skb_any(buffer->skb);
522 }
523 vfree(rcv_desc->rx_buf_arr);
524 }
525 }
526
527 vfree(adapter->cmd_buf_arr);
528 kfree(adapter->ops);
529 kfree(adapter);
530}
531
532/*
533 * Called when a network interface is made active
534 * @returns 0 on success, negative value on failure
535 */
536static int netxen_nic_open(struct net_device *netdev)
537{
538 struct netxen_port *port = netdev_priv(netdev);
539 struct netxen_adapter *adapter = port->adapter;
540 int err = 0;
541 int ctx, ring;
542
543 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) {
544 err = netxen_init_firmware(adapter);
545 if (err != 0) {
546 printk(KERN_ERR "Failed to init firmware\n");
547 return -EIO;
548 }
549 netxen_nic_flash_print(adapter);
550
551 /* setup all the resources for the Phantom... */
552 /* this include the descriptors for rcv, tx, and status */
553 netxen_nic_clear_stats(adapter);
554 err = netxen_nic_hw_resources(adapter);
555 if (err) {
556 printk(KERN_ERR "Error in setting hw resources:%d\n",
557 err);
558 return err;
559 }
560 if (adapter->ops->init_port
561 && adapter->ops->init_port(adapter, port->portnum) != 0) {
562 printk(KERN_ERR "%s: Failed to initialize port %d\n",
563 netxen_nic_driver_name, port->portnum);
564 netxen_free_hw_resources(adapter);
565 return -EIO;
566 }
567 if (adapter->ops->init_niu)
568 adapter->ops->init_niu(adapter);
569 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
570 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++)
571 netxen_post_rx_buffers(adapter, ctx, ring);
572 }
573 adapter->is_up = NETXEN_ADAPTER_UP_MAGIC;
574 }
575 adapter->active_ports++;
576 if (adapter->active_ports == 1) {
577 err = request_irq(adapter->ahw.pdev->irq, &netxen_intr,
578 SA_SHIRQ | SA_SAMPLE_RANDOM, netdev->name,
579 adapter);
580 if (err) {
581 printk(KERN_ERR "request_irq failed with: %d\n", err);
582 adapter->active_ports--;
583 return err;
584 }
585 adapter->irq = adapter->ahw.pdev->irq;
586 if (!adapter->driver_mismatch)
587 mod_timer(&adapter->watchdog_timer, jiffies);
588
589 netxen_nic_enable_int(adapter);
590 }
591
592 /* Done here again so that even if phantom sw overwrote it,
593 * we set it */
594 if (adapter->ops->macaddr_set)
595 adapter->ops->macaddr_set(port, netdev->dev_addr);
596 netxen_nic_set_link_parameters(port);
597
598 netxen_nic_set_multi(netdev);
599 if (!adapter->driver_mismatch)
600 netif_start_queue(netdev);
601
602 return 0;
603}
604
605/*
606 * netxen_nic_close - Disables a network interface entry point
607 */
608static int netxen_nic_close(struct net_device *netdev)
609{
610 struct netxen_port *port = netdev_priv(netdev);
611 struct netxen_adapter *adapter = port->adapter;
612 int i, j;
613 struct netxen_cmd_buffer *cmd_buff;
614 struct netxen_skb_frag *buffrag;
615
616 netif_carrier_off(netdev);
617 netif_stop_queue(netdev);
618
619 adapter->active_ports--;
620
621 if (!adapter->active_ports) {
622 netxen_nic_disable_int(adapter);
623 if (adapter->irq)
624 free_irq(adapter->irq, adapter);
625 cmd_buff = adapter->cmd_buf_arr;
626 for (i = 0; i < adapter->max_tx_desc_count; i++) {
627 buffrag = cmd_buff->frag_array;
628 if (buffrag->dma) {
629 pci_unmap_single(port->pdev, buffrag->dma,
630 buffrag->length,
631 PCI_DMA_TODEVICE);
632 buffrag->dma = (u64) NULL;
633 }
634 for (j = 0; j < cmd_buff->frag_count; j++) {
635 buffrag++;
636 if (buffrag->dma) {
637 pci_unmap_page(port->pdev,
638 buffrag->dma,
639 buffrag->length,
640 PCI_DMA_TODEVICE);
641 buffrag->dma = (u64) NULL;
642 }
643 }
644 /* Free the skb we received in netxen_nic_xmit_frame */
645 if (cmd_buff->skb) {
646 dev_kfree_skb_any(cmd_buff->skb);
647 cmd_buff->skb = NULL;
648 }
649 cmd_buff++;
650 }
651 del_timer_sync(&adapter->watchdog_timer);
652 }
653
654 return 0;
655}
656
657static int netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
658{
659 struct netxen_port *port = netdev_priv(netdev);
660 struct netxen_adapter *adapter = port->adapter;
661 struct netxen_hardware_context *hw = &adapter->ahw;
662 unsigned int first_seg_len = skb->len - skb->data_len;
663 struct netxen_skb_frag *buffrag;
664 unsigned int i;
665
666 u32 producer = 0;
667 u32 saved_producer = 0;
668 struct cmd_desc_type0 *hwdesc;
669 int k;
670 struct netxen_cmd_buffer *pbuf = NULL;
671 unsigned int tries = 0;
672 static int dropped_packet = 0;
673 int frag_count;
674 u32 local_producer = 0;
675 u32 max_tx_desc_count = 0;
676 u32 last_cmd_consumer = 0;
677 int no_of_desc;
678
679 port->stats.xmitcalled++;
680 frag_count = skb_shinfo(skb)->nr_frags + 1;
681
682 if (unlikely(skb->len <= 0)) {
683 dev_kfree_skb_any(skb);
684 port->stats.badskblen++;
685 return NETDEV_TX_OK;
686 }
687
688 if (frag_count > MAX_BUFFERS_PER_CMD) {
689 printk("%s: %s netxen_nic_xmit_frame: frag_count (%d)"
690 "too large, can handle only %d frags\n",
691 netxen_nic_driver_name, netdev->name,
692 frag_count, MAX_BUFFERS_PER_CMD);
693 port->stats.txdropped++;
694 if ((++dropped_packet & 0xff) == 0xff)
695 printk("%s: %s droppped packets = %d\n",
696 netxen_nic_driver_name, netdev->name,
697 dropped_packet);
698
699 return NETDEV_TX_OK;
700 }
701
702 /*
703 * Everything is set up. Now, we just need to transmit it out.
704 * Note that we have to copy the contents of buffer over to
705 * right place. Later on, this can be optimized out by de-coupling the
706 * producer index from the buffer index.
707 */
708 retry_getting_window:
709 spin_lock_bh(&adapter->tx_lock);
710 if (adapter->total_threads == MAX_XMIT_PRODUCERS) {
711 spin_unlock_bh(&adapter->tx_lock);
712 /*
713 * Yield CPU
714 */
715 if (!in_atomic())
716 schedule();
717 else {
718 for (i = 0; i < 20; i++)
719 cpu_relax(); /*This a nop instr on i386 */
720 }
721 goto retry_getting_window;
722 }
723 local_producer = adapter->cmd_producer;
724 /* There 4 fragments per descriptor */
725 no_of_desc = (frag_count + 3) >> 2;
726 if (netdev->features & NETIF_F_TSO) {
727 if (skb_shinfo(skb)->gso_size > 0) {
728
729 no_of_desc++;
730 if (((skb->nh.iph)->ihl * sizeof(u32)) +
731 ((skb->h.th)->doff * sizeof(u32)) +
732 sizeof(struct ethhdr) >
733 (sizeof(struct cmd_desc_type0) - NET_IP_ALIGN)) {
734 no_of_desc++;
735 }
736 }
737 }
738 k = adapter->cmd_producer;
739 max_tx_desc_count = adapter->max_tx_desc_count;
740 last_cmd_consumer = adapter->last_cmd_consumer;
741 if ((k + no_of_desc) >=
742 ((last_cmd_consumer <= k) ? last_cmd_consumer + max_tx_desc_count :
743 last_cmd_consumer)) {
744 spin_unlock_bh(&adapter->tx_lock);
745 if (tries == 0) {
746 local_bh_disable();
747 netxen_process_cmd_ring((unsigned long)adapter);
748 local_bh_enable();
749 ++tries;
750 goto retry_getting_window;
751 } else {
752 port->stats.nocmddescriptor++;
753 DPRINTK(ERR, "No command descriptors available,"
754 " producer = %d, consumer = %d count=%llu,"
755 " dropping packet\n", producer,
756 adapter->last_cmd_consumer,
757 port->stats.nocmddescriptor);
758
759 spin_lock_bh(&adapter->tx_lock);
760 netif_stop_queue(netdev);
761 port->flags |= NETXEN_NETDEV_STATUS;
762 spin_unlock_bh(&adapter->tx_lock);
763 return NETDEV_TX_BUSY;
764 }
765 }
766 k = get_index_range(k, max_tx_desc_count, no_of_desc);
767 adapter->cmd_producer = k;
768 adapter->total_threads++;
769 adapter->num_threads++;
770
771 spin_unlock_bh(&adapter->tx_lock);
772 /* Copy the descriptors into the hardware */
773 producer = local_producer;
774 saved_producer = producer;
775 hwdesc = &hw->cmd_desc_head[producer];
776 memset(hwdesc, 0, sizeof(struct cmd_desc_type0));
777 /* Take skb->data itself */
778 pbuf = &adapter->cmd_buf_arr[producer];
779 if ((netdev->features & NETIF_F_TSO) && skb_shinfo(skb)->gso_size > 0) {
780 pbuf->mss = skb_shinfo(skb)->gso_size;
781 hwdesc->mss = skb_shinfo(skb)->gso_size;
782 } else {
783 pbuf->mss = 0;
784 hwdesc->mss = 0;
785 }
786 pbuf->no_of_descriptors = no_of_desc;
787 pbuf->total_length = skb->len;
788 pbuf->skb = skb;
789 pbuf->cmd = TX_ETHER_PKT;
790 pbuf->frag_count = frag_count;
791 pbuf->port = port->portnum;
792 buffrag = &pbuf->frag_array[0];
793 buffrag->dma = pci_map_single(port->pdev, skb->data, first_seg_len,
794 PCI_DMA_TODEVICE);
795 buffrag->length = first_seg_len;
796 CMD_DESC_TOTAL_LENGTH_WRT(hwdesc, skb->len);
797 hwdesc->num_of_buffers = frag_count;
798 hwdesc->opcode = TX_ETHER_PKT;
799
800 CMD_DESC_PORT_WRT(hwdesc, port->portnum);
801 hwdesc->buffer1_length = cpu_to_le16(first_seg_len);
802 hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma);
803
804 for (i = 1, k = 1; i < frag_count; i++, k++) {
805 struct skb_frag_struct *frag;
806 int len, temp_len;
807 unsigned long offset;
808 dma_addr_t temp_dma;
809
810 /* move to next desc. if there is a need */
811 if ((i & 0x3) == 0) {
812 k = 0;
813 producer = get_next_index(producer,
814 adapter->max_tx_desc_count);
815 hwdesc = &hw->cmd_desc_head[producer];
816 memset(hwdesc, 0, sizeof(struct cmd_desc_type0));
817 }
818 frag = &skb_shinfo(skb)->frags[i - 1];
819 len = frag->size;
820 offset = frag->page_offset;
821
822 temp_len = len;
823 temp_dma = pci_map_page(port->pdev, frag->page, offset,
824 len, PCI_DMA_TODEVICE);
825
826 buffrag++;
827 buffrag->dma = temp_dma;
828 buffrag->length = temp_len;
829
830 DPRINTK(INFO, "for loop. i=%d k=%d\n", i, k);
831 switch (k) {
832 case 0:
833 hwdesc->buffer1_length = cpu_to_le16(temp_len);
834 hwdesc->addr_buffer1 = cpu_to_le64(temp_dma);
835 break;
836 case 1:
837 hwdesc->buffer2_length = cpu_to_le16(temp_len);
838 hwdesc->addr_buffer2 = cpu_to_le64(temp_dma);
839 break;
840 case 2:
841 hwdesc->buffer3_length = cpu_to_le16(temp_len);
842 hwdesc->addr_buffer3 = cpu_to_le64(temp_dma);
843 break;
844 case 3:
845 hwdesc->buffer4_length = temp_len;
846 hwdesc->addr_buffer4 = cpu_to_le64(temp_dma);
847 break;
848 }
849 frag++;
850 }
851 producer = get_next_index(producer, adapter->max_tx_desc_count);
852
853 /* might change opcode to TX_TCP_LSO */
854 netxen_tso_check(adapter, &hw->cmd_desc_head[saved_producer], skb);
855
856 /* For LSO, we need to copy the MAC/IP/TCP headers into
857 * the descriptor ring
858 */
859 if (hw->cmd_desc_head[saved_producer].opcode == TX_TCP_LSO) {
860 int hdr_len, first_hdr_len, more_hdr;
861 hdr_len = hw->cmd_desc_head[saved_producer].total_hdr_length;
862 if (hdr_len > (sizeof(struct cmd_desc_type0) - NET_IP_ALIGN)) {
863 first_hdr_len =
864 sizeof(struct cmd_desc_type0) - NET_IP_ALIGN;
865 more_hdr = 1;
866 } else {
867 first_hdr_len = hdr_len;
868 more_hdr = 0;
869 }
870 /* copy the MAC/IP/TCP headers to the cmd descriptor list */
871 hwdesc = &hw->cmd_desc_head[producer];
872
873 /* copy the first 64 bytes */
874 memcpy(((void *)hwdesc) + NET_IP_ALIGN,
875 (void *)(skb->data), first_hdr_len);
876 producer = get_next_index(producer, max_tx_desc_count);
877
878 if (more_hdr) {
879 hwdesc = &hw->cmd_desc_head[producer];
880 /* copy the next 64 bytes - should be enough except
881 * for pathological case
882 */
883 memcpy((void *)hwdesc, (void *)(skb->data) +
884 first_hdr_len, hdr_len - first_hdr_len);
885 producer = get_next_index(producer, max_tx_desc_count);
886 }
887 }
888 spin_lock_bh(&adapter->tx_lock);
889 port->stats.txbytes +=
890 CMD_DESC_TOTAL_LENGTH(&hw->cmd_desc_head[saved_producer]);
891 /* Code to update the adapter considering how many producer threads
892 are currently working */
893 if ((--adapter->num_threads) == 0) {
894 /* This is the last thread */
895 u32 crb_producer = adapter->cmd_producer;
896 writel(crb_producer,
897 NETXEN_CRB_NORMALIZE(adapter, CRB_CMD_PRODUCER_OFFSET));
898 wmb();
899 adapter->total_threads = 0;
900 } else {
901 u32 crb_producer = 0;
902 crb_producer =
903 readl(NETXEN_CRB_NORMALIZE
904 (adapter, CRB_CMD_PRODUCER_OFFSET));
905 if (crb_producer == local_producer) {
906 crb_producer = get_index_range(crb_producer,
907 max_tx_desc_count,
908 no_of_desc);
909 writel(crb_producer,
910 NETXEN_CRB_NORMALIZE(adapter,
911 CRB_CMD_PRODUCER_OFFSET));
912 wmb();
913 }
914 }
915
916 port->stats.xmitfinished++;
917 spin_unlock_bh(&adapter->tx_lock);
918
919 netdev->trans_start = jiffies;
920
921 DPRINTK(INFO, "wrote CMD producer %x to phantom\n", producer);
922
923 DPRINTK(INFO, "Done. Send\n");
924 return NETDEV_TX_OK;
925}
926
927static void netxen_watchdog(unsigned long v)
928{
929 struct netxen_adapter *adapter = (struct netxen_adapter *)v;
930 schedule_work(&adapter->watchdog_task);
931}
932
933static void netxen_tx_timeout(struct net_device *netdev)
934{
935 struct netxen_port *port = (struct netxen_port *)netdev_priv(netdev);
936 struct netxen_adapter *adapter = port->adapter;
937
938 schedule_work(&adapter->tx_timeout_task);
939}
940
941static void netxen_tx_timeout_task(struct net_device *netdev)
942{
943 struct netxen_port *port = (struct netxen_port *)netdev_priv(netdev);
944 unsigned long flags;
945
946 printk(KERN_ERR "%s %s: transmit timeout, resetting.\n",
947 netxen_nic_driver_name, netdev->name);
948
949 spin_lock_irqsave(&port->adapter->lock, flags);
950 netxen_nic_close(netdev);
951 netxen_nic_open(netdev);
952 spin_unlock_irqrestore(&port->adapter->lock, flags);
953 netdev->trans_start = jiffies;
954 netif_wake_queue(netdev);
955}
956
957static int
958netxen_handle_int(struct netxen_adapter *adapter, struct net_device *netdev)
959{
960 u32 ret = 0;
961
962 DPRINTK(INFO, "Entered handle ISR\n");
963
964 adapter->stats.ints++;
965
966 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
967 int count = 0;
968 u32 mask;
969 netxen_nic_disable_int(adapter);
970 /* Window = 0 or 1 */
971 do {
972 writel(0xffffffff, PCI_OFFSET_SECOND_RANGE(adapter,
973 ISR_INT_TARGET_STATUS));
974 mask = readl(pci_base_offset(adapter, ISR_INT_VECTOR));
975 } while (((mask & 0x80) != 0) && (++count < 32));
976 if ((mask & 0x80) != 0)
977 printk("Could not disable interrupt completely\n");
978
979 }
980 adapter->stats.hostints++;
981
982 if (netxen_nic_rx_has_work(adapter) || netxen_nic_tx_has_work(adapter)) {
983 if (netif_rx_schedule_prep(netdev)) {
984 /*
985 * Interrupts are already disabled.
986 */
987 __netif_rx_schedule(netdev);
988 } else {
989 static unsigned int intcount = 0;
990 if ((++intcount & 0xfff) == 0xfff)
991 printk(KERN_ERR
992 "%s: %s interrupt %d while in poll\n",
993 netxen_nic_driver_name, netdev->name,
994 intcount);
995 }
996 ret = 1;
997 }
998
999 if (ret == 0) {
1000 netxen_nic_enable_int(adapter);
1001 }
1002
1003 return ret;
1004}
1005
1006/*
1007 * netxen_intr - Interrupt Handler
1008 * @irq: interrupt number
1009 * data points to adapter stucture (which may be handling more than 1 port
1010 */
1011irqreturn_t netxen_intr(int irq, void *data)
1012{
1013 struct netxen_adapter *adapter;
1014 struct netxen_port *port;
1015 struct net_device *netdev;
1016 int i;
1017
1018 if (unlikely(!irq)) {
1019 return IRQ_NONE; /* Not our interrupt */
1020 }
1021
1022 adapter = (struct netxen_adapter *)data;
1023 for (i = 0; i < adapter->ahw.max_ports; i++) {
1024 port = adapter->port[i];
1025 netdev = port->netdev;
1026
1027 /* process our status queue (for all 4 ports) */
1028 netxen_handle_int(adapter, netdev);
1029 }
1030
1031 return IRQ_HANDLED;
1032}
1033
1034static int netxen_nic_poll(struct net_device *netdev, int *budget)
1035{
1036 struct netxen_port *port = (struct netxen_port *)netdev_priv(netdev);
1037 struct netxen_adapter *adapter = port->adapter;
1038 int work_to_do = min(*budget, netdev->quota);
1039 int done = 1;
1040 int ctx;
1041 int this_work_done;
1042
1043 DPRINTK(INFO, "polling for %d descriptors\n", *budget);
1044 port->stats.polled++;
1045
1046 adapter->work_done = 0;
1047 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
1048 /*
1049 * Fairness issue. This will give undue weight to the
1050 * receive context 0.
1051 */
1052
1053 /*
1054 * To avoid starvation, we give each of our receivers,
1055 * a fraction of the quota. Sometimes, it might happen that we
1056 * have enough quota to process every packet, but since all the
1057 * packets are on one context, it gets only half of the quota,
1058 * and ends up not processing it.
1059 */
1060 this_work_done = netxen_process_rcv_ring(adapter, ctx,
1061 work_to_do /
1062 MAX_RCV_CTX);
1063 adapter->work_done += this_work_done;
1064 }
1065
1066 netdev->quota -= adapter->work_done;
1067 *budget -= adapter->work_done;
1068
1069 if (adapter->work_done >= work_to_do
1070 && netxen_nic_rx_has_work(adapter) != 0)
1071 done = 0;
1072
1073 netxen_process_cmd_ring((unsigned long)adapter);
1074
1075 DPRINTK(INFO, "new work_done: %d work_to_do: %d\n",
1076 adapter->work_done, work_to_do);
1077 if (done) {
1078 netif_rx_complete(netdev);
1079 netxen_nic_enable_int(adapter);
1080 }
1081
1082 return !done;
1083}
1084
1085#ifdef CONFIG_NET_POLL_CONTROLLER
1086static void netxen_nic_poll_controller(struct net_device *netdev)
1087{
1088 struct netxen_port *port = netdev_priv(netdev);
1089 struct netxen_adapter *adapter = port->adapter;
1090 disable_irq(adapter->irq);
1091 netxen_intr(adapter->irq, adapter);
1092 enable_irq(adapter->irq);
1093}
1094#endif
1095/*
1096 * netxen_nic_ioctl () We provide the tcl/phanmon support through these
1097 * ioctls.
1098 */
1099static int
1100netxen_nic_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1101{
1102 int err = 0;
1103 unsigned long nr_bytes = 0;
1104 struct netxen_port *port = netdev_priv(netdev);
1105 struct netxen_adapter *adapter = port->adapter;
1106 char dev_name[NETXEN_NIC_NAME_LEN];
1107
1108 DPRINTK(INFO, "doing ioctl for %s\n", netdev->name);
1109 switch (cmd) {
1110 case NETXEN_NIC_CMD:
1111 err = netxen_nic_do_ioctl(adapter, (void *)ifr->ifr_data, port);
1112 break;
1113
1114 case NETXEN_NIC_NAME:
1115 DPRINTK(INFO, "ioctl cmd for NetXen\n");
1116 if (ifr->ifr_data) {
1117 sprintf(dev_name, "%s-%d", NETXEN_NIC_NAME_RSP,
1118 port->portnum);
1119 nr_bytes = copy_to_user((char *)ifr->ifr_data, dev_name,
1120 NETXEN_NIC_NAME_LEN);
1121 if (nr_bytes)
1122 err = -EIO;
1123
1124 }
1125 break;
1126
1127 default:
1128 DPRINTK(INFO, "ioctl cmd %x not supported\n", cmd);
1129 err = -EOPNOTSUPP;
1130 break;
1131 }
1132
1133 return err;
1134}
1135
1136static struct pci_driver netxen_driver = {
1137 .name = netxen_nic_driver_name,
1138 .id_table = netxen_pci_tbl,
1139 .probe = netxen_nic_probe,
1140 .remove = __devexit_p(netxen_nic_remove)
1141};
1142
1143/* Driver Registration on NetXen card */
1144
1145static int __init netxen_init_module(void)
1146{
1147 return pci_module_init(&netxen_driver);
1148}
1149
1150module_init(netxen_init_module);
1151
1152static void __exit netxen_exit_module(void)
1153{
1154 /*
1155 * Wait for some time to allow the dma to drain, if any.
1156 */
1157 mdelay(5);
1158 pci_unregister_driver(&netxen_driver);
1159}
1160
1161module_exit(netxen_exit_module);
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c
new file mode 100644
index 000000000000..7950a04532e6
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_niu.c
@@ -0,0 +1,894 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Provides access to the Network Interface Unit h/w block.
31 *
32 */
33
34#include "netxen_nic.h"
35
36#define NETXEN_GB_MAC_SOFT_RESET 0x80000000
37#define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
38#define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
39#define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
40
41static long phy_lock_timeout = 100000000;
42
43static inline int phy_lock(void)
44{
45 int i;
46 int done = 0, timeout = 0;
47
48 while (!done) {
49 done = readl((void __iomem *)NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
50 if (done == 1)
51 break;
52 if (timeout >= phy_lock_timeout) {
53 return -1;
54 }
55 timeout++;
56 if (!in_atomic())
57 schedule();
58 else {
59 for (i = 0; i < 20; i++)
60 cpu_relax();
61 }
62 }
63
64 writel(NETXEN_PHY_LOCK_ID, (void __iomem *)PHY_LOCK_DRIVER);
65 return 0;
66}
67
68static inline int phy_unlock(void)
69{
70 readl((void __iomem *)NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK));
71 return 0;
72}
73
74/*
75 * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
76 * mii management interface.
77 *
78 * Note: The MII management interface goes through port 0.
79 * Individual phys are addressed as follows:
80 * @param phy [15:8] phy id
81 * @param reg [7:0] register number
82 *
83 * @returns 0 on success
84 * -1 on error
85 *
86 */
87int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy,
88 long reg, __le32 * readval)
89{
90 long timeout = 0;
91 long result = 0;
92 long restore = 0;
93 __le32 address;
94 __le32 command;
95 __le32 status;
96 __le32 mac_cfg0;
97
98 if (phy_lock() != 0) {
99 return -1;
100 }
101
102 /*
103 * MII mgmt all goes through port 0 MAC interface,
104 * so it cannot be in reset
105 */
106
107 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
108 &mac_cfg0, 4))
109 return -EIO;
110 if (netxen_gb_get_soft_reset(mac_cfg0)) {
111 __le32 temp;
112 temp = 0;
113 netxen_gb_tx_reset_pb(temp);
114 netxen_gb_rx_reset_pb(temp);
115 netxen_gb_tx_reset_mac(temp);
116 netxen_gb_rx_reset_mac(temp);
117 if (netxen_nic_hw_write_wx(adapter,
118 NETXEN_NIU_GB_MAC_CONFIG_0(0),
119 &temp, 4))
120 return -EIO;
121 restore = 1;
122 }
123
124 address = 0;
125 netxen_gb_mii_mgmt_reg_addr(address, reg);
126 netxen_gb_mii_mgmt_phy_addr(address, phy);
127 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
128 &address, 4))
129 return -EIO;
130 command = 0; /* turn off any prior activity */
131 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
132 &command, 4))
133 return -EIO;
134 /* send read command */
135 netxen_gb_mii_mgmt_set_read_cycle(command);
136 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
137 &command, 4))
138 return -EIO;
139
140 status = 0;
141 do {
142 if (netxen_nic_hw_read_wx(adapter,
143 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
144 &status, 4))
145 return -EIO;
146 timeout++;
147 } while ((netxen_get_gb_mii_mgmt_busy(status)
148 || netxen_get_gb_mii_mgmt_notvalid(status))
149 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
150
151 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
152 if (netxen_nic_hw_read_wx(adapter,
153 NETXEN_NIU_GB_MII_MGMT_STATUS(0),
154 readval, 4))
155 return -EIO;
156 result = 0;
157 } else
158 result = -1;
159
160 if (restore)
161 if (netxen_nic_hw_write_wx(adapter,
162 NETXEN_NIU_GB_MAC_CONFIG_0(0),
163 &mac_cfg0, 4))
164 return -EIO;
165 phy_unlock();
166 return result;
167}
168
169/*
170 * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
171 * mii management interface.
172 *
173 * Note: The MII management interface goes through port 0.
174 * Individual phys are addressed as follows:
175 * @param phy [15:8] phy id
176 * @param reg [7:0] register number
177 *
178 * @returns 0 on success
179 * -1 on error
180 *
181 */
182int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
183 long phy, long reg, __le32 val)
184{
185 long timeout = 0;
186 long result = 0;
187 long restore = 0;
188 __le32 address;
189 __le32 command;
190 __le32 status;
191 __le32 mac_cfg0;
192
193 /*
194 * MII mgmt all goes through port 0 MAC interface, so it
195 * cannot be in reset
196 */
197
198 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
199 &mac_cfg0, 4))
200 return -EIO;
201 if (netxen_gb_get_soft_reset(mac_cfg0)) {
202 __le32 temp;
203 temp = 0;
204 netxen_gb_tx_reset_pb(temp);
205 netxen_gb_rx_reset_pb(temp);
206 netxen_gb_tx_reset_mac(temp);
207 netxen_gb_rx_reset_mac(temp);
208
209 if (netxen_nic_hw_write_wx(adapter,
210 NETXEN_NIU_GB_MAC_CONFIG_0(0),
211 &temp, 4))
212 return -EIO;
213 restore = 1;
214 }
215
216 command = 0; /* turn off any prior activity */
217 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
218 &command, 4))
219 return -EIO;
220
221 address = 0;
222 netxen_gb_mii_mgmt_reg_addr(address, reg);
223 netxen_gb_mii_mgmt_phy_addr(address, phy);
224 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
225 &address, 4))
226 return -EIO;
227
228 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
229 &val, 4))
230 return -EIO;
231
232 status = 0;
233 do {
234 if (netxen_nic_hw_read_wx(adapter,
235 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
236 &status, 4))
237 return -EIO;
238 timeout++;
239 } while ((netxen_get_gb_mii_mgmt_busy(status))
240 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
241
242 if (timeout < NETXEN_NIU_PHY_WAITMAX)
243 result = 0;
244 else
245 result = -EIO;
246
247 /* restore the state of port 0 MAC in case we tampered with it */
248 if (restore)
249 if (netxen_nic_hw_write_wx(adapter,
250 NETXEN_NIU_GB_MAC_CONFIG_0(0),
251 &mac_cfg0, 4))
252 return -EIO;
253
254 return result;
255}
256
257int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
258 int port)
259{
260 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f);
261 return 0;
262}
263
264int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
265 int port)
266{
267 int result = 0;
268 __le32 enable = 0;
269 netxen_set_phy_int_link_status_changed(enable);
270 netxen_set_phy_int_autoneg_completed(enable);
271 netxen_set_phy_int_speed_changed(enable);
272
273 if (0 !=
274 netxen_niu_gbe_phy_write(adapter, port,
275 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
276 enable))
277 result = -EIO;
278
279 return result;
280}
281
282int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
283 int port)
284{
285 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f);
286 return 0;
287}
288
289int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
290 int port)
291{
292 int result = 0;
293 if (0 !=
294 netxen_niu_gbe_phy_write(adapter, port,
295 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
296 result = -EIO;
297
298 return result;
299}
300
301int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
302 int port)
303{
304 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1);
305 return 0;
306}
307
308int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
309 int port)
310{
311 int result = 0;
312 if (0 !=
313 netxen_niu_gbe_phy_write(adapter, port,
314 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
315 -EIO))
316 result = -EIO;
317
318 return result;
319}
320
321/*
322 * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
323 *
324 */
325void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
326 int port, long enable)
327{
328 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
329 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
330 0x80000000);
331 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
332 0x0000f0025);
333 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
334 0xf1ff);
335 netxen_crb_writelit_adapter(adapter,
336 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
337 netxen_crb_writelit_adapter(adapter,
338 NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
339 netxen_crb_writelit_adapter(adapter,
340 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
341 netxen_crb_writelit_adapter(adapter,
342 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
343
344 if (enable) {
345 /*
346 * Do NOT enable flow control until a suitable solution for
347 * shutting down pause frames is found.
348 */
349 netxen_crb_writelit_adapter(adapter,
350 NETXEN_NIU_GB_MAC_CONFIG_0(port),
351 0x5);
352 }
353
354 if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
355 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
356 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
357 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
358}
359
360/*
361 * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
362 */
363void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
364 int port, long enable)
365{
366 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
367 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
368 0x80000000);
369 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
370 0x0000f0025);
371 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
372 0xf2ff);
373 netxen_crb_writelit_adapter(adapter,
374 NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
377 netxen_crb_writelit_adapter(adapter,
378 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
379 netxen_crb_writelit_adapter(adapter,
380 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
381
382 if (enable) {
383 /*
384 * Do NOT enable flow control until a suitable solution for
385 * shutting down pause frames is found.
386 */
387 netxen_crb_writelit_adapter(adapter,
388 NETXEN_NIU_GB_MAC_CONFIG_0(port),
389 0x5);
390 }
391
392 if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
393 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
394 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
395 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
396}
397
398int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
399{
400 int result = 0;
401 __le32 status;
402 if (adapter->ops->disable_phy_interrupts)
403 adapter->ops->disable_phy_interrupts(adapter, port);
404 mdelay(2);
405
406 if (0 ==
407 netxen_niu_gbe_phy_read(adapter, port,
408 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
409 (__le32 *) & status)) {
410 if (netxen_get_phy_link(status)) {
411 if (netxen_get_phy_speed(status) == 2) {
412 netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
413 } else if ((netxen_get_phy_speed(status) == 1)
414 || (netxen_get_phy_speed(status) == 0)) {
415 netxen_niu_gbe_set_mii_mode(adapter, port, 1);
416 } else {
417 result = -1;
418 }
419
420 } else {
421 /*
422 * We don't have link. Cable must be unconnected.
423 * Enable phy interrupts so we take action when
424 * plugged in.
425 */
426
427 netxen_crb_writelit_adapter(adapter,
428 NETXEN_NIU_GB_MAC_CONFIG_0
429 (port),
430 NETXEN_GB_MAC_SOFT_RESET);
431 netxen_crb_writelit_adapter(adapter,
432 NETXEN_NIU_GB_MAC_CONFIG_0
433 (port),
434 NETXEN_GB_MAC_RESET_PROT_BLK
435 | NETXEN_GB_MAC_ENABLE_TX_RX
436 |
437 NETXEN_GB_MAC_PAUSED_FRMS);
438 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
439 printk(KERN_ERR PFX
440 "ERROR clearing PHY interrupts\n");
441 if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
442 printk(KERN_ERR PFX
443 "ERROR enabling PHY interrupts\n");
444 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
445 printk(KERN_ERR PFX
446 "ERROR clearing PHY interrupts\n");
447 result = -1;
448 }
449 } else {
450 result = -EIO;
451 }
452 return result;
453}
454
455int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
456{
457 long reg = 0, ret = 0;
458
459 if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
460 netxen_crb_writelit_adapter(adapter,
461 NETXEN_NIU_XG1_CONFIG_0, 0x5);
462 /* XXX hack for Mez cards: both ports in promisc mode */
463 netxen_nic_hw_read_wx(adapter,
464 NETXEN_NIU_XGE_CONFIG_1, &reg, 4);
465 reg = (reg | 0x2000UL);
466 netxen_crb_writelit_adapter(adapter,
467 NETXEN_NIU_XGE_CONFIG_1, reg);
468 reg = 0;
469 netxen_nic_hw_read_wx(adapter,
470 NETXEN_NIU_XG1_CONFIG_1, &reg, 4);
471 reg = (reg | 0x2000UL);
472 netxen_crb_writelit_adapter(adapter,
473 NETXEN_NIU_XG1_CONFIG_1, reg);
474 }
475
476 return ret;
477}
478
479/*
480 * netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts
481 * @param enable 0 means don't enable the port
482 * 1 means enable (or re-enable) the port
483 */
484int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter,
485 int port, long enable)
486{
487 int result = 0;
488 __le32 int_src;
489
490 printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d"
491 " (device enable = %d)\n", (int)port, (int)enable);
492
493 /*
494 * The read of the PHY INT status will clear the pending
495 * interrupt status
496 */
497 if (netxen_niu_gbe_phy_read(adapter, port,
498 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
499 &int_src) != 0)
500 result = -EINVAL;
501 else {
502 printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src);
503 if (netxen_get_phy_int_jabber(int_src))
504 printk(KERN_INFO PFX "jabber Interrupt ");
505 if (netxen_get_phy_int_polarity_changed(int_src))
506 printk(KERN_INFO PFX "polarity changed ");
507 if (netxen_get_phy_int_energy_detect(int_src))
508 printk(KERN_INFO PFX "energy detect \n");
509 if (netxen_get_phy_int_downshift(int_src))
510 printk(KERN_INFO PFX "downshift \n");
511 if (netxen_get_phy_int_mdi_xover_changed(int_src))
512 printk(KERN_INFO PFX "mdi_xover_changed ");
513 if (netxen_get_phy_int_fifo_over_underflow(int_src))
514 printk(KERN_INFO PFX "fifo_over_underflow ");
515 if (netxen_get_phy_int_false_carrier(int_src))
516 printk(KERN_INFO PFX "false_carrier ");
517 if (netxen_get_phy_int_symbol_error(int_src))
518 printk(KERN_INFO PFX "symbol_error ");
519 if (netxen_get_phy_int_autoneg_completed(int_src))
520 printk(KERN_INFO PFX "autoneg_completed ");
521 if (netxen_get_phy_int_page_received(int_src))
522 printk(KERN_INFO PFX "page_received ");
523 if (netxen_get_phy_int_duplex_changed(int_src))
524 printk(KERN_INFO PFX "duplex_changed ");
525 if (netxen_get_phy_int_autoneg_error(int_src))
526 printk(KERN_INFO PFX "autoneg_error ");
527 if ((netxen_get_phy_int_speed_changed(int_src))
528 || (netxen_get_phy_int_link_status_changed(int_src))) {
529 __le32 status;
530
531 printk(KERN_INFO PFX
532 "speed_changed or link status changed");
533 if (netxen_niu_gbe_phy_read
534 (adapter, port,
535 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
536 &status) == 0) {
537 if (netxen_get_phy_speed(status) == 2) {
538 printk
539 (KERN_INFO PFX "Link speed changed"
540 " to 1000 Mbps\n");
541 netxen_niu_gbe_set_gmii_mode(adapter,
542 port,
543 enable);
544 } else if (netxen_get_phy_speed(status) == 1) {
545 printk
546 (KERN_INFO PFX "Link speed changed"
547 " to 100 Mbps\n");
548 netxen_niu_gbe_set_mii_mode(adapter,
549 port,
550 enable);
551 } else if (netxen_get_phy_speed(status) == 0) {
552 printk
553 (KERN_INFO PFX "Link speed changed"
554 " to 10 Mbps\n");
555 netxen_niu_gbe_set_mii_mode(adapter,
556 port,
557 enable);
558 } else {
559 printk(KERN_ERR PFX "ERROR reading"
560 "PHY status. Illegal speed.\n");
561 result = -1;
562 }
563 } else {
564 printk(KERN_ERR PFX
565 "ERROR reading PHY status.\n");
566 result = -1;
567 }
568
569 }
570 printk(KERN_INFO "\n");
571 }
572 return result;
573}
574
575/*
576 * Return the current station MAC address.
577 * Note that the passed-in value must already be in network byte order.
578 */
579int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
580 int phy, netxen_ethernet_macaddr_t * addr)
581{
582 u64 result = 0;
583 __le32 stationhigh;
584 __le32 stationlow;
585
586 if (addr == NULL)
587 return -EINVAL;
588 if ((phy < 0) || (phy > 3))
589 return -EINVAL;
590
591 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
592 &stationhigh, 4))
593 return -EIO;
594 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
595 &stationlow, 4))
596 return -EIO;
597
598 result = (u64) netxen_gb_get_stationaddress_low(stationlow);
599 result |= (u64) stationhigh << 16;
600 memcpy(*addr, &result, sizeof(netxen_ethernet_macaddr_t));
601
602 return 0;
603}
604
605/*
606 * Set the station MAC address.
607 * Note that the passed-in value must already be in network byte order.
608 */
609int netxen_niu_macaddr_set(struct netxen_port *port,
610 netxen_ethernet_macaddr_t addr)
611{
612 __le32 temp = 0;
613 struct netxen_adapter *adapter = port->adapter;
614 int phy = port->portnum;
615 unsigned char mac_addr[MAX_ADDR_LEN];
616 int i;
617
618 for (i = 0; i < 10; i++) {
619 memcpy(&temp, addr, 2);
620 temp <<= 16;
621 if (netxen_nic_hw_write_wx
622 (adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), &temp, 4))
623 return -EIO;
624
625 temp = 0;
626
627 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
628 if (netxen_nic_hw_write_wx
629 (adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), &temp, 4))
630 return -2;
631
632 netxen_niu_macaddr_get(adapter, phy,
633 (netxen_ethernet_macaddr_t *) mac_addr);
634 if (memcmp(mac_addr, addr, MAX_ADDR_LEN == 0))
635 break;
636 }
637
638 if (i == 10) {
639 printk(KERN_ERR "%s: cannot set Mac addr for %s\n",
640 netxen_nic_driver_name, port->netdev->name);
641 printk(KERN_ERR "MAC address set: "
642 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
643 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
644
645 printk(KERN_ERR "MAC address get: "
646 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
647 mac_addr[0],
648 mac_addr[1],
649 mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
650 }
651 return 0;
652}
653
654/* Enable a GbE interface */
655int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
656 int port, netxen_niu_gbe_ifmode_t mode)
657{
658 __le32 mac_cfg0;
659 __le32 mac_cfg1;
660 __le32 mii_cfg;
661
662 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
663 return -EINVAL;
664
665 mac_cfg0 = 0;
666 netxen_gb_soft_reset(mac_cfg0);
667 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
668 &mac_cfg0, 4))
669 return -EIO;
670 mac_cfg0 = 0;
671 netxen_gb_enable_tx(mac_cfg0);
672 netxen_gb_enable_rx(mac_cfg0);
673 netxen_gb_unset_rx_flowctl(mac_cfg0);
674 netxen_gb_tx_reset_pb(mac_cfg0);
675 netxen_gb_rx_reset_pb(mac_cfg0);
676 netxen_gb_tx_reset_mac(mac_cfg0);
677 netxen_gb_rx_reset_mac(mac_cfg0);
678
679 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
680 &mac_cfg0, 4))
681 return -EIO;
682 mac_cfg1 = 0;
683 netxen_gb_set_preamblelen(mac_cfg1, 0xf);
684 netxen_gb_set_duplex(mac_cfg1);
685 netxen_gb_set_crc_enable(mac_cfg1);
686 netxen_gb_set_padshort(mac_cfg1);
687 netxen_gb_set_checklength(mac_cfg1);
688 netxen_gb_set_hugeframes(mac_cfg1);
689
690 if (mode == NETXEN_NIU_10_100_MB) {
691 netxen_gb_set_intfmode(mac_cfg1, 1);
692 if (netxen_nic_hw_write_wx(adapter,
693 NETXEN_NIU_GB_MAC_CONFIG_1(port),
694 &mac_cfg1, 4))
695 return -EIO;
696
697 /* set mii mode */
698 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
699 (port << 3), 0);
700 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
701 (port << 3), 1);
702
703 } else if (mode == NETXEN_NIU_1000_MB) {
704 netxen_gb_set_intfmode(mac_cfg1, 2);
705 if (netxen_nic_hw_write_wx(adapter,
706 NETXEN_NIU_GB_MAC_CONFIG_1(port),
707 &mac_cfg1, 4))
708 return -EIO;
709 /* set gmii mode */
710 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
711 (port << 3), 0);
712 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
713 (port << 3), 1);
714 }
715 mii_cfg = 0;
716 netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
717 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
718 &mii_cfg, 4))
719 return -EIO;
720 mac_cfg0 = 0;
721 netxen_gb_enable_tx(mac_cfg0);
722 netxen_gb_enable_rx(mac_cfg0);
723 netxen_gb_unset_rx_flowctl(mac_cfg0);
724 netxen_gb_unset_tx_flowctl(mac_cfg0);
725
726 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
727 &mac_cfg0, 4))
728 return -EIO;
729 return 0;
730}
731
732/* Disable a GbE interface */
733int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port)
734{
735 __le32 mac_cfg0;
736
737 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
738 return -EINVAL;
739
740 mac_cfg0 = 0;
741 netxen_gb_soft_reset(mac_cfg0);
742 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
743 &mac_cfg0, 4))
744 return -EIO;
745 return 0;
746}
747
748/* Disable an XG interface */
749int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port)
750{
751 __le32 mac_cfg;
752
753 if (port != 0)
754 return -EINVAL;
755
756 mac_cfg = 0;
757 netxen_xg_soft_reset(mac_cfg);
758 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_CONFIG_0,
759 &mac_cfg, 4))
760 return -EIO;
761 return 0;
762}
763
764/* Set promiscuous mode for a GbE interface */
765int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port,
766 netxen_niu_prom_mode_t mode)
767{
768 __le32 reg;
769
770 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
771 return -EINVAL;
772
773 /* save previous contents */
774 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
775 &reg, 4))
776 return -EIO;
777 if (mode == NETXEN_NIU_PROMISC_MODE) {
778 switch (port) {
779 case 0:
780 netxen_clear_gb_drop_gb0(reg);
781 break;
782 case 1:
783 netxen_clear_gb_drop_gb1(reg);
784 break;
785 case 2:
786 netxen_clear_gb_drop_gb2(reg);
787 break;
788 case 3:
789 netxen_clear_gb_drop_gb3(reg);
790 break;
791 default:
792 return -EIO;
793 }
794 } else {
795 switch (port) {
796 case 0:
797 netxen_set_gb_drop_gb0(reg);
798 break;
799 case 1:
800 netxen_set_gb_drop_gb1(reg);
801 break;
802 case 2:
803 netxen_set_gb_drop_gb2(reg);
804 break;
805 case 3:
806 netxen_set_gb_drop_gb3(reg);
807 break;
808 default:
809 return -EIO;
810 }
811 }
812 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
813 &reg, 4))
814 return -EIO;
815 return 0;
816}
817
818/*
819 * Set the MAC address for an XG port
820 * Note that the passed-in value must already be in network byte order.
821 */
822int netxen_niu_xg_macaddr_set(struct netxen_port *port,
823 netxen_ethernet_macaddr_t addr)
824{
825 __le32 temp = 0;
826 struct netxen_adapter *adapter = port->adapter;
827
828 memcpy(&temp, addr, 2);
829 temp = cpu_to_le32(temp);
830 temp <<= 16;
831 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
832 &temp, 4))
833 return -EIO;
834
835 temp = 0;
836
837 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
838 temp = cpu_to_le32(temp);
839 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
840 &temp, 4))
841 return -EIO;
842
843 return 0;
844}
845
846/*
847 * Return the current station MAC address.
848 * Note that the passed-in value must already be in network byte order.
849 */
850int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int phy,
851 netxen_ethernet_macaddr_t * addr)
852{
853 __le32 stationhigh;
854 __le32 stationlow;
855 u64 result;
856
857 if (addr == NULL)
858 return -EINVAL;
859 if (phy != 0)
860 return -EINVAL;
861
862 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
863 &stationhigh, 4))
864 return -EIO;
865 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
866 &stationlow, 4))
867 return -EIO;
868
869 result = ((u64) stationlow) >> 16;
870 result |= (u64) stationhigh << 16;
871 memcpy(*addr, &result, sizeof(netxen_ethernet_macaddr_t));
872
873 return 0;
874}
875
876int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
877 int port, netxen_niu_prom_mode_t mode)
878{
879 __le32 reg;
880
881 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
882 return -EINVAL;
883
884 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_CONFIG_1, &reg, 4))
885 return -EIO;
886 if (mode == NETXEN_NIU_PROMISC_MODE)
887 reg = (reg | 0x2000UL);
888 else
889 reg = (reg & ~0x2000UL);
890
891 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_XGE_CONFIG_1, reg);
892
893 return 0;
894}
diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h
new file mode 100644
index 000000000000..8181d436783f
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_phan_reg.h
@@ -0,0 +1,215 @@
1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30#ifndef __NIC_PHAN_REG_H_
31#define __NIC_PHAN_REG_H_
32
33/*
34 * CRB Registers or queue message done only at initialization time.
35 */
36
37/*
38 * The following 2 are the base adresses for the CRB registers and their
39 * offsets will be added to get addresses for the index addresses.
40 */
41#define NIC_CRB_BASE_PORT1 NETXEN_CAM_RAM(0x200)
42#define NIC_CRB_BASE_PORT2 NETXEN_CAM_RAM(0x250)
43
44#define NETXEN_NIC_REG(X) (NIC_CRB_BASE_PORT1+(X))
45
46/*
47 * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
48 * which can be read by the Phantom host to get producer/consumer indexes from
49 * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
50 * registers will be used for the addresses of the ring's shared memory
51 * on the Phantom.
52 */
53
54#define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00)
55#define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04)
56
57/* point to the indexes */
58#define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08)
59#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c)
60
61#define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10)
62#define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14)
63
64/* address of command descriptors in the host memory */
65#define CRB_HOST_CMD_ADDR_HI NETXEN_NIC_REG(0x30)
66#define CRB_HOST_CMD_ADDR_LO NETXEN_NIC_REG(0x34)
67
68/* The following 4 CRB registers are for doing performance coal */
69#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x38)
70#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x3c)
71#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x40)
72#define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x44)
73
74/* Needed by the host to find out the state of Phantom's initialization */
75#define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x4c)
76#define CRB_CMDPEG_STATE NETXEN_NIC_REG(0x50)
77#define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x54)
78
79/* Interrupt coalescing parameters */
80#define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x80)
81#define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x84)
82#define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x88)
83#define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x8c)
84#define CRB_RX_PKT_TIMER NETXEN_NIC_REG(0x90)
85#define CRB_TX_PKT_TIMER NETXEN_NIC_REG(0x94)
86#define CRB_RX_PKT_CNT NETXEN_NIC_REG(0x98)
87#define CRB_RX_TMR_CNT NETXEN_NIC_REG(0x9c)
88#define CRB_INT_THRESH NETXEN_NIC_REG(0xa4)
89
90/* Register for communicating XG link status */
91#define CRB_XG_STATE NETXEN_NIC_REG(0xa0)
92
93/* Register for communicating card temperature */
94/* Upper 16 bits are temperature value. Lower 16 bits are the state */
95#define CRB_TEMP_STATE NETXEN_NIC_REG(0xa8)
96#define nx_get_temp_val(x) ((x) >> 16)
97#define nx_get_temp_state(x) ((x) & 0xffff)
98#define nx_encode_temp(val, state) (((val) << 16) | (state))
99
100/* Debug registers for controlling NIC pkt gen agent */
101#define CRB_AGENT_GO NETXEN_NIC_REG(0xb0)
102#define CRB_AGENT_TX_SIZE NETXEN_NIC_REG(0xb4)
103#define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xb8)
104#define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xbc)
105#define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xc0)
106
107/* Debug registers for observing NIC performance */
108#define CRB_TX_STATE NETXEN_NIC_REG(0xd0)
109#define CRB_TX_COUNT NETXEN_NIC_REG(0xd4)
110#define CRB_RX_STATE NETXEN_NIC_REG(0xd8)
111
112/* CRB registers per Rcv Descriptor ring */
113struct netxen_rcv_desc_crb {
114 u32 crb_rcv_producer_offset __attribute__ ((aligned(512)));
115 u32 crb_rcv_consumer_offset;
116 u32 crb_globalrcv_ring;
117};
118
119/*
120 * CRB registers used by the receive peg logic. One instance of these
121 * needs to be instantiated per instance of the receive peg.
122 */
123
124struct netxen_recv_crb {
125 struct netxen_rcv_desc_crb rcv_desc_crb[NUM_RCV_DESC_RINGS];
126 u32 crb_rcvstatus_ring;
127 u32 crb_rcv_status_producer;
128 u32 crb_rcv_status_consumer;
129 u32 crb_rcvpeg_state;
130};
131
132#if defined(DEFINE_GLOBAL_RECV_CRB)
133struct netxen_recv_crb recv_crb_registers[] = {
134 /*
135 * Instance 0.
136 */
137 {
138 /* rcv_desc_crb: */
139 {
140 {
141 /* crb_rcv_producer_offset: */
142 NETXEN_NIC_REG(0x18),
143 /* crb_rcv_consumer_offset: */
144 NETXEN_NIC_REG(0x1c),
145 /* crb_gloablrcv_ring: */
146 NETXEN_NIC_REG(0x20),
147 },
148 /* Jumbo frames */
149 {
150 /* crb_rcv_producer_offset: */
151 NETXEN_NIC_REG(0x100),
152 /* crb_rcv_consumer_offset: */
153 NETXEN_NIC_REG(0x104),
154 /* crb_gloablrcv_ring: */
155 NETXEN_NIC_REG(0x108),
156 }
157 },
158 /* crb_rcvstatus_ring: */
159 NETXEN_NIC_REG(0x24),
160 /* crb_rcv_status_producer: */
161 NETXEN_NIC_REG(0x28),
162 /* crb_rcv_status_consumer: */
163 NETXEN_NIC_REG(0x2c),
164 /* crb_rcvpeg_state: */
165 NETXEN_NIC_REG(0x48),
166
167 },
168 /*
169 * Instance 1,
170 */
171 {
172 /* rcv_desc_crb: */
173 {
174 {
175 /* crb_rcv_producer_offset: */
176 NETXEN_NIC_REG(0x80),
177 /* crb_rcv_consumer_offset: */
178 NETXEN_NIC_REG(0x84),
179 /* crb_globalrcv_ring: */
180 NETXEN_NIC_REG(0x88),
181 },
182 /* Jumbo frames */
183 {
184 /* crb_rcv_producer_offset: */
185 NETXEN_NIC_REG(0x10C),
186 /* crb_rcv_consumer_offset: */
187 NETXEN_NIC_REG(0x110),
188 /* crb_globalrcv_ring: */
189 NETXEN_NIC_REG(0x114),
190 }
191 },
192 /* crb_rcvstatus_ring: */
193 NETXEN_NIC_REG(0x8c),
194 /* crb_rcv_status_producer: */
195 NETXEN_NIC_REG(0x90),
196 /* crb_rcv_status_consumer: */
197 NETXEN_NIC_REG(0x94),
198 /* crb_rcvpeg_state: */
199 NETXEN_NIC_REG(0x98),
200 },
201};
202#else
203extern struct netxen_recv_crb recv_crb_registers[];
204#endif /* DEFINE_GLOBAL_RECEIVE_CRB */
205
206/*
207 * Temperature control.
208 */
209enum {
210 NX_TEMP_NORMAL = 0x1, /* Normal operating range */
211 NX_TEMP_WARN, /* Sound alert, temperature getting high */
212 NX_TEMP_PANIC /* Fatal error, hardware has shut down. */
213};
214
215#endif /* __NIC_PHAN_REG_H_ */
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index 0c00d182e7fd..c51cc5d8789a 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1096,7 +1096,6 @@ static void ei_watchdog(u_long arg)
1096 1096
1097 /* Check for pending interrupt with expired latency timer: with 1097 /* Check for pending interrupt with expired latency timer: with
1098 this, we can limp along even if the interrupt is blocked */ 1098 this, we can limp along even if the interrupt is blocked */
1099 outb_p(E8390_NODMA+E8390_PAGE0, nic_base + E8390_CMD);
1100 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { 1099 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) {
1101 if (!info->fast_poll) 1100 if (!info->fast_poll)
1102 printk(KERN_INFO "%s: interrupt(s) dropped!\n", dev->name); 1101 printk(KERN_INFO "%s: interrupt(s) dropped!\n", dev->name);
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index b79ec0d7480f..f994f129f3d8 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -56,13 +56,19 @@ config SMSC_PHY
56 ---help--- 56 ---help---
57 Currently supports the LAN83C185 PHY 57 Currently supports the LAN83C185 PHY
58 58
59config BROADCOM_PHY
60 tristate "Drivers for Broadcom PHYs"
61 depends on PHYLIB
62 ---help---
63 Currently supports the BCM5411, BCM5421 and BCM5461 PHYs.
64
59config FIXED_PHY 65config FIXED_PHY
60 tristate "Drivers for PHY emulation on fixed speed/link" 66 tristate "Drivers for PHY emulation on fixed speed/link"
61 depends on PHYLIB 67 depends on PHYLIB
62 ---help--- 68 ---help---
63 Adds the driver to PHY layer to cover the boards that do not have any PHY bound, 69 Adds the driver to PHY layer to cover the boards that do not have any PHY bound,
64 but with the ability to manipulate with speed/link in software. The relavant MII 70 but with the ability to manipulate the speed/link in software. The relevant MII
65 speed/duplex parameters could be effectively handled in user-specified fuction. 71 speed/duplex parameters could be effectively handled in a user-specified function.
66 Currently tested with mpc866ads. 72 Currently tested with mpc866ads.
67 73
68config FIXED_MII_10_FDX 74config FIXED_MII_10_FDX
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 320f8323123f..bcd1efbd2a18 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_LXT_PHY) += lxt.o
10obj-$(CONFIG_QSEMI_PHY) += qsemi.o 10obj-$(CONFIG_QSEMI_PHY) += qsemi.o
11obj-$(CONFIG_SMSC_PHY) += smsc.o 11obj-$(CONFIG_SMSC_PHY) += smsc.o
12obj-$(CONFIG_VITESSE_PHY) += vitesse.o 12obj-$(CONFIG_VITESSE_PHY) += vitesse.o
13obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
13obj-$(CONFIG_FIXED_PHY) += fixed.o 14obj-$(CONFIG_FIXED_PHY) += fixed.o
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
new file mode 100644
index 000000000000..29666c85ed55
--- /dev/null
+++ b/drivers/net/phy/broadcom.c
@@ -0,0 +1,175 @@
1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/phy.h>
19
20#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
21#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
22#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
23
24#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
25#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
26
27#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
28#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
29#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
30#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
31#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
32#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
33#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
34#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
35#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
36#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
37#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
38#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
39#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
40#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
41#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
42#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
43#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
44
45MODULE_DESCRIPTION("Broadcom PHY driver");
46MODULE_AUTHOR("Maciej W. Rozycki");
47MODULE_LICENSE("GPL");
48
49static int bcm54xx_config_init(struct phy_device *phydev)
50{
51 int reg, err;
52
53 reg = phy_read(phydev, MII_BCM54XX_ECR);
54 if (reg < 0)
55 return reg;
56
57 /* Mask interrupts globally. */
58 reg |= MII_BCM54XX_ECR_IM;
59 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
60 if (err < 0)
61 return err;
62
63 /* Unmask events we are interested in. */
64 reg = ~(MII_BCM54XX_INT_DUPLEX |
65 MII_BCM54XX_INT_SPEED |
66 MII_BCM54XX_INT_LINK);
67 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
68 if (err < 0)
69 return err;
70 return 0;
71}
72
73static int bcm54xx_ack_interrupt(struct phy_device *phydev)
74{
75 int reg;
76
77 /* Clear pending interrupts. */
78 reg = phy_read(phydev, MII_BCM54XX_ISR);
79 if (reg < 0)
80 return reg;
81
82 return 0;
83}
84
85static int bcm54xx_config_intr(struct phy_device *phydev)
86{
87 int reg, err;
88
89 reg = phy_read(phydev, MII_BCM54XX_ECR);
90 if (reg < 0)
91 return reg;
92
93 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
94 reg &= ~MII_BCM54XX_ECR_IM;
95 else
96 reg |= MII_BCM54XX_ECR_IM;
97
98 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
99 return err;
100}
101
102static struct phy_driver bcm5411_driver = {
103 .phy_id = 0x00206070,
104 .phy_id_mask = 0xfffffff0,
105 .name = "Broadcom BCM5411",
106 .features = PHY_GBIT_FEATURES,
107 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
108 .config_init = bcm54xx_config_init,
109 .config_aneg = genphy_config_aneg,
110 .read_status = genphy_read_status,
111 .ack_interrupt = bcm54xx_ack_interrupt,
112 .config_intr = bcm54xx_config_intr,
113 .driver = { .owner = THIS_MODULE },
114};
115
116static struct phy_driver bcm5421_driver = {
117 .phy_id = 0x002060e0,
118 .phy_id_mask = 0xfffffff0,
119 .name = "Broadcom BCM5421",
120 .features = PHY_GBIT_FEATURES,
121 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
122 .config_init = bcm54xx_config_init,
123 .config_aneg = genphy_config_aneg,
124 .read_status = genphy_read_status,
125 .ack_interrupt = bcm54xx_ack_interrupt,
126 .config_intr = bcm54xx_config_intr,
127 .driver = { .owner = THIS_MODULE },
128};
129
130static struct phy_driver bcm5461_driver = {
131 .phy_id = 0x002060c0,
132 .phy_id_mask = 0xfffffff0,
133 .name = "Broadcom BCM5461",
134 .features = PHY_GBIT_FEATURES,
135 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
136 .config_init = bcm54xx_config_init,
137 .config_aneg = genphy_config_aneg,
138 .read_status = genphy_read_status,
139 .ack_interrupt = bcm54xx_ack_interrupt,
140 .config_intr = bcm54xx_config_intr,
141 .driver = { .owner = THIS_MODULE },
142};
143
144static int __init broadcom_init(void)
145{
146 int ret;
147
148 ret = phy_driver_register(&bcm5411_driver);
149 if (ret)
150 goto out_5411;
151 ret = phy_driver_register(&bcm5421_driver);
152 if (ret)
153 goto out_5421;
154 ret = phy_driver_register(&bcm5461_driver);
155 if (ret)
156 goto out_5461;
157 return ret;
158
159out_5461:
160 phy_driver_unregister(&bcm5421_driver);
161out_5421:
162 phy_driver_unregister(&bcm5411_driver);
163out_5411:
164 return ret;
165}
166
167static void __exit broadcom_exit(void)
168{
169 phy_driver_unregister(&bcm5461_driver);
170 phy_driver_unregister(&bcm5421_driver);
171 phy_driver_unregister(&bcm5411_driver);
172}
173
174module_init(broadcom_init);
175module_exit(broadcom_exit);
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index a443976d5dcf..4044bb1ada86 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -7,6 +7,7 @@
7 * Author: Andy Fleming 7 * Author: Andy Fleming
8 * 8 *
9 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2006 Maciej W. Rozycki
10 * 11 *
11 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -32,6 +33,8 @@
32#include <linux/mii.h> 33#include <linux/mii.h>
33#include <linux/ethtool.h> 34#include <linux/ethtool.h>
34#include <linux/phy.h> 35#include <linux/phy.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
35 38
36#include <asm/io.h> 39#include <asm/io.h>
37#include <asm/irq.h> 40#include <asm/irq.h>
@@ -484,6 +487,9 @@ static irqreturn_t phy_interrupt(int irq, void *phy_dat)
484{ 487{
485 struct phy_device *phydev = phy_dat; 488 struct phy_device *phydev = phy_dat;
486 489
490 if (PHY_HALTED == phydev->state)
491 return IRQ_NONE; /* It can't be ours. */
492
487 /* The MDIO bus is not allowed to be written in interrupt 493 /* The MDIO bus is not allowed to be written in interrupt
488 * context, so we need to disable the irq here. A work 494 * context, so we need to disable the irq here. A work
489 * queue will write the PHY to disable and clear the 495 * queue will write the PHY to disable and clear the
@@ -577,6 +583,13 @@ int phy_stop_interrupts(struct phy_device *phydev)
577 if (err) 583 if (err)
578 phy_error(phydev); 584 phy_error(phydev);
579 585
586 /*
587 * Finish any pending work; we might have been scheduled
588 * to be called from keventd ourselves, though.
589 */
590 if (!current_is_keventd())
591 flush_scheduled_work();
592
580 free_irq(phydev->irq, phydev); 593 free_irq(phydev->irq, phydev);
581 594
582 return err; 595 return err;
@@ -604,7 +617,8 @@ static void phy_change(struct work_struct *work)
604 enable_irq(phydev->irq); 617 enable_irq(phydev->irq);
605 618
606 /* Reenable interrupts */ 619 /* Reenable interrupts */
607 err = phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED); 620 if (PHY_HALTED != phydev->state)
621 err = phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED);
608 622
609 if (err) 623 if (err)
610 goto irq_enable_err; 624 goto irq_enable_err;
@@ -625,18 +639,24 @@ void phy_stop(struct phy_device *phydev)
625 if (PHY_HALTED == phydev->state) 639 if (PHY_HALTED == phydev->state)
626 goto out_unlock; 640 goto out_unlock;
627 641
628 if (phydev->irq != PHY_POLL) { 642 phydev->state = PHY_HALTED;
629 /* Clear any pending interrupts */
630 phy_clear_interrupt(phydev);
631 643
644 if (phydev->irq != PHY_POLL) {
632 /* Disable PHY Interrupts */ 645 /* Disable PHY Interrupts */
633 phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED); 646 phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED);
634 }
635 647
636 phydev->state = PHY_HALTED; 648 /* Clear any pending interrupts */
649 phy_clear_interrupt(phydev);
650 }
637 651
638out_unlock: 652out_unlock:
639 spin_unlock(&phydev->lock); 653 spin_unlock(&phydev->lock);
654
655 /*
656 * Cannot call flush_scheduled_work() here as desired because
657 * of rtnl_lock(), but PHY_HALTED shall guarantee phy_change()
658 * will not reenable interrupts.
659 */
640} 660}
641 661
642 662
@@ -694,60 +714,57 @@ static void phy_timer(unsigned long data)
694 714
695 break; 715 break;
696 case PHY_AN: 716 case PHY_AN:
717 err = phy_read_status(phydev);
718
719 if (err < 0)
720 break;
721
722 /* If the link is down, give up on
723 * negotiation for now */
724 if (!phydev->link) {
725 phydev->state = PHY_NOLINK;
726 netif_carrier_off(phydev->attached_dev);
727 phydev->adjust_link(phydev->attached_dev);
728 break;
729 }
730
697 /* Check if negotiation is done. Break 731 /* Check if negotiation is done. Break
698 * if there's an error */ 732 * if there's an error */
699 err = phy_aneg_done(phydev); 733 err = phy_aneg_done(phydev);
700 if (err < 0) 734 if (err < 0)
701 break; 735 break;
702 736
703 /* If auto-negotiation is done, we change to 737 /* If AN is done, we're running */
704 * either RUNNING, or NOLINK */
705 if (err > 0) { 738 if (err > 0) {
706 err = phy_read_status(phydev); 739 phydev->state = PHY_RUNNING;
740 netif_carrier_on(phydev->attached_dev);
741 phydev->adjust_link(phydev->attached_dev);
742
743 } else if (0 == phydev->link_timeout--) {
744 int idx;
707 745
708 if (err) 746 needs_aneg = 1;
747 /* If we have the magic_aneg bit,
748 * we try again */
749 if (phydev->drv->flags & PHY_HAS_MAGICANEG)
709 break; 750 break;
710 751
711 if (phydev->link) { 752 /* The timer expired, and we still
712 phydev->state = PHY_RUNNING; 753 * don't have a setting, so we try
713 netif_carrier_on(phydev->attached_dev); 754 * forcing it until we find one that
714 } else { 755 * works, starting from the fastest speed,
715 phydev->state = PHY_NOLINK; 756 * and working our way down */
716 netif_carrier_off(phydev->attached_dev); 757 idx = phy_find_valid(0, phydev->supported);
717 }
718 758
719 phydev->adjust_link(phydev->attached_dev); 759 phydev->speed = settings[idx].speed;
760 phydev->duplex = settings[idx].duplex;
720 761
721 } else if (0 == phydev->link_timeout--) { 762 phydev->autoneg = AUTONEG_DISABLE;
722 /* The counter expired, so either we
723 * switch to forced mode, or the
724 * magic_aneg bit exists, and we try aneg
725 * again */
726 if (!(phydev->drv->flags & PHY_HAS_MAGICANEG)) {
727 int idx;
728
729 /* We'll start from the
730 * fastest speed, and work
731 * our way down */
732 idx = phy_find_valid(0,
733 phydev->supported);
734
735 phydev->speed = settings[idx].speed;
736 phydev->duplex = settings[idx].duplex;
737
738 phydev->autoneg = AUTONEG_DISABLE;
739 phydev->state = PHY_FORCING;
740 phydev->link_timeout =
741 PHY_FORCE_TIMEOUT;
742
743 pr_info("Trying %d/%s\n",
744 phydev->speed,
745 DUPLEX_FULL ==
746 phydev->duplex ?
747 "FULL" : "HALF");
748 }
749 763
750 needs_aneg = 1; 764 pr_info("Trying %d/%s\n", phydev->speed,
765 DUPLEX_FULL ==
766 phydev->duplex ?
767 "FULL" : "HALF");
751 } 768 }
752 break; 769 break;
753 case PHY_NOLINK: 770 case PHY_NOLINK:
@@ -763,7 +780,7 @@ static void phy_timer(unsigned long data)
763 } 780 }
764 break; 781 break;
765 case PHY_FORCING: 782 case PHY_FORCING:
766 err = phy_read_status(phydev); 783 err = genphy_update_link(phydev);
767 784
768 if (err) 785 if (err)
769 break; 786 break;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 3bbd5e70c209..b01fc70a57db 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -59,6 +59,7 @@ struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id)
59 dev->duplex = -1; 59 dev->duplex = -1;
60 dev->pause = dev->asym_pause = 0; 60 dev->pause = dev->asym_pause = 0;
61 dev->link = 1; 61 dev->link = 1;
62 dev->interface = PHY_INTERFACE_MODE_GMII;
62 63
63 dev->autoneg = AUTONEG_ENABLE; 64 dev->autoneg = AUTONEG_ENABLE;
64 65
@@ -137,11 +138,12 @@ void phy_prepare_link(struct phy_device *phydev,
137 * the desired functionality. 138 * the desired functionality.
138 */ 139 */
139struct phy_device * phy_connect(struct net_device *dev, const char *phy_id, 140struct phy_device * phy_connect(struct net_device *dev, const char *phy_id,
140 void (*handler)(struct net_device *), u32 flags) 141 void (*handler)(struct net_device *), u32 flags,
142 u32 interface)
141{ 143{
142 struct phy_device *phydev; 144 struct phy_device *phydev;
143 145
144 phydev = phy_attach(dev, phy_id, flags); 146 phydev = phy_attach(dev, phy_id, flags, interface);
145 147
146 if (IS_ERR(phydev)) 148 if (IS_ERR(phydev))
147 return phydev; 149 return phydev;
@@ -186,7 +188,7 @@ static int phy_compare_id(struct device *dev, void *data)
186} 188}
187 189
188struct phy_device *phy_attach(struct net_device *dev, 190struct phy_device *phy_attach(struct net_device *dev,
189 const char *phy_id, u32 flags) 191 const char *phy_id, u32 flags, u32 interface)
190{ 192{
191 struct bus_type *bus = &mdio_bus_type; 193 struct bus_type *bus = &mdio_bus_type;
192 struct phy_device *phydev; 194 struct phy_device *phydev;
@@ -231,6 +233,20 @@ struct phy_device *phy_attach(struct net_device *dev,
231 233
232 phydev->dev_flags = flags; 234 phydev->dev_flags = flags;
233 235
236 phydev->interface = interface;
237
238 /* Do initial configuration here, now that
239 * we have certain key parameters
240 * (dev_flags and interface) */
241 if (phydev->drv->config_init) {
242 int err;
243
244 err = phydev->drv->config_init(phydev);
245
246 if (err < 0)
247 return ERR_PTR(err);
248 }
249
234 return phydev; 250 return phydev;
235} 251}
236EXPORT_SYMBOL(phy_attach); 252EXPORT_SYMBOL(phy_attach);
@@ -427,6 +443,7 @@ int genphy_update_link(struct phy_device *phydev)
427 443
428 return 0; 444 return 0;
429} 445}
446EXPORT_SYMBOL(genphy_update_link);
430 447
431/* genphy_read_status 448/* genphy_read_status
432 * 449 *
@@ -611,13 +628,8 @@ static int phy_probe(struct device *dev)
611 628
612 spin_unlock(&phydev->lock); 629 spin_unlock(&phydev->lock);
613 630
614 if (err < 0)
615 return err;
616
617 if (phydev->drv->config_init)
618 err = phydev->drv->config_init(phydev);
619
620 return err; 631 return err;
632
621} 633}
622 634
623static int phy_remove(struct device *dev) 635static int phy_remove(struct device *dev)
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index f5802e7b08e9..c6de566188e4 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -860,7 +860,7 @@ static int __init ppp_init(void)
860 err = PTR_ERR(ppp_class); 860 err = PTR_ERR(ppp_class);
861 goto out_chrdev; 861 goto out_chrdev;
862 } 862 }
863 class_device_create(ppp_class, NULL, MKDEV(PPP_MAJOR, 0), NULL, "ppp"); 863 device_create(ppp_class, NULL, MKDEV(PPP_MAJOR, 0), "ppp");
864 } 864 }
865 865
866out: 866out:
@@ -2675,7 +2675,7 @@ static void __exit ppp_cleanup(void)
2675 cardmap_destroy(&all_ppp_units); 2675 cardmap_destroy(&all_ppp_units);
2676 if (unregister_chrdev(PPP_MAJOR, "ppp") != 0) 2676 if (unregister_chrdev(PPP_MAJOR, "ppp") != 0)
2677 printk(KERN_ERR "PPP: failed to unregister PPP device\n"); 2677 printk(KERN_ERR "PPP: failed to unregister PPP device\n");
2678 class_device_destroy(ppp_class, MKDEV(PPP_MAJOR, 0)); 2678 device_destroy(ppp_class, MKDEV(PPP_MAJOR, 0));
2679 class_destroy(ppp_class); 2679 class_destroy(ppp_class);
2680} 2680}
2681 2681
diff --git a/drivers/net/pppoe.c b/drivers/net/pppoe.c
index 0adee733b761..315d5c3fc66a 100644
--- a/drivers/net/pppoe.c
+++ b/drivers/net/pppoe.c
@@ -393,7 +393,7 @@ static int pppoe_rcv(struct sk_buff *skb,
393 393
394 po = get_item((unsigned long) ph->sid, eth_hdr(skb)->h_source); 394 po = get_item((unsigned long) ph->sid, eth_hdr(skb)->h_source);
395 if (po != NULL) 395 if (po != NULL)
396 return sk_receive_skb(sk_pppox(po), skb); 396 return sk_receive_skb(sk_pppox(po), skb, 0);
397drop: 397drop:
398 kfree_skb(skb); 398 kfree_skb(skb);
399out: 399out:
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 1f9663a70823..85a392fab5cc 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -572,8 +572,8 @@ static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
572{ 572{
573 unsigned int val; 573 unsigned int val;
574 574
575 val = (mdio_read(ioaddr, MII_BMCR) | BMCR_RESET) & 0xffff; 575 mdio_write(ioaddr, MII_BMCR, BMCR_RESET);
576 mdio_write(ioaddr, MII_BMCR, val); 576 val = mdio_read(ioaddr, MII_BMCR);
577} 577}
578 578
579static void rtl8169_check_link_status(struct net_device *dev, 579static void rtl8169_check_link_status(struct net_device *dev,
@@ -1407,6 +1407,22 @@ static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1407 free_netdev(dev); 1407 free_netdev(dev);
1408} 1408}
1409 1409
1410static void rtl8169_phy_reset(struct net_device *dev,
1411 struct rtl8169_private *tp)
1412{
1413 void __iomem *ioaddr = tp->mmio_addr;
1414 int i;
1415
1416 tp->phy_reset_enable(ioaddr);
1417 for (i = 0; i < 100; i++) {
1418 if (!tp->phy_reset_pending(ioaddr))
1419 return;
1420 msleep(1);
1421 }
1422 if (netif_msg_link(tp))
1423 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1424}
1425
1410static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 1426static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1411{ 1427{
1412 void __iomem *ioaddr = tp->mmio_addr; 1428 void __iomem *ioaddr = tp->mmio_addr;
@@ -1435,6 +1451,8 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1435 1451
1436 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex); 1452 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1437 1453
1454 rtl8169_phy_reset(dev, tp);
1455
1438 rtl8169_set_speed(dev, autoneg, speed, duplex); 1456 rtl8169_set_speed(dev, autoneg, speed, duplex);
1439 1457
1440 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) 1458 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
@@ -1474,8 +1492,8 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1474 struct rtl8169_private *tp; 1492 struct rtl8169_private *tp;
1475 struct net_device *dev; 1493 struct net_device *dev;
1476 void __iomem *ioaddr; 1494 void __iomem *ioaddr;
1477 unsigned int i, pm_cap; 1495 unsigned int pm_cap;
1478 int rc; 1496 int i, rc;
1479 1497
1480 if (netif_msg_drv(&debug)) { 1498 if (netif_msg_drv(&debug)) {
1481 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", 1499 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
diff --git a/drivers/net/sk98lin/h/skdrv2nd.h b/drivers/net/sk98lin/h/skdrv2nd.h
index 778d9e618ebd..3fa67171e832 100644
--- a/drivers/net/sk98lin/h/skdrv2nd.h
+++ b/drivers/net/sk98lin/h/skdrv2nd.h
@@ -160,7 +160,7 @@ struct s_IOCTL {
160 160
161/* 161/*
162** Interim definition of SK_DRV_TIMER placed in this file until 162** Interim definition of SK_DRV_TIMER placed in this file until
163** common modules have boon finallized 163** common modules have been finalized
164*/ 164*/
165#define SK_DRV_TIMER 11 165#define SK_DRV_TIMER 11
166#define SK_DRV_MODERATION_TIMER 1 166#define SK_DRV_MODERATION_TIMER 1
diff --git a/drivers/net/sk98lin/skdim.c b/drivers/net/sk98lin/skdim.c
index 07c1b4c8699d..37ce03fb8de3 100644
--- a/drivers/net/sk98lin/skdim.c
+++ b/drivers/net/sk98lin/skdim.c
@@ -252,7 +252,7 @@ SkDimEnableModerationIfNeeded(SK_AC *pAC) {
252 252
253/******************************************************************************* 253/*******************************************************************************
254** Function : SkDimDisplayModerationSettings 254** Function : SkDimDisplayModerationSettings
255** Description : Displays the current settings regaring interrupt moderation 255** Description : Displays the current settings regarding interrupt moderation
256** Programmer : Ralph Roesler 256** Programmer : Ralph Roesler
257** Last Modified: 22-mar-03 257** Last Modified: 22-mar-03
258** Returns : void (!) 258** Returns : void (!)
@@ -510,7 +510,7 @@ EnableIntMod(SK_AC *pAC) {
510 510
511/******************************************************************************* 511/*******************************************************************************
512** Function : DisableIntMod() 512** Function : DisableIntMod()
513** Description : Disbles the interrupt moderation independent of what inter- 513** Description : Disables the interrupt moderation independent of what inter-
514** rupts are running or not 514** rupts are running or not
515** Programmer : Ralph Roesler 515** Programmer : Ralph Roesler
516** Last Modified: 23-mar-03 516** Last Modified: 23-mar-03
diff --git a/drivers/net/sk98lin/skethtool.c b/drivers/net/sk98lin/skethtool.c
index e5cb5b548b88..36460694eb82 100644
--- a/drivers/net/sk98lin/skethtool.c
+++ b/drivers/net/sk98lin/skethtool.c
@@ -581,6 +581,30 @@ static int setRxCsum(struct net_device *dev, u32 data)
581 return 0; 581 return 0;
582} 582}
583 583
584static int getRegsLen(struct net_device *dev)
585{
586 return 0x4000;
587}
588
589/*
590 * Returns copy of whole control register region
591 * Note: skip RAM address register because accessing it will
592 * cause bus hangs!
593 */
594static void getRegs(struct net_device *dev, struct ethtool_regs *regs,
595 void *p)
596{
597 DEV_NET *pNet = netdev_priv(dev);
598 const void __iomem *io = pNet->pAC->IoBase;
599
600 regs->version = 1;
601 memset(p, 0, regs->len);
602 memcpy_fromio(p, io, B3_RAM_ADDR);
603
604 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
605 regs->len - B3_RI_WTO_R1);
606}
607
584const struct ethtool_ops SkGeEthtoolOps = { 608const struct ethtool_ops SkGeEthtoolOps = {
585 .get_settings = getSettings, 609 .get_settings = getSettings,
586 .set_settings = setSettings, 610 .set_settings = setSettings,
@@ -599,4 +623,6 @@ const struct ethtool_ops SkGeEthtoolOps = {
599 .set_tx_csum = setTxCsum, 623 .set_tx_csum = setTxCsum,
600 .get_rx_csum = getRxCsum, 624 .get_rx_csum = getRxCsum,
601 .set_rx_csum = setRxCsum, 625 .set_rx_csum = setRxCsum,
626 .get_regs = getRegs,
627 .get_regs_len = getRegsLen,
602}; 628};
diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c
index d4913c3de2a1..12cbfd190dd7 100644
--- a/drivers/net/sk98lin/skge.c
+++ b/drivers/net/sk98lin/skge.c
@@ -113,6 +113,7 @@
113#include <linux/init.h> 113#include <linux/init.h>
114#include <linux/dma-mapping.h> 114#include <linux/dma-mapping.h>
115#include <linux/ip.h> 115#include <linux/ip.h>
116#include <linux/mii.h>
116 117
117#include "h/skdrv1st.h" 118#include "h/skdrv1st.h"
118#include "h/skdrv2nd.h" 119#include "h/skdrv2nd.h"
@@ -1561,7 +1562,7 @@ struct sk_buff *pMessage) /* pointer to send-message */
1561 1562
1562 if (pMessage->ip_summed == CHECKSUM_PARTIAL) { 1563 if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
1563 u16 hdrlen = pMessage->h.raw - pMessage->data; 1564 u16 hdrlen = pMessage->h.raw - pMessage->data;
1564 u16 offset = hdrlen + pMessage->csum; 1565 u16 offset = hdrlen + pMessage->csum_offset;
1565 1566
1566 if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) && 1567 if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
1567 (pAC->GIni.GIChipRev == 0) && 1568 (pAC->GIni.GIChipRev == 0) &&
@@ -1680,7 +1681,7 @@ struct sk_buff *pMessage) /* pointer to send-message */
1680 */ 1681 */
1681 if (pMessage->ip_summed == CHECKSUM_PARTIAL) { 1682 if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
1682 u16 hdrlen = pMessage->h.raw - pMessage->data; 1683 u16 hdrlen = pMessage->h.raw - pMessage->data;
1683 u16 offset = hdrlen + pMessage->csum; 1684 u16 offset = hdrlen + pMessage->csum_offset;
1684 1685
1685 Control = BMU_STFWD; 1686 Control = BMU_STFWD;
1686 1687
@@ -2843,6 +2844,56 @@ unsigned long Flags; /* for spin lock */
2843 return(&pAC->stats); 2844 return(&pAC->stats);
2844} /* SkGeStats */ 2845} /* SkGeStats */
2845 2846
2847/*
2848 * Basic MII register access
2849 */
2850static int SkGeMiiIoctl(struct net_device *dev,
2851 struct mii_ioctl_data *data, int cmd)
2852{
2853 DEV_NET *pNet = netdev_priv(dev);
2854 SK_AC *pAC = pNet->pAC;
2855 SK_IOC IoC = pAC->IoBase;
2856 int Port = pNet->PortNr;
2857 SK_GEPORT *pPrt = &pAC->GIni.GP[Port];
2858 unsigned long Flags;
2859 int err = 0;
2860 int reg = data->reg_num & 0x1f;
2861 SK_U16 val = data->val_in;
2862
2863 if (!netif_running(dev))
2864 return -ENODEV; /* Phy still in reset */
2865
2866 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
2867 switch(cmd) {
2868 case SIOCGMIIPHY:
2869 data->phy_id = pPrt->PhyAddr;
2870
2871 /* fallthru */
2872 case SIOCGMIIREG:
2873 if (pAC->GIni.GIGenesis)
2874 SkXmPhyRead(pAC, IoC, Port, reg, &val);
2875 else
2876 SkGmPhyRead(pAC, IoC, Port, reg, &val);
2877
2878 data->val_out = val;
2879 break;
2880
2881 case SIOCSMIIREG:
2882 if (!capable(CAP_NET_ADMIN))
2883 err = -EPERM;
2884
2885 else if (pAC->GIni.GIGenesis)
2886 SkXmPhyWrite(pAC, IoC, Port, reg, val);
2887 else
2888 SkGmPhyWrite(pAC, IoC, Port, reg, val);
2889 break;
2890 default:
2891 err = -EOPNOTSUPP;
2892 }
2893 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
2894 return err;
2895}
2896
2846 2897
2847/***************************************************************************** 2898/*****************************************************************************
2848 * 2899 *
@@ -2876,6 +2927,9 @@ int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
2876 pNet = netdev_priv(dev); 2927 pNet = netdev_priv(dev);
2877 pAC = pNet->pAC; 2928 pAC = pNet->pAC;
2878 2929
2930 if (cmd == SIOCGMIIPHY || cmd == SIOCSMIIREG || cmd == SIOCGMIIREG)
2931 return SkGeMiiIoctl(dev, if_mii(rq), cmd);
2932
2879 if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) { 2933 if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
2880 return -EFAULT; 2934 return -EFAULT;
2881 } 2935 }
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 3b67614372a7..b60f0451f6cd 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -2155,8 +2155,6 @@ static void yukon_link_down(struct skge_port *skge)
2155 int port = skge->port; 2155 int port = skge->port;
2156 u16 ctrl; 2156 u16 ctrl;
2157 2157
2158 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2159
2160 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2158 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2161 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2159 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2162 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2160 gma_write16(hw, port, GM_GP_CTRL, ctrl);
@@ -2168,7 +2166,6 @@ static void yukon_link_down(struct skge_port *skge)
2168 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); 2166 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2169 } 2167 }
2170 2168
2171 yukon_reset(hw, port);
2172 skge_link_down(skge); 2169 skge_link_down(skge);
2173 2170
2174 yukon_init(hw, port); 2171 yukon_init(hw, port);
@@ -2256,6 +2253,7 @@ static void skge_phy_reset(struct skge_port *skge)
2256{ 2253{
2257 struct skge_hw *hw = skge->hw; 2254 struct skge_hw *hw = skge->hw;
2258 int port = skge->port; 2255 int port = skge->port;
2256 struct net_device *dev = hw->dev[port];
2259 2257
2260 netif_stop_queue(skge->netdev); 2258 netif_stop_queue(skge->netdev);
2261 netif_carrier_off(skge->netdev); 2259 netif_carrier_off(skge->netdev);
@@ -2269,6 +2267,8 @@ static void skge_phy_reset(struct skge_port *skge)
2269 yukon_init(hw, port); 2267 yukon_init(hw, port);
2270 } 2268 }
2271 mutex_unlock(&hw->phy_mutex); 2269 mutex_unlock(&hw->phy_mutex);
2270
2271 dev->set_multicast_list(dev);
2272} 2272}
2273 2273
2274/* Basic MII support */ 2274/* Basic MII support */
@@ -2566,7 +2566,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2566 2566
2567 td->csum_offs = 0; 2567 td->csum_offs = 0;
2568 td->csum_start = offset; 2568 td->csum_start = offset;
2569 td->csum_write = offset + skb->csum; 2569 td->csum_write = offset + skb->csum_offset;
2570 } else 2570 } else
2571 control = BMU_CHECK; 2571 control = BMU_CHECK;
2572 2572
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 16616f5440d0..842abd9396c6 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -104,6 +104,7 @@ static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
@@ -676,17 +677,15 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
676 /* Flush Rx MAC FIFO on any flow control or error */ 677 /* Flush Rx MAC FIFO on any flow control or error */
677 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
678 679
679 /* Set threshold to 0xa (64 bytes) 680 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
680 * ASF disabled so no need to do WA dev #4.30 681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
681 */
682 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
683 682
684 /* Configure Tx MAC FIFO */ 683 /* Configure Tx MAC FIFO */
685 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
686 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
687 686
688 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
689 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8); 688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
690 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); 689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
691 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
692 /* set Tx GMAC FIFO Almost Empty Threshold */ 691 /* set Tx GMAC FIFO Almost Empty Threshold */
@@ -1060,7 +1059,8 @@ static int sky2_rx_start(struct sky2_port *sky2)
1060 sky2->rx_put = sky2->rx_next = 0; 1059 sky2->rx_put = sky2->rx_next = 0;
1061 sky2_qset(hw, rxq); 1060 sky2_qset(hw, rxq);
1062 1061
1063 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { 1062 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1063 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
1064 /* MAC Rx RAM Read is controlled by hardware */ 1064 /* MAC Rx RAM Read is controlled by hardware */
1065 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); 1065 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1066 } 1066 }
@@ -1350,7 +1350,7 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1350 u32 tcpsum; 1350 u32 tcpsum;
1351 1351
1352 tcpsum = offset << 16; /* sum start */ 1352 tcpsum = offset << 16; /* sum start */
1353 tcpsum |= offset + skb->csum; /* sum write */ 1353 tcpsum |= offset + skb->csum_offset; /* sum write */
1354 1354
1355 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1355 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1356 if (skb->nh.iph->protocol == IPPROTO_UDP) 1356 if (skb->nh.iph->protocol == IPPROTO_UDP)
@@ -1453,7 +1453,7 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1453 if (unlikely(netif_msg_tx_done(sky2))) 1453 if (unlikely(netif_msg_tx_done(sky2)))
1454 printk(KERN_DEBUG "%s: tx done %u\n", 1454 printk(KERN_DEBUG "%s: tx done %u\n",
1455 dev->name, idx); 1455 dev->name, idx);
1456 dev_kfree_skb(re->skb); 1456 dev_kfree_skb_any(re->skb);
1457 } 1457 }
1458 1458
1459 le->opcode = 0; /* paranoia */ 1459 le->opcode = 0; /* paranoia */
@@ -1509,7 +1509,7 @@ static int sky2_down(struct net_device *dev)
1509 1509
1510 /* WA for dev. #4.209 */ 1510 /* WA for dev. #4.209 */
1511 if (hw->chip_id == CHIP_ID_YUKON_EC_U 1511 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1512 && hw->chip_rev == CHIP_REV_YU_EC_U_A1) 1512 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1513 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1513 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1514 sky2->speed != SPEED_1000 ? 1514 sky2->speed != SPEED_1000 ?
1515 TX_STFW_ENA : TX_STFW_DIS); 1515 TX_STFW_ENA : TX_STFW_DIS);
@@ -2065,7 +2065,7 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2065 case OP_RXSTAT: 2065 case OP_RXSTAT:
2066 skb = sky2_receive(dev, length, status); 2066 skb = sky2_receive(dev, length, status);
2067 if (!skb) 2067 if (!skb)
2068 break; 2068 goto force_update;
2069 2069
2070 skb->protocol = eth_type_trans(skb, dev); 2070 skb->protocol = eth_type_trans(skb, dev);
2071 dev->last_rx = jiffies; 2071 dev->last_rx = jiffies;
@@ -2081,8 +2081,8 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2081 2081
2082 /* Update receiver after 16 frames */ 2082 /* Update receiver after 16 frames */
2083 if (++buf_write[le->link] == RX_BUF_WRITE) { 2083 if (++buf_write[le->link] == RX_BUF_WRITE) {
2084 sky2_put_idx(hw, rxqaddr[le->link], 2084force_update:
2085 sky2->rx_put); 2085 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2086 buf_write[le->link] = 0; 2086 buf_write[le->link] = 0;
2087 } 2087 }
2088 2088
@@ -3311,7 +3311,7 @@ static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3311 return IRQ_NONE; 3311 return IRQ_NONE;
3312 3312
3313 if (status & Y2_IS_IRQ_SW) { 3313 if (status & Y2_IS_IRQ_SW) {
3314 hw->msi_detected = 1; 3314 hw->msi = 1;
3315 wake_up(&hw->msi_wait); 3315 wake_up(&hw->msi_wait);
3316 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 3316 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3317 } 3317 }
@@ -3330,7 +3330,7 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3330 3330
3331 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 3331 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3332 3332
3333 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw); 3333 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3334 if (err) { 3334 if (err) {
3335 printk(KERN_ERR PFX "%s: cannot assign irq %d\n", 3335 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3336 pci_name(pdev), pdev->irq); 3336 pci_name(pdev), pdev->irq);
@@ -3340,9 +3340,9 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3340 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 3340 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3341 sky2_read8(hw, B0_CTST); 3341 sky2_read8(hw, B0_CTST);
3342 3342
3343 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); 3343 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3344 3344
3345 if (!hw->msi_detected) { 3345 if (!hw->msi) {
3346 /* MSI test failed, go back to INTx mode */ 3346 /* MSI test failed, go back to INTx mode */
3347 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, " 3347 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3348 "switching to INTx mode.\n", 3348 "switching to INTx mode.\n",
@@ -3475,7 +3475,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
3475 goto err_out_free_netdev; 3475 goto err_out_free_netdev;
3476 } 3476 }
3477 3477
3478 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw); 3478 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3479 dev->name, hw);
3479 if (err) { 3480 if (err) {
3480 printk(KERN_ERR PFX "%s: cannot assign irq %d\n", 3481 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3481 pci_name(pdev), pdev->irq); 3482 pci_name(pdev), pdev->irq);
@@ -3505,7 +3506,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
3505 return 0; 3506 return 0;
3506 3507
3507err_out_unregister: 3508err_out_unregister:
3508 pci_disable_msi(pdev); 3509 if (hw->msi)
3510 pci_disable_msi(pdev);
3509 unregister_netdev(dev); 3511 unregister_netdev(dev);
3510err_out_free_netdev: 3512err_out_free_netdev:
3511 free_netdev(dev); 3513 free_netdev(dev);
@@ -3548,7 +3550,8 @@ static void __devexit sky2_remove(struct pci_dev *pdev)
3548 sky2_read8(hw, B0_CTST); 3550 sky2_read8(hw, B0_CTST);
3549 3551
3550 free_irq(pdev->irq, hw); 3552 free_irq(pdev->irq, hw);
3551 pci_disable_msi(pdev); 3553 if (hw->msi)
3554 pci_disable_msi(pdev);
3552 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); 3555 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3553 pci_release_regions(pdev); 3556 pci_release_regions(pdev);
3554 pci_disable_device(pdev); 3557 pci_disable_device(pdev);
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 6d2a23f66c9a..7760545edbf2 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -383,8 +383,13 @@ enum {
383 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ 383 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
384 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ 384 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
385 385
386 CHIP_REV_YU_EC_U_A0 = 0, 386 CHIP_REV_YU_EC_U_A0 = 1,
387 CHIP_REV_YU_EC_U_A1 = 1, 387 CHIP_REV_YU_EC_U_A1 = 2,
388 CHIP_REV_YU_EC_U_B0 = 3,
389
390 CHIP_REV_YU_FE_A1 = 1,
391 CHIP_REV_YU_FE_A2 = 2,
392
388}; 393};
389 394
390/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 395/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
@@ -1895,7 +1900,7 @@ struct sky2_hw {
1895 dma_addr_t st_dma; 1900 dma_addr_t st_dma;
1896 1901
1897 struct timer_list idle_timer; 1902 struct timer_list idle_timer;
1898 int msi_detected; 1903 int msi;
1899 wait_queue_head_t msi_wait; 1904 wait_queue_head_t msi_wait;
1900}; 1905};
1901 1906
diff --git a/drivers/net/spider_net.c b/drivers/net/spider_net.c
index f88fcac0e46a..f16f696c1ff2 100644
--- a/drivers/net/spider_net.c
+++ b/drivers/net/spider_net.c
@@ -644,20 +644,12 @@ spider_net_prepare_tx_descr(struct spider_net_card *card,
644 struct spider_net_descr *descr; 644 struct spider_net_descr *descr;
645 dma_addr_t buf; 645 dma_addr_t buf;
646 unsigned long flags; 646 unsigned long flags;
647 int length;
648 647
649 length = skb->len; 648 buf = pci_map_single(card->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
650 if (length < ETH_ZLEN) {
651 if (skb_pad(skb, ETH_ZLEN-length))
652 return 0;
653 length = ETH_ZLEN;
654 }
655
656 buf = pci_map_single(card->pdev, skb->data, length, PCI_DMA_TODEVICE);
657 if (pci_dma_mapping_error(buf)) { 649 if (pci_dma_mapping_error(buf)) {
658 if (netif_msg_tx_err(card) && net_ratelimit()) 650 if (netif_msg_tx_err(card) && net_ratelimit())
659 pr_err("could not iommu-map packet (%p, %i). " 651 pr_err("could not iommu-map packet (%p, %i). "
660 "Dropping packet\n", skb->data, length); 652 "Dropping packet\n", skb->data, skb->len);
661 card->spider_stats.tx_iommu_map_error++; 653 card->spider_stats.tx_iommu_map_error++;
662 return -ENOMEM; 654 return -ENOMEM;
663 } 655 }
@@ -667,7 +659,7 @@ spider_net_prepare_tx_descr(struct spider_net_card *card,
667 card->tx_chain.head = descr->next; 659 card->tx_chain.head = descr->next;
668 660
669 descr->buf_addr = buf; 661 descr->buf_addr = buf;
670 descr->buf_size = length; 662 descr->buf_size = skb->len;
671 descr->next_descr_addr = 0; 663 descr->next_descr_addr = 0;
672 descr->skb = skb; 664 descr->skb = skb;
673 descr->data_status = 0; 665 descr->data_status = 0;
@@ -802,8 +794,8 @@ spider_net_release_tx_chain(struct spider_net_card *card, int brutal)
802 794
803 /* unmap the skb */ 795 /* unmap the skb */
804 if (skb) { 796 if (skb) {
805 int len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 797 pci_unmap_single(card->pdev, buf_addr, skb->len,
806 pci_unmap_single(card->pdev, buf_addr, len, PCI_DMA_TODEVICE); 798 PCI_DMA_TODEVICE);
807 dev_kfree_skb(skb); 799 dev_kfree_skb(skb);
808 } 800 }
809 } 801 }
@@ -1641,7 +1633,7 @@ spider_net_enable_card(struct spider_net_card *card)
1641 SPIDER_NET_INT2_MASK_VALUE); 1633 SPIDER_NET_INT2_MASK_VALUE);
1642 1634
1643 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR, 1635 spider_net_write_reg(card, SPIDER_NET_GDTDMACCNTR,
1644 SPIDER_NET_GDTBSTA | SPIDER_NET_GDTDCEIDIS); 1636 SPIDER_NET_GDTBSTA);
1645} 1637}
1646 1638
1647/** 1639/**
diff --git a/drivers/net/spider_net.h b/drivers/net/spider_net.h
index b3b46119b424..3e196df29790 100644
--- a/drivers/net/spider_net.h
+++ b/drivers/net/spider_net.h
@@ -24,7 +24,7 @@
24#ifndef _SPIDER_NET_H 24#ifndef _SPIDER_NET_H
25#define _SPIDER_NET_H 25#define _SPIDER_NET_H
26 26
27#define VERSION "1.1 A" 27#define VERSION "1.6 A"
28 28
29#include "sungem_phy.h" 29#include "sungem_phy.h"
30 30
@@ -217,8 +217,7 @@ extern char spider_net_driver_name[];
217#define SPIDER_NET_GDTBSTA 0x00000300 217#define SPIDER_NET_GDTBSTA 0x00000300
218#define SPIDER_NET_GDTDCEIDIS 0x00000002 218#define SPIDER_NET_GDTDCEIDIS 0x00000002
219#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \ 219#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \
220 SPIDER_NET_GDTBSTA | \ 220 SPIDER_NET_GDTBSTA
221 SPIDER_NET_GDTDCEIDIS
222 221
223#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003 222#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
224 223
@@ -328,7 +327,8 @@ enum spider_net_int2_status {
328 SPIDER_NET_GRISPDNGINT 327 SPIDER_NET_GRISPDNGINT
329}; 328};
330 329
331#define SPIDER_NET_TXINT ( (1 << SPIDER_NET_GDTFDCINT) ) 330#define SPIDER_NET_TXINT ( (1 << SPIDER_NET_GDTFDCINT) | \
331 (1 << SPIDER_NET_GDTDCEINT) )
332 332
333/* We rely on flagged descriptor interrupts */ 333/* We rely on flagged descriptor interrupts */
334#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) ) 334#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )
diff --git a/drivers/net/sundance.c b/drivers/net/sundance.c
index 41c503d8bac4..c06ecc8002b9 100644
--- a/drivers/net/sundance.c
+++ b/drivers/net/sundance.c
@@ -264,8 +264,6 @@ enum alta_offsets {
264 ASICCtrl = 0x30, 264 ASICCtrl = 0x30,
265 EEData = 0x34, 265 EEData = 0x34,
266 EECtrl = 0x36, 266 EECtrl = 0x36,
267 TxStartThresh = 0x3c,
268 RxEarlyThresh = 0x3e,
269 FlashAddr = 0x40, 267 FlashAddr = 0x40,
270 FlashData = 0x44, 268 FlashData = 0x44,
271 TxStatus = 0x46, 269 TxStatus = 0x46,
@@ -790,6 +788,7 @@ static int netdev_open(struct net_device *dev)
790{ 788{
791 struct netdev_private *np = netdev_priv(dev); 789 struct netdev_private *np = netdev_priv(dev);
792 void __iomem *ioaddr = np->base; 790 void __iomem *ioaddr = np->base;
791 unsigned long flags;
793 int i; 792 int i;
794 793
795 /* Do we need to reset the chip??? */ 794 /* Do we need to reset the chip??? */
@@ -834,6 +833,10 @@ static int netdev_open(struct net_device *dev)
834 iowrite8(0x01, ioaddr + DebugCtrl1); 833 iowrite8(0x01, ioaddr + DebugCtrl1);
835 netif_start_queue(dev); 834 netif_start_queue(dev);
836 835
836 spin_lock_irqsave(&np->lock, flags);
837 reset_tx(dev);
838 spin_unlock_irqrestore(&np->lock, flags);
839
837 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); 840 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
838 841
839 if (netif_msg_ifup(np)) 842 if (netif_msg_ifup(np))
@@ -1081,6 +1084,8 @@ reset_tx (struct net_device *dev)
1081 1084
1082 /* free all tx skbuff */ 1085 /* free all tx skbuff */
1083 for (i = 0; i < TX_RING_SIZE; i++) { 1086 for (i = 0; i < TX_RING_SIZE; i++) {
1087 np->tx_ring[i].next_desc = 0;
1088
1084 skb = np->tx_skbuff[i]; 1089 skb = np->tx_skbuff[i];
1085 if (skb) { 1090 if (skb) {
1086 pci_unmap_single(np->pci_dev, 1091 pci_unmap_single(np->pci_dev,
@@ -1096,6 +1101,10 @@ reset_tx (struct net_device *dev)
1096 } 1101 }
1097 np->cur_tx = np->dirty_tx = 0; 1102 np->cur_tx = np->dirty_tx = 0;
1098 np->cur_task = 0; 1103 np->cur_task = 0;
1104
1105 np->last_tx = NULL;
1106 iowrite8(127, ioaddr + TxDMAPollPeriod);
1107
1099 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); 1108 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1100 return 0; 1109 return 0;
1101} 1110}
@@ -1111,6 +1120,7 @@ static irqreturn_t intr_handler(int irq, void *dev_instance)
1111 int tx_cnt; 1120 int tx_cnt;
1112 int tx_status; 1121 int tx_status;
1113 int handled = 0; 1122 int handled = 0;
1123 int i;
1114 1124
1115 1125
1116 do { 1126 do {
@@ -1153,21 +1163,24 @@ static irqreturn_t intr_handler(int irq, void *dev_instance)
1153 np->stats.tx_fifo_errors++; 1163 np->stats.tx_fifo_errors++;
1154 if (tx_status & 0x02) 1164 if (tx_status & 0x02)
1155 np->stats.tx_window_errors++; 1165 np->stats.tx_window_errors++;
1166
1156 /* 1167 /*
1157 ** This reset has been verified on 1168 ** This reset has been verified on
1158 ** DFE-580TX boards ! phdm@macqel.be. 1169 ** DFE-580TX boards ! phdm@macqel.be.
1159 */ 1170 */
1160 if (tx_status & 0x10) { /* TxUnderrun */ 1171 if (tx_status & 0x10) { /* TxUnderrun */
1161 unsigned short txthreshold;
1162
1163 txthreshold = ioread16 (ioaddr + TxStartThresh);
1164 /* Restart Tx FIFO and transmitter */ 1172 /* Restart Tx FIFO and transmitter */
1165 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16); 1173 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1166 iowrite16 (txthreshold, ioaddr + TxStartThresh);
1167 /* No need to reset the Tx pointer here */ 1174 /* No need to reset the Tx pointer here */
1168 } 1175 }
1169 /* Restart the Tx. */ 1176 /* Restart the Tx. Need to make sure tx enabled */
1170 iowrite16 (TxEnable, ioaddr + MACCtrl1); 1177 i = 10;
1178 do {
1179 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1180 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1181 break;
1182 mdelay(1);
1183 } while (--i);
1171 } 1184 }
1172 /* Yup, this is a documentation bug. It cost me *hours*. */ 1185 /* Yup, this is a documentation bug. It cost me *hours*. */
1173 iowrite16 (0, ioaddr + TxStatus); 1186 iowrite16 (0, ioaddr + TxStatus);
@@ -1629,6 +1642,14 @@ static int netdev_close(struct net_device *dev)
1629 struct sk_buff *skb; 1642 struct sk_buff *skb;
1630 int i; 1643 int i;
1631 1644
1645 /* Wait and kill tasklet */
1646 tasklet_kill(&np->rx_tasklet);
1647 tasklet_kill(&np->tx_tasklet);
1648 np->cur_tx = 0;
1649 np->dirty_tx = 0;
1650 np->cur_task = 0;
1651 np->last_tx = NULL;
1652
1632 netif_stop_queue(dev); 1653 netif_stop_queue(dev);
1633 1654
1634 if (netif_msg_ifdown(np)) { 1655 if (netif_msg_ifdown(np)) {
@@ -1643,12 +1664,26 @@ static int netdev_close(struct net_device *dev)
1643 /* Disable interrupts by clearing the interrupt mask. */ 1664 /* Disable interrupts by clearing the interrupt mask. */
1644 iowrite16(0x0000, ioaddr + IntrEnable); 1665 iowrite16(0x0000, ioaddr + IntrEnable);
1645 1666
1667 /* Disable Rx and Tx DMA for safely release resource */
1668 iowrite32(0x500, ioaddr + DMACtrl);
1669
1646 /* Stop the chip's Tx and Rx processes. */ 1670 /* Stop the chip's Tx and Rx processes. */
1647 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1); 1671 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1648 1672
1649 /* Wait and kill tasklet */ 1673 for (i = 2000; i > 0; i--) {
1650 tasklet_kill(&np->rx_tasklet); 1674 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1651 tasklet_kill(&np->tx_tasklet); 1675 break;
1676 mdelay(1);
1677 }
1678
1679 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1680 ioaddr +ASICCtrl + 2);
1681
1682 for (i = 2000; i > 0; i--) {
1683 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1684 break;
1685 mdelay(1);
1686 }
1652 1687
1653#ifdef __i386__ 1688#ifdef __i386__
1654 if (netif_msg_hw(np)) { 1689 if (netif_msg_hw(np)) {
@@ -1686,6 +1721,7 @@ static int netdev_close(struct net_device *dev)
1686 } 1721 }
1687 } 1722 }
1688 for (i = 0; i < TX_RING_SIZE; i++) { 1723 for (i = 0; i < TX_RING_SIZE; i++) {
1724 np->tx_ring[i].next_desc = 0;
1689 skb = np->tx_skbuff[i]; 1725 skb = np->tx_skbuff[i];
1690 if (skb) { 1726 if (skb) {
1691 pci_unmap_single(np->pci_dev, 1727 pci_unmap_single(np->pci_dev,
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 004d651681ad..d03a9a849c06 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -1030,7 +1030,7 @@ static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1030 u64 csum_start_off, csum_stuff_off; 1030 u64 csum_start_off, csum_stuff_off;
1031 1031
1032 csum_start_off = (u64) (skb->h.raw - skb->data); 1032 csum_start_off = (u64) (skb->h.raw - skb->data);
1033 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data); 1033 csum_stuff_off = csum_start_off + skb->csum_offset;
1034 1034
1035 ctrl = (TXDCTRL_CENAB | 1035 ctrl = (TXDCTRL_CENAB |
1036 (csum_start_off << 15) | 1036 (csum_start_off << 15) |
diff --git a/drivers/net/sunhme.c b/drivers/net/sunhme.c
index 9d7cd130c19d..ec432ea879fb 100644
--- a/drivers/net/sunhme.c
+++ b/drivers/net/sunhme.c
@@ -2272,7 +2272,7 @@ static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2272 u32 csum_start_off, csum_stuff_off; 2272 u32 csum_start_off, csum_stuff_off;
2273 2273
2274 csum_start_off = (u32) (skb->h.raw - skb->data); 2274 csum_start_off = (u32) (skb->h.raw - skb->data);
2275 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data); 2275 csum_stuff_off = csum_start_off + skb->csum_offset;
2276 2276
2277 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE | 2277 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2278 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) | 2278 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
diff --git a/drivers/net/tokenring/olympic.c b/drivers/net/tokenring/olympic.c
index cd142d0302bc..8f4ecc1109cb 100644
--- a/drivers/net/tokenring/olympic.c
+++ b/drivers/net/tokenring/olympic.c
@@ -1771,7 +1771,7 @@ static struct pci_driver olympic_driver = {
1771 1771
1772static int __init olympic_pci_init(void) 1772static int __init olympic_pci_init(void)
1773{ 1773{
1774 return pci_module_init (&olympic_driver) ; 1774 return pci_register_driver(&olympic_driver) ;
1775} 1775}
1776 1776
1777static void __exit olympic_pci_cleanup(void) 1777static void __exit olympic_pci_cleanup(void)
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
new file mode 100644
index 000000000000..893808ab3742
--- /dev/null
+++ b/drivers/net/tsi108_eth.c
@@ -0,0 +1,1708 @@
1/*******************************************************************************
2
3 Copyright(c) 2006 Tundra Semiconductor Corporation.
4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of the GNU General Public License as published by the Free
7 Software Foundation; either version 2 of the License, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc., 59
17 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
19*******************************************************************************/
20
21/* This driver is based on the driver code originally developed
22 * for the Intel IOC80314 (ForestLake) Gigabit Ethernet by
23 * scott.wood@timesys.com * Copyright (C) 2003 TimeSys Corporation
24 *
25 * Currently changes from original version are:
26 * - porting to Tsi108-based platform and kernel 2.6 (kong.lai@tundra.com)
27 * - modifications to handle two ports independently and support for
28 * additional PHY devices (alexandre.bounine@tundra.com)
29 * - Get hardware information from platform device. (tie-fei.zang@freescale.com)
30 *
31 */
32
33#include <linux/module.h>
34#include <linux/types.h>
35#include <linux/init.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/skbuff.h>
40#include <linux/slab.h>
41#include <linux/sched.h>
42#include <linux/spinlock.h>
43#include <linux/delay.h>
44#include <linux/crc32.h>
45#include <linux/mii.h>
46#include <linux/device.h>
47#include <linux/pci.h>
48#include <linux/rtnetlink.h>
49#include <linux/timer.h>
50#include <linux/platform_device.h>
51#include <linux/etherdevice.h>
52
53#include <asm/system.h>
54#include <asm/io.h>
55#include <asm/tsi108.h>
56
57#include "tsi108_eth.h"
58
59#define MII_READ_DELAY 10000 /* max link wait time in msec */
60
61#define TSI108_RXRING_LEN 256
62
63/* NOTE: The driver currently does not support receiving packets
64 * larger than the buffer size, so don't decrease this (unless you
65 * want to add such support).
66 */
67#define TSI108_RXBUF_SIZE 1536
68
69#define TSI108_TXRING_LEN 256
70
71#define TSI108_TX_INT_FREQ 64
72
73/* Check the phy status every half a second. */
74#define CHECK_PHY_INTERVAL (HZ/2)
75
76static int tsi108_init_one(struct platform_device *pdev);
77static int tsi108_ether_remove(struct platform_device *pdev);
78
79struct tsi108_prv_data {
80 void __iomem *regs; /* Base of normal regs */
81 void __iomem *phyregs; /* Base of register bank used for PHY access */
82
83 unsigned int phy; /* Index of PHY for this interface */
84 unsigned int irq_num;
85 unsigned int id;
86
87 struct timer_list timer;/* Timer that triggers the check phy function */
88 unsigned int rxtail; /* Next entry in rxring to read */
89 unsigned int rxhead; /* Next entry in rxring to give a new buffer */
90 unsigned int rxfree; /* Number of free, allocated RX buffers */
91
92 unsigned int rxpending; /* Non-zero if there are still descriptors
93 * to be processed from a previous descriptor
94 * interrupt condition that has been cleared */
95
96 unsigned int txtail; /* Next TX descriptor to check status on */
97 unsigned int txhead; /* Next TX descriptor to use */
98
99 /* Number of free TX descriptors. This could be calculated from
100 * rxhead and rxtail if one descriptor were left unused to disambiguate
101 * full and empty conditions, but it's simpler to just keep track
102 * explicitly. */
103
104 unsigned int txfree;
105
106 unsigned int phy_ok; /* The PHY is currently powered on. */
107
108 /* PHY status (duplex is 1 for half, 2 for full,
109 * so that the default 0 indicates that neither has
110 * yet been configured). */
111
112 unsigned int link_up;
113 unsigned int speed;
114 unsigned int duplex;
115
116 tx_desc *txring;
117 rx_desc *rxring;
118 struct sk_buff *txskbs[TSI108_TXRING_LEN];
119 struct sk_buff *rxskbs[TSI108_RXRING_LEN];
120
121 dma_addr_t txdma, rxdma;
122
123 /* txlock nests in misclock and phy_lock */
124
125 spinlock_t txlock, misclock;
126
127 /* stats is used to hold the upper bits of each hardware counter,
128 * and tmpstats is used to hold the full values for returning
129 * to the caller of get_stats(). They must be separate in case
130 * an overflow interrupt occurs before the stats are consumed.
131 */
132
133 struct net_device_stats stats;
134 struct net_device_stats tmpstats;
135
136 /* These stats are kept separate in hardware, thus require individual
137 * fields for handling carry. They are combined in get_stats.
138 */
139
140 unsigned long rx_fcs; /* Add to rx_frame_errors */
141 unsigned long rx_short_fcs; /* Add to rx_frame_errors */
142 unsigned long rx_long_fcs; /* Add to rx_frame_errors */
143 unsigned long rx_underruns; /* Add to rx_length_errors */
144 unsigned long rx_overruns; /* Add to rx_length_errors */
145
146 unsigned long tx_coll_abort; /* Add to tx_aborted_errors/collisions */
147 unsigned long tx_pause_drop; /* Add to tx_aborted_errors */
148
149 unsigned long mc_hash[16];
150 u32 msg_enable; /* debug message level */
151 struct mii_if_info mii_if;
152 unsigned int init_media;
153};
154
155/* Structure for a device driver */
156
157static struct platform_driver tsi_eth_driver = {
158 .probe = tsi108_init_one,
159 .remove = tsi108_ether_remove,
160 .driver = {
161 .name = "tsi-ethernet",
162 },
163};
164
165static void tsi108_timed_checker(unsigned long dev_ptr);
166
167static void dump_eth_one(struct net_device *dev)
168{
169 struct tsi108_prv_data *data = netdev_priv(dev);
170
171 printk("Dumping %s...\n", dev->name);
172 printk("intstat %x intmask %x phy_ok %d"
173 " link %d speed %d duplex %d\n",
174 TSI_READ(TSI108_EC_INTSTAT),
175 TSI_READ(TSI108_EC_INTMASK), data->phy_ok,
176 data->link_up, data->speed, data->duplex);
177
178 printk("TX: head %d, tail %d, free %d, stat %x, estat %x, err %x\n",
179 data->txhead, data->txtail, data->txfree,
180 TSI_READ(TSI108_EC_TXSTAT),
181 TSI_READ(TSI108_EC_TXESTAT),
182 TSI_READ(TSI108_EC_TXERR));
183
184 printk("RX: head %d, tail %d, free %d, stat %x,"
185 " estat %x, err %x, pending %d\n\n",
186 data->rxhead, data->rxtail, data->rxfree,
187 TSI_READ(TSI108_EC_RXSTAT),
188 TSI_READ(TSI108_EC_RXESTAT),
189 TSI_READ(TSI108_EC_RXERR), data->rxpending);
190}
191
192/* Synchronization is needed between the thread and up/down events.
193 * Note that the PHY is accessed through the same registers for both
194 * interfaces, so this can't be made interface-specific.
195 */
196
197static DEFINE_SPINLOCK(phy_lock);
198
199static int tsi108_read_mii(struct tsi108_prv_data *data, int reg)
200{
201 unsigned i;
202
203 TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
204 (data->phy << TSI108_MAC_MII_ADDR_PHY) |
205 (reg << TSI108_MAC_MII_ADDR_REG));
206 TSI_WRITE_PHY(TSI108_MAC_MII_CMD, 0);
207 TSI_WRITE_PHY(TSI108_MAC_MII_CMD, TSI108_MAC_MII_CMD_READ);
208 for (i = 0; i < 100; i++) {
209 if (!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
210 (TSI108_MAC_MII_IND_NOTVALID | TSI108_MAC_MII_IND_BUSY)))
211 break;
212 udelay(10);
213 }
214
215 if (i == 100)
216 return 0xffff;
217 else
218 return (TSI_READ_PHY(TSI108_MAC_MII_DATAIN));
219}
220
221static void tsi108_write_mii(struct tsi108_prv_data *data,
222 int reg, u16 val)
223{
224 unsigned i = 100;
225 TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
226 (data->phy << TSI108_MAC_MII_ADDR_PHY) |
227 (reg << TSI108_MAC_MII_ADDR_REG));
228 TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val);
229 while (i--) {
230 if(!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
231 TSI108_MAC_MII_IND_BUSY))
232 break;
233 udelay(10);
234 }
235}
236
237static int tsi108_mdio_read(struct net_device *dev, int addr, int reg)
238{
239 struct tsi108_prv_data *data = netdev_priv(dev);
240 return tsi108_read_mii(data, reg);
241}
242
243static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val)
244{
245 struct tsi108_prv_data *data = netdev_priv(dev);
246 tsi108_write_mii(data, reg, val);
247}
248
249static inline void tsi108_write_tbi(struct tsi108_prv_data *data,
250 int reg, u16 val)
251{
252 unsigned i = 1000;
253 TSI_WRITE(TSI108_MAC_MII_ADDR,
254 (0x1e << TSI108_MAC_MII_ADDR_PHY)
255 | (reg << TSI108_MAC_MII_ADDR_REG));
256 TSI_WRITE(TSI108_MAC_MII_DATAOUT, val);
257 while(i--) {
258 if(!(TSI_READ(TSI108_MAC_MII_IND) & TSI108_MAC_MII_IND_BUSY))
259 return;
260 udelay(10);
261 }
262 printk(KERN_ERR "%s function time out \n", __FUNCTION__);
263}
264
265static int mii_speed(struct mii_if_info *mii)
266{
267 int advert, lpa, val, media;
268 int lpa2 = 0;
269 int speed;
270
271 if (!mii_link_ok(mii))
272 return 0;
273
274 val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
275 if ((val & BMSR_ANEGCOMPLETE) == 0)
276 return 0;
277
278 advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
279 lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
280 media = mii_nway_result(advert & lpa);
281
282 if (mii->supports_gmii)
283 lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000);
284
285 speed = lpa2 & (LPA_1000FULL | LPA_1000HALF) ? 1000 :
286 (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 100 : 10);
287 return speed;
288}
289
290static void tsi108_check_phy(struct net_device *dev)
291{
292 struct tsi108_prv_data *data = netdev_priv(dev);
293 u32 mac_cfg2_reg, portctrl_reg;
294 u32 duplex;
295 u32 speed;
296 unsigned long flags;
297
298 /* Do a dummy read, as for some reason the first read
299 * after a link becomes up returns link down, even if
300 * it's been a while since the link came up.
301 */
302
303 spin_lock_irqsave(&phy_lock, flags);
304
305 if (!data->phy_ok)
306 goto out;
307
308 tsi108_read_mii(data, MII_BMSR);
309
310 duplex = mii_check_media(&data->mii_if, netif_msg_link(data), data->init_media);
311 data->init_media = 0;
312
313 if (netif_carrier_ok(dev)) {
314
315 speed = mii_speed(&data->mii_if);
316
317 if ((speed != data->speed) || duplex) {
318
319 mac_cfg2_reg = TSI_READ(TSI108_MAC_CFG2);
320 portctrl_reg = TSI_READ(TSI108_EC_PORTCTRL);
321
322 mac_cfg2_reg &= ~TSI108_MAC_CFG2_IFACE_MASK;
323
324 if (speed == 1000) {
325 mac_cfg2_reg |= TSI108_MAC_CFG2_GIG;
326 portctrl_reg &= ~TSI108_EC_PORTCTRL_NOGIG;
327 } else {
328 mac_cfg2_reg |= TSI108_MAC_CFG2_NOGIG;
329 portctrl_reg |= TSI108_EC_PORTCTRL_NOGIG;
330 }
331
332 data->speed = speed;
333
334 if (data->mii_if.full_duplex) {
335 mac_cfg2_reg |= TSI108_MAC_CFG2_FULLDUPLEX;
336 portctrl_reg &= ~TSI108_EC_PORTCTRL_HALFDUPLEX;
337 data->duplex = 2;
338 } else {
339 mac_cfg2_reg &= ~TSI108_MAC_CFG2_FULLDUPLEX;
340 portctrl_reg |= TSI108_EC_PORTCTRL_HALFDUPLEX;
341 data->duplex = 1;
342 }
343
344 TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg);
345 TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg);
346
347 if (data->link_up == 0) {
348 /* The manual says it can take 3-4 usecs for the speed change
349 * to take effect.
350 */
351 udelay(5);
352
353 spin_lock(&data->txlock);
354 if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
355 netif_wake_queue(dev);
356
357 data->link_up = 1;
358 spin_unlock(&data->txlock);
359 }
360 }
361
362 } else {
363 if (data->link_up == 1) {
364 netif_stop_queue(dev);
365 data->link_up = 0;
366 printk(KERN_NOTICE "%s : link is down\n", dev->name);
367 }
368
369 goto out;
370 }
371
372
373out:
374 spin_unlock_irqrestore(&phy_lock, flags);
375}
376
377static inline void
378tsi108_stat_carry_one(int carry, int carry_bit, int carry_shift,
379 unsigned long *upper)
380{
381 if (carry & carry_bit)
382 *upper += carry_shift;
383}
384
385static void tsi108_stat_carry(struct net_device *dev)
386{
387 struct tsi108_prv_data *data = netdev_priv(dev);
388 u32 carry1, carry2;
389
390 spin_lock_irq(&data->misclock);
391
392 carry1 = TSI_READ(TSI108_STAT_CARRY1);
393 carry2 = TSI_READ(TSI108_STAT_CARRY2);
394
395 TSI_WRITE(TSI108_STAT_CARRY1, carry1);
396 TSI_WRITE(TSI108_STAT_CARRY2, carry2);
397
398 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXBYTES,
399 TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
400
401 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXPKTS,
402 TSI108_STAT_RXPKTS_CARRY,
403 &data->stats.rx_packets);
404
405 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFCS,
406 TSI108_STAT_RXFCS_CARRY, &data->rx_fcs);
407
408 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXMCAST,
409 TSI108_STAT_RXMCAST_CARRY,
410 &data->stats.multicast);
411
412 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXALIGN,
413 TSI108_STAT_RXALIGN_CARRY,
414 &data->stats.rx_frame_errors);
415
416 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXLENGTH,
417 TSI108_STAT_RXLENGTH_CARRY,
418 &data->stats.rx_length_errors);
419
420 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXRUNT,
421 TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
422
423 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJUMBO,
424 TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
425
426 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFRAG,
427 TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
428
429 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJABBER,
430 TSI108_STAT_RXJABBER_CARRY, &data->rx_long_fcs);
431
432 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXDROP,
433 TSI108_STAT_RXDROP_CARRY,
434 &data->stats.rx_missed_errors);
435
436 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXBYTES,
437 TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
438
439 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPKTS,
440 TSI108_STAT_TXPKTS_CARRY,
441 &data->stats.tx_packets);
442
443 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXDEF,
444 TSI108_STAT_TXEXDEF_CARRY,
445 &data->stats.tx_aborted_errors);
446
447 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXCOL,
448 TSI108_STAT_TXEXCOL_CARRY, &data->tx_coll_abort);
449
450 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXTCOL,
451 TSI108_STAT_TXTCOL_CARRY,
452 &data->stats.collisions);
453
454 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPAUSE,
455 TSI108_STAT_TXPAUSEDROP_CARRY,
456 &data->tx_pause_drop);
457
458 spin_unlock_irq(&data->misclock);
459}
460
461/* Read a stat counter atomically with respect to carries.
462 * data->misclock must be held.
463 */
464static inline unsigned long
465tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit,
466 int carry_shift, unsigned long *upper)
467{
468 int carryreg;
469 unsigned long val;
470
471 if (reg < 0xb0)
472 carryreg = TSI108_STAT_CARRY1;
473 else
474 carryreg = TSI108_STAT_CARRY2;
475
476 again:
477 val = TSI_READ(reg) | *upper;
478
479 /* Check to see if it overflowed, but the interrupt hasn't
480 * been serviced yet. If so, handle the carry here, and
481 * try again.
482 */
483
484 if (unlikely(TSI_READ(carryreg) & carry_bit)) {
485 *upper += carry_shift;
486 TSI_WRITE(carryreg, carry_bit);
487 goto again;
488 }
489
490 return val;
491}
492
493static struct net_device_stats *tsi108_get_stats(struct net_device *dev)
494{
495 unsigned long excol;
496
497 struct tsi108_prv_data *data = netdev_priv(dev);
498 spin_lock_irq(&data->misclock);
499
500 data->tmpstats.rx_packets =
501 tsi108_read_stat(data, TSI108_STAT_RXPKTS,
502 TSI108_STAT_CARRY1_RXPKTS,
503 TSI108_STAT_RXPKTS_CARRY, &data->stats.rx_packets);
504
505 data->tmpstats.tx_packets =
506 tsi108_read_stat(data, TSI108_STAT_TXPKTS,
507 TSI108_STAT_CARRY2_TXPKTS,
508 TSI108_STAT_TXPKTS_CARRY, &data->stats.tx_packets);
509
510 data->tmpstats.rx_bytes =
511 tsi108_read_stat(data, TSI108_STAT_RXBYTES,
512 TSI108_STAT_CARRY1_RXBYTES,
513 TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
514
515 data->tmpstats.tx_bytes =
516 tsi108_read_stat(data, TSI108_STAT_TXBYTES,
517 TSI108_STAT_CARRY2_TXBYTES,
518 TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
519
520 data->tmpstats.multicast =
521 tsi108_read_stat(data, TSI108_STAT_RXMCAST,
522 TSI108_STAT_CARRY1_RXMCAST,
523 TSI108_STAT_RXMCAST_CARRY, &data->stats.multicast);
524
525 excol = tsi108_read_stat(data, TSI108_STAT_TXEXCOL,
526 TSI108_STAT_CARRY2_TXEXCOL,
527 TSI108_STAT_TXEXCOL_CARRY,
528 &data->tx_coll_abort);
529
530 data->tmpstats.collisions =
531 tsi108_read_stat(data, TSI108_STAT_TXTCOL,
532 TSI108_STAT_CARRY2_TXTCOL,
533 TSI108_STAT_TXTCOL_CARRY, &data->stats.collisions);
534
535 data->tmpstats.collisions += excol;
536
537 data->tmpstats.rx_length_errors =
538 tsi108_read_stat(data, TSI108_STAT_RXLENGTH,
539 TSI108_STAT_CARRY1_RXLENGTH,
540 TSI108_STAT_RXLENGTH_CARRY,
541 &data->stats.rx_length_errors);
542
543 data->tmpstats.rx_length_errors +=
544 tsi108_read_stat(data, TSI108_STAT_RXRUNT,
545 TSI108_STAT_CARRY1_RXRUNT,
546 TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
547
548 data->tmpstats.rx_length_errors +=
549 tsi108_read_stat(data, TSI108_STAT_RXJUMBO,
550 TSI108_STAT_CARRY1_RXJUMBO,
551 TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
552
553 data->tmpstats.rx_frame_errors =
554 tsi108_read_stat(data, TSI108_STAT_RXALIGN,
555 TSI108_STAT_CARRY1_RXALIGN,
556 TSI108_STAT_RXALIGN_CARRY,
557 &data->stats.rx_frame_errors);
558
559 data->tmpstats.rx_frame_errors +=
560 tsi108_read_stat(data, TSI108_STAT_RXFCS,
561 TSI108_STAT_CARRY1_RXFCS, TSI108_STAT_RXFCS_CARRY,
562 &data->rx_fcs);
563
564 data->tmpstats.rx_frame_errors +=
565 tsi108_read_stat(data, TSI108_STAT_RXFRAG,
566 TSI108_STAT_CARRY1_RXFRAG,
567 TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
568
569 data->tmpstats.rx_missed_errors =
570 tsi108_read_stat(data, TSI108_STAT_RXDROP,
571 TSI108_STAT_CARRY1_RXDROP,
572 TSI108_STAT_RXDROP_CARRY,
573 &data->stats.rx_missed_errors);
574
575 /* These three are maintained by software. */
576 data->tmpstats.rx_fifo_errors = data->stats.rx_fifo_errors;
577 data->tmpstats.rx_crc_errors = data->stats.rx_crc_errors;
578
579 data->tmpstats.tx_aborted_errors =
580 tsi108_read_stat(data, TSI108_STAT_TXEXDEF,
581 TSI108_STAT_CARRY2_TXEXDEF,
582 TSI108_STAT_TXEXDEF_CARRY,
583 &data->stats.tx_aborted_errors);
584
585 data->tmpstats.tx_aborted_errors +=
586 tsi108_read_stat(data, TSI108_STAT_TXPAUSEDROP,
587 TSI108_STAT_CARRY2_TXPAUSE,
588 TSI108_STAT_TXPAUSEDROP_CARRY,
589 &data->tx_pause_drop);
590
591 data->tmpstats.tx_aborted_errors += excol;
592
593 data->tmpstats.tx_errors = data->tmpstats.tx_aborted_errors;
594 data->tmpstats.rx_errors = data->tmpstats.rx_length_errors +
595 data->tmpstats.rx_crc_errors +
596 data->tmpstats.rx_frame_errors +
597 data->tmpstats.rx_fifo_errors + data->tmpstats.rx_missed_errors;
598
599 spin_unlock_irq(&data->misclock);
600 return &data->tmpstats;
601}
602
603static void tsi108_restart_rx(struct tsi108_prv_data * data, struct net_device *dev)
604{
605 TSI_WRITE(TSI108_EC_RXQ_PTRHIGH,
606 TSI108_EC_RXQ_PTRHIGH_VALID);
607
608 TSI_WRITE(TSI108_EC_RXCTRL, TSI108_EC_RXCTRL_GO
609 | TSI108_EC_RXCTRL_QUEUE0);
610}
611
612static void tsi108_restart_tx(struct tsi108_prv_data * data)
613{
614 TSI_WRITE(TSI108_EC_TXQ_PTRHIGH,
615 TSI108_EC_TXQ_PTRHIGH_VALID);
616
617 TSI_WRITE(TSI108_EC_TXCTRL, TSI108_EC_TXCTRL_IDLEINT |
618 TSI108_EC_TXCTRL_GO | TSI108_EC_TXCTRL_QUEUE0);
619}
620
621/* txlock must be held by caller, with IRQs disabled, and
622 * with permission to re-enable them when the lock is dropped.
623 */
624static void tsi108_complete_tx(struct net_device *dev)
625{
626 struct tsi108_prv_data *data = netdev_priv(dev);
627 int tx;
628 struct sk_buff *skb;
629 int release = 0;
630
631 while (!data->txfree || data->txhead != data->txtail) {
632 tx = data->txtail;
633
634 if (data->txring[tx].misc & TSI108_TX_OWN)
635 break;
636
637 skb = data->txskbs[tx];
638
639 if (!(data->txring[tx].misc & TSI108_TX_OK))
640 printk("%s: bad tx packet, misc %x\n",
641 dev->name, data->txring[tx].misc);
642
643 data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
644 data->txfree++;
645
646 if (data->txring[tx].misc & TSI108_TX_EOF) {
647 dev_kfree_skb_any(skb);
648 release++;
649 }
650 }
651
652 if (release) {
653 if (is_valid_ether_addr(dev->dev_addr) && data->link_up)
654 netif_wake_queue(dev);
655 }
656}
657
658static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev)
659{
660 struct tsi108_prv_data *data = netdev_priv(dev);
661 int frags = skb_shinfo(skb)->nr_frags + 1;
662 int i;
663
664 if (!data->phy_ok && net_ratelimit())
665 printk(KERN_ERR "%s: Transmit while PHY is down!\n", dev->name);
666
667 if (!data->link_up) {
668 printk(KERN_ERR "%s: Transmit while link is down!\n",
669 dev->name);
670 netif_stop_queue(dev);
671 return NETDEV_TX_BUSY;
672 }
673
674 if (data->txfree < MAX_SKB_FRAGS + 1) {
675 netif_stop_queue(dev);
676
677 if (net_ratelimit())
678 printk(KERN_ERR "%s: Transmit with full tx ring!\n",
679 dev->name);
680 return NETDEV_TX_BUSY;
681 }
682
683 if (data->txfree - frags < MAX_SKB_FRAGS + 1) {
684 netif_stop_queue(dev);
685 }
686
687 spin_lock_irq(&data->txlock);
688
689 for (i = 0; i < frags; i++) {
690 int misc = 0;
691 int tx = data->txhead;
692
693 /* This is done to mark every TSI108_TX_INT_FREQ tx buffers with
694 * the interrupt bit. TX descriptor-complete interrupts are
695 * enabled when the queue fills up, and masked when there is
696 * still free space. This way, when saturating the outbound
697 * link, the tx interrupts are kept to a reasonable level.
698 * When the queue is not full, reclamation of skbs still occurs
699 * as new packets are transmitted, or on a queue-empty
700 * interrupt.
701 */
702
703 if ((tx % TSI108_TX_INT_FREQ == 0) &&
704 ((TSI108_TXRING_LEN - data->txfree) >= TSI108_TX_INT_FREQ))
705 misc = TSI108_TX_INT;
706
707 data->txskbs[tx] = skb;
708
709 if (i == 0) {
710 data->txring[tx].buf0 = dma_map_single(NULL, skb->data,
711 skb->len - skb->data_len, DMA_TO_DEVICE);
712 data->txring[tx].len = skb->len - skb->data_len;
713 misc |= TSI108_TX_SOF;
714 } else {
715 skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
716
717 data->txring[tx].buf0 =
718 dma_map_page(NULL, frag->page, frag->page_offset,
719 frag->size, DMA_TO_DEVICE);
720 data->txring[tx].len = frag->size;
721 }
722
723 if (i == frags - 1)
724 misc |= TSI108_TX_EOF;
725
726 if (netif_msg_pktdata(data)) {
727 int i;
728 printk("%s: Tx Frame contents (%d)\n", dev->name,
729 skb->len);
730 for (i = 0; i < skb->len; i++)
731 printk(" %2.2x", skb->data[i]);
732 printk(".\n");
733 }
734 data->txring[tx].misc = misc | TSI108_TX_OWN;
735
736 data->txhead = (data->txhead + 1) % TSI108_TXRING_LEN;
737 data->txfree--;
738 }
739
740 tsi108_complete_tx(dev);
741
742 /* This must be done after the check for completed tx descriptors,
743 * so that the tail pointer is correct.
744 */
745
746 if (!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_QUEUE0))
747 tsi108_restart_tx(data);
748
749 spin_unlock_irq(&data->txlock);
750 return NETDEV_TX_OK;
751}
752
753static int tsi108_complete_rx(struct net_device *dev, int budget)
754{
755 struct tsi108_prv_data *data = netdev_priv(dev);
756 int done = 0;
757
758 while (data->rxfree && done != budget) {
759 int rx = data->rxtail;
760 struct sk_buff *skb;
761
762 if (data->rxring[rx].misc & TSI108_RX_OWN)
763 break;
764
765 skb = data->rxskbs[rx];
766 data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
767 data->rxfree--;
768 done++;
769
770 if (data->rxring[rx].misc & TSI108_RX_BAD) {
771 spin_lock_irq(&data->misclock);
772
773 if (data->rxring[rx].misc & TSI108_RX_CRC)
774 data->stats.rx_crc_errors++;
775 if (data->rxring[rx].misc & TSI108_RX_OVER)
776 data->stats.rx_fifo_errors++;
777
778 spin_unlock_irq(&data->misclock);
779
780 dev_kfree_skb_any(skb);
781 continue;
782 }
783 if (netif_msg_pktdata(data)) {
784 int i;
785 printk("%s: Rx Frame contents (%d)\n",
786 dev->name, data->rxring[rx].len);
787 for (i = 0; i < data->rxring[rx].len; i++)
788 printk(" %2.2x", skb->data[i]);
789 printk(".\n");
790 }
791
792 skb->dev = dev;
793 skb_put(skb, data->rxring[rx].len);
794 skb->protocol = eth_type_trans(skb, dev);
795 netif_receive_skb(skb);
796 dev->last_rx = jiffies;
797 }
798
799 return done;
800}
801
802static int tsi108_refill_rx(struct net_device *dev, int budget)
803{
804 struct tsi108_prv_data *data = netdev_priv(dev);
805 int done = 0;
806
807 while (data->rxfree != TSI108_RXRING_LEN && done != budget) {
808 int rx = data->rxhead;
809 struct sk_buff *skb;
810
811 data->rxskbs[rx] = skb = dev_alloc_skb(TSI108_RXBUF_SIZE + 2);
812 if (!skb)
813 break;
814
815 skb_reserve(skb, 2); /* Align the data on a 4-byte boundary. */
816
817 data->rxring[rx].buf0 = dma_map_single(NULL, skb->data,
818 TSI108_RX_SKB_SIZE,
819 DMA_FROM_DEVICE);
820
821 /* Sometimes the hardware sets blen to zero after packet
822 * reception, even though the manual says that it's only ever
823 * modified by the driver.
824 */
825
826 data->rxring[rx].blen = TSI108_RX_SKB_SIZE;
827 data->rxring[rx].misc = TSI108_RX_OWN | TSI108_RX_INT;
828
829 data->rxhead = (data->rxhead + 1) % TSI108_RXRING_LEN;
830 data->rxfree++;
831 done++;
832 }
833
834 if (done != 0 && !(TSI_READ(TSI108_EC_RXSTAT) &
835 TSI108_EC_RXSTAT_QUEUE0))
836 tsi108_restart_rx(data, dev);
837
838 return done;
839}
840
841static int tsi108_poll(struct net_device *dev, int *budget)
842{
843 struct tsi108_prv_data *data = netdev_priv(dev);
844 u32 estat = TSI_READ(TSI108_EC_RXESTAT);
845 u32 intstat = TSI_READ(TSI108_EC_INTSTAT);
846 int total_budget = min(*budget, dev->quota);
847 int num_received = 0, num_filled = 0, budget_used;
848
849 intstat &= TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
850 TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | TSI108_INT_RXWAIT;
851
852 TSI_WRITE(TSI108_EC_RXESTAT, estat);
853 TSI_WRITE(TSI108_EC_INTSTAT, intstat);
854
855 if (data->rxpending || (estat & TSI108_EC_RXESTAT_Q0_DESCINT))
856 num_received = tsi108_complete_rx(dev, total_budget);
857
858 /* This should normally fill no more slots than the number of
859 * packets received in tsi108_complete_rx(). The exception
860 * is when we previously ran out of memory for RX SKBs. In that
861 * case, it's helpful to obey the budget, not only so that the
862 * CPU isn't hogged, but so that memory (which may still be low)
863 * is not hogged by one device.
864 *
865 * A work unit is considered to be two SKBs to allow us to catch
866 * up when the ring has shrunk due to out-of-memory but we're
867 * still removing the full budget's worth of packets each time.
868 */
869
870 if (data->rxfree < TSI108_RXRING_LEN)
871 num_filled = tsi108_refill_rx(dev, total_budget * 2);
872
873 if (intstat & TSI108_INT_RXERROR) {
874 u32 err = TSI_READ(TSI108_EC_RXERR);
875 TSI_WRITE(TSI108_EC_RXERR, err);
876
877 if (err) {
878 if (net_ratelimit())
879 printk(KERN_DEBUG "%s: RX error %x\n",
880 dev->name, err);
881
882 if (!(TSI_READ(TSI108_EC_RXSTAT) &
883 TSI108_EC_RXSTAT_QUEUE0))
884 tsi108_restart_rx(data, dev);
885 }
886 }
887
888 if (intstat & TSI108_INT_RXOVERRUN) {
889 spin_lock_irq(&data->misclock);
890 data->stats.rx_fifo_errors++;
891 spin_unlock_irq(&data->misclock);
892 }
893
894 budget_used = max(num_received, num_filled / 2);
895
896 *budget -= budget_used;
897 dev->quota -= budget_used;
898
899 if (budget_used != total_budget) {
900 data->rxpending = 0;
901 netif_rx_complete(dev);
902
903 TSI_WRITE(TSI108_EC_INTMASK,
904 TSI_READ(TSI108_EC_INTMASK)
905 & ~(TSI108_INT_RXQUEUE0
906 | TSI108_INT_RXTHRESH |
907 TSI108_INT_RXOVERRUN |
908 TSI108_INT_RXERROR |
909 TSI108_INT_RXWAIT));
910
911 /* IRQs are level-triggered, so no need to re-check */
912 return 0;
913 } else {
914 data->rxpending = 1;
915 }
916
917 return 1;
918}
919
920static void tsi108_rx_int(struct net_device *dev)
921{
922 struct tsi108_prv_data *data = netdev_priv(dev);
923
924 /* A race could cause dev to already be scheduled, so it's not an
925 * error if that happens (and interrupts shouldn't be re-masked,
926 * because that can cause harmful races, if poll has already
927 * unmasked them but not cleared LINK_STATE_SCHED).
928 *
929 * This can happen if this code races with tsi108_poll(), which masks
930 * the interrupts after tsi108_irq_one() read the mask, but before
931 * netif_rx_schedule is called. It could also happen due to calls
932 * from tsi108_check_rxring().
933 */
934
935 if (netif_rx_schedule_prep(dev)) {
936 /* Mask, rather than ack, the receive interrupts. The ack
937 * will happen in tsi108_poll().
938 */
939
940 TSI_WRITE(TSI108_EC_INTMASK,
941 TSI_READ(TSI108_EC_INTMASK) |
942 TSI108_INT_RXQUEUE0
943 | TSI108_INT_RXTHRESH |
944 TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR |
945 TSI108_INT_RXWAIT);
946 __netif_rx_schedule(dev);
947 } else {
948 if (!netif_running(dev)) {
949 /* This can happen if an interrupt occurs while the
950 * interface is being brought down, as the START
951 * bit is cleared before the stop function is called.
952 *
953 * In this case, the interrupts must be masked, or
954 * they will continue indefinitely.
955 *
956 * There's a race here if the interface is brought down
957 * and then up in rapid succession, as the device could
958 * be made running after the above check and before
959 * the masking below. This will only happen if the IRQ
960 * thread has a lower priority than the task brining
961 * up the interface. Fixing this race would likely
962 * require changes in generic code.
963 */
964
965 TSI_WRITE(TSI108_EC_INTMASK,
966 TSI_READ
967 (TSI108_EC_INTMASK) |
968 TSI108_INT_RXQUEUE0 |
969 TSI108_INT_RXTHRESH |
970 TSI108_INT_RXOVERRUN |
971 TSI108_INT_RXERROR |
972 TSI108_INT_RXWAIT);
973 }
974 }
975}
976
977/* If the RX ring has run out of memory, try periodically
978 * to allocate some more, as otherwise poll would never
979 * get called (apart from the initial end-of-queue condition).
980 *
981 * This is called once per second (by default) from the thread.
982 */
983
984static void tsi108_check_rxring(struct net_device *dev)
985{
986 struct tsi108_prv_data *data = netdev_priv(dev);
987
988 /* A poll is scheduled, as opposed to caling tsi108_refill_rx
989 * directly, so as to keep the receive path single-threaded
990 * (and thus not needing a lock).
991 */
992
993 if (netif_running(dev) && data->rxfree < TSI108_RXRING_LEN / 4)
994 tsi108_rx_int(dev);
995}
996
997static void tsi108_tx_int(struct net_device *dev)
998{
999 struct tsi108_prv_data *data = netdev_priv(dev);
1000 u32 estat = TSI_READ(TSI108_EC_TXESTAT);
1001
1002 TSI_WRITE(TSI108_EC_TXESTAT, estat);
1003 TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_TXQUEUE0 |
1004 TSI108_INT_TXIDLE | TSI108_INT_TXERROR);
1005 if (estat & TSI108_EC_TXESTAT_Q0_ERR) {
1006 u32 err = TSI_READ(TSI108_EC_TXERR);
1007 TSI_WRITE(TSI108_EC_TXERR, err);
1008
1009 if (err && net_ratelimit())
1010 printk(KERN_ERR "%s: TX error %x\n", dev->name, err);
1011 }
1012
1013 if (estat & (TSI108_EC_TXESTAT_Q0_DESCINT | TSI108_EC_TXESTAT_Q0_EOQ)) {
1014 spin_lock(&data->txlock);
1015 tsi108_complete_tx(dev);
1016 spin_unlock(&data->txlock);
1017 }
1018}
1019
1020
1021static irqreturn_t tsi108_irq(int irq, void *dev_id)
1022{
1023 struct net_device *dev = dev_id;
1024 struct tsi108_prv_data *data = netdev_priv(dev);
1025 u32 stat = TSI_READ(TSI108_EC_INTSTAT);
1026
1027 if (!(stat & TSI108_INT_ANY))
1028 return IRQ_NONE; /* Not our interrupt */
1029
1030 stat &= ~TSI_READ(TSI108_EC_INTMASK);
1031
1032 if (stat & (TSI108_INT_TXQUEUE0 | TSI108_INT_TXIDLE |
1033 TSI108_INT_TXERROR))
1034 tsi108_tx_int(dev);
1035 if (stat & (TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
1036 TSI108_INT_RXWAIT | TSI108_INT_RXOVERRUN |
1037 TSI108_INT_RXERROR))
1038 tsi108_rx_int(dev);
1039
1040 if (stat & TSI108_INT_SFN) {
1041 if (net_ratelimit())
1042 printk(KERN_DEBUG "%s: SFN error\n", dev->name);
1043 TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_SFN);
1044 }
1045
1046 if (stat & TSI108_INT_STATCARRY) {
1047 tsi108_stat_carry(dev);
1048 TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_STATCARRY);
1049 }
1050
1051 return IRQ_HANDLED;
1052}
1053
1054static void tsi108_stop_ethernet(struct net_device *dev)
1055{
1056 struct tsi108_prv_data *data = netdev_priv(dev);
1057 int i = 1000;
1058 /* Disable all TX and RX queues ... */
1059 TSI_WRITE(TSI108_EC_TXCTRL, 0);
1060 TSI_WRITE(TSI108_EC_RXCTRL, 0);
1061
1062 /* ...and wait for them to become idle */
1063 while(i--) {
1064 if(!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_ACTIVE))
1065 break;
1066 udelay(10);
1067 }
1068 i = 1000;
1069 while(i--){
1070 if(!(TSI_READ(TSI108_EC_RXSTAT) & TSI108_EC_RXSTAT_ACTIVE))
1071 return;
1072 udelay(10);
1073 }
1074 printk(KERN_ERR "%s function time out \n", __FUNCTION__);
1075}
1076
1077static void tsi108_reset_ether(struct tsi108_prv_data * data)
1078{
1079 TSI_WRITE(TSI108_MAC_CFG1, TSI108_MAC_CFG1_SOFTRST);
1080 udelay(100);
1081 TSI_WRITE(TSI108_MAC_CFG1, 0);
1082
1083 TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATRST);
1084 udelay(100);
1085 TSI_WRITE(TSI108_EC_PORTCTRL,
1086 TSI_READ(TSI108_EC_PORTCTRL) &
1087 ~TSI108_EC_PORTCTRL_STATRST);
1088
1089 TSI_WRITE(TSI108_EC_TXCFG, TSI108_EC_TXCFG_RST);
1090 udelay(100);
1091 TSI_WRITE(TSI108_EC_TXCFG,
1092 TSI_READ(TSI108_EC_TXCFG) &
1093 ~TSI108_EC_TXCFG_RST);
1094
1095 TSI_WRITE(TSI108_EC_RXCFG, TSI108_EC_RXCFG_RST);
1096 udelay(100);
1097 TSI_WRITE(TSI108_EC_RXCFG,
1098 TSI_READ(TSI108_EC_RXCFG) &
1099 ~TSI108_EC_RXCFG_RST);
1100
1101 TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
1102 TSI_READ(TSI108_MAC_MII_MGMT_CFG) |
1103 TSI108_MAC_MII_MGMT_RST);
1104 udelay(100);
1105 TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
1106 (TSI_READ(TSI108_MAC_MII_MGMT_CFG) &
1107 ~(TSI108_MAC_MII_MGMT_RST |
1108 TSI108_MAC_MII_MGMT_CLK)) | 0x07);
1109}
1110
1111static int tsi108_get_mac(struct net_device *dev)
1112{
1113 struct tsi108_prv_data *data = netdev_priv(dev);
1114 u32 word1 = TSI_READ(TSI108_MAC_ADDR1);
1115 u32 word2 = TSI_READ(TSI108_MAC_ADDR2);
1116
1117 /* Note that the octets are reversed from what the manual says,
1118 * producing an even weirder ordering...
1119 */
1120 if (word2 == 0 && word1 == 0) {
1121 dev->dev_addr[0] = 0x00;
1122 dev->dev_addr[1] = 0x06;
1123 dev->dev_addr[2] = 0xd2;
1124 dev->dev_addr[3] = 0x00;
1125 dev->dev_addr[4] = 0x00;
1126 if (0x8 == data->phy)
1127 dev->dev_addr[5] = 0x01;
1128 else
1129 dev->dev_addr[5] = 0x02;
1130
1131 word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
1132
1133 word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
1134 (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
1135
1136 TSI_WRITE(TSI108_MAC_ADDR1, word1);
1137 TSI_WRITE(TSI108_MAC_ADDR2, word2);
1138 } else {
1139 dev->dev_addr[0] = (word2 >> 16) & 0xff;
1140 dev->dev_addr[1] = (word2 >> 24) & 0xff;
1141 dev->dev_addr[2] = (word1 >> 0) & 0xff;
1142 dev->dev_addr[3] = (word1 >> 8) & 0xff;
1143 dev->dev_addr[4] = (word1 >> 16) & 0xff;
1144 dev->dev_addr[5] = (word1 >> 24) & 0xff;
1145 }
1146
1147 if (!is_valid_ether_addr(dev->dev_addr)) {
1148 printk("KERN_ERR: word1: %08x, word2: %08x\n", word1, word2);
1149 return -EINVAL;
1150 }
1151
1152 return 0;
1153}
1154
1155static int tsi108_set_mac(struct net_device *dev, void *addr)
1156{
1157 struct tsi108_prv_data *data = netdev_priv(dev);
1158 u32 word1, word2;
1159 int i;
1160
1161 if (!is_valid_ether_addr(addr))
1162 return -EINVAL;
1163
1164 for (i = 0; i < 6; i++)
1165 /* +2 is for the offset of the HW addr type */
1166 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1167
1168 word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
1169
1170 word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
1171 (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
1172
1173 spin_lock_irq(&data->misclock);
1174 TSI_WRITE(TSI108_MAC_ADDR1, word1);
1175 TSI_WRITE(TSI108_MAC_ADDR2, word2);
1176 spin_lock(&data->txlock);
1177
1178 if (data->txfree && data->link_up)
1179 netif_wake_queue(dev);
1180
1181 spin_unlock(&data->txlock);
1182 spin_unlock_irq(&data->misclock);
1183 return 0;
1184}
1185
1186/* Protected by dev->xmit_lock. */
1187static void tsi108_set_rx_mode(struct net_device *dev)
1188{
1189 struct tsi108_prv_data *data = netdev_priv(dev);
1190 u32 rxcfg = TSI_READ(TSI108_EC_RXCFG);
1191
1192 if (dev->flags & IFF_PROMISC) {
1193 rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH);
1194 rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE;
1195 goto out;
1196 }
1197
1198 rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE);
1199
1200 if (dev->flags & IFF_ALLMULTI || dev->mc_count) {
1201 int i;
1202 struct dev_mc_list *mc = dev->mc_list;
1203 rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH;
1204
1205 memset(data->mc_hash, 0, sizeof(data->mc_hash));
1206
1207 while (mc) {
1208 u32 hash, crc;
1209
1210 if (mc->dmi_addrlen == 6) {
1211 crc = ether_crc(6, mc->dmi_addr);
1212 hash = crc >> 23;
1213
1214 __set_bit(hash, &data->mc_hash[0]);
1215 } else {
1216 printk(KERN_ERR
1217 "%s: got multicast address of length %d "
1218 "instead of 6.\n", dev->name,
1219 mc->dmi_addrlen);
1220 }
1221
1222 mc = mc->next;
1223 }
1224
1225 TSI_WRITE(TSI108_EC_HASHADDR,
1226 TSI108_EC_HASHADDR_AUTOINC |
1227 TSI108_EC_HASHADDR_MCAST);
1228
1229 for (i = 0; i < 16; i++) {
1230 /* The manual says that the hardware may drop
1231 * back-to-back writes to the data register.
1232 */
1233 udelay(1);
1234 TSI_WRITE(TSI108_EC_HASHDATA,
1235 data->mc_hash[i]);
1236 }
1237 }
1238
1239 out:
1240 TSI_WRITE(TSI108_EC_RXCFG, rxcfg);
1241}
1242
1243static void tsi108_init_phy(struct net_device *dev)
1244{
1245 struct tsi108_prv_data *data = netdev_priv(dev);
1246 u32 i = 0;
1247 u16 phyval = 0;
1248 unsigned long flags;
1249
1250 spin_lock_irqsave(&phy_lock, flags);
1251
1252 tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
1253 while (i--){
1254 if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
1255 break;
1256 udelay(10);
1257 }
1258 if (i == 0)
1259 printk(KERN_ERR "%s function time out \n", __FUNCTION__);
1260
1261#if (TSI108_PHY_TYPE == PHY_BCM54XX) /* Broadcom BCM54xx PHY */
1262 tsi108_write_mii(data, 0x09, 0x0300);
1263 tsi108_write_mii(data, 0x10, 0x1020);
1264 tsi108_write_mii(data, 0x1c, 0x8c00);
1265#endif
1266
1267 tsi108_write_mii(data,
1268 MII_BMCR,
1269 BMCR_ANENABLE | BMCR_ANRESTART);
1270 while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
1271 cpu_relax();
1272
1273 /* Set G/MII mode and receive clock select in TBI control #2. The
1274 * second port won't work if this isn't done, even though we don't
1275 * use TBI mode.
1276 */
1277
1278 tsi108_write_tbi(data, 0x11, 0x30);
1279
1280 /* FIXME: It seems to take more than 2 back-to-back reads to the
1281 * PHY_STAT register before the link up status bit is set.
1282 */
1283
1284 data->link_up = 1;
1285
1286 while (!((phyval = tsi108_read_mii(data, MII_BMSR)) &
1287 BMSR_LSTATUS)) {
1288 if (i++ > (MII_READ_DELAY / 10)) {
1289 data->link_up = 0;
1290 break;
1291 }
1292 spin_unlock_irqrestore(&phy_lock, flags);
1293 msleep(10);
1294 spin_lock_irqsave(&phy_lock, flags);
1295 }
1296
1297 printk(KERN_DEBUG "PHY_STAT reg contains %08x\n", phyval);
1298 data->phy_ok = 1;
1299 data->init_media = 1;
1300 spin_unlock_irqrestore(&phy_lock, flags);
1301}
1302
1303static void tsi108_kill_phy(struct net_device *dev)
1304{
1305 struct tsi108_prv_data *data = netdev_priv(dev);
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&phy_lock, flags);
1309 tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN);
1310 data->phy_ok = 0;
1311 spin_unlock_irqrestore(&phy_lock, flags);
1312}
1313
1314static int tsi108_open(struct net_device *dev)
1315{
1316 int i;
1317 struct tsi108_prv_data *data = netdev_priv(dev);
1318 unsigned int rxring_size = TSI108_RXRING_LEN * sizeof(rx_desc);
1319 unsigned int txring_size = TSI108_TXRING_LEN * sizeof(tx_desc);
1320
1321 i = request_irq(data->irq_num, tsi108_irq, 0, dev->name, dev);
1322 if (i != 0) {
1323 printk(KERN_ERR "tsi108_eth%d: Could not allocate IRQ%d.\n",
1324 data->id, data->irq_num);
1325 return i;
1326 } else {
1327 dev->irq = data->irq_num;
1328 printk(KERN_NOTICE
1329 "tsi108_open : Port %d Assigned IRQ %d to %s\n",
1330 data->id, dev->irq, dev->name);
1331 }
1332
1333 data->rxring = dma_alloc_coherent(NULL, rxring_size,
1334 &data->rxdma, GFP_KERNEL);
1335
1336 if (!data->rxring) {
1337 printk(KERN_DEBUG
1338 "TSI108_ETH: failed to allocate memory for rxring!\n");
1339 return -ENOMEM;
1340 } else {
1341 memset(data->rxring, 0, rxring_size);
1342 }
1343
1344 data->txring = dma_alloc_coherent(NULL, txring_size,
1345 &data->txdma, GFP_KERNEL);
1346
1347 if (!data->txring) {
1348 printk(KERN_DEBUG
1349 "TSI108_ETH: failed to allocate memory for txring!\n");
1350 pci_free_consistent(0, rxring_size, data->rxring, data->rxdma);
1351 return -ENOMEM;
1352 } else {
1353 memset(data->txring, 0, txring_size);
1354 }
1355
1356 for (i = 0; i < TSI108_RXRING_LEN; i++) {
1357 data->rxring[i].next0 = data->rxdma + (i + 1) * sizeof(rx_desc);
1358 data->rxring[i].blen = TSI108_RXBUF_SIZE;
1359 data->rxring[i].vlan = 0;
1360 }
1361
1362 data->rxring[TSI108_RXRING_LEN - 1].next0 = data->rxdma;
1363
1364 data->rxtail = 0;
1365 data->rxhead = 0;
1366
1367 for (i = 0; i < TSI108_RXRING_LEN; i++) {
1368 struct sk_buff *skb = dev_alloc_skb(TSI108_RXBUF_SIZE + NET_IP_ALIGN);
1369
1370 if (!skb) {
1371 /* Bah. No memory for now, but maybe we'll get
1372 * some more later.
1373 * For now, we'll live with the smaller ring.
1374 */
1375 printk(KERN_WARNING
1376 "%s: Could only allocate %d receive skb(s).\n",
1377 dev->name, i);
1378 data->rxhead = i;
1379 break;
1380 }
1381
1382 data->rxskbs[i] = skb;
1383 /* Align the payload on a 4-byte boundary */
1384 skb_reserve(skb, 2);
1385 data->rxskbs[i] = skb;
1386 data->rxring[i].buf0 = virt_to_phys(data->rxskbs[i]->data);
1387 data->rxring[i].misc = TSI108_RX_OWN | TSI108_RX_INT;
1388 }
1389
1390 data->rxfree = i;
1391 TSI_WRITE(TSI108_EC_RXQ_PTRLOW, data->rxdma);
1392
1393 for (i = 0; i < TSI108_TXRING_LEN; i++) {
1394 data->txring[i].next0 = data->txdma + (i + 1) * sizeof(tx_desc);
1395 data->txring[i].misc = 0;
1396 }
1397
1398 data->txring[TSI108_TXRING_LEN - 1].next0 = data->txdma;
1399 data->txtail = 0;
1400 data->txhead = 0;
1401 data->txfree = TSI108_TXRING_LEN;
1402 TSI_WRITE(TSI108_EC_TXQ_PTRLOW, data->txdma);
1403 tsi108_init_phy(dev);
1404
1405 setup_timer(&data->timer, tsi108_timed_checker, (unsigned long)dev);
1406 mod_timer(&data->timer, jiffies + 1);
1407
1408 tsi108_restart_rx(data, dev);
1409
1410 TSI_WRITE(TSI108_EC_INTSTAT, ~0);
1411
1412 TSI_WRITE(TSI108_EC_INTMASK,
1413 ~(TSI108_INT_TXQUEUE0 | TSI108_INT_RXERROR |
1414 TSI108_INT_RXTHRESH | TSI108_INT_RXQUEUE0 |
1415 TSI108_INT_RXOVERRUN | TSI108_INT_RXWAIT |
1416 TSI108_INT_SFN | TSI108_INT_STATCARRY));
1417
1418 TSI_WRITE(TSI108_MAC_CFG1,
1419 TSI108_MAC_CFG1_RXEN | TSI108_MAC_CFG1_TXEN);
1420 netif_start_queue(dev);
1421 return 0;
1422}
1423
1424static int tsi108_close(struct net_device *dev)
1425{
1426 struct tsi108_prv_data *data = netdev_priv(dev);
1427
1428 netif_stop_queue(dev);
1429
1430 del_timer_sync(&data->timer);
1431
1432 tsi108_stop_ethernet(dev);
1433 tsi108_kill_phy(dev);
1434 TSI_WRITE(TSI108_EC_INTMASK, ~0);
1435 TSI_WRITE(TSI108_MAC_CFG1, 0);
1436
1437 /* Check for any pending TX packets, and drop them. */
1438
1439 while (!data->txfree || data->txhead != data->txtail) {
1440 int tx = data->txtail;
1441 struct sk_buff *skb;
1442 skb = data->txskbs[tx];
1443 data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
1444 data->txfree++;
1445 dev_kfree_skb(skb);
1446 }
1447
1448 synchronize_irq(data->irq_num);
1449 free_irq(data->irq_num, dev);
1450
1451 /* Discard the RX ring. */
1452
1453 while (data->rxfree) {
1454 int rx = data->rxtail;
1455 struct sk_buff *skb;
1456
1457 skb = data->rxskbs[rx];
1458 data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
1459 data->rxfree--;
1460 dev_kfree_skb(skb);
1461 }
1462
1463 dma_free_coherent(0,
1464 TSI108_RXRING_LEN * sizeof(rx_desc),
1465 data->rxring, data->rxdma);
1466 dma_free_coherent(0,
1467 TSI108_TXRING_LEN * sizeof(tx_desc),
1468 data->txring, data->txdma);
1469
1470 return 0;
1471}
1472
1473static void tsi108_init_mac(struct net_device *dev)
1474{
1475 struct tsi108_prv_data *data = netdev_priv(dev);
1476
1477 TSI_WRITE(TSI108_MAC_CFG2, TSI108_MAC_CFG2_DFLT_PREAMBLE |
1478 TSI108_MAC_CFG2_PADCRC);
1479
1480 TSI_WRITE(TSI108_EC_TXTHRESH,
1481 (192 << TSI108_EC_TXTHRESH_STARTFILL) |
1482 (192 << TSI108_EC_TXTHRESH_STOPFILL));
1483
1484 TSI_WRITE(TSI108_STAT_CARRYMASK1,
1485 ~(TSI108_STAT_CARRY1_RXBYTES |
1486 TSI108_STAT_CARRY1_RXPKTS |
1487 TSI108_STAT_CARRY1_RXFCS |
1488 TSI108_STAT_CARRY1_RXMCAST |
1489 TSI108_STAT_CARRY1_RXALIGN |
1490 TSI108_STAT_CARRY1_RXLENGTH |
1491 TSI108_STAT_CARRY1_RXRUNT |
1492 TSI108_STAT_CARRY1_RXJUMBO |
1493 TSI108_STAT_CARRY1_RXFRAG |
1494 TSI108_STAT_CARRY1_RXJABBER |
1495 TSI108_STAT_CARRY1_RXDROP));
1496
1497 TSI_WRITE(TSI108_STAT_CARRYMASK2,
1498 ~(TSI108_STAT_CARRY2_TXBYTES |
1499 TSI108_STAT_CARRY2_TXPKTS |
1500 TSI108_STAT_CARRY2_TXEXDEF |
1501 TSI108_STAT_CARRY2_TXEXCOL |
1502 TSI108_STAT_CARRY2_TXTCOL |
1503 TSI108_STAT_CARRY2_TXPAUSE));
1504
1505 TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATEN);
1506 TSI_WRITE(TSI108_MAC_CFG1, 0);
1507
1508 TSI_WRITE(TSI108_EC_RXCFG,
1509 TSI108_EC_RXCFG_SE | TSI108_EC_RXCFG_BFE);
1510
1511 TSI_WRITE(TSI108_EC_TXQ_CFG, TSI108_EC_TXQ_CFG_DESC_INT |
1512 TSI108_EC_TXQ_CFG_EOQ_OWN_INT |
1513 TSI108_EC_TXQ_CFG_WSWP | (TSI108_PBM_PORT <<
1514 TSI108_EC_TXQ_CFG_SFNPORT));
1515
1516 TSI_WRITE(TSI108_EC_RXQ_CFG, TSI108_EC_RXQ_CFG_DESC_INT |
1517 TSI108_EC_RXQ_CFG_EOQ_OWN_INT |
1518 TSI108_EC_RXQ_CFG_WSWP | (TSI108_PBM_PORT <<
1519 TSI108_EC_RXQ_CFG_SFNPORT));
1520
1521 TSI_WRITE(TSI108_EC_TXQ_BUFCFG,
1522 TSI108_EC_TXQ_BUFCFG_BURST256 |
1523 TSI108_EC_TXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
1524 TSI108_EC_TXQ_BUFCFG_SFNPORT));
1525
1526 TSI_WRITE(TSI108_EC_RXQ_BUFCFG,
1527 TSI108_EC_RXQ_BUFCFG_BURST256 |
1528 TSI108_EC_RXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
1529 TSI108_EC_RXQ_BUFCFG_SFNPORT));
1530
1531 TSI_WRITE(TSI108_EC_INTMASK, ~0);
1532}
1533
1534static int tsi108_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1535{
1536 struct tsi108_prv_data *data = netdev_priv(dev);
1537 return generic_mii_ioctl(&data->mii_if, if_mii(rq), cmd, NULL);
1538}
1539
1540static int
1541tsi108_init_one(struct platform_device *pdev)
1542{
1543 struct net_device *dev = NULL;
1544 struct tsi108_prv_data *data = NULL;
1545 hw_info *einfo;
1546 int err = 0;
1547
1548 einfo = pdev->dev.platform_data;
1549
1550 if (NULL == einfo) {
1551 printk(KERN_ERR "tsi-eth %d: Missing additional data!\n",
1552 pdev->id);
1553 return -ENODEV;
1554 }
1555
1556 /* Create an ethernet device instance */
1557
1558 dev = alloc_etherdev(sizeof(struct tsi108_prv_data));
1559 if (!dev) {
1560 printk("tsi108_eth: Could not allocate a device structure\n");
1561 return -ENOMEM;
1562 }
1563
1564 printk("tsi108_eth%d: probe...\n", pdev->id);
1565 data = netdev_priv(dev);
1566
1567 pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n",
1568 pdev->id, einfo->regs, einfo->phyregs,
1569 einfo->phy, einfo->irq_num);
1570
1571 data->regs = ioremap(einfo->regs, 0x400);
1572 if (NULL == data->regs) {
1573 err = -ENOMEM;
1574 goto regs_fail;
1575 }
1576
1577 data->phyregs = ioremap(einfo->phyregs, 0x400);
1578 if (NULL == data->phyregs) {
1579 err = -ENOMEM;
1580 goto regs_fail;
1581 }
1582/* MII setup */
1583 data->mii_if.dev = dev;
1584 data->mii_if.mdio_read = tsi108_mdio_read;
1585 data->mii_if.mdio_write = tsi108_mdio_write;
1586 data->mii_if.phy_id = einfo->phy;
1587 data->mii_if.phy_id_mask = 0x1f;
1588 data->mii_if.reg_num_mask = 0x1f;
1589 data->mii_if.supports_gmii = mii_check_gmii_support(&data->mii_if);
1590
1591 data->phy = einfo->phy;
1592 data->irq_num = einfo->irq_num;
1593 data->id = pdev->id;
1594 dev->open = tsi108_open;
1595 dev->stop = tsi108_close;
1596 dev->hard_start_xmit = tsi108_send_packet;
1597 dev->set_mac_address = tsi108_set_mac;
1598 dev->set_multicast_list = tsi108_set_rx_mode;
1599 dev->get_stats = tsi108_get_stats;
1600 dev->poll = tsi108_poll;
1601 dev->do_ioctl = tsi108_do_ioctl;
1602 dev->weight = 64; /* 64 is more suitable for GigE interface - klai */
1603
1604 /* Apparently, the Linux networking code won't use scatter-gather
1605 * if the hardware doesn't do checksums. However, it's faster
1606 * to checksum in place and use SG, as (among other reasons)
1607 * the cache won't be dirtied (which then has to be flushed
1608 * before DMA). The checksumming is done by the driver (via
1609 * a new function skb_csum_dev() in net/core/skbuff.c).
1610 */
1611
1612 dev->features = NETIF_F_HIGHDMA;
1613 SET_MODULE_OWNER(dev);
1614
1615 spin_lock_init(&data->txlock);
1616 spin_lock_init(&data->misclock);
1617
1618 tsi108_reset_ether(data);
1619 tsi108_kill_phy(dev);
1620
1621 if ((err = tsi108_get_mac(dev)) != 0) {
1622 printk(KERN_ERR "%s: Invalid MAC address. Please correct.\n",
1623 dev->name);
1624 goto register_fail;
1625 }
1626
1627 tsi108_init_mac(dev);
1628 err = register_netdev(dev);
1629 if (err) {
1630 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1631 dev->name);
1632 goto register_fail;
1633 }
1634
1635 printk(KERN_INFO "%s: Tsi108 Gigabit Ethernet, MAC: "
1636 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
1637 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1638 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1639#ifdef DEBUG
1640 data->msg_enable = DEBUG;
1641 dump_eth_one(dev);
1642#endif
1643
1644 return 0;
1645
1646register_fail:
1647 iounmap(data->regs);
1648 iounmap(data->phyregs);
1649
1650regs_fail:
1651 free_netdev(dev);
1652 return err;
1653}
1654
1655/* There's no way to either get interrupts from the PHY when
1656 * something changes, or to have the Tsi108 automatically communicate
1657 * with the PHY to reconfigure itself.
1658 *
1659 * Thus, we have to do it using a timer.
1660 */
1661
1662static void tsi108_timed_checker(unsigned long dev_ptr)
1663{
1664 struct net_device *dev = (struct net_device *)dev_ptr;
1665 struct tsi108_prv_data *data = netdev_priv(dev);
1666
1667 tsi108_check_phy(dev);
1668 tsi108_check_rxring(dev);
1669 mod_timer(&data->timer, jiffies + CHECK_PHY_INTERVAL);
1670}
1671
1672static int tsi108_ether_init(void)
1673{
1674 int ret;
1675 ret = platform_driver_register (&tsi_eth_driver);
1676 if (ret < 0){
1677 printk("tsi108_ether_init: error initializing ethernet "
1678 "device\n");
1679 return ret;
1680 }
1681 return 0;
1682}
1683
1684static int tsi108_ether_remove(struct platform_device *pdev)
1685{
1686 struct net_device *dev = platform_get_drvdata(pdev);
1687 struct tsi108_prv_data *priv = netdev_priv(dev);
1688
1689 unregister_netdev(dev);
1690 tsi108_stop_ethernet(dev);
1691 platform_set_drvdata(pdev, NULL);
1692 iounmap(priv->regs);
1693 iounmap(priv->phyregs);
1694 free_netdev(dev);
1695
1696 return 0;
1697}
1698static void tsi108_ether_exit(void)
1699{
1700 platform_driver_unregister(&tsi_eth_driver);
1701}
1702
1703module_init(tsi108_ether_init);
1704module_exit(tsi108_ether_exit);
1705
1706MODULE_AUTHOR("Tundra Semiconductor Corporation");
1707MODULE_DESCRIPTION("Tsi108 Gigabit Ethernet driver");
1708MODULE_LICENSE("GPL");
diff --git a/drivers/net/tsi108_eth.h b/drivers/net/tsi108_eth.h
new file mode 100644
index 000000000000..77a769df228a
--- /dev/null
+++ b/drivers/net/tsi108_eth.h
@@ -0,0 +1,365 @@
1/*
2 * (C) Copyright 2005 Tundra Semiconductor Corp.
3 * Kong Lai, <kong.lai@tundra.com).
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * net/tsi108_eth.h - definitions for Tsi108 GIGE network controller.
26 */
27
28#ifndef __TSI108_ETH_H
29#define __TSI108_ETH_H
30
31#include <linux/types.h>
32
33#define TSI_WRITE(offset, val) \
34 out_be32((data->regs + (offset)), val)
35
36#define TSI_READ(offset) \
37 in_be32((data->regs + (offset)))
38
39#define TSI_WRITE_PHY(offset, val) \
40 out_be32((data->phyregs + (offset)), val)
41
42#define TSI_READ_PHY(offset) \
43 in_be32((data->phyregs + (offset)))
44
45/*
46 * PHY Configuration Options
47 *
48 * NOTE: Enable set of definitions corresponding to your board type
49 */
50#define PHY_MV88E 1 /* Marvel 88Exxxx PHY */
51#define PHY_BCM54XX 2 /* Broardcom BCM54xx PHY */
52#define TSI108_PHY_TYPE PHY_MV88E
53
54/*
55 * TSI108 GIGE port registers
56 */
57
58#define TSI108_ETH_PORT_NUM 2
59#define TSI108_PBM_PORT 2
60#define TSI108_SDRAM_PORT 4
61
62#define TSI108_MAC_CFG1 (0x000)
63#define TSI108_MAC_CFG1_SOFTRST (1 << 31)
64#define TSI108_MAC_CFG1_LOOPBACK (1 << 8)
65#define TSI108_MAC_CFG1_RXEN (1 << 2)
66#define TSI108_MAC_CFG1_TXEN (1 << 0)
67
68#define TSI108_MAC_CFG2 (0x004)
69#define TSI108_MAC_CFG2_DFLT_PREAMBLE (7 << 12)
70#define TSI108_MAC_CFG2_IFACE_MASK (3 << 8)
71#define TSI108_MAC_CFG2_NOGIG (1 << 8)
72#define TSI108_MAC_CFG2_GIG (2 << 8)
73#define TSI108_MAC_CFG2_PADCRC (1 << 2)
74#define TSI108_MAC_CFG2_FULLDUPLEX (1 << 0)
75
76#define TSI108_MAC_MII_MGMT_CFG (0x020)
77#define TSI108_MAC_MII_MGMT_CLK (7 << 0)
78#define TSI108_MAC_MII_MGMT_RST (1 << 31)
79
80#define TSI108_MAC_MII_CMD (0x024)
81#define TSI108_MAC_MII_CMD_READ (1 << 0)
82
83#define TSI108_MAC_MII_ADDR (0x028)
84#define TSI108_MAC_MII_ADDR_REG 0
85#define TSI108_MAC_MII_ADDR_PHY 8
86
87#define TSI108_MAC_MII_DATAOUT (0x02c)
88#define TSI108_MAC_MII_DATAIN (0x030)
89
90#define TSI108_MAC_MII_IND (0x034)
91#define TSI108_MAC_MII_IND_NOTVALID (1 << 2)
92#define TSI108_MAC_MII_IND_SCANNING (1 << 1)
93#define TSI108_MAC_MII_IND_BUSY (1 << 0)
94
95#define TSI108_MAC_IFCTRL (0x038)
96#define TSI108_MAC_IFCTRL_PHYMODE (1 << 24)
97
98#define TSI108_MAC_ADDR1 (0x040)
99#define TSI108_MAC_ADDR2 (0x044)
100
101#define TSI108_STAT_RXBYTES (0x06c)
102#define TSI108_STAT_RXBYTES_CARRY (1 << 24)
103
104#define TSI108_STAT_RXPKTS (0x070)
105#define TSI108_STAT_RXPKTS_CARRY (1 << 18)
106
107#define TSI108_STAT_RXFCS (0x074)
108#define TSI108_STAT_RXFCS_CARRY (1 << 12)
109
110#define TSI108_STAT_RXMCAST (0x078)
111#define TSI108_STAT_RXMCAST_CARRY (1 << 18)
112
113#define TSI108_STAT_RXALIGN (0x08c)
114#define TSI108_STAT_RXALIGN_CARRY (1 << 12)
115
116#define TSI108_STAT_RXLENGTH (0x090)
117#define TSI108_STAT_RXLENGTH_CARRY (1 << 12)
118
119#define TSI108_STAT_RXRUNT (0x09c)
120#define TSI108_STAT_RXRUNT_CARRY (1 << 12)
121
122#define TSI108_STAT_RXJUMBO (0x0a0)
123#define TSI108_STAT_RXJUMBO_CARRY (1 << 12)
124
125#define TSI108_STAT_RXFRAG (0x0a4)
126#define TSI108_STAT_RXFRAG_CARRY (1 << 12)
127
128#define TSI108_STAT_RXJABBER (0x0a8)
129#define TSI108_STAT_RXJABBER_CARRY (1 << 12)
130
131#define TSI108_STAT_RXDROP (0x0ac)
132#define TSI108_STAT_RXDROP_CARRY (1 << 12)
133
134#define TSI108_STAT_TXBYTES (0x0b0)
135#define TSI108_STAT_TXBYTES_CARRY (1 << 24)
136
137#define TSI108_STAT_TXPKTS (0x0b4)
138#define TSI108_STAT_TXPKTS_CARRY (1 << 18)
139
140#define TSI108_STAT_TXEXDEF (0x0c8)
141#define TSI108_STAT_TXEXDEF_CARRY (1 << 12)
142
143#define TSI108_STAT_TXEXCOL (0x0d8)
144#define TSI108_STAT_TXEXCOL_CARRY (1 << 12)
145
146#define TSI108_STAT_TXTCOL (0x0dc)
147#define TSI108_STAT_TXTCOL_CARRY (1 << 13)
148
149#define TSI108_STAT_TXPAUSEDROP (0x0e4)
150#define TSI108_STAT_TXPAUSEDROP_CARRY (1 << 12)
151
152#define TSI108_STAT_CARRY1 (0x100)
153#define TSI108_STAT_CARRY1_RXBYTES (1 << 16)
154#define TSI108_STAT_CARRY1_RXPKTS (1 << 15)
155#define TSI108_STAT_CARRY1_RXFCS (1 << 14)
156#define TSI108_STAT_CARRY1_RXMCAST (1 << 13)
157#define TSI108_STAT_CARRY1_RXALIGN (1 << 8)
158#define TSI108_STAT_CARRY1_RXLENGTH (1 << 7)
159#define TSI108_STAT_CARRY1_RXRUNT (1 << 4)
160#define TSI108_STAT_CARRY1_RXJUMBO (1 << 3)
161#define TSI108_STAT_CARRY1_RXFRAG (1 << 2)
162#define TSI108_STAT_CARRY1_RXJABBER (1 << 1)
163#define TSI108_STAT_CARRY1_RXDROP (1 << 0)
164
165#define TSI108_STAT_CARRY2 (0x104)
166#define TSI108_STAT_CARRY2_TXBYTES (1 << 13)
167#define TSI108_STAT_CARRY2_TXPKTS (1 << 12)
168#define TSI108_STAT_CARRY2_TXEXDEF (1 << 7)
169#define TSI108_STAT_CARRY2_TXEXCOL (1 << 3)
170#define TSI108_STAT_CARRY2_TXTCOL (1 << 2)
171#define TSI108_STAT_CARRY2_TXPAUSE (1 << 0)
172
173#define TSI108_STAT_CARRYMASK1 (0x108)
174#define TSI108_STAT_CARRYMASK2 (0x10c)
175
176#define TSI108_EC_PORTCTRL (0x200)
177#define TSI108_EC_PORTCTRL_STATRST (1 << 31)
178#define TSI108_EC_PORTCTRL_STATEN (1 << 28)
179#define TSI108_EC_PORTCTRL_NOGIG (1 << 18)
180#define TSI108_EC_PORTCTRL_HALFDUPLEX (1 << 16)
181
182#define TSI108_EC_INTSTAT (0x204)
183#define TSI108_EC_INTMASK (0x208)
184
185#define TSI108_INT_ANY (1 << 31)
186#define TSI108_INT_SFN (1 << 30)
187#define TSI108_INT_RXIDLE (1 << 29)
188#define TSI108_INT_RXABORT (1 << 28)
189#define TSI108_INT_RXERROR (1 << 27)
190#define TSI108_INT_RXOVERRUN (1 << 26)
191#define TSI108_INT_RXTHRESH (1 << 25)
192#define TSI108_INT_RXWAIT (1 << 24)
193#define TSI108_INT_RXQUEUE0 (1 << 16)
194#define TSI108_INT_STATCARRY (1 << 15)
195#define TSI108_INT_TXIDLE (1 << 13)
196#define TSI108_INT_TXABORT (1 << 12)
197#define TSI108_INT_TXERROR (1 << 11)
198#define TSI108_INT_TXUNDERRUN (1 << 10)
199#define TSI108_INT_TXTHRESH (1 << 9)
200#define TSI108_INT_TXWAIT (1 << 8)
201#define TSI108_INT_TXQUEUE0 (1 << 0)
202
203#define TSI108_EC_TXCFG (0x220)
204#define TSI108_EC_TXCFG_RST (1 << 31)
205
206#define TSI108_EC_TXCTRL (0x224)
207#define TSI108_EC_TXCTRL_IDLEINT (1 << 31)
208#define TSI108_EC_TXCTRL_ABORT (1 << 30)
209#define TSI108_EC_TXCTRL_GO (1 << 15)
210#define TSI108_EC_TXCTRL_QUEUE0 (1 << 0)
211
212#define TSI108_EC_TXSTAT (0x228)
213#define TSI108_EC_TXSTAT_ACTIVE (1 << 15)
214#define TSI108_EC_TXSTAT_QUEUE0 (1 << 0)
215
216#define TSI108_EC_TXESTAT (0x22c)
217#define TSI108_EC_TXESTAT_Q0_ERR (1 << 24)
218#define TSI108_EC_TXESTAT_Q0_DESCINT (1 << 16)
219#define TSI108_EC_TXESTAT_Q0_EOF (1 << 8)
220#define TSI108_EC_TXESTAT_Q0_EOQ (1 << 0)
221
222#define TSI108_EC_TXERR (0x278)
223
224#define TSI108_EC_TXQ_CFG (0x280)
225#define TSI108_EC_TXQ_CFG_DESC_INT (1 << 20)
226#define TSI108_EC_TXQ_CFG_EOQ_OWN_INT (1 << 19)
227#define TSI108_EC_TXQ_CFG_WSWP (1 << 11)
228#define TSI108_EC_TXQ_CFG_BSWP (1 << 10)
229#define TSI108_EC_TXQ_CFG_SFNPORT 0
230
231#define TSI108_EC_TXQ_BUFCFG (0x284)
232#define TSI108_EC_TXQ_BUFCFG_BURST8 (0 << 8)
233#define TSI108_EC_TXQ_BUFCFG_BURST32 (1 << 8)
234#define TSI108_EC_TXQ_BUFCFG_BURST128 (2 << 8)
235#define TSI108_EC_TXQ_BUFCFG_BURST256 (3 << 8)
236#define TSI108_EC_TXQ_BUFCFG_WSWP (1 << 11)
237#define TSI108_EC_TXQ_BUFCFG_BSWP (1 << 10)
238#define TSI108_EC_TXQ_BUFCFG_SFNPORT 0
239
240#define TSI108_EC_TXQ_PTRLOW (0x288)
241
242#define TSI108_EC_TXQ_PTRHIGH (0x28c)
243#define TSI108_EC_TXQ_PTRHIGH_VALID (1 << 31)
244
245#define TSI108_EC_TXTHRESH (0x230)
246#define TSI108_EC_TXTHRESH_STARTFILL 0
247#define TSI108_EC_TXTHRESH_STOPFILL 16
248
249#define TSI108_EC_RXCFG (0x320)
250#define TSI108_EC_RXCFG_RST (1 << 31)
251
252#define TSI108_EC_RXSTAT (0x328)
253#define TSI108_EC_RXSTAT_ACTIVE (1 << 15)
254#define TSI108_EC_RXSTAT_QUEUE0 (1 << 0)
255
256#define TSI108_EC_RXESTAT (0x32c)
257#define TSI108_EC_RXESTAT_Q0_ERR (1 << 24)
258#define TSI108_EC_RXESTAT_Q0_DESCINT (1 << 16)
259#define TSI108_EC_RXESTAT_Q0_EOF (1 << 8)
260#define TSI108_EC_RXESTAT_Q0_EOQ (1 << 0)
261
262#define TSI108_EC_HASHADDR (0x360)
263#define TSI108_EC_HASHADDR_AUTOINC (1 << 31)
264#define TSI108_EC_HASHADDR_DO1STREAD (1 << 30)
265#define TSI108_EC_HASHADDR_UNICAST (0 << 4)
266#define TSI108_EC_HASHADDR_MCAST (1 << 4)
267
268#define TSI108_EC_HASHDATA (0x364)
269
270#define TSI108_EC_RXQ_PTRLOW (0x388)
271
272#define TSI108_EC_RXQ_PTRHIGH (0x38c)
273#define TSI108_EC_RXQ_PTRHIGH_VALID (1 << 31)
274
275/* Station Enable -- accept packets destined for us */
276#define TSI108_EC_RXCFG_SE (1 << 13)
277/* Unicast Frame Enable -- for packets not destined for us */
278#define TSI108_EC_RXCFG_UFE (1 << 12)
279/* Multicast Frame Enable */
280#define TSI108_EC_RXCFG_MFE (1 << 11)
281/* Broadcast Frame Enable */
282#define TSI108_EC_RXCFG_BFE (1 << 10)
283#define TSI108_EC_RXCFG_UC_HASH (1 << 9)
284#define TSI108_EC_RXCFG_MC_HASH (1 << 8)
285
286#define TSI108_EC_RXQ_CFG (0x380)
287#define TSI108_EC_RXQ_CFG_DESC_INT (1 << 20)
288#define TSI108_EC_RXQ_CFG_EOQ_OWN_INT (1 << 19)
289#define TSI108_EC_RXQ_CFG_WSWP (1 << 11)
290#define TSI108_EC_RXQ_CFG_BSWP (1 << 10)
291#define TSI108_EC_RXQ_CFG_SFNPORT 0
292
293#define TSI108_EC_RXQ_BUFCFG (0x384)
294#define TSI108_EC_RXQ_BUFCFG_BURST8 (0 << 8)
295#define TSI108_EC_RXQ_BUFCFG_BURST32 (1 << 8)
296#define TSI108_EC_RXQ_BUFCFG_BURST128 (2 << 8)
297#define TSI108_EC_RXQ_BUFCFG_BURST256 (3 << 8)
298#define TSI108_EC_RXQ_BUFCFG_WSWP (1 << 11)
299#define TSI108_EC_RXQ_BUFCFG_BSWP (1 << 10)
300#define TSI108_EC_RXQ_BUFCFG_SFNPORT 0
301
302#define TSI108_EC_RXCTRL (0x324)
303#define TSI108_EC_RXCTRL_ABORT (1 << 30)
304#define TSI108_EC_RXCTRL_GO (1 << 15)
305#define TSI108_EC_RXCTRL_QUEUE0 (1 << 0)
306
307#define TSI108_EC_RXERR (0x378)
308
309#define TSI108_TX_EOF (1 << 0) /* End of frame; last fragment of packet */
310#define TSI108_TX_SOF (1 << 1) /* Start of frame; first frag. of packet */
311#define TSI108_TX_VLAN (1 << 2) /* Per-frame VLAN: enables VLAN override */
312#define TSI108_TX_HUGE (1 << 3) /* Huge frame enable */
313#define TSI108_TX_PAD (1 << 4) /* Pad the packet if too short */
314#define TSI108_TX_CRC (1 << 5) /* Generate CRC for this packet */
315#define TSI108_TX_INT (1 << 14) /* Generate an IRQ after frag. processed */
316#define TSI108_TX_RETRY (0xf << 16) /* 4 bit field indicating num. of retries */
317#define TSI108_TX_COL (1 << 20) /* Set if a collision occured */
318#define TSI108_TX_LCOL (1 << 24) /* Set if a late collision occured */
319#define TSI108_TX_UNDER (1 << 25) /* Set if a FIFO underrun occured */
320#define TSI108_TX_RLIM (1 << 26) /* Set if the retry limit was reached */
321#define TSI108_TX_OK (1 << 30) /* Set if the frame TX was successful */
322#define TSI108_TX_OWN (1 << 31) /* Set if the device owns the descriptor */
323
324/* Note: the descriptor layouts assume big-endian byte order. */
325typedef struct {
326 u32 buf0;
327 u32 buf1; /* Base address of buffer */
328 u32 next0; /* Address of next descriptor, if any */
329 u32 next1;
330 u16 vlan; /* VLAN, if override enabled for this packet */
331 u16 len; /* Length of buffer in bytes */
332 u32 misc; /* See TSI108_TX_* above */
333 u32 reserved0; /*reserved0 and reserved1 are added to make the desc */
334 u32 reserved1; /* 32-byte aligned */
335} __attribute__ ((aligned(32))) tx_desc;
336
337#define TSI108_RX_EOF (1 << 0) /* End of frame; last fragment of packet */
338#define TSI108_RX_SOF (1 << 1) /* Start of frame; first frag. of packet */
339#define TSI108_RX_VLAN (1 << 2) /* Set on SOF if packet has a VLAN */
340#define TSI108_RX_FTYPE (1 << 3) /* Length/Type field is type, not length */
341#define TSI108_RX_RUNT (1 << 4)/* Packet is less than minimum size */
342#define TSI108_RX_HASH (1 << 7)/* Hash table match */
343#define TSI108_RX_BAD (1 << 8) /* Bad frame */
344#define TSI108_RX_OVER (1 << 9) /* FIFO overrun occured */
345#define TSI108_RX_TRUNC (1 << 11) /* Packet truncated due to excess length */
346#define TSI108_RX_CRC (1 << 12) /* Packet had a CRC error */
347#define TSI108_RX_INT (1 << 13) /* Generate an IRQ after frag. processed */
348#define TSI108_RX_OWN (1 << 15) /* Set if the device owns the descriptor */
349
350#define TSI108_RX_SKB_SIZE 1536 /* The RX skb length */
351
352typedef struct {
353 u32 buf0; /* Base address of buffer */
354 u32 buf1; /* Base address of buffer */
355 u32 next0; /* Address of next descriptor, if any */
356 u32 next1; /* Address of next descriptor, if any */
357 u16 vlan; /* VLAN of received packet, first frag only */
358 u16 len; /* Length of received fragment in bytes */
359 u16 blen; /* Length of buffer in bytes */
360 u16 misc; /* See TSI108_RX_* above */
361 u32 reserved0; /* reserved0 and reserved1 are added to make the desc */
362 u32 reserved1; /* 32-byte aligned */
363} __attribute__ ((aligned(32))) rx_desc;
364
365#endif /* __TSI108_ETH_H */
diff --git a/drivers/net/tulip/de2104x.c b/drivers/net/tulip/de2104x.c
index f6b3a94e97bf..9d67f11422ec 100644
--- a/drivers/net/tulip/de2104x.c
+++ b/drivers/net/tulip/de2104x.c
@@ -1906,9 +1906,7 @@ fill_defaults:
1906 de->media[i].csr15 = t21041_csr15[i]; 1906 de->media[i].csr15 = t21041_csr15[i];
1907 } 1907 }
1908 1908
1909 de->ee_data = kmalloc(DE_EEPROM_SIZE, GFP_KERNEL); 1909 de->ee_data = kmemdup(&ee_data[0], DE_EEPROM_SIZE, GFP_KERNEL);
1910 if (de->ee_data)
1911 memcpy(de->ee_data, &ee_data[0], DE_EEPROM_SIZE);
1912 1910
1913 return; 1911 return;
1914 1912
diff --git a/drivers/net/tulip/dmfe.c b/drivers/net/tulip/dmfe.c
index 4dd8a0bae860..7f59a3d4fda2 100644
--- a/drivers/net/tulip/dmfe.c
+++ b/drivers/net/tulip/dmfe.c
@@ -187,7 +187,7 @@ struct rx_desc {
187struct dmfe_board_info { 187struct dmfe_board_info {
188 u32 chip_id; /* Chip vendor/Device ID */ 188 u32 chip_id; /* Chip vendor/Device ID */
189 u32 chip_revision; /* Chip revision */ 189 u32 chip_revision; /* Chip revision */
190 struct DEVICE *next_dev; /* next device */ 190 struct DEVICE *dev; /* net device */
191 struct pci_dev *pdev; /* PCI device */ 191 struct pci_dev *pdev; /* PCI device */
192 spinlock_t lock; 192 spinlock_t lock;
193 193
@@ -399,6 +399,8 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
399 /* Init system & device */ 399 /* Init system & device */
400 db = netdev_priv(dev); 400 db = netdev_priv(dev);
401 401
402 db->dev = dev;
403
402 /* Allocate Tx/Rx descriptor memory */ 404 /* Allocate Tx/Rx descriptor memory */
403 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); 405 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
404 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); 406 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
@@ -426,6 +428,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
426 dev->poll_controller = &poll_dmfe; 428 dev->poll_controller = &poll_dmfe;
427#endif 429#endif
428 dev->ethtool_ops = &netdev_ethtool_ops; 430 dev->ethtool_ops = &netdev_ethtool_ops;
431 netif_carrier_off(db->dev);
429 spin_lock_init(&db->lock); 432 spin_lock_init(&db->lock);
430 433
431 pci_read_config_dword(pdev, 0x50, &pci_pmr); 434 pci_read_config_dword(pdev, 0x50, &pci_pmr);
@@ -1050,6 +1053,7 @@ static void netdev_get_drvinfo(struct net_device *dev,
1050 1053
1051static const struct ethtool_ops netdev_ethtool_ops = { 1054static const struct ethtool_ops netdev_ethtool_ops = {
1052 .get_drvinfo = netdev_get_drvinfo, 1055 .get_drvinfo = netdev_get_drvinfo,
1056 .get_link = ethtool_op_get_link,
1053}; 1057};
1054 1058
1055/* 1059/*
@@ -1144,6 +1148,7 @@ static void dmfe_timer(unsigned long data)
1144 /* Link Failed */ 1148 /* Link Failed */
1145 DMFE_DBUG(0, "Link Failed", tmp_cr12); 1149 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1146 db->link_failed = 1; 1150 db->link_failed = 1;
1151 netif_carrier_off(db->dev);
1147 1152
1148 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ 1153 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1149 /* AUTO or force 1M Homerun/Longrun don't need */ 1154 /* AUTO or force 1M Homerun/Longrun don't need */
@@ -1166,6 +1171,8 @@ static void dmfe_timer(unsigned long data)
1166 if ( (db->media_mode & DMFE_AUTO) && 1171 if ( (db->media_mode & DMFE_AUTO) &&
1167 dmfe_sense_speed(db) ) 1172 dmfe_sense_speed(db) )
1168 db->link_failed = 1; 1173 db->link_failed = 1;
1174 else
1175 netif_carrier_on(db->dev);
1169 dmfe_process_mode(db); 1176 dmfe_process_mode(db);
1170 /* SHOW_MEDIA_TYPE(db->op_mode); */ 1177 /* SHOW_MEDIA_TYPE(db->op_mode); */
1171 } 1178 }
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index 3bf9e630404f..8ddea1da7c05 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -127,7 +127,6 @@ static const int multicast_filter_limit = 32;
127#include <asm/io.h> 127#include <asm/io.h>
128#include <asm/uaccess.h> 128#include <asm/uaccess.h>
129#include <linux/in6.h> 129#include <linux/in6.h>
130#include <asm/checksum.h>
131#include <linux/version.h> 130#include <linux/version.h>
132#include <linux/dma-mapping.h> 131#include <linux/dma-mapping.h>
133 132
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index b37888011067..1f05511fa390 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -30,7 +30,7 @@
30#include <linux/ethtool.h> 30#include <linux/ethtool.h>
31#include <linux/mii.h> 31#include <linux/mii.h>
32 32
33#include <asm/of_device.h> 33#include <asm/of_platform.h>
34#include <asm/uaccess.h> 34#include <asm/uaccess.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <asm/io.h> 36#include <asm/io.h>
@@ -4301,12 +4301,12 @@ static int __init ucc_geth_init(void)
4301 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 4301 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4302 sizeof(ugeth_primary_info)); 4302 sizeof(ugeth_primary_info));
4303 4303
4304 return of_register_driver(&ucc_geth_driver); 4304 return of_register_platform_driver(&ucc_geth_driver);
4305} 4305}
4306 4306
4307static void __exit ucc_geth_exit(void) 4307static void __exit ucc_geth_exit(void)
4308{ 4308{
4309 of_unregister_driver(&ucc_geth_driver); 4309 of_unregister_platform_driver(&ucc_geth_driver);
4310} 4310}
4311 4311
4312module_init(ucc_geth_init); 4312module_init(ucc_geth_init);
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index b5d0d7fb647a..d5ab9cf13257 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -57,44 +57,6 @@ config COSA
57 The driver will be compiled as a module: the 57 The driver will be compiled as a module: the
58 module will be called cosa. 58 module will be called cosa.
59 59
60config DSCC4
61 tristate "Etinc PCISYNC serial board support"
62 depends on WAN && PCI && m
63 help
64 Driver for Etinc PCISYNC boards based on the Infineon (ex. Siemens)
65 DSCC4 chipset.
66
67 This is supposed to work with the four port card. Take a look at
68 <http://www.cogenit.fr/dscc4/> for further information about the
69 driver.
70
71 To compile this driver as a module, choose M here: the
72 module will be called dscc4.
73
74config DSCC4_PCISYNC
75 bool "Etinc PCISYNC features"
76 depends on DSCC4
77 help
78 Due to Etinc's design choice for its PCISYNC cards, some operations
79 are only allowed on specific ports of the DSCC4. This option is the
80 only way for the driver to know that it shouldn't return a success
81 code for these operations.
82
83 Please say Y if your card is an Etinc's PCISYNC.
84
85config DSCC4_PCI_RST
86 bool "Hard reset support"
87 depends on DSCC4
88 help
89 Various DSCC4 bugs forbid any reliable software reset of the ASIC.
90 As a replacement, some vendors provide a way to assert the PCI #RST
91 pin of DSCC4 through the GPIO port of the card. If you choose Y,
92 the driver will make use of this feature before module removal
93 (i.e. rmmod). The feature is known to be available on Commtech's
94 cards. Contact your manufacturer for details.
95
96 Say Y if your card supports this feature.
97
98# 60#
99# Lan Media's board. Currently 1000, 1200, 5200, 5245 61# Lan Media's board. Currently 1000, 1200, 5200, 5245
100# 62#
@@ -323,6 +285,44 @@ config FARSYNC
323 To compile this driver as a module, choose M here: the 285 To compile this driver as a module, choose M here: the
324 module will be called farsync. 286 module will be called farsync.
325 287
288config DSCC4
289 tristate "Etinc PCISYNC serial board support"
290 depends on HDLC && PCI && m
291 help
292 Driver for Etinc PCISYNC boards based on the Infineon (ex. Siemens)
293 DSCC4 chipset.
294
295 This is supposed to work with the four port card. Take a look at
296 <http://www.cogenit.fr/dscc4/> for further information about the
297 driver.
298
299 To compile this driver as a module, choose M here: the
300 module will be called dscc4.
301
302config DSCC4_PCISYNC
303 bool "Etinc PCISYNC features"
304 depends on DSCC4
305 help
306 Due to Etinc's design choice for its PCISYNC cards, some operations
307 are only allowed on specific ports of the DSCC4. This option is the
308 only way for the driver to know that it shouldn't return a success
309 code for these operations.
310
311 Please say Y if your card is an Etinc's PCISYNC.
312
313config DSCC4_PCI_RST
314 bool "Hard reset support"
315 depends on DSCC4
316 help
317 Various DSCC4 bugs forbid any reliable software reset of the ASIC.
318 As a replacement, some vendors provide a way to assert the PCI #RST
319 pin of DSCC4 through the GPIO port of the card. If you choose Y,
320 the driver will make use of this feature before module removal
321 (i.e. rmmod). The feature is known to be available on Commtech's
322 cards. Contact your manufacturer for details.
323
324 Say Y if your card supports this feature.
325
326config DLCI 326config DLCI
327 tristate "Frame Relay DLCI support" 327 tristate "Frame Relay DLCI support"
328 depends on WAN 328 depends on WAN
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index 0c07b8b7250d..10bcb48e80d0 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -595,7 +595,7 @@ static void atmel_join_bss(struct atmel_private *priv, int bss_index);
595static void atmel_smooth_qual(struct atmel_private *priv); 595static void atmel_smooth_qual(struct atmel_private *priv);
596static void atmel_writeAR(struct net_device *dev, u16 data); 596static void atmel_writeAR(struct net_device *dev, u16 data);
597static int probe_atmel_card(struct net_device *dev); 597static int probe_atmel_card(struct net_device *dev);
598static int reset_atmel_card(struct net_device *dev ); 598static int reset_atmel_card(struct net_device *dev);
599static void atmel_enter_state(struct atmel_private *priv, int new_state); 599static void atmel_enter_state(struct atmel_private *priv, int new_state);
600int atmel_open (struct net_device *dev); 600int atmel_open (struct net_device *dev);
601 601
@@ -784,11 +784,11 @@ static void tx_update_descriptor(struct atmel_private *priv, int is_bcast,
784 784
785static int start_tx(struct sk_buff *skb, struct net_device *dev) 785static int start_tx(struct sk_buff *skb, struct net_device *dev)
786{ 786{
787 static const u8 SNAP_RFC1024[6] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
787 struct atmel_private *priv = netdev_priv(dev); 788 struct atmel_private *priv = netdev_priv(dev);
788 struct ieee80211_hdr_4addr header; 789 struct ieee80211_hdr_4addr header;
789 unsigned long flags; 790 unsigned long flags;
790 u16 buff, frame_ctl, len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN; 791 u16 buff, frame_ctl, len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
791 u8 SNAP_RFC1024[6] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
792 792
793 if (priv->card && priv->present_callback && 793 if (priv->card && priv->present_callback &&
794 !(*priv->present_callback)(priv->card)) { 794 !(*priv->present_callback)(priv->card)) {
@@ -1193,7 +1193,7 @@ static irqreturn_t service_interrupt(int irq, void *dev_id)
1193 1193
1194 atmel_set_gcr(dev, GCR_ACKINT); /* acknowledge interrupt */ 1194 atmel_set_gcr(dev, GCR_ACKINT); /* acknowledge interrupt */
1195 1195
1196 for (i = 0; i < sizeof(irq_order)/sizeof(u8); i++) 1196 for (i = 0; i < ARRAY_SIZE(irq_order); i++)
1197 if (isr & irq_order[i]) 1197 if (isr & irq_order[i])
1198 break; 1198 break;
1199 1199
@@ -1345,10 +1345,10 @@ int atmel_open(struct net_device *dev)
1345 atmel_set_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS, priv->reg_domain); 1345 atmel_set_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS, priv->reg_domain);
1346 } else { 1346 } else {
1347 priv->reg_domain = atmel_get_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS); 1347 priv->reg_domain = atmel_get_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS);
1348 for (i = 0; i < sizeof(channel_table)/sizeof(channel_table[0]); i++) 1348 for (i = 0; i < ARRAY_SIZE(channel_table); i++)
1349 if (priv->reg_domain == channel_table[i].reg_domain) 1349 if (priv->reg_domain == channel_table[i].reg_domain)
1350 break; 1350 break;
1351 if (i == sizeof(channel_table)/sizeof(channel_table[0])) { 1351 if (i == ARRAY_SIZE(channel_table)) {
1352 priv->reg_domain = REG_DOMAIN_MKK1; 1352 priv->reg_domain = REG_DOMAIN_MKK1;
1353 printk(KERN_ALERT "%s: failed to get regulatory domain: assuming MKK1.\n", dev->name); 1353 printk(KERN_ALERT "%s: failed to get regulatory domain: assuming MKK1.\n", dev->name);
1354 } 1354 }
@@ -1393,7 +1393,7 @@ static int atmel_validate_channel(struct atmel_private *priv, int channel)
1393 else return suitable default channel */ 1393 else return suitable default channel */
1394 int i; 1394 int i;
1395 1395
1396 for (i = 0; i < sizeof(channel_table)/sizeof(channel_table[0]); i++) 1396 for (i = 0; i < ARRAY_SIZE(channel_table); i++)
1397 if (priv->reg_domain == channel_table[i].reg_domain) { 1397 if (priv->reg_domain == channel_table[i].reg_domain) {
1398 if (channel >= channel_table[i].min && 1398 if (channel >= channel_table[i].min &&
1399 channel <= channel_table[i].max) 1399 channel <= channel_table[i].max)
@@ -1437,7 +1437,7 @@ static int atmel_proc_output (char *buf, struct atmel_private *priv)
1437 } 1437 }
1438 1438
1439 r = "<unknown>"; 1439 r = "<unknown>";
1440 for (i = 0; i < sizeof(channel_table)/sizeof(channel_table[0]); i++) 1440 for (i = 0; i < ARRAY_SIZE(channel_table); i++)
1441 if (priv->reg_domain == channel_table[i].reg_domain) 1441 if (priv->reg_domain == channel_table[i].reg_domain)
1442 r = channel_table[i].name; 1442 r = channel_table[i].name;
1443 1443
@@ -1736,7 +1736,7 @@ static int atmel_set_encode(struct net_device *dev,
1736 /* Disable the key */ 1736 /* Disable the key */
1737 priv->wep_key_len[index] = 0; 1737 priv->wep_key_len[index] = 0;
1738 /* Check if the key is not marked as invalid */ 1738 /* Check if the key is not marked as invalid */
1739 if(!(dwrq->flags & IW_ENCODE_NOKEY)) { 1739 if (!(dwrq->flags & IW_ENCODE_NOKEY)) {
1740 /* Cleanup */ 1740 /* Cleanup */
1741 memset(priv->wep_keys[index], 0, 13); 1741 memset(priv->wep_keys[index], 0, 13);
1742 /* Copy the key in the driver */ 1742 /* Copy the key in the driver */
@@ -1907,7 +1907,7 @@ static int atmel_get_encodeext(struct net_device *dev,
1907 1907
1908 encoding->flags = idx + 1; 1908 encoding->flags = idx + 1;
1909 memset(ext, 0, sizeof(*ext)); 1909 memset(ext, 0, sizeof(*ext));
1910 1910
1911 if (!priv->wep_is_on) { 1911 if (!priv->wep_is_on) {
1912 ext->alg = IW_ENCODE_ALG_NONE; 1912 ext->alg = IW_ENCODE_ALG_NONE;
1913 ext->key_len = 0; 1913 ext->key_len = 0;
@@ -2343,6 +2343,14 @@ static int atmel_get_scan(struct net_device *dev,
2343 iwe.u.freq.e = 0; 2343 iwe.u.freq.e = 0;
2344 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, IW_EV_FREQ_LEN); 2344 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA, &iwe, IW_EV_FREQ_LEN);
2345 2345
2346 /* Add quality statistics */
2347 iwe.cmd = IWEVQUAL;
2348 iwe.u.qual.level = priv->BSSinfo[i].RSSI;
2349 iwe.u.qual.qual = iwe.u.qual.level;
2350 /* iwe.u.qual.noise = SOMETHING */
2351 current_ev = iwe_stream_add_event(current_ev, extra + IW_SCAN_MAX_DATA , &iwe, IW_EV_QUAL_LEN);
2352
2353
2346 iwe.cmd = SIOCGIWENCODE; 2354 iwe.cmd = SIOCGIWENCODE;
2347 if (priv->BSSinfo[i].UsingWEP) 2355 if (priv->BSSinfo[i].UsingWEP)
2348 iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; 2356 iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
@@ -2373,7 +2381,7 @@ static int atmel_get_range(struct net_device *dev,
2373 range->min_nwid = 0x0000; 2381 range->min_nwid = 0x0000;
2374 range->max_nwid = 0x0000; 2382 range->max_nwid = 0x0000;
2375 range->num_channels = 0; 2383 range->num_channels = 0;
2376 for (j = 0; j < sizeof(channel_table)/sizeof(channel_table[0]); j++) 2384 for (j = 0; j < ARRAY_SIZE(channel_table); j++)
2377 if (priv->reg_domain == channel_table[j].reg_domain) { 2385 if (priv->reg_domain == channel_table[j].reg_domain) {
2378 range->num_channels = channel_table[j].max - channel_table[j].min + 1; 2386 range->num_channels = channel_table[j].max - channel_table[j].min + 1;
2379 break; 2387 break;
@@ -2579,9 +2587,9 @@ static const struct iw_priv_args atmel_private_args[] = {
2579 2587
2580static const struct iw_handler_def atmel_handler_def = 2588static const struct iw_handler_def atmel_handler_def =
2581{ 2589{
2582 .num_standard = sizeof(atmel_handler)/sizeof(iw_handler), 2590 .num_standard = ARRAY_SIZE(atmel_handler),
2583 .num_private = sizeof(atmel_private_handler)/sizeof(iw_handler), 2591 .num_private = ARRAY_SIZE(atmel_private_handler),
2584 .num_private_args = sizeof(atmel_private_args)/sizeof(struct iw_priv_args), 2592 .num_private_args = ARRAY_SIZE(atmel_private_args),
2585 .standard = (iw_handler *) atmel_handler, 2593 .standard = (iw_handler *) atmel_handler,
2586 .private = (iw_handler *) atmel_private_handler, 2594 .private = (iw_handler *) atmel_private_handler,
2587 .private_args = (struct iw_priv_args *) atmel_private_args, 2595 .private_args = (struct iw_priv_args *) atmel_private_args,
@@ -2645,7 +2653,7 @@ static int atmel_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2645 2653
2646 domain[REGDOMAINSZ] = 0; 2654 domain[REGDOMAINSZ] = 0;
2647 rc = -EINVAL; 2655 rc = -EINVAL;
2648 for (i = 0; i < sizeof(channel_table)/sizeof(channel_table[0]); i++) { 2656 for (i = 0; i < ARRAY_SIZE(channel_table); i++) {
2649 /* strcasecmp doesn't exist in the library */ 2657 /* strcasecmp doesn't exist in the library */
2650 char *a = channel_table[i].name; 2658 char *a = channel_table[i].name;
2651 char *b = domain; 2659 char *b = domain;
diff --git a/drivers/net/wireless/atmel_cs.c b/drivers/net/wireless/atmel_cs.c
index 785664090bb4..5c410989c4d7 100644
--- a/drivers/net/wireless/atmel_cs.c
+++ b/drivers/net/wireless/atmel_cs.c
@@ -5,12 +5,12 @@
5 Copyright 2000-2001 ATMEL Corporation. 5 Copyright 2000-2001 ATMEL Corporation.
6 Copyright 2003 Simon Kelley. 6 Copyright 2003 Simon Kelley.
7 7
8 This code was developed from version 2.1.1 of the Atmel drivers, 8 This code was developed from version 2.1.1 of the Atmel drivers,
9 released by Atmel corp. under the GPL in December 2002. It also 9 released by Atmel corp. under the GPL in December 2002. It also
10 includes code from the Linux aironet drivers (C) Benjamin Reed, 10 includes code from the Linux aironet drivers (C) Benjamin Reed,
11 and the Linux PCMCIA package, (C) David Hinds. 11 and the Linux PCMCIA package, (C) David Hinds.
12 12
13 For all queries about this code, please contact the current author, 13 For all queries about this code, please contact the current author,
14 Simon Kelley <simon@thekelleys.org.uk> and not Atmel Corporation. 14 Simon Kelley <simon@thekelleys.org.uk> and not Atmel Corporation.
15 15
16 This program is free software; you can redistribute it and/or modify 16 This program is free software; you can redistribute it and/or modify
@@ -87,7 +87,7 @@ MODULE_SUPPORTED_DEVICE("Atmel at76c50x PCMCIA cards");
87 event is received. The config() and release() entry points are 87 event is received. The config() and release() entry points are
88 used to configure or release a socket, in response to card 88 used to configure or release a socket, in response to card
89 insertion and ejection events. They are invoked from the atmel_cs 89 insertion and ejection events. They are invoked from the atmel_cs
90 event handler. 90 event handler.
91*/ 91*/
92 92
93static int atmel_config(struct pcmcia_device *link); 93static int atmel_config(struct pcmcia_device *link);
@@ -133,22 +133,22 @@ static void atmel_detach(struct pcmcia_device *p_dev);
133 device IO routines can use a flag like this to throttle IO to a 133 device IO routines can use a flag like this to throttle IO to a
134 card that is not ready to accept it. 134 card that is not ready to accept it.
135*/ 135*/
136 136
137typedef struct local_info_t { 137typedef struct local_info_t {
138 dev_node_t node; 138 dev_node_t node;
139 struct net_device *eth_dev; 139 struct net_device *eth_dev;
140} local_info_t; 140} local_info_t;
141 141
142/*====================================================================== 142/*======================================================================
143 143
144 atmel_attach() creates an "instance" of the driver, allocating 144 atmel_attach() creates an "instance" of the driver, allocating
145 local data structures for one device. The device is registered 145 local data structures for one device. The device is registered
146 with Card Services. 146 with Card Services.
147 147
148 The dev_link structure is initialized, but we don't actually 148 The dev_link structure is initialized, but we don't actually
149 configure the card at this point -- we wait until we receive a 149 configure the card at this point -- we wait until we receive a
150 card insertion event. 150 card insertion event.
151 151
152 ======================================================================*/ 152 ======================================================================*/
153 153
154static int atmel_probe(struct pcmcia_device *p_dev) 154static int atmel_probe(struct pcmcia_device *p_dev)
@@ -184,12 +184,12 @@ static int atmel_probe(struct pcmcia_device *p_dev)
184} /* atmel_attach */ 184} /* atmel_attach */
185 185
186/*====================================================================== 186/*======================================================================
187 187
188 This deletes a driver "instance". The device is de-registered 188 This deletes a driver "instance". The device is de-registered
189 with Card Services. If it has been released, all local data 189 with Card Services. If it has been released, all local data
190 structures are freed. Otherwise, the structures will be freed 190 structures are freed. Otherwise, the structures will be freed
191 when the device is released. 191 when the device is released.
192 192
193 ======================================================================*/ 193 ======================================================================*/
194 194
195static void atmel_detach(struct pcmcia_device *link) 195static void atmel_detach(struct pcmcia_device *link)
@@ -202,11 +202,11 @@ static void atmel_detach(struct pcmcia_device *link)
202} 202}
203 203
204/*====================================================================== 204/*======================================================================
205 205
206 atmel_config() is scheduled to run after a CARD_INSERTION event 206 atmel_config() is scheduled to run after a CARD_INSERTION event
207 is received, to configure the PCMCIA socket, and to make the 207 is received, to configure the PCMCIA socket, and to make the
208 device available to the system. 208 device available to the system.
209 209
210 ======================================================================*/ 210 ======================================================================*/
211 211
212#define CS_CHECK(fn, ret) \ 212#define CS_CHECK(fn, ret) \
@@ -237,12 +237,12 @@ static int atmel_config(struct pcmcia_device *link)
237 did = handle_to_dev(link).driver_data; 237 did = handle_to_dev(link).driver_data;
238 238
239 DEBUG(0, "atmel_config(0x%p)\n", link); 239 DEBUG(0, "atmel_config(0x%p)\n", link);
240 240
241 tuple.Attributes = 0; 241 tuple.Attributes = 0;
242 tuple.TupleData = buf; 242 tuple.TupleData = buf;
243 tuple.TupleDataMax = sizeof(buf); 243 tuple.TupleDataMax = sizeof(buf);
244 tuple.TupleOffset = 0; 244 tuple.TupleOffset = 0;
245 245
246 /* 246 /*
247 This reads the card's CONFIG tuple to find its configuration 247 This reads the card's CONFIG tuple to find its configuration
248 registers. 248 registers.
@@ -258,7 +258,7 @@ static int atmel_config(struct pcmcia_device *link)
258 In this loop, we scan the CIS for configuration table entries, 258 In this loop, we scan the CIS for configuration table entries,
259 each of which describes a valid card configuration, including 259 each of which describes a valid card configuration, including
260 voltage, IO window, memory window, and interrupt settings. 260 voltage, IO window, memory window, and interrupt settings.
261 261
262 We make no assumptions about the card to be configured: we use 262 We make no assumptions about the card to be configured: we use
263 just the information available in the CIS. In an ideal world, 263 just the information available in the CIS. In an ideal world,
264 this would work for any PCMCIA card, but it requires a complete 264 this would work for any PCMCIA card, but it requires a complete
@@ -274,17 +274,17 @@ static int atmel_config(struct pcmcia_device *link)
274 if (pcmcia_get_tuple_data(link, &tuple) != 0 || 274 if (pcmcia_get_tuple_data(link, &tuple) != 0 ||
275 pcmcia_parse_tuple(link, &tuple, &parse) != 0) 275 pcmcia_parse_tuple(link, &tuple, &parse) != 0)
276 goto next_entry; 276 goto next_entry;
277 277
278 if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg; 278 if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg;
279 if (cfg->index == 0) goto next_entry; 279 if (cfg->index == 0) goto next_entry;
280 link->conf.ConfigIndex = cfg->index; 280 link->conf.ConfigIndex = cfg->index;
281 281
282 /* Does this card need audio output? */ 282 /* Does this card need audio output? */
283 if (cfg->flags & CISTPL_CFTABLE_AUDIO) { 283 if (cfg->flags & CISTPL_CFTABLE_AUDIO) {
284 link->conf.Attributes |= CONF_ENABLE_SPKR; 284 link->conf.Attributes |= CONF_ENABLE_SPKR;
285 link->conf.Status = CCSR_AUDIO_ENA; 285 link->conf.Status = CCSR_AUDIO_ENA;
286 } 286 }
287 287
288 /* Use power settings for Vcc and Vpp if present */ 288 /* Use power settings for Vcc and Vpp if present */
289 /* Note that the CIS values need to be rescaled */ 289 /* Note that the CIS values need to be rescaled */
290 if (cfg->vpp1.present & (1<<CISTPL_POWER_VNOM)) 290 if (cfg->vpp1.present & (1<<CISTPL_POWER_VNOM))
@@ -293,11 +293,11 @@ static int atmel_config(struct pcmcia_device *link)
293 else if (dflt.vpp1.present & (1<<CISTPL_POWER_VNOM)) 293 else if (dflt.vpp1.present & (1<<CISTPL_POWER_VNOM))
294 link->conf.Vpp = 294 link->conf.Vpp =
295 dflt.vpp1.param[CISTPL_POWER_VNOM]/10000; 295 dflt.vpp1.param[CISTPL_POWER_VNOM]/10000;
296 296
297 /* Do we need to allocate an interrupt? */ 297 /* Do we need to allocate an interrupt? */
298 if (cfg->irq.IRQInfo1 || dflt.irq.IRQInfo1) 298 if (cfg->irq.IRQInfo1 || dflt.irq.IRQInfo1)
299 link->conf.Attributes |= CONF_ENABLE_IRQ; 299 link->conf.Attributes |= CONF_ENABLE_IRQ;
300 300
301 /* IO window settings */ 301 /* IO window settings */
302 link->io.NumPorts1 = link->io.NumPorts2 = 0; 302 link->io.NumPorts1 = link->io.NumPorts2 = 0;
303 if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) { 303 if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
@@ -315,18 +315,18 @@ static int atmel_config(struct pcmcia_device *link)
315 link->io.NumPorts2 = io->win[1].len; 315 link->io.NumPorts2 = io->win[1].len;
316 } 316 }
317 } 317 }
318 318
319 /* This reserves IO space but doesn't actually enable it */ 319 /* This reserves IO space but doesn't actually enable it */
320 if (pcmcia_request_io(link, &link->io) != 0) 320 if (pcmcia_request_io(link, &link->io) != 0)
321 goto next_entry; 321 goto next_entry;
322 322
323 /* If we got this far, we're cool! */ 323 /* If we got this far, we're cool! */
324 break; 324 break;
325 325
326 next_entry: 326 next_entry:
327 CS_CHECK(GetNextTuple, pcmcia_get_next_tuple(link, &tuple)); 327 CS_CHECK(GetNextTuple, pcmcia_get_next_tuple(link, &tuple));
328 } 328 }
329 329
330 /* 330 /*
331 Allocate an interrupt line. Note that this does not assign a 331 Allocate an interrupt line. Note that this does not assign a
332 handler to the interrupt, unless the 'Handler' member of the 332 handler to the interrupt, unless the 'Handler' member of the
@@ -334,31 +334,31 @@ static int atmel_config(struct pcmcia_device *link)
334 */ 334 */
335 if (link->conf.Attributes & CONF_ENABLE_IRQ) 335 if (link->conf.Attributes & CONF_ENABLE_IRQ)
336 CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq)); 336 CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
337 337
338 /* 338 /*
339 This actually configures the PCMCIA socket -- setting up 339 This actually configures the PCMCIA socket -- setting up
340 the I/O windows and the interrupt mapping, and putting the 340 the I/O windows and the interrupt mapping, and putting the
341 card and host interface into "Memory and IO" mode. 341 card and host interface into "Memory and IO" mode.
342 */ 342 */
343 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf)); 343 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
344 344
345 if (link->irq.AssignedIRQ == 0) { 345 if (link->irq.AssignedIRQ == 0) {
346 printk(KERN_ALERT 346 printk(KERN_ALERT
347 "atmel: cannot assign IRQ: check that CONFIG_ISA is set in kernel config."); 347 "atmel: cannot assign IRQ: check that CONFIG_ISA is set in kernel config.");
348 goto cs_failed; 348 goto cs_failed;
349 } 349 }
350 350
351 ((local_info_t*)link->priv)->eth_dev = 351 ((local_info_t*)link->priv)->eth_dev =
352 init_atmel_card(link->irq.AssignedIRQ, 352 init_atmel_card(link->irq.AssignedIRQ,
353 link->io.BasePort1, 353 link->io.BasePort1,
354 did ? did->driver_info : ATMEL_FW_TYPE_NONE, 354 did ? did->driver_info : ATMEL_FW_TYPE_NONE,
355 &handle_to_dev(link), 355 &handle_to_dev(link),
356 card_present, 356 card_present,
357 link); 357 link);
358 if (!((local_info_t*)link->priv)->eth_dev) 358 if (!((local_info_t*)link->priv)->eth_dev)
359 goto cs_failed; 359 goto cs_failed;
360 360
361 361
362 /* 362 /*
363 At this point, the dev_node_t structure(s) need to be 363 At this point, the dev_node_t structure(s) need to be
364 initialized and arranged in a linked list at link->dev_node. 364 initialized and arranged in a linked list at link->dev_node.
@@ -376,11 +376,11 @@ static int atmel_config(struct pcmcia_device *link)
376} 376}
377 377
378/*====================================================================== 378/*======================================================================
379 379
380 After a card is removed, atmel_release() will unregister the 380 After a card is removed, atmel_release() will unregister the
381 device, and release the PCMCIA configuration. If the device is 381 device, and release the PCMCIA configuration. If the device is
382 still open, this will be postponed until it is closed. 382 still open, this will be postponed until it is closed.
383 383
384 ======================================================================*/ 384 ======================================================================*/
385 385
386static void atmel_release(struct pcmcia_device *link) 386static void atmel_release(struct pcmcia_device *link)
@@ -517,7 +517,7 @@ static void atmel_cs_cleanup(void)
517 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 517 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
518 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 518 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
519 IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 519 IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
520 POSSIBILITY OF SUCH DAMAGE. 520 POSSIBILITY OF SUCH DAMAGE.
521*/ 521*/
522 522
523module_init(atmel_cs_init); 523module_init(atmel_cs_init);
diff --git a/drivers/net/wireless/atmel_pci.c b/drivers/net/wireless/atmel_pci.c
index 3bfa791c323d..92f87fbe750f 100644
--- a/drivers/net/wireless/atmel_pci.c
+++ b/drivers/net/wireless/atmel_pci.c
@@ -53,18 +53,18 @@ static int __devinit atmel_pci_probe(struct pci_dev *pdev,
53 const struct pci_device_id *pent) 53 const struct pci_device_id *pent)
54{ 54{
55 struct net_device *dev; 55 struct net_device *dev;
56 56
57 if (pci_enable_device(pdev)) 57 if (pci_enable_device(pdev))
58 return -ENODEV; 58 return -ENODEV;
59 59
60 pci_set_master(pdev); 60 pci_set_master(pdev);
61 61
62 dev = init_atmel_card(pdev->irq, pdev->resource[1].start, 62 dev = init_atmel_card(pdev->irq, pdev->resource[1].start,
63 ATMEL_FW_TYPE_506, 63 ATMEL_FW_TYPE_506,
64 &pdev->dev, NULL, NULL); 64 &pdev->dev, NULL, NULL);
65 if (!dev) 65 if (!dev)
66 return -ENODEV; 66 return -ENODEV;
67 67
68 pci_set_drvdata(pdev, dev); 68 pci_set_drvdata(pdev, dev);
69 return 0; 69 return 0;
70} 70}
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx.h b/drivers/net/wireless/bcm43xx/bcm43xx.h
index fbc0c087f53c..8286678513b9 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx.h
+++ b/drivers/net/wireless/bcm43xx/bcm43xx.h
@@ -159,6 +159,7 @@
159 159
160/* Chipcommon registers. */ 160/* Chipcommon registers. */
161#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 161#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
162#define BCM43xx_CHIPCOMMON_CTL 0x28
162#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 163#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
163#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 164#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
164#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 165#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
@@ -172,6 +173,33 @@
172/* SBTOPCI2 values. */ 173/* SBTOPCI2 values. */
173#define BCM43xx_SBTOPCI2_PREFETCH 0x4 174#define BCM43xx_SBTOPCI2_PREFETCH 0x4
174#define BCM43xx_SBTOPCI2_BURST 0x8 175#define BCM43xx_SBTOPCI2_BURST 0x8
176#define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20
177
178/* PCI-E core registers. */
179#define BCM43xx_PCIECORE_REG_ADDR 0x0130
180#define BCM43xx_PCIECORE_REG_DATA 0x0134
181#define BCM43xx_PCIECORE_MDIO_CTL 0x0128
182#define BCM43xx_PCIECORE_MDIO_DATA 0x012C
183
184/* PCI-E registers. */
185#define BCM43xx_PCIE_TLP_WORKAROUND 0x0004
186#define BCM43xx_PCIE_DLLP_LINKCTL 0x0100
187
188/* PCI-E MDIO bits. */
189#define BCM43xx_PCIE_MDIO_ST 0x40000000
190#define BCM43xx_PCIE_MDIO_WT 0x10000000
191#define BCM43xx_PCIE_MDIO_DEV 22
192#define BCM43xx_PCIE_MDIO_REG 18
193#define BCM43xx_PCIE_MDIO_TA 0x00020000
194#define BCM43xx_PCIE_MDIO_TC 0x0100
195
196/* MDIO devices. */
197#define BCM43xx_MDIO_SERDES_RX 0x1F
198
199/* SERDES RX registers. */
200#define BCM43xx_SERDES_RXTIMER 0x2
201#define BCM43xx_SERDES_CDR 0x6
202#define BCM43xx_SERDES_CDR_BW 0x7
175 203
176/* Chipcommon capabilities. */ 204/* Chipcommon capabilities. */
177#define BCM43xx_CAPABILITIES_PCTL 0x00040000 205#define BCM43xx_CAPABILITIES_PCTL 0x00040000
@@ -221,6 +249,7 @@
221#define BCM43xx_COREID_USB20_HOST 0x819 249#define BCM43xx_COREID_USB20_HOST 0x819
222#define BCM43xx_COREID_USB20_DEV 0x81a 250#define BCM43xx_COREID_USB20_DEV 0x81a
223#define BCM43xx_COREID_SDIO_HOST 0x81b 251#define BCM43xx_COREID_SDIO_HOST 0x81b
252#define BCM43xx_COREID_PCIE 0x820
224 253
225/* Core Information Registers */ 254/* Core Information Registers */
226#define BCM43xx_CIR_BASE 0xf00 255#define BCM43xx_CIR_BASE 0xf00
@@ -365,6 +394,9 @@
365#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 394#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
366#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 395#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
367 396
397/* FIXME: the next line is a guess as to what the maximum RSSI value might be */
398#define RX_RSSI_MAX 60
399
368/* Max size of a security key */ 400/* Max size of a security key */
369#define BCM43xx_SEC_KEYSIZE 16 401#define BCM43xx_SEC_KEYSIZE 16
370/* Security algorithms. */ 402/* Security algorithms. */
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_main.c b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
index 728a9b789fdf..2ec2e5afce67 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_main.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
@@ -130,6 +130,10 @@ MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4307 802.11b */ 131 /* Broadcom 4307 802.11b */
132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4311 802.11(a)/b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4312 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */ 137 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4319 802.11a/b/g */ 139 /* Broadcom 4319 802.11a/b/g */
@@ -2600,8 +2604,9 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2600 /* fetch sb_id_hi from core information registers */ 2604 /* fetch sb_id_hi from core information registers */
2601 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI); 2605 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2602 2606
2603 core_id = (sb_id_hi & 0xFFF0) >> 4; 2607 core_id = (sb_id_hi & 0x8FF0) >> 4;
2604 core_rev = (sb_id_hi & 0xF); 2608 core_rev = (sb_id_hi & 0x7000) >> 8;
2609 core_rev |= (sb_id_hi & 0xF);
2605 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16; 2610 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2606 2611
2607 /* if present, chipcommon is always core 0; read the chipid from it */ 2612 /* if present, chipcommon is always core 0; read the chipid from it */
@@ -2679,14 +2684,10 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2679 bcm->chip_id, bcm->chip_rev); 2684 bcm->chip_id, bcm->chip_rev);
2680 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count); 2685 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2681 if (bcm->core_chipcommon.available) { 2686 if (bcm->core_chipcommon.available) {
2682 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n", 2687 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2683 core_id, core_rev, core_vendor, 2688 core_id, core_rev, core_vendor);
2684 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2685 }
2686
2687 if (bcm->core_chipcommon.available)
2688 current_core = 1; 2689 current_core = 1;
2689 else 2690 } else
2690 current_core = 0; 2691 current_core = 0;
2691 for ( ; current_core < core_count; current_core++) { 2692 for ( ; current_core < core_count; current_core++) {
2692 struct bcm43xx_coreinfo *core; 2693 struct bcm43xx_coreinfo *core;
@@ -2704,13 +2705,13 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2704 core_rev = (sb_id_hi & 0xF); 2705 core_rev = (sb_id_hi & 0xF);
2705 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16; 2706 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2706 2707
2707 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n", 2708 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2708 current_core, core_id, core_rev, core_vendor, 2709 current_core, core_id, core_rev, core_vendor);
2709 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2710 2710
2711 core = NULL; 2711 core = NULL;
2712 switch (core_id) { 2712 switch (core_id) {
2713 case BCM43xx_COREID_PCI: 2713 case BCM43xx_COREID_PCI:
2714 case BCM43xx_COREID_PCIE:
2714 core = &bcm->core_pci; 2715 core = &bcm->core_pci;
2715 if (core->available) { 2716 if (core->available) {
2716 printk(KERN_WARNING PFX "Multiple PCI cores found.\n"); 2717 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
@@ -2749,12 +2750,12 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2749 case 6: 2750 case 6:
2750 case 7: 2751 case 7:
2751 case 9: 2752 case 9:
2753 case 10:
2752 break; 2754 break;
2753 default: 2755 default:
2754 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n", 2756 printk(KERN_WARNING PFX
2757 "Unsupported 80211 core revision %u\n",
2755 core_rev); 2758 core_rev);
2756 err = -ENODEV;
2757 goto out;
2758 } 2759 }
2759 bcm->nr_80211_available++; 2760 bcm->nr_80211_available++;
2760 core->priv = ext_80211; 2761 core->priv = ext_80211;
@@ -2868,16 +2869,11 @@ static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2868 u32 sbimconfiglow; 2869 u32 sbimconfiglow;
2869 u8 limit; 2870 u8 limit;
2870 2871
2871 if (bcm->chip_rev < 5) { 2872 if (bcm->core_pci.rev <= 5 && bcm->core_pci.id != BCM43xx_COREID_PCIE) {
2872 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW); 2873 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2873 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK; 2874 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2874 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK; 2875 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2875 if (bcm->bustype == BCM43xx_BUSTYPE_PCI) 2876 sbimconfiglow |= 0x32;
2876 sbimconfiglow |= 0x32;
2877 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2878 sbimconfiglow |= 0x53;
2879 else
2880 assert(0);
2881 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow); 2877 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2882 } 2878 }
2883 2879
@@ -3004,22 +3000,64 @@ static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
3004 3000
3005static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm) 3001static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
3006{ 3002{
3007 int err; 3003 int err = 0;
3008 struct bcm43xx_coreinfo *old_core;
3009 3004
3010 old_core = bcm->current_core; 3005 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3011 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3012 if (err)
3013 goto out;
3014 3006
3015 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000); 3007 if (bcm->core_chipcommon.available) {
3008 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
3009 if (err)
3010 goto out;
3011
3012 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3013
3014 /* this function is always called when a PCI core is mapped */
3015 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3016 if (err)
3017 goto out;
3018 } else
3019 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3020
3021 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3016 3022
3017 bcm43xx_switch_core(bcm, old_core);
3018 assert(err == 0);
3019out: 3023out:
3020 return err; 3024 return err;
3021} 3025}
3022 3026
3027static u32 bcm43xx_pcie_reg_read(struct bcm43xx_private *bcm, u32 address)
3028{
3029 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3030 return bcm43xx_read32(bcm, BCM43xx_PCIECORE_REG_DATA);
3031}
3032
3033static void bcm43xx_pcie_reg_write(struct bcm43xx_private *bcm, u32 address,
3034 u32 data)
3035{
3036 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3037 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_DATA, data);
3038}
3039
3040static void bcm43xx_pcie_mdio_write(struct bcm43xx_private *bcm, u8 dev, u8 reg,
3041 u16 data)
3042{
3043 int i;
3044
3045 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0x0082);
3046 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_DATA, BCM43xx_PCIE_MDIO_ST |
3047 BCM43xx_PCIE_MDIO_WT | (dev << BCM43xx_PCIE_MDIO_DEV) |
3048 (reg << BCM43xx_PCIE_MDIO_REG) | BCM43xx_PCIE_MDIO_TA |
3049 data);
3050 udelay(10);
3051
3052 for (i = 0; i < 10; i++) {
3053 if (bcm43xx_read32(bcm, BCM43xx_PCIECORE_MDIO_CTL) &
3054 BCM43xx_PCIE_MDIO_TC)
3055 break;
3056 msleep(1);
3057 }
3058 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0);
3059}
3060
3023/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable. 3061/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3024 * To enable core 0, pass a core_mask of 1<<0 3062 * To enable core 0, pass a core_mask of 1<<0
3025 */ 3063 */
@@ -3039,7 +3077,8 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3039 if (err) 3077 if (err)
3040 goto out; 3078 goto out;
3041 3079
3042 if (bcm->core_pci.rev < 6) { 3080 if (bcm->current_core->rev < 6 ||
3081 bcm->current_core->id == BCM43xx_COREID_PCI) {
3043 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC); 3082 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3044 value |= (1 << backplane_flag_nr); 3083 value |= (1 << backplane_flag_nr);
3045 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value); 3084 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
@@ -3057,21 +3096,46 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3057 } 3096 }
3058 } 3097 }
3059 3098
3060 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2); 3099 if (bcm->current_core->id == BCM43xx_COREID_PCI) {
3061 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST; 3100 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3062 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value); 3101 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3063 3102 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3064 if (bcm->core_pci.rev < 5) { 3103
3065 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW); 3104 if (bcm->current_core->rev < 5) {
3066 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT) 3105 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3067 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK; 3106 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3068 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT) 3107 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3069 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK; 3108 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3070 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value); 3109 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3071 err = bcm43xx_pcicore_commit_settings(bcm); 3110 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3072 assert(err == 0); 3111 err = bcm43xx_pcicore_commit_settings(bcm);
3112 assert(err == 0);
3113 } else if (bcm->current_core->rev >= 11) {
3114 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3115 value |= BCM43xx_SBTOPCI2_MEMREAD_MULTI;
3116 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3117 }
3118 } else {
3119 if (bcm->current_core->rev == 0 || bcm->current_core->rev == 1) {
3120 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_TLP_WORKAROUND);
3121 value |= 0x8;
3122 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_TLP_WORKAROUND,
3123 value);
3124 }
3125 if (bcm->current_core->rev == 0) {
3126 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3127 BCM43xx_SERDES_RXTIMER, 0x8128);
3128 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3129 BCM43xx_SERDES_CDR, 0x0100);
3130 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3131 BCM43xx_SERDES_CDR_BW, 0x1466);
3132 } else if (bcm->current_core->rev == 1) {
3133 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_DLLP_LINKCTL);
3134 value |= 0x40;
3135 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_DLLP_LINKCTL,
3136 value);
3137 }
3073 } 3138 }
3074
3075out_switch_back: 3139out_switch_back:
3076 err = bcm43xx_switch_core(bcm, old_core); 3140 err = bcm43xx_switch_core(bcm, old_core);
3077out: 3141out:
@@ -3140,43 +3204,17 @@ static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3140 3204
3141static void do_periodic_work(struct bcm43xx_private *bcm) 3205static void do_periodic_work(struct bcm43xx_private *bcm)
3142{ 3206{
3143 unsigned int state; 3207 if (bcm->periodic_state % 8 == 0)
3144
3145 state = bcm->periodic_state;
3146 if (state % 8 == 0)
3147 bcm43xx_periodic_every120sec(bcm); 3208 bcm43xx_periodic_every120sec(bcm);
3148 if (state % 4 == 0) 3209 if (bcm->periodic_state % 4 == 0)
3149 bcm43xx_periodic_every60sec(bcm); 3210 bcm43xx_periodic_every60sec(bcm);
3150 if (state % 2 == 0) 3211 if (bcm->periodic_state % 2 == 0)
3151 bcm43xx_periodic_every30sec(bcm); 3212 bcm43xx_periodic_every30sec(bcm);
3152 if (state % 1 == 0) 3213 bcm43xx_periodic_every15sec(bcm);
3153 bcm43xx_periodic_every15sec(bcm);
3154 bcm->periodic_state = state + 1;
3155 3214
3156 schedule_delayed_work(&bcm->periodic_work, HZ * 15); 3215 schedule_delayed_work(&bcm->periodic_work, HZ * 15);
3157} 3216}
3158 3217
3159/* Estimate a "Badness" value based on the periodic work
3160 * state-machine state. "Badness" is worse (bigger), if the
3161 * periodic work will take longer.
3162 */
3163static int estimate_periodic_work_badness(unsigned int state)
3164{
3165 int badness = 0;
3166
3167 if (state % 8 == 0) /* every 120 sec */
3168 badness += 10;
3169 if (state % 4 == 0) /* every 60 sec */
3170 badness += 5;
3171 if (state % 2 == 0) /* every 30 sec */
3172 badness += 1;
3173 if (state % 1 == 0) /* every 15 sec */
3174 badness += 1;
3175
3176#define BADNESS_LIMIT 4
3177 return badness;
3178}
3179
3180static void bcm43xx_periodic_work_handler(struct work_struct *work) 3218static void bcm43xx_periodic_work_handler(struct work_struct *work)
3181{ 3219{
3182 struct bcm43xx_private *bcm = 3220 struct bcm43xx_private *bcm =
@@ -3184,12 +3222,10 @@ static void bcm43xx_periodic_work_handler(struct work_struct *work)
3184 struct net_device *net_dev = bcm->net_dev; 3222 struct net_device *net_dev = bcm->net_dev;
3185 unsigned long flags; 3223 unsigned long flags;
3186 u32 savedirqs = 0; 3224 u32 savedirqs = 0;
3187 int badness;
3188 unsigned long orig_trans_start = 0; 3225 unsigned long orig_trans_start = 0;
3189 3226
3190 mutex_lock(&bcm->mutex); 3227 mutex_lock(&bcm->mutex);
3191 badness = estimate_periodic_work_badness(bcm->periodic_state); 3228 if (unlikely(bcm->periodic_state % 4 == 0)) {
3192 if (badness > BADNESS_LIMIT) {
3193 /* Periodic work will take a long time, so we want it to 3229 /* Periodic work will take a long time, so we want it to
3194 * be preemtible. 3230 * be preemtible.
3195 */ 3231 */
@@ -3221,7 +3257,7 @@ static void bcm43xx_periodic_work_handler(struct work_struct *work)
3221 3257
3222 do_periodic_work(bcm); 3258 do_periodic_work(bcm);
3223 3259
3224 if (badness > BADNESS_LIMIT) { 3260 if (unlikely(bcm->periodic_state % 4 == 0)) {
3225 spin_lock_irqsave(&bcm->irq_lock, flags); 3261 spin_lock_irqsave(&bcm->irq_lock, flags);
3226 tasklet_enable(&bcm->isr_tasklet); 3262 tasklet_enable(&bcm->isr_tasklet);
3227 bcm43xx_interrupt_enable(bcm, savedirqs); 3263 bcm43xx_interrupt_enable(bcm, savedirqs);
@@ -3232,6 +3268,7 @@ static void bcm43xx_periodic_work_handler(struct work_struct *work)
3232 net_dev->trans_start = orig_trans_start; 3268 net_dev->trans_start = orig_trans_start;
3233 } 3269 }
3234 mmiowb(); 3270 mmiowb();
3271 bcm->periodic_state++;
3235 spin_unlock_irqrestore(&bcm->irq_lock, flags); 3272 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3236 mutex_unlock(&bcm->mutex); 3273 mutex_unlock(&bcm->mutex);
3237} 3274}
@@ -3677,7 +3714,7 @@ static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3677 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND; 3714 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3678 break; 3715 break;
3679 case BCM43xx_PHYTYPE_G: 3716 case BCM43xx_PHYTYPE_G:
3680 if (phy_rev > 7) 3717 if (phy_rev > 8)
3681 phy_rev_ok = 0; 3718 phy_rev_ok = 0;
3682 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION | 3719 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3683 IEEE80211_CCK_MODULATION; 3720 IEEE80211_CCK_MODULATION;
@@ -3689,6 +3726,8 @@ static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3689 phy_type); 3726 phy_type);
3690 return -ENODEV; 3727 return -ENODEV;
3691 }; 3728 };
3729 bcm->ieee->perfect_rssi = RX_RSSI_MAX;
3730 bcm->ieee->worst_rssi = 0;
3692 if (!phy_rev_ok) { 3731 if (!phy_rev_ok) {
3693 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n", 3732 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3694 phy_rev); 3733 phy_rev);
@@ -3975,11 +4014,6 @@ static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3975 return NETDEV_TX_OK; 4014 return NETDEV_TX_OK;
3976} 4015}
3977 4016
3978static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3979{
3980 return &(bcm43xx_priv(net_dev)->ieee->stats);
3981}
3982
3983static void bcm43xx_net_tx_timeout(struct net_device *net_dev) 4017static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3984{ 4018{
3985 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev); 4019 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
@@ -4093,7 +4127,6 @@ static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4093 4127
4094 net_dev->open = bcm43xx_net_open; 4128 net_dev->open = bcm43xx_net_open;
4095 net_dev->stop = bcm43xx_net_stop; 4129 net_dev->stop = bcm43xx_net_stop;
4096 net_dev->get_stats = bcm43xx_net_get_stats;
4097 net_dev->tx_timeout = bcm43xx_net_tx_timeout; 4130 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4098#ifdef CONFIG_NET_POLL_CONTROLLER 4131#ifdef CONFIG_NET_POLL_CONTROLLER
4099 net_dev->poll_controller = bcm43xx_net_poll_controller; 4132 net_dev->poll_controller = bcm43xx_net_poll_controller;
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_power.c b/drivers/net/wireless/bcm43xx/bcm43xx_power.c
index 6569da3a7a39..7e774f410953 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_power.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_power.c
@@ -153,8 +153,6 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
153 int err, maxfreq; 153 int err, maxfreq;
154 struct bcm43xx_coreinfo *old_core; 154 struct bcm43xx_coreinfo *old_core;
155 155
156 if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
157 return 0;
158 old_core = bcm->current_core; 156 old_core = bcm->current_core;
159 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon); 157 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
160 if (err == -ENODEV) 158 if (err == -ENODEV)
@@ -162,11 +160,27 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
162 if (err) 160 if (err)
163 goto out; 161 goto out;
164 162
165 maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1); 163 if (bcm->chip_id == 0x4321) {
166 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY, 164 if (bcm->chip_rev == 0)
167 (maxfreq * 150 + 999999) / 1000000); 165 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x03A4);
168 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY, 166 if (bcm->chip_rev == 1)
169 (maxfreq * 15 + 999999) / 1000000); 167 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x00A4);
168 }
169
170 if (bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL) {
171 if (bcm->current_core->rev >= 10) {
172 /* Set Idle Power clock rate to 1Mhz */
173 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL,
174 (bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL)
175 & 0x0000FFFF) | 0x40000);
176 } else {
177 maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
178 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
179 (maxfreq * 150 + 999999) / 1000000);
180 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
181 (maxfreq * 15 + 999999) / 1000000);
182 }
183 }
170 184
171 err = bcm43xx_switch_core(bcm, old_core); 185 err = bcm43xx_switch_core(bcm, old_core);
172 assert(err == 0); 186 assert(err == 0);
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_wx.c b/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
index d27016f8c736..a659442b9c15 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
@@ -47,9 +47,6 @@
47#define BCM43xx_WX_VERSION 18 47#define BCM43xx_WX_VERSION 18
48 48
49#define MAX_WX_STRING 80 49#define MAX_WX_STRING 80
50/* FIXME: the next line is a guess as to what the maximum RSSI value might be */
51#define RX_RSSI_MAX 60
52
53 50
54static int bcm43xx_wx_get_name(struct net_device *net_dev, 51static int bcm43xx_wx_get_name(struct net_device *net_dev,
55 struct iw_request_info *info, 52 struct iw_request_info *info,
@@ -693,6 +690,7 @@ static int bcm43xx_wx_set_swencryption(struct net_device *net_dev,
693 bcm->ieee->host_encrypt = !!on; 690 bcm->ieee->host_encrypt = !!on;
694 bcm->ieee->host_decrypt = !!on; 691 bcm->ieee->host_decrypt = !!on;
695 bcm->ieee->host_build_iv = !on; 692 bcm->ieee->host_build_iv = !on;
693 bcm->ieee->host_strip_iv_icv = !on;
696 spin_unlock_irqrestore(&bcm->irq_lock, flags); 694 spin_unlock_irqrestore(&bcm->irq_lock, flags);
697 mutex_unlock(&bcm->mutex); 695 mutex_unlock(&bcm->mutex);
698 696
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c b/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
index 0159e4e93201..3e2462671690 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
@@ -544,24 +544,6 @@ int bcm43xx_rx(struct bcm43xx_private *bcm,
544 } 544 }
545 545
546 frame_ctl = le16_to_cpu(wlhdr->frame_ctl); 546 frame_ctl = le16_to_cpu(wlhdr->frame_ctl);
547 if ((frame_ctl & IEEE80211_FCTL_PROTECTED) && !bcm->ieee->host_decrypt) {
548 frame_ctl &= ~IEEE80211_FCTL_PROTECTED;
549 wlhdr->frame_ctl = cpu_to_le16(frame_ctl);
550 /* trim IV and ICV */
551 /* FIXME: this must be done only for WEP encrypted packets */
552 if (skb->len < 32) {
553 dprintkl(KERN_ERR PFX "RX packet dropped (PROTECTED flag "
554 "set and length < 32)\n");
555 return -EINVAL;
556 } else {
557 memmove(skb->data + 4, skb->data, 24);
558 skb_pull(skb, 4);
559 skb_trim(skb, skb->len - 4);
560 stats.len -= 8;
561 }
562 wlhdr = (struct ieee80211_hdr_4addr *)(skb->data);
563 }
564
565 switch (WLAN_FC_GET_TYPE(frame_ctl)) { 547 switch (WLAN_FC_GET_TYPE(frame_ctl)) {
566 case IEEE80211_FTYPE_MGMT: 548 case IEEE80211_FTYPE_MGMT:
567 ieee80211_rx_mgt(bcm->ieee, wlhdr, &stats); 549 ieee80211_rx_mgt(bcm->ieee, wlhdr, &stats);
diff --git a/drivers/net/wireless/hostap/hostap_pci.c b/drivers/net/wireless/hostap/hostap_pci.c
index c2fa011be291..d1de9766c831 100644
--- a/drivers/net/wireless/hostap/hostap_pci.c
+++ b/drivers/net/wireless/hostap/hostap_pci.c
@@ -425,8 +425,14 @@ static int prism2_pci_suspend(struct pci_dev *pdev, pm_message_t state)
425static int prism2_pci_resume(struct pci_dev *pdev) 425static int prism2_pci_resume(struct pci_dev *pdev)
426{ 426{
427 struct net_device *dev = pci_get_drvdata(pdev); 427 struct net_device *dev = pci_get_drvdata(pdev);
428 int err;
428 429
429 pci_enable_device(pdev); 430 err = pci_enable_device(pdev);
431 if (err) {
432 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
433 dev->name);
434 return err;
435 }
430 pci_restore_state(pdev); 436 pci_restore_state(pdev);
431 prism2_hw_config(dev, 0); 437 prism2_hw_config(dev, 0);
432 if (netif_running(dev)) { 438 if (netif_running(dev)) {
diff --git a/drivers/net/wireless/ipw2100.c b/drivers/net/wireless/ipw2100.c
index 0f554373a60d..1bcd352a813b 100644
--- a/drivers/net/wireless/ipw2100.c
+++ b/drivers/net/wireless/ipw2100.c
@@ -5833,19 +5833,6 @@ static void ipw2100_tx_timeout(struct net_device *dev)
5833 schedule_reset(priv); 5833 schedule_reset(priv);
5834} 5834}
5835 5835
5836/*
5837 * TODO: reimplement it so that it reads statistics
5838 * from the adapter using ordinal tables
5839 * instead of/in addition to collecting them
5840 * in the driver
5841 */
5842static struct net_device_stats *ipw2100_stats(struct net_device *dev)
5843{
5844 struct ipw2100_priv *priv = ieee80211_priv(dev);
5845
5846 return &priv->ieee->stats;
5847}
5848
5849static int ipw2100_wpa_enable(struct ipw2100_priv *priv, int value) 5836static int ipw2100_wpa_enable(struct ipw2100_priv *priv, int value)
5850{ 5837{
5851 /* This is called when wpa_supplicant loads and closes the driver 5838 /* This is called when wpa_supplicant loads and closes the driver
@@ -6030,7 +6017,6 @@ static struct net_device *ipw2100_alloc_device(struct pci_dev *pci_dev,
6030 dev->open = ipw2100_open; 6017 dev->open = ipw2100_open;
6031 dev->stop = ipw2100_close; 6018 dev->stop = ipw2100_close;
6032 dev->init = ipw2100_net_init; 6019 dev->init = ipw2100_net_init;
6033 dev->get_stats = ipw2100_stats;
6034 dev->ethtool_ops = &ipw2100_ethtool_ops; 6020 dev->ethtool_ops = &ipw2100_ethtool_ops;
6035 dev->tx_timeout = ipw2100_tx_timeout; 6021 dev->tx_timeout = ipw2100_tx_timeout;
6036 dev->wireless_handlers = &ipw2100_wx_handler_def; 6022 dev->wireless_handlers = &ipw2100_wx_handler_def;
@@ -6428,6 +6414,7 @@ static int ipw2100_resume(struct pci_dev *pci_dev)
6428{ 6414{
6429 struct ipw2100_priv *priv = pci_get_drvdata(pci_dev); 6415 struct ipw2100_priv *priv = pci_get_drvdata(pci_dev);
6430 struct net_device *dev = priv->net_dev; 6416 struct net_device *dev = priv->net_dev;
6417 int err;
6431 u32 val; 6418 u32 val;
6432 6419
6433 if (IPW2100_PM_DISABLED) 6420 if (IPW2100_PM_DISABLED)
@@ -6438,7 +6425,12 @@ static int ipw2100_resume(struct pci_dev *pci_dev)
6438 IPW_DEBUG_INFO("%s: Coming out of suspend...\n", dev->name); 6425 IPW_DEBUG_INFO("%s: Coming out of suspend...\n", dev->name);
6439 6426
6440 pci_set_power_state(pci_dev, PCI_D0); 6427 pci_set_power_state(pci_dev, PCI_D0);
6441 pci_enable_device(pci_dev); 6428 err = pci_enable_device(pci_dev);
6429 if (err) {
6430 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
6431 dev->name);
6432 return err;
6433 }
6442 pci_restore_state(pci_dev); 6434 pci_restore_state(pci_dev);
6443 6435
6444 /* 6436 /*
@@ -7573,11 +7565,10 @@ static int ipw2100_wx_set_genie(struct net_device *dev,
7573 return -EINVAL; 7565 return -EINVAL;
7574 7566
7575 if (wrqu->data.length) { 7567 if (wrqu->data.length) {
7576 buf = kmalloc(wrqu->data.length, GFP_KERNEL); 7568 buf = kmemdup(extra, wrqu->data.length, GFP_KERNEL);
7577 if (buf == NULL) 7569 if (buf == NULL)
7578 return -ENOMEM; 7570 return -ENOMEM;
7579 7571
7580 memcpy(buf, extra, wrqu->data.length);
7581 kfree(ieee->wpa_ie); 7572 kfree(ieee->wpa_ie);
7582 ieee->wpa_ie = buf; 7573 ieee->wpa_ie = buf;
7583 ieee->wpa_ie_len = wrqu->data.length; 7574 ieee->wpa_ie_len = wrqu->data.length;
diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c
index 587a0918fa52..e82e56bb85e1 100644
--- a/drivers/net/wireless/ipw2200.c
+++ b/drivers/net/wireless/ipw2200.c
@@ -6938,8 +6938,8 @@ static int ipw_qos_association(struct ipw_priv *priv,
6938} 6938}
6939 6939
6940/* 6940/*
6941* handling the beaconing responces. if we get different QoS setting 6941* handling the beaconing responses. if we get different QoS setting
6942* of the network from the the associated setting adjust the QoS 6942* off the network from the associated setting, adjust the QoS
6943* setting 6943* setting
6944*/ 6944*/
6945static int ipw_qos_association_resp(struct ipw_priv *priv, 6945static int ipw_qos_association_resp(struct ipw_priv *priv,
@@ -11746,12 +11746,18 @@ static int ipw_pci_resume(struct pci_dev *pdev)
11746{ 11746{
11747 struct ipw_priv *priv = pci_get_drvdata(pdev); 11747 struct ipw_priv *priv = pci_get_drvdata(pdev);
11748 struct net_device *dev = priv->net_dev; 11748 struct net_device *dev = priv->net_dev;
11749 int err;
11749 u32 val; 11750 u32 val;
11750 11751
11751 printk(KERN_INFO "%s: Coming out of suspend...\n", dev->name); 11752 printk(KERN_INFO "%s: Coming out of suspend...\n", dev->name);
11752 11753
11753 pci_set_power_state(pdev, PCI_D0); 11754 pci_set_power_state(pdev, PCI_D0);
11754 pci_enable_device(pdev); 11755 err = pci_enable_device(pdev);
11756 if (err) {
11757 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
11758 dev->name);
11759 return err;
11760 }
11755 pci_restore_state(pdev); 11761 pci_restore_state(pdev);
11756 11762
11757 /* 11763 /*
diff --git a/drivers/net/wireless/orinoco_pci.h b/drivers/net/wireless/orinoco_pci.h
index be1abea4b64f..f4e5e06760c1 100644
--- a/drivers/net/wireless/orinoco_pci.h
+++ b/drivers/net/wireless/orinoco_pci.h
@@ -60,7 +60,12 @@ static int orinoco_pci_resume(struct pci_dev *pdev)
60 int err; 60 int err;
61 61
62 pci_set_power_state(pdev, 0); 62 pci_set_power_state(pdev, 0);
63 pci_enable_device(pdev); 63 err = pci_enable_device(pdev);
64 if (err) {
65 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
66 dev->name);
67 return err;
68 }
64 pci_restore_state(pdev); 69 pci_restore_state(pdev);
65 70
66 err = request_irq(pdev->irq, orinoco_interrupt, IRQF_SHARED, 71 err = request_irq(pdev->irq, orinoco_interrupt, IRQF_SHARED,
diff --git a/drivers/net/wireless/prism54/isl_38xx.c b/drivers/net/wireless/prism54/isl_38xx.c
index 23deee69974b..02fc67bccbd0 100644
--- a/drivers/net/wireless/prism54/isl_38xx.c
+++ b/drivers/net/wireless/prism54/isl_38xx.c
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright (C) 2003-2004 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>_ 3 * Copyright (C) 2003-2004 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>_
5 * 4 *
@@ -38,7 +37,7 @@
38 * isl38xx_disable_interrupts - disable all interrupts 37 * isl38xx_disable_interrupts - disable all interrupts
39 * @device: pci memory base address 38 * @device: pci memory base address
40 * 39 *
41 * Instructs the device to disable all interrupt reporting by asserting 40 * Instructs the device to disable all interrupt reporting by asserting
42 * the IRQ line. New events may still show up in the interrupt identification 41 * the IRQ line. New events may still show up in the interrupt identification
43 * register located at offset %ISL38XX_INT_IDENT_REG. 42 * register located at offset %ISL38XX_INT_IDENT_REG.
44 */ 43 */
@@ -204,17 +203,19 @@ isl38xx_interface_reset(void __iomem *device_base, dma_addr_t host_address)
204 /* enable the interrupt for detecting initialization */ 203 /* enable the interrupt for detecting initialization */
205 204
206 /* Note: Do not enable other interrupts here. We want the 205 /* Note: Do not enable other interrupts here. We want the
207 * device to have come up first 100% before allowing any other 206 * device to have come up first 100% before allowing any other
208 * interrupts. */ 207 * interrupts. */
209 isl38xx_w32_flush(device_base, ISL38XX_INT_IDENT_INIT, ISL38XX_INT_EN_REG); 208 isl38xx_w32_flush(device_base, ISL38XX_INT_IDENT_INIT, ISL38XX_INT_EN_REG);
210 udelay(ISL38XX_WRITEIO_DELAY); /* allow complete full reset */ 209 udelay(ISL38XX_WRITEIO_DELAY); /* allow complete full reset */
211} 210}
212 211
213void 212void
214isl38xx_enable_common_interrupts(void __iomem *device_base) { 213isl38xx_enable_common_interrupts(void __iomem *device_base)
214{
215 u32 reg; 215 u32 reg;
216 reg = ( ISL38XX_INT_IDENT_UPDATE | 216
217 ISL38XX_INT_IDENT_SLEEP | ISL38XX_INT_IDENT_WAKEUP); 217 reg = ISL38XX_INT_IDENT_UPDATE | ISL38XX_INT_IDENT_SLEEP |
218 ISL38XX_INT_IDENT_WAKEUP;
218 isl38xx_w32_flush(device_base, reg, ISL38XX_INT_EN_REG); 219 isl38xx_w32_flush(device_base, reg, ISL38XX_INT_EN_REG);
219 udelay(ISL38XX_WRITEIO_DELAY); 220 udelay(ISL38XX_WRITEIO_DELAY);
220} 221}
@@ -234,23 +235,21 @@ isl38xx_in_queue(isl38xx_control_block *cb, int queue)
234 /* send queues */ 235 /* send queues */
235 case ISL38XX_CB_TX_MGMTQ: 236 case ISL38XX_CB_TX_MGMTQ:
236 BUG_ON(delta > ISL38XX_CB_MGMT_QSIZE); 237 BUG_ON(delta > ISL38XX_CB_MGMT_QSIZE);
238
237 case ISL38XX_CB_TX_DATA_LQ: 239 case ISL38XX_CB_TX_DATA_LQ:
238 case ISL38XX_CB_TX_DATA_HQ: 240 case ISL38XX_CB_TX_DATA_HQ:
239 BUG_ON(delta > ISL38XX_CB_TX_QSIZE); 241 BUG_ON(delta > ISL38XX_CB_TX_QSIZE);
240 return delta; 242 return delta;
241 break;
242 243
243 /* receive queues */ 244 /* receive queues */
244 case ISL38XX_CB_RX_MGMTQ: 245 case ISL38XX_CB_RX_MGMTQ:
245 BUG_ON(delta > ISL38XX_CB_MGMT_QSIZE); 246 BUG_ON(delta > ISL38XX_CB_MGMT_QSIZE);
246 return ISL38XX_CB_MGMT_QSIZE - delta; 247 return ISL38XX_CB_MGMT_QSIZE - delta;
247 break;
248 248
249 case ISL38XX_CB_RX_DATA_LQ: 249 case ISL38XX_CB_RX_DATA_LQ:
250 case ISL38XX_CB_RX_DATA_HQ: 250 case ISL38XX_CB_RX_DATA_HQ:
251 BUG_ON(delta > ISL38XX_CB_RX_QSIZE); 251 BUG_ON(delta > ISL38XX_CB_RX_QSIZE);
252 return ISL38XX_CB_RX_QSIZE - delta; 252 return ISL38XX_CB_RX_QSIZE - delta;
253 break;
254 } 253 }
255 BUG(); 254 BUG();
256 return 0; 255 return 0;
diff --git a/drivers/net/wireless/prism54/isl_38xx.h b/drivers/net/wireless/prism54/isl_38xx.h
index 8af20980af8d..3fadcb6f5297 100644
--- a/drivers/net/wireless/prism54/isl_38xx.h
+++ b/drivers/net/wireless/prism54/isl_38xx.h
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
@@ -67,10 +66,10 @@
67 * @base: (host) memory base address of the device 66 * @base: (host) memory base address of the device
68 * @val: 32bit value (host order) to write 67 * @val: 32bit value (host order) to write
69 * @offset: byte offset into @base to write value to 68 * @offset: byte offset into @base to write value to
70 * 69 *
71 * This helper takes care of writing a 32bit datum to the 70 * This helper takes care of writing a 32bit datum to the
72 * specified offset into the device's pci memory space, and making sure 71 * specified offset into the device's pci memory space, and making sure
73 * the pci memory buffers get flushed by performing one harmless read 72 * the pci memory buffers get flushed by performing one harmless read
74 * from the %ISL38XX_PCI_POSTING_FLUSH offset. 73 * from the %ISL38XX_PCI_POSTING_FLUSH offset.
75 */ 74 */
76static inline void 75static inline void
diff --git a/drivers/net/wireless/prism54/isl_ioctl.c b/drivers/net/wireless/prism54/isl_ioctl.c
index e7700b4257eb..a87eb51886c8 100644
--- a/drivers/net/wireless/prism54/isl_ioctl.c
+++ b/drivers/net/wireless/prism54/isl_ioctl.c
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * (C) 2003,2004 Aurelien Alleaume <slts@free.fr> 3 * (C) 2003,2004 Aurelien Alleaume <slts@free.fr>
5 * (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> 4 * (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
@@ -55,12 +54,12 @@ static const unsigned char scan_rate_list[] = { 2, 4, 11, 22,
55 * prism54_mib_mode_helper - MIB change mode helper function 54 * prism54_mib_mode_helper - MIB change mode helper function
56 * @mib: the &struct islpci_mib object to modify 55 * @mib: the &struct islpci_mib object to modify
57 * @iw_mode: new mode (%IW_MODE_*) 56 * @iw_mode: new mode (%IW_MODE_*)
58 * 57 *
59 * This is a helper function, hence it does not lock. Make sure 58 * This is a helper function, hence it does not lock. Make sure
60 * caller deals with locking *if* necessary. This function sets the 59 * caller deals with locking *if* necessary. This function sets the
61 * mode-dependent mib values and does the mapping of the Linux 60 * mode-dependent mib values and does the mapping of the Linux
62 * Wireless API modes to Device firmware modes. It also checks for 61 * Wireless API modes to Device firmware modes. It also checks for
63 * correct valid Linux wireless modes. 62 * correct valid Linux wireless modes.
64 */ 63 */
65static int 64static int
66prism54_mib_mode_helper(islpci_private *priv, u32 iw_mode) 65prism54_mib_mode_helper(islpci_private *priv, u32 iw_mode)
@@ -118,7 +117,7 @@ prism54_mib_mode_helper(islpci_private *priv, u32 iw_mode)
118 * 117 *
119 * this function initializes the struct given as @mib with defaults, 118 * this function initializes the struct given as @mib with defaults,
120 * of which many are retrieved from the global module parameter 119 * of which many are retrieved from the global module parameter
121 * variables. 120 * variables.
122 */ 121 */
123 122
124void 123void
@@ -134,7 +133,7 @@ prism54_mib_init(islpci_private *priv)
134 authen = CARD_DEFAULT_AUTHEN; 133 authen = CARD_DEFAULT_AUTHEN;
135 wep = CARD_DEFAULT_WEP; 134 wep = CARD_DEFAULT_WEP;
136 filter = CARD_DEFAULT_FILTER; /* (0) Do not filter un-encrypted data */ 135 filter = CARD_DEFAULT_FILTER; /* (0) Do not filter un-encrypted data */
137 dot1x = CARD_DEFAULT_DOT1X; 136 dot1x = CARD_DEFAULT_DOT1X;
138 mlme = CARD_DEFAULT_MLME_MODE; 137 mlme = CARD_DEFAULT_MLME_MODE;
139 conformance = CARD_DEFAULT_CONFORMANCE; 138 conformance = CARD_DEFAULT_CONFORMANCE;
140 power = 127; 139 power = 127;
@@ -229,7 +228,7 @@ prism54_get_wireless_stats(struct net_device *ndev)
229 } else 228 } else
230 priv->iwstatistics.qual.updated = 0; 229 priv->iwstatistics.qual.updated = 0;
231 230
232 /* Update our wireless stats, but do not schedule to often 231 /* Update our wireless stats, but do not schedule to often
233 * (max 1 HZ) */ 232 * (max 1 HZ) */
234 if ((priv->stats_timestamp == 0) || 233 if ((priv->stats_timestamp == 0) ||
235 time_after(jiffies, priv->stats_timestamp + 1 * HZ)) { 234 time_after(jiffies, priv->stats_timestamp + 1 * HZ)) {
@@ -706,7 +705,7 @@ prism54_get_scan(struct net_device *ndev, struct iw_request_info *info,
706 * Starting with WE-17, the buffer can be as big as needed. 705 * Starting with WE-17, the buffer can be as big as needed.
707 * But the device won't repport anything if you change the value 706 * But the device won't repport anything if you change the value
708 * of IWMAX_BSS=24. */ 707 * of IWMAX_BSS=24. */
709 708
710 rvalue |= mgt_get_request(priv, DOT11_OID_BSSLIST, 0, NULL, &r); 709 rvalue |= mgt_get_request(priv, DOT11_OID_BSSLIST, 0, NULL, &r);
711 bsslist = r.ptr; 710 bsslist = r.ptr;
712 711
@@ -786,7 +785,7 @@ prism54_get_essid(struct net_device *ndev, struct iw_request_info *info,
786 return rvalue; 785 return rvalue;
787} 786}
788 787
789/* Provides no functionality, just completes the ioctl. In essence this is a 788/* Provides no functionality, just completes the ioctl. In essence this is a
790 * just a cosmetic ioctl. 789 * just a cosmetic ioctl.
791 */ 790 */
792static int 791static int
@@ -1105,7 +1104,7 @@ prism54_set_encode(struct net_device *ndev, struct iw_request_info *info,
1105 &key); 1104 &key);
1106 } 1105 }
1107 /* 1106 /*
1108 * If a valid key is set, encryption should be enabled 1107 * If a valid key is set, encryption should be enabled
1109 * (user may turn it off later). 1108 * (user may turn it off later).
1110 * This is also how "iwconfig ethX key on" works 1109 * This is also how "iwconfig ethX key on" works
1111 */ 1110 */
@@ -1127,7 +1126,7 @@ prism54_set_encode(struct net_device *ndev, struct iw_request_info *info,
1127 } 1126 }
1128 /* now read the flags */ 1127 /* now read the flags */
1129 if (dwrq->flags & IW_ENCODE_DISABLED) { 1128 if (dwrq->flags & IW_ENCODE_DISABLED) {
1130 /* Encoding disabled, 1129 /* Encoding disabled,
1131 * authen = DOT11_AUTH_OS; 1130 * authen = DOT11_AUTH_OS;
1132 * invoke = 0; 1131 * invoke = 0;
1133 * exunencrypt = 0; */ 1132 * exunencrypt = 0; */
@@ -1215,7 +1214,7 @@ prism54_get_txpower(struct net_device *ndev, struct iw_request_info *info,
1215 vwrq->value = (s32) r.u / 4; 1214 vwrq->value = (s32) r.u / 4;
1216 vwrq->fixed = 1; 1215 vwrq->fixed = 1;
1217 /* radio is not turned of 1216 /* radio is not turned of
1218 * btw: how is possible to turn off only the radio 1217 * btw: how is possible to turn off only the radio
1219 */ 1218 */
1220 vwrq->disabled = 0; 1219 vwrq->disabled = 0;
1221 1220
@@ -2355,17 +2354,17 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
2355 handle_request(priv, mlme, oid); 2354 handle_request(priv, mlme, oid);
2356 send_formatted_event(priv, "Authenticate request (ex)", mlme, 1); 2355 send_formatted_event(priv, "Authenticate request (ex)", mlme, 1);
2357 2356
2358 if (priv->iw_mode != IW_MODE_MASTER 2357 if (priv->iw_mode != IW_MODE_MASTER
2359 && mlmeex->state != DOT11_STATE_AUTHING) 2358 && mlmeex->state != DOT11_STATE_AUTHING)
2360 break; 2359 break;
2361 2360
2362 confirm = kmalloc(sizeof(struct obj_mlmeex) + 6, GFP_ATOMIC); 2361 confirm = kmalloc(sizeof(struct obj_mlmeex) + 6, GFP_ATOMIC);
2363 2362
2364 if (!confirm) 2363 if (!confirm)
2365 break; 2364 break;
2366 2365
2367 memcpy(&confirm->address, mlmeex->address, ETH_ALEN); 2366 memcpy(&confirm->address, mlmeex->address, ETH_ALEN);
2368 printk(KERN_DEBUG "Authenticate from: address:\t%02x:%02x:%02x:%02x:%02x:%02x\n", 2367 printk(KERN_DEBUG "Authenticate from: address:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
2369 mlmeex->address[0], 2368 mlmeex->address[0],
2370 mlmeex->address[1], 2369 mlmeex->address[1],
2371 mlmeex->address[2], 2370 mlmeex->address[2],
@@ -2399,10 +2398,10 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
2399 handle_request(priv, mlme, oid); 2398 handle_request(priv, mlme, oid);
2400 send_formatted_event(priv, "Associate request (ex)", mlme, 1); 2399 send_formatted_event(priv, "Associate request (ex)", mlme, 1);
2401 2400
2402 if (priv->iw_mode != IW_MODE_MASTER 2401 if (priv->iw_mode != IW_MODE_MASTER
2403 && mlmeex->state != DOT11_STATE_ASSOCING) 2402 && mlmeex->state != DOT11_STATE_ASSOCING)
2404 break; 2403 break;
2405 2404
2406 confirm = kmalloc(sizeof(struct obj_mlmeex), GFP_ATOMIC); 2405 confirm = kmalloc(sizeof(struct obj_mlmeex), GFP_ATOMIC);
2407 2406
2408 if (!confirm) 2407 if (!confirm)
@@ -2418,7 +2417,7 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
2418 2417
2419 if (!wpa_ie_len) { 2418 if (!wpa_ie_len) {
2420 printk(KERN_DEBUG "No WPA IE found from " 2419 printk(KERN_DEBUG "No WPA IE found from "
2421 "address:\t%02x:%02x:%02x:%02x:%02x:%02x\n", 2420 "address:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
2422 mlmeex->address[0], 2421 mlmeex->address[0],
2423 mlmeex->address[1], 2422 mlmeex->address[1],
2424 mlmeex->address[2], 2423 mlmeex->address[2],
@@ -2436,14 +2435,14 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
2436 mgt_set_varlen(priv, oid, confirm, wpa_ie_len); 2435 mgt_set_varlen(priv, oid, confirm, wpa_ie_len);
2437 2436
2438 kfree(confirm); 2437 kfree(confirm);
2439 2438
2440 break; 2439 break;
2441 2440
2442 case DOT11_OID_REASSOCIATEEX: 2441 case DOT11_OID_REASSOCIATEEX:
2443 handle_request(priv, mlme, oid); 2442 handle_request(priv, mlme, oid);
2444 send_formatted_event(priv, "Reassociate request (ex)", mlme, 1); 2443 send_formatted_event(priv, "Reassociate request (ex)", mlme, 1);
2445 2444
2446 if (priv->iw_mode != IW_MODE_MASTER 2445 if (priv->iw_mode != IW_MODE_MASTER
2447 && mlmeex->state != DOT11_STATE_ASSOCING) 2446 && mlmeex->state != DOT11_STATE_ASSOCING)
2448 break; 2447 break;
2449 2448
@@ -2462,7 +2461,7 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
2462 2461
2463 if (!wpa_ie_len) { 2462 if (!wpa_ie_len) {
2464 printk(KERN_DEBUG "No WPA IE found from " 2463 printk(KERN_DEBUG "No WPA IE found from "
2465 "address:\t%02x:%02x:%02x:%02x:%02x:%02x\n", 2464 "address:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
2466 mlmeex->address[0], 2465 mlmeex->address[0],
2467 mlmeex->address[1], 2466 mlmeex->address[1],
2468 mlmeex->address[2], 2467 mlmeex->address[2],
@@ -2474,13 +2473,13 @@ prism54_process_trap_helper(islpci_private *priv, enum oid_num_t oid,
2474 break; 2473 break;
2475 } 2474 }
2476 2475
2477 confirm->size = wpa_ie_len; 2476 confirm->size = wpa_ie_len;
2478 memcpy(&confirm->data, wpa_ie, wpa_ie_len); 2477 memcpy(&confirm->data, wpa_ie, wpa_ie_len);
2479 2478
2480 mgt_set_varlen(priv, oid, confirm, wpa_ie_len); 2479 mgt_set_varlen(priv, oid, confirm, wpa_ie_len);
2481 2480
2482 kfree(confirm); 2481 kfree(confirm);
2483 2482
2484 break; 2483 break;
2485 2484
2486 default: 2485 default:
@@ -2547,10 +2546,10 @@ enum {
2547#define PRISM2_HOSTAPD_GENERIC_ELEMENT_HDR_LEN \ 2546#define PRISM2_HOSTAPD_GENERIC_ELEMENT_HDR_LEN \
2548((int) (&((struct prism2_hostapd_param *) 0)->u.generic_elem.data)) 2547((int) (&((struct prism2_hostapd_param *) 0)->u.generic_elem.data))
2549 2548
2550/* Maximum length for algorithm names (-1 for nul termination) 2549/* Maximum length for algorithm names (-1 for nul termination)
2551 * used in ioctl() */ 2550 * used in ioctl() */
2552#define HOSTAP_CRYPT_ALG_NAME_LEN 16 2551#define HOSTAP_CRYPT_ALG_NAME_LEN 16
2553 2552
2554struct prism2_hostapd_param { 2553struct prism2_hostapd_param {
2555 u32 cmd; 2554 u32 cmd;
2556 u8 sta_addr[ETH_ALEN]; 2555 u8 sta_addr[ETH_ALEN];
@@ -2623,7 +2622,7 @@ prism2_ioctl_set_encryption(struct net_device *dev,
2623 &key); 2622 &key);
2624 } 2623 }
2625 /* 2624 /*
2626 * If a valid key is set, encryption should be enabled 2625 * If a valid key is set, encryption should be enabled
2627 * (user may turn it off later). 2626 * (user may turn it off later).
2628 * This is also how "iwconfig ethX key on" works 2627 * This is also how "iwconfig ethX key on" works
2629 */ 2628 */
@@ -2645,7 +2644,7 @@ prism2_ioctl_set_encryption(struct net_device *dev,
2645 } 2644 }
2646 /* now read the flags */ 2645 /* now read the flags */
2647 if (param->u.crypt.flags & IW_ENCODE_DISABLED) { 2646 if (param->u.crypt.flags & IW_ENCODE_DISABLED) {
2648 /* Encoding disabled, 2647 /* Encoding disabled,
2649 * authen = DOT11_AUTH_OS; 2648 * authen = DOT11_AUTH_OS;
2650 * invoke = 0; 2649 * invoke = 0;
2651 * exunencrypt = 0; */ 2650 * exunencrypt = 0; */
@@ -2712,7 +2711,7 @@ prism2_ioctl_set_generic_element(struct net_device *ndev,
2712 2711
2713 ret = mgt_set_varlen(priv, DOT11_OID_ATTACHMENT, attach, len); 2712 ret = mgt_set_varlen(priv, DOT11_OID_ATTACHMENT, attach, len);
2714 2713
2715 if (ret == 0) 2714 if (ret == 0)
2716 printk(KERN_DEBUG "%s: WPA IE Attachment was set\n", 2715 printk(KERN_DEBUG "%s: WPA IE Attachment was set\n",
2717 ndev->name); 2716 ndev->name);
2718 } 2717 }
@@ -2872,7 +2871,7 @@ prism54_set_wpa(struct net_device *ndev, struct iw_request_info *info,
2872 mlme = DOT11_MLME_AUTO; 2871 mlme = DOT11_MLME_AUTO;
2873 printk("%s: Disabling WPA\n", ndev->name); 2872 printk("%s: Disabling WPA\n", ndev->name);
2874 break; 2873 break;
2875 case 2: 2874 case 2:
2876 case 1: /* WPA */ 2875 case 1: /* WPA */
2877 printk("%s: Enabling WPA\n", ndev->name); 2876 printk("%s: Enabling WPA\n", ndev->name);
2878 break; 2877 break;
diff --git a/drivers/net/wireless/prism54/isl_ioctl.h b/drivers/net/wireless/prism54/isl_ioctl.h
index 0802fa64996f..bcfbfb9281d2 100644
--- a/drivers/net/wireless/prism54/isl_ioctl.h
+++ b/drivers/net/wireless/prism54/isl_ioctl.h
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * (C) 2003 Aurelien Alleaume <slts@free.fr> 3 * (C) 2003 Aurelien Alleaume <slts@free.fr>
5 * (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> 4 * (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
diff --git a/drivers/net/wireless/prism54/isl_oid.h b/drivers/net/wireless/prism54/isl_oid.h
index 419edf7ccf1a..b7534c2869c8 100644
--- a/drivers/net/wireless/prism54/isl_oid.h
+++ b/drivers/net/wireless/prism54/isl_oid.h
@@ -1,6 +1,4 @@
1/* 1/*
2 *
3 *
4 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> 2 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
5 * Copyright (C) 2004 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> 3 * Copyright (C) 2004 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
6 * Copyright (C) 2004 Aurelien Alleaume <slts@free.fr> 4 * Copyright (C) 2004 Aurelien Alleaume <slts@free.fr>
@@ -23,7 +21,7 @@
23#if !defined(_ISL_OID_H) 21#if !defined(_ISL_OID_H)
24#define _ISL_OID_H 22#define _ISL_OID_H
25 23
26/* 24/*
27 * MIB related constant and structure definitions for communicating 25 * MIB related constant and structure definitions for communicating
28 * with the device firmware 26 * with the device firmware
29 */ 27 */
@@ -99,21 +97,21 @@ struct obj_attachment {
99 char data[0]; 97 char data[0];
100} __attribute__((packed)); 98} __attribute__((packed));
101 99
102/* 100/*
103 * in case everything's ok, the inlined function below will be 101 * in case everything's ok, the inlined function below will be
104 * optimized away by the compiler... 102 * optimized away by the compiler...
105 */ 103 */
106static inline void 104static inline void
107__bug_on_wrong_struct_sizes(void) 105__bug_on_wrong_struct_sizes(void)
108{ 106{
109 BUG_ON(sizeof (struct obj_ssid) != 34); 107 BUILD_BUG_ON(sizeof (struct obj_ssid) != 34);
110 BUG_ON(sizeof (struct obj_key) != 34); 108 BUILD_BUG_ON(sizeof (struct obj_key) != 34);
111 BUG_ON(sizeof (struct obj_mlme) != 12); 109 BUILD_BUG_ON(sizeof (struct obj_mlme) != 12);
112 BUG_ON(sizeof (struct obj_mlmeex) != 14); 110 BUILD_BUG_ON(sizeof (struct obj_mlmeex) != 14);
113 BUG_ON(sizeof (struct obj_buffer) != 8); 111 BUILD_BUG_ON(sizeof (struct obj_buffer) != 8);
114 BUG_ON(sizeof (struct obj_bss) != 60); 112 BUILD_BUG_ON(sizeof (struct obj_bss) != 60);
115 BUG_ON(sizeof (struct obj_bsslist) != 4); 113 BUILD_BUG_ON(sizeof (struct obj_bsslist) != 4);
116 BUG_ON(sizeof (struct obj_frequencies) != 2); 114 BUILD_BUG_ON(sizeof (struct obj_frequencies) != 2);
117} 115}
118 116
119enum dot11_state_t { 117enum dot11_state_t {
@@ -154,13 +152,13 @@ enum dot11_priv_t {
154 152
155/* Prism "Nitro" / Frameburst / "Packet Frame Grouping" 153/* Prism "Nitro" / Frameburst / "Packet Frame Grouping"
156 * Value is in microseconds. Represents the # microseconds 154 * Value is in microseconds. Represents the # microseconds
157 * the firmware will take to group frames before sending out then out 155 * the firmware will take to group frames before sending out then out
158 * together with a CSMA contention. Without this all frames are 156 * together with a CSMA contention. Without this all frames are
159 * sent with a CSMA contention. 157 * sent with a CSMA contention.
160 * Bibliography: 158 * Bibliography:
161 * http://www.hpl.hp.com/personal/Jean_Tourrilhes/Papers/Packet.Frame.Grouping.html 159 * http://www.hpl.hp.com/personal/Jean_Tourrilhes/Papers/Packet.Frame.Grouping.html
162 */ 160 */
163enum dot11_maxframeburst_t { 161enum dot11_maxframeburst_t {
164 /* Values for DOT11_OID_MAXFRAMEBURST */ 162 /* Values for DOT11_OID_MAXFRAMEBURST */
165 DOT11_MAXFRAMEBURST_OFF = 0, /* Card firmware default */ 163 DOT11_MAXFRAMEBURST_OFF = 0, /* Card firmware default */
166 DOT11_MAXFRAMEBURST_MIXED_SAFE = 650, /* 802.11 a,b,g safe */ 164 DOT11_MAXFRAMEBURST_MIXED_SAFE = 650, /* 802.11 a,b,g safe */
@@ -176,9 +174,9 @@ enum dot11_maxframeburst_t {
176/* Support for 802.11 long and short frame preambles. 174/* Support for 802.11 long and short frame preambles.
177 * Long preamble uses 128-bit sync field, 8-bit CRC 175 * Long preamble uses 128-bit sync field, 8-bit CRC
178 * Short preamble uses 56-bit sync field, 16-bit CRC 176 * Short preamble uses 56-bit sync field, 16-bit CRC
179 * 177 *
180 * 802.11a -- not sure, both optionally ? 178 * 802.11a -- not sure, both optionally ?
181 * 802.11b supports long and optionally short 179 * 802.11b supports long and optionally short
182 * 802.11g supports both */ 180 * 802.11g supports both */
183enum dot11_preamblesettings_t { 181enum dot11_preamblesettings_t {
184 DOT11_PREAMBLESETTING_LONG = 0, 182 DOT11_PREAMBLESETTING_LONG = 0,
@@ -194,7 +192,7 @@ enum dot11_preamblesettings_t {
194 * Long uses 802.11a slot timing (9 usec ?) 192 * Long uses 802.11a slot timing (9 usec ?)
195 * Short uses 802.11b slot timing (20 use ?) */ 193 * Short uses 802.11b slot timing (20 use ?) */
196enum dot11_slotsettings_t { 194enum dot11_slotsettings_t {
197 DOT11_SLOTSETTINGS_LONG = 0, 195 DOT11_SLOTSETTINGS_LONG = 0,
198 /* Allows *only* long 802.11b slot timing */ 196 /* Allows *only* long 802.11b slot timing */
199 DOT11_SLOTSETTINGS_SHORT = 1, 197 DOT11_SLOTSETTINGS_SHORT = 1,
200 /* Allows *only* long 802.11a slot timing */ 198 /* Allows *only* long 802.11a slot timing */
@@ -203,7 +201,7 @@ enum dot11_slotsettings_t {
203}; 201};
204 202
205/* All you need to know, ERP is "Extended Rate PHY". 203/* All you need to know, ERP is "Extended Rate PHY".
206 * An Extended Rate PHY (ERP) STA or AP shall support three different 204 * An Extended Rate PHY (ERP) STA or AP shall support three different
207 * preamble and header formats: 205 * preamble and header formats:
208 * Long preamble (refer to above) 206 * Long preamble (refer to above)
209 * Short preamble (refer to above) 207 * Short preamble (refer to above)
@@ -221,7 +219,7 @@ enum do11_nonerpstatus_t {
221/* (ERP is "Extended Rate PHY") Way to read NONERP is NON-ERP-* 219/* (ERP is "Extended Rate PHY") Way to read NONERP is NON-ERP-*
222 * The key here is DOT11 NON ERP NEVER protects against 220 * The key here is DOT11 NON ERP NEVER protects against
223 * NON ERP STA's. You *don't* want this unless 221 * NON ERP STA's. You *don't* want this unless
224 * you know what you are doing. It means you will only 222 * you know what you are doing. It means you will only
225 * get Extended Rate capabilities */ 223 * get Extended Rate capabilities */
226enum dot11_nonerpprotection_t { 224enum dot11_nonerpprotection_t {
227 DOT11_NONERP_NEVER = 0, 225 DOT11_NONERP_NEVER = 0,
@@ -229,13 +227,13 @@ enum dot11_nonerpprotection_t {
229 DOT11_NONERP_DYNAMIC = 2 227 DOT11_NONERP_DYNAMIC = 2
230}; 228};
231 229
232/* Preset OID configuration for 802.11 modes 230/* Preset OID configuration for 802.11 modes
233 * Note: DOT11_OID_CW[MIN|MAX] hold the values of the 231 * Note: DOT11_OID_CW[MIN|MAX] hold the values of the
234 * DCS MIN|MAX backoff used */ 232 * DCS MIN|MAX backoff used */
235enum dot11_profile_t { /* And set/allowed values */ 233enum dot11_profile_t { /* And set/allowed values */
236 /* Allowed values for DOT11_OID_PROFILES */ 234 /* Allowed values for DOT11_OID_PROFILES */
237 DOT11_PROFILE_B_ONLY = 0, 235 DOT11_PROFILE_B_ONLY = 0,
238 /* DOT11_OID_RATES: 1, 2, 5.5, 11Mbps 236 /* DOT11_OID_RATES: 1, 2, 5.5, 11Mbps
239 * DOT11_OID_PREAMBLESETTINGS: DOT11_PREAMBLESETTING_DYNAMIC 237 * DOT11_OID_PREAMBLESETTINGS: DOT11_PREAMBLESETTING_DYNAMIC
240 * DOT11_OID_CWMIN: 31 238 * DOT11_OID_CWMIN: 31
241 * DOT11_OID_NONEPROTECTION: DOT11_NOERP_DYNAMIC 239 * DOT11_OID_NONEPROTECTION: DOT11_NOERP_DYNAMIC
@@ -275,7 +273,7 @@ enum oid_inl_conformance_t {
275 OID_INL_CONFORMANCE_NONE = 0, /* Perform active scanning */ 273 OID_INL_CONFORMANCE_NONE = 0, /* Perform active scanning */
276 OID_INL_CONFORMANCE_STRICT = 1, /* Strictly adhere to 802.11d */ 274 OID_INL_CONFORMANCE_STRICT = 1, /* Strictly adhere to 802.11d */
277 OID_INL_CONFORMANCE_FLEXIBLE = 2, /* Use passed 802.11d info to 275 OID_INL_CONFORMANCE_FLEXIBLE = 2, /* Use passed 802.11d info to
278 * determine channel AND/OR just make assumption that active 276 * determine channel AND/OR just make assumption that active
279 * channels are valid channels */ 277 * channels are valid channels */
280}; 278};
281 279
diff --git a/drivers/net/wireless/prism54/islpci_dev.c b/drivers/net/wireless/prism54/islpci_dev.c
index e35fcb2543c4..f057fd9fcd79 100644
--- a/drivers/net/wireless/prism54/islpci_dev.c
+++ b/drivers/net/wireless/prism54/islpci_dev.c
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> 3 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
5 * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> 4 * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
@@ -413,7 +412,7 @@ prism54_bring_down(islpci_private *priv)
413 islpci_set_state(priv, PRV_STATE_PREBOOT); 412 islpci_set_state(priv, PRV_STATE_PREBOOT);
414 413
415 /* disable all device interrupts in case they weren't */ 414 /* disable all device interrupts in case they weren't */
416 isl38xx_disable_interrupts(priv->device_base); 415 isl38xx_disable_interrupts(priv->device_base);
417 416
418 /* For safety reasons, we may want to ensure that no DMA transfer is 417 /* For safety reasons, we may want to ensure that no DMA transfer is
419 * currently in progress by emptying the TX and RX queues. */ 418 * currently in progress by emptying the TX and RX queues. */
@@ -480,7 +479,7 @@ islpci_reset_if(islpci_private *priv)
480 479
481 DEFINE_WAIT(wait); 480 DEFINE_WAIT(wait);
482 prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE); 481 prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE);
483 482
484 /* now the last step is to reset the interface */ 483 /* now the last step is to reset the interface */
485 isl38xx_interface_reset(priv->device_base, priv->device_host_address); 484 isl38xx_interface_reset(priv->device_base, priv->device_host_address);
486 islpci_set_state(priv, PRV_STATE_PREINIT); 485 islpci_set_state(priv, PRV_STATE_PREINIT);
@@ -488,7 +487,7 @@ islpci_reset_if(islpci_private *priv)
488 for(count = 0; count < 2 && result; count++) { 487 for(count = 0; count < 2 && result; count++) {
489 /* The software reset acknowledge needs about 220 msec here. 488 /* The software reset acknowledge needs about 220 msec here.
490 * Be conservative and wait for up to one second. */ 489 * Be conservative and wait for up to one second. */
491 490
492 remaining = schedule_timeout_uninterruptible(HZ); 491 remaining = schedule_timeout_uninterruptible(HZ);
493 492
494 if(remaining > 0) { 493 if(remaining > 0) {
@@ -496,7 +495,7 @@ islpci_reset_if(islpci_private *priv)
496 break; 495 break;
497 } 496 }
498 497
499 /* If we're here it's because our IRQ hasn't yet gone through. 498 /* If we're here it's because our IRQ hasn't yet gone through.
500 * Retry a bit more... 499 * Retry a bit more...
501 */ 500 */
502 printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n", 501 printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n",
@@ -514,7 +513,7 @@ islpci_reset_if(islpci_private *priv)
514 513
515 /* Now that the device is 100% up, let's allow 514 /* Now that the device is 100% up, let's allow
516 * for the other interrupts -- 515 * for the other interrupts --
517 * NOTE: this is not *yet* true since we've only allowed the 516 * NOTE: this is not *yet* true since we've only allowed the
518 * INIT interrupt on the IRQ line. We can perhaps poll 517 * INIT interrupt on the IRQ line. We can perhaps poll
519 * the IRQ line until we know for sure the reset went through */ 518 * the IRQ line until we know for sure the reset went through */
520 isl38xx_enable_common_interrupts(priv->device_base); 519 isl38xx_enable_common_interrupts(priv->device_base);
@@ -716,7 +715,7 @@ islpci_alloc_memory(islpci_private *priv)
716 715
717 prism54_acl_init(&priv->acl); 716 prism54_acl_init(&priv->acl);
718 prism54_wpa_bss_ie_init(priv); 717 prism54_wpa_bss_ie_init(priv);
719 if (mgt_init(priv)) 718 if (mgt_init(priv))
720 goto out_free; 719 goto out_free;
721 720
722 return 0; 721 return 0;
diff --git a/drivers/net/wireless/prism54/islpci_dev.h b/drivers/net/wireless/prism54/islpci_dev.h
index 2f7e525d0cf6..a9aa1662eaa4 100644
--- a/drivers/net/wireless/prism54/islpci_dev.h
+++ b/drivers/net/wireless/prism54/islpci_dev.h
@@ -1,6 +1,5 @@
1/* 1/*
2 * 2 * Copyright (C) 2002 Intersil Americas Inc.
3 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> 3 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
5 * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> 4 * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
6 * Copyright (C) 2003 Aurelien Alleaume <slts@free.fr> 5 * Copyright (C) 2003 Aurelien Alleaume <slts@free.fr>
@@ -72,12 +71,12 @@ struct islpci_bss_wpa_ie {
72 u8 bssid[ETH_ALEN]; 71 u8 bssid[ETH_ALEN];
73 u8 wpa_ie[MAX_WPA_IE_LEN]; 72 u8 wpa_ie[MAX_WPA_IE_LEN];
74 size_t wpa_ie_len; 73 size_t wpa_ie_len;
75 74
76}; 75};
77 76
78typedef struct { 77typedef struct {
79 spinlock_t slock; /* generic spinlock; */ 78 spinlock_t slock; /* generic spinlock; */
80 79
81 u32 priv_oid; 80 u32 priv_oid;
82 81
83 /* our mib cache */ 82 /* our mib cache */
@@ -85,7 +84,7 @@ typedef struct {
85 struct rw_semaphore mib_sem; 84 struct rw_semaphore mib_sem;
86 void **mib; 85 void **mib;
87 char nickname[IW_ESSID_MAX_SIZE+1]; 86 char nickname[IW_ESSID_MAX_SIZE+1];
88 87
89 /* Take care of the wireless stats */ 88 /* Take care of the wireless stats */
90 struct work_struct stats_work; 89 struct work_struct stats_work;
91 struct semaphore stats_sem; 90 struct semaphore stats_sem;
@@ -120,7 +119,7 @@ typedef struct {
120 struct net_device *ndev; 119 struct net_device *ndev;
121 120
122 /* device queue interface members */ 121 /* device queue interface members */
123 struct isl38xx_cb *control_block; /* device control block 122 struct isl38xx_cb *control_block; /* device control block
124 (== driver_mem_address!) */ 123 (== driver_mem_address!) */
125 124
126 /* Each queue has three indexes: 125 /* Each queue has three indexes:
diff --git a/drivers/net/wireless/prism54/islpci_eth.c b/drivers/net/wireless/prism54/islpci_eth.c
index 103a37877733..b1122912ee2d 100644
--- a/drivers/net/wireless/prism54/islpci_eth.c
+++ b/drivers/net/wireless/prism54/islpci_eth.c
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright (C) 2004 Aurelien Alleaume <slts@free.fr> 3 * Copyright (C) 2004 Aurelien Alleaume <slts@free.fr>
5 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
@@ -48,7 +47,7 @@ islpci_eth_cleanup_transmit(islpci_private *priv,
48 /* read the index of the first fragment to be freed */ 47 /* read the index of the first fragment to be freed */
49 index = priv->free_data_tx % ISL38XX_CB_TX_QSIZE; 48 index = priv->free_data_tx % ISL38XX_CB_TX_QSIZE;
50 49
51 /* check for holes in the arrays caused by multi fragment frames 50 /* check for holes in the arrays caused by multi fragment frames
52 * searching for the last fragment of a frame */ 51 * searching for the last fragment of a frame */
53 if (priv->pci_map_tx_address[index] != (dma_addr_t) NULL) { 52 if (priv->pci_map_tx_address[index] != (dma_addr_t) NULL) {
54 /* entry is the last fragment of a frame 53 /* entry is the last fragment of a frame
@@ -253,6 +252,7 @@ islpci_monitor_rx(islpci_private *priv, struct sk_buff **skb)
253 * header and without the FCS. But there a is a bit that 252 * header and without the FCS. But there a is a bit that
254 * indicates if the packet is corrupted :-) */ 253 * indicates if the packet is corrupted :-) */
255 struct rfmon_header *hdr = (struct rfmon_header *) (*skb)->data; 254 struct rfmon_header *hdr = (struct rfmon_header *) (*skb)->data;
255
256 if (hdr->flags & 0x01) 256 if (hdr->flags & 0x01)
257 /* This one is bad. Drop it ! */ 257 /* This one is bad. Drop it ! */
258 return -1; 258 return -1;
@@ -284,7 +284,7 @@ islpci_monitor_rx(islpci_private *priv, struct sk_buff **skb)
284 (struct avs_80211_1_header *) skb_push(*skb, 284 (struct avs_80211_1_header *) skb_push(*skb,
285 sizeof (struct 285 sizeof (struct
286 avs_80211_1_header)); 286 avs_80211_1_header));
287 287
288 avs->version = cpu_to_be32(P80211CAPTURE_VERSION); 288 avs->version = cpu_to_be32(P80211CAPTURE_VERSION);
289 avs->length = cpu_to_be32(sizeof (struct avs_80211_1_header)); 289 avs->length = cpu_to_be32(sizeof (struct avs_80211_1_header));
290 avs->mactime = cpu_to_be64(le64_to_cpu(clock)); 290 avs->mactime = cpu_to_be64(le64_to_cpu(clock));
@@ -390,7 +390,7 @@ islpci_eth_receive(islpci_private *priv)
390 struct rx_annex_header *annex = 390 struct rx_annex_header *annex =
391 (struct rx_annex_header *) skb->data; 391 (struct rx_annex_header *) skb->data;
392 wstats.level = annex->rfmon.rssi; 392 wstats.level = annex->rfmon.rssi;
393 /* The noise value can be a bit outdated if nobody's 393 /* The noise value can be a bit outdated if nobody's
394 * reading wireless stats... */ 394 * reading wireless stats... */
395 wstats.noise = priv->local_iwstatistics.qual.noise; 395 wstats.noise = priv->local_iwstatistics.qual.noise;
396 wstats.qual = wstats.level - wstats.noise; 396 wstats.qual = wstats.level - wstats.noise;
@@ -464,10 +464,8 @@ islpci_eth_receive(islpci_private *priv)
464 break; 464 break;
465 } 465 }
466 /* update the fragment address */ 466 /* update the fragment address */
467 control_block->rx_data_low[index].address = cpu_to_le32((u32) 467 control_block->rx_data_low[index].address =
468 priv-> 468 cpu_to_le32((u32)priv->pci_map_rx_address[index]);
469 pci_map_rx_address
470 [index]);
471 wmb(); 469 wmb();
472 470
473 /* increment the driver read pointer */ 471 /* increment the driver read pointer */
@@ -485,9 +483,11 @@ void
485islpci_do_reset_and_wake(struct work_struct *work) 483islpci_do_reset_and_wake(struct work_struct *work)
486{ 484{
487 islpci_private *priv = container_of(work, islpci_private, reset_task); 485 islpci_private *priv = container_of(work, islpci_private, reset_task);
486
488 islpci_reset(priv, 1); 487 islpci_reset(priv, 1);
489 netif_wake_queue(priv->ndev);
490 priv->reset_task_pending = 0; 488 priv->reset_task_pending = 0;
489 smp_wmb();
490 netif_wake_queue(priv->ndev);
491} 491}
492 492
493void 493void
@@ -499,12 +499,14 @@ islpci_eth_tx_timeout(struct net_device *ndev)
499 /* increment the transmit error counter */ 499 /* increment the transmit error counter */
500 statistics->tx_errors++; 500 statistics->tx_errors++;
501 501
502 printk(KERN_WARNING "%s: tx_timeout", ndev->name);
503 if (!priv->reset_task_pending) { 502 if (!priv->reset_task_pending) {
504 priv->reset_task_pending = 1; 503 printk(KERN_WARNING
505 printk(", scheduling a reset"); 504 "%s: tx_timeout, scheduling reset", ndev->name);
506 netif_stop_queue(ndev); 505 netif_stop_queue(ndev);
506 priv->reset_task_pending = 1;
507 schedule_work(&priv->reset_task); 507 schedule_work(&priv->reset_task);
508 } else {
509 printk(KERN_WARNING
510 "%s: tx_timeout, waiting for reset", ndev->name);
508 } 511 }
509 printk("\n");
510} 512}
diff --git a/drivers/net/wireless/prism54/islpci_eth.h b/drivers/net/wireless/prism54/islpci_eth.h
index 99d37eda9f01..5bf820defbd0 100644
--- a/drivers/net/wireless/prism54/islpci_eth.h
+++ b/drivers/net/wireless/prism54/islpci_eth.h
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/prism54/islpci_hotplug.c b/drivers/net/wireless/prism54/islpci_hotplug.c
index f692dccf0d07..58257b40c043 100644
--- a/drivers/net/wireless/prism54/islpci_hotplug.c
+++ b/drivers/net/wireless/prism54/islpci_hotplug.c
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> 3 * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
5 * 4 *
@@ -40,8 +39,8 @@ static int init_pcitm = 0;
40module_param(init_pcitm, int, 0); 39module_param(init_pcitm, int, 0);
41 40
42/* In this order: vendor, device, subvendor, subdevice, class, class_mask, 41/* In this order: vendor, device, subvendor, subdevice, class, class_mask,
43 * driver_data 42 * driver_data
44 * If you have an update for this please contact prism54-devel@prism54.org 43 * If you have an update for this please contact prism54-devel@prism54.org
45 * The latest list can be found at http://prism54.org/supported_cards.php */ 44 * The latest list can be found at http://prism54.org/supported_cards.php */
46static const struct pci_device_id prism54_id_tbl[] = { 45static const struct pci_device_id prism54_id_tbl[] = {
47 /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */ 46 /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
@@ -132,15 +131,15 @@ prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id)
132 131
133 /* 0x40 is the programmable timer to configure the response timeout (TRDY_TIMEOUT) 132 /* 0x40 is the programmable timer to configure the response timeout (TRDY_TIMEOUT)
134 * 0x41 is the programmable timer to configure the retry timeout (RETRY_TIMEOUT) 133 * 0x41 is the programmable timer to configure the retry timeout (RETRY_TIMEOUT)
135 * The RETRY_TIMEOUT is used to set the number of retries that the core, as a 134 * The RETRY_TIMEOUT is used to set the number of retries that the core, as a
136 * Master, will perform before abandoning a cycle. The default value for 135 * Master, will perform before abandoning a cycle. The default value for
137 * RETRY_TIMEOUT is 0x80, which far exceeds the PCI 2.1 requirement for new 136 * RETRY_TIMEOUT is 0x80, which far exceeds the PCI 2.1 requirement for new
138 * devices. A write of zero to the RETRY_TIMEOUT register disables this 137 * devices. A write of zero to the RETRY_TIMEOUT register disables this
139 * function to allow use with any non-compliant legacy devices that may 138 * function to allow use with any non-compliant legacy devices that may
140 * execute more retries. 139 * execute more retries.
141 * 140 *
142 * Writing zero to both these two registers will disable both timeouts and 141 * Writing zero to both these two registers will disable both timeouts and
143 * *can* solve problems caused by devices that are slow to respond. 142 * *can* solve problems caused by devices that are slow to respond.
144 * Make this configurable - MSW 143 * Make this configurable - MSW
145 */ 144 */
146 if ( init_pcitm >= 0 ) { 145 if ( init_pcitm >= 0 ) {
@@ -171,14 +170,15 @@ prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id)
171 pci_set_master(pdev); 170 pci_set_master(pdev);
172 171
173 /* enable MWI */ 172 /* enable MWI */
174 pci_set_mwi(pdev); 173 if (!pci_set_mwi(pdev))
174 printk(KERN_INFO "%s: pci_set_mwi(pdev) succeeded\n", DRV_NAME);
175 175
176 /* setup the network device interface and its structure */ 176 /* setup the network device interface and its structure */
177 if (!(ndev = islpci_setup(pdev))) { 177 if (!(ndev = islpci_setup(pdev))) {
178 /* error configuring the driver as a network device */ 178 /* error configuring the driver as a network device */
179 printk(KERN_ERR "%s: could not configure network device\n", 179 printk(KERN_ERR "%s: could not configure network device\n",
180 DRV_NAME); 180 DRV_NAME);
181 goto do_pci_release_regions; 181 goto do_pci_clear_mwi;
182 } 182 }
183 183
184 priv = netdev_priv(ndev); 184 priv = netdev_priv(ndev);
@@ -208,6 +208,8 @@ prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id)
208 pci_set_drvdata(pdev, NULL); 208 pci_set_drvdata(pdev, NULL);
209 free_netdev(ndev); 209 free_netdev(ndev);
210 priv = NULL; 210 priv = NULL;
211 do_pci_clear_mwi:
212 pci_clear_mwi(pdev);
211 do_pci_release_regions: 213 do_pci_release_regions:
212 pci_release_regions(pdev); 214 pci_release_regions(pdev);
213 do_pci_disable_device: 215 do_pci_disable_device:
@@ -241,7 +243,7 @@ prism54_remove(struct pci_dev *pdev)
241 isl38xx_disable_interrupts(priv->device_base); 243 isl38xx_disable_interrupts(priv->device_base);
242 islpci_set_state(priv, PRV_STATE_OFF); 244 islpci_set_state(priv, PRV_STATE_OFF);
243 /* This bellow causes a lockup at rmmod time. It might be 245 /* This bellow causes a lockup at rmmod time. It might be
244 * because some interrupts still linger after rmmod time, 246 * because some interrupts still linger after rmmod time,
245 * see bug #17 */ 247 * see bug #17 */
246 /* pci_set_power_state(pdev, 3);*/ /* try to power-off */ 248 /* pci_set_power_state(pdev, 3);*/ /* try to power-off */
247 } 249 }
@@ -255,6 +257,8 @@ prism54_remove(struct pci_dev *pdev)
255 free_netdev(ndev); 257 free_netdev(ndev);
256 priv = NULL; 258 priv = NULL;
257 259
260 pci_clear_mwi(pdev);
261
258 pci_release_regions(pdev); 262 pci_release_regions(pdev);
259 263
260 pci_disable_device(pdev); 264 pci_disable_device(pdev);
@@ -288,12 +292,19 @@ prism54_resume(struct pci_dev *pdev)
288{ 292{
289 struct net_device *ndev = pci_get_drvdata(pdev); 293 struct net_device *ndev = pci_get_drvdata(pdev);
290 islpci_private *priv = ndev ? netdev_priv(ndev) : NULL; 294 islpci_private *priv = ndev ? netdev_priv(ndev) : NULL;
291 BUG_ON(!priv); 295 int err;
292 296
293 pci_enable_device(pdev); 297 BUG_ON(!priv);
294 298
295 printk(KERN_NOTICE "%s: got resume request\n", ndev->name); 299 printk(KERN_NOTICE "%s: got resume request\n", ndev->name);
296 300
301 err = pci_enable_device(pdev);
302 if (err) {
303 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
304 ndev->name);
305 return err;
306 }
307
297 pci_restore_state(pdev); 308 pci_restore_state(pdev);
298 309
299 /* alright let's go into the PREBOOT state */ 310 /* alright let's go into the PREBOOT state */
diff --git a/drivers/net/wireless/prism54/islpci_mgt.c b/drivers/net/wireless/prism54/islpci_mgt.c
index 656ec9fa7128..2246f7930b4e 100644
--- a/drivers/net/wireless/prism54/islpci_mgt.c
+++ b/drivers/net/wireless/prism54/islpci_mgt.c
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright 2004 Jens Maurer <Jens.Maurer@gmx.net> 3 * Copyright 2004 Jens Maurer <Jens.Maurer@gmx.net>
5 * 4 *
@@ -502,7 +501,7 @@ islpci_mgt_transaction(struct net_device *ndev,
502 printk(KERN_WARNING "%s: timeout waiting for mgmt response\n", 501 printk(KERN_WARNING "%s: timeout waiting for mgmt response\n",
503 ndev->name); 502 ndev->name);
504 503
505 /* TODO: we should reset the device here */ 504 /* TODO: we should reset the device here */
506 out: 505 out:
507 finish_wait(&priv->mgmt_wqueue, &wait); 506 finish_wait(&priv->mgmt_wqueue, &wait);
508 up(&priv->mgmt_sem); 507 up(&priv->mgmt_sem);
diff --git a/drivers/net/wireless/prism54/islpci_mgt.h b/drivers/net/wireless/prism54/islpci_mgt.h
index 2982be3363ef..fc53b587b722 100644
--- a/drivers/net/wireless/prism54/islpci_mgt.h
+++ b/drivers/net/wireless/prism54/islpci_mgt.h
@@ -1,5 +1,4 @@
1/* 1/*
2 *
3 * Copyright (C) 2002 Intersil Americas Inc. 2 * Copyright (C) 2002 Intersil Americas Inc.
4 * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> 3 * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
5 * 4 *
@@ -36,8 +35,8 @@ extern int pc_debug;
36 35
37 36
38/* General driver definitions */ 37/* General driver definitions */
39#define PCIDEVICE_LATENCY_TIMER_MIN 0x40 38#define PCIDEVICE_LATENCY_TIMER_MIN 0x40
40#define PCIDEVICE_LATENCY_TIMER_VAL 0x50 39#define PCIDEVICE_LATENCY_TIMER_VAL 0x50
41 40
42/* Debugging verbose definitions */ 41/* Debugging verbose definitions */
43#define SHOW_NOTHING 0x00 /* overrules everything */ 42#define SHOW_NOTHING 0x00 /* overrules everything */
diff --git a/drivers/net/wireless/prism54/oid_mgt.c b/drivers/net/wireless/prism54/oid_mgt.c
index ebb238785839..fbc52b6a3024 100644
--- a/drivers/net/wireless/prism54/oid_mgt.c
+++ b/drivers/net/wireless/prism54/oid_mgt.c
@@ -1,4 +1,4 @@
1/* 1/*
2 * Copyright (C) 2003,2004 Aurelien Alleaume <slts@free.fr> 2 * Copyright (C) 2003,2004 Aurelien Alleaume <slts@free.fr>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
@@ -503,7 +503,7 @@ mgt_set_varlen(islpci_private *priv, enum oid_num_t n, void *data, int extra_len
503 } 503 }
504 if (ret || response_op == PIMFOR_OP_ERROR) 504 if (ret || response_op == PIMFOR_OP_ERROR)
505 ret = -EIO; 505 ret = -EIO;
506 } else 506 } else
507 ret = -EIO; 507 ret = -EIO;
508 508
509 /* re-set given data to what it was */ 509 /* re-set given data to what it was */
@@ -727,7 +727,7 @@ mgt_commit(islpci_private *priv)
727 * MEDIUMLIMIT,BEACONPERIOD,DTIMPERIOD,ATIMWINDOW,LISTENINTERVAL 727 * MEDIUMLIMIT,BEACONPERIOD,DTIMPERIOD,ATIMWINDOW,LISTENINTERVAL
728 * FREQUENCY,EXTENDEDRATES. 728 * FREQUENCY,EXTENDEDRATES.
729 * 729 *
730 * The way to do this is to set ESSID. Note though that they may get 730 * The way to do this is to set ESSID. Note though that they may get
731 * unlatch before though by setting another OID. */ 731 * unlatch before though by setting another OID. */
732#if 0 732#if 0
733void 733void
diff --git a/drivers/net/wireless/prism54/prismcompat.h b/drivers/net/wireless/prism54/prismcompat.h
index d71eca55a302..aa1d1747784f 100644
--- a/drivers/net/wireless/prism54/prismcompat.h
+++ b/drivers/net/wireless/prism54/prismcompat.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * (C) 2004 Margit Schubert-While <margitsw@t-online.de> 2 * (C) 2004 Margit Schubert-While <margitsw@t-online.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
@@ -16,7 +16,7 @@
16 * 16 *
17 */ 17 */
18 18
19/* 19/*
20 * Compatibility header file to aid support of different kernel versions 20 * Compatibility header file to aid support of different kernel versions
21 */ 21 */
22 22
diff --git a/drivers/net/wireless/zd1201.c b/drivers/net/wireless/zd1201.c
index 36b29ff05814..6cb66a356c96 100644
--- a/drivers/net/wireless/zd1201.c
+++ b/drivers/net/wireless/zd1201.c
@@ -1828,10 +1828,8 @@ err_start:
1828 /* Leave the device in reset state */ 1828 /* Leave the device in reset state */
1829 zd1201_docmd(zd, ZD1201_CMDCODE_INIT, 0, 0, 0); 1829 zd1201_docmd(zd, ZD1201_CMDCODE_INIT, 0, 0, 0);
1830err_zd: 1830err_zd:
1831 if (zd->tx_urb) 1831 usb_free_urb(zd->tx_urb);
1832 usb_free_urb(zd->tx_urb); 1832 usb_free_urb(zd->rx_urb);
1833 if (zd->rx_urb)
1834 usb_free_urb(zd->rx_urb);
1835 kfree(zd); 1833 kfree(zd);
1836 return err; 1834 return err;
1837} 1835}
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
index aa661b2b76c7..8be99ebbe1cd 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.c
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -1076,6 +1076,31 @@ static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1076 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); 1076 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1077} 1077}
1078 1078
1079int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1080 u8 rts_rate, int preamble)
1081{
1082 int rts_mod = ZD_RX_CCK;
1083 u32 value = 0;
1084
1085 /* Modulation bit */
1086 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1087 rts_mod = ZD_RX_OFDM;
1088
1089 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1090 rts_rate, preamble);
1091
1092 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1093 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1094 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1095 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1096
1097 /* We always send 11M self-CTS messages, like the vendor driver. */
1098 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1099 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1100
1101 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1102}
1103
1079int zd_chip_enable_hwint(struct zd_chip *chip) 1104int zd_chip_enable_hwint(struct zd_chip *chip)
1080{ 1105{
1081 int r; 1106 int r;
@@ -1355,17 +1380,12 @@ out:
1355 return r; 1380 return r;
1356} 1381}
1357 1382
1358int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) 1383int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1359{ 1384{
1360 int r; 1385 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1361 1386 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1362 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1363 return -EINVAL;
1364 1387
1365 mutex_lock(&chip->mutex); 1388 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1366 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1367 mutex_unlock(&chip->mutex);
1368 return r;
1369} 1389}
1370 1390
1371static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size) 1391static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h
index ae59597ce4e1..ca892b9a6448 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.h
+++ b/drivers/net/wireless/zd1211rw/zd_chip.h
@@ -337,24 +337,24 @@
337#define CR_MAC_PS_STATE CTL_REG(0x050C) 337#define CR_MAC_PS_STATE CTL_REG(0x050C)
338 338
339#define CR_INTERRUPT CTL_REG(0x0510) 339#define CR_INTERRUPT CTL_REG(0x0510)
340#define INT_TX_COMPLETE 0x00000001 340#define INT_TX_COMPLETE (1 << 0)
341#define INT_RX_COMPLETE 0x00000002 341#define INT_RX_COMPLETE (1 << 1)
342#define INT_RETRY_FAIL 0x00000004 342#define INT_RETRY_FAIL (1 << 2)
343#define INT_WAKEUP 0x00000008 343#define INT_WAKEUP (1 << 3)
344#define INT_DTIM_NOTIFY 0x00000020 344#define INT_DTIM_NOTIFY (1 << 5)
345#define INT_CFG_NEXT_BCN 0x00000040 345#define INT_CFG_NEXT_BCN (1 << 6)
346#define INT_BUS_ABORT 0x00000080 346#define INT_BUS_ABORT (1 << 7)
347#define INT_TX_FIFO_READY 0x00000100 347#define INT_TX_FIFO_READY (1 << 8)
348#define INT_UART 0x00000200 348#define INT_UART (1 << 9)
349#define INT_TX_COMPLETE_EN 0x00010000 349#define INT_TX_COMPLETE_EN (1 << 16)
350#define INT_RX_COMPLETE_EN 0x00020000 350#define INT_RX_COMPLETE_EN (1 << 17)
351#define INT_RETRY_FAIL_EN 0x00040000 351#define INT_RETRY_FAIL_EN (1 << 18)
352#define INT_WAKEUP_EN 0x00080000 352#define INT_WAKEUP_EN (1 << 19)
353#define INT_DTIM_NOTIFY_EN 0x00200000 353#define INT_DTIM_NOTIFY_EN (1 << 21)
354#define INT_CFG_NEXT_BCN_EN 0x00400000 354#define INT_CFG_NEXT_BCN_EN (1 << 22)
355#define INT_BUS_ABORT_EN 0x00800000 355#define INT_BUS_ABORT_EN (1 << 23)
356#define INT_TX_FIFO_READY_EN 0x01000000 356#define INT_TX_FIFO_READY_EN (1 << 24)
357#define INT_UART_EN 0x02000000 357#define INT_UART_EN (1 << 25)
358 358
359#define CR_TSF_LOW_PART CTL_REG(0x0514) 359#define CR_TSF_LOW_PART CTL_REG(0x0514)
360#define CR_TSF_HIGH_PART CTL_REG(0x0518) 360#define CR_TSF_HIGH_PART CTL_REG(0x0518)
@@ -398,18 +398,18 @@
398 * device will use a rate in this table that is less than or equal to the rate 398 * device will use a rate in this table that is less than or equal to the rate
399 * of the incoming frame which prompted the response */ 399 * of the incoming frame which prompted the response */
400#define CR_BASIC_RATE_TBL CTL_REG(0x0630) 400#define CR_BASIC_RATE_TBL CTL_REG(0x0630)
401#define CR_RATE_1M 0x0001 /* 802.11b */ 401#define CR_RATE_1M (1 << 0) /* 802.11b */
402#define CR_RATE_2M 0x0002 /* 802.11b */ 402#define CR_RATE_2M (1 << 1) /* 802.11b */
403#define CR_RATE_5_5M 0x0004 /* 802.11b */ 403#define CR_RATE_5_5M (1 << 2) /* 802.11b */
404#define CR_RATE_11M 0x0008 /* 802.11b */ 404#define CR_RATE_11M (1 << 3) /* 802.11b */
405#define CR_RATE_6M 0x0100 /* 802.11g */ 405#define CR_RATE_6M (1 << 8) /* 802.11g */
406#define CR_RATE_9M 0x0200 /* 802.11g */ 406#define CR_RATE_9M (1 << 9) /* 802.11g */
407#define CR_RATE_12M 0x0400 /* 802.11g */ 407#define CR_RATE_12M (1 << 10) /* 802.11g */
408#define CR_RATE_18M 0x0800 /* 802.11g */ 408#define CR_RATE_18M (1 << 11) /* 802.11g */
409#define CR_RATE_24M 0x1000 /* 802.11g */ 409#define CR_RATE_24M (1 << 12) /* 802.11g */
410#define CR_RATE_36M 0x2000 /* 802.11g */ 410#define CR_RATE_36M (1 << 13) /* 802.11g */
411#define CR_RATE_48M 0x4000 /* 802.11g */ 411#define CR_RATE_48M (1 << 14) /* 802.11g */
412#define CR_RATE_54M 0x8000 /* 802.11g */ 412#define CR_RATE_54M (1 << 15) /* 802.11g */
413#define CR_RATES_80211G 0xff00 413#define CR_RATES_80211G 0xff00
414#define CR_RATES_80211B 0x000f 414#define CR_RATES_80211B 0x000f
415 415
@@ -420,15 +420,24 @@
420#define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) 420#define CR_MANDATORY_RATE_TBL CTL_REG(0x0634)
421#define CR_RTS_CTS_RATE CTL_REG(0x0638) 421#define CR_RTS_CTS_RATE CTL_REG(0x0638)
422 422
423/* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */
424#define RTSCTS_SH_RTS_RATE 0
425#define RTSCTS_SH_EXP_CTS_RATE 4
426#define RTSCTS_SH_RTS_MOD_TYPE 8
427#define RTSCTS_SH_RTS_PMB_TYPE 9
428#define RTSCTS_SH_CTS_RATE 16
429#define RTSCTS_SH_CTS_MOD_TYPE 24
430#define RTSCTS_SH_CTS_PMB_TYPE 25
431
423#define CR_WEP_PROTECT CTL_REG(0x063C) 432#define CR_WEP_PROTECT CTL_REG(0x063C)
424#define CR_RX_THRESHOLD CTL_REG(0x0640) 433#define CR_RX_THRESHOLD CTL_REG(0x0640)
425 434
426/* register for controlling the LEDS */ 435/* register for controlling the LEDS */
427#define CR_LED CTL_REG(0x0644) 436#define CR_LED CTL_REG(0x0644)
428/* masks for controlling LEDs */ 437/* masks for controlling LEDs */
429#define LED1 0x0100 438#define LED1 (1 << 8)
430#define LED2 0x0200 439#define LED2 (1 << 9)
431#define LED_SW 0x0400 440#define LED_SW (1 << 10)
432 441
433/* Seems to indicate that the configuration is over. 442/* Seems to indicate that the configuration is over.
434 */ 443 */
@@ -455,18 +464,18 @@
455 * registers, so one could argue it is a LOCK bit. But calling it 464 * registers, so one could argue it is a LOCK bit. But calling it
456 * LOCK_PHY_REGS makes it confusing. 465 * LOCK_PHY_REGS makes it confusing.
457 */ 466 */
458#define UNLOCK_PHY_REGS 0x0080 467#define UNLOCK_PHY_REGS (1 << 7)
459 468
460#define CR_DEVICE_STATE CTL_REG(0x0684) 469#define CR_DEVICE_STATE CTL_REG(0x0684)
461#define CR_UNDERRUN_CNT CTL_REG(0x0688) 470#define CR_UNDERRUN_CNT CTL_REG(0x0688)
462 471
463#define CR_RX_FILTER CTL_REG(0x068c) 472#define CR_RX_FILTER CTL_REG(0x068c)
464#define RX_FILTER_ASSOC_RESPONSE 0x0002 473#define RX_FILTER_ASSOC_RESPONSE (1 << 1)
465#define RX_FILTER_REASSOC_RESPONSE 0x0008 474#define RX_FILTER_REASSOC_RESPONSE (1 << 3)
466#define RX_FILTER_PROBE_RESPONSE 0x0020 475#define RX_FILTER_PROBE_RESPONSE (1 << 5)
467#define RX_FILTER_BEACON 0x0100 476#define RX_FILTER_BEACON (1 << 8)
468#define RX_FILTER_DISASSOC 0x0400 477#define RX_FILTER_DISASSOC (1 << 10)
469#define RX_FILTER_AUTH 0x0800 478#define RX_FILTER_AUTH (1 << 11)
470#define AP_RX_FILTER 0x0400feff 479#define AP_RX_FILTER 0x0400feff
471#define STA_RX_FILTER 0x0000ffff 480#define STA_RX_FILTER 0x0000ffff
472 481
@@ -794,6 +803,9 @@ void zd_chip_disable_rx(struct zd_chip *chip);
794int zd_chip_enable_hwint(struct zd_chip *chip); 803int zd_chip_enable_hwint(struct zd_chip *chip);
795int zd_chip_disable_hwint(struct zd_chip *chip); 804int zd_chip_disable_hwint(struct zd_chip *chip);
796 805
806int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
807 u8 rts_rate, int preamble);
808
797static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) 809static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type)
798{ 810{
799 return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); 811 return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type);
@@ -809,7 +821,17 @@ static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates)
809 return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); 821 return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates);
810} 822}
811 823
812int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); 824int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates);
825
826static inline int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
827{
828 int r;
829
830 mutex_lock(&chip->mutex);
831 r = zd_chip_set_basic_rates_locked(chip, cr_rates);
832 mutex_unlock(&chip->mutex);
833 return r;
834}
813 835
814static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter) 836static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter)
815{ 837{
diff --git a/drivers/net/wireless/zd1211rw/zd_def.h b/drivers/net/wireless/zd1211rw/zd_def.h
index a13ec72eb304..fb22f62cf1f3 100644
--- a/drivers/net/wireless/zd1211rw/zd_def.h
+++ b/drivers/net/wireless/zd1211rw/zd_def.h
@@ -39,6 +39,7 @@ do { \
39 if (!(x)) { \ 39 if (!(x)) { \
40 pr_debug("%s:%d ASSERT %s VIOLATED!\n", \ 40 pr_debug("%s:%d ASSERT %s VIOLATED!\n", \
41 __FILE__, __LINE__, __stringify(x)); \ 41 __FILE__, __LINE__, __stringify(x)); \
42 dump_stack(); \
42 } \ 43 } \
43} while (0) 44} while (0)
44#else 45#else
diff --git a/drivers/net/wireless/zd1211rw/zd_ieee80211.c b/drivers/net/wireless/zd1211rw/zd_ieee80211.c
index 66905f7b61ff..189160efd2ae 100644
--- a/drivers/net/wireless/zd1211rw/zd_ieee80211.c
+++ b/drivers/net/wireless/zd1211rw/zd_ieee80211.c
@@ -37,7 +37,12 @@ static const struct channel_range channel_ranges[] = {
37 [ZD_REGDOMAIN_JAPAN] = { 1, 14}, 37 [ZD_REGDOMAIN_JAPAN] = { 1, 14},
38 [ZD_REGDOMAIN_SPAIN] = { 1, 14}, 38 [ZD_REGDOMAIN_SPAIN] = { 1, 14},
39 [ZD_REGDOMAIN_FRANCE] = { 1, 14}, 39 [ZD_REGDOMAIN_FRANCE] = { 1, 14},
40 [ZD_REGDOMAIN_JAPAN_ADD] = {14, 15}, 40
41 /* Japan originally only had channel 14 available (see CHNL_ID 0x40 in
42 * 802.11). However, in 2001 the range was extended to include channels
43 * 1-13. The ZyDAS devices still use the old region code but are
44 * designed to allow the extra channel access in Japan. */
45 [ZD_REGDOMAIN_JAPAN_ADD] = { 1, 15},
41}; 46};
42 47
43const struct channel_range *zd_channel_range(u8 regdomain) 48const struct channel_range *zd_channel_range(u8 regdomain)
@@ -133,9 +138,6 @@ int zd_find_channel(u8 *channel, const struct iw_freq *freq)
133 int i, r; 138 int i, r;
134 u32 mhz; 139 u32 mhz;
135 140
136 if (!(freq->flags & IW_FREQ_FIXED))
137 return 0;
138
139 if (freq->m < 1000) { 141 if (freq->m < 1000) {
140 if (freq->m > NUM_CHANNELS || freq->m == 0) 142 if (freq->m > NUM_CHANNELS || freq->m == 0)
141 return -EINVAL; 143 return -EINVAL;
diff --git a/drivers/net/wireless/zd1211rw/zd_ieee80211.h b/drivers/net/wireless/zd1211rw/zd_ieee80211.h
index f63245b0d966..26b8298dff8c 100644
--- a/drivers/net/wireless/zd1211rw/zd_ieee80211.h
+++ b/drivers/net/wireless/zd1211rw/zd_ieee80211.h
@@ -50,6 +50,7 @@ static inline u8 zd_ofdm_plcp_header_rate(
50 return header->prefix[0] & 0xf; 50 return header->prefix[0] & 0xf;
51} 51}
52 52
53/* These are referred to as zd_rates */
53#define ZD_OFDM_RATE_6M 0xb 54#define ZD_OFDM_RATE_6M 0xb
54#define ZD_OFDM_RATE_9M 0xf 55#define ZD_OFDM_RATE_9M 0xf
55#define ZD_OFDM_RATE_12M 0xa 56#define ZD_OFDM_RATE_12M 0xa
@@ -64,7 +65,7 @@ struct cck_plcp_header {
64 u8 service; 65 u8 service;
65 __le16 length; 66 __le16 length;
66 __le16 crc16; 67 __le16 crc16;
67}; 68} __attribute__((packed));
68 69
69static inline u8 zd_cck_plcp_header_rate(const struct cck_plcp_header *header) 70static inline u8 zd_cck_plcp_header_rate(const struct cck_plcp_header *header)
70{ 71{
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c
index 5e4f4b707375..44f3cfd4cc1d 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.c
+++ b/drivers/net/wireless/zd1211rw/zd_mac.c
@@ -32,6 +32,8 @@
32 32
33static void ieee_init(struct ieee80211_device *ieee); 33static void ieee_init(struct ieee80211_device *ieee);
34static void softmac_init(struct ieee80211softmac_device *sm); 34static void softmac_init(struct ieee80211softmac_device *sm);
35static void set_rts_cts_work(void *d);
36static void set_basic_rates_work(void *d);
35 37
36static void housekeeping_init(struct zd_mac *mac); 38static void housekeeping_init(struct zd_mac *mac);
37static void housekeeping_enable(struct zd_mac *mac); 39static void housekeeping_enable(struct zd_mac *mac);
@@ -46,6 +48,8 @@ int zd_mac_init(struct zd_mac *mac,
46 memset(mac, 0, sizeof(*mac)); 48 memset(mac, 0, sizeof(*mac));
47 spin_lock_init(&mac->lock); 49 spin_lock_init(&mac->lock);
48 mac->netdev = netdev; 50 mac->netdev = netdev;
51 INIT_WORK(&mac->set_rts_cts_work, set_rts_cts_work, mac);
52 INIT_WORK(&mac->set_basic_rates_work, set_basic_rates_work, mac);
49 53
50 ieee_init(ieee); 54 ieee_init(ieee);
51 softmac_init(ieee80211_priv(netdev)); 55 softmac_init(ieee80211_priv(netdev));
@@ -213,6 +217,13 @@ int zd_mac_stop(struct net_device *netdev)
213 housekeeping_disable(mac); 217 housekeeping_disable(mac);
214 ieee80211softmac_stop(netdev); 218 ieee80211softmac_stop(netdev);
215 219
220 /* Ensure no work items are running or queued from this point */
221 cancel_delayed_work(&mac->set_rts_cts_work);
222 cancel_delayed_work(&mac->set_basic_rates_work);
223 flush_workqueue(zd_workqueue);
224 mac->updating_rts_rate = 0;
225 mac->updating_basic_rates = 0;
226
216 zd_chip_disable_hwint(chip); 227 zd_chip_disable_hwint(chip);
217 zd_chip_switch_radio_off(chip); 228 zd_chip_switch_radio_off(chip);
218 zd_chip_disable_int(chip); 229 zd_chip_disable_int(chip);
@@ -286,6 +297,186 @@ u8 zd_mac_get_regdomain(struct zd_mac *mac)
286 return regdomain; 297 return regdomain;
287} 298}
288 299
300/* Fallback to lowest rate, if rate is unknown. */
301static u8 rate_to_zd_rate(u8 rate)
302{
303 switch (rate) {
304 case IEEE80211_CCK_RATE_2MB:
305 return ZD_CCK_RATE_2M;
306 case IEEE80211_CCK_RATE_5MB:
307 return ZD_CCK_RATE_5_5M;
308 case IEEE80211_CCK_RATE_11MB:
309 return ZD_CCK_RATE_11M;
310 case IEEE80211_OFDM_RATE_6MB:
311 return ZD_OFDM_RATE_6M;
312 case IEEE80211_OFDM_RATE_9MB:
313 return ZD_OFDM_RATE_9M;
314 case IEEE80211_OFDM_RATE_12MB:
315 return ZD_OFDM_RATE_12M;
316 case IEEE80211_OFDM_RATE_18MB:
317 return ZD_OFDM_RATE_18M;
318 case IEEE80211_OFDM_RATE_24MB:
319 return ZD_OFDM_RATE_24M;
320 case IEEE80211_OFDM_RATE_36MB:
321 return ZD_OFDM_RATE_36M;
322 case IEEE80211_OFDM_RATE_48MB:
323 return ZD_OFDM_RATE_48M;
324 case IEEE80211_OFDM_RATE_54MB:
325 return ZD_OFDM_RATE_54M;
326 }
327 return ZD_CCK_RATE_1M;
328}
329
330static u16 rate_to_cr_rate(u8 rate)
331{
332 switch (rate) {
333 case IEEE80211_CCK_RATE_2MB:
334 return CR_RATE_1M;
335 case IEEE80211_CCK_RATE_5MB:
336 return CR_RATE_5_5M;
337 case IEEE80211_CCK_RATE_11MB:
338 return CR_RATE_11M;
339 case IEEE80211_OFDM_RATE_6MB:
340 return CR_RATE_6M;
341 case IEEE80211_OFDM_RATE_9MB:
342 return CR_RATE_9M;
343 case IEEE80211_OFDM_RATE_12MB:
344 return CR_RATE_12M;
345 case IEEE80211_OFDM_RATE_18MB:
346 return CR_RATE_18M;
347 case IEEE80211_OFDM_RATE_24MB:
348 return CR_RATE_24M;
349 case IEEE80211_OFDM_RATE_36MB:
350 return CR_RATE_36M;
351 case IEEE80211_OFDM_RATE_48MB:
352 return CR_RATE_48M;
353 case IEEE80211_OFDM_RATE_54MB:
354 return CR_RATE_54M;
355 }
356 return CR_RATE_1M;
357}
358
359static void try_enable_tx(struct zd_mac *mac)
360{
361 unsigned long flags;
362
363 spin_lock_irqsave(&mac->lock, flags);
364 if (mac->updating_rts_rate == 0 && mac->updating_basic_rates == 0)
365 netif_wake_queue(mac->netdev);
366 spin_unlock_irqrestore(&mac->lock, flags);
367}
368
369static void set_rts_cts_work(void *d)
370{
371 struct zd_mac *mac = d;
372 unsigned long flags;
373 u8 rts_rate;
374 unsigned int short_preamble;
375
376 mutex_lock(&mac->chip.mutex);
377
378 spin_lock_irqsave(&mac->lock, flags);
379 mac->updating_rts_rate = 0;
380 rts_rate = mac->rts_rate;
381 short_preamble = mac->short_preamble;
382 spin_unlock_irqrestore(&mac->lock, flags);
383
384 zd_chip_set_rts_cts_rate_locked(&mac->chip, rts_rate, short_preamble);
385 mutex_unlock(&mac->chip.mutex);
386
387 try_enable_tx(mac);
388}
389
390static void set_basic_rates_work(void *d)
391{
392 struct zd_mac *mac = d;
393 unsigned long flags;
394 u16 basic_rates;
395
396 mutex_lock(&mac->chip.mutex);
397
398 spin_lock_irqsave(&mac->lock, flags);
399 mac->updating_basic_rates = 0;
400 basic_rates = mac->basic_rates;
401 spin_unlock_irqrestore(&mac->lock, flags);
402
403 zd_chip_set_basic_rates_locked(&mac->chip, basic_rates);
404 mutex_unlock(&mac->chip.mutex);
405
406 try_enable_tx(mac);
407}
408
409static void bssinfo_change(struct net_device *netdev, u32 changes)
410{
411 struct zd_mac *mac = zd_netdev_mac(netdev);
412 struct ieee80211softmac_device *softmac = ieee80211_priv(netdev);
413 struct ieee80211softmac_bss_info *bssinfo = &softmac->bssinfo;
414 int need_set_rts_cts = 0;
415 int need_set_rates = 0;
416 u16 basic_rates;
417 unsigned long flags;
418
419 dev_dbg_f(zd_mac_dev(mac), "changes: %x\n", changes);
420
421 if (changes & IEEE80211SOFTMAC_BSSINFOCHG_SHORT_PREAMBLE) {
422 spin_lock_irqsave(&mac->lock, flags);
423 mac->short_preamble = bssinfo->short_preamble;
424 spin_unlock_irqrestore(&mac->lock, flags);
425 need_set_rts_cts = 1;
426 }
427
428 if (changes & IEEE80211SOFTMAC_BSSINFOCHG_RATES) {
429 /* Set RTS rate to highest available basic rate */
430 u8 rate = ieee80211softmac_highest_supported_rate(softmac,
431 &bssinfo->supported_rates, 1);
432 rate = rate_to_zd_rate(rate);
433
434 spin_lock_irqsave(&mac->lock, flags);
435 if (rate != mac->rts_rate) {
436 mac->rts_rate = rate;
437 need_set_rts_cts = 1;
438 }
439 spin_unlock_irqrestore(&mac->lock, flags);
440
441 /* Set basic rates */
442 need_set_rates = 1;
443 if (bssinfo->supported_rates.count == 0) {
444 /* Allow the device to be flexible */
445 basic_rates = CR_RATES_80211B | CR_RATES_80211G;
446 } else {
447 int i = 0;
448 basic_rates = 0;
449
450 for (i = 0; i < bssinfo->supported_rates.count; i++) {
451 u16 rate = bssinfo->supported_rates.rates[i];
452 if ((rate & IEEE80211_BASIC_RATE_MASK) == 0)
453 continue;
454
455 rate &= ~IEEE80211_BASIC_RATE_MASK;
456 basic_rates |= rate_to_cr_rate(rate);
457 }
458 }
459 spin_lock_irqsave(&mac->lock, flags);
460 mac->basic_rates = basic_rates;
461 spin_unlock_irqrestore(&mac->lock, flags);
462 }
463
464 /* Schedule any changes we made above */
465
466 spin_lock_irqsave(&mac->lock, flags);
467 if (need_set_rts_cts && !mac->updating_rts_rate) {
468 mac->updating_rts_rate = 1;
469 netif_stop_queue(mac->netdev);
470 queue_work(zd_workqueue, &mac->set_rts_cts_work);
471 }
472 if (need_set_rates && !mac->updating_basic_rates) {
473 mac->updating_basic_rates = 1;
474 netif_stop_queue(mac->netdev);
475 queue_work(zd_workqueue, &mac->set_basic_rates_work);
476 }
477 spin_unlock_irqrestore(&mac->lock, flags);
478}
479
289static void set_channel(struct net_device *netdev, u8 channel) 480static void set_channel(struct net_device *netdev, u8 channel)
290{ 481{
291 struct zd_mac *mac = zd_netdev_mac(netdev); 482 struct zd_mac *mac = zd_netdev_mac(netdev);
@@ -295,7 +486,6 @@ static void set_channel(struct net_device *netdev, u8 channel)
295 zd_chip_set_channel(&mac->chip, channel); 486 zd_chip_set_channel(&mac->chip, channel);
296} 487}
297 488
298/* TODO: Should not work in Managed mode. */
299int zd_mac_request_channel(struct zd_mac *mac, u8 channel) 489int zd_mac_request_channel(struct zd_mac *mac, u8 channel)
300{ 490{
301 unsigned long lock_flags; 491 unsigned long lock_flags;
@@ -317,31 +507,22 @@ int zd_mac_request_channel(struct zd_mac *mac, u8 channel)
317 return 0; 507 return 0;
318} 508}
319 509
320int zd_mac_get_channel(struct zd_mac *mac, u8 *channel, u8 *flags) 510u8 zd_mac_get_channel(struct zd_mac *mac)
321{ 511{
322 struct ieee80211_device *ieee = zd_mac_to_ieee80211(mac); 512 u8 channel = zd_chip_get_channel(&mac->chip);
323 513
324 *channel = zd_chip_get_channel(&mac->chip); 514 dev_dbg_f(zd_mac_dev(mac), "channel %u\n", channel);
325 if (ieee->iw_mode != IW_MODE_INFRA) { 515 return channel;
326 spin_lock_irq(&mac->lock);
327 *flags = *channel == mac->requested_channel ?
328 MAC_FIXED_CHANNEL : 0;
329 spin_unlock(&mac->lock);
330 } else {
331 *flags = 0;
332 }
333 dev_dbg_f(zd_mac_dev(mac), "channel %u flags %u\n", *channel, *flags);
334 return 0;
335} 516}
336 517
337/* If wrong rate is given, we are falling back to the slowest rate: 1MBit/s */ 518/* If wrong rate is given, we are falling back to the slowest rate: 1MBit/s */
338static u8 cs_typed_rate(u8 cs_rate) 519static u8 zd_rate_typed(u8 zd_rate)
339{ 520{
340 static const u8 typed_rates[16] = { 521 static const u8 typed_rates[16] = {
341 [ZD_CS_CCK_RATE_1M] = ZD_CS_CCK|ZD_CS_CCK_RATE_1M, 522 [ZD_CCK_RATE_1M] = ZD_CS_CCK|ZD_CCK_RATE_1M,
342 [ZD_CS_CCK_RATE_2M] = ZD_CS_CCK|ZD_CS_CCK_RATE_2M, 523 [ZD_CCK_RATE_2M] = ZD_CS_CCK|ZD_CCK_RATE_2M,
343 [ZD_CS_CCK_RATE_5_5M] = ZD_CS_CCK|ZD_CS_CCK_RATE_5_5M, 524 [ZD_CCK_RATE_5_5M] = ZD_CS_CCK|ZD_CCK_RATE_5_5M,
344 [ZD_CS_CCK_RATE_11M] = ZD_CS_CCK|ZD_CS_CCK_RATE_11M, 525 [ZD_CCK_RATE_11M] = ZD_CS_CCK|ZD_CCK_RATE_11M,
345 [ZD_OFDM_RATE_6M] = ZD_CS_OFDM|ZD_OFDM_RATE_6M, 526 [ZD_OFDM_RATE_6M] = ZD_CS_OFDM|ZD_OFDM_RATE_6M,
346 [ZD_OFDM_RATE_9M] = ZD_CS_OFDM|ZD_OFDM_RATE_9M, 527 [ZD_OFDM_RATE_9M] = ZD_CS_OFDM|ZD_OFDM_RATE_9M,
347 [ZD_OFDM_RATE_12M] = ZD_CS_OFDM|ZD_OFDM_RATE_12M, 528 [ZD_OFDM_RATE_12M] = ZD_CS_OFDM|ZD_OFDM_RATE_12M,
@@ -353,37 +534,7 @@ static u8 cs_typed_rate(u8 cs_rate)
353 }; 534 };
354 535
355 ZD_ASSERT(ZD_CS_RATE_MASK == 0x0f); 536 ZD_ASSERT(ZD_CS_RATE_MASK == 0x0f);
356 return typed_rates[cs_rate & ZD_CS_RATE_MASK]; 537 return typed_rates[zd_rate & ZD_CS_RATE_MASK];
357}
358
359/* Fallback to lowest rate, if rate is unknown. */
360static u8 rate_to_cs_rate(u8 rate)
361{
362 switch (rate) {
363 case IEEE80211_CCK_RATE_2MB:
364 return ZD_CS_CCK_RATE_2M;
365 case IEEE80211_CCK_RATE_5MB:
366 return ZD_CS_CCK_RATE_5_5M;
367 case IEEE80211_CCK_RATE_11MB:
368 return ZD_CS_CCK_RATE_11M;
369 case IEEE80211_OFDM_RATE_6MB:
370 return ZD_OFDM_RATE_6M;
371 case IEEE80211_OFDM_RATE_9MB:
372 return ZD_OFDM_RATE_9M;
373 case IEEE80211_OFDM_RATE_12MB:
374 return ZD_OFDM_RATE_12M;
375 case IEEE80211_OFDM_RATE_18MB:
376 return ZD_OFDM_RATE_18M;
377 case IEEE80211_OFDM_RATE_24MB:
378 return ZD_OFDM_RATE_24M;
379 case IEEE80211_OFDM_RATE_36MB:
380 return ZD_OFDM_RATE_36M;
381 case IEEE80211_OFDM_RATE_48MB:
382 return ZD_OFDM_RATE_48M;
383 case IEEE80211_OFDM_RATE_54MB:
384 return ZD_OFDM_RATE_54M;
385 }
386 return ZD_CS_CCK_RATE_1M;
387} 538}
388 539
389int zd_mac_set_mode(struct zd_mac *mac, u32 mode) 540int zd_mac_set_mode(struct zd_mac *mac, u32 mode)
@@ -484,13 +635,13 @@ int zd_mac_get_range(struct zd_mac *mac, struct iw_range *range)
484 return 0; 635 return 0;
485} 636}
486 637
487static int zd_calc_tx_length_us(u8 *service, u8 cs_rate, u16 tx_length) 638static int zd_calc_tx_length_us(u8 *service, u8 zd_rate, u16 tx_length)
488{ 639{
489 static const u8 rate_divisor[] = { 640 static const u8 rate_divisor[] = {
490 [ZD_CS_CCK_RATE_1M] = 1, 641 [ZD_CCK_RATE_1M] = 1,
491 [ZD_CS_CCK_RATE_2M] = 2, 642 [ZD_CCK_RATE_2M] = 2,
492 [ZD_CS_CCK_RATE_5_5M] = 11, /* bits must be doubled */ 643 [ZD_CCK_RATE_5_5M] = 11, /* bits must be doubled */
493 [ZD_CS_CCK_RATE_11M] = 11, 644 [ZD_CCK_RATE_11M] = 11,
494 [ZD_OFDM_RATE_6M] = 6, 645 [ZD_OFDM_RATE_6M] = 6,
495 [ZD_OFDM_RATE_9M] = 9, 646 [ZD_OFDM_RATE_9M] = 9,
496 [ZD_OFDM_RATE_12M] = 12, 647 [ZD_OFDM_RATE_12M] = 12,
@@ -504,15 +655,15 @@ static int zd_calc_tx_length_us(u8 *service, u8 cs_rate, u16 tx_length)
504 u32 bits = (u32)tx_length * 8; 655 u32 bits = (u32)tx_length * 8;
505 u32 divisor; 656 u32 divisor;
506 657
507 divisor = rate_divisor[cs_rate]; 658 divisor = rate_divisor[zd_rate];
508 if (divisor == 0) 659 if (divisor == 0)
509 return -EINVAL; 660 return -EINVAL;
510 661
511 switch (cs_rate) { 662 switch (zd_rate) {
512 case ZD_CS_CCK_RATE_5_5M: 663 case ZD_CCK_RATE_5_5M:
513 bits = (2*bits) + 10; /* round up to the next integer */ 664 bits = (2*bits) + 10; /* round up to the next integer */
514 break; 665 break;
515 case ZD_CS_CCK_RATE_11M: 666 case ZD_CCK_RATE_11M:
516 if (service) { 667 if (service) {
517 u32 t = bits % 11; 668 u32 t = bits % 11;
518 *service &= ~ZD_PLCP_SERVICE_LENGTH_EXTENSION; 669 *service &= ~ZD_PLCP_SERVICE_LENGTH_EXTENSION;
@@ -532,16 +683,16 @@ enum {
532 R2M_11A = 0x02, 683 R2M_11A = 0x02,
533}; 684};
534 685
535static u8 cs_rate_to_modulation(u8 cs_rate, int flags) 686static u8 zd_rate_to_modulation(u8 zd_rate, int flags)
536{ 687{
537 u8 modulation; 688 u8 modulation;
538 689
539 modulation = cs_typed_rate(cs_rate); 690 modulation = zd_rate_typed(zd_rate);
540 if (flags & R2M_SHORT_PREAMBLE) { 691 if (flags & R2M_SHORT_PREAMBLE) {
541 switch (ZD_CS_RATE(modulation)) { 692 switch (ZD_CS_RATE(modulation)) {
542 case ZD_CS_CCK_RATE_2M: 693 case ZD_CCK_RATE_2M:
543 case ZD_CS_CCK_RATE_5_5M: 694 case ZD_CCK_RATE_5_5M:
544 case ZD_CS_CCK_RATE_11M: 695 case ZD_CCK_RATE_11M:
545 modulation |= ZD_CS_CCK_PREA_SHORT; 696 modulation |= ZD_CS_CCK_PREA_SHORT;
546 return modulation; 697 return modulation;
547 } 698 }
@@ -558,39 +709,36 @@ static void cs_set_modulation(struct zd_mac *mac, struct zd_ctrlset *cs,
558{ 709{
559 struct ieee80211softmac_device *softmac = ieee80211_priv(mac->netdev); 710 struct ieee80211softmac_device *softmac = ieee80211_priv(mac->netdev);
560 u16 ftype = WLAN_FC_GET_TYPE(le16_to_cpu(hdr->frame_ctl)); 711 u16 ftype = WLAN_FC_GET_TYPE(le16_to_cpu(hdr->frame_ctl));
561 u8 rate, cs_rate; 712 u8 rate, zd_rate;
562 int is_mgt = (ftype == IEEE80211_FTYPE_MGMT) != 0; 713 int is_mgt = (ftype == IEEE80211_FTYPE_MGMT) != 0;
714 int is_multicast = is_multicast_ether_addr(hdr->addr1);
715 int short_preamble = ieee80211softmac_short_preamble_ok(softmac,
716 is_multicast, is_mgt);
717 int flags = 0;
718
719 /* FIXME: 802.11a? */
720 rate = ieee80211softmac_suggest_txrate(softmac, is_multicast, is_mgt);
563 721
564 /* FIXME: 802.11a? short preamble? */ 722 if (short_preamble)
565 rate = ieee80211softmac_suggest_txrate(softmac, 723 flags |= R2M_SHORT_PREAMBLE;
566 is_multicast_ether_addr(hdr->addr1), is_mgt);
567 724
568 cs_rate = rate_to_cs_rate(rate); 725 zd_rate = rate_to_zd_rate(rate);
569 cs->modulation = cs_rate_to_modulation(cs_rate, 0); 726 cs->modulation = zd_rate_to_modulation(zd_rate, flags);
570} 727}
571 728
572static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs, 729static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
573 struct ieee80211_hdr_4addr *header) 730 struct ieee80211_hdr_4addr *header)
574{ 731{
732 struct ieee80211softmac_device *softmac = ieee80211_priv(mac->netdev);
575 unsigned int tx_length = le16_to_cpu(cs->tx_length); 733 unsigned int tx_length = le16_to_cpu(cs->tx_length);
576 u16 fctl = le16_to_cpu(header->frame_ctl); 734 u16 fctl = le16_to_cpu(header->frame_ctl);
577 u16 ftype = WLAN_FC_GET_TYPE(fctl); 735 u16 ftype = WLAN_FC_GET_TYPE(fctl);
578 u16 stype = WLAN_FC_GET_STYPE(fctl); 736 u16 stype = WLAN_FC_GET_STYPE(fctl);
579 737
580 /* 738 /*
581 * CONTROL: 739 * CONTROL TODO:
582 * - start at 0x00
583 * - if fragment 0, enable bit 0
584 * - if backoff needed, enable bit 0 740 * - if backoff needed, enable bit 0
585 * - if burst (backoff not needed) disable bit 0 741 * - if burst (backoff not needed) disable bit 0
586 * - if multicast, enable bit 1
587 * - if PS-POLL frame, enable bit 2
588 * - if in INDEPENDENT_BSS mode and zd1205_DestPowerSave, then enable
589 * bit 4 (FIXME: wtf)
590 * - if frag_len > RTS threshold, set bit 5 as long if it isnt
591 * multicast or mgt
592 * - if bit 5 is set, and we are in OFDM mode, unset bit 5 and set bit
593 * 7
594 */ 742 */
595 743
596 cs->control = 0; 744 cs->control = 0;
@@ -607,17 +755,18 @@ static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
607 if (stype == IEEE80211_STYPE_PSPOLL) 755 if (stype == IEEE80211_STYPE_PSPOLL)
608 cs->control |= ZD_CS_PS_POLL_FRAME; 756 cs->control |= ZD_CS_PS_POLL_FRAME;
609 757
758 /* Unicast data frames over the threshold should have RTS */
610 if (!is_multicast_ether_addr(header->addr1) && 759 if (!is_multicast_ether_addr(header->addr1) &&
611 ftype != IEEE80211_FTYPE_MGMT && 760 ftype != IEEE80211_FTYPE_MGMT &&
612 tx_length > zd_netdev_ieee80211(mac->netdev)->rts) 761 tx_length > zd_netdev_ieee80211(mac->netdev)->rts)
613 { 762 cs->control |= ZD_CS_RTS;
614 /* FIXME: check the logic */ 763
615 if (ZD_CS_TYPE(cs->modulation) == ZD_CS_OFDM) { 764 /* Use CTS-to-self protection if required */
616 /* 802.11g */ 765 if (ZD_CS_TYPE(cs->modulation) == ZD_CS_OFDM &&
617 cs->control |= ZD_CS_SELF_CTS; 766 ieee80211softmac_protection_needed(softmac)) {
618 } else { /* 802.11b */ 767 /* FIXME: avoid sending RTS *and* self-CTS, is that correct? */
619 cs->control |= ZD_CS_RTS; 768 cs->control &= ~ZD_CS_RTS;
620 } 769 cs->control |= ZD_CS_SELF_CTS;
621 } 770 }
622 771
623 /* FIXME: Management frame? */ 772 /* FIXME: Management frame? */
@@ -721,7 +870,7 @@ struct zd_rt_hdr {
721 u8 rt_rate; 870 u8 rt_rate;
722 u16 rt_channel; 871 u16 rt_channel;
723 u16 rt_chbitmask; 872 u16 rt_chbitmask;
724}; 873} __attribute__((packed));
725 874
726static void fill_rt_header(void *buffer, struct zd_mac *mac, 875static void fill_rt_header(void *buffer, struct zd_mac *mac,
727 const struct ieee80211_rx_stats *stats, 876 const struct ieee80211_rx_stats *stats,
@@ -782,9 +931,11 @@ static int is_data_packet_for_us(struct ieee80211_device *ieee,
782 (netdev->flags & IFF_PROMISC); 931 (netdev->flags & IFF_PROMISC);
783} 932}
784 933
785/* Filters receiving packets. If it returns 1 send it to ieee80211_rx, if 0 934/* Filters received packets. The function returns 1 if the packet should be
786 * return. If an error is detected -EINVAL is returned. ieee80211_rx_mgt() is 935 * forwarded to ieee80211_rx(). If the packet should be ignored the function
787 * called here. 936 * returns 0. If an invalid packet is found the function returns -EINVAL.
937 *
938 * The function calls ieee80211_rx_mgt() directly.
788 * 939 *
789 * It has been based on ieee80211_rx_any. 940 * It has been based on ieee80211_rx_any.
790 */ 941 */
@@ -810,9 +961,9 @@ static int filter_rx(struct ieee80211_device *ieee,
810 ieee80211_rx_mgt(ieee, hdr, stats); 961 ieee80211_rx_mgt(ieee, hdr, stats);
811 return 0; 962 return 0;
812 case IEEE80211_FTYPE_CTL: 963 case IEEE80211_FTYPE_CTL:
813 /* Ignore invalid short buffers */
814 return 0; 964 return 0;
815 case IEEE80211_FTYPE_DATA: 965 case IEEE80211_FTYPE_DATA:
966 /* Ignore invalid short buffers */
816 if (length < sizeof(struct ieee80211_hdr_3addr)) 967 if (length < sizeof(struct ieee80211_hdr_3addr))
817 return -EINVAL; 968 return -EINVAL;
818 return is_data_packet_for_us(ieee, hdr); 969 return is_data_packet_for_us(ieee, hdr);
@@ -993,6 +1144,7 @@ static void ieee_init(struct ieee80211_device *ieee)
993static void softmac_init(struct ieee80211softmac_device *sm) 1144static void softmac_init(struct ieee80211softmac_device *sm)
994{ 1145{
995 sm->set_channel = set_channel; 1146 sm->set_channel = set_channel;
1147 sm->bssinfo_change = bssinfo_change;
996} 1148}
997 1149
998struct iw_statistics *zd_mac_get_wireless_stats(struct net_device *ndev) 1150struct iw_statistics *zd_mac_get_wireless_stats(struct net_device *ndev)
@@ -1028,66 +1180,6 @@ struct iw_statistics *zd_mac_get_wireless_stats(struct net_device *ndev)
1028 return iw_stats; 1180 return iw_stats;
1029} 1181}
1030 1182
1031#ifdef DEBUG
1032static const char* decryption_types[] = {
1033 [ZD_RX_NO_WEP] = "none",
1034 [ZD_RX_WEP64] = "WEP64",
1035 [ZD_RX_TKIP] = "TKIP",
1036 [ZD_RX_AES] = "AES",
1037 [ZD_RX_WEP128] = "WEP128",
1038 [ZD_RX_WEP256] = "WEP256",
1039};
1040
1041static const char *decryption_type_string(u8 type)
1042{
1043 const char *s;
1044
1045 if (type < ARRAY_SIZE(decryption_types)) {
1046 s = decryption_types[type];
1047 } else {
1048 s = NULL;
1049 }
1050 return s ? s : "unknown";
1051}
1052
1053static int is_ofdm(u8 frame_status)
1054{
1055 return (frame_status & ZD_RX_OFDM);
1056}
1057
1058void zd_dump_rx_status(const struct rx_status *status)
1059{
1060 const char* modulation;
1061 u8 quality;
1062
1063 if (is_ofdm(status->frame_status)) {
1064 modulation = "ofdm";
1065 quality = status->signal_quality_ofdm;
1066 } else {
1067 modulation = "cck";
1068 quality = status->signal_quality_cck;
1069 }
1070 pr_debug("rx status %s strength %#04x qual %#04x decryption %s\n",
1071 modulation, status->signal_strength, quality,
1072 decryption_type_string(status->decryption_type));
1073 if (status->frame_status & ZD_RX_ERROR) {
1074 pr_debug("rx error %s%s%s%s%s%s\n",
1075 (status->frame_status & ZD_RX_TIMEOUT_ERROR) ?
1076 "timeout " : "",
1077 (status->frame_status & ZD_RX_FIFO_OVERRUN_ERROR) ?
1078 "fifo " : "",
1079 (status->frame_status & ZD_RX_DECRYPTION_ERROR) ?
1080 "decryption " : "",
1081 (status->frame_status & ZD_RX_CRC32_ERROR) ?
1082 "crc32 " : "",
1083 (status->frame_status & ZD_RX_NO_ADDR1_MATCH_ERROR) ?
1084 "addr1 " : "",
1085 (status->frame_status & ZD_RX_CRC16_ERROR) ?
1086 "crc16" : "");
1087 }
1088}
1089#endif /* DEBUG */
1090
1091#define LINK_LED_WORK_DELAY HZ 1183#define LINK_LED_WORK_DELAY HZ
1092 1184
1093static void link_led_handler(struct work_struct *work) 1185static void link_led_handler(struct work_struct *work)
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.h b/drivers/net/wireless/zd1211rw/zd_mac.h
index 7957cac3de25..08d6b8c08e75 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.h
+++ b/drivers/net/wireless/zd1211rw/zd_mac.h
@@ -20,6 +20,7 @@
20 20
21#include <linux/wireless.h> 21#include <linux/wireless.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/workqueue.h>
23#include <net/ieee80211.h> 24#include <net/ieee80211.h>
24#include <net/ieee80211softmac.h> 25#include <net/ieee80211softmac.h>
25 26
@@ -48,10 +49,11 @@ struct zd_ctrlset {
48#define ZD_CS_CCK 0x00 49#define ZD_CS_CCK 0x00
49#define ZD_CS_OFDM 0x10 50#define ZD_CS_OFDM 0x10
50 51
51#define ZD_CS_CCK_RATE_1M 0x00 52/* These are referred to as zd_rates */
52#define ZD_CS_CCK_RATE_2M 0x01 53#define ZD_CCK_RATE_1M 0x00
53#define ZD_CS_CCK_RATE_5_5M 0x02 54#define ZD_CCK_RATE_2M 0x01
54#define ZD_CS_CCK_RATE_11M 0x03 55#define ZD_CCK_RATE_5_5M 0x02
56#define ZD_CCK_RATE_11M 0x03
55/* The rates for OFDM are encoded as in the PLCP header. Use ZD_OFDM_RATE_*. 57/* The rates for OFDM are encoded as in the PLCP header. Use ZD_OFDM_RATE_*.
56 */ 58 */
57 59
@@ -82,7 +84,7 @@ struct zd_ctrlset {
82struct rx_length_info { 84struct rx_length_info {
83 __le16 length[3]; 85 __le16 length[3];
84 __le16 tag; 86 __le16 tag;
85}; 87} __attribute__((packed));
86 88
87#define RX_LENGTH_INFO_TAG 0x697e 89#define RX_LENGTH_INFO_TAG 0x697e
88 90
@@ -93,7 +95,7 @@ struct rx_status {
93 u8 signal_quality_ofdm; 95 u8 signal_quality_ofdm;
94 u8 decryption_type; 96 u8 decryption_type;
95 u8 frame_status; 97 u8 frame_status;
96}; 98} __attribute__((packed));
97 99
98/* rx_status field decryption_type */ 100/* rx_status field decryption_type */
99#define ZD_RX_NO_WEP 0 101#define ZD_RX_NO_WEP 0
@@ -116,10 +118,6 @@ struct rx_status {
116#define ZD_RX_CRC16_ERROR 0x40 118#define ZD_RX_CRC16_ERROR 0x40
117#define ZD_RX_ERROR 0x80 119#define ZD_RX_ERROR 0x80
118 120
119enum mac_flags {
120 MAC_FIXED_CHANNEL = 0x01,
121};
122
123struct housekeeping { 121struct housekeeping {
124 struct delayed_work link_led_work; 122 struct delayed_work link_led_work;
125}; 123};
@@ -130,15 +128,33 @@ struct zd_mac {
130 struct zd_chip chip; 128 struct zd_chip chip;
131 spinlock_t lock; 129 spinlock_t lock;
132 struct net_device *netdev; 130 struct net_device *netdev;
131
133 /* Unlocked reading possible */ 132 /* Unlocked reading possible */
134 struct iw_statistics iw_stats; 133 struct iw_statistics iw_stats;
134
135 struct housekeeping housekeeping; 135 struct housekeeping housekeeping;
136 struct work_struct set_rts_cts_work;
137 struct work_struct set_basic_rates_work;
138
136 unsigned int stats_count; 139 unsigned int stats_count;
137 u8 qual_buffer[ZD_MAC_STATS_BUFFER_SIZE]; 140 u8 qual_buffer[ZD_MAC_STATS_BUFFER_SIZE];
138 u8 rssi_buffer[ZD_MAC_STATS_BUFFER_SIZE]; 141 u8 rssi_buffer[ZD_MAC_STATS_BUFFER_SIZE];
139 u8 regdomain; 142 u8 regdomain;
140 u8 default_regdomain; 143 u8 default_regdomain;
141 u8 requested_channel; 144 u8 requested_channel;
145
146 /* A bitpattern of cr_rates */
147 u16 basic_rates;
148
149 /* A zd_rate */
150 u8 rts_rate;
151
152 /* Short preamble (used for RTS/CTS) */
153 unsigned int short_preamble:1;
154
155 /* flags to indicate update in progress */
156 unsigned int updating_rts_rate:1;
157 unsigned int updating_basic_rates:1;
142}; 158};
143 159
144static inline struct ieee80211_device *zd_mac_to_ieee80211(struct zd_mac *mac) 160static inline struct ieee80211_device *zd_mac_to_ieee80211(struct zd_mac *mac)
@@ -180,7 +196,7 @@ int zd_mac_set_regdomain(struct zd_mac *zd_mac, u8 regdomain);
180u8 zd_mac_get_regdomain(struct zd_mac *zd_mac); 196u8 zd_mac_get_regdomain(struct zd_mac *zd_mac);
181 197
182int zd_mac_request_channel(struct zd_mac *mac, u8 channel); 198int zd_mac_request_channel(struct zd_mac *mac, u8 channel);
183int zd_mac_get_channel(struct zd_mac *mac, u8 *channel, u8 *flags); 199u8 zd_mac_get_channel(struct zd_mac *mac);
184 200
185int zd_mac_set_mode(struct zd_mac *mac, u32 mode); 201int zd_mac_set_mode(struct zd_mac *mac, u32 mode);
186int zd_mac_get_mode(struct zd_mac *mac, u32 *mode); 202int zd_mac_get_mode(struct zd_mac *mac, u32 *mode);
diff --git a/drivers/net/wireless/zd1211rw/zd_netdev.c b/drivers/net/wireless/zd1211rw/zd_netdev.c
index af3a7b36d078..60f1b0f6d45b 100644
--- a/drivers/net/wireless/zd1211rw/zd_netdev.c
+++ b/drivers/net/wireless/zd1211rw/zd_netdev.c
@@ -107,21 +107,10 @@ static int iw_get_freq(struct net_device *netdev,
107 struct iw_request_info *info, 107 struct iw_request_info *info,
108 union iwreq_data *req, char *extra) 108 union iwreq_data *req, char *extra)
109{ 109{
110 int r;
111 struct zd_mac *mac = zd_netdev_mac(netdev); 110 struct zd_mac *mac = zd_netdev_mac(netdev);
112 struct iw_freq *freq = &req->freq; 111 struct iw_freq *freq = &req->freq;
113 u8 channel;
114 u8 flags;
115
116 r = zd_mac_get_channel(mac, &channel, &flags);
117 if (r)
118 return r;
119 112
120 freq->flags = (flags & MAC_FIXED_CHANNEL) ? 113 return zd_channel_to_freq(freq, zd_mac_get_channel(mac));
121 IW_FREQ_FIXED : IW_FREQ_AUTO;
122 dev_dbg_f(zd_mac_dev(mac), "channel %s\n",
123 (flags & MAC_FIXED_CHANNEL) ? "fixed" : "auto");
124 return zd_channel_to_freq(freq, channel);
125} 114}
126 115
127static int iw_set_mode(struct net_device *netdev, 116static int iw_set_mode(struct net_device *netdev,
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.c b/drivers/net/wireless/zd1211rw/zd_usb.c
index 3faaeb2b7c89..aa782e88754b 100644
--- a/drivers/net/wireless/zd1211rw/zd_usb.c
+++ b/drivers/net/wireless/zd1211rw/zd_usb.c
@@ -47,11 +47,17 @@ static struct usb_device_id usb_ids[] = {
47 { USB_DEVICE(0x0586, 0x3402), .driver_info = DEVICE_ZD1211 }, 47 { USB_DEVICE(0x0586, 0x3402), .driver_info = DEVICE_ZD1211 },
48 { USB_DEVICE(0x0b3b, 0x5630), .driver_info = DEVICE_ZD1211 }, 48 { USB_DEVICE(0x0b3b, 0x5630), .driver_info = DEVICE_ZD1211 },
49 { USB_DEVICE(0x0b05, 0x170c), .driver_info = DEVICE_ZD1211 }, 49 { USB_DEVICE(0x0b05, 0x170c), .driver_info = DEVICE_ZD1211 },
50 { USB_DEVICE(0x1435, 0x0711), .driver_info = DEVICE_ZD1211 },
51 { USB_DEVICE(0x0586, 0x3409), .driver_info = DEVICE_ZD1211 },
52 { USB_DEVICE(0x0b3b, 0x1630), .driver_info = DEVICE_ZD1211 },
53 { USB_DEVICE(0x0586, 0x3401), .driver_info = DEVICE_ZD1211 },
54 { USB_DEVICE(0x14ea, 0xab13), .driver_info = DEVICE_ZD1211 },
50 /* ZD1211B */ 55 /* ZD1211B */
51 { USB_DEVICE(0x0ace, 0x1215), .driver_info = DEVICE_ZD1211B }, 56 { USB_DEVICE(0x0ace, 0x1215), .driver_info = DEVICE_ZD1211B },
52 { USB_DEVICE(0x157e, 0x300d), .driver_info = DEVICE_ZD1211B }, 57 { USB_DEVICE(0x157e, 0x300d), .driver_info = DEVICE_ZD1211B },
53 { USB_DEVICE(0x079b, 0x0062), .driver_info = DEVICE_ZD1211B }, 58 { USB_DEVICE(0x079b, 0x0062), .driver_info = DEVICE_ZD1211B },
54 { USB_DEVICE(0x1582, 0x6003), .driver_info = DEVICE_ZD1211B }, 59 { USB_DEVICE(0x1582, 0x6003), .driver_info = DEVICE_ZD1211B },
60 { USB_DEVICE(0x050d, 0x705c), .driver_info = DEVICE_ZD1211B },
55 /* "Driverless" devices that need ejecting */ 61 /* "Driverless" devices that need ejecting */
56 { USB_DEVICE(0x0ace, 0x2011), .driver_info = DEVICE_INSTALLER }, 62 { USB_DEVICE(0x0ace, 0x2011), .driver_info = DEVICE_INSTALLER },
57 {} 63 {}
@@ -366,15 +372,6 @@ error:
366 return r; 372 return r;
367} 373}
368 374
369static void disable_read_regs_int(struct zd_usb *usb)
370{
371 struct zd_usb_interrupt *intr = &usb->intr;
372
373 spin_lock(&intr->lock);
374 intr->read_regs_enabled = 0;
375 spin_unlock(&intr->lock);
376}
377
378#define urb_dev(urb) (&(urb)->dev->dev) 375#define urb_dev(urb) (&(urb)->dev->dev)
379 376
380static inline void handle_regs_int(struct urb *urb) 377static inline void handle_regs_int(struct urb *urb)
@@ -596,6 +593,8 @@ static void handle_rx_packet(struct zd_usb *usb, const u8 *buffer,
596 unsigned int l, k, n; 593 unsigned int l, k, n;
597 for (i = 0, l = 0;; i++) { 594 for (i = 0, l = 0;; i++) {
598 k = le16_to_cpu(get_unaligned(&length_info->length[i])); 595 k = le16_to_cpu(get_unaligned(&length_info->length[i]));
596 if (k == 0)
597 return;
599 n = l+k; 598 n = l+k;
600 if (n > length) 599 if (n > length)
601 return; 600 return;
@@ -1119,27 +1118,28 @@ static int __init usb_init(void)
1119{ 1118{
1120 int r; 1119 int r;
1121 1120
1122 pr_debug("usb_init()\n"); 1121 pr_debug("%s usb_init()\n", driver.name);
1123 1122
1124 zd_workqueue = create_singlethread_workqueue(driver.name); 1123 zd_workqueue = create_singlethread_workqueue(driver.name);
1125 if (zd_workqueue == NULL) { 1124 if (zd_workqueue == NULL) {
1126 printk(KERN_ERR "%s: couldn't create workqueue\n", driver.name); 1125 printk(KERN_ERR "%s couldn't create workqueue\n", driver.name);
1127 return -ENOMEM; 1126 return -ENOMEM;
1128 } 1127 }
1129 1128
1130 r = usb_register(&driver); 1129 r = usb_register(&driver);
1131 if (r) { 1130 if (r) {
1132 printk(KERN_ERR "usb_register() failed. Error number %d\n", r); 1131 printk(KERN_ERR "%s usb_register() failed. Error number %d\n",
1132 driver.name, r);
1133 return r; 1133 return r;
1134 } 1134 }
1135 1135
1136 pr_debug("zd1211rw initialized\n"); 1136 pr_debug("%s initialized\n", driver.name);
1137 return 0; 1137 return 0;
1138} 1138}
1139 1139
1140static void __exit usb_exit(void) 1140static void __exit usb_exit(void)
1141{ 1141{
1142 pr_debug("usb_exit()\n"); 1142 pr_debug("%s usb_exit()\n", driver.name);
1143 usb_deregister(&driver); 1143 usb_deregister(&driver);
1144 destroy_workqueue(zd_workqueue); 1144 destroy_workqueue(zd_workqueue);
1145} 1145}
@@ -1156,10 +1156,19 @@ static void prepare_read_regs_int(struct zd_usb *usb)
1156{ 1156{
1157 struct zd_usb_interrupt *intr = &usb->intr; 1157 struct zd_usb_interrupt *intr = &usb->intr;
1158 1158
1159 spin_lock(&intr->lock); 1159 spin_lock_irq(&intr->lock);
1160 intr->read_regs_enabled = 1; 1160 intr->read_regs_enabled = 1;
1161 INIT_COMPLETION(intr->read_regs.completion); 1161 INIT_COMPLETION(intr->read_regs.completion);
1162 spin_unlock(&intr->lock); 1162 spin_unlock_irq(&intr->lock);
1163}
1164
1165static void disable_read_regs_int(struct zd_usb *usb)
1166{
1167 struct zd_usb_interrupt *intr = &usb->intr;
1168
1169 spin_lock_irq(&intr->lock);
1170 intr->read_regs_enabled = 0;
1171 spin_unlock_irq(&intr->lock);
1163} 1172}
1164 1173
1165static int get_results(struct zd_usb *usb, u16 *values, 1174static int get_results(struct zd_usb *usb, u16 *values,
@@ -1171,7 +1180,7 @@ static int get_results(struct zd_usb *usb, u16 *values,
1171 struct read_regs_int *rr = &intr->read_regs; 1180 struct read_regs_int *rr = &intr->read_regs;
1172 struct usb_int_regs *regs = (struct usb_int_regs *)rr->buffer; 1181 struct usb_int_regs *regs = (struct usb_int_regs *)rr->buffer;
1173 1182
1174 spin_lock(&intr->lock); 1183 spin_lock_irq(&intr->lock);
1175 1184
1176 r = -EIO; 1185 r = -EIO;
1177 /* The created block size seems to be larger than expected. 1186 /* The created block size seems to be larger than expected.
@@ -1204,7 +1213,7 @@ static int get_results(struct zd_usb *usb, u16 *values,
1204 1213
1205 r = 0; 1214 r = 0;
1206error_unlock: 1215error_unlock:
1207 spin_unlock(&intr->lock); 1216 spin_unlock_irq(&intr->lock);
1208 return r; 1217 return r;
1209} 1218}
1210 1219
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.h b/drivers/net/wireless/zd1211rw/zd_usb.h
index e81a2d3cfffd..317d37c36679 100644
--- a/drivers/net/wireless/zd1211rw/zd_usb.h
+++ b/drivers/net/wireless/zd1211rw/zd_usb.h
@@ -74,17 +74,17 @@ enum control_requests {
74struct usb_req_read_regs { 74struct usb_req_read_regs {
75 __le16 id; 75 __le16 id;
76 __le16 addr[0]; 76 __le16 addr[0];
77}; 77} __attribute__((packed));
78 78
79struct reg_data { 79struct reg_data {
80 __le16 addr; 80 __le16 addr;
81 __le16 value; 81 __le16 value;
82}; 82} __attribute__((packed));
83 83
84struct usb_req_write_regs { 84struct usb_req_write_regs {
85 __le16 id; 85 __le16 id;
86 struct reg_data reg_writes[0]; 86 struct reg_data reg_writes[0];
87}; 87} __attribute__((packed));
88 88
89enum { 89enum {
90 RF_IF_LE = 0x02, 90 RF_IF_LE = 0x02,
@@ -101,7 +101,7 @@ struct usb_req_rfwrite {
101 /* RF2595: 24 */ 101 /* RF2595: 24 */
102 __le16 bit_values[0]; 102 __le16 bit_values[0];
103 /* (CR203 & ~(RF_IF_LE | RF_CLK | RF_DATA)) | (bit ? RF_DATA : 0) */ 103 /* (CR203 & ~(RF_IF_LE | RF_CLK | RF_DATA)) | (bit ? RF_DATA : 0) */
104}; 104} __attribute__((packed));
105 105
106/* USB interrupt */ 106/* USB interrupt */
107 107
@@ -118,12 +118,12 @@ enum usb_int_flags {
118struct usb_int_header { 118struct usb_int_header {
119 u8 type; /* must always be 1 */ 119 u8 type; /* must always be 1 */
120 u8 id; 120 u8 id;
121}; 121} __attribute__((packed));
122 122
123struct usb_int_regs { 123struct usb_int_regs {
124 struct usb_int_header hdr; 124 struct usb_int_header hdr;
125 struct reg_data regs[0]; 125 struct reg_data regs[0];
126}; 126} __attribute__((packed));
127 127
128struct usb_int_retry_fail { 128struct usb_int_retry_fail {
129 struct usb_int_header hdr; 129 struct usb_int_header hdr;
@@ -131,7 +131,7 @@ struct usb_int_retry_fail {
131 u8 _dummy; 131 u8 _dummy;
132 u8 addr[ETH_ALEN]; 132 u8 addr[ETH_ALEN];
133 u8 ibss_wakeup_dest; 133 u8 ibss_wakeup_dest;
134}; 134} __attribute__((packed));
135 135
136struct read_regs_int { 136struct read_regs_int {
137 struct completion completion; 137 struct completion completion;
diff --git a/drivers/net/zorro8390.c b/drivers/net/zorro8390.c
index df04e050c647..d85e2ea0b6af 100644
--- a/drivers/net/zorro8390.c
+++ b/drivers/net/zorro8390.c
@@ -34,8 +34,16 @@
34#include <asm/amigaints.h> 34#include <asm/amigaints.h>
35#include <asm/amigahw.h> 35#include <asm/amigahw.h>
36 36
37#include "8390.h" 37#define EI_SHIFT(x) (ei_local->reg_offset[x])
38#define ei_inb(port) in_8(port)
39#define ei_outb(val,port) out_8(port,val)
40#define ei_inb_p(port) in_8(port)
41#define ei_outb_p(val,port) out_8(port,val)
38 42
43static const char version[] =
44 "8390.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
45
46#include "lib8390.c"
39 47
40#define DRV_NAME "zorro8390" 48#define DRV_NAME "zorro8390"
41 49
@@ -114,7 +122,7 @@ static int __devinit zorro8390_init_one(struct zorro_dev *z,
114 break; 122 break;
115 board = z->resource.start; 123 board = z->resource.start;
116 ioaddr = board+cards[i].offset; 124 ioaddr = board+cards[i].offset;
117 dev = alloc_ei_netdev(); 125 dev = ____alloc_ei_netdev(0);
118 if (!dev) 126 if (!dev)
119 return -ENOMEM; 127 return -ENOMEM;
120 SET_MODULE_OWNER(dev); 128 SET_MODULE_OWNER(dev);
@@ -201,7 +209,7 @@ static int __devinit zorro8390_init(struct net_device *dev,
201 dev->irq = IRQ_AMIGA_PORTS; 209 dev->irq = IRQ_AMIGA_PORTS;
202 210
203 /* Install the Interrupt handler */ 211 /* Install the Interrupt handler */
204 i = request_irq(IRQ_AMIGA_PORTS, ei_interrupt, IRQF_SHARED, DRV_NAME, dev); 212 i = request_irq(IRQ_AMIGA_PORTS, __ei_interrupt, IRQF_SHARED, DRV_NAME, dev);
205 if (i) return i; 213 if (i) return i;
206 214
207 for(i = 0; i < ETHER_ADDR_LEN; i++) { 215 for(i = 0; i < ETHER_ADDR_LEN; i++) {
@@ -226,10 +234,10 @@ static int __devinit zorro8390_init(struct net_device *dev,
226 dev->open = &zorro8390_open; 234 dev->open = &zorro8390_open;
227 dev->stop = &zorro8390_close; 235 dev->stop = &zorro8390_close;
228#ifdef CONFIG_NET_POLL_CONTROLLER 236#ifdef CONFIG_NET_POLL_CONTROLLER
229 dev->poll_controller = ei_poll; 237 dev->poll_controller = __ei_poll;
230#endif 238#endif
231 239
232 NS8390_init(dev, 0); 240 __NS8390_init(dev, 0);
233 err = register_netdev(dev); 241 err = register_netdev(dev);
234 if (err) { 242 if (err) {
235 free_irq(IRQ_AMIGA_PORTS, dev); 243 free_irq(IRQ_AMIGA_PORTS, dev);
@@ -246,7 +254,7 @@ static int __devinit zorro8390_init(struct net_device *dev,
246 254
247static int zorro8390_open(struct net_device *dev) 255static int zorro8390_open(struct net_device *dev)
248{ 256{
249 ei_open(dev); 257 __ei_open(dev);
250 return 0; 258 return 0;
251} 259}
252 260
@@ -254,7 +262,7 @@ static int zorro8390_close(struct net_device *dev)
254{ 262{
255 if (ei_debug > 1) 263 if (ei_debug > 1)
256 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name); 264 printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name);
257 ei_close(dev); 265 __ei_close(dev);
258 return 0; 266 return 0;
259} 267}
260 268
@@ -405,7 +413,7 @@ static void zorro8390_block_output(struct net_device *dev, int count,
405 printk(KERN_ERR "%s: timeout waiting for Tx RDC.\n", 413 printk(KERN_ERR "%s: timeout waiting for Tx RDC.\n",
406 dev->name); 414 dev->name);
407 zorro8390_reset_8390(dev); 415 zorro8390_reset_8390(dev);
408 NS8390_init(dev,1); 416 __NS8390_init(dev,1);
409 break; 417 break;
410 } 418 }
411 419
diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c
index 68cb3a080050..fe3f5f5365c5 100644
--- a/drivers/parisc/ccio-dma.c
+++ b/drivers/parisc/ccio-dma.c
@@ -486,7 +486,7 @@ typedef unsigned long space_t;
486** This bit tells U2 to do R/M/W for partial cachelines. "Streaming" 486** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
487** data can avoid this if the mapping covers full cache lines. 487** data can avoid this if the mapping covers full cache lines.
488** o STOP_MOST is needed for atomicity across cachelines. 488** o STOP_MOST is needed for atomicity across cachelines.
489** Apperently only "some EISA devices" need this. 489** Apparently only "some EISA devices" need this.
490** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs 490** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
491** to use this hint iff the EISA devices needs this feature. 491** to use this hint iff the EISA devices needs this feature.
492** According to the U2 ERS, STOP_MOST enabled pages hurt performance. 492** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c
index c2949b4367e5..12bab64a62a1 100644
--- a/drivers/parisc/iosapic.c
+++ b/drivers/parisc/iosapic.c
@@ -50,12 +50,12 @@
50** 50**
51** PA Firmware 51** PA Firmware
52** ----------- 52** -----------
53** PA-RISC platforms have two fundementally different types of firmware. 53** PA-RISC platforms have two fundamentally different types of firmware.
54** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register 54** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
55** and BARs similar to a traditional PC BIOS. 55** and BARs similar to a traditional PC BIOS.
56** The newer "PAT" firmware supports PDC calls which return tables. 56** The newer "PAT" firmware supports PDC calls which return tables.
57** PAT firmware only initializes PCI Console and Boot interface. 57** PAT firmware only initializes the PCI Console and Boot interface.
58** With these tables, the OS can progam all other PCI devices. 58** With these tables, the OS can program all other PCI devices.
59** 59**
60** One such PAT PDC call returns the "Interrupt Routing Table" (IRT). 60** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
61** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC 61** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 5f1b9f58070e..f1dd81a1d592 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -19,7 +19,7 @@ config PCI_MSI
19 19
20config PCI_MULTITHREAD_PROBE 20config PCI_MULTITHREAD_PROBE
21 bool "PCI Multi-threaded probe (EXPERIMENTAL)" 21 bool "PCI Multi-threaded probe (EXPERIMENTAL)"
22 depends on PCI && EXPERIMENTAL && BROKEN 22 depends on PCI && EXPERIMENTAL
23 help 23 help
24 Say Y here if you want the PCI core to spawn a new thread for 24 Say Y here if you want the PCI core to spawn a new thread for
25 every PCI device that is probed. This can cause a huge 25 every PCI device that is probed. This can cause a huge
@@ -27,14 +27,14 @@ config PCI_MULTITHREAD_PROBE
27 smaller speedup on single processor machines. 27 smaller speedup on single processor machines.
28 28
29 But it can also cause lots of bad things to happen. A number 29 But it can also cause lots of bad things to happen. A number
30 of PCI drivers can not properly handle running in this way, 30 of PCI drivers cannot properly handle running in this way,
31 some will just not work properly at all, while others might 31 some will just not work properly at all, while others might
32 decide to blow up power supplies with a huge load all at once, 32 decide to blow up power supplies with a huge load all at once,
33 so use this option at your own risk. 33 so use this option at your own risk.
34 34
35 It is very unwise to use this option if you are not using a 35 It is very unwise to use this option if you are not using a
36 boot process that can handle devices being created in any 36 boot process that can handle devices being created in any
37 order. A program that can create persistant block and network 37 order. A program that can create persistent block and network
38 device names (like udev) is a good idea if you wish to use 38 device names (like udev) is a good idea if you wish to use
39 this option. 39 this option.
40 40
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index ea16805a153c..73a58c73d526 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -1,6 +1,7 @@
1#include <linux/pci.h> 1#include <linux/pci.h>
2#include <linux/module.h> 2#include <linux/module.h>
3#include <linux/ioport.h> 3#include <linux/ioport.h>
4#include <linux/wait.h>
4 5
5#include "pci.h" 6#include "pci.h"
6 7
@@ -63,30 +64,42 @@ EXPORT_SYMBOL(pci_bus_write_config_byte);
63EXPORT_SYMBOL(pci_bus_write_config_word); 64EXPORT_SYMBOL(pci_bus_write_config_word);
64EXPORT_SYMBOL(pci_bus_write_config_dword); 65EXPORT_SYMBOL(pci_bus_write_config_dword);
65 66
66static u32 pci_user_cached_config(struct pci_dev *dev, int pos) 67/*
67{ 68 * The following routines are to prevent the user from accessing PCI config
68 u32 data; 69 * space when it's unsafe to do so. Some devices require this during BIST and
70 * we're required to prevent it during D-state transitions.
71 *
72 * We have a bit per device to indicate it's blocked and a global wait queue
73 * for callers to sleep on until devices are unblocked.
74 */
75static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
69 76
70 data = dev->saved_config_space[pos/sizeof(dev->saved_config_space[0])]; 77static noinline void pci_wait_ucfg(struct pci_dev *dev)
71 data >>= (pos % sizeof(dev->saved_config_space[0])) * 8; 78{
72 return data; 79 DECLARE_WAITQUEUE(wait, current);
80
81 __add_wait_queue(&pci_ucfg_wait, &wait);
82 do {
83 set_current_state(TASK_UNINTERRUPTIBLE);
84 spin_unlock_irq(&pci_lock);
85 schedule();
86 spin_lock_irq(&pci_lock);
87 } while (dev->block_ucfg_access);
88 __remove_wait_queue(&pci_ucfg_wait, &wait);
73} 89}
74 90
75#define PCI_USER_READ_CONFIG(size,type) \ 91#define PCI_USER_READ_CONFIG(size,type) \
76int pci_user_read_config_##size \ 92int pci_user_read_config_##size \
77 (struct pci_dev *dev, int pos, type *val) \ 93 (struct pci_dev *dev, int pos, type *val) \
78{ \ 94{ \
79 unsigned long flags; \
80 int ret = 0; \ 95 int ret = 0; \
81 u32 data = -1; \ 96 u32 data = -1; \
82 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 97 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
83 spin_lock_irqsave(&pci_lock, flags); \ 98 spin_lock_irq(&pci_lock); \
84 if (likely(!dev->block_ucfg_access)) \ 99 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
85 ret = dev->bus->ops->read(dev->bus, dev->devfn, \ 100 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
86 pos, sizeof(type), &data); \ 101 pos, sizeof(type), &data); \
87 else if (pos < sizeof(dev->saved_config_space)) \ 102 spin_unlock_irq(&pci_lock); \
88 data = pci_user_cached_config(dev, pos); \
89 spin_unlock_irqrestore(&pci_lock, flags); \
90 *val = (type)data; \ 103 *val = (type)data; \
91 return ret; \ 104 return ret; \
92} 105}
@@ -95,14 +108,13 @@ int pci_user_read_config_##size \
95int pci_user_write_config_##size \ 108int pci_user_write_config_##size \
96 (struct pci_dev *dev, int pos, type val) \ 109 (struct pci_dev *dev, int pos, type val) \
97{ \ 110{ \
98 unsigned long flags; \
99 int ret = -EIO; \ 111 int ret = -EIO; \
100 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 112 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
101 spin_lock_irqsave(&pci_lock, flags); \ 113 spin_lock_irq(&pci_lock); \
102 if (likely(!dev->block_ucfg_access)) \ 114 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
103 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 115 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
104 pos, sizeof(type), val); \ 116 pos, sizeof(type), val); \
105 spin_unlock_irqrestore(&pci_lock, flags); \ 117 spin_unlock_irq(&pci_lock); \
106 return ret; \ 118 return ret; \
107} 119}
108 120
@@ -117,21 +129,23 @@ PCI_USER_WRITE_CONFIG(dword, u32)
117 * pci_block_user_cfg_access - Block userspace PCI config reads/writes 129 * pci_block_user_cfg_access - Block userspace PCI config reads/writes
118 * @dev: pci device struct 130 * @dev: pci device struct
119 * 131 *
120 * This function blocks any userspace PCI config accesses from occurring. 132 * When user access is blocked, any reads or writes to config space will
121 * When blocked, any writes will be bit bucketed and reads will return the 133 * sleep until access is unblocked again. We don't allow nesting of
122 * data saved using pci_save_state for the first 64 bytes of config 134 * block/unblock calls.
123 * space and return 0xff for all other config reads. 135 */
124 **/
125void pci_block_user_cfg_access(struct pci_dev *dev) 136void pci_block_user_cfg_access(struct pci_dev *dev)
126{ 137{
127 unsigned long flags; 138 unsigned long flags;
139 int was_blocked;
128 140
129 pci_save_state(dev);
130
131 /* spinlock to synchronize with anyone reading config space now */
132 spin_lock_irqsave(&pci_lock, flags); 141 spin_lock_irqsave(&pci_lock, flags);
142 was_blocked = dev->block_ucfg_access;
133 dev->block_ucfg_access = 1; 143 dev->block_ucfg_access = 1;
134 spin_unlock_irqrestore(&pci_lock, flags); 144 spin_unlock_irqrestore(&pci_lock, flags);
145
146 /* If we BUG() inside the pci_lock, we're guaranteed to hose
147 * the machine */
148 BUG_ON(was_blocked);
135} 149}
136EXPORT_SYMBOL_GPL(pci_block_user_cfg_access); 150EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
137 151
@@ -140,14 +154,19 @@ EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
140 * @dev: pci device struct 154 * @dev: pci device struct
141 * 155 *
142 * This function allows userspace PCI config accesses to resume. 156 * This function allows userspace PCI config accesses to resume.
143 **/ 157 */
144void pci_unblock_user_cfg_access(struct pci_dev *dev) 158void pci_unblock_user_cfg_access(struct pci_dev *dev)
145{ 159{
146 unsigned long flags; 160 unsigned long flags;
147 161
148 /* spinlock to synchronize with anyone reading saved config space */
149 spin_lock_irqsave(&pci_lock, flags); 162 spin_lock_irqsave(&pci_lock, flags);
163
164 /* This indicates a problem in the caller, but we don't need
165 * to kill them, unlike a double-block above. */
166 WARN_ON(!dev->block_ucfg_access);
167
150 dev->block_ucfg_access = 0; 168 dev->block_ucfg_access = 0;
169 wake_up_all(&pci_ucfg_wait);
151 spin_unlock_irqrestore(&pci_lock, flags); 170 spin_unlock_irqrestore(&pci_lock, flags);
152} 171}
153EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access); 172EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h
index 59c5b242d86d..ddbadd95387e 100644
--- a/drivers/pci/hotplug/acpiphp.h
+++ b/drivers/pci/hotplug/acpiphp.h
@@ -62,10 +62,10 @@ struct acpiphp_slot;
62struct slot { 62struct slot {
63 struct hotplug_slot *hotplug_slot; 63 struct hotplug_slot *hotplug_slot;
64 struct acpiphp_slot *acpi_slot; 64 struct acpiphp_slot *acpi_slot;
65 struct hotplug_slot_info info;
66 char name[SLOT_NAME_SIZE];
65}; 67};
66 68
67
68
69/** 69/**
70 * struct acpiphp_bridge - PCI bridge information 70 * struct acpiphp_bridge - PCI bridge information
71 * 71 *
diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c
index c57d9d5ce84e..40c79b03c7ef 100644
--- a/drivers/pci/hotplug/acpiphp_core.c
+++ b/drivers/pci/hotplug/acpiphp_core.c
@@ -303,25 +303,15 @@ static int __init init_acpi(void)
303 /* read initial number of slots */ 303 /* read initial number of slots */
304 if (!retval) { 304 if (!retval) {
305 num_slots = acpiphp_get_num_slots(); 305 num_slots = acpiphp_get_num_slots();
306 if (num_slots == 0) 306 if (num_slots == 0) {
307 acpiphp_glue_exit();
307 retval = -ENODEV; 308 retval = -ENODEV;
309 }
308 } 310 }
309 311
310 return retval; 312 return retval;
311} 313}
312 314
313
314/**
315 * make_slot_name - make a slot name that appears in pcihpfs
316 * @slot: slot to name
317 *
318 */
319static void make_slot_name(struct slot *slot)
320{
321 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%u",
322 slot->acpi_slot->sun);
323}
324
325/** 315/**
326 * release_slot - free up the memory used by a slot 316 * release_slot - free up the memory used by a slot
327 * @hotplug_slot: slot to free 317 * @hotplug_slot: slot to free
@@ -332,8 +322,6 @@ static void release_slot(struct hotplug_slot *hotplug_slot)
332 322
333 dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name); 323 dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
334 324
335 kfree(slot->hotplug_slot->info);
336 kfree(slot->hotplug_slot->name);
337 kfree(slot->hotplug_slot); 325 kfree(slot->hotplug_slot);
338 kfree(slot); 326 kfree(slot);
339} 327}
@@ -342,26 +330,19 @@ static void release_slot(struct hotplug_slot *hotplug_slot)
342int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot) 330int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot)
343{ 331{
344 struct slot *slot; 332 struct slot *slot;
345 struct hotplug_slot *hotplug_slot;
346 struct hotplug_slot_info *hotplug_slot_info;
347 int retval = -ENOMEM; 333 int retval = -ENOMEM;
348 334
349 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 335 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
350 if (!slot) 336 if (!slot)
351 goto error; 337 goto error;
352 338
353 slot->hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL); 339 slot->hotplug_slot = kzalloc(sizeof(*slot->hotplug_slot), GFP_KERNEL);
354 if (!slot->hotplug_slot) 340 if (!slot->hotplug_slot)
355 goto error_slot; 341 goto error_slot;
356 342
357 slot->hotplug_slot->info = kzalloc(sizeof(*hotplug_slot_info), 343 slot->hotplug_slot->info = &slot->info;
358 GFP_KERNEL);
359 if (!slot->hotplug_slot->info)
360 goto error_hpslot;
361 344
362 slot->hotplug_slot->name = kzalloc(SLOT_NAME_SIZE, GFP_KERNEL); 345 slot->hotplug_slot->name = slot->name;
363 if (!slot->hotplug_slot->name)
364 goto error_info;
365 346
366 slot->hotplug_slot->private = slot; 347 slot->hotplug_slot->private = slot;
367 slot->hotplug_slot->release = &release_slot; 348 slot->hotplug_slot->release = &release_slot;
@@ -376,21 +357,17 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot)
376 slot->hotplug_slot->info->cur_bus_speed = PCI_SPEED_UNKNOWN; 357 slot->hotplug_slot->info->cur_bus_speed = PCI_SPEED_UNKNOWN;
377 358
378 acpiphp_slot->slot = slot; 359 acpiphp_slot->slot = slot;
379 make_slot_name(slot); 360 snprintf(slot->name, sizeof(slot->name), "%u", slot->acpi_slot->sun);
380 361
381 retval = pci_hp_register(slot->hotplug_slot); 362 retval = pci_hp_register(slot->hotplug_slot);
382 if (retval) { 363 if (retval) {
383 err("pci_hp_register failed with error %d\n", retval); 364 err("pci_hp_register failed with error %d\n", retval);
384 goto error_name; 365 goto error_hpslot;
385 } 366 }
386 367
387 info("Slot [%s] registered\n", slot->hotplug_slot->name); 368 info("Slot [%s] registered\n", slot->hotplug_slot->name);
388 369
389 return 0; 370 return 0;
390error_name:
391 kfree(slot->hotplug_slot->name);
392error_info:
393 kfree(slot->hotplug_slot->info);
394error_hpslot: 371error_hpslot:
395 kfree(slot->hotplug_slot); 372 kfree(slot->hotplug_slot);
396error_slot: 373error_slot:
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 16167b016266..0b9d0db1590a 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -1693,14 +1693,10 @@ void __exit acpiphp_glue_exit(void)
1693 */ 1693 */
1694int __init acpiphp_get_num_slots(void) 1694int __init acpiphp_get_num_slots(void)
1695{ 1695{
1696 struct list_head *node;
1697 struct acpiphp_bridge *bridge; 1696 struct acpiphp_bridge *bridge;
1698 int num_slots; 1697 int num_slots = 0;
1699
1700 num_slots = 0;
1701 1698
1702 list_for_each (node, &bridge_list) { 1699 list_for_each_entry (bridge, &bridge_list, list) {
1703 bridge = (struct acpiphp_bridge *)node;
1704 dbg("Bus %04x:%02x has %d slot%s\n", 1700 dbg("Bus %04x:%02x has %d slot%s\n",
1705 pci_domain_nr(bridge->pci_bus), 1701 pci_domain_nr(bridge->pci_bus),
1706 bridge->pci_bus->number, bridge->nr_slots, 1702 bridge->pci_bus->number, bridge->nr_slots,
diff --git a/drivers/pci/hotplug/ibmphp_hpc.c b/drivers/pci/hotplug/ibmphp_hpc.c
index c3ac98a0a6a6..f55ac3885cb3 100644
--- a/drivers/pci/hotplug/ibmphp_hpc.c
+++ b/drivers/pci/hotplug/ibmphp_hpc.c
@@ -531,7 +531,7 @@ static u8 hpc_readcmdtoindex (u8 cmd, u8 index)
531* 531*
532* Action: issue a READ command to HPC 532* Action: issue a READ command to HPC
533* 533*
534* Input: pslot - can not be NULL for READ_ALLSTAT 534* Input: pslot - cannot be NULL for READ_ALLSTAT
535* pstatus - can be NULL for READ_ALLSTAT 535* pstatus - can be NULL for READ_ALLSTAT
536* 536*
537* Return 0 or error codes 537* Return 0 or error codes
diff --git a/drivers/pci/hotplug/ibmphp_pci.c b/drivers/pci/hotplug/ibmphp_pci.c
index d87a9e3eaeeb..d8f05d7a3c72 100644
--- a/drivers/pci/hotplug/ibmphp_pci.c
+++ b/drivers/pci/hotplug/ibmphp_pci.c
@@ -1371,12 +1371,12 @@ static int unconfigure_boot_bridge (u8 busno, u8 device, u8 function)
1371 } 1371 }
1372 1372
1373 bus = ibmphp_find_res_bus (sec_number); 1373 bus = ibmphp_find_res_bus (sec_number);
1374 debug ("bus->busno is %x\n", bus->busno);
1375 debug ("sec_number is %x\n", sec_number);
1376 if (!bus) { 1374 if (!bus) {
1377 err ("cannot find Bus structure for the bridged device\n"); 1375 err ("cannot find Bus structure for the bridged device\n");
1378 return -EINVAL; 1376 return -EINVAL;
1379 } 1377 }
1378 debug("bus->busno is %x\n", bus->busno);
1379 debug("sec_number is %x\n", sec_number);
1380 1380
1381 ibmphp_remove_bus (bus, busno); 1381 ibmphp_remove_bus (bus, busno);
1382 1382
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index f93e81e2d2c7..f13f31323e85 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -521,14 +521,9 @@ static void __exit unload_pciehpd(void)
521 521
522} 522}
523 523
524static int hpdriver_context = 0;
525
526static void pciehp_remove (struct pcie_device *device) 524static void pciehp_remove (struct pcie_device *device)
527{ 525{
528 printk("%s ENTRY\n", __FUNCTION__); 526 /* XXX - Needs to be adapted to device driver model */
529 printk("%s -> Call free_irq for irq = %d\n",
530 __FUNCTION__, device->irq);
531 free_irq(device->irq, &hpdriver_context);
532} 527}
533 528
534#ifdef CONFIG_PM 529#ifdef CONFIG_PM
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 1c551c697c35..6d3f580f2666 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -718,8 +718,6 @@ static void hpc_release_ctlr(struct controller *ctrl)
718 if (php_ctlr->irq) { 718 if (php_ctlr->irq) {
719 free_irq(php_ctlr->irq, ctrl); 719 free_irq(php_ctlr->irq, ctrl);
720 php_ctlr->irq = 0; 720 php_ctlr->irq = 0;
721 if (!pcie_mch_quirk)
722 pci_disable_msi(php_ctlr->pci_dev);
723 } 721 }
724 } 722 }
725 if (php_ctlr->pci_dev) 723 if (php_ctlr->pci_dev)
diff --git a/drivers/pci/hotplug/rpadlpar_core.c b/drivers/pci/hotplug/rpadlpar_core.c
index 46825fee3ae4..72383467a0d5 100644
--- a/drivers/pci/hotplug/rpadlpar_core.c
+++ b/drivers/pci/hotplug/rpadlpar_core.c
@@ -63,7 +63,7 @@ static struct device_node *find_php_slot_pci_node(char *drc_name,
63 char *type; 63 char *type;
64 int rc; 64 int rc;
65 65
66 while ((np = of_find_node_by_type(np, "pci"))) { 66 while ((np = of_find_node_by_name(np, "pci"))) {
67 rc = rpaphp_get_drc_props(np, NULL, &name, &type, NULL); 67 rc = rpaphp_get_drc_props(np, NULL, &name, &type, NULL);
68 if (rc == 0) 68 if (rc == 0)
69 if (!strcmp(drc_name, name) && !strcmp(drc_type, type)) 69 if (!strcmp(drc_name, name) && !strcmp(drc_type, type))
diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
index 141486df235b..71a2cb8baa4a 100644
--- a/drivers/pci/hotplug/rpaphp_core.c
+++ b/drivers/pci/hotplug/rpaphp_core.c
@@ -356,7 +356,7 @@ static int __init rpaphp_init(void)
356 info(DRIVER_DESC " version: " DRIVER_VERSION "\n"); 356 info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
357 init_MUTEX(&rpaphp_sem); 357 init_MUTEX(&rpaphp_sem);
358 358
359 while ((dn = of_find_node_by_type(dn, "pci"))) 359 while ((dn = of_find_node_by_name(dn, "pci")))
360 rpaphp_add_slot(dn); 360 rpaphp_add_slot(dn);
361 361
362 return 0; 362 return 0;
diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c
index b62ad31a9739..5d188c558386 100644
--- a/drivers/pci/hotplug/sgi_hotplug.c
+++ b/drivers/pci/hotplug/sgi_hotplug.c
@@ -205,21 +205,6 @@ static struct hotplug_slot * sn_hp_destroy(void)
205 return bss_hotplug_slot; 205 return bss_hotplug_slot;
206} 206}
207 207
208static void sn_bus_alloc_data(struct pci_dev *dev)
209{
210 struct pci_bus *subordinate_bus;
211 struct pci_dev *child;
212
213 sn_pci_fixup_slot(dev);
214
215 /* Recursively sets up the sn_irq_info structs */
216 if (dev->subordinate) {
217 subordinate_bus = dev->subordinate;
218 list_for_each_entry(child, &subordinate_bus->devices, bus_list)
219 sn_bus_alloc_data(child);
220 }
221}
222
223static void sn_bus_free_data(struct pci_dev *dev) 208static void sn_bus_free_data(struct pci_dev *dev)
224{ 209{
225 struct pci_bus *subordinate_bus; 210 struct pci_bus *subordinate_bus;
@@ -337,6 +322,11 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
337 return rc; 322 return rc;
338} 323}
339 324
325/*
326 * Power up and configure the slot via a SAL call to PROM.
327 * Scan slot (and any children), do any platform specific fixup,
328 * and find device driver.
329 */
340static int enable_slot(struct hotplug_slot *bss_hotplug_slot) 330static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
341{ 331{
342 struct slot *slot = bss_hotplug_slot->private; 332 struct slot *slot = bss_hotplug_slot->private;
@@ -345,6 +335,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
345 int func, num_funcs; 335 int func, num_funcs;
346 int new_ppb = 0; 336 int new_ppb = 0;
347 int rc; 337 int rc;
338 void pcibios_fixup_device_resources(struct pci_dev *);
348 339
349 /* Serialize the Linux PCI infrastructure */ 340 /* Serialize the Linux PCI infrastructure */
350 mutex_lock(&sn_hotplug_mutex); 341 mutex_lock(&sn_hotplug_mutex);
@@ -367,9 +358,6 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
367 return -ENODEV; 358 return -ENODEV;
368 } 359 }
369 360
370 sn_pci_controller_fixup(pci_domain_nr(slot->pci_bus),
371 slot->pci_bus->number,
372 slot->pci_bus);
373 /* 361 /*
374 * Map SN resources for all functions on the card 362 * Map SN resources for all functions on the card
375 * to the Linux PCI interface and tell the drivers 363 * to the Linux PCI interface and tell the drivers
@@ -380,6 +368,13 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
380 PCI_DEVFN(slot->device_num + 1, 368 PCI_DEVFN(slot->device_num + 1,
381 PCI_FUNC(func))); 369 PCI_FUNC(func)));
382 if (dev) { 370 if (dev) {
371 /* Need to do slot fixup on PPB before fixup of children
372 * (PPB's pcidev_info needs to be in pcidev_info list
373 * before child's SN_PCIDEV_INFO() call to setup
374 * pdi_host_pcidev_info).
375 */
376 pcibios_fixup_device_resources(dev);
377 sn_pci_fixup_slot(dev);
383 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 378 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
384 unsigned char sec_bus; 379 unsigned char sec_bus;
385 pci_read_config_byte(dev, PCI_SECONDARY_BUS, 380 pci_read_config_byte(dev, PCI_SECONDARY_BUS,
@@ -387,12 +382,8 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
387 new_bus = pci_add_new_bus(dev->bus, dev, 382 new_bus = pci_add_new_bus(dev->bus, dev,
388 sec_bus); 383 sec_bus);
389 pci_scan_child_bus(new_bus); 384 pci_scan_child_bus(new_bus);
390 sn_pci_controller_fixup(pci_domain_nr(new_bus),
391 new_bus->number,
392 new_bus);
393 new_ppb = 1; 385 new_ppb = 1;
394 } 386 }
395 sn_bus_alloc_data(dev);
396 pci_dev_put(dev); 387 pci_dev_put(dev);
397 } 388 }
398 } 389 }
diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h
index f0cca1772f9c..3898f5237144 100644
--- a/drivers/pci/msi.h
+++ b/drivers/pci/msi.h
@@ -6,14 +6,6 @@
6#ifndef MSI_H 6#ifndef MSI_H
7#define MSI_H 7#define MSI_H
8 8
9/*
10 * MSI-X Address Register
11 */
12#define PCI_MSIX_FLAGS_QSIZE 0x7FF
13#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
14#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
15#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
16
17#define PCI_MSIX_ENTRY_SIZE 16 9#define PCI_MSIX_ENTRY_SIZE 16
18#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0 10#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
19#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4 11#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index bb7456c1dbac..a064f36a0805 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -36,6 +36,7 @@ acpi_query_osc (
36 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; 36 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
37 union acpi_object *out_obj; 37 union acpi_object *out_obj;
38 u32 osc_dw0; 38 u32 osc_dw0;
39 acpi_status *ret_status = (acpi_status *)retval;
39 40
40 41
41 /* Setting up input parameters */ 42 /* Setting up input parameters */
@@ -56,6 +57,7 @@ acpi_query_osc (
56 if (ACPI_FAILURE (status)) { 57 if (ACPI_FAILURE (status)) {
57 printk(KERN_DEBUG 58 printk(KERN_DEBUG
58 "Evaluate _OSC Set fails. Status = 0x%04x\n", status); 59 "Evaluate _OSC Set fails. Status = 0x%04x\n", status);
60 *ret_status = status;
59 return status; 61 return status;
60 } 62 }
61 out_obj = output.pointer; 63 out_obj = output.pointer;
@@ -90,6 +92,7 @@ acpi_query_osc (
90 92
91query_osc_out: 93query_osc_out:
92 kfree(output.pointer); 94 kfree(output.pointer);
95 *ret_status = status;
93 return status; 96 return status;
94} 97}
95 98
@@ -166,6 +169,7 @@ run_osc_out:
166acpi_status pci_osc_support_set(u32 flags) 169acpi_status pci_osc_support_set(u32 flags)
167{ 170{
168 u32 temp; 171 u32 temp;
172 acpi_status retval;
169 173
170 if (!(flags & OSC_SUPPORT_MASKS)) { 174 if (!(flags & OSC_SUPPORT_MASKS)) {
171 return AE_TYPE; 175 return AE_TYPE;
@@ -179,9 +183,13 @@ acpi_status pci_osc_support_set(u32 flags)
179 acpi_get_devices ( PCI_ROOT_HID_STRING, 183 acpi_get_devices ( PCI_ROOT_HID_STRING,
180 acpi_query_osc, 184 acpi_query_osc,
181 ctrlset_buf, 185 ctrlset_buf,
182 NULL ); 186 (void **) &retval );
183 ctrlset_buf[OSC_QUERY_TYPE] = !OSC_QUERY_ENABLE; 187 ctrlset_buf[OSC_QUERY_TYPE] = !OSC_QUERY_ENABLE;
184 ctrlset_buf[OSC_CONTROL_TYPE] = temp; 188 ctrlset_buf[OSC_CONTROL_TYPE] = temp;
189 if (ACPI_FAILURE(retval)) {
190 /* no osc support at all */
191 ctrlset_buf[OSC_SUPPORT_TYPE] = 0;
192 }
185 return AE_OK; 193 return AE_OK;
186} 194}
187EXPORT_SYMBOL(pci_osc_support_set); 195EXPORT_SYMBOL(pci_osc_support_set);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 194f1d21d3d7..e5ae3a0c13bb 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -329,8 +329,8 @@ static int pci_default_resume(struct pci_dev *pci_dev)
329 /* restore the PCI config space */ 329 /* restore the PCI config space */
330 pci_restore_state(pci_dev); 330 pci_restore_state(pci_dev);
331 /* if the device was enabled before suspend, reenable */ 331 /* if the device was enabled before suspend, reenable */
332 if (pci_dev->is_enabled) 332 if (atomic_read(&pci_dev->enable_cnt))
333 retval = pci_enable_device(pci_dev); 333 retval = __pci_enable_device(pci_dev);
334 /* if the device was busmaster before the suspend, make it busmaster again */ 334 /* if the device was busmaster before the suspend, make it busmaster again */
335 if (pci_dev->is_busmaster) 335 if (pci_dev->is_busmaster)
336 pci_set_master(pci_dev); 336 pci_set_master(pci_dev);
@@ -445,9 +445,12 @@ int __pci_register_driver(struct pci_driver *drv, struct module *owner)
445 445
446 /* register with core */ 446 /* register with core */
447 error = driver_register(&drv->driver); 447 error = driver_register(&drv->driver);
448 if (error)
449 return error;
448 450
449 if (!error) 451 error = pci_create_newid_file(drv);
450 error = pci_create_newid_file(drv); 452 if (error)
453 driver_unregister(&drv->driver);
451 454
452 return error; 455 return error;
453} 456}
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index f952bfea48a6..7a94076752d0 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -42,7 +42,6 @@ pci_config_attr(subsystem_vendor, "0x%04x\n");
42pci_config_attr(subsystem_device, "0x%04x\n"); 42pci_config_attr(subsystem_device, "0x%04x\n");
43pci_config_attr(class, "0x%06x\n"); 43pci_config_attr(class, "0x%06x\n");
44pci_config_attr(irq, "%u\n"); 44pci_config_attr(irq, "%u\n");
45pci_config_attr(is_enabled, "%u\n");
46 45
47static ssize_t broken_parity_status_show(struct device *dev, 46static ssize_t broken_parity_status_show(struct device *dev,
48 struct device_attribute *attr, 47 struct device_attribute *attr,
@@ -112,26 +111,36 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
112 (u8)(pci_dev->class >> 16), (u8)(pci_dev->class >> 8), 111 (u8)(pci_dev->class >> 16), (u8)(pci_dev->class >> 8),
113 (u8)(pci_dev->class)); 112 (u8)(pci_dev->class));
114} 113}
115static ssize_t 114
116is_enabled_store(struct device *dev, struct device_attribute *attr, 115static ssize_t is_enabled_store(struct device *dev,
117 const char *buf, size_t count) 116 struct device_attribute *attr, const char *buf,
117 size_t count)
118{ 118{
119 ssize_t result = -EINVAL;
119 struct pci_dev *pdev = to_pci_dev(dev); 120 struct pci_dev *pdev = to_pci_dev(dev);
120 int retval = 0;
121 121
122 /* this can crash the machine when done on the "wrong" device */ 122 /* this can crash the machine when done on the "wrong" device */
123 if (!capable(CAP_SYS_ADMIN)) 123 if (!capable(CAP_SYS_ADMIN))
124 return count; 124 return count;
125 125
126 if (*buf == '0') 126 if (*buf == '0') {
127 pci_disable_device(pdev); 127 if (atomic_read(&pdev->enable_cnt) != 0)
128 pci_disable_device(pdev);
129 else
130 result = -EIO;
131 } else if (*buf == '1')
132 result = pci_enable_device(pdev);
133
134 return result < 0 ? result : count;
135}
128 136
129 if (*buf == '1') 137static ssize_t is_enabled_show(struct device *dev,
130 retval = pci_enable_device(pdev); 138 struct device_attribute *attr, char *buf)
139{
140 struct pci_dev *pdev;
131 141
132 if (retval) 142 pdev = to_pci_dev (dev);
133 return retval; 143 return sprintf (buf, "%u\n", atomic_read(&pdev->enable_cnt));
134 return count;
135} 144}
136 145
137static ssize_t 146static ssize_t
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index a544997399b3..5a14b73cf3a1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -490,6 +490,47 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
490 kfree(save_state); 490 kfree(save_state);
491} 491}
492 492
493
494static int pci_save_pcix_state(struct pci_dev *dev)
495{
496 int pos, i = 0;
497 struct pci_cap_saved_state *save_state;
498 u16 *cap;
499
500 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
501 if (pos <= 0)
502 return 0;
503
504 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
505 if (!save_state) {
506 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
507 return -ENOMEM;
508 }
509 cap = (u16 *)&save_state->data[0];
510
511 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
512 pci_add_saved_cap(dev, save_state);
513 return 0;
514}
515
516static void pci_restore_pcix_state(struct pci_dev *dev)
517{
518 int i = 0, pos;
519 struct pci_cap_saved_state *save_state;
520 u16 *cap;
521
522 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
523 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
524 if (!save_state || pos <= 0)
525 return;
526 cap = (u16 *)&save_state->data[0];
527
528 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
529 pci_remove_saved_cap(save_state);
530 kfree(save_state);
531}
532
533
493/** 534/**
494 * pci_save_state - save the PCI configuration space of a device before suspending 535 * pci_save_state - save the PCI configuration space of a device before suspending
495 * @dev: - PCI device that we're dealing with 536 * @dev: - PCI device that we're dealing with
@@ -507,6 +548,8 @@ pci_save_state(struct pci_dev *dev)
507 return i; 548 return i;
508 if ((i = pci_save_pcie_state(dev)) != 0) 549 if ((i = pci_save_pcie_state(dev)) != 0)
509 return i; 550 return i;
551 if ((i = pci_save_pcix_state(dev)) != 0)
552 return i;
510 return 0; 553 return 0;
511} 554}
512 555
@@ -538,6 +581,7 @@ pci_restore_state(struct pci_dev *dev)
538 dev->saved_config_space[i]); 581 dev->saved_config_space[i]);
539 } 582 }
540 } 583 }
584 pci_restore_pcix_state(dev);
541 pci_restore_msi_state(dev); 585 pci_restore_msi_state(dev);
542 pci_restore_msix_state(dev); 586 pci_restore_msix_state(dev);
543 return 0; 587 return 0;
@@ -568,30 +612,51 @@ pci_enable_device_bars(struct pci_dev *dev, int bars)
568} 612}
569 613
570/** 614/**
571 * pci_enable_device - Initialize device before it's used by a driver. 615 * __pci_enable_device - Initialize device before it's used by a driver.
572 * @dev: PCI device to be initialized 616 * @dev: PCI device to be initialized
573 * 617 *
574 * Initialize device before it's used by a driver. Ask low-level code 618 * Initialize device before it's used by a driver. Ask low-level code
575 * to enable I/O and memory. Wake up the device if it was suspended. 619 * to enable I/O and memory. Wake up the device if it was suspended.
576 * Beware, this function can fail. 620 * Beware, this function can fail.
621 *
622 * Note this function is a backend and is not supposed to be called by
623 * normal code, use pci_enable_device() instead.
577 */ 624 */
578int 625int
579pci_enable_device(struct pci_dev *dev) 626__pci_enable_device(struct pci_dev *dev)
580{ 627{
581 int err; 628 int err;
582 629
583 if (dev->is_enabled)
584 return 0;
585
586 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); 630 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
587 if (err) 631 if (err)
588 return err; 632 return err;
589 pci_fixup_device(pci_fixup_enable, dev); 633 pci_fixup_device(pci_fixup_enable, dev);
590 dev->is_enabled = 1;
591 return 0; 634 return 0;
592} 635}
593 636
594/** 637/**
638 * pci_enable_device - Initialize device before it's used by a driver.
639 * @dev: PCI device to be initialized
640 *
641 * Initialize device before it's used by a driver. Ask low-level code
642 * to enable I/O and memory. Wake up the device if it was suspended.
643 * Beware, this function can fail.
644 *
645 * Note we don't actually enable the device many times if we call
646 * this function repeatedly (we just increment the count).
647 */
648int pci_enable_device(struct pci_dev *dev)
649{
650 int result;
651 if (atomic_add_return(1, &dev->enable_cnt) > 1)
652 return 0; /* already enabled */
653 result = __pci_enable_device(dev);
654 if (result < 0)
655 atomic_dec(&dev->enable_cnt);
656 return result;
657}
658
659/**
595 * pcibios_disable_device - disable arch specific PCI resources for device dev 660 * pcibios_disable_device - disable arch specific PCI resources for device dev
596 * @dev: the PCI device to disable 661 * @dev: the PCI device to disable
597 * 662 *
@@ -607,12 +672,18 @@ void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
607 * 672 *
608 * Signal to the system that the PCI device is not in use by the system 673 * Signal to the system that the PCI device is not in use by the system
609 * anymore. This only involves disabling PCI bus-mastering, if active. 674 * anymore. This only involves disabling PCI bus-mastering, if active.
675 *
676 * Note we don't actually disable the device until all callers of
677 * pci_device_enable() have called pci_device_disable().
610 */ 678 */
611void 679void
612pci_disable_device(struct pci_dev *dev) 680pci_disable_device(struct pci_dev *dev)
613{ 681{
614 u16 pci_command; 682 u16 pci_command;
615 683
684 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
685 return;
686
616 if (dev->msi_enabled) 687 if (dev->msi_enabled)
617 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 688 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
618 PCI_CAP_ID_MSI); 689 PCI_CAP_ID_MSI);
@@ -628,7 +699,6 @@ pci_disable_device(struct pci_dev *dev)
628 dev->is_busmaster = 0; 699 dev->is_busmaster = 0;
629 700
630 pcibios_disable_device(dev); 701 pcibios_disable_device(dev);
631 dev->is_enabled = 0;
632} 702}
633 703
634/** 704/**
@@ -831,22 +901,38 @@ pci_set_master(struct pci_dev *dev)
831 pcibios_set_master(dev); 901 pcibios_set_master(dev);
832} 902}
833 903
834#ifndef HAVE_ARCH_PCI_MWI 904#ifdef PCI_DISABLE_MWI
905int pci_set_mwi(struct pci_dev *dev)
906{
907 return 0;
908}
909
910void pci_clear_mwi(struct pci_dev *dev)
911{
912}
913
914#else
915
916#ifndef PCI_CACHE_LINE_BYTES
917#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
918#endif
919
835/* This can be overridden by arch code. */ 920/* This can be overridden by arch code. */
836u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; 921/* Don't forget this is measured in 32-bit words, not bytes */
922u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
837 923
838/** 924/**
839 * pci_generic_prep_mwi - helper function for pci_set_mwi 925 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
840 * @dev: the PCI device for which MWI is enabled 926 * @dev: the PCI device for which MWI is to be enabled
841 * 927 *
842 * Helper function for generic implementation of pcibios_prep_mwi 928 * Helper function for pci_set_mwi.
843 * function. Originally copied from drivers/net/acenic.c. 929 * Originally copied from drivers/net/acenic.c.
844 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 930 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
845 * 931 *
846 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 932 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
847 */ 933 */
848static int 934static int
849pci_generic_prep_mwi(struct pci_dev *dev) 935pci_set_cacheline_size(struct pci_dev *dev)
850{ 936{
851 u8 cacheline_size; 937 u8 cacheline_size;
852 938
@@ -872,7 +958,6 @@ pci_generic_prep_mwi(struct pci_dev *dev)
872 958
873 return -EINVAL; 959 return -EINVAL;
874} 960}
875#endif /* !HAVE_ARCH_PCI_MWI */
876 961
877/** 962/**
878 * pci_set_mwi - enables memory-write-invalidate PCI transaction 963 * pci_set_mwi - enables memory-write-invalidate PCI transaction
@@ -890,12 +975,7 @@ pci_set_mwi(struct pci_dev *dev)
890 int rc; 975 int rc;
891 u16 cmd; 976 u16 cmd;
892 977
893#ifdef HAVE_ARCH_PCI_MWI 978 rc = pci_set_cacheline_size(dev);
894 rc = pcibios_prep_mwi(dev);
895#else
896 rc = pci_generic_prep_mwi(dev);
897#endif
898
899 if (rc) 979 if (rc)
900 return rc; 980 return rc;
901 981
@@ -926,6 +1006,7 @@ pci_clear_mwi(struct pci_dev *dev)
926 pci_write_config_word(dev, PCI_COMMAND, cmd); 1006 pci_write_config_word(dev, PCI_COMMAND, cmd);
927 } 1007 }
928} 1008}
1009#endif /* ! PCI_DISABLE_MWI */
929 1010
930/** 1011/**
931 * pci_intx - enables/disables PCI INTx for device dev 1012 * pci_intx - enables/disables PCI INTx for device dev
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 6bf327db5c5e..398852f526a6 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -1,5 +1,6 @@
1/* Functions internal to the PCI core code */ 1/* Functions internal to the PCI core code */
2 2
3extern int __must_check __pci_enable_device(struct pci_dev *);
3extern int pci_uevent(struct device *dev, char **envp, int num_envp, 4extern int pci_uevent(struct device *dev, char **envp, int num_envp,
4 char *buffer, int buffer_size); 5 char *buffer, int buffer_size);
5extern int pci_create_sysfs_dev_files(struct pci_dev *pdev); 6extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e159d6604494..0eeac60042b3 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -679,6 +679,33 @@ static int pci_setup_device(struct pci_dev * dev)
679 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 679 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
680 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 680 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
681 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 681 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
682
683 /*
684 * Do the ugly legacy mode stuff here rather than broken chip
685 * quirk code. Legacy mode ATA controllers have fixed
686 * addresses. These are not always echoed in BAR0-3, and
687 * BAR0-3 in a few cases contain junk!
688 */
689 if (class == PCI_CLASS_STORAGE_IDE) {
690 u8 progif;
691 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
692 if ((progif & 1) == 0) {
693 dev->resource[0].start = 0x1F0;
694 dev->resource[0].end = 0x1F7;
695 dev->resource[0].flags = IORESOURCE_IO;
696 dev->resource[1].start = 0x3F6;
697 dev->resource[1].end = 0x3F6;
698 dev->resource[1].flags = IORESOURCE_IO;
699 }
700 if ((progif & 4) == 0) {
701 dev->resource[2].start = 0x170;
702 dev->resource[2].end = 0x177;
703 dev->resource[2].flags = IORESOURCE_IO;
704 dev->resource[3].start = 0x376;
705 dev->resource[3].end = 0x376;
706 dev->resource[3].flags = IORESOURCE_IO;
707 }
708 }
682 break; 709 break;
683 710
684 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 711 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 5b4483811691..9ca9b9bf6160 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -797,56 +797,6 @@ static void __init quirk_mediagx_master(struct pci_dev *dev)
797DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 797DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
798 798
799/* 799/*
800 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
801 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
802 * secondary channels respectively). If the device reports Compatible mode
803 * but does use BAR0-3 for address decoding, we assume that firmware has
804 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
805 * Exceptions (if they exist) must be handled in chip/architecture specific
806 * fixups.
807 *
808 * Note: for non x86 people. You may need an arch specific quirk to handle
809 * moving IDE devices to native mode as well. Some plug in card devices power
810 * up in compatible mode and assume the BIOS will adjust them.
811 *
812 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
813 * we do now ? We don't want is pci_enable_device to come along
814 * and assign new resources. Both approaches work for that.
815 */
816static void __devinit quirk_ide_bases(struct pci_dev *dev)
817{
818 struct resource *res;
819 int first_bar = 2, last_bar = 0;
820
821 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
822 return;
823
824 res = &dev->resource[0];
825
826 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
827 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
828 res[0].start = res[0].end = res[0].flags = 0;
829 res[1].start = res[1].end = res[1].flags = 0;
830 first_bar = 0;
831 last_bar = 1;
832 }
833
834 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
835 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
836 res[2].start = res[2].end = res[2].flags = 0;
837 res[3].start = res[3].end = res[3].flags = 0;
838 last_bar = 3;
839 }
840
841 if (!last_bar)
842 return;
843
844 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
845 first_bar, last_bar, pci_name(dev));
846}
847DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
848
849/*
850 * Ensure C0 rev restreaming is off. This is normally done by 800 * Ensure C0 rev restreaming is off. This is normally done by
851 * the BIOS but in the odd case it is not the results are corruption 801 * the BIOS but in the odd case it is not the results are corruption
852 * hence the presence of a Linux check 802 * hence the presence of a Linux check
@@ -880,11 +830,10 @@ static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
880 prog &= ~5; 830 prog &= ~5;
881 pdev->class &= ~5; 831 pdev->class &= ~5;
882 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 832 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
883 /* need to re-assign BARs for compat mode */ 833 /* PCI layer will sort out resources */
884 quirk_ide_bases(pdev);
885 } 834 }
886} 835}
887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 836DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
888 837
889/* 838/*
890 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 839 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
@@ -900,11 +849,9 @@ static void __init quirk_ide_samemode(struct pci_dev *pdev)
900 prog &= ~5; 849 prog &= ~5;
901 pdev->class &= ~5; 850 pdev->class &= ~5;
902 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 851 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
903 /* need to re-assign BARs for compat mode */
904 quirk_ide_bases(pdev);
905 } 852 }
906} 853}
907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 854DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
908 855
909/* This was originally an Alpha specific thing, but it really fits here. 856/* This was originally an Alpha specific thing, but it really fits here.
910 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 857 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index e1dcefc69bb4..d087e0817715 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -81,7 +81,8 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
81 start = (loff_t)0xC0000; 81 start = (loff_t)0xC0000;
82 *size = 0x20000; /* cover C000:0 through E000:0 */ 82 *size = 0x20000; /* cover C000:0 through E000:0 */
83 } else { 83 } else {
84 if (res->flags & IORESOURCE_ROM_COPY) { 84 if (res->flags &
85 (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
85 *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); 86 *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
86 return (void __iomem *)(unsigned long) 87 return (void __iomem *)(unsigned long)
87 pci_resource_start(pdev, PCI_ROM_RESOURCE); 88 pci_resource_start(pdev, PCI_ROM_RESOURCE);
@@ -165,7 +166,8 @@ void __iomem *pci_map_rom_copy(struct pci_dev *pdev, size_t *size)
165 if (!rom) 166 if (!rom)
166 return NULL; 167 return NULL;
167 168
168 if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_SHADOW)) 169 if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_SHADOW |
170 IORESOURCE_ROM_BIOS_COPY))
169 return rom; 171 return rom;
170 172
171 res->start = (unsigned long)kmalloc(*size, GFP_KERNEL); 173 res->start = (unsigned long)kmalloc(*size, GFP_KERNEL);
@@ -191,7 +193,7 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
191{ 193{
192 struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; 194 struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
193 195
194 if (res->flags & IORESOURCE_ROM_COPY) 196 if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
195 return; 197 return;
196 198
197 iounmap(rom); 199 iounmap(rom);
@@ -215,6 +217,7 @@ void pci_remove_rom(struct pci_dev *pdev)
215 sysfs_remove_bin_file(&pdev->dev.kobj, pdev->rom_attr); 217 sysfs_remove_bin_file(&pdev->dev.kobj, pdev->rom_attr);
216 if (!(res->flags & (IORESOURCE_ROM_ENABLE | 218 if (!(res->flags & (IORESOURCE_ROM_ENABLE |
217 IORESOURCE_ROM_SHADOW | 219 IORESOURCE_ROM_SHADOW |
220 IORESOURCE_ROM_BIOS_COPY |
218 IORESOURCE_ROM_COPY))) 221 IORESOURCE_ROM_COPY)))
219 pci_disable_rom(pdev); 222 pci_disable_rom(pdev);
220} 223}
diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c
index e469a46a388b..ff14fd8f0cd1 100644
--- a/drivers/pcmcia/ds.c
+++ b/drivers/pcmcia/ds.c
@@ -1273,7 +1273,9 @@ static void pcmcia_bus_remove_socket(struct class_device *class_dev,
1273 pccard_register_pcmcia(socket, NULL); 1273 pccard_register_pcmcia(socket, NULL);
1274 1274
1275 /* unregister any unbound devices */ 1275 /* unregister any unbound devices */
1276 mutex_lock(&socket->skt_mutex);
1276 pcmcia_card_remove(socket, NULL); 1277 pcmcia_card_remove(socket, NULL);
1278 mutex_unlock(&socket->skt_mutex);
1277 1279
1278 pcmcia_put_socket(socket); 1280 pcmcia_put_socket(socket);
1279 1281
diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c
index 579cd667b16f..6f11f6dfdd9d 100644
--- a/drivers/rtc/interface.c
+++ b/drivers/rtc/interface.c
@@ -145,6 +145,13 @@ int rtc_set_alarm(struct class_device *class_dev, struct rtc_wkalrm *alarm)
145} 145}
146EXPORT_SYMBOL_GPL(rtc_set_alarm); 146EXPORT_SYMBOL_GPL(rtc_set_alarm);
147 147
148/**
149 * rtc_update_irq - report RTC periodic, alarm, and/or update irqs
150 * @class_dev: the rtc's class device
151 * @num: how many irqs are being reported (usually one)
152 * @events: mask of RTC_IRQF with one or more of RTC_PF, RTC_AF, RTC_UF
153 * Context: in_interrupt(), irqs blocked
154 */
148void rtc_update_irq(struct class_device *class_dev, 155void rtc_update_irq(struct class_device *class_dev,
149 unsigned long num, unsigned long events) 156 unsigned long num, unsigned long events)
150{ 157{
@@ -201,12 +208,12 @@ int rtc_irq_register(struct class_device *class_dev, struct rtc_task *task)
201 if (task == NULL || task->func == NULL) 208 if (task == NULL || task->func == NULL)
202 return -EINVAL; 209 return -EINVAL;
203 210
204 spin_lock(&rtc->irq_task_lock); 211 spin_lock_irq(&rtc->irq_task_lock);
205 if (rtc->irq_task == NULL) { 212 if (rtc->irq_task == NULL) {
206 rtc->irq_task = task; 213 rtc->irq_task = task;
207 retval = 0; 214 retval = 0;
208 } 215 }
209 spin_unlock(&rtc->irq_task_lock); 216 spin_unlock_irq(&rtc->irq_task_lock);
210 217
211 return retval; 218 return retval;
212} 219}
@@ -216,10 +223,10 @@ void rtc_irq_unregister(struct class_device *class_dev, struct rtc_task *task)
216{ 223{
217 struct rtc_device *rtc = to_rtc_device(class_dev); 224 struct rtc_device *rtc = to_rtc_device(class_dev);
218 225
219 spin_lock(&rtc->irq_task_lock); 226 spin_lock_irq(&rtc->irq_task_lock);
220 if (rtc->irq_task == task) 227 if (rtc->irq_task == task)
221 rtc->irq_task = NULL; 228 rtc->irq_task = NULL;
222 spin_unlock(&rtc->irq_task_lock); 229 spin_unlock_irq(&rtc->irq_task_lock);
223} 230}
224EXPORT_SYMBOL_GPL(rtc_irq_unregister); 231EXPORT_SYMBOL_GPL(rtc_irq_unregister);
225 232
@@ -265,3 +272,4 @@ int rtc_irq_set_freq(struct class_device *class_dev, struct rtc_task *task, int
265 } 272 }
266 return err; 273 return err;
267} 274}
275EXPORT_SYMBOL_GPL(rtc_irq_set_freq);
diff --git a/drivers/rtc/rtc-at91.c b/drivers/rtc/rtc-at91.c
index bd61e99540a3..5c8addcaf1fb 100644
--- a/drivers/rtc/rtc-at91.c
+++ b/drivers/rtc/rtc-at91.c
@@ -292,7 +292,8 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
292 AT91_RTC_CALEV); 292 AT91_RTC_CALEV);
293 293
294 ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt, 294 ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
295 IRQF_SHARED, "at91_rtc", pdev); 295 IRQF_DISABLED | IRQF_SHARED,
296 "at91_rtc", pdev);
296 if (ret) { 297 if (ret) {
297 printk(KERN_ERR "at91_rtc: IRQ %d already in use.\n", 298 printk(KERN_ERR "at91_rtc: IRQ %d already in use.\n",
298 AT91_ID_SYS); 299 AT91_ID_SYS);
diff --git a/drivers/rtc/rtc-dev.c b/drivers/rtc/rtc-dev.c
index dcf5f86461f7..828b329e08e0 100644
--- a/drivers/rtc/rtc-dev.c
+++ b/drivers/rtc/rtc-dev.c
@@ -62,7 +62,9 @@ static void rtc_uie_task(struct work_struct *work)
62 int err; 62 int err;
63 63
64 err = rtc_read_time(&rtc->class_dev, &tm); 64 err = rtc_read_time(&rtc->class_dev, &tm);
65 spin_lock_irq(&rtc->irq_lock); 65
66 local_irq_disable();
67 spin_lock(&rtc->irq_lock);
66 if (rtc->stop_uie_polling || err) { 68 if (rtc->stop_uie_polling || err) {
67 rtc->uie_task_active = 0; 69 rtc->uie_task_active = 0;
68 } else if (rtc->oldsecs != tm.tm_sec) { 70 } else if (rtc->oldsecs != tm.tm_sec) {
@@ -75,11 +77,11 @@ static void rtc_uie_task(struct work_struct *work)
75 } else if (schedule_work(&rtc->uie_task) == 0) { 77 } else if (schedule_work(&rtc->uie_task) == 0) {
76 rtc->uie_task_active = 0; 78 rtc->uie_task_active = 0;
77 } 79 }
78 spin_unlock_irq(&rtc->irq_lock); 80 spin_unlock(&rtc->irq_lock);
79 if (num) 81 if (num)
80 rtc_update_irq(&rtc->class_dev, num, RTC_UF | RTC_IRQF); 82 rtc_update_irq(&rtc->class_dev, num, RTC_UF | RTC_IRQF);
83 local_irq_enable();
81} 84}
82
83static void rtc_uie_timer(unsigned long data) 85static void rtc_uie_timer(unsigned long data)
84{ 86{
85 struct rtc_device *rtc = (struct rtc_device *)data; 87 struct rtc_device *rtc = (struct rtc_device *)data;
@@ -215,7 +217,7 @@ static int rtc_dev_ioctl(struct inode *inode, struct file *file,
215 struct rtc_wkalrm alarm; 217 struct rtc_wkalrm alarm;
216 void __user *uarg = (void __user *) arg; 218 void __user *uarg = (void __user *) arg;
217 219
218 /* check that the calles has appropriate permissions 220 /* check that the calling task has appropriate permissions
219 * for certain ioctls. doing this check here is useful 221 * for certain ioctls. doing this check here is useful
220 * to avoid duplicate code in each driver. 222 * to avoid duplicate code in each driver.
221 */ 223 */
@@ -239,10 +241,10 @@ static int rtc_dev_ioctl(struct inode *inode, struct file *file,
239 241
240 /* avoid conflicting IRQ users */ 242 /* avoid conflicting IRQ users */
241 if (cmd == RTC_PIE_ON || cmd == RTC_PIE_OFF || cmd == RTC_IRQP_SET) { 243 if (cmd == RTC_PIE_ON || cmd == RTC_PIE_OFF || cmd == RTC_IRQP_SET) {
242 spin_lock(&rtc->irq_task_lock); 244 spin_lock_irq(&rtc->irq_task_lock);
243 if (rtc->irq_task) 245 if (rtc->irq_task)
244 err = -EBUSY; 246 err = -EBUSY;
245 spin_unlock(&rtc->irq_task_lock); 247 spin_unlock_irq(&rtc->irq_task_lock);
246 248
247 if (err < 0) 249 if (err < 0)
248 return err; 250 return err;
@@ -300,6 +302,17 @@ static int rtc_dev_ioctl(struct inode *inode, struct file *file,
300 302
301 err = rtc_set_time(class_dev, &tm); 303 err = rtc_set_time(class_dev, &tm);
302 break; 304 break;
305
306 case RTC_IRQP_READ:
307 if (ops->irq_set_freq)
308 err = put_user(rtc->irq_freq, (unsigned long *) arg);
309 break;
310
311 case RTC_IRQP_SET:
312 if (ops->irq_set_freq)
313 err = rtc_irq_set_freq(class_dev, rtc->irq_task, arg);
314 break;
315
303#if 0 316#if 0
304 case RTC_EPOCH_SET: 317 case RTC_EPOCH_SET:
305#ifndef rtc_epoch 318#ifndef rtc_epoch
diff --git a/drivers/rtc/rtc-ds1553.c b/drivers/rtc/rtc-ds1553.c
index 78552e6e76aa..001eb1123a65 100644
--- a/drivers/rtc/rtc-ds1553.c
+++ b/drivers/rtc/rtc-ds1553.c
@@ -340,7 +340,8 @@ static int __init ds1553_rtc_probe(struct platform_device *pdev)
340 340
341 if (pdata->irq >= 0) { 341 if (pdata->irq >= 0) {
342 writeb(0, ioaddr + RTC_INTERRUPTS); 342 writeb(0, ioaddr + RTC_INTERRUPTS);
343 if (request_irq(pdata->irq, ds1553_rtc_interrupt, IRQF_SHARED, 343 if (request_irq(pdata->irq, ds1553_rtc_interrupt,
344 IRQF_DISABLED | IRQF_SHARED,
344 pdev->name, pdev) < 0) { 345 pdev->name, pdev) < 0) {
345 dev_warn(&pdev->dev, "interrupt not available.\n"); 346 dev_warn(&pdev->dev, "interrupt not available.\n");
346 pdata->irq = -1; 347 pdata->irq = -1;
diff --git a/drivers/rtc/rtc-rs5c372.c b/drivers/rtc/rtc-rs5c372.c
index 2a86632580f1..a44fe4efa216 100644
--- a/drivers/rtc/rtc-rs5c372.c
+++ b/drivers/rtc/rtc-rs5c372.c
@@ -126,13 +126,13 @@ static int rs5c372_get_trim(struct i2c_client *client, int *osc, int *trim)
126 return -EIO; 126 return -EIO;
127 } 127 }
128 128
129 dev_dbg(&client->dev, "%s: raw trim=%x\n", __FUNCTION__, *trim);
130
131 if (osc) 129 if (osc)
132 *osc = (buf & RS5C372_TRIM_XSL) ? 32000 : 32768; 130 *osc = (buf & RS5C372_TRIM_XSL) ? 32000 : 32768;
133 131
134 if (trim) 132 if (trim) {
135 *trim = buf & RS5C372_TRIM_MASK; 133 *trim = buf & RS5C372_TRIM_MASK;
134 dev_dbg(&client->dev, "%s: raw trim=%x\n", __FUNCTION__, *trim);
135 }
136 136
137 return 0; 137 return 0;
138} 138}
diff --git a/drivers/rtc/rtc-test.c b/drivers/rtc/rtc-test.c
index bc4bd24508a2..6ef9c62d5032 100644
--- a/drivers/rtc/rtc-test.c
+++ b/drivers/rtc/rtc-test.c
@@ -99,6 +99,7 @@ static ssize_t test_irq_store(struct device *dev,
99 struct rtc_device *rtc = platform_get_drvdata(plat_dev); 99 struct rtc_device *rtc = platform_get_drvdata(plat_dev);
100 100
101 retval = count; 101 retval = count;
102 local_irq_disable();
102 if (strncmp(buf, "tick", 4) == 0) 103 if (strncmp(buf, "tick", 4) == 0)
103 rtc_update_irq(&rtc->class_dev, 1, RTC_PF | RTC_IRQF); 104 rtc_update_irq(&rtc->class_dev, 1, RTC_PF | RTC_IRQF);
104 else if (strncmp(buf, "alarm", 5) == 0) 105 else if (strncmp(buf, "alarm", 5) == 0)
@@ -107,6 +108,7 @@ static ssize_t test_irq_store(struct device *dev,
107 rtc_update_irq(&rtc->class_dev, 1, RTC_UF | RTC_IRQF); 108 rtc_update_irq(&rtc->class_dev, 1, RTC_UF | RTC_IRQF);
108 else 109 else
109 retval = -EINVAL; 110 retval = -EINVAL;
111 local_irq_enable();
110 112
111 return retval; 113 return retval;
112} 114}
diff --git a/drivers/s390/net/claw.h b/drivers/s390/net/claw.h
index 969be465309c..1ee9a6f06541 100644
--- a/drivers/s390/net/claw.h
+++ b/drivers/s390/net/claw.h
@@ -29,7 +29,7 @@
29#define CLAW_COMPLETE 0xff /* flag to indicate i/o completed */ 29#define CLAW_COMPLETE 0xff /* flag to indicate i/o completed */
30 30
31/*-----------------------------------------------------* 31/*-----------------------------------------------------*
32* CLAW control comand code * 32* CLAW control command code *
33*------------------------------------------------------*/ 33*------------------------------------------------------*/
34 34
35#define SYSTEM_VALIDATE_REQUEST 0x01 /* System Validate request */ 35#define SYSTEM_VALIDATE_REQUEST 0x01 /* System Validate request */
diff --git a/drivers/s390/net/lcs.c b/drivers/s390/net/lcs.c
index 16ac68c27a27..66a8aec6efa6 100644
--- a/drivers/s390/net/lcs.c
+++ b/drivers/s390/net/lcs.c
@@ -1147,7 +1147,7 @@ list_modified:
1147 * get mac address for the relevant Multicast address 1147 * get mac address for the relevant Multicast address
1148 */ 1148 */
1149static void 1149static void
1150lcs_get_mac_for_ipm(__u32 ipm, char *mac, struct net_device *dev) 1150lcs_get_mac_for_ipm(__be32 ipm, char *mac, struct net_device *dev)
1151{ 1151{
1152 LCS_DBF_TEXT(4,trace, "getmac"); 1152 LCS_DBF_TEXT(4,trace, "getmac");
1153 if (dev->type == ARPHRD_IEEE802_TR) 1153 if (dev->type == ARPHRD_IEEE802_TR)
diff --git a/drivers/s390/net/lcs.h b/drivers/s390/net/lcs.h
index 93143932983b..b5247dc08b57 100644
--- a/drivers/s390/net/lcs.h
+++ b/drivers/s390/net/lcs.h
@@ -169,7 +169,7 @@ struct lcs_header {
169} __attribute__ ((packed)); 169} __attribute__ ((packed));
170 170
171struct lcs_ip_mac_pair { 171struct lcs_ip_mac_pair {
172 __u32 ip_addr; 172 __be32 ip_addr;
173 __u8 mac_addr[LCS_MAC_LENGTH]; 173 __u8 mac_addr[LCS_MAC_LENGTH];
174 __u8 reserved[2]; 174 __u8 reserved[2];
175} __attribute__ ((packed)); 175} __attribute__ ((packed));
@@ -287,7 +287,7 @@ struct lcs_card {
287 enum lcs_dev_states state; 287 enum lcs_dev_states state;
288 struct net_device *dev; 288 struct net_device *dev;
289 struct net_device_stats stats; 289 struct net_device_stats stats;
290 unsigned short (*lan_type_trans)(struct sk_buff *skb, 290 __be16 (*lan_type_trans)(struct sk_buff *skb,
291 struct net_device *dev); 291 struct net_device *dev);
292 struct ccwgroup_device *gdev; 292 struct ccwgroup_device *gdev;
293 struct lcs_channel read; 293 struct lcs_channel read;
diff --git a/drivers/s390/net/qeth_eddp.c b/drivers/s390/net/qeth_eddp.c
index a363721cf28d..6bb558a9a032 100644
--- a/drivers/s390/net/qeth_eddp.c
+++ b/drivers/s390/net/qeth_eddp.c
@@ -258,7 +258,7 @@ qeth_eddp_create_segment_hdrs(struct qeth_eddp_context *ctx,
258 258
259static inline void 259static inline void
260qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp, int len, 260qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp, int len,
261 u32 *hcsum) 261 __wsum *hcsum)
262{ 262{
263 struct skb_frag_struct *frag; 263 struct skb_frag_struct *frag;
264 int left_in_frag; 264 int left_in_frag;
@@ -305,7 +305,7 @@ qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp, int len,
305static inline void 305static inline void
306qeth_eddp_create_segment_data_tcp(struct qeth_eddp_context *ctx, 306qeth_eddp_create_segment_data_tcp(struct qeth_eddp_context *ctx,
307 struct qeth_eddp_data *eddp, int data_len, 307 struct qeth_eddp_data *eddp, int data_len,
308 u32 hcsum) 308 __wsum hcsum)
309{ 309{
310 u8 *page; 310 u8 *page;
311 int page_remainder; 311 int page_remainder;
@@ -349,10 +349,10 @@ qeth_eddp_create_segment_data_tcp(struct qeth_eddp_context *ctx,
349 ((struct tcphdr *)eddp->th_in_ctx)->check = csum_fold(hcsum); 349 ((struct tcphdr *)eddp->th_in_ctx)->check = csum_fold(hcsum);
350} 350}
351 351
352static inline u32 352static inline __wsum
353qeth_eddp_check_tcp4_hdr(struct qeth_eddp_data *eddp, int data_len) 353qeth_eddp_check_tcp4_hdr(struct qeth_eddp_data *eddp, int data_len)
354{ 354{
355 u32 phcsum; /* pseudo header checksum */ 355 __wsum phcsum; /* pseudo header checksum */
356 356
357 QETH_DBF_TEXT(trace, 5, "eddpckt4"); 357 QETH_DBF_TEXT(trace, 5, "eddpckt4");
358 eddp->th.tcp.h.check = 0; 358 eddp->th.tcp.h.check = 0;
@@ -363,11 +363,11 @@ qeth_eddp_check_tcp4_hdr(struct qeth_eddp_data *eddp, int data_len)
363 return csum_partial((u8 *)&eddp->th, eddp->thl, phcsum); 363 return csum_partial((u8 *)&eddp->th, eddp->thl, phcsum);
364} 364}
365 365
366static inline u32 366static inline __wsum
367qeth_eddp_check_tcp6_hdr(struct qeth_eddp_data *eddp, int data_len) 367qeth_eddp_check_tcp6_hdr(struct qeth_eddp_data *eddp, int data_len)
368{ 368{
369 u32 proto; 369 __be32 proto;
370 u32 phcsum; /* pseudo header checksum */ 370 __wsum phcsum; /* pseudo header checksum */
371 371
372 QETH_DBF_TEXT(trace, 5, "eddpckt6"); 372 QETH_DBF_TEXT(trace, 5, "eddpckt6");
373 eddp->th.tcp.h.check = 0; 373 eddp->th.tcp.h.check = 0;
@@ -405,7 +405,7 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
405{ 405{
406 struct tcphdr *tcph; 406 struct tcphdr *tcph;
407 int data_len; 407 int data_len;
408 u32 hcsum; 408 __wsum hcsum;
409 409
410 QETH_DBF_TEXT(trace, 5, "eddpftcp"); 410 QETH_DBF_TEXT(trace, 5, "eddpftcp");
411 eddp->skb_offset = sizeof(struct qeth_hdr) + eddp->nhl + eddp->thl; 411 eddp->skb_offset = sizeof(struct qeth_hdr) + eddp->nhl + eddp->thl;
@@ -433,22 +433,22 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
433 eddp->qh.hdr.l3.length = data_len + eddp->nhl + 433 eddp->qh.hdr.l3.length = data_len + eddp->nhl +
434 eddp->thl; 434 eddp->thl;
435 /* prepare ip hdr */ 435 /* prepare ip hdr */
436 if (eddp->skb->protocol == ETH_P_IP){ 436 if (eddp->skb->protocol == htons(ETH_P_IP)){
437 eddp->nh.ip4.h.tot_len = data_len + eddp->nhl + 437 eddp->nh.ip4.h.tot_len = htons(data_len + eddp->nhl +
438 eddp->thl; 438 eddp->thl);
439 eddp->nh.ip4.h.check = 0; 439 eddp->nh.ip4.h.check = 0;
440 eddp->nh.ip4.h.check = 440 eddp->nh.ip4.h.check =
441 ip_fast_csum((u8 *)&eddp->nh.ip4.h, 441 ip_fast_csum((u8 *)&eddp->nh.ip4.h,
442 eddp->nh.ip4.h.ihl); 442 eddp->nh.ip4.h.ihl);
443 } else 443 } else
444 eddp->nh.ip6.h.payload_len = data_len + eddp->thl; 444 eddp->nh.ip6.h.payload_len = htons(data_len + eddp->thl);
445 /* prepare tcp hdr */ 445 /* prepare tcp hdr */
446 if (data_len == (eddp->skb->len - eddp->skb_offset)){ 446 if (data_len == (eddp->skb->len - eddp->skb_offset)){
447 /* last segment -> set FIN and PSH flags */ 447 /* last segment -> set FIN and PSH flags */
448 eddp->th.tcp.h.fin = tcph->fin; 448 eddp->th.tcp.h.fin = tcph->fin;
449 eddp->th.tcp.h.psh = tcph->psh; 449 eddp->th.tcp.h.psh = tcph->psh;
450 } 450 }
451 if (eddp->skb->protocol == ETH_P_IP) 451 if (eddp->skb->protocol == htons(ETH_P_IP))
452 hcsum = qeth_eddp_check_tcp4_hdr(eddp, data_len); 452 hcsum = qeth_eddp_check_tcp4_hdr(eddp, data_len);
453 else 453 else
454 hcsum = qeth_eddp_check_tcp6_hdr(eddp, data_len); 454 hcsum = qeth_eddp_check_tcp6_hdr(eddp, data_len);
@@ -458,9 +458,9 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
458 if (eddp->skb_offset >= eddp->skb->len) 458 if (eddp->skb_offset >= eddp->skb->len)
459 break; 459 break;
460 /* prepare headers for next round */ 460 /* prepare headers for next round */
461 if (eddp->skb->protocol == ETH_P_IP) 461 if (eddp->skb->protocol == htons(ETH_P_IP))
462 eddp->nh.ip4.h.id++; 462 eddp->nh.ip4.h.id = htons(ntohs(eddp->nh.ip4.h.id) + 1);
463 eddp->th.tcp.h.seq += data_len; 463 eddp->th.tcp.h.seq = htonl(ntohl(eddp->th.tcp.h.seq) + data_len);
464 } 464 }
465} 465}
466 466
@@ -472,7 +472,7 @@ qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
472 472
473 QETH_DBF_TEXT(trace, 5, "eddpficx"); 473 QETH_DBF_TEXT(trace, 5, "eddpficx");
474 /* create our segmentation headers and copy original headers */ 474 /* create our segmentation headers and copy original headers */
475 if (skb->protocol == ETH_P_IP) 475 if (skb->protocol == htons(ETH_P_IP))
476 eddp = qeth_eddp_create_eddp_data(qhdr, (u8 *)skb->nh.iph, 476 eddp = qeth_eddp_create_eddp_data(qhdr, (u8 *)skb->nh.iph,
477 skb->nh.iph->ihl*4, 477 skb->nh.iph->ihl*4,
478 (u8 *)skb->h.th, skb->h.th->doff*4); 478 (u8 *)skb->h.th, skb->h.th->doff*4);
@@ -490,7 +490,7 @@ qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
490 memcpy(&eddp->mac, eth_hdr(skb), ETH_HLEN); 490 memcpy(&eddp->mac, eth_hdr(skb), ETH_HLEN);
491#ifdef CONFIG_QETH_VLAN 491#ifdef CONFIG_QETH_VLAN
492 if (eddp->mac.h_proto == __constant_htons(ETH_P_8021Q)) { 492 if (eddp->mac.h_proto == __constant_htons(ETH_P_8021Q)) {
493 eddp->vlan[0] = __constant_htons(skb->protocol); 493 eddp->vlan[0] = skb->protocol;
494 eddp->vlan[1] = htons(vlan_tx_tag_get(skb)); 494 eddp->vlan[1] = htons(vlan_tx_tag_get(skb));
495 } 495 }
496#endif /* CONFIG_QETH_VLAN */ 496#endif /* CONFIG_QETH_VLAN */
@@ -588,11 +588,11 @@ qeth_eddp_create_context_tcp(struct qeth_card *card, struct sk_buff *skb,
588 struct qeth_eddp_context *ctx = NULL; 588 struct qeth_eddp_context *ctx = NULL;
589 589
590 QETH_DBF_TEXT(trace, 5, "creddpct"); 590 QETH_DBF_TEXT(trace, 5, "creddpct");
591 if (skb->protocol == ETH_P_IP) 591 if (skb->protocol == htons(ETH_P_IP))
592 ctx = qeth_eddp_create_context_generic(card, skb, 592 ctx = qeth_eddp_create_context_generic(card, skb,
593 sizeof(struct qeth_hdr) + skb->nh.iph->ihl*4 + 593 sizeof(struct qeth_hdr) + skb->nh.iph->ihl*4 +
594 skb->h.th->doff*4); 594 skb->h.th->doff*4);
595 else if (skb->protocol == ETH_P_IPV6) 595 else if (skb->protocol == htons(ETH_P_IPV6))
596 ctx = qeth_eddp_create_context_generic(card, skb, 596 ctx = qeth_eddp_create_context_generic(card, skb,
597 sizeof(struct qeth_hdr) + sizeof(struct ipv6hdr) + 597 sizeof(struct qeth_hdr) + sizeof(struct ipv6hdr) +
598 skb->h.th->doff*4); 598 skb->h.th->doff*4);
diff --git a/drivers/s390/net/qeth_eddp.h b/drivers/s390/net/qeth_eddp.h
index cae9ba265056..103768d3bab2 100644
--- a/drivers/s390/net/qeth_eddp.h
+++ b/drivers/s390/net/qeth_eddp.h
@@ -54,7 +54,7 @@ qeth_eddp_check_buffers_for_context(struct qeth_qdio_out_q *,
54struct qeth_eddp_data { 54struct qeth_eddp_data {
55 struct qeth_hdr qh; 55 struct qeth_hdr qh;
56 struct ethhdr mac; 56 struct ethhdr mac;
57 u16 vlan[2]; 57 __be16 vlan[2];
58 union { 58 union {
59 struct { 59 struct {
60 struct iphdr h; 60 struct iphdr h;
diff --git a/drivers/scsi/aic94xx/aic94xx_reg_def.h b/drivers/scsi/aic94xx/aic94xx_reg_def.h
index b79f45f3ad47..a11f4e6d8bd9 100644
--- a/drivers/scsi/aic94xx/aic94xx_reg_def.h
+++ b/drivers/scsi/aic94xx/aic94xx_reg_def.h
@@ -2000,7 +2000,7 @@
2000 * The host accesses this scratch in a different manner from the 2000 * The host accesses this scratch in a different manner from the
2001 * central sequencer. The sequencer has to use CSEQ registers CSCRPAGE 2001 * central sequencer. The sequencer has to use CSEQ registers CSCRPAGE
2002 * and CMnSCRPAGE to access the scratch memory. A flat mapping of the 2002 * and CMnSCRPAGE to access the scratch memory. A flat mapping of the
2003 * scratch memory is avaliable for software convenience and to prevent 2003 * scratch memory is available for software convenience and to prevent
2004 * corruption while the sequencer is running. This memory is mapped 2004 * corruption while the sequencer is running. This memory is mapped
2005 * onto addresses 800h - BFFh, total of 400h bytes. 2005 * onto addresses 800h - BFFh, total of 400h bytes.
2006 * 2006 *
diff --git a/drivers/scsi/aic94xx/aic94xx_sds.c b/drivers/scsi/aic94xx/aic94xx_sds.c
index de7c04d4254d..e5a0ec37e954 100644
--- a/drivers/scsi/aic94xx/aic94xx_sds.c
+++ b/drivers/scsi/aic94xx/aic94xx_sds.c
@@ -64,7 +64,7 @@ struct asd_ocm_dir {
64 64
65#define OCM_INIT_DIR_ENTRIES 5 65#define OCM_INIT_DIR_ENTRIES 5
66/*************************************************************************** 66/***************************************************************************
67* OCM dircetory default 67* OCM directory default
68***************************************************************************/ 68***************************************************************************/
69static struct asd_ocm_dir OCMDirInit = 69static struct asd_ocm_dir OCMDirInit =
70{ 70{
@@ -73,7 +73,7 @@ static struct asd_ocm_dir OCMDirInit =
73}; 73};
74 74
75/*************************************************************************** 75/***************************************************************************
76* OCM dircetory Entries default 76* OCM directory Entries default
77***************************************************************************/ 77***************************************************************************/
78static struct asd_ocm_dir_ent OCMDirEntriesInit[OCM_INIT_DIR_ENTRIES] = 78static struct asd_ocm_dir_ent OCMDirEntriesInit[OCM_INIT_DIR_ENTRIES] =
79{ 79{
diff --git a/drivers/scsi/ncr53c8xx.c b/drivers/scsi/ncr53c8xx.c
index 6cc2bc2f62be..adb8eb4f5fd1 100644
--- a/drivers/scsi/ncr53c8xx.c
+++ b/drivers/scsi/ncr53c8xx.c
@@ -185,7 +185,7 @@ static inline struct list_head *ncr_list_pop(struct list_head *head)
185** power of 2 cache line size. 185** power of 2 cache line size.
186** Enhanced in linux-2.3.44 to provide a memory pool 186** Enhanced in linux-2.3.44 to provide a memory pool
187** per pcidev to support dynamic dma mapping. (I would 187** per pcidev to support dynamic dma mapping. (I would
188** have preferred a real bus astraction, btw). 188** have preferred a real bus abstraction, btw).
189** 189**
190**========================================================== 190**==========================================================
191*/ 191*/
@@ -1438,7 +1438,7 @@ struct head {
1438** The first four bytes (scr_st[4]) are used inside the script by 1438** The first four bytes (scr_st[4]) are used inside the script by
1439** "COPY" commands. 1439** "COPY" commands.
1440** Because source and destination must have the same alignment 1440** Because source and destination must have the same alignment
1441** in a DWORD, the fields HAVE to be at the choosen offsets. 1441** in a DWORD, the fields HAVE to be at the chosen offsets.
1442** xerr_st 0 (0x34) scratcha 1442** xerr_st 0 (0x34) scratcha
1443** sync_st 1 (0x05) sxfer 1443** sync_st 1 (0x05) sxfer
1444** wide_st 3 (0x03) scntl3 1444** wide_st 3 (0x03) scntl3
@@ -1498,7 +1498,7 @@ struct head {
1498** the DSA (data structure address) register points 1498** the DSA (data structure address) register points
1499** to this substructure of the ccb. 1499** to this substructure of the ccb.
1500** This substructure contains the header with 1500** This substructure contains the header with
1501** the script-processor-changable data and 1501** the script-processor-changeable data and
1502** data blocks for the indirect move commands. 1502** data blocks for the indirect move commands.
1503** 1503**
1504**---------------------------------------------------------- 1504**----------------------------------------------------------
@@ -5107,7 +5107,7 @@ void ncr_complete (struct ncb *np, struct ccb *cp)
5107 5107
5108/* 5108/*
5109** This CCB has been skipped by the NCR. 5109** This CCB has been skipped by the NCR.
5110** Queue it in the correponding unit queue. 5110** Queue it in the corresponding unit queue.
5111*/ 5111*/
5112static void ncr_ccb_skipped(struct ncb *np, struct ccb *cp) 5112static void ncr_ccb_skipped(struct ncb *np, struct ccb *cp)
5113{ 5113{
@@ -5896,8 +5896,8 @@ static void ncr_log_hard_error(struct ncb *np, u16 sist, u_char dstat)
5896** 5896**
5897** In normal cases, interrupt conditions occur one at a 5897** In normal cases, interrupt conditions occur one at a
5898** time. The ncr is able to stack in some extra registers 5898** time. The ncr is able to stack in some extra registers
5899** other interrupts that will occurs after the first one. 5899** other interrupts that will occur after the first one.
5900** But severall interrupts may occur at the same time. 5900** But, several interrupts may occur at the same time.
5901** 5901**
5902** We probably should only try to deal with the normal 5902** We probably should only try to deal with the normal
5903** case, but it seems that multiple interrupts occur in 5903** case, but it seems that multiple interrupts occur in
@@ -6796,7 +6796,7 @@ void ncr_int_sir (struct ncb *np)
6796** The host status field is set to HS_NEGOTIATE to mark this 6796** The host status field is set to HS_NEGOTIATE to mark this
6797** situation. 6797** situation.
6798** 6798**
6799** If the target doesn't answer this message immidiately 6799** If the target doesn't answer this message immediately
6800** (as required by the standard), the SIR_NEGO_FAIL interrupt 6800** (as required by the standard), the SIR_NEGO_FAIL interrupt
6801** will be raised eventually. 6801** will be raised eventually.
6802** The handler removes the HS_NEGOTIATE status, and sets the 6802** The handler removes the HS_NEGOTIATE status, and sets the
diff --git a/drivers/scsi/ncr53c8xx.h b/drivers/scsi/ncr53c8xx.h
index cb8b7701431e..b39357d9af8d 100644
--- a/drivers/scsi/ncr53c8xx.h
+++ b/drivers/scsi/ncr53c8xx.h
@@ -218,7 +218,7 @@
218** Same as option 1, but also deal with 218** Same as option 1, but also deal with
219** misconfigured interrupts. 219** misconfigured interrupts.
220** 220**
221** - Edge triggerred instead of level sensitive. 221** - Edge triggered instead of level sensitive.
222** - No interrupt line connected. 222** - No interrupt line connected.
223** - IRQ number misconfigured. 223** - IRQ number misconfigured.
224** 224**
@@ -549,7 +549,7 @@ struct ncr_driver_setup {
549 549
550/* 550/*
551** Initial setup. 551** Initial setup.
552** Can be overriden at startup by a command line. 552** Can be overridden at startup by a command line.
553*/ 553*/
554#define SCSI_NCR_DRIVER_SETUP \ 554#define SCSI_NCR_DRIVER_SETUP \
555{ \ 555{ \
@@ -1093,7 +1093,7 @@ struct scr_tblsel {
1093**----------------------------------------------------------- 1093**-----------------------------------------------------------
1094** On 810A, 860, 825A, 875, 895 and 896 chips the content 1094** On 810A, 860, 825A, 875, 895 and 896 chips the content
1095** of SFBR register can be used as data (SCR_SFBR_DATA). 1095** of SFBR register can be used as data (SCR_SFBR_DATA).
1096** The 896 has additionnal IO registers starting at 1096** The 896 has additional IO registers starting at
1097** offset 0x80. Bit 7 of register offset is stored in 1097** offset 0x80. Bit 7 of register offset is stored in
1098** bit 7 of the SCRIPTS instruction first DWORD. 1098** bit 7 of the SCRIPTS instruction first DWORD.
1099**----------------------------------------------------------- 1099**-----------------------------------------------------------
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 23334c8bc4c7..d895a1adb428 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,7 +16,7 @@ config SPI
16 controller and a chipselect. Most SPI slaves don't support 16 controller and a chipselect. Most SPI slaves don't support
17 dynamic device discovery; some are even write-only or read-only. 17 dynamic device discovery; some are even write-only or read-only.
18 18
19 SPI is widely used by microcontollers to talk with sensors, 19 SPI is widely used by microcontrollers to talk with sensors,
20 eeprom and flash memory, codecs and various other controller 20 eeprom and flash memory, codecs and various other controller
21 chips, analog to digital (and d-to-a) converters, and more. 21 chips, analog to digital (and d-to-a) converters, and more.
22 MMC and SD cards can be accessed using SPI protocol; and for 22 MMC and SD cards can be accessed using SPI protocol; and for
diff --git a/drivers/usb/atm/speedtch.c b/drivers/usb/atm/speedtch.c
index 7ed34bb1c50f..8ed6c75adf0f 100644
--- a/drivers/usb/atm/speedtch.c
+++ b/drivers/usb/atm/speedtch.c
@@ -837,8 +837,8 @@ static int speedtch_bind(struct usbatm_data *usbatm,
837 const struct usb_endpoint_descriptor *endpoint_desc = &desc->endpoint[i].desc; 837 const struct usb_endpoint_descriptor *endpoint_desc = &desc->endpoint[i].desc;
838 838
839 if ((endpoint_desc->bEndpointAddress == target_address)) { 839 if ((endpoint_desc->bEndpointAddress == target_address)) {
840 use_isoc = (endpoint_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == 840 use_isoc =
841 USB_ENDPOINT_XFER_ISOC; 841 usb_endpoint_xfer_isoc(endpoint_desc);
842 break; 842 break;
843 } 843 }
844 } 844 }
diff --git a/drivers/usb/atm/ueagle-atm.c b/drivers/usb/atm/ueagle-atm.c
index e39bb09f5af9..f2d196fa1e8b 100644
--- a/drivers/usb/atm/ueagle-atm.c
+++ b/drivers/usb/atm/ueagle-atm.c
@@ -401,9 +401,8 @@ static int uea_send_modem_cmd(struct usb_device *usb,
401 int ret = -ENOMEM; 401 int ret = -ENOMEM;
402 u8 *xfer_buff; 402 u8 *xfer_buff;
403 403
404 xfer_buff = kmalloc(size, GFP_KERNEL); 404 xfer_buff = kmemdup(buff, size, GFP_KERNEL);
405 if (xfer_buff) { 405 if (xfer_buff) {
406 memcpy(xfer_buff, buff, size);
407 ret = usb_control_msg(usb, 406 ret = usb_control_msg(usb,
408 usb_sndctrlpipe(usb, 0), 407 usb_sndctrlpipe(usb, 0),
409 LOAD_INTERNAL, 408 LOAD_INTERNAL,
@@ -595,14 +594,12 @@ static int uea_idma_write(struct uea_softc *sc, void *data, u32 size)
595 u8 *xfer_buff; 594 u8 *xfer_buff;
596 int bytes_read; 595 int bytes_read;
597 596
598 xfer_buff = kmalloc(size, GFP_KERNEL); 597 xfer_buff = kmemdup(data, size, GFP_KERNEL);
599 if (!xfer_buff) { 598 if (!xfer_buff) {
600 uea_err(INS_TO_USBDEV(sc), "can't allocate xfer_buff\n"); 599 uea_err(INS_TO_USBDEV(sc), "can't allocate xfer_buff\n");
601 return ret; 600 return ret;
602 } 601 }
603 602
604 memcpy(xfer_buff, data, size);
605
606 ret = usb_bulk_msg(sc->usb_dev, 603 ret = usb_bulk_msg(sc->usb_dev,
607 usb_sndbulkpipe(sc->usb_dev, UEA_IDMA_PIPE), 604 usb_sndbulkpipe(sc->usb_dev, UEA_IDMA_PIPE),
608 xfer_buff, size, &bytes_read, BULK_TIMEOUT); 605 xfer_buff, size, &bytes_read, BULK_TIMEOUT);
@@ -765,12 +762,11 @@ static int uea_request(struct uea_softc *sc,
765 u8 *xfer_buff; 762 u8 *xfer_buff;
766 int ret = -ENOMEM; 763 int ret = -ENOMEM;
767 764
768 xfer_buff = kmalloc(size, GFP_KERNEL); 765 xfer_buff = kmemdup(data, size, GFP_KERNEL);
769 if (!xfer_buff) { 766 if (!xfer_buff) {
770 uea_err(INS_TO_USBDEV(sc), "can't allocate xfer_buff\n"); 767 uea_err(INS_TO_USBDEV(sc), "can't allocate xfer_buff\n");
771 return ret; 768 return ret;
772 } 769 }
773 memcpy(xfer_buff, data, size);
774 770
775 ret = usb_control_msg(sc->usb_dev, usb_sndctrlpipe(sc->usb_dev, 0), 771 ret = usb_control_msg(sc->usb_dev, usb_sndctrlpipe(sc->usb_dev, 0),
776 UCDC_SEND_ENCAPSULATED_COMMAND, 772 UCDC_SEND_ENCAPSULATED_COMMAND,
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 6408e10fdbf8..7f1fa956dcdb 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -892,7 +892,7 @@ skip_normal_probe:
892 892
893 893
894 /* workaround for switched endpoints */ 894 /* workaround for switched endpoints */
895 if ((epread->bEndpointAddress & USB_DIR_IN) != USB_DIR_IN) { 895 if (!usb_endpoint_dir_in(epread)) {
896 /* descriptors are swapped */ 896 /* descriptors are swapped */
897 struct usb_endpoint_descriptor *t; 897 struct usb_endpoint_descriptor *t;
898 dev_dbg(&intf->dev,"The data interface has switched endpoints"); 898 dev_dbg(&intf->dev,"The data interface has switched endpoints");
diff --git a/drivers/usb/core/Kconfig b/drivers/usb/core/Kconfig
index 6e3b5358a760..f8324d8d06ac 100644
--- a/drivers/usb/core/Kconfig
+++ b/drivers/usb/core/Kconfig
@@ -72,6 +72,21 @@ config USB_SUSPEND
72 72
73 If you are unsure about this, say N here. 73 If you are unsure about this, say N here.
74 74
75config USB_MULTITHREAD_PROBE
76 bool "USB Multi-threaded probe (EXPERIMENTAL)"
77 depends on USB && EXPERIMENTAL
78 default n
79 help
80 Say Y here if you want the USB core to spawn a new thread for
81 every USB device that is probed. This can cause a small speedup
82 in boot times on systems with a lot of different USB devices.
83
84 This option should be safe to enable, but if any odd probing
85 problems are found, please disable it, or dynamically turn it
86 off in the /sys/module/usbcore/parameters/multithread_probe
87 file
88
89 When in doubt, say N.
75 90
76config USB_OTG 91config USB_OTG
77 bool 92 bool
diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c
index 3538c2fdadfe..ea398e5d50af 100644
--- a/drivers/usb/core/devices.c
+++ b/drivers/usb/core/devices.c
@@ -175,12 +175,13 @@ static char *usb_dump_endpoint_descriptor (
175) 175)
176{ 176{
177 char dir, unit, *type; 177 char dir, unit, *type;
178 unsigned interval, in, bandwidth = 1; 178 unsigned interval, bandwidth = 1;
179 179
180 if (start > end) 180 if (start > end)
181 return start; 181 return start;
182 in = (desc->bEndpointAddress & USB_DIR_IN); 182
183 dir = in ? 'I' : 'O'; 183 dir = usb_endpoint_dir_in(desc) ? 'I' : 'O';
184
184 if (speed == USB_SPEED_HIGH) { 185 if (speed == USB_SPEED_HIGH) {
185 switch (le16_to_cpu(desc->wMaxPacketSize) & (0x03 << 11)) { 186 switch (le16_to_cpu(desc->wMaxPacketSize) & (0x03 << 11)) {
186 case 1 << 11: bandwidth = 2; break; 187 case 1 << 11: bandwidth = 2; break;
@@ -204,7 +205,7 @@ static char *usb_dump_endpoint_descriptor (
204 break; 205 break;
205 case USB_ENDPOINT_XFER_BULK: 206 case USB_ENDPOINT_XFER_BULK:
206 type = "Bulk"; 207 type = "Bulk";
207 if (speed == USB_SPEED_HIGH && !in) /* uframes per NAK */ 208 if (speed == USB_SPEED_HIGH && dir == 'O') /* uframes per NAK */
208 interval = desc->bInterval; 209 interval = desc->bInterval;
209 else 210 else
210 interval = 0; 211 interval = 0;
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index fed92be63b5e..3ed4cb2d56d9 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -561,7 +561,7 @@ static int usbdev_open(struct inode *inode, struct file *file)
561 dev = inode->i_private; 561 dev = inode->i_private;
562 if (!dev) 562 if (!dev)
563 goto out; 563 goto out;
564 ret = usb_autoresume_device(dev, 1); 564 ret = usb_autoresume_device(dev);
565 if (ret) 565 if (ret)
566 goto out; 566 goto out;
567 567
@@ -609,7 +609,7 @@ static int usbdev_release(struct inode *inode, struct file *file)
609 releaseintf(ps, ifnum); 609 releaseintf(ps, ifnum);
610 } 610 }
611 destroy_all_async(ps); 611 destroy_all_async(ps);
612 usb_autosuspend_device(dev, 1); 612 usb_autosuspend_device(dev);
613 usb_unlock_device(dev); 613 usb_unlock_device(dev);
614 usb_put_dev(dev); 614 usb_put_dev(dev);
615 put_pid(ps->disc_pid); 615 put_pid(ps->disc_pid);
diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c
index 113e484c763e..d6eb5ce1dd1d 100644
--- a/drivers/usb/core/driver.c
+++ b/drivers/usb/core/driver.c
@@ -205,7 +205,7 @@ static int usb_probe_interface(struct device *dev)
205 if (id) { 205 if (id) {
206 dev_dbg(dev, "%s - got id\n", __FUNCTION__); 206 dev_dbg(dev, "%s - got id\n", __FUNCTION__);
207 207
208 error = usb_autoresume_device(udev, 1); 208 error = usb_autoresume_device(udev);
209 if (error) 209 if (error)
210 return error; 210 return error;
211 211
@@ -229,7 +229,7 @@ static int usb_probe_interface(struct device *dev)
229 } else 229 } else
230 intf->condition = USB_INTERFACE_BOUND; 230 intf->condition = USB_INTERFACE_BOUND;
231 231
232 usb_autosuspend_device(udev, 1); 232 usb_autosuspend_device(udev);
233 } 233 }
234 234
235 return error; 235 return error;
@@ -247,7 +247,7 @@ static int usb_unbind_interface(struct device *dev)
247 247
248 /* Autoresume for set_interface call below */ 248 /* Autoresume for set_interface call below */
249 udev = interface_to_usbdev(intf); 249 udev = interface_to_usbdev(intf);
250 error = usb_autoresume_device(udev, 1); 250 error = usb_autoresume_device(udev);
251 251
252 /* release all urbs for this interface */ 252 /* release all urbs for this interface */
253 usb_disable_interface(interface_to_usbdev(intf), intf); 253 usb_disable_interface(interface_to_usbdev(intf), intf);
@@ -265,7 +265,7 @@ static int usb_unbind_interface(struct device *dev)
265 intf->needs_remote_wakeup = 0; 265 intf->needs_remote_wakeup = 0;
266 266
267 if (!error) 267 if (!error)
268 usb_autosuspend_device(udev, 1); 268 usb_autosuspend_device(udev);
269 269
270 return 0; 270 return 0;
271} 271}
@@ -408,6 +408,16 @@ static int usb_match_one_id(struct usb_interface *interface,
408 (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol)) 408 (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
409 return 0; 409 return 0;
410 410
411 /* The interface class, subclass, and protocol should never be
412 * checked for a match if the device class is Vendor Specific,
413 * unless the match record specifies the Vendor ID. */
414 if (dev->descriptor.bDeviceClass == USB_CLASS_VENDOR_SPEC &&
415 !(id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
416 (id->match_flags & (USB_DEVICE_ID_MATCH_INT_CLASS |
417 USB_DEVICE_ID_MATCH_INT_SUBCLASS |
418 USB_DEVICE_ID_MATCH_INT_PROTOCOL)))
419 return 0;
420
411 if ((id->match_flags & USB_DEVICE_ID_MATCH_INT_CLASS) && 421 if ((id->match_flags & USB_DEVICE_ID_MATCH_INT_CLASS) &&
412 (id->bInterfaceClass != intf->desc.bInterfaceClass)) 422 (id->bInterfaceClass != intf->desc.bInterfaceClass))
413 return 0; 423 return 0;
@@ -476,7 +486,17 @@ static int usb_match_one_id(struct usb_interface *interface,
476 * most general; they let drivers bind to any interface on a 486 * most general; they let drivers bind to any interface on a
477 * multiple-function device. Use the USB_INTERFACE_INFO 487 * multiple-function device. Use the USB_INTERFACE_INFO
478 * macro, or its siblings, to match class-per-interface style 488 * macro, or its siblings, to match class-per-interface style
479 * devices (as recorded in bDeviceClass). 489 * devices (as recorded in bInterfaceClass).
490 *
491 * Note that an entry created by USB_INTERFACE_INFO won't match
492 * any interface if the device class is set to Vendor-Specific.
493 * This is deliberate; according to the USB spec the meanings of
494 * the interface class/subclass/protocol for these devices are also
495 * vendor-specific, and hence matching against a standard product
496 * class wouldn't work anyway. If you really want to use an
497 * interface-based match for such a device, create a match record
498 * that also specifies the vendor ID. (Unforunately there isn't a
499 * standard macro for creating records like this.)
480 * 500 *
481 * Within those groups, remember that not all combinations are 501 * Within those groups, remember that not all combinations are
482 * meaningful. For example, don't give a product version range 502 * meaningful. For example, don't give a product version range
@@ -505,7 +525,7 @@ const struct usb_device_id *usb_match_id(struct usb_interface *interface,
505} 525}
506EXPORT_SYMBOL_GPL_FUTURE(usb_match_id); 526EXPORT_SYMBOL_GPL_FUTURE(usb_match_id);
507 527
508int usb_device_match(struct device *dev, struct device_driver *drv) 528static int usb_device_match(struct device *dev, struct device_driver *drv)
509{ 529{
510 /* devices and interfaces are handled separately */ 530 /* devices and interfaces are handled separately */
511 if (is_usb_device(dev)) { 531 if (is_usb_device(dev)) {
@@ -790,7 +810,7 @@ EXPORT_SYMBOL_GPL_FUTURE(usb_deregister);
790#ifdef CONFIG_PM 810#ifdef CONFIG_PM
791 811
792/* Caller has locked udev's pm_mutex */ 812/* Caller has locked udev's pm_mutex */
793static int suspend_device(struct usb_device *udev, pm_message_t msg) 813static int usb_suspend_device(struct usb_device *udev, pm_message_t msg)
794{ 814{
795 struct usb_device_driver *udriver; 815 struct usb_device_driver *udriver;
796 int status = 0; 816 int status = 0;
@@ -817,7 +837,7 @@ done:
817} 837}
818 838
819/* Caller has locked udev's pm_mutex */ 839/* Caller has locked udev's pm_mutex */
820static int resume_device(struct usb_device *udev) 840static int usb_resume_device(struct usb_device *udev)
821{ 841{
822 struct usb_device_driver *udriver; 842 struct usb_device_driver *udriver;
823 int status = 0; 843 int status = 0;
@@ -843,7 +863,7 @@ done:
843} 863}
844 864
845/* Caller has locked intf's usb_device's pm mutex */ 865/* Caller has locked intf's usb_device's pm mutex */
846static int suspend_interface(struct usb_interface *intf, pm_message_t msg) 866static int usb_suspend_interface(struct usb_interface *intf, pm_message_t msg)
847{ 867{
848 struct usb_driver *driver; 868 struct usb_driver *driver;
849 int status = 0; 869 int status = 0;
@@ -880,7 +900,7 @@ done:
880} 900}
881 901
882/* Caller has locked intf's usb_device's pm_mutex */ 902/* Caller has locked intf's usb_device's pm_mutex */
883static int resume_interface(struct usb_interface *intf) 903static int usb_resume_interface(struct usb_interface *intf)
884{ 904{
885 struct usb_driver *driver; 905 struct usb_driver *driver;
886 int status = 0; 906 int status = 0;
@@ -920,6 +940,44 @@ done:
920 return status; 940 return status;
921} 941}
922 942
943#ifdef CONFIG_USB_SUSPEND
944
945/* Internal routine to check whether we may autosuspend a device. */
946static int autosuspend_check(struct usb_device *udev)
947{
948 int i;
949 struct usb_interface *intf;
950
951 /* For autosuspend, fail fast if anything is in use.
952 * Also fail if any interfaces require remote wakeup but it
953 * isn't available. */
954 udev->do_remote_wakeup = device_may_wakeup(&udev->dev);
955 if (udev->pm_usage_cnt > 0)
956 return -EBUSY;
957 if (udev->actconfig) {
958 for (i = 0; i < udev->actconfig->desc.bNumInterfaces; i++) {
959 intf = udev->actconfig->interface[i];
960 if (!is_active(intf))
961 continue;
962 if (intf->pm_usage_cnt > 0)
963 return -EBUSY;
964 if (intf->needs_remote_wakeup &&
965 !udev->do_remote_wakeup) {
966 dev_dbg(&udev->dev, "remote wakeup needed "
967 "for autosuspend\n");
968 return -EOPNOTSUPP;
969 }
970 }
971 }
972 return 0;
973}
974
975#else
976
977#define autosuspend_check(udev) 0
978
979#endif
980
923/** 981/**
924 * usb_suspend_both - suspend a USB device and its interfaces 982 * usb_suspend_both - suspend a USB device and its interfaces
925 * @udev: the usb_device to suspend 983 * @udev: the usb_device to suspend
@@ -971,52 +1029,34 @@ int usb_suspend_both(struct usb_device *udev, pm_message_t msg)
971 1029
972 udev->do_remote_wakeup = device_may_wakeup(&udev->dev); 1030 udev->do_remote_wakeup = device_may_wakeup(&udev->dev);
973 1031
974 /* For autosuspend, fail fast if anything is in use.
975 * Also fail if any interfaces require remote wakeup but it
976 * isn't available. */
977 if (udev->auto_pm) { 1032 if (udev->auto_pm) {
978 if (udev->pm_usage_cnt > 0) 1033 status = autosuspend_check(udev);
979 return -EBUSY; 1034 if (status < 0)
980 if (udev->actconfig) { 1035 return status;
981 for (; i < udev->actconfig->desc.bNumInterfaces; i++) {
982 intf = udev->actconfig->interface[i];
983 if (!is_active(intf))
984 continue;
985 if (intf->pm_usage_cnt > 0)
986 return -EBUSY;
987 if (intf->needs_remote_wakeup &&
988 !udev->do_remote_wakeup) {
989 dev_dbg(&udev->dev,
990 "remote wakeup needed for autosuspend\n");
991 return -EOPNOTSUPP;
992 }
993 }
994 i = 0;
995 }
996 } 1036 }
997 1037
998 /* Suspend all the interfaces and then udev itself */ 1038 /* Suspend all the interfaces and then udev itself */
999 if (udev->actconfig) { 1039 if (udev->actconfig) {
1000 for (; i < udev->actconfig->desc.bNumInterfaces; i++) { 1040 for (; i < udev->actconfig->desc.bNumInterfaces; i++) {
1001 intf = udev->actconfig->interface[i]; 1041 intf = udev->actconfig->interface[i];
1002 status = suspend_interface(intf, msg); 1042 status = usb_suspend_interface(intf, msg);
1003 if (status != 0) 1043 if (status != 0)
1004 break; 1044 break;
1005 } 1045 }
1006 } 1046 }
1007 if (status == 0) 1047 if (status == 0)
1008 status = suspend_device(udev, msg); 1048 status = usb_suspend_device(udev, msg);
1009 1049
1010 /* If the suspend failed, resume interfaces that did get suspended */ 1050 /* If the suspend failed, resume interfaces that did get suspended */
1011 if (status != 0) { 1051 if (status != 0) {
1012 while (--i >= 0) { 1052 while (--i >= 0) {
1013 intf = udev->actconfig->interface[i]; 1053 intf = udev->actconfig->interface[i];
1014 resume_interface(intf); 1054 usb_resume_interface(intf);
1015 } 1055 }
1016 1056
1017 /* If the suspend succeeded, propagate it up the tree */ 1057 /* If the suspend succeeded, propagate it up the tree */
1018 } else if (parent) 1058 } else if (parent)
1019 usb_autosuspend_device(parent, 0); 1059 usb_autosuspend_device(parent);
1020 1060
1021 // dev_dbg(&udev->dev, "%s: status %d\n", __FUNCTION__, status); 1061 // dev_dbg(&udev->dev, "%s: status %d\n", __FUNCTION__, status);
1022 return status; 1062 return status;
@@ -1064,9 +1104,25 @@ int usb_resume_both(struct usb_device *udev)
1064 /* Propagate the resume up the tree, if necessary */ 1104 /* Propagate the resume up the tree, if necessary */
1065 if (udev->state == USB_STATE_SUSPENDED) { 1105 if (udev->state == USB_STATE_SUSPENDED) {
1066 if (parent) { 1106 if (parent) {
1067 usb_pm_lock(parent); 1107 status = usb_autoresume_device(parent);
1068 parent->auto_pm = 1; 1108 if (status == 0) {
1069 status = usb_resume_both(parent); 1109 status = usb_resume_device(udev);
1110 if (status) {
1111 usb_autosuspend_device(parent);
1112
1113 /* It's possible usb_resume_device()
1114 * failed after the port was
1115 * unsuspended, causing udev to be
1116 * logically disconnected. We don't
1117 * want usb_disconnect() to autosuspend
1118 * the parent again, so tell it that
1119 * udev disconnected while still
1120 * suspended. */
1121 if (udev->state ==
1122 USB_STATE_NOTATTACHED)
1123 udev->discon_suspended = 1;
1124 }
1125 }
1070 } else { 1126 } else {
1071 1127
1072 /* We can't progagate beyond the USB subsystem, 1128 /* We can't progagate beyond the USB subsystem,
@@ -1075,24 +1131,20 @@ int usb_resume_both(struct usb_device *udev)
1075 if (udev->dev.parent->power.power_state.event != 1131 if (udev->dev.parent->power.power_state.event !=
1076 PM_EVENT_ON) 1132 PM_EVENT_ON)
1077 status = -EHOSTUNREACH; 1133 status = -EHOSTUNREACH;
1078 } 1134 else
1079 if (status == 0) 1135 status = usb_resume_device(udev);
1080 status = resume_device(udev); 1136 }
1081 if (parent)
1082 usb_pm_unlock(parent);
1083 } else { 1137 } else {
1084 1138
1085 /* Needed only for setting udev->dev.power.power_state.event 1139 /* Needed only for setting udev->dev.power.power_state.event
1086 * and for possible debugging message. */ 1140 * and for possible debugging message. */
1087 status = resume_device(udev); 1141 status = usb_resume_device(udev);
1088 } 1142 }
1089 1143
1090 /* Now the parent won't suspend until we are finished */
1091
1092 if (status == 0 && udev->actconfig) { 1144 if (status == 0 && udev->actconfig) {
1093 for (i = 0; i < udev->actconfig->desc.bNumInterfaces; i++) { 1145 for (i = 0; i < udev->actconfig->desc.bNumInterfaces; i++) {
1094 intf = udev->actconfig->interface[i]; 1146 intf = udev->actconfig->interface[i];
1095 resume_interface(intf); 1147 usb_resume_interface(intf);
1096 } 1148 }
1097 } 1149 }
1098 1150
@@ -1102,39 +1154,53 @@ int usb_resume_both(struct usb_device *udev)
1102 1154
1103#ifdef CONFIG_USB_SUSPEND 1155#ifdef CONFIG_USB_SUSPEND
1104 1156
1157/* Internal routine to adjust a device's usage counter and change
1158 * its autosuspend state.
1159 */
1160static int usb_autopm_do_device(struct usb_device *udev, int inc_usage_cnt)
1161{
1162 int status = 0;
1163
1164 usb_pm_lock(udev);
1165 udev->pm_usage_cnt += inc_usage_cnt;
1166 WARN_ON(udev->pm_usage_cnt < 0);
1167 if (inc_usage_cnt >= 0 && udev->pm_usage_cnt > 0) {
1168 udev->auto_pm = 1;
1169 status = usb_resume_both(udev);
1170 if (status != 0)
1171 udev->pm_usage_cnt -= inc_usage_cnt;
1172 } else if (inc_usage_cnt <= 0 && autosuspend_check(udev) == 0)
1173 queue_delayed_work(ksuspend_usb_wq, &udev->autosuspend,
1174 USB_AUTOSUSPEND_DELAY);
1175 usb_pm_unlock(udev);
1176 return status;
1177}
1178
1105/** 1179/**
1106 * usb_autosuspend_device - delayed autosuspend of a USB device and its interfaces 1180 * usb_autosuspend_device - delayed autosuspend of a USB device and its interfaces
1107 * @udev: the usb_device to autosuspend 1181 * @udev: the usb_device to autosuspend
1108 * @dec_usage_cnt: flag to decrement @udev's PM-usage counter
1109 * 1182 *
1110 * This routine should be called when a core subsystem is finished using 1183 * This routine should be called when a core subsystem is finished using
1111 * @udev and wants to allow it to autosuspend. Examples would be when 1184 * @udev and wants to allow it to autosuspend. Examples would be when
1112 * @udev's device file in usbfs is closed or after a configuration change. 1185 * @udev's device file in usbfs is closed or after a configuration change.
1113 * 1186 *
1114 * @dec_usage_cnt should be 1 if the subsystem previously incremented 1187 * @udev's usage counter is decremented. If it or any of the usage counters
1115 * @udev's usage counter (such as by passing 1 to usb_autoresume_device); 1188 * for an active interface is greater than 0, no autosuspend request will be
1116 * otherwise it should be 0. 1189 * queued. (If an interface driver does not support autosuspend then its
1117 * 1190 * usage counter is permanently positive.) Furthermore, if an interface
1118 * If the usage counter for @udev or any of its active interfaces is greater 1191 * driver requires remote-wakeup capability during autosuspend but remote
1119 * than 0, the autosuspend request will not be queued. (If an interface 1192 * wakeup is disabled, the autosuspend will fail.
1120 * driver does not support autosuspend then its usage counter is permanently
1121 * positive.) Likewise, if an interface driver requires remote-wakeup
1122 * capability during autosuspend but remote wakeup is disabled, the
1123 * autosuspend will fail.
1124 * 1193 *
1125 * Often the caller will hold @udev's device lock, but this is not 1194 * Often the caller will hold @udev's device lock, but this is not
1126 * necessary. 1195 * necessary.
1127 * 1196 *
1128 * This routine can run only in process context. 1197 * This routine can run only in process context.
1129 */ 1198 */
1130void usb_autosuspend_device(struct usb_device *udev, int dec_usage_cnt) 1199void usb_autosuspend_device(struct usb_device *udev)
1131{ 1200{
1132 usb_pm_lock(udev); 1201 int status;
1133 udev->pm_usage_cnt -= dec_usage_cnt; 1202
1134 if (udev->pm_usage_cnt <= 0) 1203 status = usb_autopm_do_device(udev, -1);
1135 queue_delayed_work(ksuspend_usb_wq, &udev->autosuspend,
1136 USB_AUTOSUSPEND_DELAY);
1137 usb_pm_unlock(udev);
1138 // dev_dbg(&udev->dev, "%s: cnt %d\n", 1204 // dev_dbg(&udev->dev, "%s: cnt %d\n",
1139 // __FUNCTION__, udev->pm_usage_cnt); 1205 // __FUNCTION__, udev->pm_usage_cnt);
1140} 1206}
@@ -1142,44 +1208,59 @@ void usb_autosuspend_device(struct usb_device *udev, int dec_usage_cnt)
1142/** 1208/**
1143 * usb_autoresume_device - immediately autoresume a USB device and its interfaces 1209 * usb_autoresume_device - immediately autoresume a USB device and its interfaces
1144 * @udev: the usb_device to autoresume 1210 * @udev: the usb_device to autoresume
1145 * @inc_usage_cnt: flag to increment @udev's PM-usage counter
1146 * 1211 *
1147 * This routine should be called when a core subsystem wants to use @udev 1212 * This routine should be called when a core subsystem wants to use @udev
1148 * and needs to guarantee that it is not suspended. In addition, the 1213 * and needs to guarantee that it is not suspended. No autosuspend will
1149 * caller can prevent @udev from being autosuspended subsequently. (Note 1214 * occur until usb_autosuspend_device is called. (Note that this will not
1150 * that this will not prevent suspend events originating in the PM core.) 1215 * prevent suspend events originating in the PM core.) Examples would be
1151 * Examples would be when @udev's device file in usbfs is opened (autosuspend 1216 * when @udev's device file in usbfs is opened or when a remote-wakeup
1152 * should be prevented until the file is closed) or when a remote-wakeup 1217 * request is received.
1153 * request is received (later autosuspends should not be prevented).
1154 * 1218 *
1155 * @inc_usage_cnt should be 1 to increment @udev's usage counter and prevent 1219 * @udev's usage counter is incremented to prevent subsequent autosuspends.
1156 * autosuspends. This prevention will persist until the usage counter is 1220 * However if the autoresume fails then the usage counter is re-decremented.
1157 * decremented again (such as by passing 1 to usb_autosuspend_device).
1158 * Otherwise @inc_usage_cnt should be 0 to leave the usage counter unchanged.
1159 * Regardless, if the autoresume fails then the usage counter is not
1160 * incremented.
1161 * 1221 *
1162 * Often the caller will hold @udev's device lock, but this is not 1222 * Often the caller will hold @udev's device lock, but this is not
1163 * necessary (and attempting it might cause deadlock). 1223 * necessary (and attempting it might cause deadlock).
1164 * 1224 *
1165 * This routine can run only in process context. 1225 * This routine can run only in process context.
1166 */ 1226 */
1167int usb_autoresume_device(struct usb_device *udev, int inc_usage_cnt) 1227int usb_autoresume_device(struct usb_device *udev)
1168{ 1228{
1169 int status; 1229 int status;
1170 1230
1171 usb_pm_lock(udev); 1231 status = usb_autopm_do_device(udev, 1);
1172 udev->pm_usage_cnt += inc_usage_cnt;
1173 udev->auto_pm = 1;
1174 status = usb_resume_both(udev);
1175 if (status != 0)
1176 udev->pm_usage_cnt -= inc_usage_cnt;
1177 usb_pm_unlock(udev);
1178 // dev_dbg(&udev->dev, "%s: status %d cnt %d\n", 1232 // dev_dbg(&udev->dev, "%s: status %d cnt %d\n",
1179 // __FUNCTION__, status, udev->pm_usage_cnt); 1233 // __FUNCTION__, status, udev->pm_usage_cnt);
1180 return status; 1234 return status;
1181} 1235}
1182 1236
1237/* Internal routine to adjust an interface's usage counter and change
1238 * its device's autosuspend state.
1239 */
1240static int usb_autopm_do_interface(struct usb_interface *intf,
1241 int inc_usage_cnt)
1242{
1243 struct usb_device *udev = interface_to_usbdev(intf);
1244 int status = 0;
1245
1246 usb_pm_lock(udev);
1247 if (intf->condition == USB_INTERFACE_UNBOUND)
1248 status = -ENODEV;
1249 else {
1250 intf->pm_usage_cnt += inc_usage_cnt;
1251 if (inc_usage_cnt >= 0 && intf->pm_usage_cnt > 0) {
1252 udev->auto_pm = 1;
1253 status = usb_resume_both(udev);
1254 if (status != 0)
1255 intf->pm_usage_cnt -= inc_usage_cnt;
1256 } else if (inc_usage_cnt <= 0 && autosuspend_check(udev) == 0)
1257 queue_delayed_work(ksuspend_usb_wq, &udev->autosuspend,
1258 USB_AUTOSUSPEND_DELAY);
1259 }
1260 usb_pm_unlock(udev);
1261 return status;
1262}
1263
1183/** 1264/**
1184 * usb_autopm_put_interface - decrement a USB interface's PM-usage counter 1265 * usb_autopm_put_interface - decrement a USB interface's PM-usage counter
1185 * @intf: the usb_interface whose counter should be decremented 1266 * @intf: the usb_interface whose counter should be decremented
@@ -1213,17 +1294,11 @@ int usb_autoresume_device(struct usb_device *udev, int inc_usage_cnt)
1213 */ 1294 */
1214void usb_autopm_put_interface(struct usb_interface *intf) 1295void usb_autopm_put_interface(struct usb_interface *intf)
1215{ 1296{
1216 struct usb_device *udev = interface_to_usbdev(intf); 1297 int status;
1217 1298
1218 usb_pm_lock(udev); 1299 status = usb_autopm_do_interface(intf, -1);
1219 if (intf->condition != USB_INTERFACE_UNBOUND && 1300 // dev_dbg(&intf->dev, "%s: status %d cnt %d\n",
1220 --intf->pm_usage_cnt <= 0) { 1301 // __FUNCTION__, status, intf->pm_usage_cnt);
1221 queue_delayed_work(ksuspend_usb_wq, &udev->autosuspend,
1222 USB_AUTOSUSPEND_DELAY);
1223 }
1224 usb_pm_unlock(udev);
1225 // dev_dbg(&intf->dev, "%s: cnt %d\n",
1226 // __FUNCTION__, intf->pm_usage_cnt);
1227} 1302}
1228EXPORT_SYMBOL_GPL(usb_autopm_put_interface); 1303EXPORT_SYMBOL_GPL(usb_autopm_put_interface);
1229 1304
@@ -1260,26 +1335,37 @@ EXPORT_SYMBOL_GPL(usb_autopm_put_interface);
1260 */ 1335 */
1261int usb_autopm_get_interface(struct usb_interface *intf) 1336int usb_autopm_get_interface(struct usb_interface *intf)
1262{ 1337{
1263 struct usb_device *udev = interface_to_usbdev(intf); 1338 int status;
1264 int status;
1265 1339
1266 usb_pm_lock(udev); 1340 status = usb_autopm_do_interface(intf, 1);
1267 if (intf->condition == USB_INTERFACE_UNBOUND)
1268 status = -ENODEV;
1269 else {
1270 ++intf->pm_usage_cnt;
1271 udev->auto_pm = 1;
1272 status = usb_resume_both(udev);
1273 if (status != 0)
1274 --intf->pm_usage_cnt;
1275 }
1276 usb_pm_unlock(udev);
1277 // dev_dbg(&intf->dev, "%s: status %d cnt %d\n", 1341 // dev_dbg(&intf->dev, "%s: status %d cnt %d\n",
1278 // __FUNCTION__, status, intf->pm_usage_cnt); 1342 // __FUNCTION__, status, intf->pm_usage_cnt);
1279 return status; 1343 return status;
1280} 1344}
1281EXPORT_SYMBOL_GPL(usb_autopm_get_interface); 1345EXPORT_SYMBOL_GPL(usb_autopm_get_interface);
1282 1346
1347/**
1348 * usb_autopm_set_interface - set a USB interface's autosuspend state
1349 * @intf: the usb_interface whose state should be set
1350 *
1351 * This routine sets the autosuspend state of @intf's device according
1352 * to @intf's usage counter, which the caller must have set previously.
1353 * If the counter is <= 0, the device is autosuspended (if it isn't
1354 * already suspended and if nothing else prevents the autosuspend). If
1355 * the counter is > 0, the device is autoresumed (if it isn't already
1356 * awake).
1357 */
1358int usb_autopm_set_interface(struct usb_interface *intf)
1359{
1360 int status;
1361
1362 status = usb_autopm_do_interface(intf, 0);
1363 // dev_dbg(&intf->dev, "%s: status %d cnt %d\n",
1364 // __FUNCTION__, status, intf->pm_usage_cnt);
1365 return status;
1366}
1367EXPORT_SYMBOL_GPL(usb_autopm_set_interface);
1368
1283#endif /* CONFIG_USB_SUSPEND */ 1369#endif /* CONFIG_USB_SUSPEND */
1284 1370
1285static int usb_suspend(struct device *dev, pm_message_t message) 1371static int usb_suspend(struct device *dev, pm_message_t message)
diff --git a/drivers/usb/core/endpoint.c b/drivers/usb/core/endpoint.c
index 3b2d137912be..c505b767cee1 100644
--- a/drivers/usb/core/endpoint.c
+++ b/drivers/usb/core/endpoint.c
@@ -10,15 +10,20 @@
10 */ 10 */
11 11
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/spinlock.h>
14#include <linux/idr.h>
13#include <linux/usb.h> 15#include <linux/usb.h>
14#include "usb.h" 16#include "usb.h"
15 17
16/* endpoint stuff */ 18#define MAX_ENDPOINT_MINORS (64*128*32)
19static int usb_endpoint_major;
20static DEFINE_IDR(endpoint_idr);
17 21
18struct ep_device { 22struct ep_device {
19 struct usb_endpoint_descriptor *desc; 23 struct usb_endpoint_descriptor *desc;
20 struct usb_device *udev; 24 struct usb_device *udev;
21 struct device dev; 25 struct device dev;
26 int minor;
22}; 27};
23#define to_ep_device(_dev) \ 28#define to_ep_device(_dev) \
24 container_of(_dev, struct ep_device, dev) 29 container_of(_dev, struct ep_device, dev)
@@ -152,6 +157,55 @@ static struct attribute_group ep_dev_attr_grp = {
152 .attrs = ep_dev_attrs, 157 .attrs = ep_dev_attrs,
153}; 158};
154 159
160static int usb_endpoint_major_init(void)
161{
162 dev_t dev;
163 int error;
164
165 error = alloc_chrdev_region(&dev, 0, MAX_ENDPOINT_MINORS,
166 "usb_endpoint");
167 if (error) {
168 err("unable to get a dynamic major for usb endpoints");
169 return error;
170 }
171 usb_endpoint_major = MAJOR(dev);
172
173 return error;
174}
175
176static void usb_endpoint_major_cleanup(void)
177{
178 unregister_chrdev_region(MKDEV(usb_endpoint_major, 0),
179 MAX_ENDPOINT_MINORS);
180}
181
182static int endpoint_get_minor(struct ep_device *ep_dev)
183{
184 static DEFINE_MUTEX(minor_lock);
185 int retval = -ENOMEM;
186 int id;
187
188 mutex_lock(&minor_lock);
189 if (idr_pre_get(&endpoint_idr, GFP_KERNEL) == 0)
190 goto exit;
191
192 retval = idr_get_new(&endpoint_idr, ep_dev, &id);
193 if (retval < 0) {
194 if (retval == -EAGAIN)
195 retval = -ENOMEM;
196 goto exit;
197 }
198 ep_dev->minor = id & MAX_ID_MASK;
199exit:
200 mutex_unlock(&minor_lock);
201 return retval;
202}
203
204static void endpoint_free_minor(struct ep_device *ep_dev)
205{
206 idr_remove(&endpoint_idr, ep_dev->minor);
207}
208
155static struct endpoint_class { 209static struct endpoint_class {
156 struct kref kref; 210 struct kref kref;
157 struct class *class; 211 struct class *class;
@@ -176,11 +230,20 @@ static int init_endpoint_class(void)
176 ep_class->class = class_create(THIS_MODULE, "usb_endpoint"); 230 ep_class->class = class_create(THIS_MODULE, "usb_endpoint");
177 if (IS_ERR(ep_class->class)) { 231 if (IS_ERR(ep_class->class)) {
178 result = IS_ERR(ep_class->class); 232 result = IS_ERR(ep_class->class);
179 kfree(ep_class); 233 goto class_create_error;
180 ep_class = NULL;
181 goto exit;
182 } 234 }
183 235
236 result = usb_endpoint_major_init();
237 if (result)
238 goto endpoint_major_error;
239
240 goto exit;
241
242endpoint_major_error:
243 class_destroy(ep_class->class);
244class_create_error:
245 kfree(ep_class);
246 ep_class = NULL;
184exit: 247exit:
185 return result; 248 return result;
186} 249}
@@ -191,6 +254,7 @@ static void release_endpoint_class(struct kref *kref)
191 class_destroy(ep_class->class); 254 class_destroy(ep_class->class);
192 kfree(ep_class); 255 kfree(ep_class);
193 ep_class = NULL; 256 ep_class = NULL;
257 usb_endpoint_major_cleanup();
194} 258}
195 259
196static void destroy_endpoint_class(void) 260static void destroy_endpoint_class(void)
@@ -213,7 +277,6 @@ int usb_create_ep_files(struct device *parent,
213{ 277{
214 char name[8]; 278 char name[8];
215 struct ep_device *ep_dev; 279 struct ep_device *ep_dev;
216 int minor;
217 int retval; 280 int retval;
218 281
219 retval = init_endpoint_class(); 282 retval = init_endpoint_class();
@@ -226,12 +289,16 @@ int usb_create_ep_files(struct device *parent,
226 goto error_alloc; 289 goto error_alloc;
227 } 290 }
228 291
229 /* fun calculation to determine the minor of this endpoint */ 292 retval = endpoint_get_minor(ep_dev);
230 minor = (((udev->bus->busnum - 1) * 128) * 16) + (udev->devnum - 1); 293 if (retval) {
294 dev_err(parent, "can not allocate minor number for %s",
295 ep_dev->dev.bus_id);
296 goto error_register;
297 }
231 298
232 ep_dev->desc = &endpoint->desc; 299 ep_dev->desc = &endpoint->desc;
233 ep_dev->udev = udev; 300 ep_dev->udev = udev;
234 ep_dev->dev.devt = MKDEV(442, minor); // FIXME fake number... 301 ep_dev->dev.devt = MKDEV(usb_endpoint_major, ep_dev->minor);
235 ep_dev->dev.class = ep_class->class; 302 ep_dev->dev.class = ep_class->class;
236 ep_dev->dev.parent = parent; 303 ep_dev->dev.parent = parent;
237 ep_dev->dev.release = ep_device_release; 304 ep_dev->dev.release = ep_device_release;
@@ -241,7 +308,7 @@ int usb_create_ep_files(struct device *parent,
241 308
242 retval = device_register(&ep_dev->dev); 309 retval = device_register(&ep_dev->dev);
243 if (retval) 310 if (retval)
244 goto error_register; 311 goto error_chrdev;
245 retval = sysfs_create_group(&ep_dev->dev.kobj, &ep_dev_attr_grp); 312 retval = sysfs_create_group(&ep_dev->dev.kobj, &ep_dev_attr_grp);
246 if (retval) 313 if (retval)
247 goto error_group; 314 goto error_group;
@@ -261,6 +328,9 @@ error_group:
261 destroy_endpoint_class(); 328 destroy_endpoint_class();
262 return retval; 329 return retval;
263 330
331error_chrdev:
332 endpoint_free_minor(ep_dev);
333
264error_register: 334error_register:
265 kfree(ep_dev); 335 kfree(ep_dev);
266error_alloc: 336error_alloc:
@@ -271,14 +341,16 @@ exit:
271 341
272void usb_remove_ep_files(struct usb_host_endpoint *endpoint) 342void usb_remove_ep_files(struct usb_host_endpoint *endpoint)
273{ 343{
344 struct ep_device *ep_dev = endpoint->ep_dev;
274 345
275 if (endpoint->ep_dev) { 346 if (ep_dev) {
276 char name[8]; 347 char name[8];
277 348
278 sprintf(name, "ep_%02x", endpoint->desc.bEndpointAddress); 349 sprintf(name, "ep_%02x", endpoint->desc.bEndpointAddress);
279 sysfs_remove_link(&endpoint->ep_dev->dev.parent->kobj, name); 350 sysfs_remove_link(&ep_dev->dev.parent->kobj, name);
280 sysfs_remove_group(&endpoint->ep_dev->dev.kobj, &ep_dev_attr_grp); 351 sysfs_remove_group(&ep_dev->dev.kobj, &ep_dev_attr_grp);
281 device_unregister(&endpoint->ep_dev->dev); 352 endpoint_free_minor(ep_dev);
353 device_unregister(&ep_dev->dev);
282 endpoint->ep_dev = NULL; 354 endpoint->ep_dev = NULL;
283 destroy_endpoint_class(); 355 destroy_endpoint_class();
284 } 356 }
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index afa2dd203329..10064af65d17 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -256,7 +256,9 @@ static const u8 hs_rh_config_descriptor [] = {
256 0x05, /* __u8 ep_bDescriptorType; Endpoint */ 256 0x05, /* __u8 ep_bDescriptorType; Endpoint */
257 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ 257 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
258 0x03, /* __u8 ep_bmAttributes; Interrupt */ 258 0x03, /* __u8 ep_bmAttributes; Interrupt */
259 0x02, 0x00, /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8) */ 259 /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8)
260 * see hub.c:hub_configure() for details. */
261 (USB_MAXCHILDREN + 1 + 7) / 8, 0x00,
260 0x0c /* __u8 ep_bInterval; (256ms -- usb 2.0 spec) */ 262 0x0c /* __u8 ep_bInterval; (256ms -- usb 2.0 spec) */
261}; 263};
262 264
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index ad0ffbe8f7d7..39186db1015f 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -31,6 +31,47 @@
31#include "hcd.h" 31#include "hcd.h"
32#include "hub.h" 32#include "hub.h"
33 33
34struct usb_hub {
35 struct device *intfdev; /* the "interface" device */
36 struct usb_device *hdev;
37 struct urb *urb; /* for interrupt polling pipe */
38
39 /* buffer for urb ... with extra space in case of babble */
40 char (*buffer)[8];
41 dma_addr_t buffer_dma; /* DMA address for buffer */
42 union {
43 struct usb_hub_status hub;
44 struct usb_port_status port;
45 } *status; /* buffer for status reports */
46
47 int error; /* last reported error */
48 int nerrors; /* track consecutive errors */
49
50 struct list_head event_list; /* hubs w/data or errs ready */
51 unsigned long event_bits[1]; /* status change bitmask */
52 unsigned long change_bits[1]; /* ports with logical connect
53 status change */
54 unsigned long busy_bits[1]; /* ports being reset or
55 resumed */
56#if USB_MAXCHILDREN > 31 /* 8*sizeof(unsigned long) - 1 */
57#error event_bits[] is too short!
58#endif
59
60 struct usb_hub_descriptor *descriptor; /* class descriptor */
61 struct usb_tt tt; /* Transaction Translator */
62
63 unsigned mA_per_port; /* current for each child */
64
65 unsigned limited_power:1;
66 unsigned quiescing:1;
67 unsigned activating:1;
68
69 unsigned has_indicators:1;
70 u8 indicator[USB_MAXCHILDREN];
71 struct work_struct leds;
72};
73
74
34/* Protect struct usb_device->state and ->children members 75/* Protect struct usb_device->state and ->children members
35 * Note: Both are also protected by ->dev.sem, except that ->state can 76 * Note: Both are also protected by ->dev.sem, except that ->state can
36 * change to USB_STATE_NOTATTACHED even when the semaphore isn't held. */ 77 * change to USB_STATE_NOTATTACHED even when the semaphore isn't held. */
@@ -45,6 +86,16 @@ static DECLARE_WAIT_QUEUE_HEAD(khubd_wait);
45 86
46static struct task_struct *khubd_task; 87static struct task_struct *khubd_task;
47 88
89/* multithreaded probe logic */
90static int multithread_probe =
91#ifdef CONFIG_USB_MULTITHREAD_PROBE
92 1;
93#else
94 0;
95#endif
96module_param(multithread_probe, bool, S_IRUGO);
97MODULE_PARM_DESC(multithread_probe, "Run each USB device probe in a new thread");
98
48/* cycle leds on hubs that aren't blinking for attention */ 99/* cycle leds on hubs that aren't blinking for attention */
49static int blinkenlights = 0; 100static int blinkenlights = 0;
50module_param (blinkenlights, bool, S_IRUGO); 101module_param (blinkenlights, bool, S_IRUGO);
@@ -277,6 +328,9 @@ static void kick_khubd(struct usb_hub *hub)
277{ 328{
278 unsigned long flags; 329 unsigned long flags;
279 330
331 /* Suppress autosuspend until khubd runs */
332 to_usb_interface(hub->intfdev)->pm_usage_cnt = 1;
333
280 spin_lock_irqsave(&hub_event_lock, flags); 334 spin_lock_irqsave(&hub_event_lock, flags);
281 if (list_empty(&hub->event_list)) { 335 if (list_empty(&hub->event_list)) {
282 list_add_tail(&hub->event_list, &hub_event_list); 336 list_add_tail(&hub->event_list, &hub_event_list);
@@ -459,7 +513,6 @@ static void hub_quiesce(struct usb_hub *hub)
459 /* (nonblocking) khubd and related activity won't re-trigger */ 513 /* (nonblocking) khubd and related activity won't re-trigger */
460 hub->quiescing = 1; 514 hub->quiescing = 1;
461 hub->activating = 0; 515 hub->activating = 0;
462 hub->resume_root_hub = 0;
463 516
464 /* (blocking) stop khubd and related activity */ 517 /* (blocking) stop khubd and related activity */
465 usb_kill_urb(hub->urb); 518 usb_kill_urb(hub->urb);
@@ -475,7 +528,7 @@ static void hub_activate(struct usb_hub *hub)
475 528
476 hub->quiescing = 0; 529 hub->quiescing = 0;
477 hub->activating = 1; 530 hub->activating = 1;
478 hub->resume_root_hub = 0; 531
479 status = usb_submit_urb(hub->urb, GFP_NOIO); 532 status = usb_submit_urb(hub->urb, GFP_NOIO);
480 if (status < 0) 533 if (status < 0)
481 dev_err(hub->intfdev, "activate --> %d\n", status); 534 dev_err(hub->intfdev, "activate --> %d\n", status);
@@ -761,7 +814,12 @@ static int hub_configure(struct usb_hub *hub,
761 dev_dbg(hub_dev, "%sover-current condition exists\n", 814 dev_dbg(hub_dev, "%sover-current condition exists\n",
762 (hubstatus & HUB_STATUS_OVERCURRENT) ? "" : "no "); 815 (hubstatus & HUB_STATUS_OVERCURRENT) ? "" : "no ");
763 816
764 /* set up the interrupt endpoint */ 817 /* set up the interrupt endpoint
818 * We use the EP's maxpacket size instead of (PORTS+1+7)/8
819 * bytes as USB2.0[11.12.3] says because some hubs are known
820 * to send more data (and thus cause overflow). For root hubs,
821 * maxpktsize is defined in hcd.c's fake endpoint descriptors
822 * to be big enough for at least USB_MAXCHILDREN ports. */
765 pipe = usb_rcvintpipe(hdev, endpoint->bEndpointAddress); 823 pipe = usb_rcvintpipe(hdev, endpoint->bEndpointAddress);
766 maxp = usb_maxpacket(hdev, pipe, usb_pipeout(pipe)); 824 maxp = usb_maxpacket(hdev, pipe, usb_pipeout(pipe));
767 825
@@ -885,6 +943,7 @@ descriptor_error:
885 INIT_DELAYED_WORK(&hub->leds, led_work); 943 INIT_DELAYED_WORK(&hub->leds, led_work);
886 944
887 usb_set_intfdata (intf, hub); 945 usb_set_intfdata (intf, hub);
946 intf->needs_remote_wakeup = 1;
888 947
889 if (hdev->speed == USB_SPEED_HIGH) 948 if (hdev->speed == USB_SPEED_HIGH)
890 highspeed_hubs++; 949 highspeed_hubs++;
@@ -982,6 +1041,8 @@ static void recursively_mark_NOTATTACHED(struct usb_device *udev)
982 if (udev->children[i]) 1041 if (udev->children[i])
983 recursively_mark_NOTATTACHED(udev->children[i]); 1042 recursively_mark_NOTATTACHED(udev->children[i]);
984 } 1043 }
1044 if (udev->state == USB_STATE_SUSPENDED)
1045 udev->discon_suspended = 1;
985 udev->state = USB_STATE_NOTATTACHED; 1046 udev->state = USB_STATE_NOTATTACHED;
986} 1047}
987 1048
@@ -1171,6 +1232,14 @@ void usb_disconnect(struct usb_device **pdev)
1171 *pdev = NULL; 1232 *pdev = NULL;
1172 spin_unlock_irq(&device_state_lock); 1233 spin_unlock_irq(&device_state_lock);
1173 1234
1235 /* Decrement the parent's count of unsuspended children */
1236 if (udev->parent) {
1237 usb_pm_lock(udev);
1238 if (!udev->discon_suspended)
1239 usb_autosuspend_device(udev->parent);
1240 usb_pm_unlock(udev);
1241 }
1242
1174 put_device(&udev->dev); 1243 put_device(&udev->dev);
1175} 1244}
1176 1245
@@ -1193,29 +1262,17 @@ static inline void show_string(struct usb_device *udev, char *id, char *string)
1193static int __usb_port_suspend(struct usb_device *, int port1); 1262static int __usb_port_suspend(struct usb_device *, int port1);
1194#endif 1263#endif
1195 1264
1196/** 1265static int __usb_new_device(void *void_data)
1197 * usb_new_device - perform initial device setup (usbcore-internal)
1198 * @udev: newly addressed device (in ADDRESS state)
1199 *
1200 * This is called with devices which have been enumerated, but not yet
1201 * configured. The device descriptor is available, but not descriptors
1202 * for any device configuration. The caller must have locked either
1203 * the parent hub (if udev is a normal device) or else the
1204 * usb_bus_list_lock (if udev is a root hub). The parent's pointer to
1205 * udev has already been installed, but udev is not yet visible through
1206 * sysfs or other filesystem code.
1207 *
1208 * Returns 0 for success (device is configured and listed, with its
1209 * interfaces, in sysfs); else a negative errno value.
1210 *
1211 * This call is synchronous, and may not be used in an interrupt context.
1212 *
1213 * Only the hub driver or root-hub registrar should ever call this.
1214 */
1215int usb_new_device(struct usb_device *udev)
1216{ 1266{
1267 struct usb_device *udev = void_data;
1217 int err; 1268 int err;
1218 1269
1270 /* Lock ourself into memory in order to keep a probe sequence
1271 * sleeping in a new thread from allowing us to be unloaded.
1272 */
1273 if (!try_module_get(THIS_MODULE))
1274 return -EINVAL;
1275
1219 err = usb_get_configuration(udev); 1276 err = usb_get_configuration(udev);
1220 if (err < 0) { 1277 if (err < 0) {
1221 dev_err(&udev->dev, "can't read configurations, error %d\n", 1278 dev_err(&udev->dev, "can't read configurations, error %d\n",
@@ -1311,13 +1368,56 @@ int usb_new_device(struct usb_device *udev)
1311 goto fail; 1368 goto fail;
1312 } 1369 }
1313 1370
1314 return 0; 1371 /* Increment the parent's count of unsuspended children */
1372 if (udev->parent)
1373 usb_autoresume_device(udev->parent);
1374
1375exit:
1376 module_put(THIS_MODULE);
1377 return err;
1315 1378
1316fail: 1379fail:
1317 usb_set_device_state(udev, USB_STATE_NOTATTACHED); 1380 usb_set_device_state(udev, USB_STATE_NOTATTACHED);
1318 return err; 1381 goto exit;
1319} 1382}
1320 1383
1384/**
1385 * usb_new_device - perform initial device setup (usbcore-internal)
1386 * @udev: newly addressed device (in ADDRESS state)
1387 *
1388 * This is called with devices which have been enumerated, but not yet
1389 * configured. The device descriptor is available, but not descriptors
1390 * for any device configuration. The caller must have locked either
1391 * the parent hub (if udev is a normal device) or else the
1392 * usb_bus_list_lock (if udev is a root hub). The parent's pointer to
1393 * udev has already been installed, but udev is not yet visible through
1394 * sysfs or other filesystem code.
1395 *
1396 * The return value for this function depends on if the
1397 * multithread_probe variable is set or not. If it's set, it will
1398 * return a if the probe thread was successfully created or not. If the
1399 * variable is not set, it will return if the device is configured
1400 * properly or not. interfaces, in sysfs); else a negative errno value.
1401 *
1402 * This call is synchronous, and may not be used in an interrupt context.
1403 *
1404 * Only the hub driver or root-hub registrar should ever call this.
1405 */
1406int usb_new_device(struct usb_device *udev)
1407{
1408 struct task_struct *probe_task;
1409 int ret = 0;
1410
1411 if (multithread_probe) {
1412 probe_task = kthread_run(__usb_new_device, udev,
1413 "usb-probe-%s", udev->devnum);
1414 if (IS_ERR(probe_task))
1415 ret = PTR_ERR(probe_task);
1416 } else
1417 ret = __usb_new_device(udev);
1418
1419 return ret;
1420}
1321 1421
1322static int hub_port_status(struct usb_hub *hub, int port1, 1422static int hub_port_status(struct usb_hub *hub, int port1,
1323 u16 *status, u16 *change) 1423 u16 *status, u16 *change)
@@ -1325,10 +1425,12 @@ static int hub_port_status(struct usb_hub *hub, int port1,
1325 int ret; 1425 int ret;
1326 1426
1327 ret = get_port_status(hub->hdev, port1, &hub->status->port); 1427 ret = get_port_status(hub->hdev, port1, &hub->status->port);
1328 if (ret < 0) 1428 if (ret < 4) {
1329 dev_err (hub->intfdev, 1429 dev_err (hub->intfdev,
1330 "%s failed (err = %d)\n", __FUNCTION__, ret); 1430 "%s failed (err = %d)\n", __FUNCTION__, ret);
1331 else { 1431 if (ret >= 0)
1432 ret = -EIO;
1433 } else {
1332 *status = le16_to_cpu(hub->status->port.wPortStatus); 1434 *status = le16_to_cpu(hub->status->port.wPortStatus);
1333 *change = le16_to_cpu(hub->status->port.wPortChange); 1435 *change = le16_to_cpu(hub->status->port.wPortChange);
1334 ret = 0; 1436 ret = 0;
@@ -1676,6 +1778,12 @@ static int
1676hub_port_resume(struct usb_hub *hub, int port1, struct usb_device *udev) 1778hub_port_resume(struct usb_hub *hub, int port1, struct usb_device *udev)
1677{ 1779{
1678 int status; 1780 int status;
1781 u16 portchange, portstatus;
1782
1783 /* Skip the initial Clear-Suspend step for a remote wakeup */
1784 status = hub_port_status(hub, port1, &portstatus, &portchange);
1785 if (status == 0 && !(portstatus & USB_PORT_STAT_SUSPEND))
1786 goto SuspendCleared;
1679 1787
1680 // dev_dbg(hub->intfdev, "resume port %d\n", port1); 1788 // dev_dbg(hub->intfdev, "resume port %d\n", port1);
1681 1789
@@ -1689,9 +1797,6 @@ hub_port_resume(struct usb_hub *hub, int port1, struct usb_device *udev)
1689 "can't resume port %d, status %d\n", 1797 "can't resume port %d, status %d\n",
1690 port1, status); 1798 port1, status);
1691 } else { 1799 } else {
1692 u16 devstatus;
1693 u16 portchange;
1694
1695 /* drive resume for at least 20 msec */ 1800 /* drive resume for at least 20 msec */
1696 if (udev) 1801 if (udev)
1697 dev_dbg(&udev->dev, "usb %sresume\n", 1802 dev_dbg(&udev->dev, "usb %sresume\n",
@@ -1706,16 +1811,15 @@ hub_port_resume(struct usb_hub *hub, int port1, struct usb_device *udev)
1706 * stop resume signaling. Then finish the resume 1811 * stop resume signaling. Then finish the resume
1707 * sequence. 1812 * sequence.
1708 */ 1813 */
1709 devstatus = portchange = 0; 1814 status = hub_port_status(hub, port1, &portstatus, &portchange);
1710 status = hub_port_status(hub, port1, 1815SuspendCleared:
1711 &devstatus, &portchange);
1712 if (status < 0 1816 if (status < 0
1713 || (devstatus & LIVE_FLAGS) != LIVE_FLAGS 1817 || (portstatus & LIVE_FLAGS) != LIVE_FLAGS
1714 || (devstatus & USB_PORT_STAT_SUSPEND) != 0 1818 || (portstatus & USB_PORT_STAT_SUSPEND) != 0
1715 ) { 1819 ) {
1716 dev_dbg(hub->intfdev, 1820 dev_dbg(hub->intfdev,
1717 "port %d status %04x.%04x after resume, %d\n", 1821 "port %d status %04x.%04x after resume, %d\n",
1718 port1, portchange, devstatus, status); 1822 port1, portchange, portstatus, status);
1719 if (status >= 0) 1823 if (status >= 0)
1720 status = -ENODEV; 1824 status = -ENODEV;
1721 } else { 1825 } else {
@@ -1776,23 +1880,16 @@ static int remote_wakeup(struct usb_device *udev)
1776{ 1880{
1777 int status = 0; 1881 int status = 0;
1778 1882
1779 /* All this just to avoid sending a port-resume message
1780 * to the parent hub! */
1781
1782 usb_lock_device(udev); 1883 usb_lock_device(udev);
1783 usb_pm_lock(udev);
1784 if (udev->state == USB_STATE_SUSPENDED) { 1884 if (udev->state == USB_STATE_SUSPENDED) {
1785 dev_dbg(&udev->dev, "usb %sresume\n", "wakeup-"); 1885 dev_dbg(&udev->dev, "usb %sresume\n", "wakeup-");
1786 /* TRSMRCY = 10 msec */ 1886 status = usb_autoresume_device(udev);
1787 msleep(10); 1887
1788 status = finish_port_resume(udev); 1888 /* Give the interface drivers a chance to do something,
1889 * then autosuspend the device again. */
1789 if (status == 0) 1890 if (status == 0)
1790 udev->dev.power.power_state.event = PM_EVENT_ON; 1891 usb_autosuspend_device(udev);
1791 } 1892 }
1792 usb_pm_unlock(udev);
1793
1794 if (status == 0)
1795 usb_autoresume_device(udev, 0);
1796 usb_unlock_device(udev); 1893 usb_unlock_device(udev);
1797 return status; 1894 return status;
1798} 1895}
@@ -1856,6 +1953,8 @@ static int hub_suspend(struct usb_interface *intf, pm_message_t msg)
1856 } 1953 }
1857 } 1954 }
1858 1955
1956 dev_dbg(&intf->dev, "%s\n", __FUNCTION__);
1957
1859 /* "global suspend" of the downstream HC-to-USB interface */ 1958 /* "global suspend" of the downstream HC-to-USB interface */
1860 if (!hdev->parent) { 1959 if (!hdev->parent) {
1861 struct usb_bus *bus = hdev->bus; 1960 struct usb_bus *bus = hdev->bus;
@@ -1878,10 +1977,12 @@ static int hub_suspend(struct usb_interface *intf, pm_message_t msg)
1878 1977
1879static int hub_resume(struct usb_interface *intf) 1978static int hub_resume(struct usb_interface *intf)
1880{ 1979{
1881 struct usb_device *hdev = interface_to_usbdev(intf);
1882 struct usb_hub *hub = usb_get_intfdata (intf); 1980 struct usb_hub *hub = usb_get_intfdata (intf);
1981 struct usb_device *hdev = hub->hdev;
1883 int status; 1982 int status;
1884 1983
1984 dev_dbg(&intf->dev, "%s\n", __FUNCTION__);
1985
1885 /* "global resume" of the downstream HC-to-USB interface */ 1986 /* "global resume" of the downstream HC-to-USB interface */
1886 if (!hdev->parent) { 1987 if (!hdev->parent) {
1887 struct usb_bus *bus = hdev->bus; 1988 struct usb_bus *bus = hdev->bus;
@@ -1920,7 +2021,6 @@ void usb_resume_root_hub(struct usb_device *hdev)
1920{ 2021{
1921 struct usb_hub *hub = hdev_to_hub(hdev); 2022 struct usb_hub *hub = hdev_to_hub(hdev);
1922 2023
1923 hub->resume_root_hub = 1;
1924 kick_khubd(hub); 2024 kick_khubd(hub);
1925} 2025}
1926 2026
@@ -2557,16 +2657,13 @@ static void hub_events(void)
2557 intf = to_usb_interface(hub->intfdev); 2657 intf = to_usb_interface(hub->intfdev);
2558 hub_dev = &intf->dev; 2658 hub_dev = &intf->dev;
2559 2659
2560 i = hub->resume_root_hub; 2660 dev_dbg(hub_dev, "state %d ports %d chg %04x evt %04x\n",
2561
2562 dev_dbg(hub_dev, "state %d ports %d chg %04x evt %04x%s\n",
2563 hdev->state, hub->descriptor 2661 hdev->state, hub->descriptor
2564 ? hub->descriptor->bNbrPorts 2662 ? hub->descriptor->bNbrPorts
2565 : 0, 2663 : 0,
2566 /* NOTE: expects max 15 ports... */ 2664 /* NOTE: expects max 15 ports... */
2567 (u16) hub->change_bits[0], 2665 (u16) hub->change_bits[0],
2568 (u16) hub->event_bits[0], 2666 (u16) hub->event_bits[0]);
2569 i ? ", resume root" : "");
2570 2667
2571 usb_get_intf(intf); 2668 usb_get_intf(intf);
2572 spin_unlock_irq(&hub_event_lock); 2669 spin_unlock_irq(&hub_event_lock);
@@ -2587,16 +2684,16 @@ static void hub_events(void)
2587 goto loop; 2684 goto loop;
2588 } 2685 }
2589 2686
2590 /* Is this is a root hub wanting to reactivate the downstream 2687 /* Autoresume */
2591 * ports? If so, be sure the interface resumes even if its 2688 ret = usb_autopm_get_interface(intf);
2592 * stub "device" node was never suspended. 2689 if (ret) {
2593 */ 2690 dev_dbg(hub_dev, "Can't autoresume: %d\n", ret);
2594 if (i) 2691 goto loop;
2595 usb_autoresume_device(hdev, 0); 2692 }
2596 2693
2597 /* If this is an inactive or suspended hub, do nothing */ 2694 /* If this is an inactive hub, do nothing */
2598 if (hub->quiescing) 2695 if (hub->quiescing)
2599 goto loop; 2696 goto loop_autopm;
2600 2697
2601 if (hub->error) { 2698 if (hub->error) {
2602 dev_dbg (hub_dev, "resetting for error %d\n", 2699 dev_dbg (hub_dev, "resetting for error %d\n",
@@ -2606,7 +2703,7 @@ static void hub_events(void)
2606 if (ret) { 2703 if (ret) {
2607 dev_dbg (hub_dev, 2704 dev_dbg (hub_dev,
2608 "error resetting hub: %d\n", ret); 2705 "error resetting hub: %d\n", ret);
2609 goto loop; 2706 goto loop_autopm;
2610 } 2707 }
2611 2708
2612 hub->nerrors = 0; 2709 hub->nerrors = 0;
@@ -2734,6 +2831,10 @@ static void hub_events(void)
2734 if (!hdev->parent && !hub->busy_bits[0]) 2831 if (!hdev->parent && !hub->busy_bits[0])
2735 usb_enable_root_hub_irq(hdev->bus); 2832 usb_enable_root_hub_irq(hdev->bus);
2736 2833
2834loop_autopm:
2835 /* Allow autosuspend if we're not going to run again */
2836 if (list_empty(&hub->event_list))
2837 usb_autopm_enable(intf);
2737loop: 2838loop:
2738 usb_unlock_device(hdev); 2839 usb_unlock_device(hdev);
2739 usb_put_intf(intf); 2840 usb_put_intf(intf);
@@ -2775,6 +2876,7 @@ static struct usb_driver hub_driver = {
2775 .post_reset = hub_post_reset, 2876 .post_reset = hub_post_reset,
2776 .ioctl = hub_ioctl, 2877 .ioctl = hub_ioctl,
2777 .id_table = hub_id_table, 2878 .id_table = hub_id_table,
2879 .supports_autosuspend = 1,
2778}; 2880};
2779 2881
2780int usb_hub_init(void) 2882int usb_hub_init(void)
@@ -2999,7 +3101,7 @@ int usb_reset_composite_device(struct usb_device *udev,
2999 } 3101 }
3000 3102
3001 /* Prevent autosuspend during the reset */ 3103 /* Prevent autosuspend during the reset */
3002 usb_autoresume_device(udev, 1); 3104 usb_autoresume_device(udev);
3003 3105
3004 if (iface && iface->condition != USB_INTERFACE_BINDING) 3106 if (iface && iface->condition != USB_INTERFACE_BINDING)
3005 iface = NULL; 3107 iface = NULL;
@@ -3042,7 +3144,7 @@ int usb_reset_composite_device(struct usb_device *udev,
3042 } 3144 }
3043 } 3145 }
3044 3146
3045 usb_autosuspend_device(udev, 1); 3147 usb_autosuspend_device(udev);
3046 return ret; 3148 return ret;
3047} 3149}
3048EXPORT_SYMBOL(usb_reset_composite_device); 3150EXPORT_SYMBOL(usb_reset_composite_device);
diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
index 035d3ef35888..cf9559c6c9b6 100644
--- a/drivers/usb/core/hub.h
+++ b/drivers/usb/core/hub.h
@@ -192,45 +192,4 @@ struct usb_tt_clear {
192 192
193extern void usb_hub_tt_clear_buffer (struct usb_device *dev, int pipe); 193extern void usb_hub_tt_clear_buffer (struct usb_device *dev, int pipe);
194 194
195struct usb_hub {
196 struct device *intfdev; /* the "interface" device */
197 struct usb_device *hdev;
198 struct urb *urb; /* for interrupt polling pipe */
199
200 /* buffer for urb ... with extra space in case of babble */
201 char (*buffer)[8];
202 dma_addr_t buffer_dma; /* DMA address for buffer */
203 union {
204 struct usb_hub_status hub;
205 struct usb_port_status port;
206 } *status; /* buffer for status reports */
207
208 int error; /* last reported error */
209 int nerrors; /* track consecutive errors */
210
211 struct list_head event_list; /* hubs w/data or errs ready */
212 unsigned long event_bits[1]; /* status change bitmask */
213 unsigned long change_bits[1]; /* ports with logical connect
214 status change */
215 unsigned long busy_bits[1]; /* ports being reset or
216 resumed */
217#if USB_MAXCHILDREN > 31 /* 8*sizeof(unsigned long) - 1 */
218#error event_bits[] is too short!
219#endif
220
221 struct usb_hub_descriptor *descriptor; /* class descriptor */
222 struct usb_tt tt; /* Transaction Translator */
223
224 unsigned mA_per_port; /* current for each child */
225
226 unsigned limited_power:1;
227 unsigned quiescing:1;
228 unsigned activating:1;
229 unsigned resume_root_hub:1;
230
231 unsigned has_indicators:1;
232 enum hub_led_mode indicator[USB_MAXCHILDREN];
233 struct delayed_work leds;
234};
235
236#endif /* __LINUX_HUB_H */ 195#endif /* __LINUX_HUB_H */
diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index 89572bc021b1..7390b67c609d 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -764,7 +764,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
764 err = -EINVAL; 764 err = -EINVAL;
765 goto errout; 765 goto errout;
766 } else { 766 } else {
767 dev->have_langid = -1; 767 dev->have_langid = 1;
768 dev->string_langid = tbuf[2] | (tbuf[3]<< 8); 768 dev->string_langid = tbuf[2] | (tbuf[3]<< 8);
769 /* always use the first langid listed */ 769 /* always use the first langid listed */
770 dev_dbg (&dev->dev, "default language 0x%04x\n", 770 dev_dbg (&dev->dev, "default language 0x%04x\n",
@@ -1398,7 +1398,7 @@ free_interfaces:
1398 } 1398 }
1399 1399
1400 /* Wake up the device so we can send it the Set-Config request */ 1400 /* Wake up the device so we can send it the Set-Config request */
1401 ret = usb_autoresume_device(dev, 1); 1401 ret = usb_autoresume_device(dev);
1402 if (ret) 1402 if (ret)
1403 goto free_interfaces; 1403 goto free_interfaces;
1404 1404
@@ -1421,7 +1421,7 @@ free_interfaces:
1421 dev->actconfig = cp; 1421 dev->actconfig = cp;
1422 if (!cp) { 1422 if (!cp) {
1423 usb_set_device_state(dev, USB_STATE_ADDRESS); 1423 usb_set_device_state(dev, USB_STATE_ADDRESS);
1424 usb_autosuspend_device(dev, 1); 1424 usb_autosuspend_device(dev);
1425 goto free_interfaces; 1425 goto free_interfaces;
1426 } 1426 }
1427 usb_set_device_state(dev, USB_STATE_CONFIGURED); 1427 usb_set_device_state(dev, USB_STATE_CONFIGURED);
@@ -1490,7 +1490,7 @@ free_interfaces:
1490 usb_create_sysfs_intf_files (intf); 1490 usb_create_sysfs_intf_files (intf);
1491 } 1491 }
1492 1492
1493 usb_autosuspend_device(dev, 1); 1493 usb_autosuspend_device(dev);
1494 return 0; 1494 return 0;
1495} 1495}
1496 1496
diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index ab2f68fc7d2d..02426d0b9a34 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -200,13 +200,6 @@ static void ksuspend_usb_cleanup(void)
200 destroy_workqueue(ksuspend_usb_wq); 200 destroy_workqueue(ksuspend_usb_wq);
201} 201}
202 202
203#else
204
205#define ksuspend_usb_init() 0
206#define ksuspend_usb_cleanup() do {} while (0)
207
208#endif
209
210#ifdef CONFIG_USB_SUSPEND 203#ifdef CONFIG_USB_SUSPEND
211 204
212/* usb_autosuspend_work - callback routine to autosuspend a USB device */ 205/* usb_autosuspend_work - callback routine to autosuspend a USB device */
@@ -226,7 +219,14 @@ static void usb_autosuspend_work(struct work_struct *work)
226static void usb_autosuspend_work(struct work_struct *work) 219static void usb_autosuspend_work(struct work_struct *work)
227{} 220{}
228 221
229#endif 222#endif /* CONFIG_USB_SUSPEND */
223
224#else
225
226#define ksuspend_usb_init() 0
227#define ksuspend_usb_cleanup() do {} while (0)
228
229#endif /* CONFIG_PM */
230 230
231/** 231/**
232 * usb_alloc_dev - usb device constructor (usbcore-internal) 232 * usb_alloc_dev - usb device constructor (usbcore-internal)
@@ -538,138 +538,6 @@ int usb_get_current_frame_number(struct usb_device *dev)
538 return usb_hcd_get_frame_number (dev); 538 return usb_hcd_get_frame_number (dev);
539} 539}
540 540
541/**
542 * usb_endpoint_dir_in - check if the endpoint has IN direction
543 * @epd: endpoint to be checked
544 *
545 * Returns true if the endpoint is of type IN, otherwise it returns false.
546 */
547int usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd)
548{
549 return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN);
550}
551
552/**
553 * usb_endpoint_dir_out - check if the endpoint has OUT direction
554 * @epd: endpoint to be checked
555 *
556 * Returns true if the endpoint is of type OUT, otherwise it returns false.
557 */
558int usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd)
559{
560 return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT);
561}
562
563/**
564 * usb_endpoint_xfer_bulk - check if the endpoint has bulk transfer type
565 * @epd: endpoint to be checked
566 *
567 * Returns true if the endpoint is of type bulk, otherwise it returns false.
568 */
569int usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd)
570{
571 return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
572 USB_ENDPOINT_XFER_BULK);
573}
574
575/**
576 * usb_endpoint_xfer_int - check if the endpoint has interrupt transfer type
577 * @epd: endpoint to be checked
578 *
579 * Returns true if the endpoint is of type interrupt, otherwise it returns
580 * false.
581 */
582int usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd)
583{
584 return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
585 USB_ENDPOINT_XFER_INT);
586}
587
588/**
589 * usb_endpoint_xfer_isoc - check if the endpoint has isochronous transfer type
590 * @epd: endpoint to be checked
591 *
592 * Returns true if the endpoint is of type isochronous, otherwise it returns
593 * false.
594 */
595int usb_endpoint_xfer_isoc(const struct usb_endpoint_descriptor *epd)
596{
597 return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
598 USB_ENDPOINT_XFER_ISOC);
599}
600
601/**
602 * usb_endpoint_is_bulk_in - check if the endpoint is bulk IN
603 * @epd: endpoint to be checked
604 *
605 * Returns true if the endpoint has bulk transfer type and IN direction,
606 * otherwise it returns false.
607 */
608int usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd)
609{
610 return (usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_in(epd));
611}
612
613/**
614 * usb_endpoint_is_bulk_out - check if the endpoint is bulk OUT
615 * @epd: endpoint to be checked
616 *
617 * Returns true if the endpoint has bulk transfer type and OUT direction,
618 * otherwise it returns false.
619 */
620int usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd)
621{
622 return (usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_out(epd));
623}
624
625/**
626 * usb_endpoint_is_int_in - check if the endpoint is interrupt IN
627 * @epd: endpoint to be checked
628 *
629 * Returns true if the endpoint has interrupt transfer type and IN direction,
630 * otherwise it returns false.
631 */
632int usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd)
633{
634 return (usb_endpoint_xfer_int(epd) && usb_endpoint_dir_in(epd));
635}
636
637/**
638 * usb_endpoint_is_int_out - check if the endpoint is interrupt OUT
639 * @epd: endpoint to be checked
640 *
641 * Returns true if the endpoint has interrupt transfer type and OUT direction,
642 * otherwise it returns false.
643 */
644int usb_endpoint_is_int_out(const struct usb_endpoint_descriptor *epd)
645{
646 return (usb_endpoint_xfer_int(epd) && usb_endpoint_dir_out(epd));
647}
648
649/**
650 * usb_endpoint_is_isoc_in - check if the endpoint is isochronous IN
651 * @epd: endpoint to be checked
652 *
653 * Returns true if the endpoint has isochronous transfer type and IN direction,
654 * otherwise it returns false.
655 */
656int usb_endpoint_is_isoc_in(const struct usb_endpoint_descriptor *epd)
657{
658 return (usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_in(epd));
659}
660
661/**
662 * usb_endpoint_is_isoc_out - check if the endpoint is isochronous OUT
663 * @epd: endpoint to be checked
664 *
665 * Returns true if the endpoint has isochronous transfer type and OUT direction,
666 * otherwise it returns false.
667 */
668int usb_endpoint_is_isoc_out(const struct usb_endpoint_descriptor *epd)
669{
670 return (usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_out(epd));
671}
672
673/*-------------------------------------------------------------------*/ 541/*-------------------------------------------------------------------*/
674/* 542/*
675 * __usb_get_extra_descriptor() finds a descriptor of specific type in the 543 * __usb_get_extra_descriptor() finds a descriptor of specific type in the
@@ -1103,18 +971,6 @@ EXPORT_SYMBOL(__usb_get_extra_descriptor);
1103EXPORT_SYMBOL(usb_find_device); 971EXPORT_SYMBOL(usb_find_device);
1104EXPORT_SYMBOL(usb_get_current_frame_number); 972EXPORT_SYMBOL(usb_get_current_frame_number);
1105 973
1106EXPORT_SYMBOL_GPL(usb_endpoint_dir_in);
1107EXPORT_SYMBOL_GPL(usb_endpoint_dir_out);
1108EXPORT_SYMBOL_GPL(usb_endpoint_xfer_bulk);
1109EXPORT_SYMBOL_GPL(usb_endpoint_xfer_int);
1110EXPORT_SYMBOL_GPL(usb_endpoint_xfer_isoc);
1111EXPORT_SYMBOL_GPL(usb_endpoint_is_bulk_in);
1112EXPORT_SYMBOL_GPL(usb_endpoint_is_bulk_out);
1113EXPORT_SYMBOL_GPL(usb_endpoint_is_int_in);
1114EXPORT_SYMBOL_GPL(usb_endpoint_is_int_out);
1115EXPORT_SYMBOL_GPL(usb_endpoint_is_isoc_in);
1116EXPORT_SYMBOL_GPL(usb_endpoint_is_isoc_out);
1117
1118EXPORT_SYMBOL (usb_buffer_alloc); 974EXPORT_SYMBOL (usb_buffer_alloc);
1119EXPORT_SYMBOL (usb_buffer_free); 975EXPORT_SYMBOL (usb_buffer_free);
1120 976
diff --git a/drivers/usb/core/usb.h b/drivers/usb/core/usb.h
index 13322e33f912..17830a81be14 100644
--- a/drivers/usb/core/usb.h
+++ b/drivers/usb/core/usb.h
@@ -64,14 +64,13 @@ static inline void usb_pm_unlock(struct usb_device *udev) {}
64 64
65#define USB_AUTOSUSPEND_DELAY (HZ*2) 65#define USB_AUTOSUSPEND_DELAY (HZ*2)
66 66
67extern void usb_autosuspend_device(struct usb_device *udev, int dec_busy_cnt); 67extern void usb_autosuspend_device(struct usb_device *udev);
68extern int usb_autoresume_device(struct usb_device *udev, int inc_busy_cnt); 68extern int usb_autoresume_device(struct usb_device *udev);
69 69
70#else 70#else
71 71
72#define usb_autosuspend_device(udev, dec_busy_cnt) do {} while (0) 72#define usb_autosuspend_device(udev) do {} while (0)
73static inline int usb_autoresume_device(struct usb_device *udev, 73static inline int usb_autoresume_device(struct usb_device *udev)
74 int inc_busy_cnt)
75{ 74{
76 return 0; 75 return 0;
77} 76}
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 107119c54301..d15bf22b9a03 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -1894,13 +1894,13 @@ static int eth_start_xmit (struct sk_buff *skb, struct net_device *net)
1894 if (!eth_is_promisc (dev)) { 1894 if (!eth_is_promisc (dev)) {
1895 u8 *dest = skb->data; 1895 u8 *dest = skb->data;
1896 1896
1897 if (dest [0] & 0x01) { 1897 if (is_multicast_ether_addr(dest)) {
1898 u16 type; 1898 u16 type;
1899 1899
1900 /* ignores USB_CDC_PACKET_TYPE_MULTICAST and host 1900 /* ignores USB_CDC_PACKET_TYPE_MULTICAST and host
1901 * SET_ETHERNET_MULTICAST_FILTERS requests 1901 * SET_ETHERNET_MULTICAST_FILTERS requests
1902 */ 1902 */
1903 if (memcmp (dest, net->broadcast, ETH_ALEN) == 0) 1903 if (is_broadcast_ether_addr(dest))
1904 type = USB_CDC_PACKET_TYPE_BROADCAST; 1904 type = USB_CDC_PACKET_TYPE_BROADCAST;
1905 else 1905 else
1906 type = USB_CDC_PACKET_TYPE_ALL_MULTICAST; 1906 type = USB_CDC_PACKET_TYPE_ALL_MULTICAST;
diff --git a/drivers/usb/gadget/lh7a40x_udc.c b/drivers/usb/gadget/lh7a40x_udc.c
index 179259664c18..4a991564a03e 100644
--- a/drivers/usb/gadget/lh7a40x_udc.c
+++ b/drivers/usb/gadget/lh7a40x_udc.c
@@ -83,7 +83,6 @@ static int lh7a40x_queue(struct usb_ep *ep, struct usb_request *, gfp_t);
83static int lh7a40x_dequeue(struct usb_ep *ep, struct usb_request *); 83static int lh7a40x_dequeue(struct usb_ep *ep, struct usb_request *);
84static int lh7a40x_set_halt(struct usb_ep *ep, int); 84static int lh7a40x_set_halt(struct usb_ep *ep, int);
85static int lh7a40x_fifo_status(struct usb_ep *ep); 85static int lh7a40x_fifo_status(struct usb_ep *ep);
86static int lh7a40x_fifo_status(struct usb_ep *ep);
87static void lh7a40x_fifo_flush(struct usb_ep *ep); 86static void lh7a40x_fifo_flush(struct usb_ep *ep);
88static void lh7a40x_ep0_kick(struct lh7a40x_udc *dev, struct lh7a40x_ep *ep); 87static void lh7a40x_ep0_kick(struct lh7a40x_udc *dev, struct lh7a40x_ep *ep);
89static void lh7a40x_handle_ep0(struct lh7a40x_udc *dev, u32 intr); 88static void lh7a40x_handle_ep0(struct lh7a40x_udc *dev, u32 intr);
diff --git a/drivers/usb/gadget/net2280.c b/drivers/usb/gadget/net2280.c
index 3acc896a5d4c..0b590831582c 100644
--- a/drivers/usb/gadget/net2280.c
+++ b/drivers/usb/gadget/net2280.c
@@ -1040,6 +1040,7 @@ net2280_queue (struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1040 1040
1041 } /* else the irq handler advances the queue. */ 1041 } /* else the irq handler advances the queue. */
1042 1042
1043 ep->responded = 1;
1043 if (req) 1044 if (req)
1044 list_add_tail (&req->queue, &ep->queue); 1045 list_add_tail (&req->queue, &ep->queue);
1045done: 1046done:
@@ -2188,7 +2189,8 @@ static void handle_ep_small (struct net2280_ep *ep)
2188 ep->stopped = 1; 2189 ep->stopped = 1;
2189 set_halt (ep); 2190 set_halt (ep);
2190 mode = 2; 2191 mode = 2;
2191 } else if (!req && !ep->stopped) 2192 } else if (ep->responded &&
2193 !req && !ep->stopped)
2192 write_fifo (ep, NULL); 2194 write_fifo (ep, NULL);
2193 } 2195 }
2194 } else { 2196 } else {
@@ -2203,7 +2205,7 @@ static void handle_ep_small (struct net2280_ep *ep)
2203 } else if (((t & (1 << DATA_OUT_PING_TOKEN_INTERRUPT)) 2205 } else if (((t & (1 << DATA_OUT_PING_TOKEN_INTERRUPT))
2204 && req 2206 && req
2205 && req->req.actual == req->req.length) 2207 && req->req.actual == req->req.length)
2206 || !req) { 2208 || (ep->responded && !req)) {
2207 ep->dev->protocol_stall = 1; 2209 ep->dev->protocol_stall = 1;
2208 set_halt (ep); 2210 set_halt (ep);
2209 ep->stopped = 1; 2211 ep->stopped = 1;
@@ -2469,6 +2471,7 @@ static void handle_stat0_irqs (struct net2280 *dev, u32 stat)
2469 /* we made the hardware handle most lowlevel requests; 2471 /* we made the hardware handle most lowlevel requests;
2470 * everything else goes uplevel to the gadget code. 2472 * everything else goes uplevel to the gadget code.
2471 */ 2473 */
2474 ep->responded = 1;
2472 switch (u.r.bRequest) { 2475 switch (u.r.bRequest) {
2473 case USB_REQ_GET_STATUS: { 2476 case USB_REQ_GET_STATUS: {
2474 struct net2280_ep *e; 2477 struct net2280_ep *e;
@@ -2537,6 +2540,7 @@ delegate:
2537 u.r.bRequestType, u.r.bRequest, 2540 u.r.bRequestType, u.r.bRequest,
2538 w_value, w_index, w_length, 2541 w_value, w_index, w_length,
2539 readl (&ep->regs->ep_cfg)); 2542 readl (&ep->regs->ep_cfg));
2543 ep->responded = 0;
2540 spin_unlock (&dev->lock); 2544 spin_unlock (&dev->lock);
2541 tmp = dev->driver->setup (&dev->gadget, &u.r); 2545 tmp = dev->driver->setup (&dev->gadget, &u.r);
2542 spin_lock (&dev->lock); 2546 spin_lock (&dev->lock);
diff --git a/drivers/usb/gadget/net2280.h b/drivers/usb/gadget/net2280.h
index 957d6df34015..44ca139983d8 100644
--- a/drivers/usb/gadget/net2280.h
+++ b/drivers/usb/gadget/net2280.h
@@ -110,7 +110,8 @@ struct net2280_ep {
110 out_overflow : 1, 110 out_overflow : 1,
111 stopped : 1, 111 stopped : 1,
112 is_in : 1, 112 is_in : 1,
113 is_iso : 1; 113 is_iso : 1,
114 responded : 1;
114}; 115};
115 116
116static inline void allow_status (struct net2280_ep *ep) 117static inline void allow_status (struct net2280_ep *ep)
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 671c24bc6d75..1ed506e95985 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -2472,6 +2472,7 @@ static struct pxa2xx_udc memory = {
2472#define PXA210_B1 0x00000123 2472#define PXA210_B1 0x00000123
2473#define PXA210_B0 0x00000122 2473#define PXA210_B0 0x00000122
2474#define IXP425_A0 0x000001c1 2474#define IXP425_A0 0x000001c1
2475#define IXP425_B0 0x000001f1
2475#define IXP465_AD 0x00000200 2476#define IXP465_AD 0x00000200
2476 2477
2477/* 2478/*
@@ -2509,6 +2510,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2509 break; 2510 break;
2510#elif defined(CONFIG_ARCH_IXP4XX) 2511#elif defined(CONFIG_ARCH_IXP4XX)
2511 case IXP425_A0: 2512 case IXP425_A0:
2513 case IXP425_B0:
2512 case IXP465_AD: 2514 case IXP465_AD:
2513 dev->has_cfr = 1; 2515 dev->has_cfr = 1;
2514 out_dma = 0; 2516 out_dma = 0;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index cf10cbc98f80..cc60759083bf 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -153,7 +153,7 @@ config USB_U132_HCD
153 adapter will *NOT* work with PC cards that do not contain an OHCI 153 adapter will *NOT* work with PC cards that do not contain an OHCI
154 controller. 154 controller.
155 155
156 For those PC cards that contain multiple OHCI controllers only ther 156 For those PC cards that contain multiple OHCI controllers only the
157 first one is used. 157 first one is used.
158 158
159 The driver consists of two modules, the "ftdi-elan" module is a 159 The driver consists of two modules, the "ftdi-elan" module is a
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 9030994aba98..025d33313681 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -126,6 +126,11 @@ static unsigned park = 0;
126module_param (park, uint, S_IRUGO); 126module_param (park, uint, S_IRUGO);
127MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 127MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
128 128
129/* for flakey hardware, ignore overcurrent indicators */
130static int ignore_oc = 0;
131module_param (ignore_oc, bool, S_IRUGO);
132MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
133
129#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 134#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
130 135
131/*-------------------------------------------------------------------------*/ 136/*-------------------------------------------------------------------------*/
@@ -541,9 +546,10 @@ static int ehci_run (struct usb_hcd *hcd)
541 546
542 temp = HC_VERSION(readl (&ehci->caps->hc_capbase)); 547 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
543 ehci_info (ehci, 548 ehci_info (ehci,
544 "USB %x.%x started, EHCI %x.%02x, driver %s\n", 549 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
545 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 550 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
546 temp >> 8, temp & 0xff, DRIVER_VERSION); 551 temp >> 8, temp & 0xff, DRIVER_VERSION,
552 ignore_oc ? ", overcurrent ignored" : "");
547 553
548 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */ 554 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
549 555
@@ -613,9 +619,8 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd)
613 unsigned i = HCS_N_PORTS (ehci->hcs_params); 619 unsigned i = HCS_N_PORTS (ehci->hcs_params);
614 620
615 /* resume root hub? */ 621 /* resume root hub? */
616 status = readl (&ehci->regs->command); 622 if (!(readl(&ehci->regs->command) & CMD_RUN))
617 if (!(status & CMD_RUN)) 623 usb_hcd_resume_root_hub(hcd);
618 writel (status | CMD_RUN, &ehci->regs->command);
619 624
620 while (i--) { 625 while (i--) {
621 int pstatus = readl (&ehci->regs->port_status [i]); 626 int pstatus = readl (&ehci->regs->port_status [i]);
@@ -632,7 +637,6 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd)
632 */ 637 */
633 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); 638 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
634 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 639 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
635 usb_hcd_resume_root_hub(hcd);
636 } 640 }
637 } 641 }
638 642
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 1b20722c102b..bfe5f307cba6 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -34,6 +34,7 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
34{ 34{
35 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 35 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
36 int port; 36 int port;
37 int mask;
37 38
38 if (time_before (jiffies, ehci->next_statechange)) 39 if (time_before (jiffies, ehci->next_statechange))
39 msleep(5); 40 msleep(5);
@@ -51,14 +52,25 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
51 ehci->reclaim_ready = 1; 52 ehci->reclaim_ready = 1;
52 ehci_work(ehci); 53 ehci_work(ehci);
53 54
54 /* suspend any active/unsuspended ports, maybe allow wakeup */ 55 /* Unlike other USB host controller types, EHCI doesn't have
56 * any notion of "global" or bus-wide suspend. The driver has
57 * to manually suspend all the active unsuspended ports, and
58 * then manually resume them in the bus_resume() routine.
59 */
60 ehci->bus_suspended = 0;
55 while (port--) { 61 while (port--) {
56 u32 __iomem *reg = &ehci->regs->port_status [port]; 62 u32 __iomem *reg = &ehci->regs->port_status [port];
57 u32 t1 = readl (reg) & ~PORT_RWC_BITS; 63 u32 t1 = readl (reg) & ~PORT_RWC_BITS;
58 u32 t2 = t1; 64 u32 t2 = t1;
59 65
60 if ((t1 & PORT_PE) && !(t1 & PORT_OWNER)) 66 /* keep track of which ports we suspend */
67 if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
68 !(t1 & PORT_SUSPEND)) {
61 t2 |= PORT_SUSPEND; 69 t2 |= PORT_SUSPEND;
70 set_bit(port, &ehci->bus_suspended);
71 }
72
73 /* enable remote wakeup on all ports */
62 if (device_may_wakeup(&hcd->self.root_hub->dev)) 74 if (device_may_wakeup(&hcd->self.root_hub->dev))
63 t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E; 75 t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
64 else 76 else
@@ -76,6 +88,13 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
76 ehci_halt (ehci); 88 ehci_halt (ehci);
77 hcd->state = HC_STATE_SUSPENDED; 89 hcd->state = HC_STATE_SUSPENDED;
78 90
91 /* allow remote wakeup */
92 mask = INTR_MASK;
93 if (!device_may_wakeup(&hcd->self.root_hub->dev))
94 mask &= ~STS_PCD;
95 writel(mask, &ehci->regs->intr_enable);
96 readl(&ehci->regs->intr_enable);
97
79 ehci->next_statechange = jiffies + msecs_to_jiffies(10); 98 ehci->next_statechange = jiffies + msecs_to_jiffies(10);
80 spin_unlock_irq (&ehci->lock); 99 spin_unlock_irq (&ehci->lock);
81 return 0; 100 return 0;
@@ -88,7 +107,6 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
88 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 107 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
89 u32 temp; 108 u32 temp;
90 int i; 109 int i;
91 int intr_enable;
92 110
93 if (time_before (jiffies, ehci->next_statechange)) 111 if (time_before (jiffies, ehci->next_statechange))
94 msleep(5); 112 msleep(5);
@@ -100,31 +118,30 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
100 * the last user of the controller, not reset/pm hardware keeping 118 * the last user of the controller, not reset/pm hardware keeping
101 * state we gave to it. 119 * state we gave to it.
102 */ 120 */
121 temp = readl(&ehci->regs->intr_enable);
122 ehci_dbg(ehci, "resume root hub%s\n", temp ? "" : " after power loss");
103 123
104 /* re-init operational registers in case we lost power */ 124 /* at least some APM implementations will try to deliver
105 if (readl (&ehci->regs->intr_enable) == 0) { 125 * IRQs right away, so delay them until we're ready.
106 /* at least some APM implementations will try to deliver 126 */
107 * IRQs right away, so delay them until we're ready. 127 writel(0, &ehci->regs->intr_enable);
108 */ 128
109 intr_enable = 1; 129 /* re-init operational registers */
110 writel (0, &ehci->regs->segment); 130 writel(0, &ehci->regs->segment);
111 writel (ehci->periodic_dma, &ehci->regs->frame_list); 131 writel(ehci->periodic_dma, &ehci->regs->frame_list);
112 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next); 132 writel((u32) ehci->async->qh_dma, &ehci->regs->async_next);
113 } else
114 intr_enable = 0;
115 ehci_dbg(ehci, "resume root hub%s\n",
116 intr_enable ? " after power loss" : "");
117 133
118 /* restore CMD_RUN, framelist size, and irq threshold */ 134 /* restore CMD_RUN, framelist size, and irq threshold */
119 writel (ehci->command, &ehci->regs->command); 135 writel (ehci->command, &ehci->regs->command);
120 136
121 /* take ports out of suspend */ 137 /* manually resume the ports we suspended during bus_suspend() */
122 i = HCS_N_PORTS (ehci->hcs_params); 138 i = HCS_N_PORTS (ehci->hcs_params);
123 while (i--) { 139 while (i--) {
124 temp = readl (&ehci->regs->port_status [i]); 140 temp = readl (&ehci->regs->port_status [i]);
125 temp &= ~(PORT_RWC_BITS 141 temp &= ~(PORT_RWC_BITS
126 | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E); 142 | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
127 if (temp & PORT_SUSPEND) { 143 if (test_bit(i, &ehci->bus_suspended) &&
144 (temp & PORT_SUSPEND)) {
128 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); 145 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
129 temp |= PORT_RESUME; 146 temp |= PORT_RESUME;
130 } 147 }
@@ -134,11 +151,12 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
134 mdelay (20); 151 mdelay (20);
135 while (i--) { 152 while (i--) {
136 temp = readl (&ehci->regs->port_status [i]); 153 temp = readl (&ehci->regs->port_status [i]);
137 if ((temp & PORT_SUSPEND) == 0) 154 if (test_bit(i, &ehci->bus_suspended) &&
138 continue; 155 (temp & PORT_SUSPEND)) {
139 temp &= ~(PORT_RWC_BITS | PORT_RESUME); 156 temp &= ~(PORT_RWC_BITS | PORT_RESUME);
140 writel (temp, &ehci->regs->port_status [i]); 157 writel (temp, &ehci->regs->port_status [i]);
141 ehci_vdbg (ehci, "resumed port %d\n", i + 1); 158 ehci_vdbg (ehci, "resumed port %d\n", i + 1);
159 }
142 } 160 }
143 (void) readl (&ehci->regs->command); 161 (void) readl (&ehci->regs->command);
144 162
@@ -157,8 +175,7 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
157 hcd->state = HC_STATE_RUNNING; 175 hcd->state = HC_STATE_RUNNING;
158 176
159 /* Now we can safely re-enable irqs */ 177 /* Now we can safely re-enable irqs */
160 if (intr_enable) 178 writel(INTR_MASK, &ehci->regs->intr_enable);
161 writel (INTR_MASK, &ehci->regs->intr_enable);
162 179
163 spin_unlock_irq (&ehci->lock); 180 spin_unlock_irq (&ehci->lock);
164 return 0; 181 return 0;
@@ -218,6 +235,7 @@ ehci_hub_status_data (struct usb_hcd *hcd, char *buf)
218{ 235{
219 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 236 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
220 u32 temp, status = 0; 237 u32 temp, status = 0;
238 u32 mask;
221 int ports, i, retval = 1; 239 int ports, i, retval = 1;
222 unsigned long flags; 240 unsigned long flags;
223 241
@@ -233,6 +251,18 @@ ehci_hub_status_data (struct usb_hcd *hcd, char *buf)
233 retval++; 251 retval++;
234 } 252 }
235 253
254 /* Some boards (mostly VIA?) report bogus overcurrent indications,
255 * causing massive log spam unless we completely ignore them. It
256 * may be relevant that VIA VT8235 controlers, where PORT_POWER is
257 * always set, seem to clear PORT_OCC and PORT_CSC when writing to
258 * PORT_POWER; that's surprising, but maybe within-spec.
259 */
260 if (!ignore_oc)
261 mask = PORT_CSC | PORT_PEC | PORT_OCC;
262 else
263 mask = PORT_CSC | PORT_PEC;
264 // PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND
265
236 /* no hub change reports (bit 0) for now (power, ...) */ 266 /* no hub change reports (bit 0) for now (power, ...) */
237 267
238 /* port N changes (bit N)? */ 268 /* port N changes (bit N)? */
@@ -250,8 +280,7 @@ ehci_hub_status_data (struct usb_hcd *hcd, char *buf)
250 } 280 }
251 if (!(temp & PORT_CONNECT)) 281 if (!(temp & PORT_CONNECT))
252 ehci->reset_done [i] = 0; 282 ehci->reset_done [i] = 0;
253 if ((temp & (PORT_CSC | PORT_PEC | PORT_OCC)) != 0 283 if ((temp & mask) != 0
254 // PORT_STAT_C_SUSPEND?
255 || ((temp & PORT_RESUME) != 0 284 || ((temp & PORT_RESUME) != 0
256 && time_after (jiffies, 285 && time_after (jiffies,
257 ehci->reset_done [i]))) { 286 ehci->reset_done [i]))) {
@@ -319,6 +348,7 @@ static int ehci_hub_control (
319 u32 temp, status; 348 u32 temp, status;
320 unsigned long flags; 349 unsigned long flags;
321 int retval = 0; 350 int retval = 0;
351 unsigned selector;
322 352
323 /* 353 /*
324 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 354 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
@@ -417,7 +447,7 @@ static int ehci_hub_control (
417 status |= 1 << USB_PORT_FEAT_C_CONNECTION; 447 status |= 1 << USB_PORT_FEAT_C_CONNECTION;
418 if (temp & PORT_PEC) 448 if (temp & PORT_PEC)
419 status |= 1 << USB_PORT_FEAT_C_ENABLE; 449 status |= 1 << USB_PORT_FEAT_C_ENABLE;
420 if (temp & PORT_OCC) 450 if ((temp & PORT_OCC) && !ignore_oc)
421 status |= 1 << USB_PORT_FEAT_C_OVER_CURRENT; 451 status |= 1 << USB_PORT_FEAT_C_OVER_CURRENT;
422 452
423 /* whoever resumes must GetPortStatus to complete it!! */ 453 /* whoever resumes must GetPortStatus to complete it!! */
@@ -506,6 +536,8 @@ static int ehci_hub_control (
506 } 536 }
507 break; 537 break;
508 case SetPortFeature: 538 case SetPortFeature:
539 selector = wIndex >> 8;
540 wIndex &= 0xff;
509 if (!wIndex || wIndex > ports) 541 if (!wIndex || wIndex > ports)
510 goto error; 542 goto error;
511 wIndex--; 543 wIndex--;
@@ -559,6 +591,22 @@ static int ehci_hub_control (
559 } 591 }
560 writel (temp, &ehci->regs->port_status [wIndex]); 592 writel (temp, &ehci->regs->port_status [wIndex]);
561 break; 593 break;
594
595 /* For downstream facing ports (these): one hub port is put
596 * into test mode according to USB2 11.24.2.13, then the hub
597 * must be reset (which for root hub now means rmmod+modprobe,
598 * or else system reboot). See EHCI 2.3.9 and 4.14 for info
599 * about the EHCI-specific stuff.
600 */
601 case USB_PORT_FEAT_TEST:
602 if (!selector || selector > 5)
603 goto error;
604 ehci_quiesce(ehci);
605 ehci_halt(ehci);
606 temp |= selector << 16;
607 writel (temp, &ehci->regs->port_status [wIndex]);
608 break;
609
562 default: 610 default:
563 goto error; 611 goto error;
564 } 612 }
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index e51c1ed81ac4..4bc7970ba3ef 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -257,9 +257,7 @@ static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
257static int ehci_pci_resume(struct usb_hcd *hcd) 257static int ehci_pci_resume(struct usb_hcd *hcd)
258{ 258{
259 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 259 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
260 unsigned port;
261 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 260 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
262 int retval = -EINVAL;
263 261
264 // maybe restore FLADJ 262 // maybe restore FLADJ
265 263
@@ -269,27 +267,19 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
269 /* Mark hardware accessible again as we are out of D3 state by now */ 267 /* Mark hardware accessible again as we are out of D3 state by now */
270 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 268 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
271 269
272 /* If CF is clear, we lost PCI Vaux power and need to restart. */ 270 /* If CF is still set, we maintained PCI Vaux power.
273 if (readl(&ehci->regs->configured_flag) != FLAG_CF) 271 * Just undo the effect of ehci_pci_suspend().
274 goto restart;
275
276 /* If any port is suspended (or owned by the companion),
277 * we know we can/must resume the HC (and mustn't reset it).
278 * We just defer that to the root hub code.
279 */ 272 */
280 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { 273 if (readl(&ehci->regs->configured_flag) == FLAG_CF) {
281 u32 status; 274 int mask = INTR_MASK;
282 port--; 275
283 status = readl(&ehci->regs->port_status [port]); 276 if (!device_may_wakeup(&hcd->self.root_hub->dev))
284 if (!(status & PORT_POWER)) 277 mask &= ~STS_PCD;
285 continue; 278 writel(mask, &ehci->regs->intr_enable);
286 if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { 279 readl(&ehci->regs->intr_enable);
287 usb_hcd_resume_root_hub(hcd); 280 return 0;
288 return 0;
289 }
290 } 281 }
291 282
292restart:
293 ehci_dbg(ehci, "lost power, restarting\n"); 283 ehci_dbg(ehci, "lost power, restarting\n");
294 usb_root_hub_lost_power(hcd->self.root_hub); 284 usb_root_hub_lost_power(hcd->self.root_hub);
295 285
@@ -307,13 +297,15 @@ restart:
307 ehci_work(ehci); 297 ehci_work(ehci);
308 spin_unlock_irq(&ehci->lock); 298 spin_unlock_irq(&ehci->lock);
309 299
310 /* restart; khubd will disconnect devices */
311 retval = ehci_run(hcd);
312
313 /* here we "know" root ports should always stay powered */ 300 /* here we "know" root ports should always stay powered */
314 ehci_port_power(ehci, 1); 301 ehci_port_power(ehci, 1);
315 302
316 return retval; 303 writel(ehci->command, &ehci->regs->command);
304 writel(FLAG_CF, &ehci->regs->configured_flag);
305 readl(&ehci->regs->command); /* unblock posted writes */
306
307 hcd->state = HC_STATE_SUSPENDED;
308 return 0;
317} 309}
318#endif 310#endif
319 311
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index bbc3082a73d7..74dbc6c8228f 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -74,6 +74,7 @@ struct ehci_hcd { /* one per controller */
74 74
75 /* per root hub port */ 75 /* per root hub port */
76 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 76 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
77 unsigned long bus_suspended;
77 78
78 /* per-HC memory pools (could be per-bus, but ...) */ 79 /* per-HC memory pools (could be per-bus, but ...) */
79 struct dma_pool *qh_pool; /* qh per active urb */ 80 struct dma_pool *qh_pool; /* qh per active urb */
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ea4714e557e4..a95275a401b1 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -729,6 +729,16 @@ static irqreturn_t ohci_irq (struct usb_hcd *hcd)
729 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 729 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
730 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 730 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
731 &regs->intrstatus); 731 &regs->intrstatus);
732
733 /* NOTE: Vendors didn't always make the same implementation
734 * choices for RHSC. Many followed the spec; RHSC triggers
735 * on an edge, like setting and maybe clearing a port status
736 * change bit. With others it's level-triggered, active
737 * until khubd clears all the port status change bits. We'll
738 * always disable it here and rely on polling until khubd
739 * re-enables it.
740 */
741 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
732 usb_hcd_poll_rh_status(hcd); 742 usb_hcd_poll_rh_status(hcd);
733 } 743 }
734 744
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index 6995ea36f2e8..2441642cb7b4 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -41,7 +41,11 @@ static void ohci_rhsc_enable (struct usb_hcd *hcd)
41{ 41{
42 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 42 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
43 43
44 ohci_writel (ohci, OHCI_INTR_RHSC, &ohci->regs->intrenable); 44 spin_lock_irq(&ohci->lock);
45 if (!ohci->autostop)
46 del_timer(&hcd->rh_timer); /* Prevent next poll */
47 ohci_writel(ohci, OHCI_INTR_RHSC, &ohci->regs->intrenable);
48 spin_unlock_irq(&ohci->lock);
45} 49}
46 50
47#define OHCI_SCHED_ENABLES \ 51#define OHCI_SCHED_ENABLES \
@@ -50,6 +54,9 @@ static void ohci_rhsc_enable (struct usb_hcd *hcd)
50static void dl_done_list (struct ohci_hcd *); 54static void dl_done_list (struct ohci_hcd *);
51static void finish_unlinks (struct ohci_hcd *, u16); 55static void finish_unlinks (struct ohci_hcd *, u16);
52 56
57#ifdef CONFIG_PM
58static int ohci_restart(struct ohci_hcd *ohci);
59
53static int ohci_rh_suspend (struct ohci_hcd *ohci, int autostop) 60static int ohci_rh_suspend (struct ohci_hcd *ohci, int autostop)
54__releases(ohci->lock) 61__releases(ohci->lock)
55__acquires(ohci->lock) 62__acquires(ohci->lock)
@@ -132,8 +139,6 @@ static inline struct ed *find_head (struct ed *ed)
132 return ed; 139 return ed;
133} 140}
134 141
135static int ohci_restart (struct ohci_hcd *ohci);
136
137/* caller has locked the root hub */ 142/* caller has locked the root hub */
138static int ohci_rh_resume (struct ohci_hcd *ohci) 143static int ohci_rh_resume (struct ohci_hcd *ohci)
139__releases(ohci->lock) 144__releases(ohci->lock)
@@ -169,7 +174,7 @@ __acquires(ohci->lock)
169 break; 174 break;
170 case OHCI_USB_RESUME: 175 case OHCI_USB_RESUME:
171 /* HCFS changes sometime after INTR_RD */ 176 /* HCFS changes sometime after INTR_RD */
172 ohci_info(ohci, "%swakeup\n", 177 ohci_dbg(ohci, "%swakeup root hub\n",
173 autostopped ? "auto-" : ""); 178 autostopped ? "auto-" : "");
174 break; 179 break;
175 case OHCI_USB_OPER: 180 case OHCI_USB_OPER:
@@ -181,7 +186,6 @@ __acquires(ohci->lock)
181 ohci_dbg (ohci, "lost power\n"); 186 ohci_dbg (ohci, "lost power\n");
182 status = -EBUSY; 187 status = -EBUSY;
183 } 188 }
184#ifdef CONFIG_PM
185 if (status == -EBUSY) { 189 if (status == -EBUSY) {
186 if (!autostopped) { 190 if (!autostopped) {
187 spin_unlock_irq (&ohci->lock); 191 spin_unlock_irq (&ohci->lock);
@@ -191,25 +195,12 @@ __acquires(ohci->lock)
191 } 195 }
192 return status; 196 return status;
193 } 197 }
194#endif
195 if (status != -EINPROGRESS) 198 if (status != -EINPROGRESS)
196 return status; 199 return status;
197 if (autostopped) 200 if (autostopped)
198 goto skip_resume; 201 goto skip_resume;
199 spin_unlock_irq (&ohci->lock); 202 spin_unlock_irq (&ohci->lock);
200 203
201 temp = ohci->num_ports;
202 while (temp--) {
203 u32 stat = ohci_readl (ohci,
204 &ohci->regs->roothub.portstatus [temp]);
205
206 /* force global, not selective, resume */
207 if (!(stat & RH_PS_PSS))
208 continue;
209 ohci_writel (ohci, RH_PS_POCI,
210 &ohci->regs->roothub.portstatus [temp]);
211 }
212
213 /* Some controllers (lucent erratum) need extra-long delays */ 204 /* Some controllers (lucent erratum) need extra-long delays */
214 msleep (20 /* usb 11.5.1.10 */ + 12 /* 32 msec counter */ + 1); 205 msleep (20 /* usb 11.5.1.10 */ + 12 /* 32 msec counter */ + 1);
215 206
@@ -217,6 +208,7 @@ __acquires(ohci->lock)
217 temp &= OHCI_CTRL_HCFS; 208 temp &= OHCI_CTRL_HCFS;
218 if (temp != OHCI_USB_RESUME) { 209 if (temp != OHCI_USB_RESUME) {
219 ohci_err (ohci, "controller won't resume\n"); 210 ohci_err (ohci, "controller won't resume\n");
211 spin_lock_irq(&ohci->lock);
220 return -EBUSY; 212 return -EBUSY;
221 } 213 }
222 214
@@ -296,8 +288,6 @@ skip_resume:
296 return 0; 288 return 0;
297} 289}
298 290
299#ifdef CONFIG_PM
300
301static int ohci_bus_suspend (struct usb_hcd *hcd) 291static int ohci_bus_suspend (struct usb_hcd *hcd)
302{ 292{
303 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 293 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
@@ -335,6 +325,83 @@ static int ohci_bus_resume (struct usb_hcd *hcd)
335 return rc; 325 return rc;
336} 326}
337 327
328/* Carry out polling-, autostop-, and autoresume-related state changes */
329static int ohci_root_hub_state_changes(struct ohci_hcd *ohci, int changed,
330 int any_connected)
331{
332 int poll_rh = 1;
333
334 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
335
336 case OHCI_USB_OPER:
337 /* keep on polling until we know a device is connected
338 * and RHSC is enabled */
339 if (!ohci->autostop) {
340 if (any_connected ||
341 !device_may_wakeup(&ohci_to_hcd(ohci)
342 ->self.root_hub->dev)) {
343 if (ohci_readl(ohci, &ohci->regs->intrenable) &
344 OHCI_INTR_RHSC)
345 poll_rh = 0;
346 } else {
347 ohci->autostop = 1;
348 ohci->next_statechange = jiffies + HZ;
349 }
350
351 /* if no devices have been attached for one second, autostop */
352 } else {
353 if (changed || any_connected) {
354 ohci->autostop = 0;
355 ohci->next_statechange = jiffies +
356 STATECHANGE_DELAY;
357 } else if (time_after_eq(jiffies,
358 ohci->next_statechange)
359 && !ohci->ed_rm_list
360 && !(ohci->hc_control &
361 OHCI_SCHED_ENABLES)) {
362 ohci_rh_suspend(ohci, 1);
363 }
364 }
365 break;
366
367 /* if there is a port change, autostart or ask to be resumed */
368 case OHCI_USB_SUSPEND:
369 case OHCI_USB_RESUME:
370 if (changed) {
371 if (ohci->autostop)
372 ohci_rh_resume(ohci);
373 else
374 usb_hcd_resume_root_hub(ohci_to_hcd(ohci));
375 } else {
376 /* everything is idle, no need for polling */
377 poll_rh = 0;
378 }
379 break;
380 }
381 return poll_rh;
382}
383
384#else /* CONFIG_PM */
385
386static inline int ohci_rh_resume(struct ohci_hcd *ohci)
387{
388 return 0;
389}
390
391/* Carry out polling-related state changes.
392 * autostop isn't used when CONFIG_PM is turned off.
393 */
394static int ohci_root_hub_state_changes(struct ohci_hcd *ohci, int changed,
395 int any_connected)
396{
397 int poll_rh = 1;
398
399 /* keep on polling until RHSC is enabled */
400 if (ohci_readl(ohci, &ohci->regs->intrenable) & OHCI_INTR_RHSC)
401 poll_rh = 0;
402 return poll_rh;
403}
404
338#endif /* CONFIG_PM */ 405#endif /* CONFIG_PM */
339 406
340/*-------------------------------------------------------------------------*/ 407/*-------------------------------------------------------------------------*/
@@ -346,7 +413,7 @@ ohci_hub_status_data (struct usb_hcd *hcd, char *buf)
346{ 413{
347 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 414 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
348 int i, changed = 0, length = 1; 415 int i, changed = 0, length = 1;
349 int any_connected = 0, rhsc_enabled = 1; 416 int any_connected = 0;
350 unsigned long flags; 417 unsigned long flags;
351 418
352 spin_lock_irqsave (&ohci->lock, flags); 419 spin_lock_irqsave (&ohci->lock, flags);
@@ -387,67 +454,8 @@ ohci_hub_status_data (struct usb_hcd *hcd, char *buf)
387 } 454 }
388 } 455 }
389 456
390 /* NOTE: vendors didn't always make the same implementation 457 hcd->poll_rh = ohci_root_hub_state_changes(ohci, changed,
391 * choices for RHSC. Sometimes it triggers on an edge (like 458 any_connected);
392 * setting and maybe clearing a port status change bit); and
393 * it's level-triggered on other silicon, active until khubd
394 * clears all active port status change bits. If it's still
395 * set (level-triggered) we must disable it and rely on
396 * polling until khubd re-enables it.
397 */
398 if (ohci_readl (ohci, &ohci->regs->intrstatus) & OHCI_INTR_RHSC) {
399 ohci_writel (ohci, OHCI_INTR_RHSC, &ohci->regs->intrdisable);
400 (void) ohci_readl (ohci, &ohci->regs->intrdisable);
401 rhsc_enabled = 0;
402 }
403 hcd->poll_rh = 1;
404
405 /* carry out appropriate state changes */
406 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
407
408 case OHCI_USB_OPER:
409 /* keep on polling until we know a device is connected
410 * and RHSC is enabled */
411 if (!ohci->autostop) {
412 if (any_connected) {
413 if (rhsc_enabled)
414 hcd->poll_rh = 0;
415 } else {
416 ohci->autostop = 1;
417 ohci->next_statechange = jiffies + HZ;
418 }
419
420 /* if no devices have been attached for one second, autostop */
421 } else {
422 if (changed || any_connected) {
423 ohci->autostop = 0;
424 ohci->next_statechange = jiffies +
425 STATECHANGE_DELAY;
426 } else if (device_may_wakeup(&hcd->self.root_hub->dev)
427 && time_after_eq(jiffies,
428 ohci->next_statechange)
429 && !ohci->ed_rm_list
430 && !(ohci->hc_control &
431 OHCI_SCHED_ENABLES)) {
432 ohci_rh_suspend (ohci, 1);
433 }
434 }
435 break;
436
437 /* if there is a port change, autostart or ask to be resumed */
438 case OHCI_USB_SUSPEND:
439 case OHCI_USB_RESUME:
440 if (changed) {
441 if (ohci->autostop)
442 ohci_rh_resume (ohci);
443 else
444 usb_hcd_resume_root_hub (hcd);
445 } else {
446 /* everything is idle, no need for polling */
447 hcd->poll_rh = 0;
448 }
449 break;
450 }
451 459
452done: 460done:
453 spin_unlock_irqrestore (&ohci->lock, flags); 461 spin_unlock_irqrestore (&ohci->lock, flags);
diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c
index 4f95a249c913..a9d7119e3176 100644
--- a/drivers/usb/host/u132-hcd.c
+++ b/drivers/usb/host/u132-hcd.c
@@ -71,7 +71,7 @@ static int distrust_firmware = 1;
71module_param(distrust_firmware, bool, 0); 71module_param(distrust_firmware, bool, 0);
72MODULE_PARM_DESC(distrust_firmware, "true to distrust firmware power/overcurren" 72MODULE_PARM_DESC(distrust_firmware, "true to distrust firmware power/overcurren"
73 "t setup"); 73 "t setup");
74DECLARE_WAIT_QUEUE_HEAD(u132_hcd_wait); 74static DECLARE_WAIT_QUEUE_HEAD(u132_hcd_wait);
75/* 75/*
76* u132_module_lock exists to protect access to global variables 76* u132_module_lock exists to protect access to global variables
77* 77*
@@ -205,13 +205,9 @@ struct u132 {
205 struct u132_port port[MAX_U132_PORTS]; 205 struct u132_port port[MAX_U132_PORTS];
206 struct u132_endp *endp[MAX_U132_ENDPS]; 206 struct u132_endp *endp[MAX_U132_ENDPS];
207}; 207};
208int usb_ftdi_elan_read_reg(struct platform_device *pdev, u32 *data); 208
209int usb_ftdi_elan_read_pcimem(struct platform_device *pdev, u8 addressofs,
210 u8 width, u32 *data);
211int usb_ftdi_elan_write_pcimem(struct platform_device *pdev, u8 addressofs,
212 u8 width, u32 data);
213/* 209/*
214* these can not be inlines because we need the structure offset!! 210* these cannot be inlines because we need the structure offset!!
215* Does anyone have a better way????? 211* Does anyone have a better way?????
216*/ 212*/
217#define u132_read_pcimem(u132, member, data) \ 213#define u132_read_pcimem(u132, member, data) \
@@ -3031,7 +3027,7 @@ static struct hc_driver u132_hc_driver = {
3031* This function may be called by the USB core whilst the "usb_all_devices_rwsem" 3027* This function may be called by the USB core whilst the "usb_all_devices_rwsem"
3032* is held for writing, thus this module must not call usb_remove_hcd() 3028* is held for writing, thus this module must not call usb_remove_hcd()
3033* synchronously - but instead should immediately stop activity to the 3029* synchronously - but instead should immediately stop activity to the
3034* device and ansynchronously call usb_remove_hcd() 3030* device and asynchronously call usb_remove_hcd()
3035*/ 3031*/
3036static int __devexit u132_remove(struct platform_device *pdev) 3032static int __devexit u132_remove(struct platform_device *pdev)
3037{ 3033{
@@ -3227,7 +3223,7 @@ static int u132_resume(struct platform_device *pdev)
3227#define u132_resume NULL 3223#define u132_resume NULL
3228#endif 3224#endif
3229/* 3225/*
3230* this driver is loaded explicitely by ftdi_u132 3226* this driver is loaded explicitly by ftdi_u132
3231* 3227*
3232* the platform_driver struct is static because it is per type of module 3228* the platform_driver struct is static because it is per type of module
3233*/ 3229*/
diff --git a/drivers/usb/image/microtek.c b/drivers/usb/image/microtek.c
index 3038ed0700d3..8ccddf74534a 100644
--- a/drivers/usb/image/microtek.c
+++ b/drivers/usb/image/microtek.c
@@ -796,7 +796,7 @@ static int mts_usb_probe(struct usb_interface *intf,
796 796
797 new_desc->context.scsi_status = kmalloc(1, GFP_KERNEL); 797 new_desc->context.scsi_status = kmalloc(1, GFP_KERNEL);
798 if (!new_desc->context.scsi_status) 798 if (!new_desc->context.scsi_status)
799 goto out_kfree2; 799 goto out_free_urb;
800 800
801 new_desc->usb_dev = dev; 801 new_desc->usb_dev = dev;
802 new_desc->usb_intf = intf; 802 new_desc->usb_intf = intf;
@@ -822,18 +822,20 @@ static int mts_usb_probe(struct usb_interface *intf,
822 new_desc->host = scsi_host_alloc(&mts_scsi_host_template, 822 new_desc->host = scsi_host_alloc(&mts_scsi_host_template,
823 sizeof(new_desc)); 823 sizeof(new_desc));
824 if (!new_desc->host) 824 if (!new_desc->host)
825 goto out_free_urb; 825 goto out_kfree2;
826 826
827 new_desc->host->hostdata[0] = (unsigned long)new_desc; 827 new_desc->host->hostdata[0] = (unsigned long)new_desc;
828 if (scsi_add_host(new_desc->host, NULL)) { 828 if (scsi_add_host(new_desc->host, NULL)) {
829 err_retval = -EIO; 829 err_retval = -EIO;
830 goto out_free_urb; 830 goto out_host_put;
831 } 831 }
832 scsi_scan_host(new_desc->host); 832 scsi_scan_host(new_desc->host);
833 833
834 usb_set_intfdata(intf, new_desc); 834 usb_set_intfdata(intf, new_desc);
835 return 0; 835 return 0;
836 836
837 out_host_put:
838 scsi_host_put(new_desc->host);
837 out_kfree2: 839 out_kfree2:
838 kfree(new_desc->context.scsi_status); 840 kfree(new_desc->context.scsi_status);
839 out_free_urb: 841 out_free_urb:
diff --git a/drivers/usb/input/Kconfig b/drivers/usb/input/Kconfig
index 20db36448ab3..661af7aa6236 100644
--- a/drivers/usb/input/Kconfig
+++ b/drivers/usb/input/Kconfig
@@ -221,6 +221,7 @@ config USB_TOUCHSCREEN
221 - ITM 221 - ITM
222 - some other eTurboTouch 222 - some other eTurboTouch
223 - Gunze AHL61 223 - Gunze AHL61
224 - DMC TSC-10/25
224 225
225 Have a look at <http://linux.chapter7.ch/touchkit/> for 226 Have a look at <http://linux.chapter7.ch/touchkit/> for
226 a usage description and the required user-space stuff. 227 a usage description and the required user-space stuff.
@@ -258,6 +259,11 @@ config USB_TOUCHSCREEN_GUNZE
258 bool "Gunze AHL61 device support" if EMBEDDED 259 bool "Gunze AHL61 device support" if EMBEDDED
259 depends on USB_TOUCHSCREEN 260 depends on USB_TOUCHSCREEN
260 261
262config USB_TOUCHSCREEN_DMC_TSC10
263 default y
264 bool "DMC TSC-10/25 device support" if EMBEDDED
265 depends on USB_TOUCHSCREEN
266
261config USB_YEALINK 267config USB_YEALINK
262 tristate "Yealink usb-p1k voip phone" 268 tristate "Yealink usb-p1k voip phone"
263 depends on USB && INPUT && EXPERIMENTAL 269 depends on USB && INPUT && EXPERIMENTAL
diff --git a/drivers/usb/input/ati_remote.c b/drivers/usb/input/ati_remote.c
index f659f3028ad2..ff23318dc301 100644
--- a/drivers/usb/input/ati_remote.c
+++ b/drivers/usb/input/ati_remote.c
@@ -630,19 +630,14 @@ static int ati_remote_alloc_buffers(struct usb_device *udev,
630 */ 630 */
631static void ati_remote_free_buffers(struct ati_remote *ati_remote) 631static void ati_remote_free_buffers(struct ati_remote *ati_remote)
632{ 632{
633 if (ati_remote->irq_urb) 633 usb_free_urb(ati_remote->irq_urb);
634 usb_free_urb(ati_remote->irq_urb); 634 usb_free_urb(ati_remote->out_urb);
635 635
636 if (ati_remote->out_urb) 636 usb_buffer_free(ati_remote->udev, DATA_BUFSIZE,
637 usb_free_urb(ati_remote->out_urb); 637 ati_remote->inbuf, ati_remote->inbuf_dma);
638 638
639 if (ati_remote->inbuf) 639 usb_buffer_free(ati_remote->udev, DATA_BUFSIZE,
640 usb_buffer_free(ati_remote->udev, DATA_BUFSIZE, 640 ati_remote->outbuf, ati_remote->outbuf_dma);
641 ati_remote->inbuf, ati_remote->inbuf_dma);
642
643 if (ati_remote->outbuf)
644 usb_buffer_free(ati_remote->udev, DATA_BUFSIZE,
645 ati_remote->inbuf, ati_remote->outbuf_dma);
646} 641}
647 642
648static void ati_remote_input_init(struct ati_remote *ati_remote) 643static void ati_remote_input_init(struct ati_remote *ati_remote)
diff --git a/drivers/usb/input/ati_remote2.c b/drivers/usb/input/ati_remote2.c
index f982a2b4a7f9..83f1f79db7c7 100644
--- a/drivers/usb/input/ati_remote2.c
+++ b/drivers/usb/input/ati_remote2.c
@@ -372,8 +372,7 @@ static void ati_remote2_urb_cleanup(struct ati_remote2 *ar2)
372 int i; 372 int i;
373 373
374 for (i = 0; i < 2; i++) { 374 for (i = 0; i < 2; i++) {
375 if (ar2->urb[i]) 375 usb_free_urb(ar2->urb[i]);
376 usb_free_urb(ar2->urb[i]);
377 376
378 if (ar2->buf[i]) 377 if (ar2->buf[i])
379 usb_buffer_free(ar2->udev, 4, ar2->buf[i], ar2->buf_dma[i]); 378 usb_buffer_free(ar2->udev, 4, ar2->buf[i], ar2->buf_dma[i]);
diff --git a/drivers/usb/input/hid-core.c b/drivers/usb/input/hid-core.c
index ebc9e823a46e..4295bab4f1e2 100644
--- a/drivers/usb/input/hid-core.c
+++ b/drivers/usb/input/hid-core.c
@@ -968,21 +968,30 @@ static void hid_retry_timeout(unsigned long _hid)
968 hid_io_error(hid); 968 hid_io_error(hid);
969} 969}
970 970
971/* Workqueue routine to reset the device */ 971/* Workqueue routine to reset the device or clear a halt */
972static void hid_reset(struct work_struct *work) 972static void hid_reset(struct work_struct *work)
973{ 973{
974 struct hid_device *hid = 974 struct hid_device *hid =
975 container_of(work, struct hid_device, reset_work); 975 container_of(work, struct hid_device, reset_work);
976 int rc_lock, rc; 976 int rc_lock, rc = 0;
977 977
978 dev_dbg(&hid->intf->dev, "resetting device\n"); 978 if (test_bit(HID_CLEAR_HALT, &hid->iofl)) {
979 rc = rc_lock = usb_lock_device_for_reset(hid->dev, hid->intf); 979 dev_dbg(&hid->intf->dev, "clear halt\n");
980 if (rc_lock >= 0) { 980 rc = usb_clear_halt(hid->dev, hid->urbin->pipe);
981 rc = usb_reset_composite_device(hid->dev, hid->intf); 981 clear_bit(HID_CLEAR_HALT, &hid->iofl);
982 if (rc_lock) 982 hid_start_in(hid);
983 usb_unlock_device(hid->dev); 983 }
984
985 else if (test_bit(HID_RESET_PENDING, &hid->iofl)) {
986 dev_dbg(&hid->intf->dev, "resetting device\n");
987 rc = rc_lock = usb_lock_device_for_reset(hid->dev, hid->intf);
988 if (rc_lock >= 0) {
989 rc = usb_reset_composite_device(hid->dev, hid->intf);
990 if (rc_lock)
991 usb_unlock_device(hid->dev);
992 }
993 clear_bit(HID_RESET_PENDING, &hid->iofl);
984 } 994 }
985 clear_bit(HID_RESET_PENDING, &hid->iofl);
986 995
987 switch (rc) { 996 switch (rc) {
988 case 0: 997 case 0:
@@ -1024,9 +1033,8 @@ static void hid_io_error(struct hid_device *hid)
1024 1033
1025 /* Retries failed, so do a port reset */ 1034 /* Retries failed, so do a port reset */
1026 if (!test_and_set_bit(HID_RESET_PENDING, &hid->iofl)) { 1035 if (!test_and_set_bit(HID_RESET_PENDING, &hid->iofl)) {
1027 if (schedule_work(&hid->reset_work)) 1036 schedule_work(&hid->reset_work);
1028 goto done; 1037 goto done;
1029 clear_bit(HID_RESET_PENDING, &hid->iofl);
1030 } 1038 }
1031 } 1039 }
1032 1040
@@ -1050,6 +1058,11 @@ static void hid_irq_in(struct urb *urb)
1050 hid->retry_delay = 0; 1058 hid->retry_delay = 0;
1051 hid_input_report(HID_INPUT_REPORT, urb, 1); 1059 hid_input_report(HID_INPUT_REPORT, urb, 1);
1052 break; 1060 break;
1061 case -EPIPE: /* stall */
1062 clear_bit(HID_IN_RUNNING, &hid->iofl);
1063 set_bit(HID_CLEAR_HALT, &hid->iofl);
1064 schedule_work(&hid->reset_work);
1065 return;
1053 case -ECONNRESET: /* unlink */ 1066 case -ECONNRESET: /* unlink */
1054 case -ENOENT: 1067 case -ENOENT:
1055 case -ESHUTDOWN: /* unplug */ 1068 case -ESHUTDOWN: /* unplug */
@@ -1628,6 +1641,19 @@ void hid_init_reports(struct hid_device *hid)
1628 1641
1629#define USB_VENDOR_ID_APPLE 0x05ac 1642#define USB_VENDOR_ID_APPLE 0x05ac
1630#define USB_DEVICE_ID_APPLE_MIGHTYMOUSE 0x0304 1643#define USB_DEVICE_ID_APPLE_MIGHTYMOUSE 0x0304
1644#define USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI 0x020e
1645#define USB_DEVICE_ID_APPLE_FOUNTAIN_ISO 0x020f
1646#define USB_DEVICE_ID_APPLE_GEYSER_ANSI 0x0214
1647#define USB_DEVICE_ID_APPLE_GEYSER_ISO 0x0215
1648#define USB_DEVICE_ID_APPLE_GEYSER_JIS 0x0216
1649#define USB_DEVICE_ID_APPLE_GEYSER3_ANSI 0x0217
1650#define USB_DEVICE_ID_APPLE_GEYSER3_ISO 0x0218
1651#define USB_DEVICE_ID_APPLE_GEYSER3_JIS 0x0219
1652#define USB_DEVICE_ID_APPLE_GEYSER4_ANSI 0x021a
1653#define USB_DEVICE_ID_APPLE_GEYSER4_ISO 0x021b
1654#define USB_DEVICE_ID_APPLE_GEYSER4_JIS 0x021c
1655#define USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY 0x030a
1656#define USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY 0x030b
1631 1657
1632#define USB_VENDOR_ID_CHERRY 0x046a 1658#define USB_VENDOR_ID_CHERRY 0x046a
1633#define USB_DEVICE_ID_CHERRY_CYMOTION 0x0023 1659#define USB_DEVICE_ID_CHERRY_CYMOTION 0x0023
@@ -1795,17 +1821,19 @@ static const struct hid_blacklist {
1795 1821
1796 { USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION, HID_QUIRK_CYMOTION }, 1822 { USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION, HID_QUIRK_CYMOTION },
1797 1823
1798 { USB_VENDOR_ID_APPLE, 0x020E, HID_QUIRK_POWERBOOK_HAS_FN }, 1824 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI, HID_QUIRK_POWERBOOK_HAS_FN },
1799 { USB_VENDOR_ID_APPLE, 0x020F, HID_QUIRK_POWERBOOK_HAS_FN }, 1825 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ISO, HID_QUIRK_POWERBOOK_HAS_FN },
1800 { USB_VENDOR_ID_APPLE, 0x0214, HID_QUIRK_POWERBOOK_HAS_FN }, 1826 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ANSI, HID_QUIRK_POWERBOOK_HAS_FN },
1801 { USB_VENDOR_ID_APPLE, 0x0215, HID_QUIRK_POWERBOOK_HAS_FN | HID_QUIRK_POWERBOOK_ISO_KEYBOARD}, 1827 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ISO, HID_QUIRK_POWERBOOK_HAS_FN | HID_QUIRK_POWERBOOK_ISO_KEYBOARD},
1802 { USB_VENDOR_ID_APPLE, 0x0216, HID_QUIRK_POWERBOOK_HAS_FN }, 1828 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_JIS, HID_QUIRK_POWERBOOK_HAS_FN },
1803 { USB_VENDOR_ID_APPLE, 0x0217, HID_QUIRK_POWERBOOK_HAS_FN }, 1829 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_ANSI, HID_QUIRK_POWERBOOK_HAS_FN },
1804 { USB_VENDOR_ID_APPLE, 0x0218, HID_QUIRK_POWERBOOK_HAS_FN | HID_QUIRK_POWERBOOK_ISO_KEYBOARD}, 1830 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_ISO, HID_QUIRK_POWERBOOK_HAS_FN | HID_QUIRK_POWERBOOK_ISO_KEYBOARD},
1805 { USB_VENDOR_ID_APPLE, 0x0219, HID_QUIRK_POWERBOOK_HAS_FN }, 1831 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_JIS, HID_QUIRK_POWERBOOK_HAS_FN },
1806 { USB_VENDOR_ID_APPLE, 0x021B, HID_QUIRK_POWERBOOK_HAS_FN }, 1832 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_ANSI, HID_QUIRK_POWERBOOK_HAS_FN },
1807 { USB_VENDOR_ID_APPLE, 0x030A, HID_QUIRK_POWERBOOK_HAS_FN }, 1833 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_ISO, HID_QUIRK_POWERBOOK_HAS_FN },
1808 { USB_VENDOR_ID_APPLE, 0x030B, HID_QUIRK_POWERBOOK_HAS_FN }, 1834 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_JIS, HID_QUIRK_POWERBOOK_HAS_FN },
1835 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY, HID_QUIRK_POWERBOOK_HAS_FN },
1836 { USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY, HID_QUIRK_POWERBOOK_HAS_FN },
1809 1837
1810 { USB_VENDOR_ID_PANJIT, 0x0001, HID_QUIRK_IGNORE }, 1838 { USB_VENDOR_ID_PANJIT, 0x0001, HID_QUIRK_IGNORE },
1811 { USB_VENDOR_ID_PANJIT, 0x0002, HID_QUIRK_IGNORE }, 1839 { USB_VENDOR_ID_PANJIT, 0x0002, HID_QUIRK_IGNORE },
@@ -1986,7 +2014,7 @@ static struct hid_device *usb_hid_configure(struct usb_interface *intf)
1986 if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0) 2014 if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0)
1987 interval = hid_mousepoll_interval; 2015 interval = hid_mousepoll_interval;
1988 2016
1989 if (endpoint->bEndpointAddress & USB_DIR_IN) { 2017 if (usb_endpoint_dir_in(endpoint)) {
1990 if (hid->urbin) 2018 if (hid->urbin)
1991 continue; 2019 continue;
1992 if (!(hid->urbin = usb_alloc_urb(0, GFP_KERNEL))) 2020 if (!(hid->urbin = usb_alloc_urb(0, GFP_KERNEL)))
@@ -2068,13 +2096,9 @@ static struct hid_device *usb_hid_configure(struct usb_interface *intf)
2068 return hid; 2096 return hid;
2069 2097
2070fail: 2098fail:
2071 2099 usb_free_urb(hid->urbin);
2072 if (hid->urbin) 2100 usb_free_urb(hid->urbout);
2073 usb_free_urb(hid->urbin); 2101 usb_free_urb(hid->urbctrl);
2074 if (hid->urbout)
2075 usb_free_urb(hid->urbout);
2076 if (hid->urbctrl)
2077 usb_free_urb(hid->urbctrl);
2078 hid_free_buffers(dev, hid); 2102 hid_free_buffers(dev, hid);
2079 hid_free_device(hid); 2103 hid_free_device(hid);
2080 2104
@@ -2105,8 +2129,7 @@ static void hid_disconnect(struct usb_interface *intf)
2105 2129
2106 usb_free_urb(hid->urbin); 2130 usb_free_urb(hid->urbin);
2107 usb_free_urb(hid->urbctrl); 2131 usb_free_urb(hid->urbctrl);
2108 if (hid->urbout) 2132 usb_free_urb(hid->urbout);
2109 usb_free_urb(hid->urbout);
2110 2133
2111 hid_free_buffers(hid->dev, hid); 2134 hid_free_buffers(hid->dev, hid);
2112 hid_free_device(hid); 2135 hid_free_device(hid);
diff --git a/drivers/usb/input/hid.h b/drivers/usb/input/hid.h
index 0e76e6dcac37..2a9bf07944c0 100644
--- a/drivers/usb/input/hid.h
+++ b/drivers/usb/input/hid.h
@@ -385,6 +385,7 @@ struct hid_control_fifo {
385#define HID_IN_RUNNING 3 385#define HID_IN_RUNNING 3
386#define HID_RESET_PENDING 4 386#define HID_RESET_PENDING 4
387#define HID_SUSPENDED 5 387#define HID_SUSPENDED 5
388#define HID_CLEAR_HALT 6
388 389
389struct hid_input { 390struct hid_input {
390 struct list_head list; 391 struct list_head list;
diff --git a/drivers/usb/input/usbkbd.c b/drivers/usb/input/usbkbd.c
index c73285cf8558..dac88640eab6 100644
--- a/drivers/usb/input/usbkbd.c
+++ b/drivers/usb/input/usbkbd.c
@@ -208,10 +208,8 @@ static int usb_kbd_alloc_mem(struct usb_device *dev, struct usb_kbd *kbd)
208 208
209static void usb_kbd_free_mem(struct usb_device *dev, struct usb_kbd *kbd) 209static void usb_kbd_free_mem(struct usb_device *dev, struct usb_kbd *kbd)
210{ 210{
211 if (kbd->irq) 211 usb_free_urb(kbd->irq);
212 usb_free_urb(kbd->irq); 212 usb_free_urb(kbd->led);
213 if (kbd->led)
214 usb_free_urb(kbd->led);
215 if (kbd->new) 213 if (kbd->new)
216 usb_buffer_free(dev, 8, kbd->new, kbd->new_dma); 214 usb_buffer_free(dev, 8, kbd->new, kbd->new_dma);
217 if (kbd->cr) 215 if (kbd->cr)
@@ -236,9 +234,7 @@ static int usb_kbd_probe(struct usb_interface *iface,
236 return -ENODEV; 234 return -ENODEV;
237 235
238 endpoint = &interface->endpoint[0].desc; 236 endpoint = &interface->endpoint[0].desc;
239 if (!(endpoint->bEndpointAddress & USB_DIR_IN)) 237 if (!usb_endpoint_is_int_in(endpoint))
240 return -ENODEV;
241 if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) != USB_ENDPOINT_XFER_INT)
242 return -ENODEV; 238 return -ENODEV;
243 239
244 pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress); 240 pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress);
diff --git a/drivers/usb/input/usbmouse.c b/drivers/usb/input/usbmouse.c
index cbbbea332ed7..68a55642c082 100644
--- a/drivers/usb/input/usbmouse.c
+++ b/drivers/usb/input/usbmouse.c
@@ -126,9 +126,7 @@ static int usb_mouse_probe(struct usb_interface *intf, const struct usb_device_i
126 return -ENODEV; 126 return -ENODEV;
127 127
128 endpoint = &interface->endpoint[0].desc; 128 endpoint = &interface->endpoint[0].desc;
129 if (!(endpoint->bEndpointAddress & USB_DIR_IN)) 129 if (!usb_endpoint_is_int_in(endpoint))
130 return -ENODEV;
131 if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) != USB_ENDPOINT_XFER_INT)
132 return -ENODEV; 130 return -ENODEV;
133 131
134 pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress); 132 pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress);
diff --git a/drivers/usb/input/usbtouchscreen.c b/drivers/usb/input/usbtouchscreen.c
index 933ceddf3dee..49704d4ed0e2 100644
--- a/drivers/usb/input/usbtouchscreen.c
+++ b/drivers/usb/input/usbtouchscreen.c
@@ -8,6 +8,7 @@
8 * - PanJit TouchSet 8 * - PanJit TouchSet
9 * - eTurboTouch 9 * - eTurboTouch
10 * - Gunze AHL61 10 * - Gunze AHL61
11 * - DMC TSC-10/25
11 * 12 *
12 * Copyright (C) 2004-2006 by Daniel Ritz <daniel.ritz@gmx.ch> 13 * Copyright (C) 2004-2006 by Daniel Ritz <daniel.ritz@gmx.ch>
13 * Copyright (C) by Todd E. Johnson (mtouchusb.c) 14 * Copyright (C) by Todd E. Johnson (mtouchusb.c)
@@ -30,6 +31,8 @@
30 * - ITM parts are from itmtouch.c 31 * - ITM parts are from itmtouch.c
31 * - 3M parts are from mtouchusb.c 32 * - 3M parts are from mtouchusb.c
32 * - PanJit parts are from an unmerged driver by Lanslott Gish 33 * - PanJit parts are from an unmerged driver by Lanslott Gish
34 * - DMC TSC 10/25 are from Holger Schurig, with ideas from an unmerged
35 * driver from Marius Vollmer
33 * 36 *
34 *****************************************************************************/ 37 *****************************************************************************/
35 38
@@ -44,7 +47,7 @@
44#include <linux/usb/input.h> 47#include <linux/usb/input.h>
45 48
46 49
47#define DRIVER_VERSION "v0.4" 50#define DRIVER_VERSION "v0.5"
48#define DRIVER_AUTHOR "Daniel Ritz <daniel.ritz@gmx.ch>" 51#define DRIVER_AUTHOR "Daniel Ritz <daniel.ritz@gmx.ch>"
49#define DRIVER_DESC "USB Touchscreen Driver" 52#define DRIVER_DESC "USB Touchscreen Driver"
50 53
@@ -103,6 +106,7 @@ enum {
103 DEVTYPE_ITM, 106 DEVTYPE_ITM,
104 DEVTYPE_ETURBO, 107 DEVTYPE_ETURBO,
105 DEVTYPE_GUNZE, 108 DEVTYPE_GUNZE,
109 DEVTYPE_DMC_TSC10,
106}; 110};
107 111
108static struct usb_device_id usbtouch_devices[] = { 112static struct usb_device_id usbtouch_devices[] = {
@@ -139,6 +143,10 @@ static struct usb_device_id usbtouch_devices[] = {
139 {USB_DEVICE(0x0637, 0x0001), .driver_info = DEVTYPE_GUNZE}, 143 {USB_DEVICE(0x0637, 0x0001), .driver_info = DEVTYPE_GUNZE},
140#endif 144#endif
141 145
146#ifdef CONFIG_USB_TOUCHSCREEN_DMC_TSC10
147 {USB_DEVICE(0x0afa, 0x03e8), .driver_info = DEVTYPE_DMC_TSC10},
148#endif
149
142 {} 150 {}
143}; 151};
144 152
@@ -313,6 +321,80 @@ static int gunze_read_data(unsigned char *pkt, int *x, int *y, int *touch, int *
313#endif 321#endif
314 322
315/***************************************************************************** 323/*****************************************************************************
324 * DMC TSC-10/25 Part
325 *
326 * Documentation about the controller and it's protocol can be found at
327 * http://www.dmccoltd.com/files/controler/tsc10usb_pi_e.pdf
328 * http://www.dmccoltd.com/files/controler/tsc25_usb_e.pdf
329 */
330#ifdef CONFIG_USB_TOUCHSCREEN_DMC_TSC10
331
332/* supported data rates. currently using 130 */
333#define TSC10_RATE_POINT 0x50
334#define TSC10_RATE_30 0x40
335#define TSC10_RATE_50 0x41
336#define TSC10_RATE_80 0x42
337#define TSC10_RATE_100 0x43
338#define TSC10_RATE_130 0x44
339#define TSC10_RATE_150 0x45
340
341/* commands */
342#define TSC10_CMD_RESET 0x55
343#define TSC10_CMD_RATE 0x05
344#define TSC10_CMD_DATA1 0x01
345
346static int dmc_tsc10_init(struct usbtouch_usb *usbtouch)
347{
348 struct usb_device *dev = usbtouch->udev;
349 int ret;
350 unsigned char buf[2];
351
352 /* reset */
353 buf[0] = buf[1] = 0xFF;
354 ret = usb_control_msg(dev, usb_rcvctrlpipe (dev, 0),
355 TSC10_CMD_RESET,
356 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
357 0, 0, buf, 2, USB_CTRL_SET_TIMEOUT);
358 if (ret < 0)
359 return ret;
360 if (buf[0] != 0x06 || buf[1] != 0x00)
361 return -ENODEV;
362
363 /* set coordinate output rate */
364 buf[0] = buf[1] = 0xFF;
365 ret = usb_control_msg(dev, usb_rcvctrlpipe (dev, 0),
366 TSC10_CMD_RATE,
367 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
368 TSC10_RATE_150, 0, buf, 2, USB_CTRL_SET_TIMEOUT);
369 if (ret < 0)
370 return ret;
371 if (buf[0] != 0x06 || buf[1] != 0x00)
372 return -ENODEV;
373
374 /* start sending data */
375 ret = usb_control_msg(dev, usb_rcvctrlpipe (dev, 0),
376 TSC10_CMD_DATA1,
377 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
378 0, 0, NULL, 0, USB_CTRL_SET_TIMEOUT);
379 if (ret < 0)
380 return ret;
381
382 return 0;
383}
384
385
386static int dmc_tsc10_read_data(unsigned char *pkt, int *x, int *y, int *touch, int *press)
387{
388 *x = ((pkt[2] & 0x03) << 8) | pkt[1];
389 *y = ((pkt[4] & 0x03) << 8) | pkt[3];
390 *touch = pkt[0] & 0x01;
391
392 return 1;
393}
394#endif
395
396
397/*****************************************************************************
316 * the different device descriptors 398 * the different device descriptors
317 */ 399 */
318static struct usbtouch_device_info usbtouch_dev_info[] = { 400static struct usbtouch_device_info usbtouch_dev_info[] = {
@@ -389,6 +471,18 @@ static struct usbtouch_device_info usbtouch_dev_info[] = {
389 .read_data = gunze_read_data, 471 .read_data = gunze_read_data,
390 }, 472 },
391#endif 473#endif
474
475#ifdef CONFIG_USB_TOUCHSCREEN_DMC_TSC10
476 [DEVTYPE_DMC_TSC10] = {
477 .min_xc = 0x0,
478 .max_xc = 0x03ff,
479 .min_yc = 0x0,
480 .max_yc = 0x03ff,
481 .rept_size = 5,
482 .init = dmc_tsc10_init,
483 .read_data = dmc_tsc10_read_data,
484 },
485#endif
392}; 486};
393 487
394 488
diff --git a/drivers/usb/input/wacom.h b/drivers/usb/input/wacom.h
index 1cf08f02c50e..d85abfc5ab58 100644
--- a/drivers/usb/input/wacom.h
+++ b/drivers/usb/input/wacom.h
@@ -110,7 +110,6 @@ struct wacom_combo {
110}; 110};
111 111
112extern int wacom_wac_irq(struct wacom_wac * wacom_wac, void * wcombo); 112extern int wacom_wac_irq(struct wacom_wac * wacom_wac, void * wcombo);
113extern void wacom_sys_irq(struct urb *urb);
114extern void wacom_report_abs(void *wcombo, unsigned int abs_type, int abs_data); 113extern void wacom_report_abs(void *wcombo, unsigned int abs_type, int abs_data);
115extern void wacom_report_rel(void *wcombo, unsigned int rel_type, int rel_data); 114extern void wacom_report_rel(void *wcombo, unsigned int rel_type, int rel_data);
116extern void wacom_report_key(void *wcombo, unsigned int key_type, int key_data); 115extern void wacom_report_key(void *wcombo, unsigned int key_type, int key_data);
diff --git a/drivers/usb/input/wacom_sys.c b/drivers/usb/input/wacom_sys.c
index 3498b893b53b..e7cc20ab8155 100644
--- a/drivers/usb/input/wacom_sys.c
+++ b/drivers/usb/input/wacom_sys.c
@@ -42,7 +42,7 @@ static struct input_dev * get_input_dev(struct wacom_combo *wcombo)
42 return wcombo->wacom->dev; 42 return wcombo->wacom->dev;
43} 43}
44 44
45void wacom_sys_irq(struct urb *urb) 45static void wacom_sys_irq(struct urb *urb)
46{ 46{
47 struct wacom *wacom = urb->context; 47 struct wacom *wacom = urb->context;
48 struct wacom_combo wcombo; 48 struct wacom_combo wcombo;
diff --git a/drivers/usb/input/yealink.c b/drivers/usb/input/yealink.c
index 905bf6398257..2268ca311ade 100644
--- a/drivers/usb/input/yealink.c
+++ b/drivers/usb/input/yealink.c
@@ -859,10 +859,8 @@ static int usb_probe(struct usb_interface *intf, const struct usb_device_id *id)
859 859
860 interface = intf->cur_altsetting; 860 interface = intf->cur_altsetting;
861 endpoint = &interface->endpoint[0].desc; 861 endpoint = &interface->endpoint[0].desc;
862 if (!(endpoint->bEndpointAddress & USB_DIR_IN)) 862 if (!usb_endpoint_is_int_in(endpoint))
863 return -EIO; 863 return -ENODEV;
864 if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) != USB_ENDPOINT_XFER_INT)
865 return -EIO;
866 864
867 yld = kzalloc(sizeof(struct yealink_dev), GFP_KERNEL); 865 yld = kzalloc(sizeof(struct yealink_dev), GFP_KERNEL);
868 if (!yld) 866 if (!yld)
diff --git a/drivers/usb/misc/Makefile b/drivers/usb/misc/Makefile
index 11dc59540cda..2cba07d31971 100644
--- a/drivers/usb/misc/Makefile
+++ b/drivers/usb/misc/Makefile
@@ -4,6 +4,7 @@
4# 4#
5 5
6obj-$(CONFIG_USB_ADUTUX) += adutux.o 6obj-$(CONFIG_USB_ADUTUX) += adutux.o
7obj-$(CONFIG_USB_APPLEDISPLAY) += appledisplay.o
7obj-$(CONFIG_USB_AUERSWALD) += auerswald.o 8obj-$(CONFIG_USB_AUERSWALD) += auerswald.o
8obj-$(CONFIG_USB_CYPRESS_CY7C63)+= cypress_cy7c63.o 9obj-$(CONFIG_USB_CYPRESS_CY7C63)+= cypress_cy7c63.o
9obj-$(CONFIG_USB_CYTHERM) += cytherm.o 10obj-$(CONFIG_USB_CYTHERM) += cytherm.o
diff --git a/drivers/usb/misc/appledisplay.c b/drivers/usb/misc/appledisplay.c
index 6b23a1def9fe..ba30ca6a14aa 100644
--- a/drivers/usb/misc/appledisplay.c
+++ b/drivers/usb/misc/appledisplay.c
@@ -216,10 +216,7 @@ static int appledisplay_probe(struct usb_interface *iface,
216 iface_desc = iface->cur_altsetting; 216 iface_desc = iface->cur_altsetting;
217 for (i = 0; i < iface_desc->desc.bNumEndpoints; i++) { 217 for (i = 0; i < iface_desc->desc.bNumEndpoints; i++) {
218 endpoint = &iface_desc->endpoint[i].desc; 218 endpoint = &iface_desc->endpoint[i].desc;
219 if (!int_in_endpointAddr && 219 if (!int_in_endpointAddr && usb_endpoint_is_int_in(endpoint)) {
220 (endpoint->bEndpointAddress & USB_DIR_IN) &&
221 ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
222 USB_ENDPOINT_XFER_INT)) {
223 /* we found an interrupt in endpoint */ 220 /* we found an interrupt in endpoint */
224 int_in_endpointAddr = endpoint->bEndpointAddress; 221 int_in_endpointAddr = endpoint->bEndpointAddress;
225 break; 222 break;
diff --git a/drivers/usb/misc/auerswald.c b/drivers/usb/misc/auerswald.c
index e4971d6aaafb..c703f73e1655 100644
--- a/drivers/usb/misc/auerswald.c
+++ b/drivers/usb/misc/auerswald.c
@@ -704,9 +704,7 @@ static void auerbuf_free (pauerbuf_t bp)
704{ 704{
705 kfree(bp->bufp); 705 kfree(bp->bufp);
706 kfree(bp->dr); 706 kfree(bp->dr);
707 if (bp->urbp) { 707 usb_free_urb(bp->urbp);
708 usb_free_urb(bp->urbp);
709 }
710 kfree(bp); 708 kfree(bp);
711} 709}
712 710
@@ -1155,8 +1153,7 @@ static void auerswald_int_release (pauerswald_t cp)
1155 dbg ("auerswald_int_release"); 1153 dbg ("auerswald_int_release");
1156 1154
1157 /* stop the int endpoint */ 1155 /* stop the int endpoint */
1158 if (cp->inturbp) 1156 usb_kill_urb (cp->inturbp);
1159 usb_kill_urb (cp->inturbp);
1160 1157
1161 /* deallocate memory */ 1158 /* deallocate memory */
1162 auerswald_int_free (cp); 1159 auerswald_int_free (cp);
diff --git a/drivers/usb/misc/emi26.c b/drivers/usb/misc/emi26.c
index 1fd9cb85f4ca..5c0a26cbd128 100644
--- a/drivers/usb/misc/emi26.c
+++ b/drivers/usb/misc/emi26.c
@@ -53,13 +53,12 @@ static void __exit emi26_exit (void);
53static int emi26_writememory (struct usb_device *dev, int address, unsigned char *data, int length, __u8 request) 53static int emi26_writememory (struct usb_device *dev, int address, unsigned char *data, int length, __u8 request)
54{ 54{
55 int result; 55 int result;
56 unsigned char *buffer = kmalloc (length, GFP_KERNEL); 56 unsigned char *buffer = kmemdup(data, length, GFP_KERNEL);
57 57
58 if (!buffer) { 58 if (!buffer) {
59 err("emi26: kmalloc(%d) failed.", length); 59 err("emi26: kmalloc(%d) failed.", length);
60 return -ENOMEM; 60 return -ENOMEM;
61 } 61 }
62 memcpy (buffer, data, length);
63 /* Note: usb_control_msg returns negative value on error or length of the 62 /* Note: usb_control_msg returns negative value on error or length of the
64 * data that was written! */ 63 * data that was written! */
65 result = usb_control_msg (dev, usb_sndctrlpipe(dev, 0), request, 0x40, address, 0, buffer, length, 300); 64 result = usb_control_msg (dev, usb_sndctrlpipe(dev, 0), request, 0x40, address, 0, buffer, length, 300);
diff --git a/drivers/usb/misc/emi62.c b/drivers/usb/misc/emi62.c
index fe351371f274..23153eac0dfa 100644
--- a/drivers/usb/misc/emi62.c
+++ b/drivers/usb/misc/emi62.c
@@ -61,13 +61,12 @@ static void __exit emi62_exit (void);
61static int emi62_writememory (struct usb_device *dev, int address, unsigned char *data, int length, __u8 request) 61static int emi62_writememory (struct usb_device *dev, int address, unsigned char *data, int length, __u8 request)
62{ 62{
63 int result; 63 int result;
64 unsigned char *buffer = kmalloc (length, GFP_KERNEL); 64 unsigned char *buffer = kmemdup(data, length, GFP_KERNEL);
65 65
66 if (!buffer) { 66 if (!buffer) {
67 err("emi62: kmalloc(%d) failed.", length); 67 err("emi62: kmalloc(%d) failed.", length);
68 return -ENOMEM; 68 return -ENOMEM;
69 } 69 }
70 memcpy (buffer, data, length);
71 /* Note: usb_control_msg returns negative value on error or length of the 70 /* Note: usb_control_msg returns negative value on error or length of the
72 * data that was written! */ 71 * data that was written! */
73 result = usb_control_msg (dev, usb_sndctrlpipe(dev, 0), request, 0x40, address, 0, buffer, length, 300); 72 result = usb_control_msg (dev, usb_sndctrlpipe(dev, 0), request, 0x40, address, 0, buffer, length, 300);
diff --git a/drivers/usb/misc/ftdi-elan.c b/drivers/usb/misc/ftdi-elan.c
index e4e2cf2ba915..18b1925032a8 100644
--- a/drivers/usb/misc/ftdi-elan.c
+++ b/drivers/usb/misc/ftdi-elan.c
@@ -272,7 +272,7 @@ void ftdi_elan_gone_away(struct platform_device *pdev)
272 272
273 273
274EXPORT_SYMBOL_GPL(ftdi_elan_gone_away); 274EXPORT_SYMBOL_GPL(ftdi_elan_gone_away);
275void ftdi_release_platform_dev(struct device *dev) 275static void ftdi_release_platform_dev(struct device *dev)
276{ 276{
277 dev->parent = NULL; 277 dev->parent = NULL;
278} 278}
@@ -1399,14 +1399,6 @@ static int ftdi_elan_read_reg(struct usb_ftdi *ftdi, u32 *data)
1399 } 1399 }
1400} 1400}
1401 1401
1402int usb_ftdi_elan_read_reg(struct platform_device *pdev, u32 *data)
1403{
1404 struct usb_ftdi *ftdi = platform_device_to_usb_ftdi(pdev);
1405 return ftdi_elan_read_reg(ftdi, data);
1406}
1407
1408
1409EXPORT_SYMBOL_GPL(usb_ftdi_elan_read_reg);
1410static int ftdi_elan_read_config(struct usb_ftdi *ftdi, int config_offset, 1402static int ftdi_elan_read_config(struct usb_ftdi *ftdi, int config_offset,
1411 u8 width, u32 *data) 1403 u8 width, u32 *data)
1412{ 1404{
@@ -2606,10 +2598,7 @@ static int ftdi_elan_probe(struct usb_interface *interface,
2606 for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) { 2598 for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
2607 endpoint = &iface_desc->endpoint[i].desc; 2599 endpoint = &iface_desc->endpoint[i].desc;
2608 if (!ftdi->bulk_in_endpointAddr && 2600 if (!ftdi->bulk_in_endpointAddr &&
2609 ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) 2601 usb_endpoint_is_bulk_in(endpoint)) {
2610 == USB_DIR_IN) && ((endpoint->bmAttributes &
2611 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
2612 {
2613 buffer_size = le16_to_cpu(endpoint->wMaxPacketSize); 2602 buffer_size = le16_to_cpu(endpoint->wMaxPacketSize);
2614 ftdi->bulk_in_size = buffer_size; 2603 ftdi->bulk_in_size = buffer_size;
2615 ftdi->bulk_in_endpointAddr = endpoint->bEndpointAddress; 2604 ftdi->bulk_in_endpointAddr = endpoint->bEndpointAddress;
@@ -2622,10 +2611,7 @@ static int ftdi_elan_probe(struct usb_interface *interface,
2622 } 2611 }
2623 } 2612 }
2624 if (!ftdi->bulk_out_endpointAddr && 2613 if (!ftdi->bulk_out_endpointAddr &&
2625 ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) 2614 usb_endpoint_is_bulk_out(endpoint)) {
2626 == USB_DIR_OUT) && ((endpoint->bmAttributes &
2627 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
2628 {
2629 ftdi->bulk_out_endpointAddr = 2615 ftdi->bulk_out_endpointAddr =
2630 endpoint->bEndpointAddress; 2616 endpoint->bEndpointAddress;
2631 } 2617 }
diff --git a/drivers/usb/misc/idmouse.c b/drivers/usb/misc/idmouse.c
index 8e6e195a22ba..c9418535bef8 100644
--- a/drivers/usb/misc/idmouse.c
+++ b/drivers/usb/misc/idmouse.c
@@ -125,12 +125,12 @@ static DEFINE_MUTEX(disconnect_mutex);
125 125
126static int idmouse_create_image(struct usb_idmouse *dev) 126static int idmouse_create_image(struct usb_idmouse *dev)
127{ 127{
128 int bytes_read = 0; 128 int bytes_read;
129 int bulk_read = 0; 129 int bulk_read;
130 int result = 0; 130 int result;
131 131
132 memcpy(dev->bulk_in_buffer, HEADER, sizeof(HEADER)-1); 132 memcpy(dev->bulk_in_buffer, HEADER, sizeof(HEADER)-1);
133 bytes_read += sizeof(HEADER)-1; 133 bytes_read = sizeof(HEADER)-1;
134 134
135 /* reset the device and set a fast blink rate */ 135 /* reset the device and set a fast blink rate */
136 result = ftip_command(dev, FTIP_RELEASE, 0, 0); 136 result = ftip_command(dev, FTIP_RELEASE, 0, 0);
@@ -208,9 +208,9 @@ static inline void idmouse_delete(struct usb_idmouse *dev)
208 208
209static int idmouse_open(struct inode *inode, struct file *file) 209static int idmouse_open(struct inode *inode, struct file *file)
210{ 210{
211 struct usb_idmouse *dev = NULL; 211 struct usb_idmouse *dev;
212 struct usb_interface *interface; 212 struct usb_interface *interface;
213 int result = 0; 213 int result;
214 214
215 /* prevent disconnects */ 215 /* prevent disconnects */
216 mutex_lock(&disconnect_mutex); 216 mutex_lock(&disconnect_mutex);
@@ -305,7 +305,7 @@ static ssize_t idmouse_read(struct file *file, char __user *buffer, size_t count
305 loff_t * ppos) 305 loff_t * ppos)
306{ 306{
307 struct usb_idmouse *dev; 307 struct usb_idmouse *dev;
308 int result = 0; 308 int result;
309 309
310 dev = (struct usb_idmouse *) file->private_data; 310 dev = (struct usb_idmouse *) file->private_data;
311 311
@@ -329,7 +329,7 @@ static int idmouse_probe(struct usb_interface *interface,
329 const struct usb_device_id *id) 329 const struct usb_device_id *id)
330{ 330{
331 struct usb_device *udev = interface_to_usbdev(interface); 331 struct usb_device *udev = interface_to_usbdev(interface);
332 struct usb_idmouse *dev = NULL; 332 struct usb_idmouse *dev;
333 struct usb_host_interface *iface_desc; 333 struct usb_host_interface *iface_desc;
334 struct usb_endpoint_descriptor *endpoint; 334 struct usb_endpoint_descriptor *endpoint;
335 int result; 335 int result;
@@ -350,11 +350,7 @@ static int idmouse_probe(struct usb_interface *interface,
350 350
351 /* set up the endpoint information - use only the first bulk-in endpoint */ 351 /* set up the endpoint information - use only the first bulk-in endpoint */
352 endpoint = &iface_desc->endpoint[0].desc; 352 endpoint = &iface_desc->endpoint[0].desc;
353 if (!dev->bulk_in_endpointAddr 353 if (!dev->bulk_in_endpointAddr && usb_endpoint_is_bulk_in(endpoint)) {
354 && (endpoint->bEndpointAddress & USB_DIR_IN)
355 && ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
356 USB_ENDPOINT_XFER_BULK)) {
357
358 /* we found a bulk in endpoint */ 354 /* we found a bulk in endpoint */
359 dev->orig_bi_size = le16_to_cpu(endpoint->wMaxPacketSize); 355 dev->orig_bi_size = le16_to_cpu(endpoint->wMaxPacketSize);
360 dev->bulk_in_size = 0x200; /* works _much_ faster */ 356 dev->bulk_in_size = 0x200; /* works _much_ faster */
diff --git a/drivers/usb/misc/legousbtower.c b/drivers/usb/misc/legousbtower.c
index 27089497e717..5dce797bddb7 100644
--- a/drivers/usb/misc/legousbtower.c
+++ b/drivers/usb/misc/legousbtower.c
@@ -317,12 +317,8 @@ static inline void tower_delete (struct lego_usb_tower *dev)
317 tower_abort_transfers (dev); 317 tower_abort_transfers (dev);
318 318
319 /* free data structures */ 319 /* free data structures */
320 if (dev->interrupt_in_urb != NULL) { 320 usb_free_urb(dev->interrupt_in_urb);
321 usb_free_urb (dev->interrupt_in_urb); 321 usb_free_urb(dev->interrupt_out_urb);
322 }
323 if (dev->interrupt_out_urb != NULL) {
324 usb_free_urb (dev->interrupt_out_urb);
325 }
326 kfree (dev->read_buffer); 322 kfree (dev->read_buffer);
327 kfree (dev->interrupt_in_buffer); 323 kfree (dev->interrupt_in_buffer);
328 kfree (dev->interrupt_out_buffer); 324 kfree (dev->interrupt_out_buffer);
@@ -502,15 +498,11 @@ static void tower_abort_transfers (struct lego_usb_tower *dev)
502 if (dev->interrupt_in_running) { 498 if (dev->interrupt_in_running) {
503 dev->interrupt_in_running = 0; 499 dev->interrupt_in_running = 0;
504 mb(); 500 mb();
505 if (dev->interrupt_in_urb != NULL && dev->udev) { 501 if (dev->udev)
506 usb_kill_urb (dev->interrupt_in_urb); 502 usb_kill_urb (dev->interrupt_in_urb);
507 }
508 }
509 if (dev->interrupt_out_busy) {
510 if (dev->interrupt_out_urb != NULL && dev->udev) {
511 usb_kill_urb (dev->interrupt_out_urb);
512 }
513 } 503 }
504 if (dev->interrupt_out_busy && dev->udev)
505 usb_kill_urb(dev->interrupt_out_urb);
514 506
515exit: 507exit:
516 dbg(2, "%s: leave", __FUNCTION__); 508 dbg(2, "%s: leave", __FUNCTION__);
@@ -898,14 +890,11 @@ static int tower_probe (struct usb_interface *interface, const struct usb_device
898 for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) { 890 for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
899 endpoint = &iface_desc->endpoint[i].desc; 891 endpoint = &iface_desc->endpoint[i].desc;
900 892
901 if (((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) && 893 if (usb_endpoint_xfer_int(endpoint)) {
902 ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT)) { 894 if (usb_endpoint_dir_in(endpoint))
903 dev->interrupt_in_endpoint = endpoint; 895 dev->interrupt_in_endpoint = endpoint;
904 } 896 else
905 897 dev->interrupt_out_endpoint = endpoint;
906 if (((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) &&
907 ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT)) {
908 dev->interrupt_out_endpoint = endpoint;
909 } 898 }
910 } 899 }
911 if(dev->interrupt_in_endpoint == NULL) { 900 if(dev->interrupt_in_endpoint == NULL) {
diff --git a/drivers/usb/misc/phidgetkit.c b/drivers/usb/misc/phidgetkit.c
index 33e716c6a79b..9659c79e187e 100644
--- a/drivers/usb/misc/phidgetkit.c
+++ b/drivers/usb/misc/phidgetkit.c
@@ -554,7 +554,7 @@ static int interfacekit_probe(struct usb_interface *intf, const struct usb_devic
554 return -ENODEV; 554 return -ENODEV;
555 555
556 endpoint = &interface->endpoint[0].desc; 556 endpoint = &interface->endpoint[0].desc;
557 if (!(endpoint->bEndpointAddress & 0x80)) 557 if (!usb_endpoint_dir_in(endpoint))
558 return -ENODEV; 558 return -ENODEV;
559 /* 559 /*
560 * bmAttributes 560 * bmAttributes
@@ -653,8 +653,7 @@ out2:
653 device_remove_file(kit->dev, &dev_output_attrs[i]); 653 device_remove_file(kit->dev, &dev_output_attrs[i]);
654out: 654out:
655 if (kit) { 655 if (kit) {
656 if (kit->irq) 656 usb_free_urb(kit->irq);
657 usb_free_urb(kit->irq);
658 if (kit->data) 657 if (kit->data)
659 usb_buffer_free(dev, URB_INT_SIZE, kit->data, kit->data_dma); 658 usb_buffer_free(dev, URB_INT_SIZE, kit->data, kit->data_dma);
660 if (kit->dev) 659 if (kit->dev)
diff --git a/drivers/usb/misc/phidgetmotorcontrol.c b/drivers/usb/misc/phidgetmotorcontrol.c
index 0385ffcc7419..2bb4fa572bb7 100644
--- a/drivers/usb/misc/phidgetmotorcontrol.c
+++ b/drivers/usb/misc/phidgetmotorcontrol.c
@@ -324,7 +324,7 @@ static int motorcontrol_probe(struct usb_interface *intf, const struct usb_devic
324 return -ENODEV; 324 return -ENODEV;
325 325
326 endpoint = &interface->endpoint[0].desc; 326 endpoint = &interface->endpoint[0].desc;
327 if (!(endpoint->bEndpointAddress & 0x80)) 327 if (!usb_endpoint_dir_in(endpoint))
328 return -ENODEV; 328 return -ENODEV;
329 329
330 /* 330 /*
@@ -393,8 +393,7 @@ out2:
393 device_remove_file(mc->dev, &dev_attrs[i]); 393 device_remove_file(mc->dev, &dev_attrs[i]);
394out: 394out:
395 if (mc) { 395 if (mc) {
396 if (mc->irq) 396 usb_free_urb(mc->irq);
397 usb_free_urb(mc->irq);
398 if (mc->data) 397 if (mc->data)
399 usb_buffer_free(dev, URB_INT_SIZE, mc->data, mc->data_dma); 398 usb_buffer_free(dev, URB_INT_SIZE, mc->data, mc->data_dma);
400 if (mc->dev) 399 if (mc->dev)
diff --git a/drivers/usb/misc/usb_u132.h b/drivers/usb/misc/usb_u132.h
index 551ba8906d62..dc2e5a31caec 100644
--- a/drivers/usb/misc/usb_u132.h
+++ b/drivers/usb/misc/usb_u132.h
@@ -52,7 +52,7 @@
52* the kernel to load the "u132-hcd" module. 52* the kernel to load the "u132-hcd" module.
53* 53*
54* The "ftdi-u132" module provides the interface to the inserted 54* The "ftdi-u132" module provides the interface to the inserted
55* PC card and the "u132-hcd" module uses the API to send and recieve 55* PC card and the "u132-hcd" module uses the API to send and receive
56* data. The API features call-backs, so that part of the "u132-hcd" 56* data. The API features call-backs, so that part of the "u132-hcd"
57* module code will run in the context of one of the kernel threads 57* module code will run in the context of one of the kernel threads
58* of the "ftdi-u132" module. 58* of the "ftdi-u132" module.
@@ -95,3 +95,7 @@ int usb_ftdi_elan_edset_setup(struct platform_device *pdev, u8 ed_number,
95 int halted, int skipped, int actual, int non_null)); 95 int halted, int skipped, int actual, int non_null));
96int usb_ftdi_elan_edset_flush(struct platform_device *pdev, u8 ed_number, 96int usb_ftdi_elan_edset_flush(struct platform_device *pdev, u8 ed_number,
97 void *endp); 97 void *endp);
98int usb_ftdi_elan_read_pcimem(struct platform_device *pdev, int mem_offset,
99 u8 width, u32 *data);
100int usb_ftdi_elan_write_pcimem(struct platform_device *pdev, int mem_offset,
101 u8 width, u32 data);
diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c
index 7c2cbdf81d20..194065dbb51f 100644
--- a/drivers/usb/misc/usbtest.c
+++ b/drivers/usb/misc/usbtest.c
@@ -138,7 +138,7 @@ get_endpoints (struct usbtest_dev *dev, struct usb_interface *intf)
138 default: 138 default:
139 continue; 139 continue;
140 } 140 }
141 if (e->desc.bEndpointAddress & USB_DIR_IN) { 141 if (usb_endpoint_dir_in(&e->desc)) {
142 if (!in) 142 if (!in)
143 in = e; 143 in = e;
144 } else { 144 } else {
@@ -147,7 +147,7 @@ get_endpoints (struct usbtest_dev *dev, struct usb_interface *intf)
147 } 147 }
148 continue; 148 continue;
149try_iso: 149try_iso:
150 if (e->desc.bEndpointAddress & USB_DIR_IN) { 150 if (usb_endpoint_dir_in(&e->desc)) {
151 if (!iso_in) 151 if (!iso_in)
152 iso_in = e; 152 iso_in = e;
153 } else { 153 } else {
diff --git a/drivers/usb/net/asix.c b/drivers/usb/net/asix.c
index 881841e600de..95e682e2c9d6 100644
--- a/drivers/usb/net/asix.c
+++ b/drivers/usb/net/asix.c
@@ -249,9 +249,9 @@ asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index,
249 249
250 req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; 250 req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
251 req->bRequest = cmd; 251 req->bRequest = cmd;
252 req->wValue = value; 252 req->wValue = cpu_to_le16(value);
253 req->wIndex = index; 253 req->wIndex = cpu_to_le16(index);
254 req->wLength = size; 254 req->wLength = cpu_to_le16(size);
255 255
256 usb_fill_control_urb(urb, dev->udev, 256 usb_fill_control_urb(urb, dev->udev,
257 usb_sndctrlpipe(dev->udev, 0), 257 usb_sndctrlpipe(dev->udev, 0),
diff --git a/drivers/usb/net/catc.c b/drivers/usb/net/catc.c
index f740325abac4..907b820a5faf 100644
--- a/drivers/usb/net/catc.c
+++ b/drivers/usb/net/catc.c
@@ -786,14 +786,10 @@ static int catc_probe(struct usb_interface *intf, const struct usb_device_id *id
786 if ((!catc->ctrl_urb) || (!catc->tx_urb) || 786 if ((!catc->ctrl_urb) || (!catc->tx_urb) ||
787 (!catc->rx_urb) || (!catc->irq_urb)) { 787 (!catc->rx_urb) || (!catc->irq_urb)) {
788 err("No free urbs available."); 788 err("No free urbs available.");
789 if (catc->ctrl_urb) 789 usb_free_urb(catc->ctrl_urb);
790 usb_free_urb(catc->ctrl_urb); 790 usb_free_urb(catc->tx_urb);
791 if (catc->tx_urb) 791 usb_free_urb(catc->rx_urb);
792 usb_free_urb(catc->tx_urb); 792 usb_free_urb(catc->irq_urb);
793 if (catc->rx_urb)
794 usb_free_urb(catc->rx_urb);
795 if (catc->irq_urb)
796 usb_free_urb(catc->irq_urb);
797 free_netdev(netdev); 793 free_netdev(netdev);
798 return -ENOMEM; 794 return -ENOMEM;
799 } 795 }
diff --git a/drivers/usb/net/cdc_ether.c b/drivers/usb/net/cdc_ether.c
index f6971b88349d..44a91547146e 100644
--- a/drivers/usb/net/cdc_ether.c
+++ b/drivers/usb/net/cdc_ether.c
@@ -200,8 +200,7 @@ next_desc:
200 200
201 dev->status = &info->control->cur_altsetting->endpoint [0]; 201 dev->status = &info->control->cur_altsetting->endpoint [0];
202 desc = &dev->status->desc; 202 desc = &dev->status->desc;
203 if (desc->bmAttributes != USB_ENDPOINT_XFER_INT 203 if (!usb_endpoint_is_int_in(desc)
204 || !(desc->bEndpointAddress & USB_DIR_IN)
205 || (le16_to_cpu(desc->wMaxPacketSize) 204 || (le16_to_cpu(desc->wMaxPacketSize)
206 < sizeof(struct usb_cdc_notification)) 205 < sizeof(struct usb_cdc_notification))
207 || !desc->bInterval) { 206 || !desc->bInterval) {
diff --git a/drivers/usb/net/net1080.c b/drivers/usb/net/net1080.c
index ce00de8f13a1..a77410562e12 100644
--- a/drivers/usb/net/net1080.c
+++ b/drivers/usb/net/net1080.c
@@ -237,12 +237,12 @@ static inline void nc_dump_usbctl(struct usbnet *dev, u16 usbctl)
237#define STATUS_CONN_OTHER (1 << 14) 237#define STATUS_CONN_OTHER (1 << 14)
238#define STATUS_SUSPEND_OTHER (1 << 13) 238#define STATUS_SUSPEND_OTHER (1 << 13)
239#define STATUS_MAILBOX_OTHER (1 << 12) 239#define STATUS_MAILBOX_OTHER (1 << 12)
240#define STATUS_PACKETS_OTHER(n) (((n) >> 8) && 0x03) 240#define STATUS_PACKETS_OTHER(n) (((n) >> 8) & 0x03)
241 241
242#define STATUS_CONN_THIS (1 << 6) 242#define STATUS_CONN_THIS (1 << 6)
243#define STATUS_SUSPEND_THIS (1 << 5) 243#define STATUS_SUSPEND_THIS (1 << 5)
244#define STATUS_MAILBOX_THIS (1 << 4) 244#define STATUS_MAILBOX_THIS (1 << 4)
245#define STATUS_PACKETS_THIS(n) (((n) >> 0) && 0x03) 245#define STATUS_PACKETS_THIS(n) (((n) >> 0) & 0x03)
246 246
247#define STATUS_UNSPEC_MASK 0x0c8c 247#define STATUS_UNSPEC_MASK 0x0c8c
248#define STATUS_NOISE_MASK ((u16)~(0x0303|STATUS_UNSPEC_MASK)) 248#define STATUS_NOISE_MASK ((u16)~(0x0303|STATUS_UNSPEC_MASK))
diff --git a/drivers/usb/net/pegasus.c b/drivers/usb/net/pegasus.c
index 78cf6f091285..b5690b3834e3 100644
--- a/drivers/usb/net/pegasus.c
+++ b/drivers/usb/net/pegasus.c
@@ -163,6 +163,7 @@ static int get_registers(pegasus_t * pegasus, __u16 indx, __u16 size,
163 163
164 /* using ATOMIC, we'd never wake up if we slept */ 164 /* using ATOMIC, we'd never wake up if we slept */
165 if ((ret = usb_submit_urb(pegasus->ctrl_urb, GFP_ATOMIC))) { 165 if ((ret = usb_submit_urb(pegasus->ctrl_urb, GFP_ATOMIC))) {
166 set_current_state(TASK_RUNNING);
166 if (ret == -ENODEV) 167 if (ret == -ENODEV)
167 netif_device_detach(pegasus->net); 168 netif_device_detach(pegasus->net);
168 if (netif_msg_drv(pegasus)) 169 if (netif_msg_drv(pegasus))
diff --git a/drivers/usb/net/usbnet.c b/drivers/usb/net/usbnet.c
index 79b5474fe234..327f97555679 100644
--- a/drivers/usb/net/usbnet.c
+++ b/drivers/usb/net/usbnet.c
@@ -116,7 +116,7 @@ int usbnet_get_endpoints(struct usbnet *dev, struct usb_interface *intf)
116 e = alt->endpoint + ep; 116 e = alt->endpoint + ep;
117 switch (e->desc.bmAttributes) { 117 switch (e->desc.bmAttributes) {
118 case USB_ENDPOINT_XFER_INT: 118 case USB_ENDPOINT_XFER_INT:
119 if (!(e->desc.bEndpointAddress & USB_DIR_IN)) 119 if (!usb_endpoint_dir_in(&e->desc))
120 continue; 120 continue;
121 intr = 1; 121 intr = 1;
122 /* FALLTHROUGH */ 122 /* FALLTHROUGH */
@@ -125,7 +125,7 @@ int usbnet_get_endpoints(struct usbnet *dev, struct usb_interface *intf)
125 default: 125 default:
126 continue; 126 continue;
127 } 127 }
128 if (e->desc.bEndpointAddress & USB_DIR_IN) { 128 if (usb_endpoint_dir_in(&e->desc)) {
129 if (!intr && !in) 129 if (!intr && !in)
130 in = e; 130 in = e;
131 else if (intr && !status) 131 else if (intr && !status)
diff --git a/drivers/usb/serial/Kconfig b/drivers/usb/serial/Kconfig
index 2a8dd4cc943d..2f4d303ee36f 100644
--- a/drivers/usb/serial/Kconfig
+++ b/drivers/usb/serial/Kconfig
@@ -554,6 +554,17 @@ config USB_SERIAL_OMNINET
554 To compile this driver as a module, choose M here: the 554 To compile this driver as a module, choose M here: the
555 module will be called omninet. 555 module will be called omninet.
556 556
557config USB_SERIAL_DEBUG
558 tristate "USB Debugging Device"
559 depends on USB_SERIAL
560 help
561 Say Y here if you have a USB debugging device used to recieve
562 debugging data from another machine. The most common of these
563 devices is the NetChip TurboCONNECT device.
564
565 To compile this driver as a module, choose M here: the
566 module will be called usb-debug.
567
557config USB_EZUSB 568config USB_EZUSB
558 bool 569 bool
559 depends on USB_SERIAL_KEYSPAN_PDA || USB_SERIAL_XIRCOM || USB_SERIAL_KEYSPAN || USB_SERIAL_WHITEHEAT 570 depends on USB_SERIAL_KEYSPAN_PDA || USB_SERIAL_XIRCOM || USB_SERIAL_KEYSPAN || USB_SERIAL_WHITEHEAT
diff --git a/drivers/usb/serial/Makefile b/drivers/usb/serial/Makefile
index a5047dc599bb..61166ad450e6 100644
--- a/drivers/usb/serial/Makefile
+++ b/drivers/usb/serial/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_USB_SERIAL_BELKIN) += belkin_sa.o
18obj-$(CONFIG_USB_SERIAL_CP2101) += cp2101.o 18obj-$(CONFIG_USB_SERIAL_CP2101) += cp2101.o
19obj-$(CONFIG_USB_SERIAL_CYBERJACK) += cyberjack.o 19obj-$(CONFIG_USB_SERIAL_CYBERJACK) += cyberjack.o
20obj-$(CONFIG_USB_SERIAL_CYPRESS_M8) += cypress_m8.o 20obj-$(CONFIG_USB_SERIAL_CYPRESS_M8) += cypress_m8.o
21obj-$(CONFIG_USB_SERIAL_DEBUG) += usb_debug.o
21obj-$(CONFIG_USB_SERIAL_DIGI_ACCELEPORT) += digi_acceleport.o 22obj-$(CONFIG_USB_SERIAL_DIGI_ACCELEPORT) += digi_acceleport.o
22obj-$(CONFIG_USB_SERIAL_EDGEPORT) += io_edgeport.o 23obj-$(CONFIG_USB_SERIAL_EDGEPORT) += io_edgeport.o
23obj-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += io_ti.o 24obj-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += io_ti.o
diff --git a/drivers/usb/serial/aircable.c b/drivers/usb/serial/aircable.c
index 2a4ac9bd6a3a..86bcf63b6ba5 100644
--- a/drivers/usb/serial/aircable.c
+++ b/drivers/usb/serial/aircable.c
@@ -272,8 +272,11 @@ static void aircable_read(struct work_struct *work)
272 */ 272 */
273 tty = port->tty; 273 tty = port->tty;
274 274
275 if (!tty) 275 if (!tty) {
276 schedule_work(&priv->rx_work); 276 schedule_work(&priv->rx_work);
277 err("%s - No tty available", __FUNCTION__);
278 return ;
279 }
277 280
278 count = min(64, serial_buf_data_avail(priv->rx_buf)); 281 count = min(64, serial_buf_data_avail(priv->rx_buf));
279 282
@@ -307,9 +310,7 @@ static int aircable_probe(struct usb_serial *serial,
307 310
308 for (i = 0; i < iface_desc->desc.bNumEndpoints; i++) { 311 for (i = 0; i < iface_desc->desc.bNumEndpoints; i++) {
309 endpoint = &iface_desc->endpoint[i].desc; 312 endpoint = &iface_desc->endpoint[i].desc;
310 if (((endpoint->bEndpointAddress & 0x80) == 0x00) && 313 if (usb_endpoint_is_bulk_out(endpoint)) {
311 ((endpoint->bmAttributes & 3) == 0x02)) {
312 /* we found our bulk out endpoint */
313 dbg("found bulk out on endpoint %d", i); 314 dbg("found bulk out on endpoint %d", i);
314 ++num_bulk_out; 315 ++num_bulk_out;
315 } 316 }
diff --git a/drivers/usb/serial/airprime.c b/drivers/usb/serial/airprime.c
index 7f5d546da39a..96c73726d74a 100644
--- a/drivers/usb/serial/airprime.c
+++ b/drivers/usb/serial/airprime.c
@@ -19,6 +19,7 @@
19static struct usb_device_id id_table [] = { 19static struct usb_device_id id_table [] = {
20 { USB_DEVICE(0x0c88, 0x17da) }, /* Kyocera Wireless KPC650/Passport */ 20 { USB_DEVICE(0x0c88, 0x17da) }, /* Kyocera Wireless KPC650/Passport */
21 { USB_DEVICE(0x1410, 0x1110) }, /* Novatel Wireless Merlin CDMA */ 21 { USB_DEVICE(0x1410, 0x1110) }, /* Novatel Wireless Merlin CDMA */
22 { USB_DEVICE(0x1410, 0x1430) }, /* Novatel Merlin XU870 HSDPA/3G */
22 { USB_DEVICE(0x1410, 0x1100) }, /* ExpressCard34 Qualcomm 3G CDMA */ 23 { USB_DEVICE(0x1410, 0x1100) }, /* ExpressCard34 Qualcomm 3G CDMA */
23 { }, 24 { },
24}; 25};
diff --git a/drivers/usb/serial/ark3116.c b/drivers/usb/serial/ark3116.c
index ca52f12f0e24..863966c1c5ac 100644
--- a/drivers/usb/serial/ark3116.c
+++ b/drivers/usb/serial/ark3116.c
@@ -85,10 +85,9 @@ static int ark3116_attach(struct usb_serial *serial)
85 int i; 85 int i;
86 86
87 for (i = 0; i < serial->num_ports; ++i) { 87 for (i = 0; i < serial->num_ports; ++i) {
88 priv = kmalloc(sizeof (struct ark3116_private), GFP_KERNEL); 88 priv = kzalloc(sizeof(struct ark3116_private), GFP_KERNEL);
89 if (!priv) 89 if (!priv)
90 goto cleanup; 90 goto cleanup;
91 memset(priv, 0x00, sizeof (struct ark3116_private));
92 spin_lock_init(&priv->lock); 91 spin_lock_init(&priv->lock);
93 92
94 usb_set_serial_port_data(serial->port[i], priv); 93 usb_set_serial_port_data(serial->port[i], priv);
diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c
index 3a9073dbfe6a..7167728d764c 100644
--- a/drivers/usb/serial/console.c
+++ b/drivers/usb/serial/console.c
@@ -166,19 +166,17 @@ static int usb_console_setup(struct console *co, char *options)
166 if (serial->type->set_termios) { 166 if (serial->type->set_termios) {
167 /* build up a fake tty structure so that the open call has something 167 /* build up a fake tty structure so that the open call has something
168 * to look at to get the cflag value */ 168 * to look at to get the cflag value */
169 tty = kmalloc (sizeof (*tty), GFP_KERNEL); 169 tty = kzalloc(sizeof(*tty), GFP_KERNEL);
170 if (!tty) { 170 if (!tty) {
171 err ("no more memory"); 171 err ("no more memory");
172 return -ENOMEM; 172 return -ENOMEM;
173 } 173 }
174 termios = kmalloc (sizeof (*termios), GFP_KERNEL); 174 termios = kzalloc(sizeof(*termios), GFP_KERNEL);
175 if (!termios) { 175 if (!termios) {
176 err ("no more memory"); 176 err ("no more memory");
177 kfree (tty); 177 kfree (tty);
178 return -ENOMEM; 178 return -ENOMEM;
179 } 179 }
180 memset (tty, 0x00, sizeof(*tty));
181 memset (termios, 0x00, sizeof(*termios));
182 termios->c_cflag = cflag; 180 termios->c_cflag = cflag;
183 tty->termios = termios; 181 tty->termios = termios;
184 port->tty = tty; 182 port->tty = tty;
diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c
index f2e89a083659..093f303b3189 100644
--- a/drivers/usb/serial/cypress_m8.c
+++ b/drivers/usb/serial/cypress_m8.c
@@ -1684,15 +1684,14 @@ static int __init cypress_init(void)
1684 1684
1685 info(DRIVER_DESC " " DRIVER_VERSION); 1685 info(DRIVER_DESC " " DRIVER_VERSION);
1686 return 0; 1686 return 0;
1687
1687failed_usb_register: 1688failed_usb_register:
1688 usb_deregister(&cypress_driver);
1689failed_ca42v2_register:
1690 usb_serial_deregister(&cypress_ca42v2_device); 1689 usb_serial_deregister(&cypress_ca42v2_device);
1691failed_hidcom_register: 1690failed_ca42v2_register:
1692 usb_serial_deregister(&cypress_hidcom_device); 1691 usb_serial_deregister(&cypress_hidcom_device);
1693failed_em_register: 1692failed_hidcom_register:
1694 usb_serial_deregister(&cypress_earthmate_device); 1693 usb_serial_deregister(&cypress_earthmate_device);
1695 1694failed_em_register:
1696 return retval; 1695 return retval;
1697} 1696}
1698 1697
diff --git a/drivers/usb/serial/digi_acceleport.c b/drivers/usb/serial/digi_acceleport.c
index fd159b040bfb..83d0e21145b0 100644
--- a/drivers/usb/serial/digi_acceleport.c
+++ b/drivers/usb/serial/digi_acceleport.c
@@ -157,7 +157,7 @@
157* to TASK_RUNNING will be lost and write_chan's subsequent call to 157* to TASK_RUNNING will be lost and write_chan's subsequent call to
158* schedule() will never return (unless it catches a signal). 158* schedule() will never return (unless it catches a signal).
159* This race condition occurs because write_bulk_callback() (and thus 159* This race condition occurs because write_bulk_callback() (and thus
160* the wakeup) are called asynchonously from an interrupt, rather than 160* the wakeup) are called asynchronously from an interrupt, rather than
161* from the scheduler. We can avoid the race by calling the wakeup 161* from the scheduler. We can avoid the race by calling the wakeup
162* from the scheduler queue and that's our fix: Now, at the end of 162* from the scheduler queue and that's our fix: Now, at the end of
163* write_bulk_callback() we queue up a wakeup call on the scheduler 163* write_bulk_callback() we queue up a wakeup call on the scheduler
diff --git a/drivers/usb/serial/ezusb.c b/drivers/usb/serial/ezusb.c
index 5169c2d154ab..97ee718b1da2 100644
--- a/drivers/usb/serial/ezusb.c
+++ b/drivers/usb/serial/ezusb.c
@@ -31,12 +31,11 @@ int ezusb_writememory (struct usb_serial *serial, int address, unsigned char *da
31 return -ENODEV; 31 return -ENODEV;
32 } 32 }
33 33
34 transfer_buffer = kmalloc (length, GFP_KERNEL); 34 transfer_buffer = kmemdup(data, length, GFP_KERNEL);
35 if (!transfer_buffer) { 35 if (!transfer_buffer) {
36 dev_err(&serial->dev->dev, "%s - kmalloc(%d) failed.\n", __FUNCTION__, length); 36 dev_err(&serial->dev->dev, "%s - kmalloc(%d) failed.\n", __FUNCTION__, length);
37 return -ENOMEM; 37 return -ENOMEM;
38 } 38 }
39 memcpy (transfer_buffer, data, length);
40 result = usb_control_msg (serial->dev, usb_sndctrlpipe(serial->dev, 0), bRequest, 0x40, address, 0, transfer_buffer, length, 3000); 39 result = usb_control_msg (serial->dev, usb_sndctrlpipe(serial->dev, 0), bRequest, 0x40, address, 0, transfer_buffer, length, 3000);
41 kfree (transfer_buffer); 40 kfree (transfer_buffer);
42 return result; 41 return result;
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index 88ed5c1d236c..72e4d48f51e9 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -1390,8 +1390,7 @@ static void ftdi_close (struct usb_serial_port *port, struct file *filp)
1390 flush_scheduled_work(); 1390 flush_scheduled_work();
1391 1391
1392 /* shutdown our bulk read */ 1392 /* shutdown our bulk read */
1393 if (port->read_urb) 1393 usb_kill_urb(port->read_urb);
1394 usb_kill_urb(port->read_urb);
1395} /* ftdi_close */ 1394} /* ftdi_close */
1396 1395
1397 1396
diff --git a/drivers/usb/serial/garmin_gps.c b/drivers/usb/serial/garmin_gps.c
index 4543152a9966..6530d391ebed 100644
--- a/drivers/usb/serial/garmin_gps.c
+++ b/drivers/usb/serial/garmin_gps.c
@@ -1523,12 +1523,11 @@ static int garmin_attach (struct usb_serial *serial)
1523 1523
1524 dbg("%s", __FUNCTION__); 1524 dbg("%s", __FUNCTION__);
1525 1525
1526 garmin_data_p = kmalloc (sizeof(struct garmin_data), GFP_KERNEL); 1526 garmin_data_p = kzalloc(sizeof(struct garmin_data), GFP_KERNEL);
1527 if (garmin_data_p == NULL) { 1527 if (garmin_data_p == NULL) {
1528 dev_err(&port->dev, "%s - Out of memory\n", __FUNCTION__); 1528 dev_err(&port->dev, "%s - Out of memory\n", __FUNCTION__);
1529 return -ENOMEM; 1529 return -ENOMEM;
1530 } 1530 }
1531 memset (garmin_data_p, 0, sizeof(struct garmin_data));
1532 init_timer(&garmin_data_p->timer); 1531 init_timer(&garmin_data_p->timer);
1533 spin_lock_init(&garmin_data_p->lock); 1532 spin_lock_init(&garmin_data_p->lock);
1534 INIT_LIST_HEAD(&garmin_data_p->pktlist); 1533 INIT_LIST_HEAD(&garmin_data_p->pktlist);
diff --git a/drivers/usb/serial/io_edgeport.c b/drivers/usb/serial/io_edgeport.c
index 91bd3014ef1e..d06547a13f28 100644
--- a/drivers/usb/serial/io_edgeport.c
+++ b/drivers/usb/serial/io_edgeport.c
@@ -1038,9 +1038,7 @@ static void edge_close (struct usb_serial_port *port, struct file * filp)
1038 edge_port->open = FALSE; 1038 edge_port->open = FALSE;
1039 edge_port->openPending = FALSE; 1039 edge_port->openPending = FALSE;
1040 1040
1041 if (edge_port->write_urb) { 1041 usb_kill_urb(edge_port->write_urb);
1042 usb_kill_urb(edge_port->write_urb);
1043 }
1044 1042
1045 if (edge_port->write_urb) { 1043 if (edge_port->write_urb) {
1046 /* if this urb had a transfer buffer already (old transfer) free it */ 1044 /* if this urb had a transfer buffer already (old transfer) free it */
diff --git a/drivers/usb/serial/ipw.c b/drivers/usb/serial/ipw.c
index 2a4bb66691ad..d3b9a351cef8 100644
--- a/drivers/usb/serial/ipw.c
+++ b/drivers/usb/serial/ipw.c
@@ -206,10 +206,9 @@ static int ipw_open(struct usb_serial_port *port, struct file *filp)
206 206
207 dbg("%s", __FUNCTION__); 207 dbg("%s", __FUNCTION__);
208 208
209 buf_flow_init = kmalloc(16, GFP_KERNEL); 209 buf_flow_init = kmemdup(buf_flow_static, 16, GFP_KERNEL);
210 if (!buf_flow_init) 210 if (!buf_flow_init)
211 return -ENOMEM; 211 return -ENOMEM;
212 memcpy(buf_flow_init, buf_flow_static, 16);
213 212
214 if (port->tty) 213 if (port->tty)
215 port->tty->low_latency = 1; 214 port->tty->low_latency = 1;
diff --git a/drivers/usb/serial/keyspan.c b/drivers/usb/serial/keyspan.c
index 53be824eb1bf..7639652cec42 100644
--- a/drivers/usb/serial/keyspan.c
+++ b/drivers/usb/serial/keyspan.c
@@ -2306,22 +2306,16 @@ static void keyspan_shutdown (struct usb_serial *serial)
2306 } 2306 }
2307 2307
2308 /* Now free them */ 2308 /* Now free them */
2309 if (s_priv->instat_urb) 2309 usb_free_urb(s_priv->instat_urb);
2310 usb_free_urb(s_priv->instat_urb); 2310 usb_free_urb(s_priv->glocont_urb);
2311 if (s_priv->glocont_urb)
2312 usb_free_urb(s_priv->glocont_urb);
2313 for (i = 0; i < serial->num_ports; ++i) { 2311 for (i = 0; i < serial->num_ports; ++i) {
2314 port = serial->port[i]; 2312 port = serial->port[i];
2315 p_priv = usb_get_serial_port_data(port); 2313 p_priv = usb_get_serial_port_data(port);
2316 if (p_priv->inack_urb) 2314 usb_free_urb(p_priv->inack_urb);
2317 usb_free_urb(p_priv->inack_urb); 2315 usb_free_urb(p_priv->outcont_urb);
2318 if (p_priv->outcont_urb)
2319 usb_free_urb(p_priv->outcont_urb);
2320 for (j = 0; j < 2; j++) { 2316 for (j = 0; j < 2; j++) {
2321 if (p_priv->in_urbs[j]) 2317 usb_free_urb(p_priv->in_urbs[j]);
2322 usb_free_urb(p_priv->in_urbs[j]); 2318 usb_free_urb(p_priv->out_urbs[j]);
2323 if (p_priv->out_urbs[j])
2324 usb_free_urb(p_priv->out_urbs[j]);
2325 } 2319 }
2326 } 2320 }
2327 2321
diff --git a/drivers/usb/serial/kobil_sct.c b/drivers/usb/serial/kobil_sct.c
index ff03331e0bcf..237289920f03 100644
--- a/drivers/usb/serial/kobil_sct.c
+++ b/drivers/usb/serial/kobil_sct.c
@@ -185,13 +185,11 @@ static int kobil_startup (struct usb_serial *serial)
185 185
186 for (i = 0; i < altsetting->desc.bNumEndpoints; i++) { 186 for (i = 0; i < altsetting->desc.bNumEndpoints; i++) {
187 endpoint = &altsetting->endpoint[i]; 187 endpoint = &altsetting->endpoint[i];
188 if (((endpoint->desc.bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) && 188 if (usb_endpoint_is_int_out(&endpoint->desc)) {
189 ((endpoint->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT)) {
190 dbg("%s Found interrupt out endpoint. Address: %d", __FUNCTION__, endpoint->desc.bEndpointAddress); 189 dbg("%s Found interrupt out endpoint. Address: %d", __FUNCTION__, endpoint->desc.bEndpointAddress);
191 priv->write_int_endpoint_address = endpoint->desc.bEndpointAddress; 190 priv->write_int_endpoint_address = endpoint->desc.bEndpointAddress;
192 } 191 }
193 if (((endpoint->desc.bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) && 192 if (usb_endpoint_is_int_in(&endpoint->desc)) {
194 ((endpoint->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT)) {
195 dbg("%s Found interrupt in endpoint. Address: %d", __FUNCTION__, endpoint->desc.bEndpointAddress); 193 dbg("%s Found interrupt in endpoint. Address: %d", __FUNCTION__, endpoint->desc.bEndpointAddress);
196 priv->read_int_endpoint_address = endpoint->desc.bEndpointAddress; 194 priv->read_int_endpoint_address = endpoint->desc.bEndpointAddress;
197 } 195 }
@@ -355,8 +353,7 @@ static void kobil_close (struct usb_serial_port *port, struct file *filp)
355 usb_free_urb( port->write_urb ); 353 usb_free_urb( port->write_urb );
356 port->write_urb = NULL; 354 port->write_urb = NULL;
357 } 355 }
358 if (port->interrupt_in_urb) 356 usb_kill_urb(port->interrupt_in_urb);
359 usb_kill_urb(port->interrupt_in_urb);
360} 357}
361 358
362 359
diff --git a/drivers/usb/serial/mct_u232.c b/drivers/usb/serial/mct_u232.c
index b7582cc496dc..a906e500a02b 100644
--- a/drivers/usb/serial/mct_u232.c
+++ b/drivers/usb/serial/mct_u232.c
@@ -358,10 +358,8 @@ static int mct_u232_startup (struct usb_serial *serial)
358 /* Puh, that's dirty */ 358 /* Puh, that's dirty */
359 port = serial->port[0]; 359 port = serial->port[0];
360 rport = serial->port[1]; 360 rport = serial->port[1];
361 if (port->read_urb) { 361 /* No unlinking, it wasn't submitted yet. */
362 /* No unlinking, it wasn't submitted yet. */ 362 usb_free_urb(port->read_urb);
363 usb_free_urb(port->read_urb);
364 }
365 port->read_urb = rport->interrupt_in_urb; 363 port->read_urb = rport->interrupt_in_urb;
366 rport->interrupt_in_urb = NULL; 364 rport->interrupt_in_urb = NULL;
367 port->read_urb->context = port; 365 port->read_urb->context = port;
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index 5b71962d0351..02c89e10b2cf 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -2596,12 +2596,11 @@ static int mos7840_startup(struct usb_serial *serial)
2596 2596
2597 /* set up port private structures */ 2597 /* set up port private structures */
2598 for (i = 0; i < serial->num_ports; ++i) { 2598 for (i = 0; i < serial->num_ports; ++i) {
2599 mos7840_port = kmalloc(sizeof(struct moschip_port), GFP_KERNEL); 2599 mos7840_port = kzalloc(sizeof(struct moschip_port), GFP_KERNEL);
2600 if (mos7840_port == NULL) { 2600 if (mos7840_port == NULL) {
2601 err("%s - Out of memory", __FUNCTION__); 2601 err("%s - Out of memory", __FUNCTION__);
2602 return -ENOMEM; 2602 return -ENOMEM;
2603 } 2603 }
2604 memset(mos7840_port, 0, sizeof(struct moschip_port));
2605 2604
2606 /* Initialize all port interrupt end point to port 0 int endpoint * 2605 /* Initialize all port interrupt end point to port 0 int endpoint *
2607 * Our device has only one interrupt end point comman to all port */ 2606 * Our device has only one interrupt end point comman to all port */
diff --git a/drivers/usb/serial/navman.c b/drivers/usb/serial/navman.c
index 0610409a6568..054abee81652 100644
--- a/drivers/usb/serial/navman.c
+++ b/drivers/usb/serial/navman.c
@@ -95,8 +95,7 @@ static void navman_close(struct usb_serial_port *port, struct file *filp)
95{ 95{
96 dbg("%s - port %d", __FUNCTION__, port->number); 96 dbg("%s - port %d", __FUNCTION__, port->number);
97 97
98 if (port->interrupt_in_urb) 98 usb_kill_urb(port->interrupt_in_urb);
99 usb_kill_urb(port->interrupt_in_urb);
100} 99}
101 100
102static int navman_write(struct usb_serial_port *port, 101static int navman_write(struct usb_serial_port *port,
diff --git a/drivers/usb/serial/ti_usb_3410_5052.c b/drivers/usb/serial/ti_usb_3410_5052.c
index 07400c0c8a8c..ae98d8cbdbb8 100644
--- a/drivers/usb/serial/ti_usb_3410_5052.c
+++ b/drivers/usb/serial/ti_usb_3410_5052.c
@@ -228,6 +228,7 @@ static int product_5052_count;
228/* null entry */ 228/* null entry */
229static struct usb_device_id ti_id_table_3410[1+TI_EXTRA_VID_PID_COUNT+1] = { 229static struct usb_device_id ti_id_table_3410[1+TI_EXTRA_VID_PID_COUNT+1] = {
230 { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, 230 { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) },
231 { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) },
231}; 232};
232 233
233static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = { 234static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = {
@@ -239,6 +240,7 @@ static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = {
239 240
240static struct usb_device_id ti_id_table_combined[] = { 241static struct usb_device_id ti_id_table_combined[] = {
241 { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, 242 { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) },
243 { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) },
242 { USB_DEVICE(TI_VENDOR_ID, TI_5052_BOOT_PRODUCT_ID) }, 244 { USB_DEVICE(TI_VENDOR_ID, TI_5052_BOOT_PRODUCT_ID) },
243 { USB_DEVICE(TI_VENDOR_ID, TI_5152_BOOT_PRODUCT_ID) }, 245 { USB_DEVICE(TI_VENDOR_ID, TI_5152_BOOT_PRODUCT_ID) },
244 { USB_DEVICE(TI_VENDOR_ID, TI_5052_EEPROM_PRODUCT_ID) }, 246 { USB_DEVICE(TI_VENDOR_ID, TI_5052_EEPROM_PRODUCT_ID) },
@@ -459,13 +461,12 @@ static int ti_startup(struct usb_serial *serial)
459 461
460 /* set up port structures */ 462 /* set up port structures */
461 for (i = 0; i < serial->num_ports; ++i) { 463 for (i = 0; i < serial->num_ports; ++i) {
462 tport = kmalloc(sizeof(struct ti_port), GFP_KERNEL); 464 tport = kzalloc(sizeof(struct ti_port), GFP_KERNEL);
463 if (tport == NULL) { 465 if (tport == NULL) {
464 dev_err(&dev->dev, "%s - out of memory\n", __FUNCTION__); 466 dev_err(&dev->dev, "%s - out of memory\n", __FUNCTION__);
465 status = -ENOMEM; 467 status = -ENOMEM;
466 goto free_tports; 468 goto free_tports;
467 } 469 }
468 memset(tport, 0, sizeof(struct ti_port));
469 spin_lock_init(&tport->tp_lock); 470 spin_lock_init(&tport->tp_lock);
470 tport->tp_uart_base_addr = (i == 0 ? TI_UART1_BASE_ADDR : TI_UART2_BASE_ADDR); 471 tport->tp_uart_base_addr = (i == 0 ? TI_UART1_BASE_ADDR : TI_UART2_BASE_ADDR);
471 tport->tp_flags = low_latency ? ASYNC_LOW_LATENCY : 0; 472 tport->tp_flags = low_latency ? ASYNC_LOW_LATENCY : 0;
diff --git a/drivers/usb/serial/ti_usb_3410_5052.h b/drivers/usb/serial/ti_usb_3410_5052.h
index 02c1aeb9e1b8..b5541bf991ba 100644
--- a/drivers/usb/serial/ti_usb_3410_5052.h
+++ b/drivers/usb/serial/ti_usb_3410_5052.h
@@ -28,6 +28,7 @@
28/* Vendor and product ids */ 28/* Vendor and product ids */
29#define TI_VENDOR_ID 0x0451 29#define TI_VENDOR_ID 0x0451
30#define TI_3410_PRODUCT_ID 0x3410 30#define TI_3410_PRODUCT_ID 0x3410
31#define TI_3410_EZ430_ID 0xF430 /* TI ez430 development tool */
31#define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */ 32#define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */
32#define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */ 33#define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */
33#define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ 34#define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */
diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c
index 2cfba8488a93..3d5072f14b8d 100644
--- a/drivers/usb/serial/usb-serial.c
+++ b/drivers/usb/serial/usb-serial.c
@@ -953,32 +953,28 @@ probe_error:
953 port = serial->port[i]; 953 port = serial->port[i];
954 if (!port) 954 if (!port)
955 continue; 955 continue;
956 if (port->read_urb) 956 usb_free_urb(port->read_urb);
957 usb_free_urb (port->read_urb);
958 kfree(port->bulk_in_buffer); 957 kfree(port->bulk_in_buffer);
959 } 958 }
960 for (i = 0; i < num_bulk_out; ++i) { 959 for (i = 0; i < num_bulk_out; ++i) {
961 port = serial->port[i]; 960 port = serial->port[i];
962 if (!port) 961 if (!port)
963 continue; 962 continue;
964 if (port->write_urb) 963 usb_free_urb(port->write_urb);
965 usb_free_urb (port->write_urb);
966 kfree(port->bulk_out_buffer); 964 kfree(port->bulk_out_buffer);
967 } 965 }
968 for (i = 0; i < num_interrupt_in; ++i) { 966 for (i = 0; i < num_interrupt_in; ++i) {
969 port = serial->port[i]; 967 port = serial->port[i];
970 if (!port) 968 if (!port)
971 continue; 969 continue;
972 if (port->interrupt_in_urb) 970 usb_free_urb(port->interrupt_in_urb);
973 usb_free_urb (port->interrupt_in_urb);
974 kfree(port->interrupt_in_buffer); 971 kfree(port->interrupt_in_buffer);
975 } 972 }
976 for (i = 0; i < num_interrupt_out; ++i) { 973 for (i = 0; i < num_interrupt_out; ++i) {
977 port = serial->port[i]; 974 port = serial->port[i];
978 if (!port) 975 if (!port)
979 continue; 976 continue;
980 if (port->interrupt_out_urb) 977 usb_free_urb(port->interrupt_out_urb);
981 usb_free_urb (port->interrupt_out_urb);
982 kfree(port->interrupt_out_buffer); 978 kfree(port->interrupt_out_buffer);
983 } 979 }
984 980
diff --git a/drivers/usb/serial/usb_debug.c b/drivers/usb/serial/usb_debug.c
new file mode 100644
index 000000000000..257a5e436873
--- /dev/null
+++ b/drivers/usb/serial/usb_debug.c
@@ -0,0 +1,65 @@
1/*
2 * USB Debug cable driver
3 *
4 * Copyright (C) 2006 Greg Kroah-Hartman <greg@kroah.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/tty.h>
14#include <linux/module.h>
15#include <linux/usb.h>
16#include <linux/usb/serial.h>
17
18static struct usb_device_id id_table [] = {
19 { USB_DEVICE(0x0525, 0x127a) },
20 { },
21};
22MODULE_DEVICE_TABLE(usb, id_table);
23
24static struct usb_driver debug_driver = {
25 .name = "debug",
26 .probe = usb_serial_probe,
27 .disconnect = usb_serial_disconnect,
28 .id_table = id_table,
29 .no_dynamic_id = 1,
30};
31
32static struct usb_serial_driver debug_device = {
33 .driver = {
34 .owner = THIS_MODULE,
35 .name = "debug",
36 },
37 .id_table = id_table,
38 .num_interrupt_in = NUM_DONT_CARE,
39 .num_bulk_in = NUM_DONT_CARE,
40 .num_bulk_out = NUM_DONT_CARE,
41 .num_ports = 1,
42};
43
44static int __init debug_init(void)
45{
46 int retval;
47
48 retval = usb_serial_register(&debug_device);
49 if (retval)
50 return retval;
51 retval = usb_register(&debug_driver);
52 if (retval)
53 usb_serial_deregister(&debug_device);
54 return retval;
55}
56
57static void __exit debug_exit(void)
58{
59 usb_deregister(&debug_driver);
60 usb_serial_deregister(&debug_device);
61}
62
63module_init(debug_init);
64module_exit(debug_exit);
65MODULE_LICENSE("GPL");
diff --git a/drivers/usb/serial/visor.c b/drivers/usb/serial/visor.c
index befe2e11a041..eef5eaa5fa0b 100644
--- a/drivers/usb/serial/visor.c
+++ b/drivers/usb/serial/visor.c
@@ -348,8 +348,7 @@ static void visor_close (struct usb_serial_port *port, struct file * filp)
348 348
349 /* shutdown our urbs */ 349 /* shutdown our urbs */
350 usb_kill_urb(port->read_urb); 350 usb_kill_urb(port->read_urb);
351 if (port->interrupt_in_urb) 351 usb_kill_urb(port->interrupt_in_urb);
352 usb_kill_urb(port->interrupt_in_urb);
353 352
354 /* Try to send shutdown message, if the device is gone, this will just fail. */ 353 /* Try to send shutdown message, if the device is gone, this will just fail. */
355 transfer_buffer = kmalloc (0x12, GFP_KERNEL); 354 transfer_buffer = kmalloc (0x12, GFP_KERNEL);
diff --git a/drivers/usb/storage/onetouch.c b/drivers/usb/storage/onetouch.c
index 3baf448e300d..3a158d58441f 100644
--- a/drivers/usb/storage/onetouch.c
+++ b/drivers/usb/storage/onetouch.c
@@ -142,10 +142,7 @@ int onetouch_connect_input(struct us_data *ss)
142 return -ENODEV; 142 return -ENODEV;
143 143
144 endpoint = &interface->endpoint[2].desc; 144 endpoint = &interface->endpoint[2].desc;
145 if (!(endpoint->bEndpointAddress & USB_DIR_IN)) 145 if (!usb_endpoint_is_int_in(endpoint))
146 return -ENODEV;
147 if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
148 != USB_ENDPOINT_XFER_INT)
149 return -ENODEV; 146 return -ENODEV;
150 147
151 pipe = usb_rcvintpipe(udev, endpoint->bEndpointAddress); 148 pipe = usb_rcvintpipe(udev, endpoint->bEndpointAddress);
diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
index efb047f431e8..db8b26012c75 100644
--- a/drivers/usb/storage/unusual_devs.h
+++ b/drivers/usb/storage/unusual_devs.h
@@ -1318,6 +1318,16 @@ UNUSUAL_DEV( 0x1019, 0x0c55, 0x0000, 0x0110,
1318 US_SC_DEVICE, US_PR_DEVICE, usb_stor_ucr61s2b_init, 1318 US_SC_DEVICE, US_PR_DEVICE, usb_stor_ucr61s2b_init,
1319 0 ), 1319 0 ),
1320 1320
1321/* Reported by Jaco Kroon <jaco@kroon.co.za>
1322 * The usb-storage module found on the Digitech GNX4 (and supposedly other
1323 * devices) misbehaves and causes a bunch of invalid I/O errors.
1324 */
1325UNUSUAL_DEV( 0x1210, 0x0003, 0x0100, 0x0100,
1326 "Digitech HMG",
1327 "DigiTech Mass Storage",
1328 US_SC_DEVICE, US_PR_DEVICE, NULL,
1329 US_FL_IGNORE_RESIDUE ),
1330
1321/* Reported by Vilius Bilinkevicius <vilisas AT xxx DOT lt) */ 1331/* Reported by Vilius Bilinkevicius <vilisas AT xxx DOT lt) */
1322UNUSUAL_DEV( 0x132b, 0x000b, 0x0001, 0x0001, 1332UNUSUAL_DEV( 0x132b, 0x000b, 0x0001, 0x0001,
1323 "Minolta", 1333 "Minolta",
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index b8d6031b0975..b401084b3d22 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -740,18 +740,16 @@ static int get_pipes(struct us_data *us)
740 ep = &altsetting->endpoint[i].desc; 740 ep = &altsetting->endpoint[i].desc;
741 741
742 /* Is it a BULK endpoint? */ 742 /* Is it a BULK endpoint? */
743 if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) 743 if (usb_endpoint_xfer_bulk(ep)) {
744 == USB_ENDPOINT_XFER_BULK) {
745 /* BULK in or out? */ 744 /* BULK in or out? */
746 if (ep->bEndpointAddress & USB_DIR_IN) 745 if (usb_endpoint_dir_in(ep))
747 ep_in = ep; 746 ep_in = ep;
748 else 747 else
749 ep_out = ep; 748 ep_out = ep;
750 } 749 }
751 750
752 /* Is it an interrupt endpoint? */ 751 /* Is it an interrupt endpoint? */
753 else if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) 752 else if (usb_endpoint_xfer_int(ep)) {
754 == USB_ENDPOINT_XFER_INT) {
755 ep_int = ep; 753 ep_int = ep;
756 } 754 }
757 } 755 }
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index 93ffcdd95f50..e973a87fbb01 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -1296,14 +1296,14 @@ register_framebuffer(struct fb_info *fb_info)
1296 break; 1296 break;
1297 fb_info->node = i; 1297 fb_info->node = i;
1298 1298
1299 fb_info->class_device = class_device_create(fb_class, NULL, MKDEV(FB_MAJOR, i), 1299 fb_info->dev = device_create(fb_class, fb_info->device,
1300 fb_info->device, "fb%d", i); 1300 MKDEV(FB_MAJOR, i), "fb%d", i);
1301 if (IS_ERR(fb_info->class_device)) { 1301 if (IS_ERR(fb_info->dev)) {
1302 /* Not fatal */ 1302 /* Not fatal */
1303 printk(KERN_WARNING "Unable to create class_device for framebuffer %d; errno = %ld\n", i, PTR_ERR(fb_info->class_device)); 1303 printk(KERN_WARNING "Unable to create device for framebuffer %d; errno = %ld\n", i, PTR_ERR(fb_info->dev));
1304 fb_info->class_device = NULL; 1304 fb_info->dev = NULL;
1305 } else 1305 } else
1306 fb_init_class_device(fb_info); 1306 fb_init_device(fb_info);
1307 1307
1308 if (fb_info->pixmap.addr == NULL) { 1308 if (fb_info->pixmap.addr == NULL) {
1309 fb_info->pixmap.addr = kmalloc(FBPIXMAPSIZE, GFP_KERNEL); 1309 fb_info->pixmap.addr = kmalloc(FBPIXMAPSIZE, GFP_KERNEL);
@@ -1356,8 +1356,8 @@ unregister_framebuffer(struct fb_info *fb_info)
1356 fb_destroy_modelist(&fb_info->modelist); 1356 fb_destroy_modelist(&fb_info->modelist);
1357 registered_fb[i]=NULL; 1357 registered_fb[i]=NULL;
1358 num_registered_fb--; 1358 num_registered_fb--;
1359 fb_cleanup_class_device(fb_info); 1359 fb_cleanup_device(fb_info);
1360 class_device_destroy(fb_class, MKDEV(FB_MAJOR, i)); 1360 device_destroy(fb_class, MKDEV(FB_MAJOR, i));
1361 event.info = fb_info; 1361 event.info = fb_info;
1362 fb_notifier_call_chain(FB_EVENT_FB_UNREGISTERED, &event); 1362 fb_notifier_call_chain(FB_EVENT_FB_UNREGISTERED, &event);
1363 return 0; 1363 return 0;
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c
index d3a50417ed9a..323bdf6fc7d5 100644
--- a/drivers/video/fbsysfs.c
+++ b/drivers/video/fbsysfs.c
@@ -73,7 +73,7 @@ EXPORT_SYMBOL(framebuffer_alloc);
73 * 73 *
74 * @info: frame buffer info structure 74 * @info: frame buffer info structure
75 * 75 *
76 * Drop the reference count of the class_device embedded in the 76 * Drop the reference count of the device embedded in the
77 * framebuffer info structure. 77 * framebuffer info structure.
78 * 78 *
79 */ 79 */
@@ -120,10 +120,10 @@ static int mode_string(char *buf, unsigned int offset,
120 m, mode->xres, mode->yres, v, mode->refresh); 120 m, mode->xres, mode->yres, v, mode->refresh);
121} 121}
122 122
123static ssize_t store_mode(struct class_device *class_device, const char * buf, 123static ssize_t store_mode(struct device *device, struct device_attribute *attr,
124 size_t count) 124 const char *buf, size_t count)
125{ 125{
126 struct fb_info *fb_info = class_get_devdata(class_device); 126 struct fb_info *fb_info = dev_get_drvdata(device);
127 char mstr[100]; 127 char mstr[100];
128 struct fb_var_screeninfo var; 128 struct fb_var_screeninfo var;
129 struct fb_modelist *modelist; 129 struct fb_modelist *modelist;
@@ -151,9 +151,10 @@ static ssize_t store_mode(struct class_device *class_device, const char * buf,
151 return -EINVAL; 151 return -EINVAL;
152} 152}
153 153
154static ssize_t show_mode(struct class_device *class_device, char *buf) 154static ssize_t show_mode(struct device *device, struct device_attribute *attr,
155 char *buf)
155{ 156{
156 struct fb_info *fb_info = class_get_devdata(class_device); 157 struct fb_info *fb_info = dev_get_drvdata(device);
157 158
158 if (!fb_info->mode) 159 if (!fb_info->mode)
159 return 0; 160 return 0;
@@ -161,10 +162,11 @@ static ssize_t show_mode(struct class_device *class_device, char *buf)
161 return mode_string(buf, 0, fb_info->mode); 162 return mode_string(buf, 0, fb_info->mode);
162} 163}
163 164
164static ssize_t store_modes(struct class_device *class_device, const char * buf, 165static ssize_t store_modes(struct device *device,
165 size_t count) 166 struct device_attribute *attr,
167 const char *buf, size_t count)
166{ 168{
167 struct fb_info *fb_info = class_get_devdata(class_device); 169 struct fb_info *fb_info = dev_get_drvdata(device);
168 LIST_HEAD(old_list); 170 LIST_HEAD(old_list);
169 int i = count / sizeof(struct fb_videomode); 171 int i = count / sizeof(struct fb_videomode);
170 172
@@ -186,9 +188,10 @@ static ssize_t store_modes(struct class_device *class_device, const char * buf,
186 return 0; 188 return 0;
187} 189}
188 190
189static ssize_t show_modes(struct class_device *class_device, char *buf) 191static ssize_t show_modes(struct device *device, struct device_attribute *attr,
192 char *buf)
190{ 193{
191 struct fb_info *fb_info = class_get_devdata(class_device); 194 struct fb_info *fb_info = dev_get_drvdata(device);
192 unsigned int i; 195 unsigned int i;
193 struct list_head *pos; 196 struct list_head *pos;
194 struct fb_modelist *modelist; 197 struct fb_modelist *modelist;
@@ -203,10 +206,10 @@ static ssize_t show_modes(struct class_device *class_device, char *buf)
203 return i; 206 return i;
204} 207}
205 208
206static ssize_t store_bpp(struct class_device *class_device, const char * buf, 209static ssize_t store_bpp(struct device *device, struct device_attribute *attr,
207 size_t count) 210 const char *buf, size_t count)
208{ 211{
209 struct fb_info *fb_info = class_get_devdata(class_device); 212 struct fb_info *fb_info = dev_get_drvdata(device);
210 struct fb_var_screeninfo var; 213 struct fb_var_screeninfo var;
211 char ** last = NULL; 214 char ** last = NULL;
212 int err; 215 int err;
@@ -218,16 +221,18 @@ static ssize_t store_bpp(struct class_device *class_device, const char * buf,
218 return count; 221 return count;
219} 222}
220 223
221static ssize_t show_bpp(struct class_device *class_device, char *buf) 224static ssize_t show_bpp(struct device *device, struct device_attribute *attr,
225 char *buf)
222{ 226{
223 struct fb_info *fb_info = class_get_devdata(class_device); 227 struct fb_info *fb_info = dev_get_drvdata(device);
224 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.bits_per_pixel); 228 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.bits_per_pixel);
225} 229}
226 230
227static ssize_t store_rotate(struct class_device *class_device, const char *buf, 231static ssize_t store_rotate(struct device *device,
228 size_t count) 232 struct device_attribute *attr,
233 const char *buf, size_t count)
229{ 234{
230 struct fb_info *fb_info = class_get_devdata(class_device); 235 struct fb_info *fb_info = dev_get_drvdata(device);
231 struct fb_var_screeninfo var; 236 struct fb_var_screeninfo var;
232 char **last = NULL; 237 char **last = NULL;
233 int err; 238 int err;
@@ -242,17 +247,19 @@ static ssize_t store_rotate(struct class_device *class_device, const char *buf,
242} 247}
243 248
244 249
245static ssize_t show_rotate(struct class_device *class_device, char *buf) 250static ssize_t show_rotate(struct device *device,
251 struct device_attribute *attr, char *buf)
246{ 252{
247 struct fb_info *fb_info = class_get_devdata(class_device); 253 struct fb_info *fb_info = dev_get_drvdata(device);
248 254
249 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.rotate); 255 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->var.rotate);
250} 256}
251 257
252static ssize_t store_virtual(struct class_device *class_device, 258static ssize_t store_virtual(struct device *device,
253 const char * buf, size_t count) 259 struct device_attribute *attr,
260 const char *buf, size_t count)
254{ 261{
255 struct fb_info *fb_info = class_get_devdata(class_device); 262 struct fb_info *fb_info = dev_get_drvdata(device);
256 struct fb_var_screeninfo var; 263 struct fb_var_screeninfo var;
257 char *last = NULL; 264 char *last = NULL;
258 int err; 265 int err;
@@ -269,23 +276,26 @@ static ssize_t store_virtual(struct class_device *class_device,
269 return count; 276 return count;
270} 277}
271 278
272static ssize_t show_virtual(struct class_device *class_device, char *buf) 279static ssize_t show_virtual(struct device *device,
280 struct device_attribute *attr, char *buf)
273{ 281{
274 struct fb_info *fb_info = class_get_devdata(class_device); 282 struct fb_info *fb_info = dev_get_drvdata(device);
275 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xres_virtual, 283 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xres_virtual,
276 fb_info->var.yres_virtual); 284 fb_info->var.yres_virtual);
277} 285}
278 286
279static ssize_t show_stride(struct class_device *class_device, char *buf) 287static ssize_t show_stride(struct device *device,
288 struct device_attribute *attr, char *buf)
280{ 289{
281 struct fb_info *fb_info = class_get_devdata(class_device); 290 struct fb_info *fb_info = dev_get_drvdata(device);
282 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->fix.line_length); 291 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->fix.line_length);
283} 292}
284 293
285static ssize_t store_blank(struct class_device *class_device, const char * buf, 294static ssize_t store_blank(struct device *device,
286 size_t count) 295 struct device_attribute *attr,
296 const char *buf, size_t count)
287{ 297{
288 struct fb_info *fb_info = class_get_devdata(class_device); 298 struct fb_info *fb_info = dev_get_drvdata(device);
289 char *last = NULL; 299 char *last = NULL;
290 int err; 300 int err;
291 301
@@ -299,42 +309,48 @@ static ssize_t store_blank(struct class_device *class_device, const char * buf,
299 return count; 309 return count;
300} 310}
301 311
302static ssize_t show_blank(struct class_device *class_device, char *buf) 312static ssize_t show_blank(struct device *device,
313 struct device_attribute *attr, char *buf)
303{ 314{
304// struct fb_info *fb_info = class_get_devdata(class_device); 315// struct fb_info *fb_info = dev_get_drvdata(device);
305 return 0; 316 return 0;
306} 317}
307 318
308static ssize_t store_console(struct class_device *class_device, 319static ssize_t store_console(struct device *device,
309 const char * buf, size_t count) 320 struct device_attribute *attr,
321 const char *buf, size_t count)
310{ 322{
311// struct fb_info *fb_info = class_get_devdata(class_device); 323// struct fb_info *fb_info = dev_get_drvdata(device);
312 return 0; 324 return 0;
313} 325}
314 326
315static ssize_t show_console(struct class_device *class_device, char *buf) 327static ssize_t show_console(struct device *device,
328 struct device_attribute *attr, char *buf)
316{ 329{
317// struct fb_info *fb_info = class_get_devdata(class_device); 330// struct fb_info *fb_info = dev_get_drvdata(device);
318 return 0; 331 return 0;
319} 332}
320 333
321static ssize_t store_cursor(struct class_device *class_device, 334static ssize_t store_cursor(struct device *device,
322 const char * buf, size_t count) 335 struct device_attribute *attr,
336 const char *buf, size_t count)
323{ 337{
324// struct fb_info *fb_info = class_get_devdata(class_device); 338// struct fb_info *fb_info = dev_get_drvdata(device);
325 return 0; 339 return 0;
326} 340}
327 341
328static ssize_t show_cursor(struct class_device *class_device, char *buf) 342static ssize_t show_cursor(struct device *device,
343 struct device_attribute *attr, char *buf)
329{ 344{
330// struct fb_info *fb_info = class_get_devdata(class_device); 345// struct fb_info *fb_info = dev_get_drvdata(device);
331 return 0; 346 return 0;
332} 347}
333 348
334static ssize_t store_pan(struct class_device *class_device, const char * buf, 349static ssize_t store_pan(struct device *device,
335 size_t count) 350 struct device_attribute *attr,
351 const char *buf, size_t count)
336{ 352{
337 struct fb_info *fb_info = class_get_devdata(class_device); 353 struct fb_info *fb_info = dev_get_drvdata(device);
338 struct fb_var_screeninfo var; 354 struct fb_var_screeninfo var;
339 char *last = NULL; 355 char *last = NULL;
340 int err; 356 int err;
@@ -355,24 +371,27 @@ static ssize_t store_pan(struct class_device *class_device, const char * buf,
355 return count; 371 return count;
356} 372}
357 373
358static ssize_t show_pan(struct class_device *class_device, char *buf) 374static ssize_t show_pan(struct device *device,
375 struct device_attribute *attr, char *buf)
359{ 376{
360 struct fb_info *fb_info = class_get_devdata(class_device); 377 struct fb_info *fb_info = dev_get_drvdata(device);
361 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xoffset, 378 return snprintf(buf, PAGE_SIZE, "%d,%d\n", fb_info->var.xoffset,
362 fb_info->var.xoffset); 379 fb_info->var.xoffset);
363} 380}
364 381
365static ssize_t show_name(struct class_device *class_device, char *buf) 382static ssize_t show_name(struct device *device,
383 struct device_attribute *attr, char *buf)
366{ 384{
367 struct fb_info *fb_info = class_get_devdata(class_device); 385 struct fb_info *fb_info = dev_get_drvdata(device);
368 386
369 return snprintf(buf, PAGE_SIZE, "%s\n", fb_info->fix.id); 387 return snprintf(buf, PAGE_SIZE, "%s\n", fb_info->fix.id);
370} 388}
371 389
372static ssize_t store_fbstate(struct class_device *class_device, 390static ssize_t store_fbstate(struct device *device,
373 const char *buf, size_t count) 391 struct device_attribute *attr,
392 const char *buf, size_t count)
374{ 393{
375 struct fb_info *fb_info = class_get_devdata(class_device); 394 struct fb_info *fb_info = dev_get_drvdata(device);
376 u32 state; 395 u32 state;
377 char *last = NULL; 396 char *last = NULL;
378 397
@@ -385,17 +404,19 @@ static ssize_t store_fbstate(struct class_device *class_device,
385 return count; 404 return count;
386} 405}
387 406
388static ssize_t show_fbstate(struct class_device *class_device, char *buf) 407static ssize_t show_fbstate(struct device *device,
408 struct device_attribute *attr, char *buf)
389{ 409{
390 struct fb_info *fb_info = class_get_devdata(class_device); 410 struct fb_info *fb_info = dev_get_drvdata(device);
391 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->state); 411 return snprintf(buf, PAGE_SIZE, "%d\n", fb_info->state);
392} 412}
393 413
394#ifdef CONFIG_FB_BACKLIGHT 414#ifdef CONFIG_FB_BACKLIGHT
395static ssize_t store_bl_curve(struct class_device *class_device, 415static ssize_t store_bl_curve(struct device *device,
396 const char *buf, size_t count) 416 struct device_attribute *attr,
417 const char *buf, size_t count)
397{ 418{
398 struct fb_info *fb_info = class_get_devdata(class_device); 419 struct fb_info *fb_info = dev_get_drvdata(device);
399 u8 tmp_curve[FB_BACKLIGHT_LEVELS]; 420 u8 tmp_curve[FB_BACKLIGHT_LEVELS];
400 unsigned int i; 421 unsigned int i;
401 422
@@ -432,9 +453,10 @@ static ssize_t store_bl_curve(struct class_device *class_device,
432 return count; 453 return count;
433} 454}
434 455
435static ssize_t show_bl_curve(struct class_device *class_device, char *buf) 456static ssize_t show_bl_curve(struct device *device,
457 struct device_attribute *attr, char *buf)
436{ 458{
437 struct fb_info *fb_info = class_get_devdata(class_device); 459 struct fb_info *fb_info = dev_get_drvdata(device);
438 ssize_t len = 0; 460 ssize_t len = 0;
439 unsigned int i; 461 unsigned int i;
440 462
@@ -465,7 +487,7 @@ static ssize_t show_bl_curve(struct class_device *class_device, char *buf)
465/* When cmap is added back in it should be a binary attribute 487/* When cmap is added back in it should be a binary attribute
466 * not a text one. Consideration should also be given to converting 488 * not a text one. Consideration should also be given to converting
467 * fbdev to use configfs instead of sysfs */ 489 * fbdev to use configfs instead of sysfs */
468static struct class_device_attribute class_device_attrs[] = { 490static struct device_attribute device_attrs[] = {
469 __ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp), 491 __ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp),
470 __ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank), 492 __ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank),
471 __ATTR(console, S_IRUGO|S_IWUSR, show_console, store_console), 493 __ATTR(console, S_IRUGO|S_IWUSR, show_console, store_console),
@@ -483,17 +505,16 @@ static struct class_device_attribute class_device_attrs[] = {
483#endif 505#endif
484}; 506};
485 507
486int fb_init_class_device(struct fb_info *fb_info) 508int fb_init_device(struct fb_info *fb_info)
487{ 509{
488 int i, error = 0; 510 int i, error = 0;
489 511
490 class_set_devdata(fb_info->class_device, fb_info); 512 dev_set_drvdata(fb_info->dev, fb_info);
491 513
492 fb_info->class_flag |= FB_SYSFS_FLAG_ATTR; 514 fb_info->class_flag |= FB_SYSFS_FLAG_ATTR;
493 515
494 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++) { 516 for (i = 0; i < ARRAY_SIZE(device_attrs); i++) {
495 error = class_device_create_file(fb_info->class_device, 517 error = device_create_file(fb_info->dev, &device_attrs[i]);
496 &class_device_attrs[i]);
497 518
498 if (error) 519 if (error)
499 break; 520 break;
@@ -501,22 +522,20 @@ int fb_init_class_device(struct fb_info *fb_info)
501 522
502 if (error) { 523 if (error) {
503 while (--i >= 0) 524 while (--i >= 0)
504 class_device_remove_file(fb_info->class_device, 525 device_remove_file(fb_info->dev, &device_attrs[i]);
505 &class_device_attrs[i]);
506 fb_info->class_flag &= ~FB_SYSFS_FLAG_ATTR; 526 fb_info->class_flag &= ~FB_SYSFS_FLAG_ATTR;
507 } 527 }
508 528
509 return 0; 529 return 0;
510} 530}
511 531
512void fb_cleanup_class_device(struct fb_info *fb_info) 532void fb_cleanup_device(struct fb_info *fb_info)
513{ 533{
514 unsigned int i; 534 unsigned int i;
515 535
516 if (fb_info->class_flag & FB_SYSFS_FLAG_ATTR) { 536 if (fb_info->class_flag & FB_SYSFS_FLAG_ATTR) {
517 for (i = 0; i < ARRAY_SIZE(class_device_attrs); i++) 537 for (i = 0; i < ARRAY_SIZE(device_attrs); i++)
518 class_device_remove_file(fb_info->class_device, 538 device_remove_file(fb_info->dev, &device_attrs[i]);
519 &class_device_attrs[i]);
520 539
521 fb_info->class_flag &= ~FB_SYSFS_FLAG_ATTR; 540 fb_info->class_flag &= ~FB_SYSFS_FLAG_ATTR;
522 } 541 }