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authorMatt Carlson <mcarlson@broadcom.com>2010-04-12 02:58:25 -0400
committerDavid S. Miller <davem@davemloft.net>2010-04-13 05:25:43 -0400
commit1a3190254c0d1d1951e1d7e93542387c6ec82384 (patch)
tree6aeebe6eda37c098d639149bbc456741ca9bad53 /drivers
parentcea46462681d61a65a208d17206d38739c1ea1b1 (diff)
tg3: Set card 57765 card reader MRRS to 1024B
This patch sets the Maximum Read Request Size for the card reader function to 1024 bytes to prevent an SD controller lockup. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c2
-rw-r--r--drivers/net/tg3.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4ae01b3799f4..a0ab89eb8bcc 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7704,6 +7704,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { 7704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7705 val = tr32(TG3PCI_DMA_RW_CTRL) & 7705 val = tr32(TG3PCI_DMA_RW_CTRL) &
7706 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; 7706 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7707 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7708 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7707 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); 7709 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7708 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && 7710 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7709 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { 7711 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 8a6012ab23ff..9e7fe0e7cdb8 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -183,6 +183,7 @@
183#define METAL_REV_B2 0x02 183#define METAL_REV_B2 0x02
184#define TG3PCI_DMA_RW_CTRL 0x0000006c 184#define TG3PCI_DMA_RW_CTRL 0x0000006c
185#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 185#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
186#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
186#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 187#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
187#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 188#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
188#define DMA_RWCTRL_READ_BNDRY_16 0x00000100 189#define DMA_RWCTRL_READ_BNDRY_16 0x00000100