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authorRafał Miłecki <zajec5@gmail.com>2010-02-04 06:23:08 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-02-08 16:50:55 -0500
commit67cbc3ed5b96a5acfddae142fa0e2adb1b6270d5 (patch)
tree0d151a917adbe83c9c5bced82e7b9a842541e68b /drivers
parent371ba88322ea5750ad411fdef7674dcee50f7235 (diff)
b43: N-PHY: implement overriding RF control intc
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/b43/phy_n.c117
1 files changed, 109 insertions, 8 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 6392da25efed..8992457b0c0b 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -68,6 +68,10 @@ static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
68 u8 *events, u8 *delays, u8 length); 68 u8 *events, u8 *delays, u8 length);
69static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 69static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
70 enum b43_nphy_rf_sequence seq); 70 enum b43_nphy_rf_sequence seq);
71static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
72 u16 value, u8 core, bool off);
73static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
74 u16 value, u8 core);
71 75
72void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) 76void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
73{//TODO 77{//TODO
@@ -498,8 +502,8 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
498 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 502 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
499 } 503 }
500 504
501 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */ 505 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
502 /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */ 506 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
503 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 507 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
504 508
505 if (core == 0) { 509 if (core == 0) {
@@ -509,9 +513,8 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
509 rxval = 4; 513 rxval = 4;
510 txval = 2; 514 txval = 2;
511 } 515 }
512 516 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
513 /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */ 517 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
514 /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
515} 518}
516 519
517/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ 520/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
@@ -1264,6 +1267,104 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1264 } 1267 }
1265} 1268}
1266 1269
1270/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1271static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1272 u16 value, u8 core)
1273{
1274 u8 i, j;
1275 u16 reg, tmp, val;
1276
1277 B43_WARN_ON(dev->phy.rev < 3);
1278 B43_WARN_ON(field > 4);
1279
1280 for (i = 0; i < 2; i++) {
1281 if ((core == 1 && i == 1) || (core == 2 && !i))
1282 continue;
1283
1284 reg = (i == 0) ?
1285 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1286 b43_phy_mask(dev, reg, 0xFBFF);
1287
1288 switch (field) {
1289 case 0:
1290 b43_phy_write(dev, reg, 0);
1291 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1292 break;
1293 case 1:
1294 if (!i) {
1295 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1296 0xFC3F, (value << 6));
1297 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1298 0xFFFE, 1);
1299 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1300 B43_NPHY_RFCTL_CMD_START);
1301 for (j = 0; j < 100; j++) {
1302 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1303 j = 0;
1304 break;
1305 }
1306 udelay(10);
1307 }
1308 if (j)
1309 b43err(dev->wl,
1310 "intc override timeout\n");
1311 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1312 0xFFFE);
1313 } else {
1314 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1315 0xFC3F, (value << 6));
1316 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1317 0xFFFE, 1);
1318 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1319 B43_NPHY_RFCTL_CMD_RXTX);
1320 for (j = 0; j < 100; j++) {
1321 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1322 j = 0;
1323 break;
1324 }
1325 udelay(10);
1326 }
1327 if (j)
1328 b43err(dev->wl,
1329 "intc override timeout\n");
1330 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1331 0xFFFE);
1332 }
1333 break;
1334 case 2:
1335 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1336 tmp = 0x0020;
1337 val = value << 5;
1338 } else {
1339 tmp = 0x0010;
1340 val = value << 4;
1341 }
1342 b43_phy_maskset(dev, reg, ~tmp, val);
1343 break;
1344 case 3:
1345 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1346 tmp = 0x0001;
1347 val = value;
1348 } else {
1349 tmp = 0x0004;
1350 val = value << 2;
1351 }
1352 b43_phy_maskset(dev, reg, ~tmp, val);
1353 break;
1354 case 4:
1355 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1356 tmp = 0x0002;
1357 val = value << 1;
1358 } else {
1359 tmp = 0x0008;
1360 val = value << 3;
1361 }
1362 b43_phy_maskset(dev, reg, ~tmp, val);
1363 break;
1364 }
1365 }
1366}
1367
1267static void b43_nphy_bphy_init(struct b43_wldev *dev) 1368static void b43_nphy_bphy_init(struct b43_wldev *dev)
1268{ 1369{
1269 unsigned int i; 1370 unsigned int i;
@@ -2161,9 +2262,9 @@ static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2161 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2262 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2162 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2263 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2163 2264
2164 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */ 2265 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2165 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */ 2266 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2166 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */ 2267 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2167 2268
2168 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 2269 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2169 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 2270 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);