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authorBorislav Petkov <borislav.petkov@amd.com>2011-01-07 10:26:49 -0500
committerBorislav Petkov <borislav.petkov@amd.com>2011-03-17 09:46:18 -0400
commit5980bb9cd88a3fa44cc5beab599f08fbc928b832 (patch)
treed5af45439240fb8e6535fc8a11c6f6903966c7ed /drivers
parentbcd781f46a5f892ef2ae5843839849aa579fe096 (diff)
amd64_edac: Cleanup old defines cruft
Remove unused defines, drop family names from define names. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/edac/amd64_edac.c26
-rw-r--r--drivers/edac/amd64_edac.h72
2 files changed, 22 insertions, 76 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 04d481b578e4..729d9f1aecb9 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -229,7 +229,7 @@ static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
229 229
230 scrubval = scrubrates[i].scrubval; 230 scrubval = scrubrates[i].scrubval;
231 231
232 pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); 232 pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
233 233
234 if (scrubval) 234 if (scrubval)
235 return scrubrates[i].bandwidth; 235 return scrubrates[i].bandwidth;
@@ -250,7 +250,7 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
250 u32 scrubval = 0; 250 u32 scrubval = 0;
251 int i, retval = -EINVAL; 251 int i, retval = -EINVAL;
252 252
253 amd64_read_pci_cfg(pvt->F3, K8_SCRCTRL, &scrubval); 253 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
254 254
255 scrubval = scrubval & 0x001F; 255 scrubval = scrubval & 0x001F;
256 256
@@ -843,11 +843,11 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
843 debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); 843 debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
844 844
845 debugf1(" NB two channel DRAM capable: %s\n", 845 debugf1(" NB two channel DRAM capable: %s\n",
846 (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no"); 846 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
847 847
848 debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", 848 debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n",
849 (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no", 849 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
850 (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no"); 850 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
851 851
852 amd64_dump_dramcfg_low(pvt->dclr0, 0); 852 amd64_dump_dramcfg_low(pvt->dclr0, 0);
853 853
@@ -1814,7 +1814,7 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
1814 int ecc_type = (info->nbsh >> 13) & 0x3; 1814 int ecc_type = (info->nbsh >> 13) & 0x3;
1815 1815
1816 /* Bail early out if this was an 'observed' error */ 1816 /* Bail early out if this was an 'observed' error */
1817 if (PP(ec) == K8_NBSL_PP_OBS) 1817 if (PP(ec) == NBSL_PP_OBS)
1818 return; 1818 return;
1819 1819
1820 /* Do only ECC errors */ 1820 /* Do only ECC errors */
@@ -1906,7 +1906,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
1906 } else 1906 } else
1907 debugf0(" TOP_MEM2 disabled.\n"); 1907 debugf0(" TOP_MEM2 disabled.\n");
1908 1908
1909 amd64_read_pci_cfg(pvt->F3, K8_NBCAP, &pvt->nbcap); 1909 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
1910 1910
1911 if (pvt->ops->read_dram_ctl_register) 1911 if (pvt->ops->read_dram_ctl_register)
1912 pvt->ops->read_dram_ctl_register(pvt); 1912 pvt->ops->read_dram_ctl_register(pvt);
@@ -2126,7 +2126,7 @@ static bool amd64_nb_mce_bank_enabled_on_node(int nid)
2126 2126
2127 for_each_cpu(cpu, mask) { 2127 for_each_cpu(cpu, mask) {
2128 struct msr *reg = per_cpu_ptr(msrs, cpu); 2128 struct msr *reg = per_cpu_ptr(msrs, cpu);
2129 nbe = reg->l & K8_MSR_MCGCTL_NBE; 2129 nbe = reg->l & MSR_MCGCTL_NBE;
2130 2130
2131 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", 2131 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2132 cpu, reg->q, 2132 cpu, reg->q,
@@ -2161,16 +2161,16 @@ static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
2161 struct msr *reg = per_cpu_ptr(msrs, cpu); 2161 struct msr *reg = per_cpu_ptr(msrs, cpu);
2162 2162
2163 if (on) { 2163 if (on) {
2164 if (reg->l & K8_MSR_MCGCTL_NBE) 2164 if (reg->l & MSR_MCGCTL_NBE)
2165 s->flags.nb_mce_enable = 1; 2165 s->flags.nb_mce_enable = 1;
2166 2166
2167 reg->l |= K8_MSR_MCGCTL_NBE; 2167 reg->l |= MSR_MCGCTL_NBE;
2168 } else { 2168 } else {
2169 /* 2169 /*
2170 * Turn off NB MCE reporting only when it was off before 2170 * Turn off NB MCE reporting only when it was off before
2171 */ 2171 */
2172 if (!s->flags.nb_mce_enable) 2172 if (!s->flags.nb_mce_enable)
2173 reg->l &= ~K8_MSR_MCGCTL_NBE; 2173 reg->l &= ~MSR_MCGCTL_NBE;
2174 } 2174 }
2175 } 2175 }
2176 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); 2176 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
@@ -2324,10 +2324,10 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
2324 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; 2324 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
2325 mci->edac_ctl_cap = EDAC_FLAG_NONE; 2325 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2326 2326
2327 if (pvt->nbcap & K8_NBCAP_SECDED) 2327 if (pvt->nbcap & NBCAP_SECDED)
2328 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; 2328 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
2329 2329
2330 if (pvt->nbcap & K8_NBCAP_CHIPKILL) 2330 if (pvt->nbcap & NBCAP_CHIPKILL)
2331 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; 2331 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
2332 2332
2333 mci->edac_cap = amd64_determine_edac_cap(pvt); 2333 mci->edac_cap = amd64_determine_edac_cap(pvt);
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 6c52736b09f2..04293306bedc 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -250,57 +250,11 @@
250#define NBCFG_CHIPKILL BIT(23) 250#define NBCFG_CHIPKILL BIT(23)
251#define NBCFG_ECC_ENABLE BIT(22) 251#define NBCFG_ECC_ENABLE BIT(22)
252 252
253#define K8_NBSL 0x48 253/* F3x48: NBSL */
254
255/* Family F10h: Normalized Extended Error Codes */
256#define F10_NBSL_EXT_ERR_RES 0x0
257#define F10_NBSL_EXT_ERR_ECC 0x8 254#define F10_NBSL_EXT_ERR_ECC 0x8
255#define NBSL_PP_OBS 0x2
258 256
259/* Next two are overloaded values */ 257#define SCRCTRL 0x58
260#define F10_NBSL_EXT_ERR_LINK_PROTO 0xB
261#define F10_NBSL_EXT_ERR_L3_PROTO 0xB
262
263#define F10_NBSL_EXT_ERR_NB_ARRAY 0xC
264#define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD
265#define F10_NBSL_EXT_ERR_LINK_RETRY 0xE
266
267/* Next two are overloaded values */
268#define F10_NBSL_EXT_ERR_GART_WALK 0xF
269#define F10_NBSL_EXT_ERR_DEV_WALK 0xF
270
271/* 0x10 to 0x1B: Reserved */
272#define F10_NBSL_EXT_ERR_L3_DATA 0x1C
273#define F10_NBSL_EXT_ERR_L3_TAG 0x1D
274#define F10_NBSL_EXT_ERR_L3_LRU 0x1E
275
276/* K8: Normalized Extended Error Codes */
277#define K8_NBSL_EXT_ERR_ECC 0x0
278#define K8_NBSL_EXT_ERR_CRC 0x1
279#define K8_NBSL_EXT_ERR_SYNC 0x2
280#define K8_NBSL_EXT_ERR_MST 0x3
281#define K8_NBSL_EXT_ERR_TGT 0x4
282#define K8_NBSL_EXT_ERR_GART 0x5
283#define K8_NBSL_EXT_ERR_RMW 0x6
284#define K8_NBSL_EXT_ERR_WDT 0x7
285#define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8
286#define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD
287
288/*
289 * The following are for BUS type errors AFTER values have been normalized by
290 * shifting right
291 */
292#define K8_NBSL_PP_SRC 0x0
293#define K8_NBSL_PP_RES 0x1
294#define K8_NBSL_PP_OBS 0x2
295#define K8_NBSL_PP_GENERIC 0x3
296
297#define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
298
299#define K8_NBEAL 0x50
300#define K8_NBEAH 0x54
301#define K8_SCRCTRL 0x58
302
303#define F10_NB_CFG_LOW 0x88
304 258
305#define F10_ONLINE_SPARE 0xB0 259#define F10_ONLINE_SPARE 0xB0
306#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) 260#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
@@ -309,36 +263,28 @@
309#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) 263#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
310 264
311#define F10_NB_ARRAY_ADDR 0xB8 265#define F10_NB_ARRAY_ADDR 0xB8
312 266#define F10_NB_ARRAY_DRAM_ECC BIT(31)
313#define F10_NB_ARRAY_DRAM_ECC 0x80000000
314 267
315/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 268/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
316#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) 269#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
317 270
318#define F10_NB_ARRAY_DATA 0xBC 271#define F10_NB_ARRAY_DATA 0xBC
319
320#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ 272#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
321 (BIT(((word) & 0xF) + 20) | \ 273 (BIT(((word) & 0xF) + 20) | \
322 BIT(17) | bits) 274 BIT(17) | bits)
323
324#define SET_NB_DRAM_INJECTION_READ(word, bits) \ 275#define SET_NB_DRAM_INJECTION_READ(word, bits) \
325 (BIT(((word) & 0xF) + 20) | \ 276 (BIT(((word) & 0xF) + 20) | \
326 BIT(16) | bits) 277 BIT(16) | bits)
327 278
328#define K8_NBCAP 0xE8 279#define NBCAP 0xE8
329#define K8_NBCAP_CORES (BIT(12)|BIT(13)) 280#define NBCAP_CHIPKILL BIT(4)
330#define K8_NBCAP_CHIPKILL BIT(4) 281#define NBCAP_SECDED BIT(3)
331#define K8_NBCAP_SECDED BIT(3) 282#define NBCAP_DCT_DUAL BIT(0)
332#define K8_NBCAP_DCT_DUAL BIT(0)
333 283
334#define EXT_NB_MCA_CFG 0x180 284#define EXT_NB_MCA_CFG 0x180
335 285
336/* MSRs */ 286/* MSRs */
337#define K8_MSR_MCGCTL_NBE BIT(4) 287#define MSR_MCGCTL_NBE BIT(4)
338
339#define K8_MSR_MC4CTL 0x0410
340#define K8_MSR_MC4STAT 0x0411
341#define K8_MSR_MC4ADDR 0x0412
342 288
343/* AMD sets the first MC device at device ID 0x18. */ 289/* AMD sets the first MC device at device ID 0x18. */
344static inline int get_node_id(struct pci_dev *pdev) 290static inline int get_node_id(struct pci_dev *pdev)