aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorSteve Wise <swise@opengridcomputing.com>2010-05-20 17:58:05 -0400
committerRoland Dreier <rolandd@cisco.com>2010-05-25 00:08:03 -0400
commitf64b88433c27815f931d4d5ff7db7ac701fdc8c9 (patch)
tree6881d14dc4fd695e237f6003f5898f95eb8f0c9d /drivers
parent25737bd4ca1b58e86efa9211c1717140e0d4910e (diff)
RDMA/cxgb4: Update some HW limits
Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/infiniband/hw/cxgb4/t4.h17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h
index 333abd3c7264..1057cb96302e 100644
--- a/drivers/infiniband/hw/cxgb4/t4.h
+++ b/drivers/infiniband/hw/cxgb4/t4.h
@@ -41,11 +41,13 @@
41#define T4_MAX_NUM_QP (1<<16) 41#define T4_MAX_NUM_QP (1<<16)
42#define T4_MAX_NUM_CQ (1<<15) 42#define T4_MAX_NUM_CQ (1<<15)
43#define T4_MAX_NUM_PD (1<<15) 43#define T4_MAX_NUM_PD (1<<15)
44#define T4_MAX_PBL_SIZE 256 44#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
45#define T4_MAX_RQ_SIZE 1024 45#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
46#define T4_MAX_SQ_SIZE 1024 46#define T4_MAX_IQ_SIZE (65520 - 1)
47#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE-1) 47#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
48#define T4_MAX_CQ_DEPTH 8192 48#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
49#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
50#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
49#define T4_MAX_NUM_STAG (1<<15) 51#define T4_MAX_NUM_STAG (1<<15)
50#define T4_MAX_MR_SIZE (~0ULL - 1) 52#define T4_MAX_MR_SIZE (~0ULL - 1)
51#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ 53#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
@@ -79,12 +81,11 @@ struct t4_status_page {
79 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 81 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
80#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 82#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
81 sizeof(struct fw_ri_immd))) 83 sizeof(struct fw_ri_immd)))
82#define T4_MAX_FR_DEPTH 255 84#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
83 85
84#define T4_RQ_NUM_SLOTS 2 86#define T4_RQ_NUM_SLOTS 2
85#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS) 87#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
86#define T4_MAX_RECV_SGE ((T4_RQ_NUM_BYTES - sizeof(struct fw_ri_recv_wr) - \ 88#define T4_MAX_RECV_SGE 4
87 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
88 89
89union t4_wr { 90union t4_wr {
90 struct fw_ri_res_wr res; 91 struct fw_ri_res_wr res;