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authorMatt Carlson <mcarlson@broadcom.com>2010-02-17 10:17:04 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-17 20:27:40 -0500
commit6a443a0f72ad7706345412dbd2e4d4981fdfce39 (patch)
treee0e9724789c0bf2e232bae18080147834e58da50 /drivers
parent79eb6904361fe4e54e589919a9b62c5e036c42c3 (diff)
tg3: Push phylib definitions to phylib
This patch pushes phylib definitions out to phylib headers. For phy IDs, this removes some code duplication. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/phy/broadcom.c5
-rw-r--r--drivers/net/tg3.c32
-rw-r--r--drivers/net/tg3.h14
3 files changed, 20 insertions, 31 deletions
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 33c4b12a63ba..f482fc4f8cf1 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -18,9 +18,6 @@
18#include <linux/phy.h> 18#include <linux/phy.h>
19#include <linux/brcmphy.h> 19#include <linux/brcmphy.h>
20 20
21#define PHY_ID_BCM50610 0x0143bd60
22#define PHY_ID_BCM50610M 0x0143bd70
23#define PHY_ID_BCM57780 0x03625d90
24 21
25#define BRCM_PHY_MODEL(phydev) \ 22#define BRCM_PHY_MODEL(phydev) \
26 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask) 23 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
@@ -823,7 +820,7 @@ static struct phy_driver bcm57780_driver = {
823}; 820};
824 821
825static struct phy_driver bcmac131_driver = { 822static struct phy_driver bcmac131_driver = {
826 .phy_id = 0x0143bc70, 823 .phy_id = PHY_ID_BCMAC131,
827 .phy_id_mask = 0xfffffff0, 824 .phy_id_mask = 0xfffffff0,
828 .name = "Broadcom BCMAC131", 825 .name = "Broadcom BCMAC131",
829 .features = PHY_BASIC_FEATURES | 826 .features = PHY_BASIC_FEATURES |
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 965efa92b020..994bac0b018b 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -955,17 +955,17 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
955 955
956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; 956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
957 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { 957 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
958 case TG3_PHY_ID_BCM50610: 958 case PHY_ID_BCM50610:
959 case TG3_PHY_ID_BCM50610M: 959 case PHY_ID_BCM50610M:
960 val = MAC_PHYCFG2_50610_LED_MODES; 960 val = MAC_PHYCFG2_50610_LED_MODES;
961 break; 961 break;
962 case TG3_PHY_ID_BCMAC131: 962 case PHY_ID_BCMAC131:
963 val = MAC_PHYCFG2_AC131_LED_MODES; 963 val = MAC_PHYCFG2_AC131_LED_MODES;
964 break; 964 break;
965 case TG3_PHY_ID_RTL8211C: 965 case PHY_ID_RTL8211C:
966 val = MAC_PHYCFG2_RTL8211C_LED_MODES; 966 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
967 break; 967 break;
968 case TG3_PHY_ID_RTL8201E: 968 case PHY_ID_RTL8201E:
969 val = MAC_PHYCFG2_RTL8201E_LED_MODES; 969 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
970 break; 970 break;
971 default: 971 default:
@@ -1115,12 +1115,12 @@ static int tg3_mdio_init(struct tg3 *tp)
1115 } 1115 }
1116 1116
1117 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { 1117 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1118 case TG3_PHY_ID_BCM57780: 1118 case PHY_ID_BCM57780:
1119 phydev->interface = PHY_INTERFACE_MODE_GMII; 1119 phydev->interface = PHY_INTERFACE_MODE_GMII;
1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; 1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121 break; 1121 break;
1122 case TG3_PHY_ID_BCM50610: 1122 case PHY_ID_BCM50610:
1123 case TG3_PHY_ID_BCM50610M: 1123 case PHY_ID_BCM50610M:
1124 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | 1124 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1125 PHY_BRCM_RX_REFCLK_UNUSED | 1125 PHY_BRCM_RX_REFCLK_UNUSED |
1126 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1126 PHY_BRCM_DIS_TXCRXC_NOENRGY |
@@ -1132,11 +1132,11 @@ static int tg3_mdio_init(struct tg3 *tp)
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) 1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; 1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1134 /* fallthru */ 1134 /* fallthru */
1135 case TG3_PHY_ID_RTL8211C: 1135 case PHY_ID_RTL8211C:
1136 phydev->interface = PHY_INTERFACE_MODE_RGMII; 1136 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1137 break; 1137 break;
1138 case TG3_PHY_ID_RTL8201E: 1138 case PHY_ID_RTL8201E:
1139 case TG3_PHY_ID_BCMAC131: 1139 case PHY_ID_BCMAC131:
1140 phydev->interface = PHY_INTERFACE_MODE_MII; 1140 phydev->interface = PHY_INTERFACE_MODE_MII;
1141 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; 1141 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1142 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; 1142 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
@@ -2563,11 +2563,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2563 phy_start_aneg(phydev); 2563 phy_start_aneg(phydev);
2564 2564
2565 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; 2565 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2566 if (phyid != TG3_PHY_ID_BCMAC131) { 2566 if (phyid != PHY_ID_BCMAC131) {
2567 phyid &= TG3_PHY_OUI_MASK; 2567 phyid &= PHY_BCM_OUI_MASK;
2568 if (phyid == TG3_PHY_OUI_1 || 2568 if (phyid == PHY_BCM_OUI_1 ||
2569 phyid == TG3_PHY_OUI_2 || 2569 phyid == PHY_BCM_OUI_2 ||
2570 phyid == TG3_PHY_OUI_3) 2570 phyid == PHY_BCM_OUI_3)
2571 do_low_power = true; 2571 do_low_power = true;
2572 } 2572 }
2573 } 2573 }
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 800dec463e98..574a1cc4d353 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2943,22 +2943,14 @@ struct tg3 {
2943#define TG3_PHY_ID_BCM57765 0x5c0d8a40 2943#define TG3_PHY_ID_BCM57765 0x5c0d8a40
2944#define TG3_PHY_ID_BCM5906 0xdc00ac40 2944#define TG3_PHY_ID_BCM5906 0xdc00ac40
2945#define TG3_PHY_ID_BCM8002 0x60010140 2945#define TG3_PHY_ID_BCM8002 0x60010140
2946#define TG3_PHY_ID_BCM50610 0x0143bd60
2947#define TG3_PHY_ID_BCM50610M 0x0143bd70
2948#define TG3_PHY_ID_BCMAC131 0x0143bc70
2949#define TG3_PHY_ID_RTL8211C 0x001cc910
2950#define TG3_PHY_ID_RTL8201E 0x00008200
2951#define TG3_PHY_ID_BCM57780 0x03625d90
2952#define TG3_PHY_ID_INVALID 0xffffffff 2946#define TG3_PHY_ID_INVALID 0xffffffff
2953 2947
2948#define PHY_ID_RTL8211C 0x001cc910
2949#define PHY_ID_RTL8201E 0x00008200
2950
2954#define TG3_PHY_ID_REV_MASK 0x0000000f 2951#define TG3_PHY_ID_REV_MASK 0x0000000f
2955#define TG3_PHY_REV_BCM5401_B0 0x1 2952#define TG3_PHY_REV_BCM5401_B0 0x1
2956 2953
2957#define TG3_PHY_OUI_MASK 0xfffffc00
2958#define TG3_PHY_OUI_1 0x00206000
2959#define TG3_PHY_OUI_2 0x0143bc00
2960#define TG3_PHY_OUI_3 0x03625c00
2961
2962 /* This macro assumes the passed PHY ID is 2954 /* This macro assumes the passed PHY ID is
2963 * already masked with TG3_PHY_ID_MASK. 2955 * already masked with TG3_PHY_ID_MASK.
2964 */ 2956 */