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authorIra Snyder <iws@ovro.caltech.edu>2011-03-03 02:54:57 -0500
committerDan Williams <dan.j.williams@intel.com>2011-03-11 20:52:36 -0500
commit31f4306c83a2daa3e348056b720de511bffe5a9b (patch)
treea11e82cde6d5ce8098c9fd02c7069be74b400517 /drivers
parent0ab09c36818ca88f65c88f4d8c6d067fbf10578d (diff)
fsldma: minor codingstyle and consistency fixes
This fixes some minor violations of the coding style. It also changes the style of the device_prep_dma_*() function definitions so they are identical. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/dma/fsldma.c29
-rw-r--r--drivers/dma/fsldma.h4
2 files changed, 15 insertions, 18 deletions
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 82b8e9f9c7bf..5da1a4a817e3 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -89,7 +89,7 @@ static void set_desc_cnt(struct fsldma_chan *chan,
89} 89}
90 90
91static void set_desc_src(struct fsldma_chan *chan, 91static void set_desc_src(struct fsldma_chan *chan,
92 struct fsl_dma_ld_hw *hw, dma_addr_t src) 92 struct fsl_dma_ld_hw *hw, dma_addr_t src)
93{ 93{
94 u64 snoop_bits; 94 u64 snoop_bits;
95 95
@@ -99,7 +99,7 @@ static void set_desc_src(struct fsldma_chan *chan,
99} 99}
100 100
101static void set_desc_dst(struct fsldma_chan *chan, 101static void set_desc_dst(struct fsldma_chan *chan,
102 struct fsl_dma_ld_hw *hw, dma_addr_t dst) 102 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
103{ 103{
104 u64 snoop_bits; 104 u64 snoop_bits;
105 105
@@ -109,7 +109,7 @@ static void set_desc_dst(struct fsldma_chan *chan,
109} 109}
110 110
111static void set_desc_next(struct fsldma_chan *chan, 111static void set_desc_next(struct fsldma_chan *chan,
112 struct fsl_dma_ld_hw *hw, dma_addr_t next) 112 struct fsl_dma_ld_hw *hw, dma_addr_t next)
113{ 113{
114 u64 snoop_bits; 114 u64 snoop_bits;
115 115
@@ -118,8 +118,7 @@ static void set_desc_next(struct fsldma_chan *chan,
118 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); 118 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
119} 119}
120 120
121static void set_ld_eol(struct fsldma_chan *chan, 121static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
122 struct fsl_desc_sw *desc)
123{ 122{
124 u64 snoop_bits; 123 u64 snoop_bits;
125 124
@@ -338,8 +337,7 @@ static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
338 chan->feature &= ~FSL_DMA_CHAN_START_EXT; 337 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
339} 338}
340 339
341static void append_ld_queue(struct fsldma_chan *chan, 340static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
342 struct fsl_desc_sw *desc)
343{ 341{
344 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); 342 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
345 343
@@ -380,8 +378,8 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
380 cookie = chan->common.cookie; 378 cookie = chan->common.cookie;
381 list_for_each_entry(child, &desc->tx_list, node) { 379 list_for_each_entry(child, &desc->tx_list, node) {
382 cookie++; 380 cookie++;
383 if (cookie < 0) 381 if (cookie < DMA_MIN_COOKIE)
384 cookie = 1; 382 cookie = DMA_MIN_COOKIE;
385 383
386 child->async_tx.cookie = cookie; 384 child->async_tx.cookie = cookie;
387 } 385 }
@@ -402,8 +400,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
402 * 400 *
403 * Return - The descriptor allocated. NULL for failed. 401 * Return - The descriptor allocated. NULL for failed.
404 */ 402 */
405static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 403static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
406 struct fsldma_chan *chan)
407{ 404{
408 struct fsl_desc_sw *desc; 405 struct fsl_desc_sw *desc;
409 dma_addr_t pdesc; 406 dma_addr_t pdesc;
@@ -427,7 +424,6 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
427 return desc; 424 return desc;
428} 425}
429 426
430
431/** 427/**
432 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 428 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
433 * @chan : Freescale DMA channel 429 * @chan : Freescale DMA channel
@@ -537,14 +533,15 @@ fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
537 /* Insert the link descriptor to the LD ring */ 533 /* Insert the link descriptor to the LD ring */
538 list_add_tail(&new->node, &new->tx_list); 534 list_add_tail(&new->node, &new->tx_list);
539 535
540 /* Set End-of-link to the last link descriptor of new list*/ 536 /* Set End-of-link to the last link descriptor of new list */
541 set_ld_eol(chan, new); 537 set_ld_eol(chan, new);
542 538
543 return &new->async_tx; 539 return &new->async_tx;
544} 540}
545 541
546static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 542static struct dma_async_tx_descriptor *
547 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, 543fsl_dma_prep_memcpy(struct dma_chan *dchan,
544 dma_addr_t dma_dst, dma_addr_t dma_src,
548 size_t len, unsigned long flags) 545 size_t len, unsigned long flags)
549{ 546{
550 struct fsldma_chan *chan; 547 struct fsldma_chan *chan;
@@ -594,7 +591,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
594 new->async_tx.flags = flags; /* client is in control of this ack */ 591 new->async_tx.flags = flags; /* client is in control of this ack */
595 new->async_tx.cookie = -EBUSY; 592 new->async_tx.cookie = -EBUSY;
596 593
597 /* Set End-of-link to the last link descriptor of new list*/ 594 /* Set End-of-link to the last link descriptor of new list */
598 set_ld_eol(chan, new); 595 set_ld_eol(chan, new);
599 596
600 return &first->async_tx; 597 return &first->async_tx;
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 113e7134010b..49189dacd5f4 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -102,8 +102,8 @@ struct fsl_desc_sw {
102} __attribute__((aligned(32))); 102} __attribute__((aligned(32)));
103 103
104struct fsldma_chan_regs { 104struct fsldma_chan_regs {
105 u32 mr; /* 0x00 - Mode Register */ 105 u32 mr; /* 0x00 - Mode Register */
106 u32 sr; /* 0x04 - Status Register */ 106 u32 sr; /* 0x04 - Status Register */
107 u64 cdar; /* 0x08 - Current descriptor address register */ 107 u64 cdar; /* 0x08 - Current descriptor address register */
108 u64 sar; /* 0x10 - Source Address Register */ 108 u64 sar; /* 0x10 - Source Address Register */
109 u64 dar; /* 0x18 - Destination Address Register */ 109 u64 dar; /* 0x18 - Destination Address Register */