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authorStephen Hemminger <shemminger@linux-foundation.org>2007-05-24 18:22:43 -0400
committerJeff Garzik <jeff@garzik.org>2007-05-30 09:52:47 -0400
commitb4ed372b29e458021293e1c791d92d90f1bf5fe3 (patch)
tree717bacf9e4679908db59f41d7f88147f28070b6f /drivers
parent8903bab009d3e9b34050042f8c0faf741eb027be (diff)
sky2: dont set bogus bit in PHY register
This code inherited from the sk98lin driver is incorrect on the Yukon2. The GPHY_CTRL register values are specific to the internal PHY of the chip and the values used were leftovers. Driver was setting bit 13 which is now the INT polarity for the PHY! Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/sky2.c2
-rw-r--r--drivers/net/sky2.h22
2 files changed, 1 insertions, 23 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 832fd69a0e59..d9bc98bd8af7 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -658,7 +658,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
658 const u8 *addr = hw->dev[port]->dev_addr; 658 const u8 *addr = hw->dev[port]->dev_addr;
659 659
660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); 661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 662
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664 664
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 5efb5afc45ba..3266609cd819 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -1732,28 +1732,6 @@ enum {
1732 1732
1733/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 1733/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1734enum { 1734enum {
1735 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1736 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1737 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1738 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1739 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1740 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1741 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1742 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1743 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1744 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1745 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1746 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1747 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1748 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1749 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1750 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1751 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1752 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1753 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1754 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1755 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1756 /* Bits 7..2: reserved */
1757 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 1735 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1758 GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 1736 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1759}; 1737};