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authorJouni Hogander <jouni.hogander@nokia.com>2009-09-22 19:45:58 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-23 10:39:42 -0400
commit7a8fa725b21ae19a3d9a2de196a440da8c9085a6 (patch)
treeb6eedf5cba51e899a8ad6c5bd40f1c8c6f196f14 /drivers
parent07fcaa2486ca4f5c67bebedfa56e705c4dd23fc2 (diff)
spi: omap2_mcspi use BIT(n)
Convert bit shifted values into BIT format Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/omap2_mcspi.c50
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 9b80ad36dbba..ae785cc627b6 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -59,40 +59,40 @@
59 59
60/* per-register bitmasks: */ 60/* per-register bitmasks: */
61 61
62#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) 62#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
63#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2) 63#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
64#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0) 64#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
65#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1) 65#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
66 66
67#define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0) 67#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
68 68
69#define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0) 69#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
70#define OMAP2_MCSPI_MODULCTRL_MS (1 << 2) 70#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
71#define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3) 71#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
72 72
73#define OMAP2_MCSPI_CHCONF_PHA (1 << 0) 73#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
74#define OMAP2_MCSPI_CHCONF_POL (1 << 1) 74#define OMAP2_MCSPI_CHCONF_POL BIT(1)
75#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 75#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
76#define OMAP2_MCSPI_CHCONF_EPOL (1 << 6) 76#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
77#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 77#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
78#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12) 78#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
79#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12) 79#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
80#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 80#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
81#define OMAP2_MCSPI_CHCONF_DMAW (1 << 14) 81#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
82#define OMAP2_MCSPI_CHCONF_DMAR (1 << 15) 82#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
83#define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16) 83#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
84#define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17) 84#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
85#define OMAP2_MCSPI_CHCONF_IS (1 << 18) 85#define OMAP2_MCSPI_CHCONF_IS BIT(18)
86#define OMAP2_MCSPI_CHCONF_TURBO (1 << 19) 86#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
87#define OMAP2_MCSPI_CHCONF_FORCE (1 << 20) 87#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
88 88
89#define OMAP2_MCSPI_CHSTAT_RXS (1 << 0) 89#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
90#define OMAP2_MCSPI_CHSTAT_TXS (1 << 1) 90#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
91#define OMAP2_MCSPI_CHSTAT_EOT (1 << 2) 91#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
92 92
93#define OMAP2_MCSPI_CHCTRL_EN (1 << 0) 93#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
94 94
95#define OMAP2_MCSPI_WAKEUPENABLE_WKEN (1 << 0) 95#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
96 96
97/* We have 2 DMA channels per CS, one for RX and one for TX */ 97/* We have 2 DMA channels per CS, one for RX and one for TX */
98struct omap2_mcspi_dma { 98struct omap2_mcspi_dma {