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authorJoe Perches <joe@perches.com>2008-04-03 13:06:32 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-04-16 20:41:45 -0400
commit406874a7ccee927049b1c182df69457718b938da (patch)
treea5110e1ef04eeba215460ca5b8ceae2cc413a8b5 /drivers
parent222441a6201f791238320e77eb4ba9528cd3934c (diff)
e1000: convert uint16_t style integers to u16
Conglomerate from 4 separate patches from Joe. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000/e1000.h86
-rw-r--r--drivers/net/e1000/e1000_ethtool.c160
-rw-r--r--drivers/net/e1000/e1000_hw.c1324
-rw-r--r--drivers/net/e1000/e1000_hw.h512
-rw-r--r--drivers/net/e1000/e1000_main.c174
5 files changed, 1128 insertions, 1128 deletions
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index a05aa51ecfa6..31feae1ea390 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -161,13 +161,13 @@ struct e1000_buffer {
161 struct sk_buff *skb; 161 struct sk_buff *skb;
162 dma_addr_t dma; 162 dma_addr_t dma;
163 unsigned long time_stamp; 163 unsigned long time_stamp;
164 uint16_t length; 164 u16 length;
165 uint16_t next_to_watch; 165 u16 next_to_watch;
166}; 166};
167 167
168 168
169struct e1000_ps_page { struct page *ps_page[PS_PAGE_BUFFERS]; }; 169struct e1000_ps_page { struct page *ps_page[PS_PAGE_BUFFERS]; };
170struct e1000_ps_page_dma { uint64_t ps_page_dma[PS_PAGE_BUFFERS]; }; 170struct e1000_ps_page_dma { u64 ps_page_dma[PS_PAGE_BUFFERS]; };
171 171
172struct e1000_tx_ring { 172struct e1000_tx_ring {
173 /* pointer to the descriptor ring memory */ 173 /* pointer to the descriptor ring memory */
@@ -186,8 +186,8 @@ struct e1000_tx_ring {
186 struct e1000_buffer *buffer_info; 186 struct e1000_buffer *buffer_info;
187 187
188 spinlock_t tx_lock; 188 spinlock_t tx_lock;
189 uint16_t tdh; 189 u16 tdh;
190 uint16_t tdt; 190 u16 tdt;
191 bool last_tx_tso; 191 bool last_tx_tso;
192}; 192};
193 193
@@ -213,8 +213,8 @@ struct e1000_rx_ring {
213 /* cpu for rx queue */ 213 /* cpu for rx queue */
214 int cpu; 214 int cpu;
215 215
216 uint16_t rdh; 216 u16 rdh;
217 uint16_t rdt; 217 u16 rdt;
218}; 218};
219 219
220#define E1000_DESC_UNUSED(R) \ 220#define E1000_DESC_UNUSED(R) \
@@ -237,14 +237,14 @@ struct e1000_adapter {
237 struct timer_list watchdog_timer; 237 struct timer_list watchdog_timer;
238 struct timer_list phy_info_timer; 238 struct timer_list phy_info_timer;
239 struct vlan_group *vlgrp; 239 struct vlan_group *vlgrp;
240 uint16_t mng_vlan_id; 240 u16 mng_vlan_id;
241 uint32_t bd_number; 241 u32 bd_number;
242 uint32_t rx_buffer_len; 242 u32 rx_buffer_len;
243 uint32_t wol; 243 u32 wol;
244 uint32_t smartspeed; 244 u32 smartspeed;
245 uint32_t en_mng_pt; 245 u32 en_mng_pt;
246 uint16_t link_speed; 246 u16 link_speed;
247 uint16_t link_duplex; 247 u16 link_duplex;
248 spinlock_t stats_lock; 248 spinlock_t stats_lock;
249#ifdef CONFIG_E1000_NAPI 249#ifdef CONFIG_E1000_NAPI
250 spinlock_t tx_queue_lock; 250 spinlock_t tx_queue_lock;
@@ -254,13 +254,13 @@ struct e1000_adapter {
254 unsigned int total_rx_bytes; 254 unsigned int total_rx_bytes;
255 unsigned int total_rx_packets; 255 unsigned int total_rx_packets;
256 /* Interrupt Throttle Rate */ 256 /* Interrupt Throttle Rate */
257 uint32_t itr; 257 u32 itr;
258 uint32_t itr_setting; 258 u32 itr_setting;
259 uint16_t tx_itr; 259 u16 tx_itr;
260 uint16_t rx_itr; 260 u16 rx_itr;
261 261
262 struct work_struct reset_task; 262 struct work_struct reset_task;
263 uint8_t fc_autoneg; 263 u8 fc_autoneg;
264 264
265 struct timer_list blink_timer; 265 struct timer_list blink_timer;
266 unsigned long led_status; 266 unsigned long led_status;
@@ -269,18 +269,18 @@ struct e1000_adapter {
269 struct e1000_tx_ring *tx_ring; /* One per active queue */ 269 struct e1000_tx_ring *tx_ring; /* One per active queue */
270 unsigned int restart_queue; 270 unsigned int restart_queue;
271 unsigned long tx_queue_len; 271 unsigned long tx_queue_len;
272 uint32_t txd_cmd; 272 u32 txd_cmd;
273 uint32_t tx_int_delay; 273 u32 tx_int_delay;
274 uint32_t tx_abs_int_delay; 274 u32 tx_abs_int_delay;
275 uint32_t gotcl; 275 u32 gotcl;
276 uint64_t gotcl_old; 276 u64 gotcl_old;
277 uint64_t tpt_old; 277 u64 tpt_old;
278 uint64_t colc_old; 278 u64 colc_old;
279 uint32_t tx_timeout_count; 279 u32 tx_timeout_count;
280 uint32_t tx_fifo_head; 280 u32 tx_fifo_head;
281 uint32_t tx_head_addr; 281 u32 tx_head_addr;
282 uint32_t tx_fifo_size; 282 u32 tx_fifo_size;
283 uint8_t tx_timeout_factor; 283 u8 tx_timeout_factor;
284 atomic_t tx_fifo_stall; 284 atomic_t tx_fifo_stall;
285 bool pcix_82544; 285 bool pcix_82544;
286 bool detect_tx_hung; 286 bool detect_tx_hung;
@@ -305,17 +305,17 @@ struct e1000_adapter {
305 int num_tx_queues; 305 int num_tx_queues;
306 int num_rx_queues; 306 int num_rx_queues;
307 307
308 uint64_t hw_csum_err; 308 u64 hw_csum_err;
309 uint64_t hw_csum_good; 309 u64 hw_csum_good;
310 uint64_t rx_hdr_split; 310 u64 rx_hdr_split;
311 uint32_t alloc_rx_buff_failed; 311 u32 alloc_rx_buff_failed;
312 uint32_t rx_int_delay; 312 u32 rx_int_delay;
313 uint32_t rx_abs_int_delay; 313 u32 rx_abs_int_delay;
314 bool rx_csum; 314 bool rx_csum;
315 unsigned int rx_ps_pages; 315 unsigned int rx_ps_pages;
316 uint32_t gorcl; 316 u32 gorcl;
317 uint64_t gorcl_old; 317 u64 gorcl_old;
318 uint16_t rx_ps_bsize0; 318 u16 rx_ps_bsize0;
319 319
320 320
321 /* OS defined structs */ 321 /* OS defined structs */
@@ -329,7 +329,7 @@ struct e1000_adapter {
329 struct e1000_phy_info phy_info; 329 struct e1000_phy_info phy_info;
330 struct e1000_phy_stats phy_stats; 330 struct e1000_phy_stats phy_stats;
331 331
332 uint32_t test_icr; 332 u32 test_icr;
333 struct e1000_tx_ring test_tx_ring; 333 struct e1000_tx_ring test_tx_ring;
334 struct e1000_rx_ring test_rx_ring; 334 struct e1000_rx_ring test_rx_ring;
335 335
@@ -341,7 +341,7 @@ struct e1000_adapter {
341 bool smart_power_down; /* phy smart power down */ 341 bool smart_power_down; /* phy smart power down */
342 bool quad_port_a; 342 bool quad_port_a;
343 unsigned long flags; 343 unsigned long flags;
344 uint32_t eeprom_wol; 344 u32 eeprom_wol;
345}; 345};
346 346
347enum e1000_state_t { 347enum e1000_state_t {
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 05e1fb3cf49f..701531e72e7b 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -36,7 +36,7 @@ extern int e1000_up(struct e1000_adapter *adapter);
36extern void e1000_down(struct e1000_adapter *adapter); 36extern void e1000_down(struct e1000_adapter *adapter);
37extern void e1000_reinit_locked(struct e1000_adapter *adapter); 37extern void e1000_reinit_locked(struct e1000_adapter *adapter);
38extern void e1000_reset(struct e1000_adapter *adapter); 38extern void e1000_reset(struct e1000_adapter *adapter);
39extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx); 39extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx);
40extern int e1000_setup_all_rx_resources(struct e1000_adapter *adapter); 40extern int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
41extern int e1000_setup_all_tx_resources(struct e1000_adapter *adapter); 41extern int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
42extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter); 42extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
@@ -289,7 +289,7 @@ e1000_set_pauseparam(struct net_device *netdev,
289 return retval; 289 return retval;
290} 290}
291 291
292static uint32_t 292static u32
293e1000_get_rx_csum(struct net_device *netdev) 293e1000_get_rx_csum(struct net_device *netdev)
294{ 294{
295 struct e1000_adapter *adapter = netdev_priv(netdev); 295 struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -297,7 +297,7 @@ e1000_get_rx_csum(struct net_device *netdev)
297} 297}
298 298
299static int 299static int
300e1000_set_rx_csum(struct net_device *netdev, uint32_t data) 300e1000_set_rx_csum(struct net_device *netdev, u32 data)
301{ 301{
302 struct e1000_adapter *adapter = netdev_priv(netdev); 302 struct e1000_adapter *adapter = netdev_priv(netdev);
303 adapter->rx_csum = data; 303 adapter->rx_csum = data;
@@ -309,14 +309,14 @@ e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
309 return 0; 309 return 0;
310} 310}
311 311
312static uint32_t 312static u32
313e1000_get_tx_csum(struct net_device *netdev) 313e1000_get_tx_csum(struct net_device *netdev)
314{ 314{
315 return (netdev->features & NETIF_F_HW_CSUM) != 0; 315 return (netdev->features & NETIF_F_HW_CSUM) != 0;
316} 316}
317 317
318static int 318static int
319e1000_set_tx_csum(struct net_device *netdev, uint32_t data) 319e1000_set_tx_csum(struct net_device *netdev, u32 data)
320{ 320{
321 struct e1000_adapter *adapter = netdev_priv(netdev); 321 struct e1000_adapter *adapter = netdev_priv(netdev);
322 322
@@ -335,7 +335,7 @@ e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
335} 335}
336 336
337static int 337static int
338e1000_set_tso(struct net_device *netdev, uint32_t data) 338e1000_set_tso(struct net_device *netdev, u32 data)
339{ 339{
340 struct e1000_adapter *adapter = netdev_priv(netdev); 340 struct e1000_adapter *adapter = netdev_priv(netdev);
341 if ((adapter->hw.mac_type < e1000_82544) || 341 if ((adapter->hw.mac_type < e1000_82544) ||
@@ -357,7 +357,7 @@ e1000_set_tso(struct net_device *netdev, uint32_t data)
357 return 0; 357 return 0;
358} 358}
359 359
360static uint32_t 360static u32
361e1000_get_msglevel(struct net_device *netdev) 361e1000_get_msglevel(struct net_device *netdev)
362{ 362{
363 struct e1000_adapter *adapter = netdev_priv(netdev); 363 struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -365,7 +365,7 @@ e1000_get_msglevel(struct net_device *netdev)
365} 365}
366 366
367static void 367static void
368e1000_set_msglevel(struct net_device *netdev, uint32_t data) 368e1000_set_msglevel(struct net_device *netdev, u32 data)
369{ 369{
370 struct e1000_adapter *adapter = netdev_priv(netdev); 370 struct e1000_adapter *adapter = netdev_priv(netdev);
371 adapter->msg_enable = data; 371 adapter->msg_enable = data;
@@ -375,7 +375,7 @@ static int
375e1000_get_regs_len(struct net_device *netdev) 375e1000_get_regs_len(struct net_device *netdev)
376{ 376{
377#define E1000_REGS_LEN 32 377#define E1000_REGS_LEN 32
378 return E1000_REGS_LEN * sizeof(uint32_t); 378 return E1000_REGS_LEN * sizeof(u32);
379} 379}
380 380
381static void 381static void
@@ -384,10 +384,10 @@ e1000_get_regs(struct net_device *netdev,
384{ 384{
385 struct e1000_adapter *adapter = netdev_priv(netdev); 385 struct e1000_adapter *adapter = netdev_priv(netdev);
386 struct e1000_hw *hw = &adapter->hw; 386 struct e1000_hw *hw = &adapter->hw;
387 uint32_t *regs_buff = p; 387 u32 *regs_buff = p;
388 uint16_t phy_data; 388 u16 phy_data;
389 389
390 memset(p, 0, E1000_REGS_LEN * sizeof(uint32_t)); 390 memset(p, 0, E1000_REGS_LEN * sizeof(u32));
391 391
392 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 392 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
393 393
@@ -412,44 +412,44 @@ e1000_get_regs(struct net_device *netdev,
412 IGP01E1000_PHY_AGC_A); 412 IGP01E1000_PHY_AGC_A);
413 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A & 413 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &
414 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 414 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
415 regs_buff[13] = (uint32_t)phy_data; /* cable length */ 415 regs_buff[13] = (u32)phy_data; /* cable length */
416 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 416 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
417 IGP01E1000_PHY_AGC_B); 417 IGP01E1000_PHY_AGC_B);
418 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B & 418 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B &
419 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 419 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
420 regs_buff[14] = (uint32_t)phy_data; /* cable length */ 420 regs_buff[14] = (u32)phy_data; /* cable length */
421 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 421 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
422 IGP01E1000_PHY_AGC_C); 422 IGP01E1000_PHY_AGC_C);
423 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C & 423 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C &
424 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 424 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
425 regs_buff[15] = (uint32_t)phy_data; /* cable length */ 425 regs_buff[15] = (u32)phy_data; /* cable length */
426 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 426 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
427 IGP01E1000_PHY_AGC_D); 427 IGP01E1000_PHY_AGC_D);
428 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D & 428 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D &
429 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 429 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
430 regs_buff[16] = (uint32_t)phy_data; /* cable length */ 430 regs_buff[16] = (u32)phy_data; /* cable length */
431 regs_buff[17] = 0; /* extended 10bt distance (not needed) */ 431 regs_buff[17] = 0; /* extended 10bt distance (not needed) */
432 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); 432 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
433 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS & 433 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS &
434 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 434 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
435 regs_buff[18] = (uint32_t)phy_data; /* cable polarity */ 435 regs_buff[18] = (u32)phy_data; /* cable polarity */
436 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 436 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
437 IGP01E1000_PHY_PCS_INIT_REG); 437 IGP01E1000_PHY_PCS_INIT_REG);
438 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG & 438 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
439 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 439 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
440 regs_buff[19] = (uint32_t)phy_data; /* cable polarity */ 440 regs_buff[19] = (u32)phy_data; /* cable polarity */
441 regs_buff[20] = 0; /* polarity correction enabled (always) */ 441 regs_buff[20] = 0; /* polarity correction enabled (always) */
442 regs_buff[22] = 0; /* phy receive errors (unavailable) */ 442 regs_buff[22] = 0; /* phy receive errors (unavailable) */
443 regs_buff[23] = regs_buff[18]; /* mdix mode */ 443 regs_buff[23] = regs_buff[18]; /* mdix mode */
444 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); 444 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
445 } else { 445 } else {
446 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 446 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
447 regs_buff[13] = (uint32_t)phy_data; /* cable length */ 447 regs_buff[13] = (u32)phy_data; /* cable length */
448 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 448 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
449 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 449 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
450 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 450 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
451 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 451 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
452 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */ 452 regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
453 regs_buff[18] = regs_buff[13]; /* cable polarity */ 453 regs_buff[18] = regs_buff[13]; /* cable polarity */
454 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 454 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
455 regs_buff[20] = regs_buff[17]; /* polarity correction */ 455 regs_buff[20] = regs_buff[17]; /* polarity correction */
@@ -459,7 +459,7 @@ e1000_get_regs(struct net_device *netdev,
459 } 459 }
460 regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */ 460 regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */
461 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 461 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
462 regs_buff[24] = (uint32_t)phy_data; /* phy local receiver status */ 462 regs_buff[24] = (u32)phy_data; /* phy local receiver status */
463 regs_buff[25] = regs_buff[24]; /* phy remote receiver status */ 463 regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
464 if (hw->mac_type >= e1000_82540 && 464 if (hw->mac_type >= e1000_82540 &&
465 hw->mac_type < e1000_82571 && 465 hw->mac_type < e1000_82571 &&
@@ -477,14 +477,14 @@ e1000_get_eeprom_len(struct net_device *netdev)
477 477
478static int 478static int
479e1000_get_eeprom(struct net_device *netdev, 479e1000_get_eeprom(struct net_device *netdev,
480 struct ethtool_eeprom *eeprom, uint8_t *bytes) 480 struct ethtool_eeprom *eeprom, u8 *bytes)
481{ 481{
482 struct e1000_adapter *adapter = netdev_priv(netdev); 482 struct e1000_adapter *adapter = netdev_priv(netdev);
483 struct e1000_hw *hw = &adapter->hw; 483 struct e1000_hw *hw = &adapter->hw;
484 uint16_t *eeprom_buff; 484 u16 *eeprom_buff;
485 int first_word, last_word; 485 int first_word, last_word;
486 int ret_val = 0; 486 int ret_val = 0;
487 uint16_t i; 487 u16 i;
488 488
489 if (eeprom->len == 0) 489 if (eeprom->len == 0)
490 return -EINVAL; 490 return -EINVAL;
@@ -494,7 +494,7 @@ e1000_get_eeprom(struct net_device *netdev,
494 first_word = eeprom->offset >> 1; 494 first_word = eeprom->offset >> 1;
495 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 495 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
496 496
497 eeprom_buff = kmalloc(sizeof(uint16_t) * 497 eeprom_buff = kmalloc(sizeof(u16) *
498 (last_word - first_word + 1), GFP_KERNEL); 498 (last_word - first_word + 1), GFP_KERNEL);
499 if (!eeprom_buff) 499 if (!eeprom_buff)
500 return -ENOMEM; 500 return -ENOMEM;
@@ -514,7 +514,7 @@ e1000_get_eeprom(struct net_device *netdev,
514 for (i = 0; i < last_word - first_word + 1; i++) 514 for (i = 0; i < last_word - first_word + 1; i++)
515 le16_to_cpus(&eeprom_buff[i]); 515 le16_to_cpus(&eeprom_buff[i]);
516 516
517 memcpy(bytes, (uint8_t *)eeprom_buff + (eeprom->offset & 1), 517 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
518 eeprom->len); 518 eeprom->len);
519 kfree(eeprom_buff); 519 kfree(eeprom_buff);
520 520
@@ -523,14 +523,14 @@ e1000_get_eeprom(struct net_device *netdev,
523 523
524static int 524static int
525e1000_set_eeprom(struct net_device *netdev, 525e1000_set_eeprom(struct net_device *netdev,
526 struct ethtool_eeprom *eeprom, uint8_t *bytes) 526 struct ethtool_eeprom *eeprom, u8 *bytes)
527{ 527{
528 struct e1000_adapter *adapter = netdev_priv(netdev); 528 struct e1000_adapter *adapter = netdev_priv(netdev);
529 struct e1000_hw *hw = &adapter->hw; 529 struct e1000_hw *hw = &adapter->hw;
530 uint16_t *eeprom_buff; 530 u16 *eeprom_buff;
531 void *ptr; 531 void *ptr;
532 int max_len, first_word, last_word, ret_val = 0; 532 int max_len, first_word, last_word, ret_val = 0;
533 uint16_t i; 533 u16 i;
534 534
535 if (eeprom->len == 0) 535 if (eeprom->len == 0)
536 return -EOPNOTSUPP; 536 return -EOPNOTSUPP;
@@ -590,7 +590,7 @@ e1000_get_drvinfo(struct net_device *netdev,
590{ 590{
591 struct e1000_adapter *adapter = netdev_priv(netdev); 591 struct e1000_adapter *adapter = netdev_priv(netdev);
592 char firmware_version[32]; 592 char firmware_version[32];
593 uint16_t eeprom_data; 593 u16 eeprom_data;
594 594
595 strncpy(drvinfo->driver, e1000_driver_name, 32); 595 strncpy(drvinfo->driver, e1000_driver_name, 32);
596 strncpy(drvinfo->version, e1000_driver_version, 32); 596 strncpy(drvinfo->version, e1000_driver_version, 32);
@@ -674,13 +674,13 @@ e1000_set_ringparam(struct net_device *netdev,
674 adapter->tx_ring = txdr; 674 adapter->tx_ring = txdr;
675 adapter->rx_ring = rxdr; 675 adapter->rx_ring = rxdr;
676 676
677 rxdr->count = max(ring->rx_pending,(uint32_t)E1000_MIN_RXD); 677 rxdr->count = max(ring->rx_pending,(u32)E1000_MIN_RXD);
678 rxdr->count = min(rxdr->count,(uint32_t)(mac_type < e1000_82544 ? 678 rxdr->count = min(rxdr->count,(u32)(mac_type < e1000_82544 ?
679 E1000_MAX_RXD : E1000_MAX_82544_RXD)); 679 E1000_MAX_RXD : E1000_MAX_82544_RXD));
680 rxdr->count = ALIGN(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE); 680 rxdr->count = ALIGN(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
681 681
682 txdr->count = max(ring->tx_pending,(uint32_t)E1000_MIN_TXD); 682 txdr->count = max(ring->tx_pending,(u32)E1000_MIN_TXD);
683 txdr->count = min(txdr->count,(uint32_t)(mac_type < e1000_82544 ? 683 txdr->count = min(txdr->count,(u32)(mac_type < e1000_82544 ?
684 E1000_MAX_TXD : E1000_MAX_82544_TXD)); 684 E1000_MAX_TXD : E1000_MAX_82544_TXD));
685 txdr->count = ALIGN(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE); 685 txdr->count = ALIGN(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
686 686
@@ -728,13 +728,13 @@ err_setup:
728 return err; 728 return err;
729} 729}
730 730
731static bool reg_pattern_test(struct e1000_adapter *adapter, uint64_t *data, 731static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
732 int reg, uint32_t mask, uint32_t write) 732 int reg, u32 mask, u32 write)
733{ 733{
734 static const uint32_t test[] = 734 static const u32 test[] =
735 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 735 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
736 uint8_t __iomem *address = adapter->hw.hw_addr + reg; 736 u8 __iomem *address = adapter->hw.hw_addr + reg;
737 uint32_t read; 737 u32 read;
738 int i; 738 int i;
739 739
740 for (i = 0; i < ARRAY_SIZE(test); i++) { 740 for (i = 0; i < ARRAY_SIZE(test); i++) {
@@ -751,11 +751,11 @@ static bool reg_pattern_test(struct e1000_adapter *adapter, uint64_t *data,
751 return false; 751 return false;
752} 752}
753 753
754static bool reg_set_and_check(struct e1000_adapter *adapter, uint64_t *data, 754static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
755 int reg, uint32_t mask, uint32_t write) 755 int reg, u32 mask, u32 write)
756{ 756{
757 uint8_t __iomem *address = adapter->hw.hw_addr + reg; 757 u8 __iomem *address = adapter->hw.hw_addr + reg;
758 uint32_t read; 758 u32 read;
759 759
760 writel(write & mask, address); 760 writel(write & mask, address);
761 read = readl(address); 761 read = readl(address);
@@ -788,10 +788,10 @@ static bool reg_set_and_check(struct e1000_adapter *adapter, uint64_t *data,
788 } while (0) 788 } while (0)
789 789
790static int 790static int
791e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data) 791e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
792{ 792{
793 uint32_t value, before, after; 793 u32 value, before, after;
794 uint32_t i, toggle; 794 u32 i, toggle;
795 795
796 /* The status register is Read Only, so a write should fail. 796 /* The status register is Read Only, so a write should fail.
797 * Some bits that get toggled are ignored. 797 * Some bits that get toggled are ignored.
@@ -884,11 +884,11 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
884} 884}
885 885
886static int 886static int
887e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data) 887e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
888{ 888{
889 uint16_t temp; 889 u16 temp;
890 uint16_t checksum = 0; 890 u16 checksum = 0;
891 uint16_t i; 891 u16 i;
892 892
893 *data = 0; 893 *data = 0;
894 /* Read and add up the contents of the EEPROM */ 894 /* Read and add up the contents of the EEPROM */
@@ -901,7 +901,7 @@ e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
901 } 901 }
902 902
903 /* If Checksum is not Correct return error else test passed */ 903 /* If Checksum is not Correct return error else test passed */
904 if ((checksum != (uint16_t) EEPROM_SUM) && !(*data)) 904 if ((checksum != (u16) EEPROM_SUM) && !(*data))
905 *data = 2; 905 *data = 2;
906 906
907 return *data; 907 return *data;
@@ -919,12 +919,12 @@ e1000_test_intr(int irq, void *data)
919} 919}
920 920
921static int 921static int
922e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data) 922e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
923{ 923{
924 struct net_device *netdev = adapter->netdev; 924 struct net_device *netdev = adapter->netdev;
925 uint32_t mask, i = 0; 925 u32 mask, i = 0;
926 bool shared_int = true; 926 bool shared_int = true;
927 uint32_t irq = adapter->pdev->irq; 927 u32 irq = adapter->pdev->irq;
928 928
929 *data = 0; 929 *data = 0;
930 930
@@ -1070,7 +1070,7 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
1070 struct e1000_tx_ring *txdr = &adapter->test_tx_ring; 1070 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1071 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring; 1071 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
1072 struct pci_dev *pdev = adapter->pdev; 1072 struct pci_dev *pdev = adapter->pdev;
1073 uint32_t rctl; 1073 u32 rctl;
1074 int i, ret_val; 1074 int i, ret_val;
1075 1075
1076 /* Setup Tx descriptor ring and Tx buffers */ 1076 /* Setup Tx descriptor ring and Tx buffers */
@@ -1096,8 +1096,8 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
1096 txdr->next_to_use = txdr->next_to_clean = 0; 1096 txdr->next_to_use = txdr->next_to_clean = 0;
1097 1097
1098 E1000_WRITE_REG(&adapter->hw, TDBAL, 1098 E1000_WRITE_REG(&adapter->hw, TDBAL,
1099 ((uint64_t) txdr->dma & 0x00000000FFFFFFFF)); 1099 ((u64) txdr->dma & 0x00000000FFFFFFFF));
1100 E1000_WRITE_REG(&adapter->hw, TDBAH, ((uint64_t) txdr->dma >> 32)); 1100 E1000_WRITE_REG(&adapter->hw, TDBAH, ((u64) txdr->dma >> 32));
1101 E1000_WRITE_REG(&adapter->hw, TDLEN, 1101 E1000_WRITE_REG(&adapter->hw, TDLEN,
1102 txdr->count * sizeof(struct e1000_tx_desc)); 1102 txdr->count * sizeof(struct e1000_tx_desc));
1103 E1000_WRITE_REG(&adapter->hw, TDH, 0); 1103 E1000_WRITE_REG(&adapter->hw, TDH, 0);
@@ -1153,8 +1153,8 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
1153 rctl = E1000_READ_REG(&adapter->hw, RCTL); 1153 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1154 E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN); 1154 E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
1155 E1000_WRITE_REG(&adapter->hw, RDBAL, 1155 E1000_WRITE_REG(&adapter->hw, RDBAL,
1156 ((uint64_t) rxdr->dma & 0xFFFFFFFF)); 1156 ((u64) rxdr->dma & 0xFFFFFFFF));
1157 E1000_WRITE_REG(&adapter->hw, RDBAH, ((uint64_t) rxdr->dma >> 32)); 1157 E1000_WRITE_REG(&adapter->hw, RDBAH, ((u64) rxdr->dma >> 32));
1158 E1000_WRITE_REG(&adapter->hw, RDLEN, rxdr->size); 1158 E1000_WRITE_REG(&adapter->hw, RDLEN, rxdr->size);
1159 E1000_WRITE_REG(&adapter->hw, RDH, 0); 1159 E1000_WRITE_REG(&adapter->hw, RDH, 0);
1160 E1000_WRITE_REG(&adapter->hw, RDT, 0); 1160 E1000_WRITE_REG(&adapter->hw, RDT, 0);
@@ -1202,7 +1202,7 @@ e1000_phy_disable_receiver(struct e1000_adapter *adapter)
1202static void 1202static void
1203e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter) 1203e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
1204{ 1204{
1205 uint16_t phy_reg; 1205 u16 phy_reg;
1206 1206
1207 /* Because we reset the PHY above, we need to re-force TX_CLK in the 1207 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1208 * Extended PHY Specific Control Register to 25MHz clock. This 1208 * Extended PHY Specific Control Register to 25MHz clock. This
@@ -1226,8 +1226,8 @@ e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
1226static int 1226static int
1227e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter) 1227e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
1228{ 1228{
1229 uint32_t ctrl_reg; 1229 u32 ctrl_reg;
1230 uint16_t phy_reg; 1230 u16 phy_reg;
1231 1231
1232 /* Setup the Device Control Register for PHY loopback test. */ 1232 /* Setup the Device Control Register for PHY loopback test. */
1233 1233
@@ -1293,8 +1293,8 @@ e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
1293static int 1293static int
1294e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 1294e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1295{ 1295{
1296 uint32_t ctrl_reg = 0; 1296 u32 ctrl_reg = 0;
1297 uint32_t stat_reg = 0; 1297 u32 stat_reg = 0;
1298 1298
1299 adapter->hw.autoneg = false; 1299 adapter->hw.autoneg = false;
1300 1300
@@ -1363,8 +1363,8 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1363static int 1363static int
1364e1000_set_phy_loopback(struct e1000_adapter *adapter) 1364e1000_set_phy_loopback(struct e1000_adapter *adapter)
1365{ 1365{
1366 uint16_t phy_reg = 0; 1366 u16 phy_reg = 0;
1367 uint16_t count = 0; 1367 u16 count = 0;
1368 1368
1369 switch (adapter->hw.mac_type) { 1369 switch (adapter->hw.mac_type) {
1370 case e1000_82543: 1370 case e1000_82543:
@@ -1416,7 +1416,7 @@ static int
1416e1000_setup_loopback_test(struct e1000_adapter *adapter) 1416e1000_setup_loopback_test(struct e1000_adapter *adapter)
1417{ 1417{
1418 struct e1000_hw *hw = &adapter->hw; 1418 struct e1000_hw *hw = &adapter->hw;
1419 uint32_t rctl; 1419 u32 rctl;
1420 1420
1421 if (hw->media_type == e1000_media_type_fiber || 1421 if (hw->media_type == e1000_media_type_fiber ||
1422 hw->media_type == e1000_media_type_internal_serdes) { 1422 hw->media_type == e1000_media_type_internal_serdes) {
@@ -1451,8 +1451,8 @@ static void
1451e1000_loopback_cleanup(struct e1000_adapter *adapter) 1451e1000_loopback_cleanup(struct e1000_adapter *adapter)
1452{ 1452{
1453 struct e1000_hw *hw = &adapter->hw; 1453 struct e1000_hw *hw = &adapter->hw;
1454 uint32_t rctl; 1454 u32 rctl;
1455 uint16_t phy_reg; 1455 u16 phy_reg;
1456 1456
1457 rctl = E1000_READ_REG(hw, RCTL); 1457 rctl = E1000_READ_REG(hw, RCTL);
1458 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1458 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
@@ -1578,7 +1578,7 @@ e1000_run_loopback_test(struct e1000_adapter *adapter)
1578} 1578}
1579 1579
1580static int 1580static int
1581e1000_loopback_test(struct e1000_adapter *adapter, uint64_t *data) 1581e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
1582{ 1582{
1583 /* PHY loopback cannot be performed if SoL/IDER 1583 /* PHY loopback cannot be performed if SoL/IDER
1584 * sessions are active */ 1584 * sessions are active */
@@ -1603,7 +1603,7 @@ out:
1603} 1603}
1604 1604
1605static int 1605static int
1606e1000_link_test(struct e1000_adapter *adapter, uint64_t *data) 1606e1000_link_test(struct e1000_adapter *adapter, u64 *data)
1607{ 1607{
1608 *data = 0; 1608 *data = 0;
1609 if (adapter->hw.media_type == e1000_media_type_internal_serdes) { 1609 if (adapter->hw.media_type == e1000_media_type_internal_serdes) {
@@ -1647,7 +1647,7 @@ e1000_get_sset_count(struct net_device *netdev, int sset)
1647 1647
1648static void 1648static void
1649e1000_diag_test(struct net_device *netdev, 1649e1000_diag_test(struct net_device *netdev,
1650 struct ethtool_test *eth_test, uint64_t *data) 1650 struct ethtool_test *eth_test, u64 *data)
1651{ 1651{
1652 struct e1000_adapter *adapter = netdev_priv(netdev); 1652 struct e1000_adapter *adapter = netdev_priv(netdev);
1653 bool if_running = netif_running(netdev); 1653 bool if_running = netif_running(netdev);
@@ -1657,9 +1657,9 @@ e1000_diag_test(struct net_device *netdev,
1657 /* Offline tests */ 1657 /* Offline tests */
1658 1658
1659 /* save speed, duplex, autoneg settings */ 1659 /* save speed, duplex, autoneg settings */
1660 uint16_t autoneg_advertised = adapter->hw.autoneg_advertised; 1660 u16 autoneg_advertised = adapter->hw.autoneg_advertised;
1661 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex; 1661 u8 forced_speed_duplex = adapter->hw.forced_speed_duplex;
1662 uint8_t autoneg = adapter->hw.autoneg; 1662 u8 autoneg = adapter->hw.autoneg;
1663 1663
1664 DPRINTK(HW, INFO, "offline testing starting\n"); 1664 DPRINTK(HW, INFO, "offline testing starting\n");
1665 1665
@@ -1877,7 +1877,7 @@ e1000_led_blink_callback(unsigned long data)
1877} 1877}
1878 1878
1879static int 1879static int
1880e1000_phys_id(struct net_device *netdev, uint32_t data) 1880e1000_phys_id(struct net_device *netdev, u32 data)
1881{ 1881{
1882 struct e1000_adapter *adapter = netdev_priv(netdev); 1882 struct e1000_adapter *adapter = netdev_priv(netdev);
1883 1883
@@ -1927,7 +1927,7 @@ e1000_nway_reset(struct net_device *netdev)
1927 1927
1928static void 1928static void
1929e1000_get_ethtool_stats(struct net_device *netdev, 1929e1000_get_ethtool_stats(struct net_device *netdev,
1930 struct ethtool_stats *stats, uint64_t *data) 1930 struct ethtool_stats *stats, u64 *data)
1931{ 1931{
1932 struct e1000_adapter *adapter = netdev_priv(netdev); 1932 struct e1000_adapter *adapter = netdev_priv(netdev);
1933 int i; 1933 int i;
@@ -1936,15 +1936,15 @@ e1000_get_ethtool_stats(struct net_device *netdev,
1936 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { 1936 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1937 char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset; 1937 char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
1938 data[i] = (e1000_gstrings_stats[i].sizeof_stat == 1938 data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
1939 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; 1939 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1940 } 1940 }
1941/* BUG_ON(i != E1000_STATS_LEN); */ 1941/* BUG_ON(i != E1000_STATS_LEN); */
1942} 1942}
1943 1943
1944static void 1944static void
1945e1000_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data) 1945e1000_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1946{ 1946{
1947 uint8_t *p = data; 1947 u8 *p = data;
1948 int i; 1948 int i;
1949 1949
1950 switch (stringset) { 1950 switch (stringset) {
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index b64203458e9a..9a4b6cbddf2c 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -33,107 +33,107 @@
33 33
34#include "e1000_hw.h" 34#include "e1000_hw.h"
35 35
36static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
38static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); 38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
39static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
40static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); 40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw); 41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42 42
43static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); 43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static int32_t e1000_check_downshift(struct e1000_hw *hw); 44static s32 e1000_check_downshift(struct e1000_hw *hw);
45static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); 45static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 46static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw); 47static void e1000_clear_vfta(struct e1000_hw *hw);
48static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); 48static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
49static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, 49static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
50 bool link_up); 50 bool link_up);
51static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); 51static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
52static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); 52static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
53static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); 53static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
54static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); 54static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
55static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); 55static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, u16 *max_length);
56static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); 56static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
57static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); 57static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
58static int32_t e1000_get_software_flag(struct e1000_hw *hw); 58static s32 e1000_get_software_flag(struct e1000_hw *hw);
59static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); 59static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
60static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); 60static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
61static int32_t e1000_id_led_init(struct e1000_hw *hw); 61static s32 e1000_id_led_init(struct e1000_hw *hw);
62static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); 62static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, u32 cnf_base_addr, u32 cnf_size);
63static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); 63static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
64static void e1000_init_rx_addrs(struct e1000_hw *hw); 64static void e1000_init_rx_addrs(struct e1000_hw *hw);
65static void e1000_initialize_hardware_bits(struct e1000_hw *hw); 65static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
66static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); 66static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
67static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); 67static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
68static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); 68static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
69static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); 69static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum);
70static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); 70static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
71static int32_t e1000_mng_write_commit(struct e1000_hw *hw); 71static s32 e1000_mng_write_commit(struct e1000_hw *hw);
72static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 72static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 73static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
74static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 74static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
75static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 75static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
76static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); 76static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
77static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 77static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
78static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 78static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
79static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); 79static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
80static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); 80static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
81static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); 81static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
82static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); 82static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
83static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); 83static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 *data);
84static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); 84static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 data);
85static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 85static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
86static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 86static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
87static void e1000_release_software_flag(struct e1000_hw *hw); 87static void e1000_release_software_flag(struct e1000_hw *hw);
88static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 88static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
89static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); 89static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
90static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); 90static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
91static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); 91static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
92static int32_t e1000_wait_autoneg(struct e1000_hw *hw); 92static s32 e1000_wait_autoneg(struct e1000_hw *hw);
93static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); 93static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
94static int32_t e1000_set_phy_type(struct e1000_hw *hw); 94static s32 e1000_set_phy_type(struct e1000_hw *hw);
95static void e1000_phy_init_script(struct e1000_hw *hw); 95static void e1000_phy_init_script(struct e1000_hw *hw);
96static int32_t e1000_setup_copper_link(struct e1000_hw *hw); 96static s32 e1000_setup_copper_link(struct e1000_hw *hw);
97static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 97static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
98static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 98static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
99static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); 99static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
100static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); 100static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
101static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); 101static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
102static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); 102static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
103static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, 103static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
104 uint16_t count); 104 u16 count);
105static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); 105static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
106static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); 106static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
107static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, 107static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
108 uint16_t words, uint16_t *data); 108 u16 words, u16 *data);
109static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, 109static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw,
110 uint16_t offset, uint16_t words, 110 u16 offset, u16 words,
111 uint16_t *data); 111 u16 *data);
112static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); 112static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
113static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 113static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
114static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 114static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
115static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, 115static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data,
116 uint16_t count); 116 u16 count);
117static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 117static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
118 uint16_t phy_data); 118 u16 phy_data);
119static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, 119static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
120 uint16_t *phy_data); 120 u16 *phy_data);
121static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); 121static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
122static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 122static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
123static void e1000_release_eeprom(struct e1000_hw *hw); 123static void e1000_release_eeprom(struct e1000_hw *hw);
124static void e1000_standby_eeprom(struct e1000_hw *hw); 124static void e1000_standby_eeprom(struct e1000_hw *hw);
125static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 125static s32 e1000_set_vco_speed(struct e1000_hw *hw);
126static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 126static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
127static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 127static s32 e1000_set_phy_mode(struct e1000_hw *hw);
128static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); 128static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
129static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); 129static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
130static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, 130static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
131 uint16_t duplex); 131 u16 duplex);
132static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 132static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
133 133
134/* IGP cable length table */ 134/* IGP cable length table */
135static const 135static const
136uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 136u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
137 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 137 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
138 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 138 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
139 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 139 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
@@ -144,7 +144,7 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
145 145
146static const 146static const
147uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 147u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
148 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 148 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
149 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 149 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
150 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 150 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
@@ -159,7 +159,7 @@ uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
159 * 159 *
160 * hw - Struct containing variables accessed by shared code 160 * hw - Struct containing variables accessed by shared code
161 *****************************************************************************/ 161 *****************************************************************************/
162static int32_t 162static s32
163e1000_set_phy_type(struct e1000_hw *hw) 163e1000_set_phy_type(struct e1000_hw *hw)
164{ 164{
165 DEBUGFUNC("e1000_set_phy_type"); 165 DEBUGFUNC("e1000_set_phy_type");
@@ -213,8 +213,8 @@ e1000_set_phy_type(struct e1000_hw *hw)
213static void 213static void
214e1000_phy_init_script(struct e1000_hw *hw) 214e1000_phy_init_script(struct e1000_hw *hw)
215{ 215{
216 uint32_t ret_val; 216 u32 ret_val;
217 uint16_t phy_saved_data; 217 u16 phy_saved_data;
218 218
219 DEBUGFUNC("e1000_phy_init_script"); 219 DEBUGFUNC("e1000_phy_init_script");
220 220
@@ -272,7 +272,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
273 273
274 if (hw->mac_type == e1000_82547) { 274 if (hw->mac_type == e1000_82547) {
275 uint16_t fused, fine, coarse; 275 u16 fused, fine, coarse;
276 276
277 /* Move to analog registers page */ 277 /* Move to analog registers page */
278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
@@ -306,7 +306,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
306 * 306 *
307 * hw - Struct containing variables accessed by shared code 307 * hw - Struct containing variables accessed by shared code
308 *****************************************************************************/ 308 *****************************************************************************/
309int32_t 309s32
310e1000_set_mac_type(struct e1000_hw *hw) 310e1000_set_mac_type(struct e1000_hw *hw)
311{ 311{
312 DEBUGFUNC("e1000_set_mac_type"); 312 DEBUGFUNC("e1000_set_mac_type");
@@ -477,7 +477,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
477void 477void
478e1000_set_media_type(struct e1000_hw *hw) 478e1000_set_media_type(struct e1000_hw *hw)
479{ 479{
480 uint32_t status; 480 u32 status;
481 481
482 DEBUGFUNC("e1000_set_media_type"); 482 DEBUGFUNC("e1000_set_media_type");
483 483
@@ -528,17 +528,17 @@ e1000_set_media_type(struct e1000_hw *hw)
528 * 528 *
529 * hw - Struct containing variables accessed by shared code 529 * hw - Struct containing variables accessed by shared code
530 *****************************************************************************/ 530 *****************************************************************************/
531int32_t 531s32
532e1000_reset_hw(struct e1000_hw *hw) 532e1000_reset_hw(struct e1000_hw *hw)
533{ 533{
534 uint32_t ctrl; 534 u32 ctrl;
535 uint32_t ctrl_ext; 535 u32 ctrl_ext;
536 uint32_t icr; 536 u32 icr;
537 uint32_t manc; 537 u32 manc;
538 uint32_t led_ctrl; 538 u32 led_ctrl;
539 uint32_t timeout; 539 u32 timeout;
540 uint32_t extcnf_ctrl; 540 u32 extcnf_ctrl;
541 int32_t ret_val; 541 s32 ret_val;
542 542
543 DEBUGFUNC("e1000_reset_hw"); 543 DEBUGFUNC("e1000_reset_hw");
544 544
@@ -730,7 +730,7 @@ e1000_reset_hw(struct e1000_hw *hw)
730 } 730 }
731 731
732 if (hw->mac_type == e1000_ich8lan) { 732 if (hw->mac_type == e1000_ich8lan) {
733 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 733 u32 kab = E1000_READ_REG(hw, KABGTXD);
734 kab |= E1000_KABGTXD_BGSQLBIAS; 734 kab |= E1000_KABGTXD_BGSQLBIAS;
735 E1000_WRITE_REG(hw, KABGTXD, kab); 735 E1000_WRITE_REG(hw, KABGTXD, kab);
736 } 736 }
@@ -752,10 +752,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
752{ 752{
753 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { 753 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
754 /* Settings common to all PCI-express silicon */ 754 /* Settings common to all PCI-express silicon */
755 uint32_t reg_ctrl, reg_ctrl_ext; 755 u32 reg_ctrl, reg_ctrl_ext;
756 uint32_t reg_tarc0, reg_tarc1; 756 u32 reg_tarc0, reg_tarc1;
757 uint32_t reg_tctl; 757 u32 reg_tctl;
758 uint32_t reg_txdctl, reg_txdctl1; 758 u32 reg_txdctl, reg_txdctl1;
759 759
760 /* link autonegotiation/sync workarounds */ 760 /* link autonegotiation/sync workarounds */
761 reg_tarc0 = E1000_READ_REG(hw, TARC0); 761 reg_tarc0 = E1000_READ_REG(hw, TARC0);
@@ -866,15 +866,15 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
866 * configuration and flow control settings. Clears all on-chip counters. Leaves 866 * configuration and flow control settings. Clears all on-chip counters. Leaves
867 * the transmit and receive units disabled and uninitialized. 867 * the transmit and receive units disabled and uninitialized.
868 *****************************************************************************/ 868 *****************************************************************************/
869int32_t 869s32
870e1000_init_hw(struct e1000_hw *hw) 870e1000_init_hw(struct e1000_hw *hw)
871{ 871{
872 uint32_t ctrl; 872 u32 ctrl;
873 uint32_t i; 873 u32 i;
874 int32_t ret_val; 874 s32 ret_val;
875 uint32_t mta_size; 875 u32 mta_size;
876 uint32_t reg_data; 876 u32 reg_data;
877 uint32_t ctrl_ext; 877 u32 ctrl_ext;
878 878
879 DEBUGFUNC("e1000_init_hw"); 879 DEBUGFUNC("e1000_init_hw");
880 880
@@ -1020,7 +1020,7 @@ e1000_init_hw(struct e1000_hw *hw)
1020 1020
1021 1021
1022 if (hw->mac_type == e1000_82573) { 1022 if (hw->mac_type == e1000_82573) {
1023 uint32_t gcr = E1000_READ_REG(hw, GCR); 1023 u32 gcr = E1000_READ_REG(hw, GCR);
1024 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1024 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1025 E1000_WRITE_REG(hw, GCR, gcr); 1025 E1000_WRITE_REG(hw, GCR, gcr);
1026 } 1026 }
@@ -1054,11 +1054,11 @@ e1000_init_hw(struct e1000_hw *hw)
1054 * 1054 *
1055 * hw - Struct containing variables accessed by shared code. 1055 * hw - Struct containing variables accessed by shared code.
1056 *****************************************************************************/ 1056 *****************************************************************************/
1057static int32_t 1057static s32
1058e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 1058e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1059{ 1059{
1060 uint16_t eeprom_data; 1060 u16 eeprom_data;
1061 int32_t ret_val; 1061 s32 ret_val;
1062 1062
1063 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 1063 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1064 1064
@@ -1100,12 +1100,12 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1100 * established. Assumes the hardware has previously been reset and the 1100 * established. Assumes the hardware has previously been reset and the
1101 * transmitter and receiver are not enabled. 1101 * transmitter and receiver are not enabled.
1102 *****************************************************************************/ 1102 *****************************************************************************/
1103int32_t 1103s32
1104e1000_setup_link(struct e1000_hw *hw) 1104e1000_setup_link(struct e1000_hw *hw)
1105{ 1105{
1106 uint32_t ctrl_ext; 1106 u32 ctrl_ext;
1107 int32_t ret_val; 1107 s32 ret_val;
1108 uint16_t eeprom_data; 1108 u16 eeprom_data;
1109 1109
1110 DEBUGFUNC("e1000_setup_link"); 1110 DEBUGFUNC("e1000_setup_link");
1111 1111
@@ -1233,15 +1233,15 @@ e1000_setup_link(struct e1000_hw *hw)
1233 * link. Assumes the hardware has been previously reset and the transmitter 1233 * link. Assumes the hardware has been previously reset and the transmitter
1234 * and receiver are not enabled. 1234 * and receiver are not enabled.
1235 *****************************************************************************/ 1235 *****************************************************************************/
1236static int32_t 1236static s32
1237e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 1237e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1238{ 1238{
1239 uint32_t ctrl; 1239 u32 ctrl;
1240 uint32_t status; 1240 u32 status;
1241 uint32_t txcw = 0; 1241 u32 txcw = 0;
1242 uint32_t i; 1242 u32 i;
1243 uint32_t signal = 0; 1243 u32 signal = 0;
1244 int32_t ret_val; 1244 s32 ret_val;
1245 1245
1246 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 1246 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1247 1247
@@ -1380,12 +1380,12 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1380* 1380*
1381* hw - Struct containing variables accessed by shared code 1381* hw - Struct containing variables accessed by shared code
1382******************************************************************************/ 1382******************************************************************************/
1383static int32_t 1383static s32
1384e1000_copper_link_preconfig(struct e1000_hw *hw) 1384e1000_copper_link_preconfig(struct e1000_hw *hw)
1385{ 1385{
1386 uint32_t ctrl; 1386 u32 ctrl;
1387 int32_t ret_val; 1387 s32 ret_val;
1388 uint16_t phy_data; 1388 u16 phy_data;
1389 1389
1390 DEBUGFUNC("e1000_copper_link_preconfig"); 1390 DEBUGFUNC("e1000_copper_link_preconfig");
1391 1391
@@ -1440,12 +1440,12 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1440* 1440*
1441* hw - Struct containing variables accessed by shared code 1441* hw - Struct containing variables accessed by shared code
1442*********************************************************************/ 1442*********************************************************************/
1443static int32_t 1443static s32
1444e1000_copper_link_igp_setup(struct e1000_hw *hw) 1444e1000_copper_link_igp_setup(struct e1000_hw *hw)
1445{ 1445{
1446 uint32_t led_ctrl; 1446 u32 led_ctrl;
1447 int32_t ret_val; 1447 s32 ret_val;
1448 uint16_t phy_data; 1448 u16 phy_data;
1449 1449
1450 DEBUGFUNC("e1000_copper_link_igp_setup"); 1450 DEBUGFUNC("e1000_copper_link_igp_setup");
1451 1451
@@ -1587,12 +1587,12 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1587* 1587*
1588* hw - Struct containing variables accessed by shared code 1588* hw - Struct containing variables accessed by shared code
1589*********************************************************************/ 1589*********************************************************************/
1590static int32_t 1590static s32
1591e1000_copper_link_ggp_setup(struct e1000_hw *hw) 1591e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1592{ 1592{
1593 int32_t ret_val; 1593 s32 ret_val;
1594 uint16_t phy_data; 1594 u16 phy_data;
1595 uint32_t reg_data; 1595 u32 reg_data;
1596 1596
1597 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1597 DEBUGFUNC("e1000_copper_link_ggp_setup");
1598 1598
@@ -1735,11 +1735,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1735* 1735*
1736* hw - Struct containing variables accessed by shared code 1736* hw - Struct containing variables accessed by shared code
1737*********************************************************************/ 1737*********************************************************************/
1738static int32_t 1738static s32
1739e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1739e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1740{ 1740{
1741 int32_t ret_val; 1741 s32 ret_val;
1742 uint16_t phy_data; 1742 u16 phy_data;
1743 1743
1744 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1744 DEBUGFUNC("e1000_copper_link_mgp_setup");
1745 1745
@@ -1839,11 +1839,11 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1839* 1839*
1840* hw - Struct containing variables accessed by shared code 1840* hw - Struct containing variables accessed by shared code
1841*********************************************************************/ 1841*********************************************************************/
1842static int32_t 1842static s32
1843e1000_copper_link_autoneg(struct e1000_hw *hw) 1843e1000_copper_link_autoneg(struct e1000_hw *hw)
1844{ 1844{
1845 int32_t ret_val; 1845 s32 ret_val;
1846 uint16_t phy_data; 1846 u16 phy_data;
1847 1847
1848 DEBUGFUNC("e1000_copper_link_autoneg"); 1848 DEBUGFUNC("e1000_copper_link_autoneg");
1849 1849
@@ -1910,10 +1910,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1910* 1910*
1911* hw - Struct containing variables accessed by shared code 1911* hw - Struct containing variables accessed by shared code
1912******************************************************************************/ 1912******************************************************************************/
1913static int32_t 1913static s32
1914e1000_copper_link_postconfig(struct e1000_hw *hw) 1914e1000_copper_link_postconfig(struct e1000_hw *hw)
1915{ 1915{
1916 int32_t ret_val; 1916 s32 ret_val;
1917 DEBUGFUNC("e1000_copper_link_postconfig"); 1917 DEBUGFUNC("e1000_copper_link_postconfig");
1918 1918
1919 if (hw->mac_type >= e1000_82544) { 1919 if (hw->mac_type >= e1000_82544) {
@@ -1948,13 +1948,13 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
1948* 1948*
1949* hw - Struct containing variables accessed by shared code 1949* hw - Struct containing variables accessed by shared code
1950******************************************************************************/ 1950******************************************************************************/
1951static int32_t 1951static s32
1952e1000_setup_copper_link(struct e1000_hw *hw) 1952e1000_setup_copper_link(struct e1000_hw *hw)
1953{ 1953{
1954 int32_t ret_val; 1954 s32 ret_val;
1955 uint16_t i; 1955 u16 i;
1956 uint16_t phy_data; 1956 u16 phy_data;
1957 uint16_t reg_data; 1957 u16 reg_data;
1958 1958
1959 DEBUGFUNC("e1000_setup_copper_link"); 1959 DEBUGFUNC("e1000_setup_copper_link");
1960 1960
@@ -2062,12 +2062,12 @@ e1000_setup_copper_link(struct e1000_hw *hw)
2062* 2062*
2063* hw - Struct containing variables accessed by shared code 2063* hw - Struct containing variables accessed by shared code
2064******************************************************************************/ 2064******************************************************************************/
2065static int32_t 2065static s32
2066e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 2066e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2067{ 2067{
2068 int32_t ret_val = E1000_SUCCESS; 2068 s32 ret_val = E1000_SUCCESS;
2069 uint32_t tipg; 2069 u32 tipg;
2070 uint16_t reg_data; 2070 u16 reg_data;
2071 2071
2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2073 2073
@@ -2098,12 +2098,12 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2098 return ret_val; 2098 return ret_val;
2099} 2099}
2100 2100
2101static int32_t 2101static s32
2102e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 2102e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2103{ 2103{
2104 int32_t ret_val = E1000_SUCCESS; 2104 s32 ret_val = E1000_SUCCESS;
2105 uint16_t reg_data; 2105 u16 reg_data;
2106 uint32_t tipg; 2106 u32 tipg;
2107 2107
2108 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 2108 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2109 2109
@@ -2135,12 +2135,12 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2135* 2135*
2136* hw - Struct containing variables accessed by shared code 2136* hw - Struct containing variables accessed by shared code
2137******************************************************************************/ 2137******************************************************************************/
2138int32_t 2138s32
2139e1000_phy_setup_autoneg(struct e1000_hw *hw) 2139e1000_phy_setup_autoneg(struct e1000_hw *hw)
2140{ 2140{
2141 int32_t ret_val; 2141 s32 ret_val;
2142 uint16_t mii_autoneg_adv_reg; 2142 u16 mii_autoneg_adv_reg;
2143 uint16_t mii_1000t_ctrl_reg; 2143 u16 mii_1000t_ctrl_reg;
2144 2144
2145 DEBUGFUNC("e1000_phy_setup_autoneg"); 2145 DEBUGFUNC("e1000_phy_setup_autoneg");
2146 2146
@@ -2284,15 +2284,15 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2284* 2284*
2285* hw - Struct containing variables accessed by shared code 2285* hw - Struct containing variables accessed by shared code
2286******************************************************************************/ 2286******************************************************************************/
2287static int32_t 2287static s32
2288e1000_phy_force_speed_duplex(struct e1000_hw *hw) 2288e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2289{ 2289{
2290 uint32_t ctrl; 2290 u32 ctrl;
2291 int32_t ret_val; 2291 s32 ret_val;
2292 uint16_t mii_ctrl_reg; 2292 u16 mii_ctrl_reg;
2293 uint16_t mii_status_reg; 2293 u16 mii_status_reg;
2294 uint16_t phy_data; 2294 u16 phy_data;
2295 uint16_t i; 2295 u16 i;
2296 2296
2297 DEBUGFUNC("e1000_phy_force_speed_duplex"); 2297 DEBUGFUNC("e1000_phy_force_speed_duplex");
2298 2298
@@ -2538,7 +2538,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2538void 2538void
2539e1000_config_collision_dist(struct e1000_hw *hw) 2539e1000_config_collision_dist(struct e1000_hw *hw)
2540{ 2540{
2541 uint32_t tctl, coll_dist; 2541 u32 tctl, coll_dist;
2542 2542
2543 DEBUGFUNC("e1000_config_collision_dist"); 2543 DEBUGFUNC("e1000_config_collision_dist");
2544 2544
@@ -2565,12 +2565,12 @@ e1000_config_collision_dist(struct e1000_hw *hw)
2565* The contents of the PHY register containing the needed information need to 2565* The contents of the PHY register containing the needed information need to
2566* be passed in. 2566* be passed in.
2567******************************************************************************/ 2567******************************************************************************/
2568static int32_t 2568static s32
2569e1000_config_mac_to_phy(struct e1000_hw *hw) 2569e1000_config_mac_to_phy(struct e1000_hw *hw)
2570{ 2570{
2571 uint32_t ctrl; 2571 u32 ctrl;
2572 int32_t ret_val; 2572 s32 ret_val;
2573 uint16_t phy_data; 2573 u16 phy_data;
2574 2574
2575 DEBUGFUNC("e1000_config_mac_to_phy"); 2575 DEBUGFUNC("e1000_config_mac_to_phy");
2576 2576
@@ -2624,10 +2624,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2624 * by the PHY rather than the MAC. Software must also configure these 2624 * by the PHY rather than the MAC. Software must also configure these
2625 * bits when link is forced on a fiber connection. 2625 * bits when link is forced on a fiber connection.
2626 *****************************************************************************/ 2626 *****************************************************************************/
2627int32_t 2627s32
2628e1000_force_mac_fc(struct e1000_hw *hw) 2628e1000_force_mac_fc(struct e1000_hw *hw)
2629{ 2629{
2630 uint32_t ctrl; 2630 u32 ctrl;
2631 2631
2632 DEBUGFUNC("e1000_force_mac_fc"); 2632 DEBUGFUNC("e1000_force_mac_fc");
2633 2633
@@ -2691,15 +2691,15 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2691 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2691 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2692 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 2692 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2693 *****************************************************************************/ 2693 *****************************************************************************/
2694static int32_t 2694static s32
2695e1000_config_fc_after_link_up(struct e1000_hw *hw) 2695e1000_config_fc_after_link_up(struct e1000_hw *hw)
2696{ 2696{
2697 int32_t ret_val; 2697 s32 ret_val;
2698 uint16_t mii_status_reg; 2698 u16 mii_status_reg;
2699 uint16_t mii_nway_adv_reg; 2699 u16 mii_nway_adv_reg;
2700 uint16_t mii_nway_lp_ability_reg; 2700 u16 mii_nway_lp_ability_reg;
2701 uint16_t speed; 2701 u16 speed;
2702 uint16_t duplex; 2702 u16 duplex;
2703 2703
2704 DEBUGFUNC("e1000_config_fc_after_link_up"); 2704 DEBUGFUNC("e1000_config_fc_after_link_up");
2705 2705
@@ -2896,17 +2896,17 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2896 * 2896 *
2897 * Called by any function that needs to check the link status of the adapter. 2897 * Called by any function that needs to check the link status of the adapter.
2898 *****************************************************************************/ 2898 *****************************************************************************/
2899int32_t 2899s32
2900e1000_check_for_link(struct e1000_hw *hw) 2900e1000_check_for_link(struct e1000_hw *hw)
2901{ 2901{
2902 uint32_t rxcw = 0; 2902 u32 rxcw = 0;
2903 uint32_t ctrl; 2903 u32 ctrl;
2904 uint32_t status; 2904 u32 status;
2905 uint32_t rctl; 2905 u32 rctl;
2906 uint32_t icr; 2906 u32 icr;
2907 uint32_t signal = 0; 2907 u32 signal = 0;
2908 int32_t ret_val; 2908 s32 ret_val;
2909 uint16_t phy_data; 2909 u16 phy_data;
2910 2910
2911 DEBUGFUNC("e1000_check_for_link"); 2911 DEBUGFUNC("e1000_check_for_link");
2912 2912
@@ -3022,7 +3022,7 @@ e1000_check_for_link(struct e1000_hw *hw)
3022 * at gigabit speed, we turn on TBI compatibility. 3022 * at gigabit speed, we turn on TBI compatibility.
3023 */ 3023 */
3024 if (hw->tbi_compatibility_en) { 3024 if (hw->tbi_compatibility_en) {
3025 uint16_t speed, duplex; 3025 u16 speed, duplex;
3026 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 3026 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3027 if (ret_val) { 3027 if (ret_val) {
3028 DEBUGOUT("Error getting link speed and duplex\n"); 3028 DEBUGOUT("Error getting link speed and duplex\n");
@@ -3132,14 +3132,14 @@ e1000_check_for_link(struct e1000_hw *hw)
3132 * speed - Speed of the connection 3132 * speed - Speed of the connection
3133 * duplex - Duplex setting of the connection 3133 * duplex - Duplex setting of the connection
3134 *****************************************************************************/ 3134 *****************************************************************************/
3135int32_t 3135s32
3136e1000_get_speed_and_duplex(struct e1000_hw *hw, 3136e1000_get_speed_and_duplex(struct e1000_hw *hw,
3137 uint16_t *speed, 3137 u16 *speed,
3138 uint16_t *duplex) 3138 u16 *duplex)
3139{ 3139{
3140 uint32_t status; 3140 u32 status;
3141 int32_t ret_val; 3141 s32 ret_val;
3142 uint16_t phy_data; 3142 u16 phy_data;
3143 3143
3144 DEBUGFUNC("e1000_get_speed_and_duplex"); 3144 DEBUGFUNC("e1000_get_speed_and_duplex");
3145 3145
@@ -3214,12 +3214,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3214* 3214*
3215* hw - Struct containing variables accessed by shared code 3215* hw - Struct containing variables accessed by shared code
3216******************************************************************************/ 3216******************************************************************************/
3217static int32_t 3217static s32
3218e1000_wait_autoneg(struct e1000_hw *hw) 3218e1000_wait_autoneg(struct e1000_hw *hw)
3219{ 3219{
3220 int32_t ret_val; 3220 s32 ret_val;
3221 uint16_t i; 3221 u16 i;
3222 uint16_t phy_data; 3222 u16 phy_data;
3223 3223
3224 DEBUGFUNC("e1000_wait_autoneg"); 3224 DEBUGFUNC("e1000_wait_autoneg");
3225 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3225 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
@@ -3251,7 +3251,7 @@ e1000_wait_autoneg(struct e1000_hw *hw)
3251******************************************************************************/ 3251******************************************************************************/
3252static void 3252static void
3253e1000_raise_mdi_clk(struct e1000_hw *hw, 3253e1000_raise_mdi_clk(struct e1000_hw *hw,
3254 uint32_t *ctrl) 3254 u32 *ctrl)
3255{ 3255{
3256 /* Raise the clock input to the Management Data Clock (by setting the MDC 3256 /* Raise the clock input to the Management Data Clock (by setting the MDC
3257 * bit), and then delay 10 microseconds. 3257 * bit), and then delay 10 microseconds.
@@ -3269,7 +3269,7 @@ e1000_raise_mdi_clk(struct e1000_hw *hw,
3269******************************************************************************/ 3269******************************************************************************/
3270static void 3270static void
3271e1000_lower_mdi_clk(struct e1000_hw *hw, 3271e1000_lower_mdi_clk(struct e1000_hw *hw,
3272 uint32_t *ctrl) 3272 u32 *ctrl)
3273{ 3273{
3274 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3274 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3275 * bit), and then delay 10 microseconds. 3275 * bit), and then delay 10 microseconds.
@@ -3290,11 +3290,11 @@ e1000_lower_mdi_clk(struct e1000_hw *hw,
3290******************************************************************************/ 3290******************************************************************************/
3291static void 3291static void
3292e1000_shift_out_mdi_bits(struct e1000_hw *hw, 3292e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3293 uint32_t data, 3293 u32 data,
3294 uint16_t count) 3294 u16 count)
3295{ 3295{
3296 uint32_t ctrl; 3296 u32 ctrl;
3297 uint32_t mask; 3297 u32 mask;
3298 3298
3299 /* We need to shift "count" number of bits out to the PHY. So, the value 3299 /* We need to shift "count" number of bits out to the PHY. So, the value
3300 * in the "data" parameter will be shifted out to the PHY one bit at a 3300 * in the "data" parameter will be shifted out to the PHY one bit at a
@@ -3338,12 +3338,12 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3338* 3338*
3339* Bits are shifted in in MSB to LSB order. 3339* Bits are shifted in in MSB to LSB order.
3340******************************************************************************/ 3340******************************************************************************/
3341static uint16_t 3341static u16
3342e1000_shift_in_mdi_bits(struct e1000_hw *hw) 3342e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3343{ 3343{
3344 uint32_t ctrl; 3344 u32 ctrl;
3345 uint16_t data = 0; 3345 u16 data = 0;
3346 uint8_t i; 3346 u8 i;
3347 3347
3348 /* In order to read a register from the PHY, we need to shift in a total 3348 /* In order to read a register from the PHY, we need to shift in a total
3349 * of 18 bits from the PHY. The first two bit (turnaround) times are used 3349 * of 18 bits from the PHY. The first two bit (turnaround) times are used
@@ -3384,13 +3384,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3384 return data; 3384 return data;
3385} 3385}
3386 3386
3387static int32_t 3387static s32
3388e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 3388e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3389{ 3389{
3390 uint32_t swfw_sync = 0; 3390 u32 swfw_sync = 0;
3391 uint32_t swmask = mask; 3391 u32 swmask = mask;
3392 uint32_t fwmask = mask << 16; 3392 u32 fwmask = mask << 16;
3393 int32_t timeout = 200; 3393 s32 timeout = 200;
3394 3394
3395 DEBUGFUNC("e1000_swfw_sync_acquire"); 3395 DEBUGFUNC("e1000_swfw_sync_acquire");
3396 3396
@@ -3429,10 +3429,10 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3429} 3429}
3430 3430
3431static void 3431static void
3432e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 3432e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3433{ 3433{
3434 uint32_t swfw_sync; 3434 u32 swfw_sync;
3435 uint32_t swmask = mask; 3435 u32 swmask = mask;
3436 3436
3437 DEBUGFUNC("e1000_swfw_sync_release"); 3437 DEBUGFUNC("e1000_swfw_sync_release");
3438 3438
@@ -3464,13 +3464,13 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3464* hw - Struct containing variables accessed by shared code 3464* hw - Struct containing variables accessed by shared code
3465* reg_addr - address of the PHY register to read 3465* reg_addr - address of the PHY register to read
3466******************************************************************************/ 3466******************************************************************************/
3467int32_t 3467s32
3468e1000_read_phy_reg(struct e1000_hw *hw, 3468e1000_read_phy_reg(struct e1000_hw *hw,
3469 uint32_t reg_addr, 3469 u32 reg_addr,
3470 uint16_t *phy_data) 3470 u16 *phy_data)
3471{ 3471{
3472 uint32_t ret_val; 3472 u32 ret_val;
3473 uint16_t swfw; 3473 u16 swfw;
3474 3474
3475 DEBUGFUNC("e1000_read_phy_reg"); 3475 DEBUGFUNC("e1000_read_phy_reg");
3476 3476
@@ -3488,7 +3488,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3488 hw->phy_type == e1000_phy_igp_2) && 3488 hw->phy_type == e1000_phy_igp_2) &&
3489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3490 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3490 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3491 (uint16_t)reg_addr); 3491 (u16)reg_addr);
3492 if (ret_val) { 3492 if (ret_val) {
3493 e1000_swfw_sync_release(hw, swfw); 3493 e1000_swfw_sync_release(hw, swfw);
3494 return ret_val; 3494 return ret_val;
@@ -3499,14 +3499,14 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3499 /* Select Configuration Page */ 3499 /* Select Configuration Page */
3500 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3500 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3501 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3501 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3502 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3502 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3503 } else { 3503 } else {
3504 /* Use Alternative Page Select register to access 3504 /* Use Alternative Page Select register to access
3505 * registers 30 and 31 3505 * registers 30 and 31
3506 */ 3506 */
3507 ret_val = e1000_write_phy_reg_ex(hw, 3507 ret_val = e1000_write_phy_reg_ex(hw,
3508 GG82563_PHY_PAGE_SELECT_ALT, 3508 GG82563_PHY_PAGE_SELECT_ALT,
3509 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3509 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3510 } 3510 }
3511 3511
3512 if (ret_val) { 3512 if (ret_val) {
@@ -3523,13 +3523,13 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3523 return ret_val; 3523 return ret_val;
3524} 3524}
3525 3525
3526static int32_t 3526static s32
3527e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 3527e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3528 uint16_t *phy_data) 3528 u16 *phy_data)
3529{ 3529{
3530 uint32_t i; 3530 u32 i;
3531 uint32_t mdic = 0; 3531 u32 mdic = 0;
3532 const uint32_t phy_addr = 1; 3532 const u32 phy_addr = 1;
3533 3533
3534 DEBUGFUNC("e1000_read_phy_reg_ex"); 3534 DEBUGFUNC("e1000_read_phy_reg_ex");
3535 3535
@@ -3563,7 +3563,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3563 DEBUGOUT("MDI Error\n"); 3563 DEBUGOUT("MDI Error\n");
3564 return -E1000_ERR_PHY; 3564 return -E1000_ERR_PHY;
3565 } 3565 }
3566 *phy_data = (uint16_t) mdic; 3566 *phy_data = (u16) mdic;
3567 } else { 3567 } else {
3568 /* We must first send a preamble through the MDIO pin to signal the 3568 /* We must first send a preamble through the MDIO pin to signal the
3569 * beginning of an MII instruction. This is done by sending 32 3569 * beginning of an MII instruction. This is done by sending 32
@@ -3603,12 +3603,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3603* reg_addr - address of the PHY register to write 3603* reg_addr - address of the PHY register to write
3604* data - data to write to the PHY 3604* data - data to write to the PHY
3605******************************************************************************/ 3605******************************************************************************/
3606int32_t 3606s32
3607e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 3607e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr,
3608 uint16_t phy_data) 3608 u16 phy_data)
3609{ 3609{
3610 uint32_t ret_val; 3610 u32 ret_val;
3611 uint16_t swfw; 3611 u16 swfw;
3612 3612
3613 DEBUGFUNC("e1000_write_phy_reg"); 3613 DEBUGFUNC("e1000_write_phy_reg");
3614 3614
@@ -3626,7 +3626,7 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3626 hw->phy_type == e1000_phy_igp_2) && 3626 hw->phy_type == e1000_phy_igp_2) &&
3627 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3627 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3628 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3628 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3629 (uint16_t)reg_addr); 3629 (u16)reg_addr);
3630 if (ret_val) { 3630 if (ret_val) {
3631 e1000_swfw_sync_release(hw, swfw); 3631 e1000_swfw_sync_release(hw, swfw);
3632 return ret_val; 3632 return ret_val;
@@ -3637,14 +3637,14 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3637 /* Select Configuration Page */ 3637 /* Select Configuration Page */
3638 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3638 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3639 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3639 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3640 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3640 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3641 } else { 3641 } else {
3642 /* Use Alternative Page Select register to access 3642 /* Use Alternative Page Select register to access
3643 * registers 30 and 31 3643 * registers 30 and 31
3644 */ 3644 */
3645 ret_val = e1000_write_phy_reg_ex(hw, 3645 ret_val = e1000_write_phy_reg_ex(hw,
3646 GG82563_PHY_PAGE_SELECT_ALT, 3646 GG82563_PHY_PAGE_SELECT_ALT,
3647 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3647 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3648 } 3648 }
3649 3649
3650 if (ret_val) { 3650 if (ret_val) {
@@ -3661,13 +3661,13 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3661 return ret_val; 3661 return ret_val;
3662} 3662}
3663 3663
3664static int32_t 3664static s32
3665e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 3665e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3666 uint16_t phy_data) 3666 u16 phy_data)
3667{ 3667{
3668 uint32_t i; 3668 u32 i;
3669 uint32_t mdic = 0; 3669 u32 mdic = 0;
3670 const uint32_t phy_addr = 1; 3670 const u32 phy_addr = 1;
3671 3671
3672 DEBUGFUNC("e1000_write_phy_reg_ex"); 3672 DEBUGFUNC("e1000_write_phy_reg_ex");
3673 3673
@@ -3681,7 +3681,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3681 * for the PHY register in the MDI Control register. The MAC will take 3681 * for the PHY register in the MDI Control register. The MAC will take
3682 * care of interfacing with the PHY to send the desired data. 3682 * care of interfacing with the PHY to send the desired data.
3683 */ 3683 */
3684 mdic = (((uint32_t) phy_data) | 3684 mdic = (((u32) phy_data) |
3685 (reg_addr << E1000_MDIC_REG_SHIFT) | 3685 (reg_addr << E1000_MDIC_REG_SHIFT) |
3686 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3686 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3687 (E1000_MDIC_OP_WRITE)); 3687 (E1000_MDIC_OP_WRITE));
@@ -3715,7 +3715,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3715 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3715 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3716 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3716 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3717 mdic <<= 16; 3717 mdic <<= 16;
3718 mdic |= (uint32_t) phy_data; 3718 mdic |= (u32) phy_data;
3719 3719
3720 e1000_shift_out_mdi_bits(hw, mdic, 32); 3720 e1000_shift_out_mdi_bits(hw, mdic, 32);
3721 } 3721 }
@@ -3723,13 +3723,13 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3723 return E1000_SUCCESS; 3723 return E1000_SUCCESS;
3724} 3724}
3725 3725
3726static int32_t 3726static s32
3727e1000_read_kmrn_reg(struct e1000_hw *hw, 3727e1000_read_kmrn_reg(struct e1000_hw *hw,
3728 uint32_t reg_addr, 3728 u32 reg_addr,
3729 uint16_t *data) 3729 u16 *data)
3730{ 3730{
3731 uint32_t reg_val; 3731 u32 reg_val;
3732 uint16_t swfw; 3732 u16 swfw;
3733 DEBUGFUNC("e1000_read_kmrn_reg"); 3733 DEBUGFUNC("e1000_read_kmrn_reg");
3734 3734
3735 if ((hw->mac_type == e1000_80003es2lan) && 3735 if ((hw->mac_type == e1000_80003es2lan) &&
@@ -3750,19 +3750,19 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
3750 3750
3751 /* Read the data returned */ 3751 /* Read the data returned */
3752 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 3752 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3753 *data = (uint16_t)reg_val; 3753 *data = (u16)reg_val;
3754 3754
3755 e1000_swfw_sync_release(hw, swfw); 3755 e1000_swfw_sync_release(hw, swfw);
3756 return E1000_SUCCESS; 3756 return E1000_SUCCESS;
3757} 3757}
3758 3758
3759static int32_t 3759static s32
3760e1000_write_kmrn_reg(struct e1000_hw *hw, 3760e1000_write_kmrn_reg(struct e1000_hw *hw,
3761 uint32_t reg_addr, 3761 u32 reg_addr,
3762 uint16_t data) 3762 u16 data)
3763{ 3763{
3764 uint32_t reg_val; 3764 u32 reg_val;
3765 uint16_t swfw; 3765 u16 swfw;
3766 DEBUGFUNC("e1000_write_kmrn_reg"); 3766 DEBUGFUNC("e1000_write_kmrn_reg");
3767 3767
3768 if ((hw->mac_type == e1000_80003es2lan) && 3768 if ((hw->mac_type == e1000_80003es2lan) &&
@@ -3788,13 +3788,13 @@ e1000_write_kmrn_reg(struct e1000_hw *hw,
3788* 3788*
3789* hw - Struct containing variables accessed by shared code 3789* hw - Struct containing variables accessed by shared code
3790******************************************************************************/ 3790******************************************************************************/
3791int32_t 3791s32
3792e1000_phy_hw_reset(struct e1000_hw *hw) 3792e1000_phy_hw_reset(struct e1000_hw *hw)
3793{ 3793{
3794 uint32_t ctrl, ctrl_ext; 3794 u32 ctrl, ctrl_ext;
3795 uint32_t led_ctrl; 3795 u32 led_ctrl;
3796 int32_t ret_val; 3796 s32 ret_val;
3797 uint16_t swfw; 3797 u16 swfw;
3798 3798
3799 DEBUGFUNC("e1000_phy_hw_reset"); 3799 DEBUGFUNC("e1000_phy_hw_reset");
3800 3800
@@ -3882,11 +3882,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3882* 3882*
3883* Sets bit 15 of the MII Control register 3883* Sets bit 15 of the MII Control register
3884******************************************************************************/ 3884******************************************************************************/
3885int32_t 3885s32
3886e1000_phy_reset(struct e1000_hw *hw) 3886e1000_phy_reset(struct e1000_hw *hw)
3887{ 3887{
3888 int32_t ret_val; 3888 s32 ret_val;
3889 uint16_t phy_data; 3889 u16 phy_data;
3890 3890
3891 DEBUGFUNC("e1000_phy_reset"); 3891 DEBUGFUNC("e1000_phy_reset");
3892 3892
@@ -3937,9 +3937,9 @@ e1000_phy_reset(struct e1000_hw *hw)
3937void 3937void
3938e1000_phy_powerdown_workaround(struct e1000_hw *hw) 3938e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3939{ 3939{
3940 int32_t reg; 3940 s32 reg;
3941 uint16_t phy_data; 3941 u16 phy_data;
3942 int32_t retry = 0; 3942 s32 retry = 0;
3943 3943
3944 DEBUGFUNC("e1000_phy_powerdown_workaround"); 3944 DEBUGFUNC("e1000_phy_powerdown_workaround");
3945 3945
@@ -3987,13 +3987,13 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3987* 3987*
3988* hw - struct containing variables accessed by shared code 3988* hw - struct containing variables accessed by shared code
3989******************************************************************************/ 3989******************************************************************************/
3990static int32_t 3990static s32
3991e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) 3991e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3992{ 3992{
3993 int32_t ret_val; 3993 s32 ret_val;
3994 int32_t reg; 3994 s32 reg;
3995 int32_t cnt; 3995 s32 cnt;
3996 uint16_t phy_data; 3996 u16 phy_data;
3997 3997
3998 if (hw->kmrn_lock_loss_workaround_disabled) 3998 if (hw->kmrn_lock_loss_workaround_disabled)
3999 return E1000_SUCCESS; 3999 return E1000_SUCCESS;
@@ -4040,11 +4040,11 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4040* 4040*
4041* hw - Struct containing variables accessed by shared code 4041* hw - Struct containing variables accessed by shared code
4042******************************************************************************/ 4042******************************************************************************/
4043static int32_t 4043static s32
4044e1000_detect_gig_phy(struct e1000_hw *hw) 4044e1000_detect_gig_phy(struct e1000_hw *hw)
4045{ 4045{
4046 int32_t phy_init_status, ret_val; 4046 s32 phy_init_status, ret_val;
4047 uint16_t phy_id_high, phy_id_low; 4047 u16 phy_id_high, phy_id_low;
4048 bool match = false; 4048 bool match = false;
4049 4049
4050 DEBUGFUNC("e1000_detect_gig_phy"); 4050 DEBUGFUNC("e1000_detect_gig_phy");
@@ -4076,14 +4076,14 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4076 if (ret_val) 4076 if (ret_val)
4077 return ret_val; 4077 return ret_val;
4078 4078
4079 hw->phy_id = (uint32_t) (phy_id_high << 16); 4079 hw->phy_id = (u32) (phy_id_high << 16);
4080 udelay(20); 4080 udelay(20);
4081 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4081 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4082 if (ret_val) 4082 if (ret_val)
4083 return ret_val; 4083 return ret_val;
4084 4084
4085 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4085 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
4086 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4086 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
4087 4087
4088 switch (hw->mac_type) { 4088 switch (hw->mac_type) {
4089 case e1000_82543: 4089 case e1000_82543:
@@ -4136,10 +4136,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4136* 4136*
4137* hw - Struct containing variables accessed by shared code 4137* hw - Struct containing variables accessed by shared code
4138******************************************************************************/ 4138******************************************************************************/
4139static int32_t 4139static s32
4140e1000_phy_reset_dsp(struct e1000_hw *hw) 4140e1000_phy_reset_dsp(struct e1000_hw *hw)
4141{ 4141{
4142 int32_t ret_val; 4142 s32 ret_val;
4143 DEBUGFUNC("e1000_phy_reset_dsp"); 4143 DEBUGFUNC("e1000_phy_reset_dsp");
4144 4144
4145 do { 4145 do {
@@ -4163,12 +4163,12 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4163* hw - Struct containing variables accessed by shared code 4163* hw - Struct containing variables accessed by shared code
4164* phy_info - PHY information structure 4164* phy_info - PHY information structure
4165******************************************************************************/ 4165******************************************************************************/
4166static int32_t 4166static s32
4167e1000_phy_igp_get_info(struct e1000_hw *hw, 4167e1000_phy_igp_get_info(struct e1000_hw *hw,
4168 struct e1000_phy_info *phy_info) 4168 struct e1000_phy_info *phy_info)
4169{ 4169{
4170 int32_t ret_val; 4170 s32 ret_val;
4171 uint16_t phy_data, min_length, max_length, average; 4171 u16 phy_data, min_length, max_length, average;
4172 e1000_rev_polarity polarity; 4172 e1000_rev_polarity polarity;
4173 4173
4174 DEBUGFUNC("e1000_phy_igp_get_info"); 4174 DEBUGFUNC("e1000_phy_igp_get_info");
@@ -4240,12 +4240,12 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4240* hw - Struct containing variables accessed by shared code 4240* hw - Struct containing variables accessed by shared code
4241* phy_info - PHY information structure 4241* phy_info - PHY information structure
4242******************************************************************************/ 4242******************************************************************************/
4243static int32_t 4243static s32
4244e1000_phy_ife_get_info(struct e1000_hw *hw, 4244e1000_phy_ife_get_info(struct e1000_hw *hw,
4245 struct e1000_phy_info *phy_info) 4245 struct e1000_phy_info *phy_info)
4246{ 4246{
4247 int32_t ret_val; 4247 s32 ret_val;
4248 uint16_t phy_data; 4248 u16 phy_data;
4249 e1000_rev_polarity polarity; 4249 e1000_rev_polarity polarity;
4250 4250
4251 DEBUGFUNC("e1000_phy_ife_get_info"); 4251 DEBUGFUNC("e1000_phy_ife_get_info");
@@ -4290,12 +4290,12 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4290* hw - Struct containing variables accessed by shared code 4290* hw - Struct containing variables accessed by shared code
4291* phy_info - PHY information structure 4291* phy_info - PHY information structure
4292******************************************************************************/ 4292******************************************************************************/
4293static int32_t 4293static s32
4294e1000_phy_m88_get_info(struct e1000_hw *hw, 4294e1000_phy_m88_get_info(struct e1000_hw *hw,
4295 struct e1000_phy_info *phy_info) 4295 struct e1000_phy_info *phy_info)
4296{ 4296{
4297 int32_t ret_val; 4297 s32 ret_val;
4298 uint16_t phy_data; 4298 u16 phy_data;
4299 e1000_rev_polarity polarity; 4299 e1000_rev_polarity polarity;
4300 4300
4301 DEBUGFUNC("e1000_phy_m88_get_info"); 4301 DEBUGFUNC("e1000_phy_m88_get_info");
@@ -4369,12 +4369,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4369* hw - Struct containing variables accessed by shared code 4369* hw - Struct containing variables accessed by shared code
4370* phy_info - PHY information structure 4370* phy_info - PHY information structure
4371******************************************************************************/ 4371******************************************************************************/
4372int32_t 4372s32
4373e1000_phy_get_info(struct e1000_hw *hw, 4373e1000_phy_get_info(struct e1000_hw *hw,
4374 struct e1000_phy_info *phy_info) 4374 struct e1000_phy_info *phy_info)
4375{ 4375{
4376 int32_t ret_val; 4376 s32 ret_val;
4377 uint16_t phy_data; 4377 u16 phy_data;
4378 4378
4379 DEBUGFUNC("e1000_phy_get_info"); 4379 DEBUGFUNC("e1000_phy_get_info");
4380 4380
@@ -4415,7 +4415,7 @@ e1000_phy_get_info(struct e1000_hw *hw,
4415 return e1000_phy_m88_get_info(hw, phy_info); 4415 return e1000_phy_m88_get_info(hw, phy_info);
4416} 4416}
4417 4417
4418int32_t 4418s32
4419e1000_validate_mdi_setting(struct e1000_hw *hw) 4419e1000_validate_mdi_setting(struct e1000_hw *hw)
4420{ 4420{
4421 DEBUGFUNC("e1000_validate_mdi_settings"); 4421 DEBUGFUNC("e1000_validate_mdi_settings");
@@ -4436,13 +4436,13 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
4436 * 4436 *
4437 * hw - Struct containing variables accessed by shared code 4437 * hw - Struct containing variables accessed by shared code
4438 *****************************************************************************/ 4438 *****************************************************************************/
4439int32_t 4439s32
4440e1000_init_eeprom_params(struct e1000_hw *hw) 4440e1000_init_eeprom_params(struct e1000_hw *hw)
4441{ 4441{
4442 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4442 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4443 uint32_t eecd = E1000_READ_REG(hw, EECD); 4443 u32 eecd = E1000_READ_REG(hw, EECD);
4444 int32_t ret_val = E1000_SUCCESS; 4444 s32 ret_val = E1000_SUCCESS;
4445 uint16_t eeprom_size; 4445 u16 eeprom_size;
4446 4446
4447 DEBUGFUNC("e1000_init_eeprom_params"); 4447 DEBUGFUNC("e1000_init_eeprom_params");
4448 4448
@@ -4561,8 +4561,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4561 break; 4561 break;
4562 case e1000_ich8lan: 4562 case e1000_ich8lan:
4563 { 4563 {
4564 int32_t i = 0; 4564 s32 i = 0;
4565 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 4565 u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4566 4566
4567 eeprom->type = e1000_eeprom_ich8; 4567 eeprom->type = e1000_eeprom_ich8;
4568 eeprom->use_eerd = false; 4568 eeprom->use_eerd = false;
@@ -4586,7 +4586,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4586 4586
4587 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 4587 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4588 4588
4589 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4589 hw->flash_bank_size /= 2 * sizeof(u16);
4590 4590
4591 break; 4591 break;
4592 } 4592 }
@@ -4611,7 +4611,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4611 if (eeprom_size) 4611 if (eeprom_size)
4612 eeprom_size++; 4612 eeprom_size++;
4613 } else { 4613 } else {
4614 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4614 eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4615 E1000_EECD_SIZE_EX_SHIFT); 4615 E1000_EECD_SIZE_EX_SHIFT);
4616 } 4616 }
4617 4617
@@ -4628,7 +4628,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4628 *****************************************************************************/ 4628 *****************************************************************************/
4629static void 4629static void
4630e1000_raise_ee_clk(struct e1000_hw *hw, 4630e1000_raise_ee_clk(struct e1000_hw *hw,
4631 uint32_t *eecd) 4631 u32 *eecd)
4632{ 4632{
4633 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 4633 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4634 * wait <delay> microseconds. 4634 * wait <delay> microseconds.
@@ -4647,7 +4647,7 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
4647 *****************************************************************************/ 4647 *****************************************************************************/
4648static void 4648static void
4649e1000_lower_ee_clk(struct e1000_hw *hw, 4649e1000_lower_ee_clk(struct e1000_hw *hw,
4650 uint32_t *eecd) 4650 u32 *eecd)
4651{ 4651{
4652 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 4652 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4653 * wait 50 microseconds. 4653 * wait 50 microseconds.
@@ -4667,12 +4667,12 @@ e1000_lower_ee_clk(struct e1000_hw *hw,
4667 *****************************************************************************/ 4667 *****************************************************************************/
4668static void 4668static void
4669e1000_shift_out_ee_bits(struct e1000_hw *hw, 4669e1000_shift_out_ee_bits(struct e1000_hw *hw,
4670 uint16_t data, 4670 u16 data,
4671 uint16_t count) 4671 u16 count)
4672{ 4672{
4673 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4673 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4674 uint32_t eecd; 4674 u32 eecd;
4675 uint32_t mask; 4675 u32 mask;
4676 4676
4677 /* We need to shift "count" bits out to the EEPROM. So, value in the 4677 /* We need to shift "count" bits out to the EEPROM. So, value in the
4678 * "data" parameter will be shifted out to the EEPROM one bit at a time. 4678 * "data" parameter will be shifted out to the EEPROM one bit at a time.
@@ -4718,13 +4718,13 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4718 * 4718 *
4719 * hw - Struct containing variables accessed by shared code 4719 * hw - Struct containing variables accessed by shared code
4720 *****************************************************************************/ 4720 *****************************************************************************/
4721static uint16_t 4721static u16
4722e1000_shift_in_ee_bits(struct e1000_hw *hw, 4722e1000_shift_in_ee_bits(struct e1000_hw *hw,
4723 uint16_t count) 4723 u16 count)
4724{ 4724{
4725 uint32_t eecd; 4725 u32 eecd;
4726 uint32_t i; 4726 u32 i;
4727 uint16_t data; 4727 u16 data;
4728 4728
4729 /* In order to read a register from the EEPROM, we need to shift 'count' 4729 /* In order to read a register from the EEPROM, we need to shift 'count'
4730 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 4730 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
@@ -4762,11 +4762,11 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4762 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 4762 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4763 * function should be called before issuing a command to the EEPROM. 4763 * function should be called before issuing a command to the EEPROM.
4764 *****************************************************************************/ 4764 *****************************************************************************/
4765static int32_t 4765static s32
4766e1000_acquire_eeprom(struct e1000_hw *hw) 4766e1000_acquire_eeprom(struct e1000_hw *hw)
4767{ 4767{
4768 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4768 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4769 uint32_t eecd, i=0; 4769 u32 eecd, i=0;
4770 4770
4771 DEBUGFUNC("e1000_acquire_eeprom"); 4771 DEBUGFUNC("e1000_acquire_eeprom");
4772 4772
@@ -4825,7 +4825,7 @@ static void
4825e1000_standby_eeprom(struct e1000_hw *hw) 4825e1000_standby_eeprom(struct e1000_hw *hw)
4826{ 4826{
4827 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4827 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4828 uint32_t eecd; 4828 u32 eecd;
4829 4829
4830 eecd = E1000_READ_REG(hw, EECD); 4830 eecd = E1000_READ_REG(hw, EECD);
4831 4831
@@ -4873,7 +4873,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4873static void 4873static void
4874e1000_release_eeprom(struct e1000_hw *hw) 4874e1000_release_eeprom(struct e1000_hw *hw)
4875{ 4875{
4876 uint32_t eecd; 4876 u32 eecd;
4877 4877
4878 DEBUGFUNC("e1000_release_eeprom"); 4878 DEBUGFUNC("e1000_release_eeprom");
4879 4879
@@ -4921,11 +4921,11 @@ e1000_release_eeprom(struct e1000_hw *hw)
4921 * 4921 *
4922 * hw - Struct containing variables accessed by shared code 4922 * hw - Struct containing variables accessed by shared code
4923 *****************************************************************************/ 4923 *****************************************************************************/
4924static int32_t 4924static s32
4925e1000_spi_eeprom_ready(struct e1000_hw *hw) 4925e1000_spi_eeprom_ready(struct e1000_hw *hw)
4926{ 4926{
4927 uint16_t retry_count = 0; 4927 u16 retry_count = 0;
4928 uint8_t spi_stat_reg; 4928 u8 spi_stat_reg;
4929 4929
4930 DEBUGFUNC("e1000_spi_eeprom_ready"); 4930 DEBUGFUNC("e1000_spi_eeprom_ready");
4931 4931
@@ -4938,7 +4938,7 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4938 do { 4938 do {
4939 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 4939 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4940 hw->eeprom.opcode_bits); 4940 hw->eeprom.opcode_bits);
4941 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 4941 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
4942 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 4942 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4943 break; 4943 break;
4944 4944
@@ -4967,14 +4967,14 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4967 * data - word read from the EEPROM 4967 * data - word read from the EEPROM
4968 * words - number of words to read 4968 * words - number of words to read
4969 *****************************************************************************/ 4969 *****************************************************************************/
4970int32_t 4970s32
4971e1000_read_eeprom(struct e1000_hw *hw, 4971e1000_read_eeprom(struct e1000_hw *hw,
4972 uint16_t offset, 4972 u16 offset,
4973 uint16_t words, 4973 u16 words,
4974 uint16_t *data) 4974 u16 *data)
4975{ 4975{
4976 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4976 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4977 uint32_t i = 0; 4977 u32 i = 0;
4978 4978
4979 DEBUGFUNC("e1000_read_eeprom"); 4979 DEBUGFUNC("e1000_read_eeprom");
4980 4980
@@ -5012,8 +5012,8 @@ e1000_read_eeprom(struct e1000_hw *hw,
5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5013 * acquired the EEPROM at this point, so any returns should relase it */ 5013 * acquired the EEPROM at this point, so any returns should relase it */
5014 if (eeprom->type == e1000_eeprom_spi) { 5014 if (eeprom->type == e1000_eeprom_spi) {
5015 uint16_t word_in; 5015 u16 word_in;
5016 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 5016 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
5017 5017
5018 if (e1000_spi_eeprom_ready(hw)) { 5018 if (e1000_spi_eeprom_ready(hw)) {
5019 e1000_release_eeprom(hw); 5019 e1000_release_eeprom(hw);
@@ -5028,7 +5028,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
5028 5028
5029 /* Send the READ command (opcode + addr) */ 5029 /* Send the READ command (opcode + addr) */
5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5031 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); 5031 e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
5032 5032
5033 /* Read the data. The address of the eeprom internally increments with 5033 /* Read the data. The address of the eeprom internally increments with
5034 * each byte (spi) being read, saving on the overhead of eeprom setup 5034 * each byte (spi) being read, saving on the overhead of eeprom setup
@@ -5044,7 +5044,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
5044 /* Send the READ command (opcode + addr) */ 5044 /* Send the READ command (opcode + addr) */
5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5046 eeprom->opcode_bits); 5046 eeprom->opcode_bits);
5047 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 5047 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
5048 eeprom->address_bits); 5048 eeprom->address_bits);
5049 5049
5050 /* Read the data. For microwire, each word requires the overhead 5050 /* Read the data. For microwire, each word requires the overhead
@@ -5068,14 +5068,14 @@ e1000_read_eeprom(struct e1000_hw *hw,
5068 * data - word read from the EEPROM 5068 * data - word read from the EEPROM
5069 * words - number of words to read 5069 * words - number of words to read
5070 *****************************************************************************/ 5070 *****************************************************************************/
5071static int32_t 5071static s32
5072e1000_read_eeprom_eerd(struct e1000_hw *hw, 5072e1000_read_eeprom_eerd(struct e1000_hw *hw,
5073 uint16_t offset, 5073 u16 offset,
5074 uint16_t words, 5074 u16 words,
5075 uint16_t *data) 5075 u16 *data)
5076{ 5076{
5077 uint32_t i, eerd = 0; 5077 u32 i, eerd = 0;
5078 int32_t error = 0; 5078 s32 error = 0;
5079 5079
5080 for (i = 0; i < words; i++) { 5080 for (i = 0; i < words; i++) {
5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
@@ -5102,15 +5102,15 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
5102 * data - word read from the EEPROM 5102 * data - word read from the EEPROM
5103 * words - number of words to read 5103 * words - number of words to read
5104 *****************************************************************************/ 5104 *****************************************************************************/
5105static int32_t 5105static s32
5106e1000_write_eeprom_eewr(struct e1000_hw *hw, 5106e1000_write_eeprom_eewr(struct e1000_hw *hw,
5107 uint16_t offset, 5107 u16 offset,
5108 uint16_t words, 5108 u16 words,
5109 uint16_t *data) 5109 u16 *data)
5110{ 5110{
5111 uint32_t register_value = 0; 5111 u32 register_value = 0;
5112 uint32_t i = 0; 5112 u32 i = 0;
5113 int32_t error = 0; 5113 s32 error = 0;
5114 5114
5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5116 return -E1000_ERR_SWFW_SYNC; 5116 return -E1000_ERR_SWFW_SYNC;
@@ -5143,12 +5143,12 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
5143 * 5143 *
5144 * hw - Struct containing variables accessed by shared code 5144 * hw - Struct containing variables accessed by shared code
5145 *****************************************************************************/ 5145 *****************************************************************************/
5146static int32_t 5146static s32
5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5148{ 5148{
5149 uint32_t attempts = 100000; 5149 u32 attempts = 100000;
5150 uint32_t i, reg = 0; 5150 u32 i, reg = 0;
5151 int32_t done = E1000_ERR_EEPROM; 5151 s32 done = E1000_ERR_EEPROM;
5152 5152
5153 for (i = 0; i < attempts; i++) { 5153 for (i = 0; i < attempts; i++) {
5154 if (eerd == E1000_EEPROM_POLL_READ) 5154 if (eerd == E1000_EEPROM_POLL_READ)
@@ -5174,7 +5174,7 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5174static bool 5174static bool
5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5176{ 5176{
5177 uint32_t eecd = 0; 5177 u32 eecd = 0;
5178 5178
5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5180 5180
@@ -5204,11 +5204,11 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5205 * valid. 5205 * valid.
5206 *****************************************************************************/ 5206 *****************************************************************************/
5207int32_t 5207s32
5208e1000_validate_eeprom_checksum(struct e1000_hw *hw) 5208e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5209{ 5209{
5210 uint16_t checksum = 0; 5210 u16 checksum = 0;
5211 uint16_t i, eeprom_data; 5211 u16 i, eeprom_data;
5212 5212
5213 DEBUGFUNC("e1000_validate_eeprom_checksum"); 5213 DEBUGFUNC("e1000_validate_eeprom_checksum");
5214 5214
@@ -5252,7 +5252,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5252 checksum += eeprom_data; 5252 checksum += eeprom_data;
5253 } 5253 }
5254 5254
5255 if (checksum == (uint16_t) EEPROM_SUM) 5255 if (checksum == (u16) EEPROM_SUM)
5256 return E1000_SUCCESS; 5256 return E1000_SUCCESS;
5257 else { 5257 else {
5258 DEBUGOUT("EEPROM Checksum Invalid\n"); 5258 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5268,12 +5268,12 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5268 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 5268 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5269 * Writes the difference to word offset 63 of the EEPROM. 5269 * Writes the difference to word offset 63 of the EEPROM.
5270 *****************************************************************************/ 5270 *****************************************************************************/
5271int32_t 5271s32
5272e1000_update_eeprom_checksum(struct e1000_hw *hw) 5272e1000_update_eeprom_checksum(struct e1000_hw *hw)
5273{ 5273{
5274 uint32_t ctrl_ext; 5274 u32 ctrl_ext;
5275 uint16_t checksum = 0; 5275 u16 checksum = 0;
5276 uint16_t i, eeprom_data; 5276 u16 i, eeprom_data;
5277 5277
5278 DEBUGFUNC("e1000_update_eeprom_checksum"); 5278 DEBUGFUNC("e1000_update_eeprom_checksum");
5279 5279
@@ -5284,7 +5284,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5284 } 5284 }
5285 checksum += eeprom_data; 5285 checksum += eeprom_data;
5286 } 5286 }
5287 checksum = (uint16_t) EEPROM_SUM - checksum; 5287 checksum = (u16) EEPROM_SUM - checksum;
5288 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5288 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5289 DEBUGOUT("EEPROM Write Error\n"); 5289 DEBUGOUT("EEPROM Write Error\n");
5290 return -E1000_ERR_EEPROM; 5290 return -E1000_ERR_EEPROM;
@@ -5313,14 +5313,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5313 * If e1000_update_eeprom_checksum is not called after this function, the 5313 * If e1000_update_eeprom_checksum is not called after this function, the
5314 * EEPROM will most likely contain an invalid checksum. 5314 * EEPROM will most likely contain an invalid checksum.
5315 *****************************************************************************/ 5315 *****************************************************************************/
5316int32_t 5316s32
5317e1000_write_eeprom(struct e1000_hw *hw, 5317e1000_write_eeprom(struct e1000_hw *hw,
5318 uint16_t offset, 5318 u16 offset,
5319 uint16_t words, 5319 u16 words,
5320 uint16_t *data) 5320 u16 *data)
5321{ 5321{
5322 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5322 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5323 int32_t status = 0; 5323 s32 status = 0;
5324 5324
5325 DEBUGFUNC("e1000_write_eeprom"); 5325 DEBUGFUNC("e1000_write_eeprom");
5326 5326
@@ -5370,19 +5370,19 @@ e1000_write_eeprom(struct e1000_hw *hw,
5370 * data - pointer to array of 8 bit words to be written to the EEPROM 5370 * data - pointer to array of 8 bit words to be written to the EEPROM
5371 * 5371 *
5372 *****************************************************************************/ 5372 *****************************************************************************/
5373static int32_t 5373static s32
5374e1000_write_eeprom_spi(struct e1000_hw *hw, 5374e1000_write_eeprom_spi(struct e1000_hw *hw,
5375 uint16_t offset, 5375 u16 offset,
5376 uint16_t words, 5376 u16 words,
5377 uint16_t *data) 5377 u16 *data)
5378{ 5378{
5379 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5379 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5380 uint16_t widx = 0; 5380 u16 widx = 0;
5381 5381
5382 DEBUGFUNC("e1000_write_eeprom_spi"); 5382 DEBUGFUNC("e1000_write_eeprom_spi");
5383 5383
5384 while (widx < words) { 5384 while (widx < words) {
5385 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5385 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
5386 5386
5387 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5387 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5388 5388
@@ -5401,14 +5401,14 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5401 /* Send the Write command (8-bit opcode + addr) */ 5401 /* Send the Write command (8-bit opcode + addr) */
5402 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 5402 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5403 5403
5404 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), 5404 e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
5405 eeprom->address_bits); 5405 eeprom->address_bits);
5406 5406
5407 /* Send the data */ 5407 /* Send the data */
5408 5408
5409 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 5409 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5410 while (widx < words) { 5410 while (widx < words) {
5411 uint16_t word_out = data[widx]; 5411 u16 word_out = data[widx];
5412 word_out = (word_out >> 8) | (word_out << 8); 5412 word_out = (word_out >> 8) | (word_out << 8);
5413 e1000_shift_out_ee_bits(hw, word_out, 16); 5413 e1000_shift_out_ee_bits(hw, word_out, 16);
5414 widx++; 5414 widx++;
@@ -5436,16 +5436,16 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5436 * data - pointer to array of 16 bit words to be written to the EEPROM 5436 * data - pointer to array of 16 bit words to be written to the EEPROM
5437 * 5437 *
5438 *****************************************************************************/ 5438 *****************************************************************************/
5439static int32_t 5439static s32
5440e1000_write_eeprom_microwire(struct e1000_hw *hw, 5440e1000_write_eeprom_microwire(struct e1000_hw *hw,
5441 uint16_t offset, 5441 u16 offset,
5442 uint16_t words, 5442 u16 words,
5443 uint16_t *data) 5443 u16 *data)
5444{ 5444{
5445 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5445 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5446 uint32_t eecd; 5446 u32 eecd;
5447 uint16_t words_written = 0; 5447 u16 words_written = 0;
5448 uint16_t i = 0; 5448 u16 i = 0;
5449 5449
5450 DEBUGFUNC("e1000_write_eeprom_microwire"); 5450 DEBUGFUNC("e1000_write_eeprom_microwire");
5451 5451
@@ -5456,9 +5456,9 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5456 * EEPROM into write/erase mode. 5456 * EEPROM into write/erase mode.
5457 */ 5457 */
5458 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 5458 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5459 (uint16_t)(eeprom->opcode_bits + 2)); 5459 (u16)(eeprom->opcode_bits + 2));
5460 5460
5461 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5461 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5462 5462
5463 /* Prepare the EEPROM */ 5463 /* Prepare the EEPROM */
5464 e1000_standby_eeprom(hw); 5464 e1000_standby_eeprom(hw);
@@ -5468,7 +5468,7 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5468 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 5468 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5469 eeprom->opcode_bits); 5469 eeprom->opcode_bits);
5470 5470
5471 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), 5471 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
5472 eeprom->address_bits); 5472 eeprom->address_bits);
5473 5473
5474 /* Send the data */ 5474 /* Send the data */
@@ -5506,9 +5506,9 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5506 * EEPROM out of write/erase mode. 5506 * EEPROM out of write/erase mode.
5507 */ 5507 */
5508 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 5508 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5509 (uint16_t)(eeprom->opcode_bits + 2)); 5509 (u16)(eeprom->opcode_bits + 2));
5510 5510
5511 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5511 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5512 5512
5513 return E1000_SUCCESS; 5513 return E1000_SUCCESS;
5514} 5514}
@@ -5523,18 +5523,18 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5523 * data - word read from the EEPROM 5523 * data - word read from the EEPROM
5524 * words - number of words to read 5524 * words - number of words to read
5525 *****************************************************************************/ 5525 *****************************************************************************/
5526static int32_t 5526static s32
5527e1000_commit_shadow_ram(struct e1000_hw *hw) 5527e1000_commit_shadow_ram(struct e1000_hw *hw)
5528{ 5528{
5529 uint32_t attempts = 100000; 5529 u32 attempts = 100000;
5530 uint32_t eecd = 0; 5530 u32 eecd = 0;
5531 uint32_t flop = 0; 5531 u32 flop = 0;
5532 uint32_t i = 0; 5532 u32 i = 0;
5533 int32_t error = E1000_SUCCESS; 5533 s32 error = E1000_SUCCESS;
5534 uint32_t old_bank_offset = 0; 5534 u32 old_bank_offset = 0;
5535 uint32_t new_bank_offset = 0; 5535 u32 new_bank_offset = 0;
5536 uint8_t low_byte = 0; 5536 u8 low_byte = 0;
5537 uint8_t high_byte = 0; 5537 u8 high_byte = 0;
5538 bool sector_write_failed = false; 5538 bool sector_write_failed = false;
5539 5539
5540 if (hw->mac_type == e1000_82573) { 5540 if (hw->mac_type == e1000_82573) {
@@ -5595,7 +5595,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5595 * in the other NVM bank or a modified value stored 5595 * in the other NVM bank or a modified value stored
5596 * in the shadow RAM */ 5596 * in the shadow RAM */
5597 if (hw->eeprom_shadow_ram[i].modified) { 5597 if (hw->eeprom_shadow_ram[i].modified) {
5598 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; 5598 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
5599 udelay(100); 5599 udelay(100);
5600 error = e1000_verify_write_ich8_byte(hw, 5600 error = e1000_verify_write_ich8_byte(hw,
5601 (i << 1) + new_bank_offset, low_byte); 5601 (i << 1) + new_bank_offset, low_byte);
@@ -5604,7 +5604,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5604 sector_write_failed = true; 5604 sector_write_failed = true;
5605 else { 5605 else {
5606 high_byte = 5606 high_byte =
5607 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); 5607 (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5608 udelay(100); 5608 udelay(100);
5609 } 5609 }
5610 } else { 5610 } else {
@@ -5687,11 +5687,11 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5687 * 5687 *
5688 * hw - Struct containing variables accessed by shared code 5688 * hw - Struct containing variables accessed by shared code
5689 *****************************************************************************/ 5689 *****************************************************************************/
5690int32_t 5690s32
5691e1000_read_mac_addr(struct e1000_hw * hw) 5691e1000_read_mac_addr(struct e1000_hw * hw)
5692{ 5692{
5693 uint16_t offset; 5693 u16 offset;
5694 uint16_t eeprom_data, i; 5694 u16 eeprom_data, i;
5695 5695
5696 DEBUGFUNC("e1000_read_mac_addr"); 5696 DEBUGFUNC("e1000_read_mac_addr");
5697 5697
@@ -5701,8 +5701,8 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5701 DEBUGOUT("EEPROM Read Error\n"); 5701 DEBUGOUT("EEPROM Read Error\n");
5702 return -E1000_ERR_EEPROM; 5702 return -E1000_ERR_EEPROM;
5703 } 5703 }
5704 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 5704 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
5705 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); 5705 hw->perm_mac_addr[i+1] = (u8) (eeprom_data >> 8);
5706 } 5706 }
5707 5707
5708 switch (hw->mac_type) { 5708 switch (hw->mac_type) {
@@ -5734,8 +5734,8 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5734static void 5734static void
5735e1000_init_rx_addrs(struct e1000_hw *hw) 5735e1000_init_rx_addrs(struct e1000_hw *hw)
5736{ 5736{
5737 uint32_t i; 5737 u32 i;
5738 uint32_t rar_num; 5738 u32 rar_num;
5739 5739
5740 DEBUGFUNC("e1000_init_rx_addrs"); 5740 DEBUGFUNC("e1000_init_rx_addrs");
5741 5741
@@ -5770,11 +5770,11 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5770 * hw - Struct containing variables accessed by shared code 5770 * hw - Struct containing variables accessed by shared code
5771 * mc_addr - the multicast address to hash 5771 * mc_addr - the multicast address to hash
5772 *****************************************************************************/ 5772 *****************************************************************************/
5773uint32_t 5773u32
5774e1000_hash_mc_addr(struct e1000_hw *hw, 5774e1000_hash_mc_addr(struct e1000_hw *hw,
5775 uint8_t *mc_addr) 5775 u8 *mc_addr)
5776{ 5776{
5777 uint32_t hash_value = 0; 5777 u32 hash_value = 0;
5778 5778
5779 /* The portion of the address that is used for the hash table is 5779 /* The portion of the address that is used for the hash table is
5780 * determined by the mc_filter_type setting. 5780 * determined by the mc_filter_type setting.
@@ -5787,37 +5787,37 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5787 case 0: 5787 case 0:
5788 if (hw->mac_type == e1000_ich8lan) { 5788 if (hw->mac_type == e1000_ich8lan) {
5789 /* [47:38] i.e. 0x158 for above example address */ 5789 /* [47:38] i.e. 0x158 for above example address */
5790 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); 5790 hash_value = ((mc_addr[4] >> 6) | (((u16) mc_addr[5]) << 2));
5791 } else { 5791 } else {
5792 /* [47:36] i.e. 0x563 for above example address */ 5792 /* [47:36] i.e. 0x563 for above example address */
5793 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5793 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
5794 } 5794 }
5795 break; 5795 break;
5796 case 1: 5796 case 1:
5797 if (hw->mac_type == e1000_ich8lan) { 5797 if (hw->mac_type == e1000_ich8lan) {
5798 /* [46:37] i.e. 0x2B1 for above example address */ 5798 /* [46:37] i.e. 0x2B1 for above example address */
5799 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); 5799 hash_value = ((mc_addr[4] >> 5) | (((u16) mc_addr[5]) << 3));
5800 } else { 5800 } else {
5801 /* [46:35] i.e. 0xAC6 for above example address */ 5801 /* [46:35] i.e. 0xAC6 for above example address */
5802 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5802 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
5803 } 5803 }
5804 break; 5804 break;
5805 case 2: 5805 case 2:
5806 if (hw->mac_type == e1000_ich8lan) { 5806 if (hw->mac_type == e1000_ich8lan) {
5807 /*[45:36] i.e. 0x163 for above example address */ 5807 /*[45:36] i.e. 0x163 for above example address */
5808 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5808 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
5809 } else { 5809 } else {
5810 /* [45:34] i.e. 0x5D8 for above example address */ 5810 /* [45:34] i.e. 0x5D8 for above example address */
5811 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5811 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
5812 } 5812 }
5813 break; 5813 break;
5814 case 3: 5814 case 3:
5815 if (hw->mac_type == e1000_ich8lan) { 5815 if (hw->mac_type == e1000_ich8lan) {
5816 /* [43:34] i.e. 0x18D for above example address */ 5816 /* [43:34] i.e. 0x18D for above example address */
5817 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5817 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
5818 } else { 5818 } else {
5819 /* [43:32] i.e. 0x634 for above example address */ 5819 /* [43:32] i.e. 0x634 for above example address */
5820 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5820 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
5821 } 5821 }
5822 break; 5822 break;
5823 } 5823 }
@@ -5837,11 +5837,11 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5837 *****************************************************************************/ 5837 *****************************************************************************/
5838void 5838void
5839e1000_mta_set(struct e1000_hw *hw, 5839e1000_mta_set(struct e1000_hw *hw,
5840 uint32_t hash_value) 5840 u32 hash_value)
5841{ 5841{
5842 uint32_t hash_bit, hash_reg; 5842 u32 hash_bit, hash_reg;
5843 uint32_t mta; 5843 u32 mta;
5844 uint32_t temp; 5844 u32 temp;
5845 5845
5846 /* The MTA is a register array of 128 32-bit registers. 5846 /* The MTA is a register array of 128 32-bit registers.
5847 * It is treated like an array of 4096 bits. We want to set 5847 * It is treated like an array of 4096 bits. We want to set
@@ -5886,18 +5886,18 @@ e1000_mta_set(struct e1000_hw *hw,
5886 *****************************************************************************/ 5886 *****************************************************************************/
5887void 5887void
5888e1000_rar_set(struct e1000_hw *hw, 5888e1000_rar_set(struct e1000_hw *hw,
5889 uint8_t *addr, 5889 u8 *addr,
5890 uint32_t index) 5890 u32 index)
5891{ 5891{
5892 uint32_t rar_low, rar_high; 5892 u32 rar_low, rar_high;
5893 5893
5894 /* HW expects these in little endian so we reverse the byte order 5894 /* HW expects these in little endian so we reverse the byte order
5895 * from network order (big endian) to little endian 5895 * from network order (big endian) to little endian
5896 */ 5896 */
5897 rar_low = ((uint32_t) addr[0] | 5897 rar_low = ((u32) addr[0] |
5898 ((uint32_t) addr[1] << 8) | 5898 ((u32) addr[1] << 8) |
5899 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 5899 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5900 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 5900 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5901 5901
5902 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 5902 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5903 * unit hang. 5903 * unit hang.
@@ -5944,10 +5944,10 @@ e1000_rar_set(struct e1000_hw *hw,
5944 *****************************************************************************/ 5944 *****************************************************************************/
5945void 5945void
5946e1000_write_vfta(struct e1000_hw *hw, 5946e1000_write_vfta(struct e1000_hw *hw,
5947 uint32_t offset, 5947 u32 offset,
5948 uint32_t value) 5948 u32 value)
5949{ 5949{
5950 uint32_t temp; 5950 u32 temp;
5951 5951
5952 if (hw->mac_type == e1000_ich8lan) 5952 if (hw->mac_type == e1000_ich8lan)
5953 return; 5953 return;
@@ -5972,10 +5972,10 @@ e1000_write_vfta(struct e1000_hw *hw,
5972static void 5972static void
5973e1000_clear_vfta(struct e1000_hw *hw) 5973e1000_clear_vfta(struct e1000_hw *hw)
5974{ 5974{
5975 uint32_t offset; 5975 u32 offset;
5976 uint32_t vfta_value = 0; 5976 u32 vfta_value = 0;
5977 uint32_t vfta_offset = 0; 5977 u32 vfta_offset = 0;
5978 uint32_t vfta_bit_in_reg = 0; 5978 u32 vfta_bit_in_reg = 0;
5979 5979
5980 if (hw->mac_type == e1000_ich8lan) 5980 if (hw->mac_type == e1000_ich8lan)
5981 return; 5981 return;
@@ -6003,15 +6003,15 @@ e1000_clear_vfta(struct e1000_hw *hw)
6003 } 6003 }
6004} 6004}
6005 6005
6006static int32_t 6006static s32
6007e1000_id_led_init(struct e1000_hw * hw) 6007e1000_id_led_init(struct e1000_hw * hw)
6008{ 6008{
6009 uint32_t ledctl; 6009 u32 ledctl;
6010 const uint32_t ledctl_mask = 0x000000FF; 6010 const u32 ledctl_mask = 0x000000FF;
6011 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 6011 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6012 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 6012 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6013 uint16_t eeprom_data, i, temp; 6013 u16 eeprom_data, i, temp;
6014 const uint16_t led_mask = 0x0F; 6014 const u16 led_mask = 0x0F;
6015 6015
6016 DEBUGFUNC("e1000_id_led_init"); 6016 DEBUGFUNC("e1000_id_led_init");
6017 6017
@@ -6086,11 +6086,11 @@ e1000_id_led_init(struct e1000_hw * hw)
6086 * 6086 *
6087 * hw - Struct containing variables accessed by shared code 6087 * hw - Struct containing variables accessed by shared code
6088 *****************************************************************************/ 6088 *****************************************************************************/
6089int32_t 6089s32
6090e1000_setup_led(struct e1000_hw *hw) 6090e1000_setup_led(struct e1000_hw *hw)
6091{ 6091{
6092 uint32_t ledctl; 6092 u32 ledctl;
6093 int32_t ret_val = E1000_SUCCESS; 6093 s32 ret_val = E1000_SUCCESS;
6094 6094
6095 DEBUGFUNC("e1000_setup_led"); 6095 DEBUGFUNC("e1000_setup_led");
6096 6096
@@ -6111,7 +6111,7 @@ e1000_setup_led(struct e1000_hw *hw)
6111 if (ret_val) 6111 if (ret_val)
6112 return ret_val; 6112 return ret_val;
6113 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6113 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6114 (uint16_t)(hw->phy_spd_default & 6114 (u16)(hw->phy_spd_default &
6115 ~IGP01E1000_GMII_SPD)); 6115 ~IGP01E1000_GMII_SPD));
6116 if (ret_val) 6116 if (ret_val)
6117 return ret_val; 6117 return ret_val;
@@ -6145,11 +6145,11 @@ e1000_setup_led(struct e1000_hw *hw)
6145 * 6145 *
6146 * hw - Struct containing variables accessed by shared code 6146 * hw - Struct containing variables accessed by shared code
6147 *****************************************************************************/ 6147 *****************************************************************************/
6148int32_t 6148s32
6149e1000_blink_led_start(struct e1000_hw *hw) 6149e1000_blink_led_start(struct e1000_hw *hw)
6150{ 6150{
6151 int16_t i; 6151 s16 i;
6152 uint32_t ledctl_blink = 0; 6152 u32 ledctl_blink = 0;
6153 6153
6154 DEBUGFUNC("e1000_id_led_blink_on"); 6154 DEBUGFUNC("e1000_id_led_blink_on");
6155 6155
@@ -6180,10 +6180,10 @@ e1000_blink_led_start(struct e1000_hw *hw)
6180 * 6180 *
6181 * hw - Struct containing variables accessed by shared code 6181 * hw - Struct containing variables accessed by shared code
6182 *****************************************************************************/ 6182 *****************************************************************************/
6183int32_t 6183s32
6184e1000_cleanup_led(struct e1000_hw *hw) 6184e1000_cleanup_led(struct e1000_hw *hw)
6185{ 6185{
6186 int32_t ret_val = E1000_SUCCESS; 6186 s32 ret_val = E1000_SUCCESS;
6187 6187
6188 DEBUGFUNC("e1000_cleanup_led"); 6188 DEBUGFUNC("e1000_cleanup_led");
6189 6189
@@ -6222,10 +6222,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
6222 * 6222 *
6223 * hw - Struct containing variables accessed by shared code 6223 * hw - Struct containing variables accessed by shared code
6224 *****************************************************************************/ 6224 *****************************************************************************/
6225int32_t 6225s32
6226e1000_led_on(struct e1000_hw *hw) 6226e1000_led_on(struct e1000_hw *hw)
6227{ 6227{
6228 uint32_t ctrl = E1000_READ_REG(hw, CTRL); 6228 u32 ctrl = E1000_READ_REG(hw, CTRL);
6229 6229
6230 DEBUGFUNC("e1000_led_on"); 6230 DEBUGFUNC("e1000_led_on");
6231 6231
@@ -6273,10 +6273,10 @@ e1000_led_on(struct e1000_hw *hw)
6273 * 6273 *
6274 * hw - Struct containing variables accessed by shared code 6274 * hw - Struct containing variables accessed by shared code
6275 *****************************************************************************/ 6275 *****************************************************************************/
6276int32_t 6276s32
6277e1000_led_off(struct e1000_hw *hw) 6277e1000_led_off(struct e1000_hw *hw)
6278{ 6278{
6279 uint32_t ctrl = E1000_READ_REG(hw, CTRL); 6279 u32 ctrl = E1000_READ_REG(hw, CTRL);
6280 6280
6281 DEBUGFUNC("e1000_led_off"); 6281 DEBUGFUNC("e1000_led_off");
6282 6282
@@ -6327,7 +6327,7 @@ e1000_led_off(struct e1000_hw *hw)
6327static void 6327static void
6328e1000_clear_hw_cntrs(struct e1000_hw *hw) 6328e1000_clear_hw_cntrs(struct e1000_hw *hw)
6329{ 6329{
6330 volatile uint32_t temp; 6330 volatile u32 temp;
6331 6331
6332 temp = E1000_READ_REG(hw, CRCERRS); 6332 temp = E1000_READ_REG(hw, CRCERRS);
6333 temp = E1000_READ_REG(hw, SYMERRS); 6333 temp = E1000_READ_REG(hw, SYMERRS);
@@ -6495,10 +6495,10 @@ e1000_update_adaptive(struct e1000_hw *hw)
6495void 6495void
6496e1000_tbi_adjust_stats(struct e1000_hw *hw, 6496e1000_tbi_adjust_stats(struct e1000_hw *hw,
6497 struct e1000_hw_stats *stats, 6497 struct e1000_hw_stats *stats,
6498 uint32_t frame_len, 6498 u32 frame_len,
6499 uint8_t *mac_addr) 6499 u8 *mac_addr)
6500{ 6500{
6501 uint64_t carry_bit; 6501 u64 carry_bit;
6502 6502
6503 /* First adjust the frame length. */ 6503 /* First adjust the frame length. */
6504 frame_len--; 6504 frame_len--;
@@ -6527,7 +6527,7 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6527 * since the test for a multicast frame will test positive on 6527 * since the test for a multicast frame will test positive on
6528 * a broadcast frame. 6528 * a broadcast frame.
6529 */ 6529 */
6530 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6530 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
6531 /* Broadcast packet */ 6531 /* Broadcast packet */
6532 stats->bprc++; 6532 stats->bprc++;
6533 else if (*mac_addr & 0x01) 6533 else if (*mac_addr & 0x01)
@@ -6573,9 +6573,9 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6573void 6573void
6574e1000_get_bus_info(struct e1000_hw *hw) 6574e1000_get_bus_info(struct e1000_hw *hw)
6575{ 6575{
6576 int32_t ret_val; 6576 s32 ret_val;
6577 uint16_t pci_ex_link_status; 6577 u16 pci_ex_link_status;
6578 uint32_t status; 6578 u32 status;
6579 6579
6580 switch (hw->mac_type) { 6580 switch (hw->mac_type) {
6581 case e1000_82542_rev2_0: 6581 case e1000_82542_rev2_0:
@@ -6647,8 +6647,8 @@ e1000_get_bus_info(struct e1000_hw *hw)
6647 *****************************************************************************/ 6647 *****************************************************************************/
6648static void 6648static void
6649e1000_write_reg_io(struct e1000_hw *hw, 6649e1000_write_reg_io(struct e1000_hw *hw,
6650 uint32_t offset, 6650 u32 offset,
6651 uint32_t value) 6651 u32 value)
6652{ 6652{
6653 unsigned long io_addr = hw->io_base; 6653 unsigned long io_addr = hw->io_base;
6654 unsigned long io_data = hw->io_base + 4; 6654 unsigned long io_data = hw->io_base + 4;
@@ -6672,15 +6672,15 @@ e1000_write_reg_io(struct e1000_hw *hw,
6672 * register to the minimum and maximum range. 6672 * register to the minimum and maximum range.
6673 * For IGP phy's, the function calculates the range by the AGC registers. 6673 * For IGP phy's, the function calculates the range by the AGC registers.
6674 *****************************************************************************/ 6674 *****************************************************************************/
6675static int32_t 6675static s32
6676e1000_get_cable_length(struct e1000_hw *hw, 6676e1000_get_cable_length(struct e1000_hw *hw,
6677 uint16_t *min_length, 6677 u16 *min_length,
6678 uint16_t *max_length) 6678 u16 *max_length)
6679{ 6679{
6680 int32_t ret_val; 6680 s32 ret_val;
6681 uint16_t agc_value = 0; 6681 u16 agc_value = 0;
6682 uint16_t i, phy_data; 6682 u16 i, phy_data;
6683 uint16_t cable_length; 6683 u16 cable_length;
6684 6684
6685 DEBUGFUNC("e1000_get_cable_length"); 6685 DEBUGFUNC("e1000_get_cable_length");
6686 6686
@@ -6751,9 +6751,9 @@ e1000_get_cable_length(struct e1000_hw *hw,
6751 break; 6751 break;
6752 } 6752 }
6753 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6753 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6754 uint16_t cur_agc_value; 6754 u16 cur_agc_value;
6755 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6755 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6756 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6756 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6757 {IGP01E1000_PHY_AGC_A, 6757 {IGP01E1000_PHY_AGC_A,
6758 IGP01E1000_PHY_AGC_B, 6758 IGP01E1000_PHY_AGC_B,
6759 IGP01E1000_PHY_AGC_C, 6759 IGP01E1000_PHY_AGC_C,
@@ -6799,9 +6799,9 @@ e1000_get_cable_length(struct e1000_hw *hw,
6799 IGP01E1000_AGC_RANGE; 6799 IGP01E1000_AGC_RANGE;
6800 } else if (hw->phy_type == e1000_phy_igp_2 || 6800 } else if (hw->phy_type == e1000_phy_igp_2 ||
6801 hw->phy_type == e1000_phy_igp_3) { 6801 hw->phy_type == e1000_phy_igp_3) {
6802 uint16_t cur_agc_index, max_agc_index = 0; 6802 u16 cur_agc_index, max_agc_index = 0;
6803 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 6803 u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6804 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6804 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6805 {IGP02E1000_PHY_AGC_A, 6805 {IGP02E1000_PHY_AGC_A,
6806 IGP02E1000_PHY_AGC_B, 6806 IGP02E1000_PHY_AGC_B,
6807 IGP02E1000_PHY_AGC_C, 6807 IGP02E1000_PHY_AGC_C,
@@ -6863,12 +6863,12 @@ e1000_get_cable_length(struct e1000_hw *hw,
6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the 6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6864 * IGP01E1000_PHY_PCS_INIT_REG. 6864 * IGP01E1000_PHY_PCS_INIT_REG.
6865 *****************************************************************************/ 6865 *****************************************************************************/
6866static int32_t 6866static s32
6867e1000_check_polarity(struct e1000_hw *hw, 6867e1000_check_polarity(struct e1000_hw *hw,
6868 e1000_rev_polarity *polarity) 6868 e1000_rev_polarity *polarity)
6869{ 6869{
6870 int32_t ret_val; 6870 s32 ret_val;
6871 uint16_t phy_data; 6871 u16 phy_data;
6872 6872
6873 DEBUGFUNC("e1000_check_polarity"); 6873 DEBUGFUNC("e1000_check_polarity");
6874 6874
@@ -6939,11 +6939,11 @@ e1000_check_polarity(struct e1000_hw *hw,
6939 * Link Health register. In IGP this bit is latched high, so the driver must 6939 * Link Health register. In IGP this bit is latched high, so the driver must
6940 * read it immediately after link is established. 6940 * read it immediately after link is established.
6941 *****************************************************************************/ 6941 *****************************************************************************/
6942static int32_t 6942static s32
6943e1000_check_downshift(struct e1000_hw *hw) 6943e1000_check_downshift(struct e1000_hw *hw)
6944{ 6944{
6945 int32_t ret_val; 6945 s32 ret_val;
6946 uint16_t phy_data; 6946 u16 phy_data;
6947 6947
6948 DEBUGFUNC("e1000_check_downshift"); 6948 DEBUGFUNC("e1000_check_downshift");
6949 6949
@@ -6985,18 +6985,18 @@ e1000_check_downshift(struct e1000_hw *hw)
6985 * 6985 *
6986 ****************************************************************************/ 6986 ****************************************************************************/
6987 6987
6988static int32_t 6988static s32
6989e1000_config_dsp_after_link_change(struct e1000_hw *hw, 6989e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6990 bool link_up) 6990 bool link_up)
6991{ 6991{
6992 int32_t ret_val; 6992 s32 ret_val;
6993 uint16_t phy_data, phy_saved_data, speed, duplex, i; 6993 u16 phy_data, phy_saved_data, speed, duplex, i;
6994 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6994 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6995 {IGP01E1000_PHY_AGC_PARAM_A, 6995 {IGP01E1000_PHY_AGC_PARAM_A,
6996 IGP01E1000_PHY_AGC_PARAM_B, 6996 IGP01E1000_PHY_AGC_PARAM_B,
6997 IGP01E1000_PHY_AGC_PARAM_C, 6997 IGP01E1000_PHY_AGC_PARAM_C,
6998 IGP01E1000_PHY_AGC_PARAM_D}; 6998 IGP01E1000_PHY_AGC_PARAM_D};
6999 uint16_t min_length, max_length; 6999 u16 min_length, max_length;
7000 7000
7001 DEBUGFUNC("e1000_config_dsp_after_link_change"); 7001 DEBUGFUNC("e1000_config_dsp_after_link_change");
7002 7002
@@ -7038,8 +7038,8 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7038 if ((hw->ffe_config_state == e1000_ffe_config_enabled) && 7038 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7039 (min_length < e1000_igp_cable_length_50)) { 7039 (min_length < e1000_igp_cable_length_50)) {
7040 7040
7041 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7041 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7042 uint32_t idle_errs = 0; 7042 u32 idle_errs = 0;
7043 7043
7044 /* clear previous idle error counts */ 7044 /* clear previous idle error counts */
7045 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7045 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
@@ -7173,11 +7173,11 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7173 * 7173 *
7174 * hw - Struct containing variables accessed by shared code 7174 * hw - Struct containing variables accessed by shared code
7175 ****************************************************************************/ 7175 ****************************************************************************/
7176static int32_t 7176static s32
7177e1000_set_phy_mode(struct e1000_hw *hw) 7177e1000_set_phy_mode(struct e1000_hw *hw)
7178{ 7178{
7179 int32_t ret_val; 7179 s32 ret_val;
7180 uint16_t eeprom_data; 7180 u16 eeprom_data;
7181 7181
7182 DEBUGFUNC("e1000_set_phy_mode"); 7182 DEBUGFUNC("e1000_set_phy_mode");
7183 7183
@@ -7218,13 +7218,13 @@ e1000_set_phy_mode(struct e1000_hw *hw)
7218 * 7218 *
7219 ****************************************************************************/ 7219 ****************************************************************************/
7220 7220
7221static int32_t 7221static s32
7222e1000_set_d3_lplu_state(struct e1000_hw *hw, 7222e1000_set_d3_lplu_state(struct e1000_hw *hw,
7223 bool active) 7223 bool active)
7224{ 7224{
7225 uint32_t phy_ctrl = 0; 7225 u32 phy_ctrl = 0;
7226 int32_t ret_val; 7226 s32 ret_val;
7227 uint16_t phy_data; 7227 u16 phy_data;
7228 DEBUGFUNC("e1000_set_d3_lplu_state"); 7228 DEBUGFUNC("e1000_set_d3_lplu_state");
7229 7229
7230 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 7230 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
@@ -7348,13 +7348,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7348 * 7348 *
7349 ****************************************************************************/ 7349 ****************************************************************************/
7350 7350
7351static int32_t 7351static s32
7352e1000_set_d0_lplu_state(struct e1000_hw *hw, 7352e1000_set_d0_lplu_state(struct e1000_hw *hw,
7353 bool active) 7353 bool active)
7354{ 7354{
7355 uint32_t phy_ctrl = 0; 7355 u32 phy_ctrl = 0;
7356 int32_t ret_val; 7356 s32 ret_val;
7357 uint16_t phy_data; 7357 u16 phy_data;
7358 DEBUGFUNC("e1000_set_d0_lplu_state"); 7358 DEBUGFUNC("e1000_set_d0_lplu_state");
7359 7359
7360 if (hw->mac_type <= e1000_82547_rev_2) 7360 if (hw->mac_type <= e1000_82547_rev_2)
@@ -7439,12 +7439,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7439 * 7439 *
7440 * hw - Struct containing variables accessed by shared code 7440 * hw - Struct containing variables accessed by shared code
7441 *****************************************************************************/ 7441 *****************************************************************************/
7442static int32_t 7442static s32
7443e1000_set_vco_speed(struct e1000_hw *hw) 7443e1000_set_vco_speed(struct e1000_hw *hw)
7444{ 7444{
7445 int32_t ret_val; 7445 s32 ret_val;
7446 uint16_t default_page = 0; 7446 u16 default_page = 0;
7447 uint16_t phy_data; 7447 u16 phy_data;
7448 7448
7449 DEBUGFUNC("e1000_set_vco_speed"); 7449 DEBUGFUNC("e1000_set_vco_speed");
7450 7450
@@ -7503,18 +7503,18 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7503 * 7503 *
7504 * returns: - E1000_SUCCESS . 7504 * returns: - E1000_SUCCESS .
7505 ****************************************************************************/ 7505 ****************************************************************************/
7506static int32_t 7506static s32
7507e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) 7507e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer)
7508{ 7508{
7509 uint8_t i; 7509 u8 i;
7510 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 7510 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7511 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 7511 u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7512 7512
7513 length = (length >> 2); 7513 length = (length >> 2);
7514 offset = (offset >> 2); 7514 offset = (offset >> 2);
7515 7515
7516 for (i = 0; i < length; i++) { 7516 for (i = 0; i < length; i++) {
7517 *((uint32_t *) buffer + i) = 7517 *((u32 *) buffer + i) =
7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7519 } 7519 }
7520 return E1000_SUCCESS; 7520 return E1000_SUCCESS;
@@ -7530,11 +7530,11 @@ e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7530 * timeout 7530 * timeout
7531 * - E1000_SUCCESS for success. 7531 * - E1000_SUCCESS for success.
7532 ****************************************************************************/ 7532 ****************************************************************************/
7533static int32_t 7533static s32
7534e1000_mng_enable_host_if(struct e1000_hw * hw) 7534e1000_mng_enable_host_if(struct e1000_hw * hw)
7535{ 7535{
7536 uint32_t hicr; 7536 u32 hicr;
7537 uint8_t i; 7537 u8 i;
7538 7538
7539 /* Check that the host interface is enabled. */ 7539 /* Check that the host interface is enabled. */
7540 hicr = E1000_READ_REG(hw, HICR); 7540 hicr = E1000_READ_REG(hw, HICR);
@@ -7564,14 +7564,14 @@ e1000_mng_enable_host_if(struct e1000_hw * hw)
7564 * 7564 *
7565 * returns - E1000_SUCCESS for success. 7565 * returns - E1000_SUCCESS for success.
7566 ****************************************************************************/ 7566 ****************************************************************************/
7567static int32_t 7567static s32
7568e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, 7568e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer,
7569 uint16_t length, uint16_t offset, uint8_t *sum) 7569 u16 length, u16 offset, u8 *sum)
7570{ 7570{
7571 uint8_t *tmp; 7571 u8 *tmp;
7572 uint8_t *bufptr = buffer; 7572 u8 *bufptr = buffer;
7573 uint32_t data = 0; 7573 u32 data = 0;
7574 uint16_t remaining, i, j, prev_bytes; 7574 u16 remaining, i, j, prev_bytes;
7575 7575
7576 /* sum = only sum of the data and it is not checksum */ 7576 /* sum = only sum of the data and it is not checksum */
7577 7577
@@ -7579,14 +7579,14 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7579 return -E1000_ERR_PARAM; 7579 return -E1000_ERR_PARAM;
7580 } 7580 }
7581 7581
7582 tmp = (uint8_t *)&data; 7582 tmp = (u8 *)&data;
7583 prev_bytes = offset & 0x3; 7583 prev_bytes = offset & 0x3;
7584 offset &= 0xFFFC; 7584 offset &= 0xFFFC;
7585 offset >>= 2; 7585 offset >>= 2;
7586 7586
7587 if (prev_bytes) { 7587 if (prev_bytes) {
7588 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); 7588 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7589 for (j = prev_bytes; j < sizeof(uint32_t); j++) { 7589 for (j = prev_bytes; j < sizeof(u32); j++) {
7590 *(tmp + j) = *bufptr++; 7590 *(tmp + j) = *bufptr++;
7591 *sum += *(tmp + j); 7591 *sum += *(tmp + j);
7592 } 7592 }
@@ -7604,7 +7604,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7604 /* The device driver writes the relevant command block into the 7604 /* The device driver writes the relevant command block into the
7605 * ram area. */ 7605 * ram area. */
7606 for (i = 0; i < length; i++) { 7606 for (i = 0; i < length; i++) {
7607 for (j = 0; j < sizeof(uint32_t); j++) { 7607 for (j = 0; j < sizeof(u32); j++) {
7608 *(tmp + j) = *bufptr++; 7608 *(tmp + j) = *bufptr++;
7609 *sum += *(tmp + j); 7609 *sum += *(tmp + j);
7610 } 7610 }
@@ -7612,7 +7612,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7612 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); 7612 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7613 } 7613 }
7614 if (remaining) { 7614 if (remaining) {
7615 for (j = 0; j < sizeof(uint32_t); j++) { 7615 for (j = 0; j < sizeof(u32); j++) {
7616 if (j < remaining) 7616 if (j < remaining)
7617 *(tmp + j) = *bufptr++; 7617 *(tmp + j) = *bufptr++;
7618 else 7618 else
@@ -7632,23 +7632,23 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7632 * 7632 *
7633 * returns - E1000_SUCCESS for success. 7633 * returns - E1000_SUCCESS for success.
7634 ****************************************************************************/ 7634 ****************************************************************************/
7635static int32_t 7635static s32
7636e1000_mng_write_cmd_header(struct e1000_hw * hw, 7636e1000_mng_write_cmd_header(struct e1000_hw * hw,
7637 struct e1000_host_mng_command_header * hdr) 7637 struct e1000_host_mng_command_header * hdr)
7638{ 7638{
7639 uint16_t i; 7639 u16 i;
7640 uint8_t sum; 7640 u8 sum;
7641 uint8_t *buffer; 7641 u8 *buffer;
7642 7642
7643 /* Write the whole command header structure which includes sum of 7643 /* Write the whole command header structure which includes sum of
7644 * the buffer */ 7644 * the buffer */
7645 7645
7646 uint16_t length = sizeof(struct e1000_host_mng_command_header); 7646 u16 length = sizeof(struct e1000_host_mng_command_header);
7647 7647
7648 sum = hdr->checksum; 7648 sum = hdr->checksum;
7649 hdr->checksum = 0; 7649 hdr->checksum = 0;
7650 7650
7651 buffer = (uint8_t *) hdr; 7651 buffer = (u8 *) hdr;
7652 i = length; 7652 i = length;
7653 while (i--) 7653 while (i--)
7654 sum += buffer[i]; 7654 sum += buffer[i];
@@ -7658,7 +7658,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7658 length >>= 2; 7658 length >>= 2;
7659 /* The device driver writes the relevant command block into the ram area. */ 7659 /* The device driver writes the relevant command block into the ram area. */
7660 for (i = 0; i < length; i++) { 7660 for (i = 0; i < length; i++) {
7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i));
7662 E1000_WRITE_FLUSH(hw); 7662 E1000_WRITE_FLUSH(hw);
7663 } 7663 }
7664 7664
@@ -7672,10 +7672,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7672 * 7672 *
7673 * returns - E1000_SUCCESS for success. 7673 * returns - E1000_SUCCESS for success.
7674 ****************************************************************************/ 7674 ****************************************************************************/
7675static int32_t 7675static s32
7676e1000_mng_write_commit(struct e1000_hw * hw) 7676e1000_mng_write_commit(struct e1000_hw * hw)
7677{ 7677{
7678 uint32_t hicr; 7678 u32 hicr;
7679 7679
7680 hicr = E1000_READ_REG(hw, HICR); 7680 hicr = E1000_READ_REG(hw, HICR);
7681 /* Setting this bit tells the ARC that a new command is pending. */ 7681 /* Setting this bit tells the ARC that a new command is pending. */
@@ -7693,7 +7693,7 @@ e1000_mng_write_commit(struct e1000_hw * hw)
7693bool 7693bool
7694e1000_check_mng_mode(struct e1000_hw *hw) 7694e1000_check_mng_mode(struct e1000_hw *hw)
7695{ 7695{
7696 uint32_t fwsm; 7696 u32 fwsm;
7697 7697
7698 fwsm = E1000_READ_REG(hw, FWSM); 7698 fwsm = E1000_READ_REG(hw, FWSM);
7699 7699
@@ -7712,11 +7712,11 @@ e1000_check_mng_mode(struct e1000_hw *hw)
7712/***************************************************************************** 7712/*****************************************************************************
7713 * This function writes the dhcp info . 7713 * This function writes the dhcp info .
7714 ****************************************************************************/ 7714 ****************************************************************************/
7715int32_t 7715s32
7716e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, 7716e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer,
7717 uint16_t length) 7717 u16 length)
7718{ 7718{
7719 int32_t ret_val; 7719 s32 ret_val;
7720 struct e1000_host_mng_command_header hdr; 7720 struct e1000_host_mng_command_header hdr;
7721 7721
7722 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; 7722 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
@@ -7744,11 +7744,11 @@ e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7744 * 7744 *
7745 * returns - checksum of buffer contents. 7745 * returns - checksum of buffer contents.
7746 ****************************************************************************/ 7746 ****************************************************************************/
7747static uint8_t 7747static u8
7748e1000_calculate_mng_checksum(char *buffer, uint32_t length) 7748e1000_calculate_mng_checksum(char *buffer, u32 length)
7749{ 7749{
7750 uint8_t sum = 0; 7750 u8 sum = 0;
7751 uint32_t i; 7751 u32 i;
7752 7752
7753 if (!buffer) 7753 if (!buffer)
7754 return 0; 7754 return 0;
@@ -7756,7 +7756,7 @@ e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7756 for (i=0; i < length; i++) 7756 for (i=0; i < length; i++)
7757 sum += buffer[i]; 7757 sum += buffer[i];
7758 7758
7759 return (uint8_t) (0 - sum); 7759 return (u8) (0 - sum);
7760} 7760}
7761 7761
7762/***************************************************************************** 7762/*****************************************************************************
@@ -7769,10 +7769,10 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7769{ 7769{
7770 /* called in init as well as watchdog timer functions */ 7770 /* called in init as well as watchdog timer functions */
7771 7771
7772 int32_t ret_val, checksum; 7772 s32 ret_val, checksum;
7773 bool tx_filter = false; 7773 bool tx_filter = false;
7774 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 7774 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7775 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); 7775 u8 *buffer = (u8 *) &(hw->mng_cookie);
7776 7776
7777 if (e1000_check_mng_mode(hw)) { 7777 if (e1000_check_mng_mode(hw)) {
7778 ret_val = e1000_mng_enable_host_if(hw); 7778 ret_val = e1000_mng_enable_host_if(hw);
@@ -7806,11 +7806,11 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7806 * returns: - true/false 7806 * returns: - true/false
7807 * 7807 *
7808 *****************************************************************************/ 7808 *****************************************************************************/
7809uint32_t 7809u32
7810e1000_enable_mng_pass_thru(struct e1000_hw *hw) 7810e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7811{ 7811{
7812 uint32_t manc; 7812 u32 manc;
7813 uint32_t fwsm, factps; 7813 u32 fwsm, factps;
7814 7814
7815 if (hw->asf_firmware_present) { 7815 if (hw->asf_firmware_present) {
7816 manc = E1000_READ_REG(hw, MANC); 7816 manc = E1000_READ_REG(hw, MANC);
@@ -7832,12 +7832,12 @@ e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7832 return false; 7832 return false;
7833} 7833}
7834 7834
7835static int32_t 7835static s32
7836e1000_polarity_reversal_workaround(struct e1000_hw *hw) 7836e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7837{ 7837{
7838 int32_t ret_val; 7838 s32 ret_val;
7839 uint16_t mii_status_reg; 7839 u16 mii_status_reg;
7840 uint16_t i; 7840 u16 i;
7841 7841
7842 /* Polarity reversal workaround for forced 10F/10H links. */ 7842 /* Polarity reversal workaround for forced 10F/10H links. */
7843 7843
@@ -7929,7 +7929,7 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7929static void 7929static void
7930e1000_set_pci_express_master_disable(struct e1000_hw *hw) 7930e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7931{ 7931{
7932 uint32_t ctrl; 7932 u32 ctrl;
7933 7933
7934 DEBUGFUNC("e1000_set_pci_express_master_disable"); 7934 DEBUGFUNC("e1000_set_pci_express_master_disable");
7935 7935
@@ -7952,10 +7952,10 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7952 * E1000_SUCCESS master requests disabled. 7952 * E1000_SUCCESS master requests disabled.
7953 * 7953 *
7954 ******************************************************************************/ 7954 ******************************************************************************/
7955int32_t 7955s32
7956e1000_disable_pciex_master(struct e1000_hw *hw) 7956e1000_disable_pciex_master(struct e1000_hw *hw)
7957{ 7957{
7958 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 7958 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7959 7959
7960 DEBUGFUNC("e1000_disable_pciex_master"); 7960 DEBUGFUNC("e1000_disable_pciex_master");
7961 7961
@@ -7990,10 +7990,10 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7990 * E1000_SUCCESS at any other case. 7990 * E1000_SUCCESS at any other case.
7991 * 7991 *
7992 ******************************************************************************/ 7992 ******************************************************************************/
7993static int32_t 7993static s32
7994e1000_get_auto_rd_done(struct e1000_hw *hw) 7994e1000_get_auto_rd_done(struct e1000_hw *hw)
7995{ 7995{
7996 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 7996 s32 timeout = AUTO_READ_DONE_TIMEOUT;
7997 7997
7998 DEBUGFUNC("e1000_get_auto_rd_done"); 7998 DEBUGFUNC("e1000_get_auto_rd_done");
7999 7999
@@ -8038,11 +8038,11 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8038 * E1000_SUCCESS at any other case. 8038 * E1000_SUCCESS at any other case.
8039 * 8039 *
8040 ***************************************************************************/ 8040 ***************************************************************************/
8041static int32_t 8041static s32
8042e1000_get_phy_cfg_done(struct e1000_hw *hw) 8042e1000_get_phy_cfg_done(struct e1000_hw *hw)
8043{ 8043{
8044 int32_t timeout = PHY_CFG_TIMEOUT; 8044 s32 timeout = PHY_CFG_TIMEOUT;
8045 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 8045 u32 cfg_mask = E1000_EEPROM_CFG_DONE;
8046 8046
8047 DEBUGFUNC("e1000_get_phy_cfg_done"); 8047 DEBUGFUNC("e1000_get_phy_cfg_done");
8048 8048
@@ -8085,11 +8085,11 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8085 * E1000_SUCCESS at any other case. 8085 * E1000_SUCCESS at any other case.
8086 * 8086 *
8087 ***************************************************************************/ 8087 ***************************************************************************/
8088static int32_t 8088static s32
8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090{ 8090{
8091 int32_t timeout; 8091 s32 timeout;
8092 uint32_t swsm; 8092 u32 swsm;
8093 8093
8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); 8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8095 8095
@@ -8138,7 +8138,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8138static void 8138static void
8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8140{ 8140{
8141 uint32_t swsm; 8141 u32 swsm;
8142 8142
8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); 8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8144 8144
@@ -8164,11 +8164,11 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8164 * E1000_SUCCESS at any other case. 8164 * E1000_SUCCESS at any other case.
8165 * 8165 *
8166 ***************************************************************************/ 8166 ***************************************************************************/
8167static int32_t 8167static s32
8168e1000_get_software_semaphore(struct e1000_hw *hw) 8168e1000_get_software_semaphore(struct e1000_hw *hw)
8169{ 8169{
8170 int32_t timeout = hw->eeprom.word_size + 1; 8170 s32 timeout = hw->eeprom.word_size + 1;
8171 uint32_t swsm; 8171 u32 swsm;
8172 8172
8173 DEBUGFUNC("e1000_get_software_semaphore"); 8173 DEBUGFUNC("e1000_get_software_semaphore");
8174 8174
@@ -8203,7 +8203,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8203static void 8203static void
8204e1000_release_software_semaphore(struct e1000_hw *hw) 8204e1000_release_software_semaphore(struct e1000_hw *hw)
8205{ 8205{
8206 uint32_t swsm; 8206 u32 swsm;
8207 8207
8208 DEBUGFUNC("e1000_release_software_semaphore"); 8208 DEBUGFUNC("e1000_release_software_semaphore");
8209 8209
@@ -8228,11 +8228,11 @@ e1000_release_software_semaphore(struct e1000_hw *hw)
8228 * E1000_SUCCESS 8228 * E1000_SUCCESS
8229 * 8229 *
8230 *****************************************************************************/ 8230 *****************************************************************************/
8231int32_t 8231s32
8232e1000_check_phy_reset_block(struct e1000_hw *hw) 8232e1000_check_phy_reset_block(struct e1000_hw *hw)
8233{ 8233{
8234 uint32_t manc = 0; 8234 u32 manc = 0;
8235 uint32_t fwsm = 0; 8235 u32 fwsm = 0;
8236 8236
8237 if (hw->mac_type == e1000_ich8lan) { 8237 if (hw->mac_type == e1000_ich8lan) {
8238 fwsm = E1000_READ_REG(hw, FWSM); 8238 fwsm = E1000_READ_REG(hw, FWSM);
@@ -8246,10 +8246,10 @@ e1000_check_phy_reset_block(struct e1000_hw *hw)
8246 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8246 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8247} 8247}
8248 8248
8249static uint8_t 8249static u8
8250e1000_arc_subsystem_valid(struct e1000_hw *hw) 8250e1000_arc_subsystem_valid(struct e1000_hw *hw)
8251{ 8251{
8252 uint32_t fwsm; 8252 u32 fwsm;
8253 8253
8254 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC 8254 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8255 * may not be provided a DMA clock when no manageability features are 8255 * may not be provided a DMA clock when no manageability features are
@@ -8283,10 +8283,10 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8283 * returns: E1000_SUCCESS 8283 * returns: E1000_SUCCESS
8284 * 8284 *
8285 *****************************************************************************/ 8285 *****************************************************************************/
8286static int32_t 8286static s32
8287e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) 8287e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8288{ 8288{
8289 uint32_t gcr_reg = 0; 8289 u32 gcr_reg = 0;
8290 8290
8291 DEBUGFUNC("e1000_set_pci_ex_no_snoop"); 8291 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8292 8292
@@ -8303,7 +8303,7 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8303 E1000_WRITE_REG(hw, GCR, gcr_reg); 8303 E1000_WRITE_REG(hw, GCR, gcr_reg);
8304 } 8304 }
8305 if (hw->mac_type == e1000_ich8lan) { 8305 if (hw->mac_type == e1000_ich8lan) {
8306 uint32_t ctrl_ext; 8306 u32 ctrl_ext;
8307 8307
8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); 8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8309 8309
@@ -8324,11 +8324,11 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8324 * hw: Struct containing variables accessed by shared code 8324 * hw: Struct containing variables accessed by shared code
8325 * 8325 *
8326 ***************************************************************************/ 8326 ***************************************************************************/
8327static int32_t 8327static s32
8328e1000_get_software_flag(struct e1000_hw *hw) 8328e1000_get_software_flag(struct e1000_hw *hw)
8329{ 8329{
8330 int32_t timeout = PHY_CFG_TIMEOUT; 8330 s32 timeout = PHY_CFG_TIMEOUT;
8331 uint32_t extcnf_ctrl; 8331 u32 extcnf_ctrl;
8332 8332
8333 DEBUGFUNC("e1000_get_software_flag"); 8333 DEBUGFUNC("e1000_get_software_flag");
8334 8334
@@ -8366,7 +8366,7 @@ e1000_get_software_flag(struct e1000_hw *hw)
8366static void 8366static void
8367e1000_release_software_flag(struct e1000_hw *hw) 8367e1000_release_software_flag(struct e1000_hw *hw)
8368{ 8368{
8369 uint32_t extcnf_ctrl; 8369 u32 extcnf_ctrl;
8370 8370
8371 DEBUGFUNC("e1000_release_software_flag"); 8371 DEBUGFUNC("e1000_release_software_flag");
8372 8372
@@ -8388,16 +8388,16 @@ e1000_release_software_flag(struct e1000_hw *hw)
8388 * data - word read from the EEPROM 8388 * data - word read from the EEPROM
8389 * words - number of words to read 8389 * words - number of words to read
8390 *****************************************************************************/ 8390 *****************************************************************************/
8391static int32_t 8391static s32
8392e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, 8392e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8393 uint16_t *data) 8393 u16 *data)
8394{ 8394{
8395 int32_t error = E1000_SUCCESS; 8395 s32 error = E1000_SUCCESS;
8396 uint32_t flash_bank = 0; 8396 u32 flash_bank = 0;
8397 uint32_t act_offset = 0; 8397 u32 act_offset = 0;
8398 uint32_t bank_offset = 0; 8398 u32 bank_offset = 0;
8399 uint16_t word = 0; 8399 u16 word = 0;
8400 uint16_t i = 0; 8400 u16 i = 0;
8401 8401
8402 /* We need to know which is the valid flash bank. In the event 8402 /* We need to know which is the valid flash bank. In the event
8403 * that we didn't allocate eeprom_shadow_ram, we may not be 8403 * that we didn't allocate eeprom_shadow_ram, we may not be
@@ -8444,12 +8444,12 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8444 * words - number of words to write 8444 * words - number of words to write
8445 * data - words to write to the EEPROM 8445 * data - words to write to the EEPROM
8446 *****************************************************************************/ 8446 *****************************************************************************/
8447static int32_t 8447static s32
8448e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, 8448e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8449 uint16_t *data) 8449 u16 *data)
8450{ 8450{
8451 uint32_t i = 0; 8451 u32 i = 0;
8452 int32_t error = E1000_SUCCESS; 8452 s32 error = E1000_SUCCESS;
8453 8453
8454 error = e1000_get_software_flag(hw); 8454 error = e1000_get_software_flag(hw);
8455 if (error != E1000_SUCCESS) 8455 if (error != E1000_SUCCESS)
@@ -8491,12 +8491,12 @@ e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8491 * 8491 *
8492 * hw - The pointer to the hw structure 8492 * hw - The pointer to the hw structure
8493 ****************************************************************************/ 8493 ****************************************************************************/
8494static int32_t 8494static s32
8495e1000_ich8_cycle_init(struct e1000_hw *hw) 8495e1000_ich8_cycle_init(struct e1000_hw *hw)
8496{ 8496{
8497 union ich8_hws_flash_status hsfsts; 8497 union ich8_hws_flash_status hsfsts;
8498 int32_t error = E1000_ERR_EEPROM; 8498 s32 error = E1000_ERR_EEPROM;
8499 int32_t i = 0; 8499 s32 i = 0;
8500 8500
8501 DEBUGFUNC("e1000_ich8_cycle_init"); 8501 DEBUGFUNC("e1000_ich8_cycle_init");
8502 8502
@@ -8558,13 +8558,13 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8558 * 8558 *
8559 * hw - The pointer to the hw structure 8559 * hw - The pointer to the hw structure
8560 ****************************************************************************/ 8560 ****************************************************************************/
8561static int32_t 8561static s32
8562e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) 8562e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8563{ 8563{
8564 union ich8_hws_flash_ctrl hsflctl; 8564 union ich8_hws_flash_ctrl hsflctl;
8565 union ich8_hws_flash_status hsfsts; 8565 union ich8_hws_flash_status hsfsts;
8566 int32_t error = E1000_ERR_EEPROM; 8566 s32 error = E1000_ERR_EEPROM;
8567 uint32_t i = 0; 8567 u32 i = 0;
8568 8568
8569 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 8569 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8570 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8570 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
@@ -8593,16 +8593,16 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8593 * size - Size of data to read, 1=byte 2=word 8593 * size - Size of data to read, 1=byte 2=word
8594 * data - Pointer to the word to store the value read. 8594 * data - Pointer to the word to store the value read.
8595 *****************************************************************************/ 8595 *****************************************************************************/
8596static int32_t 8596static s32
8597e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, 8597e1000_read_ich8_data(struct e1000_hw *hw, u32 index,
8598 uint32_t size, uint16_t* data) 8598 u32 size, u16* data)
8599{ 8599{
8600 union ich8_hws_flash_status hsfsts; 8600 union ich8_hws_flash_status hsfsts;
8601 union ich8_hws_flash_ctrl hsflctl; 8601 union ich8_hws_flash_ctrl hsflctl;
8602 uint32_t flash_linear_address; 8602 u32 flash_linear_address;
8603 uint32_t flash_data = 0; 8603 u32 flash_data = 0;
8604 int32_t error = -E1000_ERR_EEPROM; 8604 s32 error = -E1000_ERR_EEPROM;
8605 int32_t count = 0; 8605 s32 count = 0;
8606 8606
8607 DEBUGFUNC("e1000_read_ich8_data"); 8607 DEBUGFUNC("e1000_read_ich8_data");
8608 8608
@@ -8640,9 +8640,9 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8640 if (error == E1000_SUCCESS) { 8640 if (error == E1000_SUCCESS) {
8641 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); 8641 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8642 if (size == 1) { 8642 if (size == 1) {
8643 *data = (uint8_t)(flash_data & 0x000000FF); 8643 *data = (u8)(flash_data & 0x000000FF);
8644 } else if (size == 2) { 8644 } else if (size == 2) {
8645 *data = (uint16_t)(flash_data & 0x0000FFFF); 8645 *data = (u16)(flash_data & 0x0000FFFF);
8646 } 8646 }
8647 break; 8647 break;
8648 } else { 8648 } else {
@@ -8672,16 +8672,16 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8672 * size - Size of data to read, 1=byte 2=word 8672 * size - Size of data to read, 1=byte 2=word
8673 * data - The byte(s) to write to the NVM. 8673 * data - The byte(s) to write to the NVM.
8674 *****************************************************************************/ 8674 *****************************************************************************/
8675static int32_t 8675static s32
8676e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, 8676e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8677 uint16_t data) 8677 u16 data)
8678{ 8678{
8679 union ich8_hws_flash_status hsfsts; 8679 union ich8_hws_flash_status hsfsts;
8680 union ich8_hws_flash_ctrl hsflctl; 8680 union ich8_hws_flash_ctrl hsflctl;
8681 uint32_t flash_linear_address; 8681 u32 flash_linear_address;
8682 uint32_t flash_data = 0; 8682 u32 flash_data = 0;
8683 int32_t error = -E1000_ERR_EEPROM; 8683 s32 error = -E1000_ERR_EEPROM;
8684 int32_t count = 0; 8684 s32 count = 0;
8685 8685
8686 DEBUGFUNC("e1000_write_ich8_data"); 8686 DEBUGFUNC("e1000_write_ich8_data");
8687 8687
@@ -8710,9 +8710,9 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8710 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 8710 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8711 8711
8712 if (size == 1) 8712 if (size == 1)
8713 flash_data = (uint32_t)data & 0x00FF; 8713 flash_data = (u32)data & 0x00FF;
8714 else 8714 else
8715 flash_data = (uint32_t)data; 8715 flash_data = (u32)data;
8716 8716
8717 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 8717 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8718 8718
@@ -8747,15 +8747,15 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8747 * index - The index of the byte to read. 8747 * index - The index of the byte to read.
8748 * data - Pointer to a byte to store the value read. 8748 * data - Pointer to a byte to store the value read.
8749 *****************************************************************************/ 8749 *****************************************************************************/
8750static int32_t 8750static s32
8751e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) 8751e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8* data)
8752{ 8752{
8753 int32_t status = E1000_SUCCESS; 8753 s32 status = E1000_SUCCESS;
8754 uint16_t word = 0; 8754 u16 word = 0;
8755 8755
8756 status = e1000_read_ich8_data(hw, index, 1, &word); 8756 status = e1000_read_ich8_data(hw, index, 1, &word);
8757 if (status == E1000_SUCCESS) { 8757 if (status == E1000_SUCCESS) {
8758 *data = (uint8_t)word; 8758 *data = (u8)word;
8759 } 8759 }
8760 8760
8761 return status; 8761 return status;
@@ -8770,11 +8770,11 @@ e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8770 * index - The index of the byte to write. 8770 * index - The index of the byte to write.
8771 * byte - The byte to write to the NVM. 8771 * byte - The byte to write to the NVM.
8772 *****************************************************************************/ 8772 *****************************************************************************/
8773static int32_t 8773static s32
8774e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) 8774e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8775{ 8775{
8776 int32_t error = E1000_SUCCESS; 8776 s32 error = E1000_SUCCESS;
8777 int32_t program_retries = 0; 8777 s32 program_retries = 0;
8778 8778
8779 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 8779 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8780 8780
@@ -8803,11 +8803,11 @@ e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8803 * index - The index of the byte to read. 8803 * index - The index of the byte to read.
8804 * data - The byte to write to the NVM. 8804 * data - The byte to write to the NVM.
8805 *****************************************************************************/ 8805 *****************************************************************************/
8806static int32_t 8806static s32
8807e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) 8807e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8808{ 8808{
8809 int32_t status = E1000_SUCCESS; 8809 s32 status = E1000_SUCCESS;
8810 uint16_t word = (uint16_t)data; 8810 u16 word = (u16)data;
8811 8811
8812 status = e1000_write_ich8_data(hw, index, 1, word); 8812 status = e1000_write_ich8_data(hw, index, 1, word);
8813 8813
@@ -8821,10 +8821,10 @@ e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8821 * index - The starting byte index of the word to read. 8821 * index - The starting byte index of the word to read.
8822 * data - Pointer to a word to store the value read. 8822 * data - Pointer to a word to store the value read.
8823 *****************************************************************************/ 8823 *****************************************************************************/
8824static int32_t 8824static s32
8825e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) 8825e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8826{ 8826{
8827 int32_t status = E1000_SUCCESS; 8827 s32 status = E1000_SUCCESS;
8828 status = e1000_read_ich8_data(hw, index, 2, data); 8828 status = e1000_read_ich8_data(hw, index, 2, data);
8829 return status; 8829 return status;
8830} 8830}
@@ -8840,19 +8840,19 @@ e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8840 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 8840 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8841 * bank size may be 4, 8 or 64 KBytes 8841 * bank size may be 4, 8 or 64 KBytes
8842 *****************************************************************************/ 8842 *****************************************************************************/
8843static int32_t 8843static s32
8844e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) 8844e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8845{ 8845{
8846 union ich8_hws_flash_status hsfsts; 8846 union ich8_hws_flash_status hsfsts;
8847 union ich8_hws_flash_ctrl hsflctl; 8847 union ich8_hws_flash_ctrl hsflctl;
8848 uint32_t flash_linear_address; 8848 u32 flash_linear_address;
8849 int32_t count = 0; 8849 s32 count = 0;
8850 int32_t error = E1000_ERR_EEPROM; 8850 s32 error = E1000_ERR_EEPROM;
8851 int32_t iteration; 8851 s32 iteration;
8852 int32_t sub_sector_size = 0; 8852 s32 sub_sector_size = 0;
8853 int32_t bank_size; 8853 s32 bank_size;
8854 int32_t j = 0; 8854 s32 j = 0;
8855 int32_t error_flag = 0; 8855 s32 error_flag = 0;
8856 8856
8857 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8857 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8858 8858
@@ -8930,16 +8930,16 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8930 return error; 8930 return error;
8931} 8931}
8932 8932
8933static int32_t 8933static s32
8934e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, 8934e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8935 uint32_t cnf_base_addr, uint32_t cnf_size) 8935 u32 cnf_base_addr, u32 cnf_size)
8936{ 8936{
8937 uint32_t ret_val = E1000_SUCCESS; 8937 u32 ret_val = E1000_SUCCESS;
8938 uint16_t word_addr, reg_data, reg_addr; 8938 u16 word_addr, reg_data, reg_addr;
8939 uint16_t i; 8939 u16 i;
8940 8940
8941 /* cnf_base_addr is in DWORD */ 8941 /* cnf_base_addr is in DWORD */
8942 word_addr = (uint16_t)(cnf_base_addr << 1); 8942 word_addr = (u16)(cnf_base_addr << 1);
8943 8943
8944 /* cnf_size is returned in size of dwords */ 8944 /* cnf_size is returned in size of dwords */
8945 for (i = 0; i < cnf_size; i++) { 8945 for (i = 0; i < cnf_size; i++) {
@@ -8955,7 +8955,7 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8955 if (ret_val != E1000_SUCCESS) 8955 if (ret_val != E1000_SUCCESS)
8956 return ret_val; 8956 return ret_val;
8957 8957
8958 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); 8958 ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
8959 8959
8960 e1000_release_software_flag(hw); 8960 e1000_release_software_flag(hw);
8961 } 8961 }
@@ -8972,10 +8972,10 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8972 * 8972 *
8973 * hw: Struct containing variables accessed by shared code 8973 * hw: Struct containing variables accessed by shared code
8974 *****************************************************************************/ 8974 *****************************************************************************/
8975static int32_t 8975static s32
8976e1000_init_lcd_from_nvm(struct e1000_hw *hw) 8976e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8977{ 8977{
8978 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; 8978 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8979 8979
8980 if (hw->phy_type != e1000_phy_igp_3) 8980 if (hw->phy_type != e1000_phy_igp_3)
8981 return E1000_SUCCESS; 8981 return E1000_SUCCESS;
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 572a7b6dc12e..99fce2c5dd26 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -100,7 +100,7 @@ typedef enum {
100} e1000_fc_type; 100} e1000_fc_type;
101 101
102struct e1000_shadow_ram { 102struct e1000_shadow_ram {
103 uint16_t eeprom_word; 103 u16 eeprom_word;
104 bool modified; 104 bool modified;
105}; 105};
106 106
@@ -263,17 +263,17 @@ struct e1000_phy_info {
263}; 263};
264 264
265struct e1000_phy_stats { 265struct e1000_phy_stats {
266 uint32_t idle_errors; 266 u32 idle_errors;
267 uint32_t receive_errors; 267 u32 receive_errors;
268}; 268};
269 269
270struct e1000_eeprom_info { 270struct e1000_eeprom_info {
271 e1000_eeprom_type type; 271 e1000_eeprom_type type;
272 uint16_t word_size; 272 u16 word_size;
273 uint16_t opcode_bits; 273 u16 opcode_bits;
274 uint16_t address_bits; 274 u16 address_bits;
275 uint16_t delay_usec; 275 u16 delay_usec;
276 uint16_t page_size; 276 u16 page_size;
277 bool use_eerd; 277 bool use_eerd;
278 bool use_eewr; 278 bool use_eewr;
279}; 279};
@@ -308,34 +308,34 @@ typedef enum {
308 308
309/* Function prototypes */ 309/* Function prototypes */
310/* Initialization */ 310/* Initialization */
311int32_t e1000_reset_hw(struct e1000_hw *hw); 311s32 e1000_reset_hw(struct e1000_hw *hw);
312int32_t e1000_init_hw(struct e1000_hw *hw); 312s32 e1000_init_hw(struct e1000_hw *hw);
313int32_t e1000_set_mac_type(struct e1000_hw *hw); 313s32 e1000_set_mac_type(struct e1000_hw *hw);
314void e1000_set_media_type(struct e1000_hw *hw); 314void e1000_set_media_type(struct e1000_hw *hw);
315 315
316/* Link Configuration */ 316/* Link Configuration */
317int32_t e1000_setup_link(struct e1000_hw *hw); 317s32 e1000_setup_link(struct e1000_hw *hw);
318int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw); 318s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
319void e1000_config_collision_dist(struct e1000_hw *hw); 319void e1000_config_collision_dist(struct e1000_hw *hw);
320int32_t e1000_check_for_link(struct e1000_hw *hw); 320s32 e1000_check_for_link(struct e1000_hw *hw);
321int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex); 321s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
322int32_t e1000_force_mac_fc(struct e1000_hw *hw); 322s32 e1000_force_mac_fc(struct e1000_hw *hw);
323 323
324/* PHY */ 324/* PHY */
325int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 325s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data);
326int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 326s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
327int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 327s32 e1000_phy_hw_reset(struct e1000_hw *hw);
328int32_t e1000_phy_reset(struct e1000_hw *hw); 328s32 e1000_phy_reset(struct e1000_hw *hw);
329int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 329s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
330int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 330s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
331 331
332void e1000_phy_powerdown_workaround(struct e1000_hw *hw); 332void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
333 333
334/* EEPROM Functions */ 334/* EEPROM Functions */
335int32_t e1000_init_eeprom_params(struct e1000_hw *hw); 335s32 e1000_init_eeprom_params(struct e1000_hw *hw);
336 336
337/* MNG HOST IF functions */ 337/* MNG HOST IF functions */
338uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); 338u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
339 339
340#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 340#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
341#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 341#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
@@ -354,80 +354,80 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
354#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 354#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
355 355
356struct e1000_host_mng_command_header { 356struct e1000_host_mng_command_header {
357 uint8_t command_id; 357 u8 command_id;
358 uint8_t checksum; 358 u8 checksum;
359 uint16_t reserved1; 359 u16 reserved1;
360 uint16_t reserved2; 360 u16 reserved2;
361 uint16_t command_length; 361 u16 command_length;
362}; 362};
363 363
364struct e1000_host_mng_command_info { 364struct e1000_host_mng_command_info {
365 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 365 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
366 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 366 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
367}; 367};
368#ifdef __BIG_ENDIAN 368#ifdef __BIG_ENDIAN
369struct e1000_host_mng_dhcp_cookie{ 369struct e1000_host_mng_dhcp_cookie{
370 uint32_t signature; 370 u32 signature;
371 uint16_t vlan_id; 371 u16 vlan_id;
372 uint8_t reserved0; 372 u8 reserved0;
373 uint8_t status; 373 u8 status;
374 uint32_t reserved1; 374 u32 reserved1;
375 uint8_t checksum; 375 u8 checksum;
376 uint8_t reserved3; 376 u8 reserved3;
377 uint16_t reserved2; 377 u16 reserved2;
378}; 378};
379#else 379#else
380struct e1000_host_mng_dhcp_cookie{ 380struct e1000_host_mng_dhcp_cookie{
381 uint32_t signature; 381 u32 signature;
382 uint8_t status; 382 u8 status;
383 uint8_t reserved0; 383 u8 reserved0;
384 uint16_t vlan_id; 384 u16 vlan_id;
385 uint32_t reserved1; 385 u32 reserved1;
386 uint16_t reserved2; 386 u16 reserved2;
387 uint8_t reserved3; 387 u8 reserved3;
388 uint8_t checksum; 388 u8 checksum;
389}; 389};
390#endif 390#endif
391 391
392int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, 392s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
393 uint16_t length); 393 u16 length);
394bool e1000_check_mng_mode(struct e1000_hw *hw); 394bool e1000_check_mng_mode(struct e1000_hw *hw);
395bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 395bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
396int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 396s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
397int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 397s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
398int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 398s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
399int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 399s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
400int32_t e1000_read_mac_addr(struct e1000_hw * hw); 400s32 e1000_read_mac_addr(struct e1000_hw * hw);
401 401
402/* Filters (multicast, vlan, receive) */ 402/* Filters (multicast, vlan, receive) */
403uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr); 403u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
404void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value); 404void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
405void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index); 405void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
406void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value); 406void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
407 407
408/* LED functions */ 408/* LED functions */
409int32_t e1000_setup_led(struct e1000_hw *hw); 409s32 e1000_setup_led(struct e1000_hw *hw);
410int32_t e1000_cleanup_led(struct e1000_hw *hw); 410s32 e1000_cleanup_led(struct e1000_hw *hw);
411int32_t e1000_led_on(struct e1000_hw *hw); 411s32 e1000_led_on(struct e1000_hw *hw);
412int32_t e1000_led_off(struct e1000_hw *hw); 412s32 e1000_led_off(struct e1000_hw *hw);
413int32_t e1000_blink_led_start(struct e1000_hw *hw); 413s32 e1000_blink_led_start(struct e1000_hw *hw);
414 414
415/* Adaptive IFS Functions */ 415/* Adaptive IFS Functions */
416 416
417/* Everything else */ 417/* Everything else */
418void e1000_reset_adaptive(struct e1000_hw *hw); 418void e1000_reset_adaptive(struct e1000_hw *hw);
419void e1000_update_adaptive(struct e1000_hw *hw); 419void e1000_update_adaptive(struct e1000_hw *hw);
420void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); 420void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr);
421void e1000_get_bus_info(struct e1000_hw *hw); 421void e1000_get_bus_info(struct e1000_hw *hw);
422void e1000_pci_set_mwi(struct e1000_hw *hw); 422void e1000_pci_set_mwi(struct e1000_hw *hw);
423void e1000_pci_clear_mwi(struct e1000_hw *hw); 423void e1000_pci_clear_mwi(struct e1000_hw *hw);
424int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value); 424s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
425void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); 425void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
426int e1000_pcix_get_mmrbc(struct e1000_hw *hw); 426int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
427/* Port I/O is only supported on 82544 and newer */ 427/* Port I/O is only supported on 82544 and newer */
428void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); 428void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
429int32_t e1000_disable_pciex_master(struct e1000_hw *hw); 429s32 e1000_disable_pciex_master(struct e1000_hw *hw);
430int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 430s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
431 431
432 432
433#define E1000_READ_REG_IO(a, reg) \ 433#define E1000_READ_REG_IO(a, reg) \
@@ -596,8 +596,8 @@ struct e1000_rx_desc {
596 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 596 __le64 buffer_addr; /* Address of the descriptor's data buffer */
597 __le16 length; /* Length of data DMAed into data buffer */ 597 __le16 length; /* Length of data DMAed into data buffer */
598 __le16 csum; /* Packet checksum */ 598 __le16 csum; /* Packet checksum */
599 uint8_t status; /* Descriptor status */ 599 u8 status; /* Descriptor status */
600 uint8_t errors; /* Descriptor Errors */ 600 u8 errors; /* Descriptor Errors */
601 __le16 special; 601 __le16 special;
602}; 602};
603 603
@@ -718,15 +718,15 @@ struct e1000_tx_desc {
718 __le32 data; 718 __le32 data;
719 struct { 719 struct {
720 __le16 length; /* Data buffer length */ 720 __le16 length; /* Data buffer length */
721 uint8_t cso; /* Checksum offset */ 721 u8 cso; /* Checksum offset */
722 uint8_t cmd; /* Descriptor control */ 722 u8 cmd; /* Descriptor control */
723 } flags; 723 } flags;
724 } lower; 724 } lower;
725 union { 725 union {
726 __le32 data; 726 __le32 data;
727 struct { 727 struct {
728 uint8_t status; /* Descriptor status */ 728 u8 status; /* Descriptor status */
729 uint8_t css; /* Checksum start */ 729 u8 css; /* Checksum start */
730 __le16 special; 730 __le16 special;
731 } fields; 731 } fields;
732 } upper; 732 } upper;
@@ -759,16 +759,16 @@ struct e1000_context_desc {
759 union { 759 union {
760 __le32 ip_config; 760 __le32 ip_config;
761 struct { 761 struct {
762 uint8_t ipcss; /* IP checksum start */ 762 u8 ipcss; /* IP checksum start */
763 uint8_t ipcso; /* IP checksum offset */ 763 u8 ipcso; /* IP checksum offset */
764 __le16 ipcse; /* IP checksum end */ 764 __le16 ipcse; /* IP checksum end */
765 } ip_fields; 765 } ip_fields;
766 } lower_setup; 766 } lower_setup;
767 union { 767 union {
768 __le32 tcp_config; 768 __le32 tcp_config;
769 struct { 769 struct {
770 uint8_t tucss; /* TCP checksum start */ 770 u8 tucss; /* TCP checksum start */
771 uint8_t tucso; /* TCP checksum offset */ 771 u8 tucso; /* TCP checksum offset */
772 __le16 tucse; /* TCP checksum end */ 772 __le16 tucse; /* TCP checksum end */
773 } tcp_fields; 773 } tcp_fields;
774 } upper_setup; 774 } upper_setup;
@@ -776,8 +776,8 @@ struct e1000_context_desc {
776 union { 776 union {
777 __le32 data; 777 __le32 data;
778 struct { 778 struct {
779 uint8_t status; /* Descriptor status */ 779 u8 status; /* Descriptor status */
780 uint8_t hdr_len; /* Header length */ 780 u8 hdr_len; /* Header length */
781 __le16 mss; /* Maximum segment size */ 781 __le16 mss; /* Maximum segment size */
782 } fields; 782 } fields;
783 } tcp_seg_setup; 783 } tcp_seg_setup;
@@ -790,15 +790,15 @@ struct e1000_data_desc {
790 __le32 data; 790 __le32 data;
791 struct { 791 struct {
792 __le16 length; /* Data buffer length */ 792 __le16 length; /* Data buffer length */
793 uint8_t typ_len_ext; /* */ 793 u8 typ_len_ext; /* */
794 uint8_t cmd; /* */ 794 u8 cmd; /* */
795 } flags; 795 } flags;
796 } lower; 796 } lower;
797 union { 797 union {
798 __le32 data; 798 __le32 data;
799 struct { 799 struct {
800 uint8_t status; /* Descriptor status */ 800 u8 status; /* Descriptor status */
801 uint8_t popts; /* Packet Options */ 801 u8 popts; /* Packet Options */
802 __le16 special; /* */ 802 __le16 special; /* */
803 } fields; 803 } fields;
804 } upper; 804 } upper;
@@ -825,8 +825,8 @@ struct e1000_rar {
825 825
826/* IPv4 Address Table Entry */ 826/* IPv4 Address Table Entry */
827struct e1000_ipv4_at_entry { 827struct e1000_ipv4_at_entry {
828 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 828 volatile u32 ipv4_addr; /* IP Address (RW) */
829 volatile uint32_t reserved; 829 volatile u32 reserved;
830}; 830};
831 831
832/* Four wakeup IP addresses are supported */ 832/* Four wakeup IP addresses are supported */
@@ -837,25 +837,25 @@ struct e1000_ipv4_at_entry {
837 837
838/* IPv6 Address Table Entry */ 838/* IPv6 Address Table Entry */
839struct e1000_ipv6_at_entry { 839struct e1000_ipv6_at_entry {
840 volatile uint8_t ipv6_addr[16]; 840 volatile u8 ipv6_addr[16];
841}; 841};
842 842
843/* Flexible Filter Length Table Entry */ 843/* Flexible Filter Length Table Entry */
844struct e1000_fflt_entry { 844struct e1000_fflt_entry {
845 volatile uint32_t length; /* Flexible Filter Length (RW) */ 845 volatile u32 length; /* Flexible Filter Length (RW) */
846 volatile uint32_t reserved; 846 volatile u32 reserved;
847}; 847};
848 848
849/* Flexible Filter Mask Table Entry */ 849/* Flexible Filter Mask Table Entry */
850struct e1000_ffmt_entry { 850struct e1000_ffmt_entry {
851 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 851 volatile u32 mask; /* Flexible Filter Mask (RW) */
852 volatile uint32_t reserved; 852 volatile u32 reserved;
853}; 853};
854 854
855/* Flexible Filter Value Table Entry */ 855/* Flexible Filter Value Table Entry */
856struct e1000_ffvt_entry { 856struct e1000_ffvt_entry {
857 volatile uint32_t value; /* Flexible Filter Value (RW) */ 857 volatile u32 value; /* Flexible Filter Value (RW) */
858 volatile uint32_t reserved; 858 volatile u32 reserved;
859}; 859};
860 860
861/* Four Flexible Filters are supported */ 861/* Four Flexible Filters are supported */
@@ -1309,89 +1309,89 @@ struct e1000_ffvt_entry {
1309 1309
1310/* Statistics counters collected by the MAC */ 1310/* Statistics counters collected by the MAC */
1311struct e1000_hw_stats { 1311struct e1000_hw_stats {
1312 uint64_t crcerrs; 1312 u64 crcerrs;
1313 uint64_t algnerrc; 1313 u64 algnerrc;
1314 uint64_t symerrs; 1314 u64 symerrs;
1315 uint64_t rxerrc; 1315 u64 rxerrc;
1316 uint64_t txerrc; 1316 u64 txerrc;
1317 uint64_t mpc; 1317 u64 mpc;
1318 uint64_t scc; 1318 u64 scc;
1319 uint64_t ecol; 1319 u64 ecol;
1320 uint64_t mcc; 1320 u64 mcc;
1321 uint64_t latecol; 1321 u64 latecol;
1322 uint64_t colc; 1322 u64 colc;
1323 uint64_t dc; 1323 u64 dc;
1324 uint64_t tncrs; 1324 u64 tncrs;
1325 uint64_t sec; 1325 u64 sec;
1326 uint64_t cexterr; 1326 u64 cexterr;
1327 uint64_t rlec; 1327 u64 rlec;
1328 uint64_t xonrxc; 1328 u64 xonrxc;
1329 uint64_t xontxc; 1329 u64 xontxc;
1330 uint64_t xoffrxc; 1330 u64 xoffrxc;
1331 uint64_t xofftxc; 1331 u64 xofftxc;
1332 uint64_t fcruc; 1332 u64 fcruc;
1333 uint64_t prc64; 1333 u64 prc64;
1334 uint64_t prc127; 1334 u64 prc127;
1335 uint64_t prc255; 1335 u64 prc255;
1336 uint64_t prc511; 1336 u64 prc511;
1337 uint64_t prc1023; 1337 u64 prc1023;
1338 uint64_t prc1522; 1338 u64 prc1522;
1339 uint64_t gprc; 1339 u64 gprc;
1340 uint64_t bprc; 1340 u64 bprc;
1341 uint64_t mprc; 1341 u64 mprc;
1342 uint64_t gptc; 1342 u64 gptc;
1343 uint64_t gorcl; 1343 u64 gorcl;
1344 uint64_t gorch; 1344 u64 gorch;
1345 uint64_t gotcl; 1345 u64 gotcl;
1346 uint64_t gotch; 1346 u64 gotch;
1347 uint64_t rnbc; 1347 u64 rnbc;
1348 uint64_t ruc; 1348 u64 ruc;
1349 uint64_t rfc; 1349 u64 rfc;
1350 uint64_t roc; 1350 u64 roc;
1351 uint64_t rlerrc; 1351 u64 rlerrc;
1352 uint64_t rjc; 1352 u64 rjc;
1353 uint64_t mgprc; 1353 u64 mgprc;
1354 uint64_t mgpdc; 1354 u64 mgpdc;
1355 uint64_t mgptc; 1355 u64 mgptc;
1356 uint64_t torl; 1356 u64 torl;
1357 uint64_t torh; 1357 u64 torh;
1358 uint64_t totl; 1358 u64 totl;
1359 uint64_t toth; 1359 u64 toth;
1360 uint64_t tpr; 1360 u64 tpr;
1361 uint64_t tpt; 1361 u64 tpt;
1362 uint64_t ptc64; 1362 u64 ptc64;
1363 uint64_t ptc127; 1363 u64 ptc127;
1364 uint64_t ptc255; 1364 u64 ptc255;
1365 uint64_t ptc511; 1365 u64 ptc511;
1366 uint64_t ptc1023; 1366 u64 ptc1023;
1367 uint64_t ptc1522; 1367 u64 ptc1522;
1368 uint64_t mptc; 1368 u64 mptc;
1369 uint64_t bptc; 1369 u64 bptc;
1370 uint64_t tsctc; 1370 u64 tsctc;
1371 uint64_t tsctfc; 1371 u64 tsctfc;
1372 uint64_t iac; 1372 u64 iac;
1373 uint64_t icrxptc; 1373 u64 icrxptc;
1374 uint64_t icrxatc; 1374 u64 icrxatc;
1375 uint64_t ictxptc; 1375 u64 ictxptc;
1376 uint64_t ictxatc; 1376 u64 ictxatc;
1377 uint64_t ictxqec; 1377 u64 ictxqec;
1378 uint64_t ictxqmtc; 1378 u64 ictxqmtc;
1379 uint64_t icrxdmtc; 1379 u64 icrxdmtc;
1380 uint64_t icrxoc; 1380 u64 icrxoc;
1381}; 1381};
1382 1382
1383/* Structure containing variables used by the shared code (e1000_hw.c) */ 1383/* Structure containing variables used by the shared code (e1000_hw.c) */
1384struct e1000_hw { 1384struct e1000_hw {
1385 uint8_t __iomem *hw_addr; 1385 u8 __iomem *hw_addr;
1386 uint8_t __iomem *flash_address; 1386 u8 __iomem *flash_address;
1387 e1000_mac_type mac_type; 1387 e1000_mac_type mac_type;
1388 e1000_phy_type phy_type; 1388 e1000_phy_type phy_type;
1389 uint32_t phy_init_script; 1389 u32 phy_init_script;
1390 e1000_media_type media_type; 1390 e1000_media_type media_type;
1391 void *back; 1391 void *back;
1392 struct e1000_shadow_ram *eeprom_shadow_ram; 1392 struct e1000_shadow_ram *eeprom_shadow_ram;
1393 uint32_t flash_bank_size; 1393 u32 flash_bank_size;
1394 uint32_t flash_base_addr; 1394 u32 flash_base_addr;
1395 e1000_fc_type fc; 1395 e1000_fc_type fc;
1396 e1000_bus_speed bus_speed; 1396 e1000_bus_speed bus_speed;
1397 e1000_bus_width bus_width; 1397 e1000_bus_width bus_width;
@@ -1400,51 +1400,51 @@ struct e1000_hw {
1400 e1000_ms_type master_slave; 1400 e1000_ms_type master_slave;
1401 e1000_ms_type original_master_slave; 1401 e1000_ms_type original_master_slave;
1402 e1000_ffe_config ffe_config_state; 1402 e1000_ffe_config ffe_config_state;
1403 uint32_t asf_firmware_present; 1403 u32 asf_firmware_present;
1404 uint32_t eeprom_semaphore_present; 1404 u32 eeprom_semaphore_present;
1405 uint32_t swfw_sync_present; 1405 u32 swfw_sync_present;
1406 uint32_t swfwhw_semaphore_present; 1406 u32 swfwhw_semaphore_present;
1407 unsigned long io_base; 1407 unsigned long io_base;
1408 uint32_t phy_id; 1408 u32 phy_id;
1409 uint32_t phy_revision; 1409 u32 phy_revision;
1410 uint32_t phy_addr; 1410 u32 phy_addr;
1411 uint32_t original_fc; 1411 u32 original_fc;
1412 uint32_t txcw; 1412 u32 txcw;
1413 uint32_t autoneg_failed; 1413 u32 autoneg_failed;
1414 uint32_t max_frame_size; 1414 u32 max_frame_size;
1415 uint32_t min_frame_size; 1415 u32 min_frame_size;
1416 uint32_t mc_filter_type; 1416 u32 mc_filter_type;
1417 uint32_t num_mc_addrs; 1417 u32 num_mc_addrs;
1418 uint32_t collision_delta; 1418 u32 collision_delta;
1419 uint32_t tx_packet_delta; 1419 u32 tx_packet_delta;
1420 uint32_t ledctl_default; 1420 u32 ledctl_default;
1421 uint32_t ledctl_mode1; 1421 u32 ledctl_mode1;
1422 uint32_t ledctl_mode2; 1422 u32 ledctl_mode2;
1423 bool tx_pkt_filtering; 1423 bool tx_pkt_filtering;
1424 struct e1000_host_mng_dhcp_cookie mng_cookie; 1424 struct e1000_host_mng_dhcp_cookie mng_cookie;
1425 uint16_t phy_spd_default; 1425 u16 phy_spd_default;
1426 uint16_t autoneg_advertised; 1426 u16 autoneg_advertised;
1427 uint16_t pci_cmd_word; 1427 u16 pci_cmd_word;
1428 uint16_t fc_high_water; 1428 u16 fc_high_water;
1429 uint16_t fc_low_water; 1429 u16 fc_low_water;
1430 uint16_t fc_pause_time; 1430 u16 fc_pause_time;
1431 uint16_t current_ifs_val; 1431 u16 current_ifs_val;
1432 uint16_t ifs_min_val; 1432 u16 ifs_min_val;
1433 uint16_t ifs_max_val; 1433 u16 ifs_max_val;
1434 uint16_t ifs_step_size; 1434 u16 ifs_step_size;
1435 uint16_t ifs_ratio; 1435 u16 ifs_ratio;
1436 uint16_t device_id; 1436 u16 device_id;
1437 uint16_t vendor_id; 1437 u16 vendor_id;
1438 uint16_t subsystem_id; 1438 u16 subsystem_id;
1439 uint16_t subsystem_vendor_id; 1439 u16 subsystem_vendor_id;
1440 uint8_t revision_id; 1440 u8 revision_id;
1441 uint8_t autoneg; 1441 u8 autoneg;
1442 uint8_t mdix; 1442 u8 mdix;
1443 uint8_t forced_speed_duplex; 1443 u8 forced_speed_duplex;
1444 uint8_t wait_autoneg_complete; 1444 u8 wait_autoneg_complete;
1445 uint8_t dma_fairness; 1445 u8 dma_fairness;
1446 uint8_t mac_addr[NODE_ADDRESS_SIZE]; 1446 u8 mac_addr[NODE_ADDRESS_SIZE];
1447 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 1447 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1448 bool disable_polarity_correction; 1448 bool disable_polarity_correction;
1449 bool speed_downgraded; 1449 bool speed_downgraded;
1450 e1000_smart_speed smart_speed; 1450 e1000_smart_speed smart_speed;
@@ -2165,14 +2165,14 @@ typedef enum {
2165#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2165#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2166 2166
2167struct e1000_host_command_header { 2167struct e1000_host_command_header {
2168 uint8_t command_id; 2168 u8 command_id;
2169 uint8_t command_length; 2169 u8 command_length;
2170 uint8_t command_options; /* I/F bits for command, status for return */ 2170 u8 command_options; /* I/F bits for command, status for return */
2171 uint8_t checksum; 2171 u8 checksum;
2172}; 2172};
2173struct e1000_host_command_info { 2173struct e1000_host_command_info {
2174 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2174 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2175 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2175 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2176}; 2176};
2177 2177
2178/* Host SMB register #0 */ 2178/* Host SMB register #0 */
@@ -2495,7 +2495,7 @@ struct e1000_host_command_info {
2495/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2495/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2496#define PHY_CFG_TIMEOUT 100 2496#define PHY_CFG_TIMEOUT 100
2497 2497
2498#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2498#define E1000_TX_BUFFER_SIZE ((u32)1514)
2499 2499
2500/* The carrier extension symbol, as received by the NIC. */ 2500/* The carrier extension symbol, as received by the NIC. */
2501#define CARRIER_EXTENSION 0x0F 2501#define CARRIER_EXTENSION 0x0F
@@ -3312,68 +3312,68 @@ struct e1000_host_command_info {
3312/* Offset 04h HSFSTS */ 3312/* Offset 04h HSFSTS */
3313union ich8_hws_flash_status { 3313union ich8_hws_flash_status {
3314 struct ich8_hsfsts { 3314 struct ich8_hsfsts {
3315#ifdef E1000_BIG_ENDIAN 3315#ifdef __BIG_ENDIAN
3316 uint16_t reserved2 :6; 3316 u16 reserved2 :6;
3317 uint16_t fldesvalid :1; 3317 u16 fldesvalid :1;
3318 uint16_t flockdn :1; 3318 u16 flockdn :1;
3319 uint16_t flcdone :1; 3319 u16 flcdone :1;
3320 uint16_t flcerr :1; 3320 u16 flcerr :1;
3321 uint16_t dael :1; 3321 u16 dael :1;
3322 uint16_t berasesz :2; 3322 u16 berasesz :2;
3323 uint16_t flcinprog :1; 3323 u16 flcinprog :1;
3324 uint16_t reserved1 :2; 3324 u16 reserved1 :2;
3325#else 3325#else
3326 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */ 3326 u16 flcdone :1; /* bit 0 Flash Cycle Done */
3327 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */ 3327 u16 flcerr :1; /* bit 1 Flash Cycle Error */
3328 uint16_t dael :1; /* bit 2 Direct Access error Log */ 3328 u16 dael :1; /* bit 2 Direct Access error Log */
3329 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */ 3329 u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3330 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */ 3330 u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3331 uint16_t reserved1 :2; /* bit 13:6 Reserved */ 3331 u16 reserved1 :2; /* bit 13:6 Reserved */
3332 uint16_t reserved2 :6; /* bit 13:6 Reserved */ 3332 u16 reserved2 :6; /* bit 13:6 Reserved */
3333 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 3333 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3334 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */ 3334 u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3335#endif 3335#endif
3336 } hsf_status; 3336 } hsf_status;
3337 uint16_t regval; 3337 u16 regval;
3338}; 3338};
3339 3339
3340/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 3340/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3341/* Offset 06h FLCTL */ 3341/* Offset 06h FLCTL */
3342union ich8_hws_flash_ctrl { 3342union ich8_hws_flash_ctrl {
3343 struct ich8_hsflctl { 3343 struct ich8_hsflctl {
3344#ifdef E1000_BIG_ENDIAN 3344#ifdef __BIG_ENDIAN
3345 uint16_t fldbcount :2; 3345 u16 fldbcount :2;
3346 uint16_t flockdn :6; 3346 u16 flockdn :6;
3347 uint16_t flcgo :1; 3347 u16 flcgo :1;
3348 uint16_t flcycle :2; 3348 u16 flcycle :2;
3349 uint16_t reserved :5; 3349 u16 reserved :5;
3350#else 3350#else
3351 uint16_t flcgo :1; /* 0 Flash Cycle Go */ 3351 u16 flcgo :1; /* 0 Flash Cycle Go */
3352 uint16_t flcycle :2; /* 2:1 Flash Cycle */ 3352 u16 flcycle :2; /* 2:1 Flash Cycle */
3353 uint16_t reserved :5; /* 7:3 Reserved */ 3353 u16 reserved :5; /* 7:3 Reserved */
3354 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */ 3354 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
3355 uint16_t flockdn :6; /* 15:10 Reserved */ 3355 u16 flockdn :6; /* 15:10 Reserved */
3356#endif 3356#endif
3357 } hsf_ctrl; 3357 } hsf_ctrl;
3358 uint16_t regval; 3358 u16 regval;
3359}; 3359};
3360 3360
3361/* ICH8 Flash Region Access Permissions */ 3361/* ICH8 Flash Region Access Permissions */
3362union ich8_hws_flash_regacc { 3362union ich8_hws_flash_regacc {
3363 struct ich8_flracc { 3363 struct ich8_flracc {
3364#ifdef E1000_BIG_ENDIAN 3364#ifdef __BIG_ENDIAN
3365 uint32_t gmwag :8; 3365 u32 gmwag :8;
3366 uint32_t gmrag :8; 3366 u32 gmrag :8;
3367 uint32_t grwa :8; 3367 u32 grwa :8;
3368 uint32_t grra :8; 3368 u32 grra :8;
3369#else 3369#else
3370 uint32_t grra :8; /* 0:7 GbE region Read Access */ 3370 u32 grra :8; /* 0:7 GbE region Read Access */
3371 uint32_t grwa :8; /* 8:15 GbE region Write Access */ 3371 u32 grwa :8; /* 8:15 GbE region Write Access */
3372 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */ 3372 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
3373 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */ 3373 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
3374#endif 3374#endif
3375 } hsf_flregacc; 3375 } hsf_flregacc;
3376 uint16_t regval; 3376 u16 regval;
3377}; 3377};
3378 3378
3379/* Miscellaneous PHY bit definitions. */ 3379/* Miscellaneous PHY bit definitions. */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 757d02f443a5..59579b1d8843 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -127,7 +127,7 @@ int e1000_up(struct e1000_adapter *adapter);
127void e1000_down(struct e1000_adapter *adapter); 127void e1000_down(struct e1000_adapter *adapter);
128void e1000_reinit_locked(struct e1000_adapter *adapter); 128void e1000_reinit_locked(struct e1000_adapter *adapter);
129void e1000_reset(struct e1000_adapter *adapter); 129void e1000_reset(struct e1000_adapter *adapter);
130int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx); 130int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx);
131int e1000_setup_all_tx_resources(struct e1000_adapter *adapter); 131int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
132int e1000_setup_all_rx_resources(struct e1000_adapter *adapter); 132int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
133void e1000_free_all_tx_resources(struct e1000_adapter *adapter); 133void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
@@ -203,8 +203,8 @@ static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
203 struct sk_buff *skb); 203 struct sk_buff *skb);
204 204
205static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp); 205static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
206static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid); 206static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
207static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid); 207static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid);
208static void e1000_restore_vlan(struct e1000_adapter *adapter); 208static void e1000_restore_vlan(struct e1000_adapter *adapter);
209 209
210static int e1000_suspend(struct pci_dev *pdev, pm_message_t state); 210static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
@@ -368,8 +368,8 @@ static void
368e1000_update_mng_vlan(struct e1000_adapter *adapter) 368e1000_update_mng_vlan(struct e1000_adapter *adapter)
369{ 369{
370 struct net_device *netdev = adapter->netdev; 370 struct net_device *netdev = adapter->netdev;
371 uint16_t vid = adapter->hw.mng_cookie.vlan_id; 371 u16 vid = adapter->hw.mng_cookie.vlan_id;
372 uint16_t old_vid = adapter->mng_vlan_id; 372 u16 old_vid = adapter->mng_vlan_id;
373 if (adapter->vlgrp) { 373 if (adapter->vlgrp) {
374 if (!vlan_group_get_device(adapter->vlgrp, vid)) { 374 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
375 if (adapter->hw.mng_cookie.status & 375 if (adapter->hw.mng_cookie.status &
@@ -379,7 +379,7 @@ e1000_update_mng_vlan(struct e1000_adapter *adapter)
379 } else 379 } else
380 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 380 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
381 381
382 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) && 382 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) &&
383 (vid != old_vid) && 383 (vid != old_vid) &&
384 !vlan_group_get_device(adapter->vlgrp, old_vid)) 384 !vlan_group_get_device(adapter->vlgrp, old_vid))
385 e1000_vlan_rx_kill_vid(netdev, old_vid); 385 e1000_vlan_rx_kill_vid(netdev, old_vid);
@@ -402,8 +402,8 @@ e1000_update_mng_vlan(struct e1000_adapter *adapter)
402static void 402static void
403e1000_release_hw_control(struct e1000_adapter *adapter) 403e1000_release_hw_control(struct e1000_adapter *adapter)
404{ 404{
405 uint32_t ctrl_ext; 405 u32 ctrl_ext;
406 uint32_t swsm; 406 u32 swsm;
407 407
408 /* Let firmware taken over control of h/w */ 408 /* Let firmware taken over control of h/w */
409 switch (adapter->hw.mac_type) { 409 switch (adapter->hw.mac_type) {
@@ -439,8 +439,8 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
439static void 439static void
440e1000_get_hw_control(struct e1000_adapter *adapter) 440e1000_get_hw_control(struct e1000_adapter *adapter)
441{ 441{
442 uint32_t ctrl_ext; 442 u32 ctrl_ext;
443 uint32_t swsm; 443 u32 swsm;
444 444
445 /* Let firmware know the driver has taken over */ 445 /* Let firmware know the driver has taken over */
446 switch (adapter->hw.mac_type) { 446 switch (adapter->hw.mac_type) {
@@ -466,7 +466,7 @@ static void
466e1000_init_manageability(struct e1000_adapter *adapter) 466e1000_init_manageability(struct e1000_adapter *adapter)
467{ 467{
468 if (adapter->en_mng_pt) { 468 if (adapter->en_mng_pt) {
469 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC); 469 u32 manc = E1000_READ_REG(&adapter->hw, MANC);
470 470
471 /* disable hardware interception of ARP */ 471 /* disable hardware interception of ARP */
472 manc &= ~(E1000_MANC_ARP_EN); 472 manc &= ~(E1000_MANC_ARP_EN);
@@ -475,7 +475,7 @@ e1000_init_manageability(struct e1000_adapter *adapter)
475 /* this will probably generate destination unreachable messages 475 /* this will probably generate destination unreachable messages
476 * from the host OS, but the packets will be handled on SMBUS */ 476 * from the host OS, but the packets will be handled on SMBUS */
477 if (adapter->hw.has_manc2h) { 477 if (adapter->hw.has_manc2h) {
478 uint32_t manc2h = E1000_READ_REG(&adapter->hw, MANC2H); 478 u32 manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
479 479
480 manc |= E1000_MANC_EN_MNG2HOST; 480 manc |= E1000_MANC_EN_MNG2HOST;
481#define E1000_MNG2HOST_PORT_623 (1 << 5) 481#define E1000_MNG2HOST_PORT_623 (1 << 5)
@@ -493,7 +493,7 @@ static void
493e1000_release_manageability(struct e1000_adapter *adapter) 493e1000_release_manageability(struct e1000_adapter *adapter)
494{ 494{
495 if (adapter->en_mng_pt) { 495 if (adapter->en_mng_pt) {
496 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC); 496 u32 manc = E1000_READ_REG(&adapter->hw, MANC);
497 497
498 /* re-enable hardware interception of ARP */ 498 /* re-enable hardware interception of ARP */
499 manc |= E1000_MANC_ARP_EN; 499 manc |= E1000_MANC_ARP_EN;
@@ -566,7 +566,7 @@ int e1000_up(struct e1000_adapter *adapter)
566 566
567void e1000_power_up_phy(struct e1000_adapter *adapter) 567void e1000_power_up_phy(struct e1000_adapter *adapter)
568{ 568{
569 uint16_t mii_reg = 0; 569 u16 mii_reg = 0;
570 570
571 /* Just clear the power down bit to wake the phy back up */ 571 /* Just clear the power down bit to wake the phy back up */
572 if (adapter->hw.media_type == e1000_media_type_copper) { 572 if (adapter->hw.media_type == e1000_media_type_copper) {
@@ -587,7 +587,7 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter)
587 * (c) SoL/IDER session is active */ 587 * (c) SoL/IDER session is active */
588 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 && 588 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
589 adapter->hw.media_type == e1000_media_type_copper) { 589 adapter->hw.media_type == e1000_media_type_copper) {
590 uint16_t mii_reg = 0; 590 u16 mii_reg = 0;
591 591
592 switch (adapter->hw.mac_type) { 592 switch (adapter->hw.mac_type) {
593 case e1000_82540: 593 case e1000_82540:
@@ -667,8 +667,8 @@ e1000_reinit_locked(struct e1000_adapter *adapter)
667void 667void
668e1000_reset(struct e1000_adapter *adapter) 668e1000_reset(struct e1000_adapter *adapter)
669{ 669{
670 uint32_t pba = 0, tx_space, min_tx_space, min_rx_space; 670 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
671 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF; 671 u16 fc_high_water_mark = E1000_FC_HIGH_DIFF;
672 bool legacy_pba_adjust = false; 672 bool legacy_pba_adjust = false;
673 673
674 /* Repartition Pba for greater than 9k mtu 674 /* Repartition Pba for greater than 9k mtu
@@ -815,7 +815,7 @@ e1000_reset(struct e1000_adapter *adapter)
815 adapter->hw.mac_type <= e1000_82547_rev_2 && 815 adapter->hw.mac_type <= e1000_82547_rev_2 &&
816 adapter->hw.autoneg == 1 && 816 adapter->hw.autoneg == 1 &&
817 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) { 817 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
818 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL); 818 u32 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
819 /* clear phy power management bit if we are in gig only mode, 819 /* clear phy power management bit if we are in gig only mode,
820 * which if enabled will attempt negotiation to 100Mb, which 820 * which if enabled will attempt negotiation to 100Mb, which
821 * can cause a loss of link at power off or driver unload */ 821 * can cause a loss of link at power off or driver unload */
@@ -832,7 +832,7 @@ e1000_reset(struct e1000_adapter *adapter)
832 if (!adapter->smart_power_down && 832 if (!adapter->smart_power_down &&
833 (adapter->hw.mac_type == e1000_82571 || 833 (adapter->hw.mac_type == e1000_82571 ||
834 adapter->hw.mac_type == e1000_82572)) { 834 adapter->hw.mac_type == e1000_82572)) {
835 uint16_t phy_data = 0; 835 u16 phy_data = 0;
836 /* speed up time to link by disabling smart power down, ignore 836 /* speed up time to link by disabling smart power down, ignore
837 * the return value of this function because there is nothing 837 * the return value of this function because there is nothing
838 * different we would do if it failed */ 838 * different we would do if it failed */
@@ -926,8 +926,8 @@ e1000_probe(struct pci_dev *pdev,
926 static int cards_found = 0; 926 static int cards_found = 0;
927 static int global_quad_port_a = 0; /* global ksp3 port a indication */ 927 static int global_quad_port_a = 0; /* global ksp3 port a indication */
928 int i, err, pci_using_dac; 928 int i, err, pci_using_dac;
929 uint16_t eeprom_data = 0; 929 u16 eeprom_data = 0;
930 uint16_t eeprom_apme_mask = E1000_EEPROM_APME; 930 u16 eeprom_apme_mask = E1000_EEPROM_APME;
931 DECLARE_MAC_BUF(mac); 931 DECLARE_MAC_BUF(mac);
932 932
933 if ((err = pci_enable_device(pdev))) 933 if ((err = pci_enable_device(pdev)))
@@ -1702,10 +1702,10 @@ e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1702static void 1702static void
1703e1000_configure_tx(struct e1000_adapter *adapter) 1703e1000_configure_tx(struct e1000_adapter *adapter)
1704{ 1704{
1705 uint64_t tdba; 1705 u64 tdba;
1706 struct e1000_hw *hw = &adapter->hw; 1706 struct e1000_hw *hw = &adapter->hw;
1707 uint32_t tdlen, tctl, tipg, tarc; 1707 u32 tdlen, tctl, tipg, tarc;
1708 uint32_t ipgr1, ipgr2; 1708 u32 ipgr1, ipgr2;
1709 1709
1710 /* Setup the HW Tx Head and Tail descriptor pointers */ 1710 /* Setup the HW Tx Head and Tail descriptor pointers */
1711 1711
@@ -1947,10 +1947,10 @@ e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1947static void 1947static void
1948e1000_setup_rctl(struct e1000_adapter *adapter) 1948e1000_setup_rctl(struct e1000_adapter *adapter)
1949{ 1949{
1950 uint32_t rctl, rfctl; 1950 u32 rctl, rfctl;
1951 uint32_t psrctl = 0; 1951 u32 psrctl = 0;
1952#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT 1952#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
1953 uint32_t pages = 0; 1953 u32 pages = 0;
1954#endif 1954#endif
1955 1955
1956 rctl = E1000_READ_REG(&adapter->hw, RCTL); 1956 rctl = E1000_READ_REG(&adapter->hw, RCTL);
@@ -2065,9 +2065,9 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
2065static void 2065static void
2066e1000_configure_rx(struct e1000_adapter *adapter) 2066e1000_configure_rx(struct e1000_adapter *adapter)
2067{ 2067{
2068 uint64_t rdba; 2068 u64 rdba;
2069 struct e1000_hw *hw = &adapter->hw; 2069 struct e1000_hw *hw = &adapter->hw;
2070 uint32_t rdlen, rctl, rxcsum, ctrl_ext; 2070 u32 rdlen, rctl, rxcsum, ctrl_ext;
2071 2071
2072 if (adapter->rx_ps_pages) { 2072 if (adapter->rx_ps_pages) {
2073 /* this is a 32 byte descriptor */ 2073 /* this is a 32 byte descriptor */
@@ -2387,7 +2387,7 @@ static void
2387e1000_enter_82542_rst(struct e1000_adapter *adapter) 2387e1000_enter_82542_rst(struct e1000_adapter *adapter)
2388{ 2388{
2389 struct net_device *netdev = adapter->netdev; 2389 struct net_device *netdev = adapter->netdev;
2390 uint32_t rctl; 2390 u32 rctl;
2391 2391
2392 e1000_pci_clear_mwi(&adapter->hw); 2392 e1000_pci_clear_mwi(&adapter->hw);
2393 2393
@@ -2405,7 +2405,7 @@ static void
2405e1000_leave_82542_rst(struct e1000_adapter *adapter) 2405e1000_leave_82542_rst(struct e1000_adapter *adapter)
2406{ 2406{
2407 struct net_device *netdev = adapter->netdev; 2407 struct net_device *netdev = adapter->netdev;
2408 uint32_t rctl; 2408 u32 rctl;
2409 2409
2410 rctl = E1000_READ_REG(&adapter->hw, RCTL); 2410 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2411 rctl &= ~E1000_RCTL_RST; 2411 rctl &= ~E1000_RCTL_RST;
@@ -2490,8 +2490,8 @@ e1000_set_rx_mode(struct net_device *netdev)
2490 struct e1000_hw *hw = &adapter->hw; 2490 struct e1000_hw *hw = &adapter->hw;
2491 struct dev_addr_list *uc_ptr; 2491 struct dev_addr_list *uc_ptr;
2492 struct dev_addr_list *mc_ptr; 2492 struct dev_addr_list *mc_ptr;
2493 uint32_t rctl; 2493 u32 rctl;
2494 uint32_t hash_value; 2494 u32 hash_value;
2495 int i, rar_entries = E1000_RAR_ENTRIES; 2495 int i, rar_entries = E1000_RAR_ENTRIES;
2496 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ? 2496 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2497 E1000_NUM_MTA_REGISTERS_ICH8LAN : 2497 E1000_NUM_MTA_REGISTERS_ICH8LAN :
@@ -2595,7 +2595,7 @@ e1000_82547_tx_fifo_stall(unsigned long data)
2595{ 2595{
2596 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 2596 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2597 struct net_device *netdev = adapter->netdev; 2597 struct net_device *netdev = adapter->netdev;
2598 uint32_t tctl; 2598 u32 tctl;
2599 2599
2600 if (atomic_read(&adapter->tx_fifo_stall)) { 2600 if (atomic_read(&adapter->tx_fifo_stall)) {
2601 if ((E1000_READ_REG(&adapter->hw, TDT) == 2601 if ((E1000_READ_REG(&adapter->hw, TDT) ==
@@ -2637,8 +2637,8 @@ e1000_watchdog(unsigned long data)
2637 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 2637 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2638 struct net_device *netdev = adapter->netdev; 2638 struct net_device *netdev = adapter->netdev;
2639 struct e1000_tx_ring *txdr = adapter->tx_ring; 2639 struct e1000_tx_ring *txdr = adapter->tx_ring;
2640 uint32_t link, tctl; 2640 u32 link, tctl;
2641 int32_t ret_val; 2641 s32 ret_val;
2642 2642
2643 ret_val = e1000_check_for_link(&adapter->hw); 2643 ret_val = e1000_check_for_link(&adapter->hw);
2644 if ((ret_val == E1000_ERR_PHY) && 2644 if ((ret_val == E1000_ERR_PHY) &&
@@ -2663,7 +2663,7 @@ e1000_watchdog(unsigned long data)
2663 2663
2664 if (link) { 2664 if (link) {
2665 if (!netif_carrier_ok(netdev)) { 2665 if (!netif_carrier_ok(netdev)) {
2666 uint32_t ctrl; 2666 u32 ctrl;
2667 bool txb2b = true; 2667 bool txb2b = true;
2668 e1000_get_speed_and_duplex(&adapter->hw, 2668 e1000_get_speed_and_duplex(&adapter->hw,
2669 &adapter->link_speed, 2669 &adapter->link_speed,
@@ -2700,7 +2700,7 @@ e1000_watchdog(unsigned long data)
2700 if ((adapter->hw.mac_type == e1000_82571 || 2700 if ((adapter->hw.mac_type == e1000_82571 ||
2701 adapter->hw.mac_type == e1000_82572) && 2701 adapter->hw.mac_type == e1000_82572) &&
2702 !txb2b) { 2702 !txb2b) {
2703 uint32_t tarc0; 2703 u32 tarc0;
2704 tarc0 = E1000_READ_REG(&adapter->hw, TARC0); 2704 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2705 tarc0 &= ~(1 << 21); 2705 tarc0 &= ~(1 << 21);
2706 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0); 2706 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
@@ -2742,7 +2742,7 @@ e1000_watchdog(unsigned long data)
2742 /* make sure the receive unit is started */ 2742 /* make sure the receive unit is started */
2743 if (adapter->hw.rx_needs_kicking) { 2743 if (adapter->hw.rx_needs_kicking) {
2744 struct e1000_hw *hw = &adapter->hw; 2744 struct e1000_hw *hw = &adapter->hw;
2745 uint32_t rctl = E1000_READ_REG(hw, RCTL); 2745 u32 rctl = E1000_READ_REG(hw, RCTL);
2746 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN); 2746 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN);
2747 } 2747 }
2748 } 2748 }
@@ -2832,7 +2832,7 @@ enum latency_range {
2832 * @bytes: the number of bytes during this measurement interval 2832 * @bytes: the number of bytes during this measurement interval
2833 **/ 2833 **/
2834static unsigned int e1000_update_itr(struct e1000_adapter *adapter, 2834static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2835 uint16_t itr_setting, 2835 u16 itr_setting,
2836 int packets, 2836 int packets,
2837 int bytes) 2837 int bytes)
2838{ 2838{
@@ -2884,8 +2884,8 @@ update_itr_done:
2884static void e1000_set_itr(struct e1000_adapter *adapter) 2884static void e1000_set_itr(struct e1000_adapter *adapter)
2885{ 2885{
2886 struct e1000_hw *hw = &adapter->hw; 2886 struct e1000_hw *hw = &adapter->hw;
2887 uint16_t current_itr; 2887 u16 current_itr;
2888 uint32_t new_itr = adapter->itr; 2888 u32 new_itr = adapter->itr;
2889 2889
2890 if (unlikely(hw->mac_type < e1000_82540)) 2890 if (unlikely(hw->mac_type < e1000_82540))
2891 return; 2891 return;
@@ -2959,9 +2959,9 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2959 struct e1000_context_desc *context_desc; 2959 struct e1000_context_desc *context_desc;
2960 struct e1000_buffer *buffer_info; 2960 struct e1000_buffer *buffer_info;
2961 unsigned int i; 2961 unsigned int i;
2962 uint32_t cmd_length = 0; 2962 u32 cmd_length = 0;
2963 uint16_t ipcse = 0, tucse, mss; 2963 u16 ipcse = 0, tucse, mss;
2964 uint8_t ipcss, ipcso, tucss, tucso, hdr_len; 2964 u8 ipcss, ipcso, tucss, tucso, hdr_len;
2965 int err; 2965 int err;
2966 2966
2967 if (skb_is_gso(skb)) { 2967 if (skb_is_gso(skb)) {
@@ -3032,7 +3032,7 @@ e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3032 struct e1000_context_desc *context_desc; 3032 struct e1000_context_desc *context_desc;
3033 struct e1000_buffer *buffer_info; 3033 struct e1000_buffer *buffer_info;
3034 unsigned int i; 3034 unsigned int i;
3035 uint8_t css; 3035 u8 css;
3036 3036
3037 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 3037 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
3038 css = skb_transport_offset(skb); 3038 css = skb_transport_offset(skb);
@@ -3177,7 +3177,7 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3177{ 3177{
3178 struct e1000_tx_desc *tx_desc = NULL; 3178 struct e1000_tx_desc *tx_desc = NULL;
3179 struct e1000_buffer *buffer_info; 3179 struct e1000_buffer *buffer_info;
3180 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 3180 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
3181 unsigned int i; 3181 unsigned int i;
3182 3182
3183 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) { 3183 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
@@ -3241,8 +3241,8 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3241static int 3241static int
3242e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb) 3242e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
3243{ 3243{
3244 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 3244 u32 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3245 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR; 3245 u32 skb_fifo_len = skb->len + E1000_FIFO_HDR;
3246 3246
3247 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR); 3247 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR);
3248 3248
@@ -3269,7 +3269,7 @@ static int
3269e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb) 3269e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3270{ 3270{
3271 struct e1000_hw *hw = &adapter->hw; 3271 struct e1000_hw *hw = &adapter->hw;
3272 uint16_t length, offset; 3272 u16 length, offset;
3273 if (vlan_tx_tag_present(skb)) { 3273 if (vlan_tx_tag_present(skb)) {
3274 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 3274 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
3275 ( adapter->hw.mng_cookie.status & 3275 ( adapter->hw.mng_cookie.status &
@@ -3280,17 +3280,17 @@ e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3280 struct ethhdr *eth = (struct ethhdr *) skb->data; 3280 struct ethhdr *eth = (struct ethhdr *) skb->data;
3281 if ((htons(ETH_P_IP) == eth->h_proto)) { 3281 if ((htons(ETH_P_IP) == eth->h_proto)) {
3282 const struct iphdr *ip = 3282 const struct iphdr *ip =
3283 (struct iphdr *)((uint8_t *)skb->data+14); 3283 (struct iphdr *)((u8 *)skb->data+14);
3284 if (IPPROTO_UDP == ip->protocol) { 3284 if (IPPROTO_UDP == ip->protocol) {
3285 struct udphdr *udp = 3285 struct udphdr *udp =
3286 (struct udphdr *)((uint8_t *)ip + 3286 (struct udphdr *)((u8 *)ip +
3287 (ip->ihl << 2)); 3287 (ip->ihl << 2));
3288 if (ntohs(udp->dest) == 67) { 3288 if (ntohs(udp->dest) == 67) {
3289 offset = (uint8_t *)udp + 8 - skb->data; 3289 offset = (u8 *)udp + 8 - skb->data;
3290 length = skb->len - offset; 3290 length = skb->len - offset;
3291 3291
3292 return e1000_mng_write_dhcp_info(hw, 3292 return e1000_mng_write_dhcp_info(hw,
3293 (uint8_t *)udp + 8, 3293 (u8 *)udp + 8,
3294 length); 3294 length);
3295 } 3295 }
3296 } 3296 }
@@ -3370,7 +3370,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3370 * overrun the FIFO, adjust the max buffer len if mss 3370 * overrun the FIFO, adjust the max buffer len if mss
3371 * drops. */ 3371 * drops. */
3372 if (mss) { 3372 if (mss) {
3373 uint8_t hdr_len; 3373 u8 hdr_len;
3374 max_per_txd = min(mss << 2, max_per_txd); 3374 max_per_txd = min(mss << 2, max_per_txd);
3375 max_txd_pwr = fls(max_per_txd) - 1; 3375 max_txd_pwr = fls(max_per_txd) - 1;
3376 3376
@@ -3557,7 +3557,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
3557{ 3557{
3558 struct e1000_adapter *adapter = netdev_priv(netdev); 3558 struct e1000_adapter *adapter = netdev_priv(netdev);
3559 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 3559 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
3560 uint16_t eeprom_data = 0; 3560 u16 eeprom_data = 0;
3561 3561
3562 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || 3562 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3563 (max_frame > MAX_JUMBO_FRAME_SIZE)) { 3563 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
@@ -3652,7 +3652,7 @@ e1000_update_stats(struct e1000_adapter *adapter)
3652 struct e1000_hw *hw = &adapter->hw; 3652 struct e1000_hw *hw = &adapter->hw;
3653 struct pci_dev *pdev = adapter->pdev; 3653 struct pci_dev *pdev = adapter->pdev;
3654 unsigned long flags; 3654 unsigned long flags;
3655 uint16_t phy_tmp; 3655 u16 phy_tmp;
3656 3656
3657#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 3657#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3658 3658
@@ -3829,7 +3829,7 @@ e1000_intr_msi(int irq, void *data)
3829#ifndef CONFIG_E1000_NAPI 3829#ifndef CONFIG_E1000_NAPI
3830 int i; 3830 int i;
3831#endif 3831#endif
3832 uint32_t icr = E1000_READ_REG(hw, ICR); 3832 u32 icr = E1000_READ_REG(hw, ICR);
3833 3833
3834 /* in NAPI mode read ICR disables interrupts using IAM */ 3834 /* in NAPI mode read ICR disables interrupts using IAM */
3835 3835
@@ -3841,7 +3841,7 @@ e1000_intr_msi(int irq, void *data)
3841 if (netif_carrier_ok(netdev) && 3841 if (netif_carrier_ok(netdev) &&
3842 (adapter->hw.mac_type == e1000_80003es2lan)) { 3842 (adapter->hw.mac_type == e1000_80003es2lan)) {
3843 /* disable receives */ 3843 /* disable receives */
3844 uint32_t rctl = E1000_READ_REG(hw, RCTL); 3844 u32 rctl = E1000_READ_REG(hw, RCTL);
3845 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 3845 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3846 } 3846 }
3847 /* guard against interrupt when we're going down */ 3847 /* guard against interrupt when we're going down */
@@ -3888,7 +3888,7 @@ e1000_intr(int irq, void *data)
3888 struct net_device *netdev = data; 3888 struct net_device *netdev = data;
3889 struct e1000_adapter *adapter = netdev_priv(netdev); 3889 struct e1000_adapter *adapter = netdev_priv(netdev);
3890 struct e1000_hw *hw = &adapter->hw; 3890 struct e1000_hw *hw = &adapter->hw;
3891 uint32_t rctl, icr = E1000_READ_REG(hw, ICR); 3891 u32 rctl, icr = E1000_READ_REG(hw, ICR);
3892#ifndef CONFIG_E1000_NAPI 3892#ifndef CONFIG_E1000_NAPI
3893 int i; 3893 int i;
3894#endif 3894#endif
@@ -4139,11 +4139,11 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
4139 4139
4140static void 4140static void
4141e1000_rx_checksum(struct e1000_adapter *adapter, 4141e1000_rx_checksum(struct e1000_adapter *adapter,
4142 uint32_t status_err, uint32_t csum, 4142 u32 status_err, u32 csum,
4143 struct sk_buff *skb) 4143 struct sk_buff *skb)
4144{ 4144{
4145 uint16_t status = (uint16_t)status_err; 4145 u16 status = (u16)status_err;
4146 uint8_t errors = (uint8_t)(status_err >> 24); 4146 u8 errors = (u8)(status_err >> 24);
4147 skb->ip_summed = CHECKSUM_NONE; 4147 skb->ip_summed = CHECKSUM_NONE;
4148 4148
4149 /* 82543 or newer only */ 4149 /* 82543 or newer only */
@@ -4200,8 +4200,8 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
4200 struct e1000_rx_desc *rx_desc, *next_rxd; 4200 struct e1000_rx_desc *rx_desc, *next_rxd;
4201 struct e1000_buffer *buffer_info, *next_buffer; 4201 struct e1000_buffer *buffer_info, *next_buffer;
4202 unsigned long flags; 4202 unsigned long flags;
4203 uint32_t length; 4203 u32 length;
4204 uint8_t last_byte; 4204 u8 last_byte;
4205 unsigned int i; 4205 unsigned int i;
4206 int cleaned_count = 0; 4206 int cleaned_count = 0;
4207 bool cleaned = false; 4207 bool cleaned = false;
@@ -4301,8 +4301,8 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
4301 4301
4302 /* Receive Checksum Offload */ 4302 /* Receive Checksum Offload */
4303 e1000_rx_checksum(adapter, 4303 e1000_rx_checksum(adapter,
4304 (uint32_t)(status) | 4304 (u32)(status) |
4305 ((uint32_t)(rx_desc->errors) << 24), 4305 ((u32)(rx_desc->errors) << 24),
4306 le16_to_cpu(rx_desc->csum), skb); 4306 le16_to_cpu(rx_desc->csum), skb);
4307 4307
4308 skb->protocol = eth_type_trans(skb, netdev); 4308 skb->protocol = eth_type_trans(skb, netdev);
@@ -4376,7 +4376,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4376 struct e1000_ps_page_dma *ps_page_dma; 4376 struct e1000_ps_page_dma *ps_page_dma;
4377 struct sk_buff *skb; 4377 struct sk_buff *skb;
4378 unsigned int i, j; 4378 unsigned int i, j;
4379 uint32_t length, staterr; 4379 u32 length, staterr;
4380 int cleaned_count = 0; 4380 int cleaned_count = 0;
4381 bool cleaned = false; 4381 bool cleaned = false;
4382 unsigned int total_rx_bytes=0, total_rx_packets=0; 4382 unsigned int total_rx_bytes=0, total_rx_packets=0;
@@ -4759,8 +4759,8 @@ no_buffers:
4759static void 4759static void
4760e1000_smartspeed(struct e1000_adapter *adapter) 4760e1000_smartspeed(struct e1000_adapter *adapter)
4761{ 4761{
4762 uint16_t phy_status; 4762 u16 phy_status;
4763 uint16_t phy_ctrl; 4763 u16 phy_ctrl;
4764 4764
4765 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg || 4765 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
4766 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 4766 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
@@ -4839,8 +4839,8 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4839 struct e1000_adapter *adapter = netdev_priv(netdev); 4839 struct e1000_adapter *adapter = netdev_priv(netdev);
4840 struct mii_ioctl_data *data = if_mii(ifr); 4840 struct mii_ioctl_data *data = if_mii(ifr);
4841 int retval; 4841 int retval;
4842 uint16_t mii_reg; 4842 u16 mii_reg;
4843 uint16_t spddplx; 4843 u16 spddplx;
4844 unsigned long flags; 4844 unsigned long flags;
4845 4845
4846 if (adapter->hw.media_type != e1000_media_type_copper) 4846 if (adapter->hw.media_type != e1000_media_type_copper)
@@ -4959,11 +4959,11 @@ e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc)
4959 pcix_set_mmrbc(adapter->pdev, mmrbc); 4959 pcix_set_mmrbc(adapter->pdev, mmrbc);
4960} 4960}
4961 4961
4962int32_t 4962s32
4963e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4963e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
4964{ 4964{
4965 struct e1000_adapter *adapter = hw->back; 4965 struct e1000_adapter *adapter = hw->back;
4966 uint16_t cap_offset; 4966 u16 cap_offset;
4967 4967
4968 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 4968 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4969 if (!cap_offset) 4969 if (!cap_offset)
@@ -4975,7 +4975,7 @@ e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4975} 4975}
4976 4976
4977void 4977void
4978e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 4978e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value)
4979{ 4979{
4980 outl(value, port); 4980 outl(value, port);
4981} 4981}
@@ -4984,7 +4984,7 @@ static void
4984e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) 4984e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4985{ 4985{
4986 struct e1000_adapter *adapter = netdev_priv(netdev); 4986 struct e1000_adapter *adapter = netdev_priv(netdev);
4987 uint32_t ctrl, rctl; 4987 u32 ctrl, rctl;
4988 4988
4989 if (!test_bit(__E1000_DOWN, &adapter->flags)) 4989 if (!test_bit(__E1000_DOWN, &adapter->flags))
4990 e1000_irq_disable(adapter); 4990 e1000_irq_disable(adapter);
@@ -5016,7 +5016,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
5016 rctl &= ~E1000_RCTL_VFE; 5016 rctl &= ~E1000_RCTL_VFE;
5017 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 5017 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5018 if (adapter->mng_vlan_id != 5018 if (adapter->mng_vlan_id !=
5019 (uint16_t)E1000_MNG_VLAN_NONE) { 5019 (u16)E1000_MNG_VLAN_NONE) {
5020 e1000_vlan_rx_kill_vid(netdev, 5020 e1000_vlan_rx_kill_vid(netdev,
5021 adapter->mng_vlan_id); 5021 adapter->mng_vlan_id);
5022 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 5022 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
@@ -5029,10 +5029,10 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
5029} 5029}
5030 5030
5031static void 5031static void
5032e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid) 5032e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5033{ 5033{
5034 struct e1000_adapter *adapter = netdev_priv(netdev); 5034 struct e1000_adapter *adapter = netdev_priv(netdev);
5035 uint32_t vfta, index; 5035 u32 vfta, index;
5036 5036
5037 if ((adapter->hw.mng_cookie.status & 5037 if ((adapter->hw.mng_cookie.status &
5038 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && 5038 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
@@ -5046,10 +5046,10 @@ e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
5046} 5046}
5047 5047
5048static void 5048static void
5049e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid) 5049e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5050{ 5050{
5051 struct e1000_adapter *adapter = netdev_priv(netdev); 5051 struct e1000_adapter *adapter = netdev_priv(netdev);
5052 uint32_t vfta, index; 5052 u32 vfta, index;
5053 5053
5054 if (!test_bit(__E1000_DOWN, &adapter->flags)) 5054 if (!test_bit(__E1000_DOWN, &adapter->flags))
5055 e1000_irq_disable(adapter); 5055 e1000_irq_disable(adapter);
@@ -5078,7 +5078,7 @@ e1000_restore_vlan(struct e1000_adapter *adapter)
5078 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp); 5078 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5079 5079
5080 if (adapter->vlgrp) { 5080 if (adapter->vlgrp) {
5081 uint16_t vid; 5081 u16 vid;
5082 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { 5082 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5083 if (!vlan_group_get_device(adapter->vlgrp, vid)) 5083 if (!vlan_group_get_device(adapter->vlgrp, vid))
5084 continue; 5084 continue;
@@ -5088,7 +5088,7 @@ e1000_restore_vlan(struct e1000_adapter *adapter)
5088} 5088}
5089 5089
5090int 5090int
5091e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx) 5091e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
5092{ 5092{
5093 adapter->hw.autoneg = 0; 5093 adapter->hw.autoneg = 0;
5094 5094
@@ -5129,8 +5129,8 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
5129{ 5129{
5130 struct net_device *netdev = pci_get_drvdata(pdev); 5130 struct net_device *netdev = pci_get_drvdata(pdev);
5131 struct e1000_adapter *adapter = netdev_priv(netdev); 5131 struct e1000_adapter *adapter = netdev_priv(netdev);
5132 uint32_t ctrl, ctrl_ext, rctl, status; 5132 u32 ctrl, ctrl_ext, rctl, status;
5133 uint32_t wufc = adapter->wol; 5133 u32 wufc = adapter->wol;
5134#ifdef CONFIG_PM 5134#ifdef CONFIG_PM
5135 int retval = 0; 5135 int retval = 0;
5136#endif 5136#endif
@@ -5227,7 +5227,7 @@ e1000_resume(struct pci_dev *pdev)
5227{ 5227{
5228 struct net_device *netdev = pci_get_drvdata(pdev); 5228 struct net_device *netdev = pci_get_drvdata(pdev);
5229 struct e1000_adapter *adapter = netdev_priv(netdev); 5229 struct e1000_adapter *adapter = netdev_priv(netdev);
5230 uint32_t err; 5230 u32 err;
5231 5231
5232 pci_set_power_state(pdev, PCI_D0); 5232 pci_set_power_state(pdev, PCI_D0);
5233 pci_restore_state(pdev); 5233 pci_restore_state(pdev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 00:07:21 -0500