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authorMichal Miroslaw <mirq-linux@rere.qmqm.pl>2009-05-12 16:49:26 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-06-16 17:29:08 -0400
commit26c56dc0c4fbdf3af12ebc48278f09ef65ddb4dd (patch)
treee1312ea1b9a0f44f8c6208930e410cfd308a8f96 /drivers
parent4096ed0fc7c6ed83da44ab27ab7d1c7cd6e8e175 (diff)
PCI quirk: unhide 'Overflow' device on i828{6,7}5P/PE chipsets
Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets. The same happens for i82865P/PE. Add a quirk to enable this device. This allows i82875 EDAC driver to bind to chipset's dev #6 and not dev #0 as the latter is used by AGP driver. On my laptop (i82865P based) ACPI code is disabling this device again in \_SB.PCI0._CRS method (called at least at PNP init time). This can be easily worked around by patching DSDT. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Michal Miroslaw <mirq-linux@rere.qmqm.pl> Acked-by: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/quirks.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index a778c84d04a9..15a8ab7ea911 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2017,6 +2017,28 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2017 PCI_DEVICE_ID_NX2_5709S, 2017 PCI_DEVICE_ID_NX2_5709S,
2018 quirk_brcm_570x_limit_vpd); 2018 quirk_brcm_570x_limit_vpd);
2019 2019
2020/* Originally in EDAC sources for i82875P:
2021 * Intel tells BIOS developers to hide device 6 which
2022 * configures the overflow device access containing
2023 * the DRBs - this is where we expose device 6.
2024 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2025 */
2026static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2027{
2028 u8 reg;
2029
2030 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2031 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2032 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2033 }
2034}
2035
2036DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2037 quirk_unhide_mch_dev6);
2038DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2039 quirk_unhide_mch_dev6);
2040
2041
2020#ifdef CONFIG_PCI_MSI 2042#ifdef CONFIG_PCI_MSI
2021/* Some chipsets do not support MSI. We cannot easily rely on setting 2043/* Some chipsets do not support MSI. We cannot easily rely on setting
2022 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2044 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually